diff --git a/.cproject b/.cproject new file mode 100644 index 0000000..58bf25c --- /dev/null +++ b/.cproject @@ -0,0 +1,393 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/.mxproject b/.mxproject new file mode 100644 index 0000000..7116191 --- /dev/null +++ b/.mxproject @@ -0,0 +1,35 @@ +[PreviousLibFiles] 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+ +[PreviousUsedCubeIDEFiles] +SourceFiles=Core\Src\main.c;USB_HOST\App\usb_host.c;USB_HOST\Target\usbh_conf.c;USB_HOST\Target\usbh_platform.c;Core\Src\stm32f4xx_it.c;Core\Src\stm32f4xx_hal_msp.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_core.c;Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ctlreq.c;Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ioreq.c;Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_pipes.c;Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Src/usbh_cdc.c;Core\Src/system_stm32f4xx.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_core.c;Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ctlreq.c;Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ioreq.c;Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_pipes.c;Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Src/usbh_cdc.c;Core\Src/system_stm32f4xx.c;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;;Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_core.c;Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ctlreq.c;Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ioreq.c;Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_pipes.c;Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Src/usbh_cdc.c; +HeaderPath=Drivers\STM32F4xx_HAL_Driver\Inc;Drivers\STM32F4xx_HAL_Driver\Inc\Legacy;Middlewares\ST\STM32_USB_Host_Library\Core\Inc;Middlewares\ST\STM32_USB_Host_Library\Class\CDC\Inc;Drivers\CMSIS\Device\ST\STM32F4xx\Include;Drivers\CMSIS\Include;USB_HOST\App;USB_HOST\Target;Core\Inc; +CDefines=USE_HAL_DRIVER;STM32F401xC;USE_HAL_DRIVER;USE_HAL_DRIVER; + +[PreviousGenFiles] +AdvancedFolderStructure=true +HeaderFileListSize=6 +HeaderFiles#0=D:/Users/Think/Programmation/STM32CUBEIDE/Test/USB_HOST/App/usb_host.h +HeaderFiles#1=D:/Users/Think/Programmation/STM32CUBEIDE/Test/USB_HOST/Target/usbh_conf.h +HeaderFiles#2=D:/Users/Think/Programmation/STM32CUBEIDE/Test/USB_HOST/Target/usbh_platform.h +HeaderFiles#3=D:/Users/Think/Programmation/STM32CUBEIDE/Test/Core/Inc/stm32f4xx_it.h +HeaderFiles#4=D:/Users/Think/Programmation/STM32CUBEIDE/Test/Core/Inc/stm32f4xx_hal_conf.h +HeaderFiles#5=D:/Users/Think/Programmation/STM32CUBEIDE/Test/Core/Inc/main.h +HeaderFolderListSize=3 +HeaderPath#0=D:/Users/Think/Programmation/STM32CUBEIDE/Test/USB_HOST/App +HeaderPath#1=D:/Users/Think/Programmation/STM32CUBEIDE/Test/USB_HOST/Target +HeaderPath#2=D:/Users/Think/Programmation/STM32CUBEIDE/Test/Core/Inc +HeaderFiles=; +SourceFileListSize=6 +SourceFiles#0=D:/Users/Think/Programmation/STM32CUBEIDE/Test/USB_HOST/App/usb_host.c +SourceFiles#1=D:/Users/Think/Programmation/STM32CUBEIDE/Test/USB_HOST/Target/usbh_conf.c +SourceFiles#2=D:/Users/Think/Programmation/STM32CUBEIDE/Test/USB_HOST/Target/usbh_platform.c +SourceFiles#3=D:/Users/Think/Programmation/STM32CUBEIDE/Test/Core/Src/stm32f4xx_it.c +SourceFiles#4=D:/Users/Think/Programmation/STM32CUBEIDE/Test/Core/Src/stm32f4xx_hal_msp.c +SourceFiles#5=D:/Users/Think/Programmation/STM32CUBEIDE/Test/Core/Src/main.c +SourceFolderListSize=3 +SourcePath#0=D:/Users/Think/Programmation/STM32CUBEIDE/Test/USB_HOST/App +SourcePath#1=D:/Users/Think/Programmation/STM32CUBEIDE/Test/USB_HOST/Target +SourcePath#2=D:/Users/Think/Programmation/STM32CUBEIDE/Test/Core/Src +SourceFiles=; + diff --git a/.project b/.project new file mode 100644 index 0000000..12a4132 --- /dev/null +++ b/.project @@ -0,0 +1,34 @@ + + + eCompass + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.st.stm32cube.ide.mcu.MCUProjectNature + com.st.stm32cube.ide.mcu.MCUCubeProjectNature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAev2ProjectNature + com.st.stm32cube.ide.mcu.MCUAdvancedStructureProjectNature + com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature + com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature + com.st.stm32cube.ide.mcu.MCURootProjectNature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/.settings/language.settings.xml b/.settings/language.settings.xml new file mode 100644 index 0000000..92c71d9 --- /dev/null +++ b/.settings/language.settings.xml @@ -0,0 +1,27 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/.settings/stm32cubeide.project.prefs b/.settings/stm32cubeide.project.prefs new file mode 100644 index 0000000..df27a66 --- /dev/null +++ b/.settings/stm32cubeide.project.prefs @@ -0,0 +1,3 @@ +8DF89ED150041C4CBC7CB9A9CAA90856=0200E7423990B2759ED933AA554D57BA +DC22A860405A8BF2F2C095E5B6529F12=0200E7423990B2759ED933AA554D57BA +eclipse.preferences.version=1 diff --git a/Core/Inc/app.h b/Core/Inc/app.h new file mode 100644 index 0000000..8247217 --- /dev/null +++ b/Core/Inc/app.h @@ -0,0 +1,15 @@ +/* + * app.h + * + * Created on: Apr 3, 2021 + * Author: Think + */ + +#ifndef INC_APP_H_ +#define INC_APP_H_ + +void setup(void); +void loop(void); + + +#endif /* INC_APP_H_ */ diff --git a/Core/Inc/main.h b/Core/Inc/main.h new file mode 100644 index 0000000..8020901 --- /dev/null +++ b/Core/Inc/main.h @@ -0,0 +1,135 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +#define CS_I2C_SPI_Pin GPIO_PIN_3 +#define CS_I2C_SPI_GPIO_Port GPIOE +#define PC14_OSC32_IN_Pin GPIO_PIN_14 +#define PC14_OSC32_IN_GPIO_Port GPIOC +#define PC15_OSC32_OUT_Pin GPIO_PIN_15 +#define PC15_OSC32_OUT_GPIO_Port GPIOC +#define PH0_OSC_IN_Pin GPIO_PIN_0 +#define PH0_OSC_IN_GPIO_Port GPIOH +#define PH1_OSC_OUT_Pin GPIO_PIN_1 +#define PH1_OSC_OUT_GPIO_Port GPIOH +#define OTG_FS_PowerSwitchOn_Pin GPIO_PIN_0 +#define OTG_FS_PowerSwitchOn_GPIO_Port GPIOC +#define PDM_OUT_Pin GPIO_PIN_3 +#define PDM_OUT_GPIO_Port GPIOC +#define B1_Pin GPIO_PIN_0 +#define B1_GPIO_Port GPIOA +#define I2S3_WS_Pin GPIO_PIN_4 +#define I2S3_WS_GPIO_Port GPIOA +#define SPI1_SCK_Pin GPIO_PIN_5 +#define SPI1_SCK_GPIO_Port GPIOA +#define SPI1_MISO_Pin GPIO_PIN_6 +#define SPI1_MISO_GPIO_Port GPIOA +#define SPI1_MISOA7_Pin GPIO_PIN_7 +#define SPI1_MISOA7_GPIO_Port GPIOA +#define CLK_IN_Pin GPIO_PIN_10 +#define CLK_IN_GPIO_Port GPIOB +#define LD4_Pin GPIO_PIN_12 +#define LD4_GPIO_Port GPIOD +#define LD3_Pin GPIO_PIN_13 +#define LD3_GPIO_Port GPIOD +#define LD5_Pin GPIO_PIN_14 +#define LD5_GPIO_Port GPIOD +#define LD6_Pin GPIO_PIN_15 +#define LD6_GPIO_Port GPIOD +#define I2S3_MCK_Pin GPIO_PIN_7 +#define I2S3_MCK_GPIO_Port GPIOC +#define VBUS_FS_Pin GPIO_PIN_9 +#define VBUS_FS_GPIO_Port GPIOA +#define OTG_FS_ID_Pin GPIO_PIN_10 +#define OTG_FS_ID_GPIO_Port GPIOA +#define OTG_FS_DM_Pin GPIO_PIN_11 +#define OTG_FS_DM_GPIO_Port GPIOA +#define OTG_FS_DP_Pin GPIO_PIN_12 +#define OTG_FS_DP_GPIO_Port GPIOA +#define SWDIO_Pin GPIO_PIN_13 +#define SWDIO_GPIO_Port GPIOA +#define SWCLK_Pin GPIO_PIN_14 +#define SWCLK_GPIO_Port GPIOA +#define I2S3_SCK_Pin GPIO_PIN_10 +#define I2S3_SCK_GPIO_Port GPIOC +#define I2S3_SD_Pin GPIO_PIN_12 +#define I2S3_SD_GPIO_Port GPIOC +#define Audio_RST_Pin GPIO_PIN_4 +#define Audio_RST_GPIO_Port GPIOD +#define OTG_FS_OverCurrent_Pin GPIO_PIN_5 +#define OTG_FS_OverCurrent_GPIO_Port GPIOD +#define SWO_Pin GPIO_PIN_3 +#define SWO_GPIO_Port GPIOB +#define Audio_SCL_Pin GPIO_PIN_6 +#define Audio_SCL_GPIO_Port GPIOB +#define Audio_SDA_Pin GPIO_PIN_9 +#define Audio_SDA_GPIO_Port GPIOB +#define MEMS_INT2_Pin GPIO_PIN_1 +#define MEMS_INT2_GPIO_Port GPIOE +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Core/Inc/stm32f4xx_hal_conf.h b/Core/Inc/stm32f4xx_hal_conf.h new file mode 100644 index 0000000..f6735b1 --- /dev/null +++ b/Core/Inc/stm32f4xx_hal_conf.h @@ -0,0 +1,486 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_conf_template.h + * @author MCD Application Team + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32f4xx_hal_conf.h. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_CONF_H +#define __STM32F4xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED + + /* #define HAL_ADC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_CAN_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_DAC_MODULE_ENABLED */ +/* #define HAL_DCMI_MODULE_ENABLED */ +/* #define HAL_DMA2D_MODULE_ENABLED */ +/* #define HAL_ETH_MODULE_ENABLED */ +/* #define HAL_NAND_MODULE_ENABLED */ +/* #define HAL_NOR_MODULE_ENABLED */ +/* #define HAL_PCCARD_MODULE_ENABLED */ +/* #define HAL_SRAM_MODULE_ENABLED */ +/* #define HAL_SDRAM_MODULE_ENABLED */ +/* #define HAL_HASH_MODULE_ENABLED */ +#define HAL_I2C_MODULE_ENABLED +#define HAL_I2S_MODULE_ENABLED +/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_LTDC_MODULE_ENABLED */ +/* #define HAL_RNG_MODULE_ENABLED */ +/* #define HAL_RTC_MODULE_ENABLED */ +/* #define HAL_SAI_MODULE_ENABLED */ +/* #define HAL_SD_MODULE_ENABLED */ +/* #define HAL_MMC_MODULE_ENABLED */ +#define HAL_SPI_MODULE_ENABLED +/* #define HAL_TIM_MODULE_ENABLED */ +#define HAL_UART_MODULE_ENABLED +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_SMBUS_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ +/* #define HAL_PCD_MODULE_ENABLED */ +#define HAL_HCD_MODULE_ENABLED +/* #define HAL_DSI_MODULE_ENABLED */ +/* #define HAL_QSPI_MODULE_ENABLED */ +/* #define HAL_QSPI_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_FMPI2C_MODULE_ENABLED */ +/* #define HAL_SPDIFRX_MODULE_ENABLED */ +/* #define HAL_DFSDM_MODULE_ENABLED */ +/* #define HAL_LPTIM_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## HSE/HSI Values adaptation ##################### */ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature.*/ +/** + * @brief External Low Speed oscillator (LSE) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for I2S peripheral + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) + #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the External audio frequency in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 1U +#define INSTRUCTION_CACHE_ENABLE 1U +#define DATA_CACHE_ENABLE 1U + +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ +#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ +#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ +#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ +#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ +#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ +#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ +#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ +#define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */ +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ +#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ +#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ +#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */ +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ +#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ +#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ +#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ +#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ +#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ +#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## Ethernet peripheral configuration ##################### */ + +/* Section 1 : Ethernet peripheral configuration */ + +/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ +#define MAC_ADDR0 2U +#define MAC_ADDR1 0U +#define MAC_ADDR2 0U +#define MAC_ADDR3 0U +#define MAC_ADDR4 0U +#define MAC_ADDR5 0U + +/* Definition of the Ethernet driver buffers size and count */ +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ +#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ + +/* Section 2: PHY configuration section */ + +/* DP83848_PHY_ADDRESS Address*/ +#define DP83848_PHY_ADDRESS 0x01U +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +#define PHY_RESET_DELAY ((uint32_t)0x000000FFU) +/* PHY Configuration delay */ +#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU) + +#define PHY_READ_TO ((uint32_t)0x0000FFFFU) +#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU) + +/* Section 3: Common PHY Registers */ + +#define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */ + +#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ + +/* Section 4: Extended PHY Registers */ +#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ + +#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver +* Activated: CRC code is present inside driver +* Deactivated: CRC code cleaned from driver +*/ + +#define USE_SPI_CRC 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32f4xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32f4xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32f4xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32f4xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32f4xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32f4xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32f4xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #include "stm32f4xx_hal_can_legacy.h" +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32f4xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32f4xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32f4xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32f4xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32f4xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32f4xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32f4xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32f4xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32f4xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32f4xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_PCCARD_MODULE_ENABLED + #include "stm32f4xx_hal_pccard.h" +#endif /* HAL_PCCARD_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32f4xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32f4xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32f4xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32f4xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32f4xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32f4xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32f4xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32f4xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32f4xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32f4xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32f4xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32f4xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32f4xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32f4xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32f4xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32f4xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32f4xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32f4xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32f4xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32f4xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32f4xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_DSI_MODULE_ENABLED + #include "stm32f4xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32f4xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32f4xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_FMPI2C_MODULE_ENABLED + #include "stm32f4xx_hal_fmpi2c.h" +#endif /* HAL_FMPI2C_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED + #include "stm32f4xx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_DFSDM_MODULE_ENABLED + #include "stm32f4xx_hal_dfsdm.h" +#endif /* HAL_DFSDM_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "stm32f4xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32f4xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Core/Inc/stm32f4xx_it.h b/Core/Inc/stm32f4xx_it.h new file mode 100644 index 0000000..86b00e6 --- /dev/null +++ b/Core/Inc/stm32f4xx_it.h @@ -0,0 +1,70 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f4xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_IT_H +#define __STM32F4xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void OTG_FS_IRQHandler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Core/Src/app.c b/Core/Src/app.c new file mode 100644 index 0000000..d3f3ed1 --- /dev/null +++ b/Core/Src/app.c @@ -0,0 +1,78 @@ +/* + * app.c + * + * Created on: Apr 3, 2021 + * Author: Think + */ + +#include +#include +#include +#include +#include "app.h" +#include "main.h" +#include "LSM303DLHC.h" + +#include "COMPASS_LEDS.h" + +#define BLINK_RATE_MS 500 +#define PRINT_RATE_MS 100 + +uint32_t ts_blink = 0, ts_print = 0; +int16_t x = 0, y = 0, z = 0; +uint8_t id[3] = {0}; + +//eCompasse declaration +extern I2C_HandleTypeDef hi2c1; +LSM303 eComp; +COMPASS_LEDS compLeds; + +void setup(void) +{ + COMPASS_LEDS_Init(&compLeds); + + if(!LSM303_Init(&eComp, &hi2c1)) + printf("Failed to init eCompass\r\n"); + + if(!LSM303_EnableTemperatureSensor(&eComp, true)) + printf("Failed to enable temp sensor\r\n"); + + if(!LSM303_ApplyConfig(&eComp)) + printf("Failed to apply config\r\n"); + + if(!LSM303_GetDeviceID(&eComp, id)) + printf("Failed to retrieve id\r\n"); + else + printf("LSM303 ID : %#X,%#X,%#X\r\n", id[0], id[1], id[2]); +} + +void loop(void) +{ + if(HAL_GetTick() - ts_print > PRINT_RATE_MS) + { + //Lets read the temperature : + float temperature = 0; + + if(!LSM303_GetTemperature(&eComp, &temperature, NULL)) + printf("Failed to get temperature\r\n"); + else + printf("Temp is : %.3f\r\n", temperature); + + if(!LSM303_GetMagneticFieldData(&eComp, &x, &y, &z)) + printf("Failed to get magnetic data\r\n"); + else + printf("x : %d, y : %d, z : %d\r\n", x, y, z); + + ts_print = HAL_GetTick(); + } + + if(x > 0 && x > abs(y) - 50) + COMPASS_LEDS_Light(&compLeds, NORTH); + if(x < 0 && abs(x) > abs(y) - 50) + COMPASS_LEDS_Light(&compLeds, SOUTH); + if(y > 0 && y > abs(x) - 50) + COMPASS_LEDS_Light(&compLeds, EAST); + if(y < 0 && abs(y) > abs(x) - 50) + COMPASS_LEDS_Light(&compLeds, WEST); +} + diff --git a/Core/Src/main.c b/Core/Src/main.c new file mode 100644 index 0000000..36270f3 --- /dev/null +++ b/Core/Src/main.c @@ -0,0 +1,469 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "usb_host.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +#include +#include "app.h" +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +I2C_HandleTypeDef hi2c1; + +I2S_HandleTypeDef hi2s2; +I2S_HandleTypeDef hi2s3; + +SPI_HandleTypeDef hspi1; + +UART_HandleTypeDef huart2; + +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +static void MX_GPIO_Init(void); +static void MX_I2C1_Init(void); +static void MX_I2S2_Init(void); +static void MX_I2S3_Init(void); +static void MX_SPI1_Init(void); +static void MX_USART2_UART_Init(void); +void MX_USB_HOST_Process(void); + +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +int __io_putchar(int ch) +{ + HAL_UART_Transmit(&huart2, (uint8_t*)&ch, 1, HAL_MAX_DELAY); + return ch; +} +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + /* USER CODE BEGIN 1 */ + + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_I2C1_Init(); + MX_I2S2_Init(); + MX_I2S3_Init(); + MX_SPI1_Init(); + MX_USB_HOST_Init(); + MX_USART2_UART_Init(); + /* USER CODE BEGIN 2 */ + setup(); + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + /* USER CODE END WHILE */ + MX_USB_HOST_Process(); + + /* USER CODE BEGIN 3 */ + loop(); + } + /* USER CODE END 3 */ +} + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + + /** Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 8; + RCC_OscInitStruct.PLL.PLLN = 336; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; + RCC_OscInitStruct.PLL.PLLQ = 7; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) + { + Error_Handler(); + } + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2S; + PeriphClkInitStruct.PLLI2S.PLLI2SN = 192; + PeriphClkInitStruct.PLLI2S.PLLI2SR = 2; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } +} + +/** + * @brief I2C1 Initialization Function + * @param None + * @retval None + */ +static void MX_I2C1_Init(void) +{ + + /* USER CODE BEGIN I2C1_Init 0 */ + + /* USER CODE END I2C1_Init 0 */ + + /* USER CODE BEGIN I2C1_Init 1 */ + + /* USER CODE END I2C1_Init 1 */ + hi2c1.Instance = I2C1; + hi2c1.Init.ClockSpeed = 100000; + hi2c1.Init.DutyCycle = I2C_DUTYCYCLE_2; + hi2c1.Init.OwnAddress1 = 0; + hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; + hi2c1.Init.OwnAddress2 = 0; + hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; + hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; + if (HAL_I2C_Init(&hi2c1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN I2C1_Init 2 */ + + /* USER CODE END I2C1_Init 2 */ + +} + +/** + * @brief I2S2 Initialization Function + * @param None + * @retval None + */ +static void MX_I2S2_Init(void) +{ + + /* USER CODE BEGIN I2S2_Init 0 */ + + /* USER CODE END I2S2_Init 0 */ + + /* USER CODE BEGIN I2S2_Init 1 */ + + /* USER CODE END I2S2_Init 1 */ + hi2s2.Instance = SPI2; + hi2s2.Init.Mode = I2S_MODE_MASTER_TX; + hi2s2.Init.Standard = I2S_STANDARD_PHILIPS; + hi2s2.Init.DataFormat = I2S_DATAFORMAT_16B; + hi2s2.Init.MCLKOutput = I2S_MCLKOUTPUT_DISABLE; + hi2s2.Init.AudioFreq = I2S_AUDIOFREQ_8K; + hi2s2.Init.CPOL = I2S_CPOL_LOW; + hi2s2.Init.ClockSource = I2S_CLOCK_PLL; + hi2s2.Init.FullDuplexMode = I2S_FULLDUPLEXMODE_DISABLE; + if (HAL_I2S_Init(&hi2s2) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN I2S2_Init 2 */ + + /* USER CODE END I2S2_Init 2 */ + +} + +/** + * @brief I2S3 Initialization Function + * @param None + * @retval None + */ +static void MX_I2S3_Init(void) +{ + + /* USER CODE BEGIN I2S3_Init 0 */ + + /* USER CODE END I2S3_Init 0 */ + + /* USER CODE BEGIN I2S3_Init 1 */ + + /* USER CODE END I2S3_Init 1 */ + hi2s3.Instance = SPI3; + hi2s3.Init.Mode = I2S_MODE_MASTER_TX; + hi2s3.Init.Standard = I2S_STANDARD_PHILIPS; + hi2s3.Init.DataFormat = I2S_DATAFORMAT_16B; + hi2s3.Init.MCLKOutput = I2S_MCLKOUTPUT_ENABLE; + hi2s3.Init.AudioFreq = I2S_AUDIOFREQ_96K; + hi2s3.Init.CPOL = I2S_CPOL_LOW; + hi2s3.Init.ClockSource = I2S_CLOCK_PLL; + hi2s3.Init.FullDuplexMode = I2S_FULLDUPLEXMODE_DISABLE; + if (HAL_I2S_Init(&hi2s3) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN I2S3_Init 2 */ + + /* USER CODE END I2S3_Init 2 */ + +} + +/** + * @brief SPI1 Initialization Function + * @param None + * @retval None + */ +static void MX_SPI1_Init(void) +{ + + /* USER CODE BEGIN SPI1_Init 0 */ + + /* USER CODE END SPI1_Init 0 */ + + /* USER CODE BEGIN SPI1_Init 1 */ + + /* USER CODE END SPI1_Init 1 */ + /* SPI1 parameter configuration*/ + hspi1.Instance = SPI1; + hspi1.Init.Mode = SPI_MODE_MASTER; + hspi1.Init.Direction = SPI_DIRECTION_2LINES; + hspi1.Init.DataSize = SPI_DATASIZE_8BIT; + hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; + hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; + hspi1.Init.NSS = SPI_NSS_SOFT; + hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; + hspi1.Init.TIMode = SPI_TIMODE_DISABLE; + hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + hspi1.Init.CRCPolynomial = 10; + if (HAL_SPI_Init(&hspi1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SPI1_Init 2 */ + + /* USER CODE END SPI1_Init 2 */ + +} + +/** + * @brief USART2 Initialization Function + * @param None + * @retval None + */ +static void MX_USART2_UART_Init(void) +{ + + /* USER CODE BEGIN USART2_Init 0 */ + + /* USER CODE END USART2_Init 0 */ + + /* USER CODE BEGIN USART2_Init 1 */ + + /* USER CODE END USART2_Init 1 */ + huart2.Instance = USART2; + huart2.Init.BaudRate = 115200; + huart2.Init.WordLength = UART_WORDLENGTH_8B; + huart2.Init.StopBits = UART_STOPBITS_1; + huart2.Init.Parity = UART_PARITY_NONE; + huart2.Init.Mode = UART_MODE_TX_RX; + huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart2.Init.OverSampling = UART_OVERSAMPLING_16; + if (HAL_UART_Init(&huart2) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART2_Init 2 */ + + /* USER CODE END USART2_Init 2 */ + +} + +/** + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOE_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(CS_I2C_SPI_GPIO_Port, CS_I2C_SPI_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(OTG_FS_PowerSwitchOn_GPIO_Port, OTG_FS_PowerSwitchOn_Pin, GPIO_PIN_SET); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOD, LD4_Pin|LD3_Pin|LD5_Pin|LD6_Pin + |Audio_RST_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pin : PE2 */ + GPIO_InitStruct.Pin = GPIO_PIN_2; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + + /*Configure GPIO pin : CS_I2C_SPI_Pin */ + GPIO_InitStruct.Pin = CS_I2C_SPI_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(CS_I2C_SPI_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pins : PE4 PE5 MEMS_INT2_Pin */ + GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|MEMS_INT2_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_EVT_RISING; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + + /*Configure GPIO pin : OTG_FS_PowerSwitchOn_Pin */ + GPIO_InitStruct.Pin = OTG_FS_PowerSwitchOn_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(OTG_FS_PowerSwitchOn_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pin : B1_Pin */ + GPIO_InitStruct.Pin = B1_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_EVT_RISING; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pins : LD4_Pin LD3_Pin LD5_Pin LD6_Pin + Audio_RST_Pin */ + GPIO_InitStruct.Pin = LD4_Pin|LD3_Pin|LD5_Pin|LD6_Pin + |Audio_RST_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /*Configure GPIO pin : OTG_FS_OverCurrent_Pin */ + GPIO_InitStruct.Pin = OTG_FS_OverCurrent_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(OTG_FS_OverCurrent_GPIO_Port, &GPIO_InitStruct); + +} + +/* USER CODE BEGIN 4 */ + +/* USER CODE END 4 */ + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + { + } + /* USER CODE END Error_Handler_Debug */ +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Core/Src/stm32f4xx_hal_msp.c b/Core/Src/stm32f4xx_hal_msp.c new file mode 100644 index 0000000..2b74e2a --- /dev/null +++ b/Core/Src/stm32f4xx_hal_msp.c @@ -0,0 +1,418 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f4xx_hal_msp.c + * @brief This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_SYSCFG_CLK_ENABLE(); + __HAL_RCC_PWR_CLK_ENABLE(); + + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_0); + + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/** +* @brief I2C MSP Initialization +* This function configures the hardware resources used in this example +* @param hi2c: I2C handle pointer +* @retval None +*/ +void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hi2c->Instance==I2C1) + { + /* USER CODE BEGIN I2C1_MspInit 0 */ + + /* USER CODE END I2C1_MspInit 0 */ + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**I2C1 GPIO Configuration + PB6 ------> I2C1_SCL + PB9 ------> I2C1_SDA + */ + GPIO_InitStruct.Pin = Audio_SCL_Pin|Audio_SDA_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* Peripheral clock enable */ + __HAL_RCC_I2C1_CLK_ENABLE(); + /* USER CODE BEGIN I2C1_MspInit 1 */ + + /* USER CODE END I2C1_MspInit 1 */ + } + +} + +/** +* @brief I2C MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hi2c: I2C handle pointer +* @retval None +*/ +void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c) +{ + if(hi2c->Instance==I2C1) + { + /* USER CODE BEGIN I2C1_MspDeInit 0 */ + + /* USER CODE END I2C1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_I2C1_CLK_DISABLE(); + + /**I2C1 GPIO Configuration + PB6 ------> I2C1_SCL + PB9 ------> I2C1_SDA + */ + HAL_GPIO_DeInit(Audio_SCL_GPIO_Port, Audio_SCL_Pin); + + HAL_GPIO_DeInit(Audio_SDA_GPIO_Port, Audio_SDA_Pin); + + /* USER CODE BEGIN I2C1_MspDeInit 1 */ + + /* USER CODE END I2C1_MspDeInit 1 */ + } + +} + +/** +* @brief I2S MSP Initialization +* This function configures the hardware resources used in this example +* @param hi2s: I2S handle pointer +* @retval None +*/ +void HAL_I2S_MspInit(I2S_HandleTypeDef* hi2s) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hi2s->Instance==SPI2) + { + /* USER CODE BEGIN SPI2_MspInit 0 */ + + /* USER CODE END SPI2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI2_CLK_ENABLE(); + + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**I2S2 GPIO Configuration + PC3 ------> I2S2_SD + PB10 ------> I2S2_CK + PB12 ------> I2S2_WS + */ + GPIO_InitStruct.Pin = PDM_OUT_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; + HAL_GPIO_Init(PDM_OUT_GPIO_Port, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = CLK_IN_Pin|GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* USER CODE BEGIN SPI2_MspInit 1 */ + + /* USER CODE END SPI2_MspInit 1 */ + } + else if(hi2s->Instance==SPI3) + { + /* USER CODE BEGIN SPI3_MspInit 0 */ + + /* USER CODE END SPI3_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI3_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + /**I2S3 GPIO Configuration + PA4 ------> I2S3_WS + PC7 ------> I2S3_MCK + PC10 ------> I2S3_CK + PC12 ------> I2S3_SD + */ + GPIO_InitStruct.Pin = I2S3_WS_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF6_SPI3; + HAL_GPIO_Init(I2S3_WS_GPIO_Port, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = I2S3_MCK_Pin|I2S3_SCK_Pin|I2S3_SD_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF6_SPI3; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /* USER CODE BEGIN SPI3_MspInit 1 */ + + /* USER CODE END SPI3_MspInit 1 */ + } + +} + +/** +* @brief I2S MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hi2s: I2S handle pointer +* @retval None +*/ +void HAL_I2S_MspDeInit(I2S_HandleTypeDef* hi2s) +{ + if(hi2s->Instance==SPI2) + { + /* USER CODE BEGIN SPI2_MspDeInit 0 */ + + /* USER CODE END SPI2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SPI2_CLK_DISABLE(); + + /**I2S2 GPIO Configuration + PC3 ------> I2S2_SD + PB10 ------> I2S2_CK + PB12 ------> I2S2_WS + */ + HAL_GPIO_DeInit(PDM_OUT_GPIO_Port, PDM_OUT_Pin); + + HAL_GPIO_DeInit(GPIOB, CLK_IN_Pin|GPIO_PIN_12); + + /* USER CODE BEGIN SPI2_MspDeInit 1 */ + + /* USER CODE END SPI2_MspDeInit 1 */ + } + else if(hi2s->Instance==SPI3) + { + /* USER CODE BEGIN SPI3_MspDeInit 0 */ + + /* USER CODE END SPI3_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SPI3_CLK_DISABLE(); + + /**I2S3 GPIO Configuration + PA4 ------> I2S3_WS + PC7 ------> I2S3_MCK + PC10 ------> I2S3_CK + PC12 ------> I2S3_SD + */ + HAL_GPIO_DeInit(I2S3_WS_GPIO_Port, I2S3_WS_Pin); + + HAL_GPIO_DeInit(GPIOC, I2S3_MCK_Pin|I2S3_SCK_Pin|I2S3_SD_Pin); + + /* USER CODE BEGIN SPI3_MspDeInit 1 */ + + /* USER CODE END SPI3_MspDeInit 1 */ + } + +} + +/** +* @brief SPI MSP Initialization +* This function configures the hardware resources used in this example +* @param hspi: SPI handle pointer +* @retval None +*/ +void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hspi->Instance==SPI1) + { + /* USER CODE BEGIN SPI1_MspInit 0 */ + + /* USER CODE END SPI1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI1_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**SPI1 GPIO Configuration + PA5 ------> SPI1_SCK + PA6 ------> SPI1_MISO + PA7 ------> SPI1_MOSI + */ + GPIO_InitStruct.Pin = SPI1_SCK_Pin|SPI1_MISO_Pin|SPI1_MISOA7_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN SPI1_MspInit 1 */ + + /* USER CODE END SPI1_MspInit 1 */ + } + +} + +/** +* @brief SPI MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hspi: SPI handle pointer +* @retval None +*/ +void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) +{ + if(hspi->Instance==SPI1) + { + /* USER CODE BEGIN SPI1_MspDeInit 0 */ + + /* USER CODE END SPI1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SPI1_CLK_DISABLE(); + + /**SPI1 GPIO Configuration + PA5 ------> SPI1_SCK + PA6 ------> SPI1_MISO + PA7 ------> SPI1_MOSI + */ + HAL_GPIO_DeInit(GPIOA, SPI1_SCK_Pin|SPI1_MISO_Pin|SPI1_MISOA7_Pin); + + /* USER CODE BEGIN SPI1_MspDeInit 1 */ + + /* USER CODE END SPI1_MspDeInit 1 */ + } + +} + +/** +* @brief UART MSP Initialization +* This function configures the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspInit(UART_HandleTypeDef* huart) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(huart->Instance==USART2) + { + /* USER CODE BEGIN USART2_MspInit 0 */ + + /* USER CODE END USART2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_USART2_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**USART2 GPIO Configuration + PA2 ------> USART2_TX + PA3 ------> USART2_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF7_USART2; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN USART2_MspInit 1 */ + + /* USER CODE END USART2_MspInit 1 */ + } + +} + +/** +* @brief UART MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) +{ + if(huart->Instance==USART2) + { + /* USER CODE BEGIN USART2_MspDeInit 0 */ + + /* USER CODE END USART2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART2_CLK_DISABLE(); + + /**USART2 GPIO Configuration + PA2 ------> USART2_TX + PA3 ------> USART2_RX + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3); + + /* USER CODE BEGIN USART2_MspDeInit 1 */ + + /* USER CODE END USART2_MspDeInit 1 */ + } + +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Core/Src/stm32f4xx_it.c b/Core/Src/stm32f4xx_it.c new file mode 100644 index 0000000..a134e3d --- /dev/null +++ b/Core/Src/stm32f4xx_it.c @@ -0,0 +1,219 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f4xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32f4xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +extern HCD_HandleTypeDef hhcd_USB_OTG_FS; +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex-M4 Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + { + } + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } +} + +/** + * @brief This function handles Pre-fetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn 0 */ + + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ + + /* USER CODE END SVCall_IRQn 1 */ +} + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn 0 */ + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32F4xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32f4xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles USB On The Go FS global interrupt. + */ +void OTG_FS_IRQHandler(void) +{ + /* USER CODE BEGIN OTG_FS_IRQn 0 */ + + /* USER CODE END OTG_FS_IRQn 0 */ + HAL_HCD_IRQHandler(&hhcd_USB_OTG_FS); + /* USER CODE BEGIN OTG_FS_IRQn 1 */ + + /* USER CODE END OTG_FS_IRQn 1 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Core/Src/syscalls.c b/Core/Src/syscalls.c new file mode 100644 index 0000000..4ec9584 --- /dev/null +++ b/Core/Src/syscalls.c @@ -0,0 +1,159 @@ +/** + ****************************************************************************** + * @file syscalls.c + * @author Auto-generated by STM32CubeIDE + * @brief STM32CubeIDE Minimal System calls file + * + * For more information about which c-functions + * need which of these lowlevel functions + * please consult the Newlib libc-manual + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes */ +#include +#include +#include +#include +#include +#include +#include +#include + + +/* Variables */ +//#undef errno +extern int errno; +extern int __io_putchar(int ch) __attribute__((weak)); +extern int __io_getchar(void) __attribute__((weak)); + +register char * stack_ptr asm("sp"); + +char *__env[1] = { 0 }; +char **environ = __env; + + +/* Functions */ +void initialise_monitor_handles() +{ +} + +int _getpid(void) +{ + return 1; +} + +int _kill(int pid, int sig) +{ + errno = EINVAL; + return -1; +} + +void _exit (int status) +{ + _kill(status, -1); + while (1) {} /* Make sure we hang here */ +} + +__attribute__((weak)) int _read(int file, char *ptr, int len) +{ + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + *ptr++ = __io_getchar(); + } + +return len; +} + +__attribute__((weak)) int _write(int file, char *ptr, int len) +{ + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + __io_putchar(*ptr++); + } + return len; +} + +int _close(int file) +{ + return -1; +} + + +int _fstat(int file, struct stat *st) +{ + st->st_mode = S_IFCHR; + return 0; +} + +int _isatty(int file) +{ + return 1; +} + +int _lseek(int file, int ptr, int dir) +{ + return 0; +} + +int _open(char *path, int flags, ...) +{ + /* Pretend like we always fail */ + return -1; +} + +int _wait(int *status) +{ + errno = ECHILD; + return -1; +} + +int _unlink(char *name) +{ + errno = ENOENT; + return -1; +} + +int _times(struct tms *buf) +{ + return -1; +} + +int _stat(char *file, struct stat *st) +{ + st->st_mode = S_IFCHR; + return 0; +} + +int _link(char *old, char *new) +{ + errno = EMLINK; + return -1; +} + +int _fork(void) +{ + errno = EAGAIN; + return -1; +} + +int _execve(char *name, char **argv, char **env) +{ + errno = ENOMEM; + return -1; +} diff --git a/Core/Src/sysmem.c b/Core/Src/sysmem.c new file mode 100644 index 0000000..d7cc52c --- /dev/null +++ b/Core/Src/sysmem.c @@ -0,0 +1,80 @@ +/** + ****************************************************************************** + * @file sysmem.c + * @author Generated by STM32CubeIDE + * @brief STM32CubeIDE System Memory calls file + * + * For more information about which C functions + * need which of these lowlevel functions + * please consult the newlib libc manual + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes */ +#include +#include + +/** + * Pointer to the current high watermark of the heap usage + */ +static uint8_t *__sbrk_heap_end = NULL; + +/** + * @brief _sbrk() allocates memory to the newlib heap and is used by malloc + * and others from the C library + * + * @verbatim + * ############################################################################ + * # .data # .bss # newlib heap # MSP stack # + * # # # # Reserved by _Min_Stack_Size # + * ############################################################################ + * ^-- RAM start ^-- _end _estack, RAM end --^ + * @endverbatim + * + * This implementation starts allocating at the '_end' linker symbol + * The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack + * The implementation considers '_estack' linker symbol to be RAM end + * NOTE: If the MSP stack, at any point during execution, grows larger than the + * reserved size, please increase the '_Min_Stack_Size'. + * + * @param incr Memory size + * @return Pointer to allocated memory + */ +void *_sbrk(ptrdiff_t incr) +{ + extern uint8_t _end; /* Symbol defined in the linker script */ + extern uint8_t _estack; /* Symbol defined in the linker script */ + extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ + const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; + const uint8_t *max_heap = (uint8_t *)stack_limit; + uint8_t *prev_heap_end; + + /* Initialize heap end at first call */ + if (NULL == __sbrk_heap_end) + { + __sbrk_heap_end = &_end; + } + + /* Protect heap from growing into the reserved MSP stack */ + if (__sbrk_heap_end + incr > max_heap) + { + errno = ENOMEM; + return (void *)-1; + } + + prev_heap_end = __sbrk_heap_end; + __sbrk_heap_end += incr; + + return (void *)prev_heap_end; +} diff --git a/Core/Src/system_stm32f4xx.c b/Core/Src/system_stm32f4xx.c new file mode 100644 index 0000000..bcb2b9f --- /dev/null +++ b/Core/Src/system_stm32f4xx.c @@ -0,0 +1,727 @@ +/** + ****************************************************************************** + * @file system_stm32f4xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f4xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx_system + * @{ + */ + +/** @addtogroup STM32F4xx_System_Private_Includes + * @{ + */ + + +#include "stm32f4xx.h" + +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ + || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) +/* #define DATA_IN_ExtSRAM */ +#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\ + STM32F412Zx || STM32F412Vx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +/* #define DATA_IN_ExtSDRAM */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\ + STM32F479xx */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +uint32_t SystemCoreClock = 16000000; +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes + * @{ + */ + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the FPU setting, vector table location and External memory + * configuration. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + #endif + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value + * depends on the application requirements), user has to ensure that HSE_VALUE + * is same as the real frequency of the crystal used. Otherwise, this function + * may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f4xx.s before jump to main. + * This function configures the external memories (SRAM/SDRAM) + * This SRAM/SDRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ + __IO uint32_t tmp = 0x00; + + register uint32_t tmpreg = 0, timeout = 0xFFFF; + register __IO uint32_t index; + + /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */ + RCC->AHB1ENR |= 0x000001F8; + + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x00CCC0CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A8A; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xFFFF0FCF; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00CC0CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA828A; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xFFFFC3CF; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0xCCCCCCCC; + GPIOF->AFR[1] = 0xCCCCCCCC; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA800AAA; + /* Configure PFx pins speed to 50 MHz */ + GPIOF->OSPEEDR = 0xAA800AAA; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0xCCCCCCCC; + GPIOG->AFR[1] = 0xCCCCCCCC; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0xAAAAAAAA; + /* Configure PGx pins speed to 50 MHz */ + GPIOG->OSPEEDR = 0xAAAAAAAA; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + + /* Connect PHx pins to FMC Alternate function */ + GPIOH->AFR[0] = 0x00C0CC00; + GPIOH->AFR[1] = 0xCCCCCCCC; + /* Configure PHx pins in Alternate function mode */ + GPIOH->MODER = 0xAAAA08A0; + /* Configure PHx pins speed to 50 MHz */ + GPIOH->OSPEEDR = 0xAAAA08A0; + /* Configure PHx pins Output type to push-pull */ + GPIOH->OTYPER = 0x00000000; + /* No pull-up, pull-down for PHx pins */ + GPIOH->PUPDR = 0x00000000; + + /* Connect PIx pins to FMC Alternate function */ + GPIOI->AFR[0] = 0xCCCCCCCC; + GPIOI->AFR[1] = 0x00000CC0; + /* Configure PIx pins in Alternate function mode */ + GPIOI->MODER = 0x0028AAAA; + /* Configure PIx pins speed to 50 MHz */ + GPIOI->OSPEEDR = 0x0028AAAA; + /* Configure PIx pins Output type to push-pull */ + GPIOI->OTYPER = 0x00000000; + /* No pull-up, pull-down for PIx pins */ + GPIOI->PUPDR = 0x00000000; + +/*-- FMC Configuration -------------------------------------------------------*/ + /* Enable the FMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + FMC_Bank5_6->SDCR[0] = 0x000019E4; + FMC_Bank5_6->SDTR[0] = 0x01115351; + + /* SDRAM initialization sequence */ + /* Clock enable command */ + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Delay */ + for (index = 0; index<1000; index++); + + /* PALL command */ + FMC_Bank5_6->SDCMR = 0x00000012; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Auto refresh command */ + FMC_Bank5_6->SDCMR = 0x00000073; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* MRD register program */ + FMC_Bank5_6->SDCMR = 0x00046014; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Set refresh count */ + tmpreg = FMC_Bank5_6->SDRTR; + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); + + /* Disable write protection */ + tmpreg = FMC_Bank5_6->SDCR[0]; + FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001011; + FMC_Bank1->BTCR[3] = 0x00000201; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#if defined(STM32F469xx) || defined(STM32F479xx) + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001091; + FMC_Bank1->BTCR[3] = 0x00110212; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F469xx || STM32F479xx */ + + (void)(tmp); +} +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ +#elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f4xx.s before jump to main. + * This function configures the external memories (SRAM/SDRAM) + * This SRAM/SDRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ + __IO uint32_t tmp = 0x00; +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +#if defined (DATA_IN_ExtSDRAM) + register uint32_t tmpreg = 0, timeout = 0xFFFF; + register __IO uint32_t index; + +#if defined(STM32F446xx) + /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface + clock */ + RCC->AHB1ENR |= 0x0000007D; +#else + /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface + clock */ + RCC->AHB1ENR |= 0x000001F8; +#endif /* STM32F446xx */ + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); + +#if defined(STM32F446xx) + /* Connect PAx pins to FMC Alternate function */ + GPIOA->AFR[0] |= 0xC0000000; + GPIOA->AFR[1] |= 0x00000000; + /* Configure PDx pins in Alternate function mode */ + GPIOA->MODER |= 0x00008000; + /* Configure PDx pins speed to 50 MHz */ + GPIOA->OSPEEDR |= 0x00008000; + /* Configure PDx pins Output type to push-pull */ + GPIOA->OTYPER |= 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOA->PUPDR |= 0x00000000; + + /* Connect PCx pins to FMC Alternate function */ + GPIOC->AFR[0] |= 0x00CC0000; + GPIOC->AFR[1] |= 0x00000000; + /* Configure PDx pins in Alternate function mode */ + GPIOC->MODER |= 0x00000A00; + /* Configure PDx pins speed to 50 MHz */ + GPIOC->OSPEEDR |= 0x00000A00; + /* Configure PDx pins Output type to push-pull */ + GPIOC->OTYPER |= 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOC->PUPDR |= 0x00000000; +#endif /* STM32F446xx */ + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x000000CC; + GPIOD->AFR[1] = 0xCC000CCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xA02A000A; + /* Configure PDx pins speed to 50 MHz */ + GPIOD->OSPEEDR = 0xA02A000A; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00000CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA800A; + /* Configure PEx pins speed to 50 MHz */ + GPIOE->OSPEEDR = 0xAAAA800A; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0xCCCCCCCC; + GPIOF->AFR[1] = 0xCCCCCCCC; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA800AAA; + /* Configure PFx pins speed to 50 MHz */ + GPIOF->OSPEEDR = 0xAA800AAA; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0xCCCCCCCC; + GPIOG->AFR[1] = 0xCCCCCCCC; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0xAAAAAAAA; + /* Configure PGx pins speed to 50 MHz */ + GPIOG->OSPEEDR = 0xAAAAAAAA; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) + /* Connect PHx pins to FMC Alternate function */ + GPIOH->AFR[0] = 0x00C0CC00; + GPIOH->AFR[1] = 0xCCCCCCCC; + /* Configure PHx pins in Alternate function mode */ + GPIOH->MODER = 0xAAAA08A0; + /* Configure PHx pins speed to 50 MHz */ + GPIOH->OSPEEDR = 0xAAAA08A0; + /* Configure PHx pins Output type to push-pull */ + GPIOH->OTYPER = 0x00000000; + /* No pull-up, pull-down for PHx pins */ + GPIOH->PUPDR = 0x00000000; + + /* Connect PIx pins to FMC Alternate function */ + GPIOI->AFR[0] = 0xCCCCCCCC; + GPIOI->AFR[1] = 0x00000CC0; + /* Configure PIx pins in Alternate function mode */ + GPIOI->MODER = 0x0028AAAA; + /* Configure PIx pins speed to 50 MHz */ + GPIOI->OSPEEDR = 0x0028AAAA; + /* Configure PIx pins Output type to push-pull */ + GPIOI->OTYPER = 0x00000000; + /* No pull-up, pull-down for PIx pins */ + GPIOI->PUPDR = 0x00000000; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +/*-- FMC Configuration -------------------------------------------------------*/ + /* Enable the FMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + /* Configure and enable SDRAM bank1 */ +#if defined(STM32F446xx) + FMC_Bank5_6->SDCR[0] = 0x00001954; +#else + FMC_Bank5_6->SDCR[0] = 0x000019E4; +#endif /* STM32F446xx */ + FMC_Bank5_6->SDTR[0] = 0x01115351; + + /* SDRAM initialization sequence */ + /* Clock enable command */ + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Delay */ + for (index = 0; index<1000; index++); + + /* PALL command */ + FMC_Bank5_6->SDCMR = 0x00000012; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Auto refresh command */ +#if defined(STM32F446xx) + FMC_Bank5_6->SDCMR = 0x000000F3; +#else + FMC_Bank5_6->SDCMR = 0x00000073; +#endif /* STM32F446xx */ + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* MRD register program */ +#if defined(STM32F446xx) + FMC_Bank5_6->SDCMR = 0x00044014; +#else + FMC_Bank5_6->SDCMR = 0x00046014; +#endif /* STM32F446xx */ + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Set refresh count */ + tmpreg = FMC_Bank5_6->SDRTR; +#if defined(STM32F446xx) + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1)); +#else + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); +#endif /* STM32F446xx */ + + /* Disable write protection */ + tmpreg = FMC_Bank5_6->SDCR[0]; + FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); +#endif /* DATA_IN_ExtSDRAM */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ + || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) + +#if defined(DATA_IN_ExtSRAM) +/*-- GPIOs Configuration -----------------------------------------------------*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR |= 0x00000078; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN); + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x00CCC0CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A8A; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xFFFF0FCF; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00CC0CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA828A; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xFFFFC3CF; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0x00CCCCCC; + GPIOF->AFR[1] = 0xCCCC0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA000AAA; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xFF000FFF; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0x00CCCCCC; + GPIOG->AFR[1] = 0x000000C0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00085AAA; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000CAFFF; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FMC/FSMC Configuration --------------------------------------------------*/ + /* Enable the FMC/FSMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001011; + FMC_Bank1->BTCR[3] = 0x00000201; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#if defined(STM32F469xx) || defined(STM32F479xx) + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001091; + FMC_Bank1->BTCR[3] = 0x00110212; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F469xx || STM32F479xx */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\ + || defined(STM32F412Zx) || defined(STM32F412Vx) + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN); + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001011; + FSMC_Bank1->BTCR[3] = 0x00000201; + FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF; +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */ + +#endif /* DATA_IN_ExtSRAM */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ + STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */ + (void)(tmp); +} +#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Core/Startup/startup_stm32f401vctx.s b/Core/Startup/startup_stm32f401vctx.s new file mode 100644 index 0000000..10ad298 --- /dev/null +++ b/Core/Startup/startup_stm32f401vctx.s @@ -0,0 +1,432 @@ +/** + ****************************************************************************** + * @file startup_stm32f401xc.s + * @author MCD Application Team + * @brief STM32F401xCxx Devices vector table for GCC based toolchains. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word 0 /* Reserved */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word 0 /* Reserved */ + .word SDIO_IRQHandler /* SDIO */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word FPU_IRQHandler /* FPU */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SPI4_IRQHandler /* SPI4 */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/Debug/Core/Src/subdir.mk b/Debug/Core/Src/subdir.mk new file mode 100644 index 0000000..1c34243 --- /dev/null +++ b/Debug/Core/Src/subdir.mk @@ -0,0 +1,49 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Core/Src/app.c \ +../Core/Src/main.c \ +../Core/Src/stm32f4xx_hal_msp.c \ +../Core/Src/stm32f4xx_it.c \ +../Core/Src/syscalls.c \ +../Core/Src/sysmem.c \ +../Core/Src/system_stm32f4xx.c + +C_DEPS += \ +./Core/Src/app.d \ +./Core/Src/main.d \ +./Core/Src/stm32f4xx_hal_msp.d \ +./Core/Src/stm32f4xx_it.d \ +./Core/Src/syscalls.d \ +./Core/Src/sysmem.d \ +./Core/Src/system_stm32f4xx.d + +OBJS += \ +./Core/Src/app.o \ +./Core/Src/main.o \ +./Core/Src/stm32f4xx_hal_msp.o \ +./Core/Src/stm32f4xx_it.o \ +./Core/Src/syscalls.o \ +./Core/Src/sysmem.o \ +./Core/Src/system_stm32f4xx.o + + +# Each subdirectory must supply rules for building sources it contributes +Core/Src/app.o: ../Core/Src/app.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F401xC -DDEBUG -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/app.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Core/Src/main.o: ../Core/Src/main.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F401xC -DDEBUG -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/main.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Core/Src/stm32f4xx_hal_msp.o: ../Core/Src/stm32f4xx_hal_msp.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F401xC -DDEBUG -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/stm32f4xx_hal_msp.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Core/Src/stm32f4xx_it.o: ../Core/Src/stm32f4xx_it.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F401xC -DDEBUG -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/stm32f4xx_it.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Core/Src/syscalls.o: ../Core/Src/syscalls.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F401xC -DDEBUG -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/syscalls.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Core/Src/sysmem.o: ../Core/Src/sysmem.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F401xC -DDEBUG -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/sysmem.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Core/Src/system_stm32f4xx.o: ../Core/Src/system_stm32f4xx.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F401xC -DDEBUG -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/system_stm32f4xx.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + diff --git a/Debug/Core/Startup/subdir.mk b/Debug/Core/Startup/subdir.mk new file mode 100644 index 0000000..ee377a6 --- /dev/null +++ b/Debug/Core/Startup/subdir.mk @@ -0,0 +1,19 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Core/Startup/startup_stm32f401vctx.s + +S_DEPS += \ +./Core/Startup/startup_stm32f401vctx.d + +OBJS += \ +./Core/Startup/startup_stm32f401vctx.o + + +# Each subdirectory must supply rules for building sources it contributes +Core/Startup/startup_stm32f401vctx.o: ../Core/Startup/startup_stm32f401vctx.s + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -c -x assembler-with-cpp -MMD -MP -MF"Core/Startup/startup_stm32f401vctx.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" "$<" + diff --git a/Debug/Drivers/COMPASS_LEDS/subdir.mk b/Debug/Drivers/COMPASS_LEDS/subdir.mk new file mode 100644 index 0000000..6e1e336 --- /dev/null +++ b/Debug/Drivers/COMPASS_LEDS/subdir.mk @@ -0,0 +1,19 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/COMPASS_LEDS/COMPASS_LEDS.c + +C_DEPS += \ +./Drivers/COMPASS_LEDS/COMPASS_LEDS.d + +OBJS += \ +./Drivers/COMPASS_LEDS/COMPASS_LEDS.o + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/COMPASS_LEDS/COMPASS_LEDS.o: ../Drivers/COMPASS_LEDS/COMPASS_LEDS.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F401xC -DDEBUG -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/COMPASS_LEDS/COMPASS_LEDS.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + diff --git a/Debug/Drivers/LSM303DLHC/subdir.mk b/Debug/Drivers/LSM303DLHC/subdir.mk new file mode 100644 index 0000000..ad5689d --- /dev/null +++ b/Debug/Drivers/LSM303DLHC/subdir.mk @@ -0,0 +1,19 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/LSM303DLHC/LSM303DLHC.c + +C_DEPS += \ +./Drivers/LSM303DLHC/LSM303DLHC.d + +OBJS += \ +./Drivers/LSM303DLHC/LSM303DLHC.o + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/LSM303DLHC/LSM303DLHC.o: ../Drivers/LSM303DLHC/LSM303DLHC.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F401xC -DDEBUG -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/LSM303DLHC/LSM303DLHC.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/subdir.mk b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/subdir.mk new file mode 100644 index 0000000..057bd06 --- /dev/null +++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/subdir.mk @@ -0,0 +1,129 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c + +C_DEPS += \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.d + +OBJS += \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.o + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o: ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F401xC -DDEBUG -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o: ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F401xC -DDEBUG -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o: ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F401xC -DDEBUG -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o: ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F401xC -DDEBUG -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o: ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F401xC -DDEBUG -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o: ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F401xC -DDEBUG -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o: ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F401xC -DDEBUG -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o: ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F401xC -DDEBUG -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o: ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F401xC -DDEBUG -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.o: ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F401xC -DDEBUG -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.o: ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F401xC -DDEBUG -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.o: ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F401xC -DDEBUG -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.o: ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F401xC -DDEBUG -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.o: ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F401xC -DDEBUG -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o: ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F401xC -DDEBUG -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o: ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F401xC -DDEBUG -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o: ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F401xC -DDEBUG -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o: ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F401xC -DDEBUG -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.o: ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F401xC -DDEBUG -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o: ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F401xC -DDEBUG -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o: ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F401xC -DDEBUG -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o: ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F401xC -DDEBUG -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.o: ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F401xC -DDEBUG -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + diff --git a/Debug/Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Src/subdir.mk b/Debug/Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Src/subdir.mk new file mode 100644 index 0000000..3d351dc --- /dev/null +++ b/Debug/Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Src/subdir.mk @@ -0,0 +1,19 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Src/usbh_cdc.c + +C_DEPS += \ +./Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Src/usbh_cdc.d + +OBJS += \ +./Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Src/usbh_cdc.o + + +# Each subdirectory must supply rules for building sources it contributes +Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Src/usbh_cdc.o: ../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Src/usbh_cdc.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F401xC -DDEBUG -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Src/usbh_cdc.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + diff --git a/Debug/Middlewares/ST/STM32_USB_Host_Library/Core/Src/subdir.mk b/Debug/Middlewares/ST/STM32_USB_Host_Library/Core/Src/subdir.mk new file mode 100644 index 0000000..87783c5 --- /dev/null +++ b/Debug/Middlewares/ST/STM32_USB_Host_Library/Core/Src/subdir.mk @@ -0,0 +1,34 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_core.c \ +../Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ctlreq.c \ +../Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ioreq.c \ +../Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_pipes.c + +C_DEPS += \ +./Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_core.d \ +./Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ctlreq.d \ +./Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ioreq.d \ +./Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_pipes.d + +OBJS += \ +./Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_core.o \ +./Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ctlreq.o \ +./Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ioreq.o \ +./Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_pipes.o + + +# Each subdirectory must supply rules for building sources it contributes +Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_core.o: ../Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_core.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F401xC -DDEBUG -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_core.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ctlreq.o: ../Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ctlreq.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F401xC -DDEBUG -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ctlreq.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ioreq.o: ../Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ioreq.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F401xC -DDEBUG -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ioreq.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_pipes.o: ../Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_pipes.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F401xC -DDEBUG -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_pipes.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + diff --git a/Debug/USB_HOST/App/subdir.mk b/Debug/USB_HOST/App/subdir.mk new file mode 100644 index 0000000..dfb37cc --- /dev/null +++ b/Debug/USB_HOST/App/subdir.mk @@ -0,0 +1,19 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../USB_HOST/App/usb_host.c + +C_DEPS += \ +./USB_HOST/App/usb_host.d + +OBJS += \ +./USB_HOST/App/usb_host.o + + +# Each subdirectory must supply rules for building sources it contributes +USB_HOST/App/usb_host.o: ../USB_HOST/App/usb_host.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F401xC -DDEBUG -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"USB_HOST/App/usb_host.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + diff --git a/Debug/USB_HOST/Target/subdir.mk b/Debug/USB_HOST/Target/subdir.mk new file mode 100644 index 0000000..65baee5 --- /dev/null +++ b/Debug/USB_HOST/Target/subdir.mk @@ -0,0 +1,24 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../USB_HOST/Target/usbh_conf.c \ +../USB_HOST/Target/usbh_platform.c + +C_DEPS += \ +./USB_HOST/Target/usbh_conf.d \ +./USB_HOST/Target/usbh_platform.d + +OBJS += \ +./USB_HOST/Target/usbh_conf.o \ +./USB_HOST/Target/usbh_platform.o + + +# Each subdirectory must supply rules for building sources it contributes +USB_HOST/Target/usbh_conf.o: ../USB_HOST/Target/usbh_conf.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F401xC -DDEBUG -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"USB_HOST/Target/usbh_conf.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +USB_HOST/Target/usbh_platform.o: ../USB_HOST/Target/usbh_platform.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F401xC -DDEBUG -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"USB_HOST/Target/usbh_platform.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + diff --git a/Debug/eCompass.bin b/Debug/eCompass.bin new file mode 100644 index 0000000..032667a Binary files /dev/null and b/Debug/eCompass.bin differ diff --git a/Debug/eCompass.list b/Debug/eCompass.list new file mode 100644 index 0000000..057d94d --- /dev/null +++ b/Debug/eCompass.list @@ -0,0 +1,33036 @@ + +eCompass.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .isr_vector 00000194 08000000 08000000 00010000 2**0 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 1 .text 0000e680 080001a0 080001a0 000101a0 2**4 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 .rodata 00000438 0800e820 0800e820 0001e820 2**3 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .ARM.extab 00000000 0800ec58 0800ec58 000201fc 2**0 + CONTENTS + 4 .ARM 00000008 0800ec58 0800ec58 0001ec58 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 5 .preinit_array 00000000 0800ec60 0800ec60 000201fc 2**0 + CONTENTS, ALLOC, LOAD, DATA + 6 .init_array 00000004 0800ec60 0800ec60 0001ec60 2**2 + CONTENTS, ALLOC, LOAD, DATA + 7 .fini_array 00000004 0800ec64 0800ec64 0001ec64 2**2 + CONTENTS, ALLOC, LOAD, DATA + 8 .data 000001fc 20000000 0800ec68 00020000 2**2 + CONTENTS, ALLOC, LOAD, DATA + 9 .bss 000008b8 200001fc 0800ee64 000201fc 2**2 + ALLOC + 10 ._user_heap_stack 00000604 20000ab4 0800ee64 00020ab4 2**0 + ALLOC + 11 .ARM.attributes 00000030 00000000 00000000 000201fc 2**0 + CONTENTS, READONLY + 12 .debug_info 0001d66d 00000000 00000000 0002022c 2**0 + CONTENTS, READONLY, DEBUGGING + 13 .debug_abbrev 00004048 00000000 00000000 0003d899 2**0 + CONTENTS, READONLY, DEBUGGING + 14 .debug_aranges 00001458 00000000 00000000 000418e8 2**3 + CONTENTS, READONLY, DEBUGGING + 15 .debug_ranges 000012a8 00000000 00000000 00042d40 2**3 + CONTENTS, READONLY, DEBUGGING + 16 .debug_macro 0001ba14 00000000 00000000 00043fe8 2**0 + CONTENTS, READONLY, DEBUGGING + 17 .debug_line 000147bf 00000000 00000000 0005f9fc 2**0 + CONTENTS, READONLY, DEBUGGING + 18 .debug_str 00092511 00000000 00000000 000741bb 2**0 + CONTENTS, READONLY, DEBUGGING + 19 .comment 0000007b 00000000 00000000 001066cc 2**0 + CONTENTS, READONLY + 20 .debug_frame 000066f8 00000000 00000000 00106748 2**2 + CONTENTS, READONLY, DEBUGGING + +Disassembly of section .text: + +080001a0 <__do_global_dtors_aux>: + 80001a0: b510 push {r4, lr} + 80001a2: 4c05 ldr r4, [pc, #20] ; (80001b8 <__do_global_dtors_aux+0x18>) + 80001a4: 7823 ldrb r3, [r4, #0] + 80001a6: b933 cbnz r3, 80001b6 <__do_global_dtors_aux+0x16> + 80001a8: 4b04 ldr r3, [pc, #16] ; (80001bc <__do_global_dtors_aux+0x1c>) + 80001aa: b113 cbz r3, 80001b2 <__do_global_dtors_aux+0x12> + 80001ac: 4804 ldr r0, [pc, #16] ; (80001c0 <__do_global_dtors_aux+0x20>) + 80001ae: f3af 8000 nop.w + 80001b2: 2301 movs r3, #1 + 80001b4: 7023 strb r3, [r4, #0] + 80001b6: bd10 pop {r4, pc} + 80001b8: 200001fc .word 0x200001fc + 80001bc: 00000000 .word 0x00000000 + 80001c0: 0800e808 .word 0x0800e808 + +080001c4 : + 80001c4: b508 push {r3, lr} + 80001c6: 4b03 ldr r3, [pc, #12] ; (80001d4 ) + 80001c8: b11b cbz r3, 80001d2 + 80001ca: 4903 ldr r1, [pc, #12] ; (80001d8 ) + 80001cc: 4803 ldr r0, [pc, #12] ; (80001dc ) + 80001ce: f3af 8000 nop.w + 80001d2: bd08 pop {r3, pc} + 80001d4: 00000000 .word 0x00000000 + 80001d8: 20000200 .word 0x20000200 + 80001dc: 0800e808 .word 0x0800e808 + +080001e0 : + 80001e0: 4603 mov r3, r0 + 80001e2: f813 2b01 ldrb.w r2, [r3], #1 + 80001e6: 2a00 cmp r2, #0 + 80001e8: d1fb bne.n 80001e2 + 80001ea: 1a18 subs r0, r3, r0 + 80001ec: 3801 subs r0, #1 + 80001ee: 4770 bx lr + +080001f0 : + 80001f0: f001 01ff and.w r1, r1, #255 ; 0xff + 80001f4: 2a10 cmp r2, #16 + 80001f6: db2b blt.n 8000250 + 80001f8: f010 0f07 tst.w r0, #7 + 80001fc: d008 beq.n 8000210 + 80001fe: f810 3b01 ldrb.w r3, [r0], #1 + 8000202: 3a01 subs r2, #1 + 8000204: 428b cmp r3, r1 + 8000206: d02d beq.n 8000264 + 8000208: f010 0f07 tst.w r0, #7 + 800020c: b342 cbz r2, 8000260 + 800020e: d1f6 bne.n 80001fe + 8000210: b4f0 push {r4, r5, r6, r7} + 8000212: ea41 2101 orr.w r1, r1, r1, lsl #8 + 8000216: ea41 4101 orr.w r1, r1, r1, lsl #16 + 800021a: f022 0407 bic.w r4, r2, #7 + 800021e: f07f 0700 mvns.w r7, #0 + 8000222: 2300 movs r3, #0 + 8000224: e8f0 5602 ldrd r5, r6, [r0], #8 + 8000228: 3c08 subs r4, #8 + 800022a: ea85 0501 eor.w r5, r5, r1 + 800022e: ea86 0601 eor.w r6, r6, r1 + 8000232: fa85 f547 uadd8 r5, r5, r7 + 8000236: faa3 f587 sel r5, r3, r7 + 800023a: fa86 f647 uadd8 r6, r6, r7 + 800023e: faa5 f687 sel r6, r5, r7 + 8000242: b98e cbnz r6, 8000268 + 8000244: d1ee bne.n 8000224 + 8000246: bcf0 pop {r4, r5, r6, r7} + 8000248: f001 01ff and.w r1, r1, #255 ; 0xff + 800024c: f002 0207 and.w r2, r2, #7 + 8000250: b132 cbz r2, 8000260 + 8000252: f810 3b01 ldrb.w r3, [r0], #1 + 8000256: 3a01 subs r2, #1 + 8000258: ea83 0301 eor.w r3, r3, r1 + 800025c: b113 cbz r3, 8000264 + 800025e: d1f8 bne.n 8000252 + 8000260: 2000 movs r0, #0 + 8000262: 4770 bx lr + 8000264: 3801 subs r0, #1 + 8000266: 4770 bx lr + 8000268: 2d00 cmp r5, #0 + 800026a: bf06 itte eq + 800026c: 4635 moveq r5, r6 + 800026e: 3803 subeq r0, #3 + 8000270: 3807 subne r0, #7 + 8000272: f015 0f01 tst.w r5, #1 + 8000276: d107 bne.n 8000288 + 8000278: 3001 adds r0, #1 + 800027a: f415 7f80 tst.w r5, #256 ; 0x100 + 800027e: bf02 ittt eq + 8000280: 3001 addeq r0, #1 + 8000282: f415 3fc0 tsteq.w r5, #98304 ; 0x18000 + 8000286: 3001 addeq r0, #1 + 8000288: bcf0 pop {r4, r5, r6, r7} + 800028a: 3801 subs r0, #1 + 800028c: 4770 bx lr + 800028e: bf00 nop + +08000290 <__aeabi_drsub>: + 8000290: f081 4100 eor.w r1, r1, #2147483648 ; 0x80000000 + 8000294: e002 b.n 800029c <__adddf3> + 8000296: bf00 nop + +08000298 <__aeabi_dsub>: + 8000298: f083 4300 eor.w r3, r3, #2147483648 ; 0x80000000 + +0800029c <__adddf3>: + 800029c: b530 push {r4, r5, lr} + 800029e: ea4f 0441 mov.w r4, r1, lsl #1 + 80002a2: ea4f 0543 mov.w r5, r3, lsl #1 + 80002a6: ea94 0f05 teq r4, r5 + 80002aa: bf08 it eq + 80002ac: ea90 0f02 teqeq r0, r2 + 80002b0: bf1f itttt ne + 80002b2: ea54 0c00 orrsne.w ip, r4, r0 + 80002b6: ea55 0c02 orrsne.w ip, r5, r2 + 80002ba: ea7f 5c64 mvnsne.w ip, r4, asr #21 + 80002be: ea7f 5c65 mvnsne.w ip, r5, asr #21 + 80002c2: f000 80e2 beq.w 800048a <__adddf3+0x1ee> + 80002c6: ea4f 5454 mov.w r4, r4, lsr #21 + 80002ca: ebd4 5555 rsbs r5, r4, r5, lsr #21 + 80002ce: bfb8 it lt + 80002d0: 426d neglt r5, r5 + 80002d2: dd0c ble.n 80002ee <__adddf3+0x52> + 80002d4: 442c add r4, r5 + 80002d6: ea80 0202 eor.w r2, r0, r2 + 80002da: ea81 0303 eor.w r3, r1, r3 + 80002de: ea82 0000 eor.w r0, r2, r0 + 80002e2: ea83 0101 eor.w r1, r3, r1 + 80002e6: ea80 0202 eor.w r2, r0, r2 + 80002ea: ea81 0303 eor.w r3, r1, r3 + 80002ee: 2d36 cmp r5, #54 ; 0x36 + 80002f0: bf88 it hi + 80002f2: bd30 pophi {r4, r5, pc} + 80002f4: f011 4f00 tst.w r1, #2147483648 ; 0x80000000 + 80002f8: ea4f 3101 mov.w r1, r1, lsl #12 + 80002fc: f44f 1c80 mov.w ip, #1048576 ; 0x100000 + 8000300: ea4c 3111 orr.w r1, ip, r1, lsr #12 + 8000304: d002 beq.n 800030c <__adddf3+0x70> + 8000306: 4240 negs r0, r0 + 8000308: eb61 0141 sbc.w r1, r1, r1, lsl #1 + 800030c: f013 4f00 tst.w r3, #2147483648 ; 0x80000000 + 8000310: ea4f 3303 mov.w r3, r3, lsl #12 + 8000314: ea4c 3313 orr.w r3, ip, r3, lsr #12 + 8000318: d002 beq.n 8000320 <__adddf3+0x84> + 800031a: 4252 negs r2, r2 + 800031c: eb63 0343 sbc.w r3, r3, r3, lsl #1 + 8000320: ea94 0f05 teq r4, r5 + 8000324: f000 80a7 beq.w 8000476 <__adddf3+0x1da> + 8000328: f1a4 0401 sub.w r4, r4, #1 + 800032c: f1d5 0e20 rsbs lr, r5, #32 + 8000330: db0d blt.n 800034e <__adddf3+0xb2> + 8000332: fa02 fc0e lsl.w ip, r2, lr + 8000336: fa22 f205 lsr.w r2, r2, r5 + 800033a: 1880 adds r0, r0, r2 + 800033c: f141 0100 adc.w r1, r1, #0 + 8000340: fa03 f20e lsl.w r2, r3, lr + 8000344: 1880 adds r0, r0, r2 + 8000346: fa43 f305 asr.w r3, r3, r5 + 800034a: 4159 adcs r1, r3 + 800034c: e00e b.n 800036c <__adddf3+0xd0> + 800034e: f1a5 0520 sub.w r5, r5, #32 + 8000352: f10e 0e20 add.w lr, lr, #32 + 8000356: 2a01 cmp r2, #1 + 8000358: fa03 fc0e lsl.w ip, r3, lr + 800035c: bf28 it cs + 800035e: f04c 0c02 orrcs.w ip, ip, #2 + 8000362: fa43 f305 asr.w r3, r3, r5 + 8000366: 18c0 adds r0, r0, r3 + 8000368: eb51 71e3 adcs.w r1, r1, r3, asr #31 + 800036c: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 + 8000370: d507 bpl.n 8000382 <__adddf3+0xe6> + 8000372: f04f 0e00 mov.w lr, #0 + 8000376: f1dc 0c00 rsbs ip, ip, #0 + 800037a: eb7e 0000 sbcs.w r0, lr, r0 + 800037e: eb6e 0101 sbc.w r1, lr, r1 + 8000382: f5b1 1f80 cmp.w r1, #1048576 ; 0x100000 + 8000386: d31b bcc.n 80003c0 <__adddf3+0x124> + 8000388: f5b1 1f00 cmp.w r1, #2097152 ; 0x200000 + 800038c: d30c bcc.n 80003a8 <__adddf3+0x10c> + 800038e: 0849 lsrs r1, r1, #1 + 8000390: ea5f 0030 movs.w r0, r0, rrx + 8000394: ea4f 0c3c mov.w ip, ip, rrx + 8000398: f104 0401 add.w r4, r4, #1 + 800039c: ea4f 5244 mov.w r2, r4, lsl #21 + 80003a0: f512 0f80 cmn.w r2, #4194304 ; 0x400000 + 80003a4: f080 809a bcs.w 80004dc <__adddf3+0x240> + 80003a8: f1bc 4f00 cmp.w ip, #2147483648 ; 0x80000000 + 80003ac: bf08 it eq + 80003ae: ea5f 0c50 movseq.w ip, r0, lsr #1 + 80003b2: f150 0000 adcs.w r0, r0, #0 + 80003b6: eb41 5104 adc.w r1, r1, r4, lsl #20 + 80003ba: ea41 0105 orr.w r1, r1, r5 + 80003be: bd30 pop {r4, r5, pc} + 80003c0: ea5f 0c4c movs.w ip, ip, lsl #1 + 80003c4: 4140 adcs r0, r0 + 80003c6: eb41 0101 adc.w r1, r1, r1 + 80003ca: f411 1f80 tst.w r1, #1048576 ; 0x100000 + 80003ce: f1a4 0401 sub.w r4, r4, #1 + 80003d2: d1e9 bne.n 80003a8 <__adddf3+0x10c> + 80003d4: f091 0f00 teq r1, #0 + 80003d8: bf04 itt eq + 80003da: 4601 moveq r1, r0 + 80003dc: 2000 moveq r0, #0 + 80003de: fab1 f381 clz r3, r1 + 80003e2: bf08 it eq + 80003e4: 3320 addeq r3, #32 + 80003e6: f1a3 030b sub.w r3, r3, #11 + 80003ea: f1b3 0220 subs.w r2, r3, #32 + 80003ee: da0c bge.n 800040a <__adddf3+0x16e> + 80003f0: 320c adds r2, #12 + 80003f2: dd08 ble.n 8000406 <__adddf3+0x16a> + 80003f4: f102 0c14 add.w ip, r2, #20 + 80003f8: f1c2 020c rsb r2, r2, #12 + 80003fc: fa01 f00c lsl.w r0, r1, ip + 8000400: fa21 f102 lsr.w r1, r1, r2 + 8000404: e00c b.n 8000420 <__adddf3+0x184> + 8000406: f102 0214 add.w r2, r2, #20 + 800040a: bfd8 it le + 800040c: f1c2 0c20 rsble ip, r2, #32 + 8000410: fa01 f102 lsl.w r1, r1, r2 + 8000414: fa20 fc0c lsr.w ip, r0, ip + 8000418: bfdc itt le + 800041a: ea41 010c orrle.w r1, r1, ip + 800041e: 4090 lslle r0, r2 + 8000420: 1ae4 subs r4, r4, r3 + 8000422: bfa2 ittt ge + 8000424: eb01 5104 addge.w r1, r1, r4, lsl #20 + 8000428: 4329 orrge r1, r5 + 800042a: bd30 popge {r4, r5, pc} + 800042c: ea6f 0404 mvn.w r4, r4 + 8000430: 3c1f subs r4, #31 + 8000432: da1c bge.n 800046e <__adddf3+0x1d2> + 8000434: 340c adds r4, #12 + 8000436: dc0e bgt.n 8000456 <__adddf3+0x1ba> + 8000438: f104 0414 add.w r4, r4, #20 + 800043c: f1c4 0220 rsb r2, r4, #32 + 8000440: fa20 f004 lsr.w r0, r0, r4 + 8000444: fa01 f302 lsl.w r3, r1, r2 + 8000448: ea40 0003 orr.w r0, r0, r3 + 800044c: fa21 f304 lsr.w r3, r1, r4 + 8000450: ea45 0103 orr.w r1, r5, r3 + 8000454: bd30 pop {r4, r5, pc} + 8000456: f1c4 040c rsb r4, r4, #12 + 800045a: f1c4 0220 rsb r2, r4, #32 + 800045e: fa20 f002 lsr.w r0, r0, r2 + 8000462: fa01 f304 lsl.w r3, r1, r4 + 8000466: ea40 0003 orr.w r0, r0, r3 + 800046a: 4629 mov r1, r5 + 800046c: bd30 pop {r4, r5, pc} + 800046e: fa21 f004 lsr.w r0, r1, r4 + 8000472: 4629 mov r1, r5 + 8000474: bd30 pop {r4, r5, pc} + 8000476: f094 0f00 teq r4, #0 + 800047a: f483 1380 eor.w r3, r3, #1048576 ; 0x100000 + 800047e: bf06 itte eq + 8000480: f481 1180 eoreq.w r1, r1, #1048576 ; 0x100000 + 8000484: 3401 addeq r4, #1 + 8000486: 3d01 subne r5, #1 + 8000488: e74e b.n 8000328 <__adddf3+0x8c> + 800048a: ea7f 5c64 mvns.w ip, r4, asr #21 + 800048e: bf18 it ne + 8000490: ea7f 5c65 mvnsne.w ip, r5, asr #21 + 8000494: d029 beq.n 80004ea <__adddf3+0x24e> + 8000496: ea94 0f05 teq r4, r5 + 800049a: bf08 it eq + 800049c: ea90 0f02 teqeq r0, r2 + 80004a0: d005 beq.n 80004ae <__adddf3+0x212> + 80004a2: ea54 0c00 orrs.w ip, r4, r0 + 80004a6: bf04 itt eq + 80004a8: 4619 moveq r1, r3 + 80004aa: 4610 moveq r0, r2 + 80004ac: bd30 pop {r4, r5, pc} + 80004ae: ea91 0f03 teq r1, r3 + 80004b2: bf1e ittt ne + 80004b4: 2100 movne r1, #0 + 80004b6: 2000 movne r0, #0 + 80004b8: bd30 popne {r4, r5, pc} + 80004ba: ea5f 5c54 movs.w ip, r4, lsr #21 + 80004be: d105 bne.n 80004cc <__adddf3+0x230> + 80004c0: 0040 lsls r0, r0, #1 + 80004c2: 4149 adcs r1, r1 + 80004c4: bf28 it cs + 80004c6: f041 4100 orrcs.w r1, r1, #2147483648 ; 0x80000000 + 80004ca: bd30 pop {r4, r5, pc} + 80004cc: f514 0480 adds.w r4, r4, #4194304 ; 0x400000 + 80004d0: bf3c itt cc + 80004d2: f501 1180 addcc.w r1, r1, #1048576 ; 0x100000 + 80004d6: bd30 popcc {r4, r5, pc} + 80004d8: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 + 80004dc: f045 41fe orr.w r1, r5, #2130706432 ; 0x7f000000 + 80004e0: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000 + 80004e4: f04f 0000 mov.w r0, #0 + 80004e8: bd30 pop {r4, r5, pc} + 80004ea: ea7f 5c64 mvns.w ip, r4, asr #21 + 80004ee: bf1a itte ne + 80004f0: 4619 movne r1, r3 + 80004f2: 4610 movne r0, r2 + 80004f4: ea7f 5c65 mvnseq.w ip, r5, asr #21 + 80004f8: bf1c itt ne + 80004fa: 460b movne r3, r1 + 80004fc: 4602 movne r2, r0 + 80004fe: ea50 3401 orrs.w r4, r0, r1, lsl #12 + 8000502: bf06 itte eq + 8000504: ea52 3503 orrseq.w r5, r2, r3, lsl #12 + 8000508: ea91 0f03 teqeq r1, r3 + 800050c: f441 2100 orrne.w r1, r1, #524288 ; 0x80000 + 8000510: bd30 pop {r4, r5, pc} + 8000512: bf00 nop + +08000514 <__aeabi_ui2d>: + 8000514: f090 0f00 teq r0, #0 + 8000518: bf04 itt eq + 800051a: 2100 moveq r1, #0 + 800051c: 4770 bxeq lr + 800051e: b530 push {r4, r5, lr} + 8000520: f44f 6480 mov.w r4, #1024 ; 0x400 + 8000524: f104 0432 add.w r4, r4, #50 ; 0x32 + 8000528: f04f 0500 mov.w r5, #0 + 800052c: f04f 0100 mov.w r1, #0 + 8000530: e750 b.n 80003d4 <__adddf3+0x138> + 8000532: bf00 nop + +08000534 <__aeabi_i2d>: + 8000534: f090 0f00 teq r0, #0 + 8000538: bf04 itt eq + 800053a: 2100 moveq r1, #0 + 800053c: 4770 bxeq lr + 800053e: b530 push {r4, r5, lr} + 8000540: f44f 6480 mov.w r4, #1024 ; 0x400 + 8000544: f104 0432 add.w r4, r4, #50 ; 0x32 + 8000548: f010 4500 ands.w r5, r0, #2147483648 ; 0x80000000 + 800054c: bf48 it mi + 800054e: 4240 negmi r0, r0 + 8000550: f04f 0100 mov.w r1, #0 + 8000554: e73e b.n 80003d4 <__adddf3+0x138> + 8000556: bf00 nop + +08000558 <__aeabi_f2d>: + 8000558: 0042 lsls r2, r0, #1 + 800055a: ea4f 01e2 mov.w r1, r2, asr #3 + 800055e: ea4f 0131 mov.w r1, r1, rrx + 8000562: ea4f 7002 mov.w r0, r2, lsl #28 + 8000566: bf1f itttt ne + 8000568: f012 437f andsne.w r3, r2, #4278190080 ; 0xff000000 + 800056c: f093 4f7f teqne r3, #4278190080 ; 0xff000000 + 8000570: f081 5160 eorne.w r1, r1, #939524096 ; 0x38000000 + 8000574: 4770 bxne lr + 8000576: f032 427f bics.w r2, r2, #4278190080 ; 0xff000000 + 800057a: bf08 it eq + 800057c: 4770 bxeq lr + 800057e: f093 4f7f teq r3, #4278190080 ; 0xff000000 + 8000582: bf04 itt eq + 8000584: f441 2100 orreq.w r1, r1, #524288 ; 0x80000 + 8000588: 4770 bxeq lr + 800058a: b530 push {r4, r5, lr} + 800058c: f44f 7460 mov.w r4, #896 ; 0x380 + 8000590: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 + 8000594: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000 + 8000598: e71c b.n 80003d4 <__adddf3+0x138> + 800059a: bf00 nop + +0800059c <__aeabi_ul2d>: + 800059c: ea50 0201 orrs.w r2, r0, r1 + 80005a0: bf08 it eq + 80005a2: 4770 bxeq lr + 80005a4: b530 push {r4, r5, lr} + 80005a6: f04f 0500 mov.w r5, #0 + 80005aa: e00a b.n 80005c2 <__aeabi_l2d+0x16> + +080005ac <__aeabi_l2d>: + 80005ac: ea50 0201 orrs.w r2, r0, r1 + 80005b0: bf08 it eq + 80005b2: 4770 bxeq lr + 80005b4: b530 push {r4, r5, lr} + 80005b6: f011 4500 ands.w r5, r1, #2147483648 ; 0x80000000 + 80005ba: d502 bpl.n 80005c2 <__aeabi_l2d+0x16> + 80005bc: 4240 negs r0, r0 + 80005be: eb61 0141 sbc.w r1, r1, r1, lsl #1 + 80005c2: f44f 6480 mov.w r4, #1024 ; 0x400 + 80005c6: f104 0432 add.w r4, r4, #50 ; 0x32 + 80005ca: ea5f 5c91 movs.w ip, r1, lsr #22 + 80005ce: f43f aed8 beq.w 8000382 <__adddf3+0xe6> + 80005d2: f04f 0203 mov.w r2, #3 + 80005d6: ea5f 0cdc movs.w ip, ip, lsr #3 + 80005da: bf18 it ne + 80005dc: 3203 addne r2, #3 + 80005de: ea5f 0cdc movs.w ip, ip, lsr #3 + 80005e2: bf18 it ne + 80005e4: 3203 addne r2, #3 + 80005e6: eb02 02dc add.w r2, r2, ip, lsr #3 + 80005ea: f1c2 0320 rsb r3, r2, #32 + 80005ee: fa00 fc03 lsl.w ip, r0, r3 + 80005f2: fa20 f002 lsr.w r0, r0, r2 + 80005f6: fa01 fe03 lsl.w lr, r1, r3 + 80005fa: ea40 000e orr.w r0, r0, lr + 80005fe: fa21 f102 lsr.w r1, r1, r2 + 8000602: 4414 add r4, r2 + 8000604: e6bd b.n 8000382 <__adddf3+0xe6> + 8000606: bf00 nop + +08000608 <__aeabi_dmul>: + 8000608: b570 push {r4, r5, r6, lr} + 800060a: f04f 0cff mov.w ip, #255 ; 0xff + 800060e: f44c 6ce0 orr.w ip, ip, #1792 ; 0x700 + 8000612: ea1c 5411 ands.w r4, ip, r1, lsr #20 + 8000616: bf1d ittte ne + 8000618: ea1c 5513 andsne.w r5, ip, r3, lsr #20 + 800061c: ea94 0f0c teqne r4, ip + 8000620: ea95 0f0c teqne r5, ip + 8000624: f000 f8de bleq 80007e4 <__aeabi_dmul+0x1dc> + 8000628: 442c add r4, r5 + 800062a: ea81 0603 eor.w r6, r1, r3 + 800062e: ea21 514c bic.w r1, r1, ip, lsl #21 + 8000632: ea23 534c bic.w r3, r3, ip, lsl #21 + 8000636: ea50 3501 orrs.w r5, r0, r1, lsl #12 + 800063a: bf18 it ne + 800063c: ea52 3503 orrsne.w r5, r2, r3, lsl #12 + 8000640: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 + 8000644: f443 1380 orr.w r3, r3, #1048576 ; 0x100000 + 8000648: d038 beq.n 80006bc <__aeabi_dmul+0xb4> + 800064a: fba0 ce02 umull ip, lr, r0, r2 + 800064e: f04f 0500 mov.w r5, #0 + 8000652: fbe1 e502 umlal lr, r5, r1, r2 + 8000656: f006 4200 and.w r2, r6, #2147483648 ; 0x80000000 + 800065a: fbe0 e503 umlal lr, r5, r0, r3 + 800065e: f04f 0600 mov.w r6, #0 + 8000662: fbe1 5603 umlal r5, r6, r1, r3 + 8000666: f09c 0f00 teq ip, #0 + 800066a: bf18 it ne + 800066c: f04e 0e01 orrne.w lr, lr, #1 + 8000670: f1a4 04ff sub.w r4, r4, #255 ; 0xff + 8000674: f5b6 7f00 cmp.w r6, #512 ; 0x200 + 8000678: f564 7440 sbc.w r4, r4, #768 ; 0x300 + 800067c: d204 bcs.n 8000688 <__aeabi_dmul+0x80> + 800067e: ea5f 0e4e movs.w lr, lr, lsl #1 + 8000682: 416d adcs r5, r5 + 8000684: eb46 0606 adc.w r6, r6, r6 + 8000688: ea42 21c6 orr.w r1, r2, r6, lsl #11 + 800068c: ea41 5155 orr.w r1, r1, r5, lsr #21 + 8000690: ea4f 20c5 mov.w r0, r5, lsl #11 + 8000694: ea40 505e orr.w r0, r0, lr, lsr #21 + 8000698: ea4f 2ece mov.w lr, lr, lsl #11 + 800069c: f1b4 0cfd subs.w ip, r4, #253 ; 0xfd + 80006a0: bf88 it hi + 80006a2: f5bc 6fe0 cmphi.w ip, #1792 ; 0x700 + 80006a6: d81e bhi.n 80006e6 <__aeabi_dmul+0xde> + 80006a8: f1be 4f00 cmp.w lr, #2147483648 ; 0x80000000 + 80006ac: bf08 it eq + 80006ae: ea5f 0e50 movseq.w lr, r0, lsr #1 + 80006b2: f150 0000 adcs.w r0, r0, #0 + 80006b6: eb41 5104 adc.w r1, r1, r4, lsl #20 + 80006ba: bd70 pop {r4, r5, r6, pc} + 80006bc: f006 4600 and.w r6, r6, #2147483648 ; 0x80000000 + 80006c0: ea46 0101 orr.w r1, r6, r1 + 80006c4: ea40 0002 orr.w r0, r0, r2 + 80006c8: ea81 0103 eor.w r1, r1, r3 + 80006cc: ebb4 045c subs.w r4, r4, ip, lsr #1 + 80006d0: bfc2 ittt gt + 80006d2: ebd4 050c rsbsgt r5, r4, ip + 80006d6: ea41 5104 orrgt.w r1, r1, r4, lsl #20 + 80006da: bd70 popgt {r4, r5, r6, pc} + 80006dc: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 + 80006e0: f04f 0e00 mov.w lr, #0 + 80006e4: 3c01 subs r4, #1 + 80006e6: f300 80ab bgt.w 8000840 <__aeabi_dmul+0x238> + 80006ea: f114 0f36 cmn.w r4, #54 ; 0x36 + 80006ee: bfde ittt le + 80006f0: 2000 movle r0, #0 + 80006f2: f001 4100 andle.w r1, r1, #2147483648 ; 0x80000000 + 80006f6: bd70 pople {r4, r5, r6, pc} + 80006f8: f1c4 0400 rsb r4, r4, #0 + 80006fc: 3c20 subs r4, #32 + 80006fe: da35 bge.n 800076c <__aeabi_dmul+0x164> + 8000700: 340c adds r4, #12 + 8000702: dc1b bgt.n 800073c <__aeabi_dmul+0x134> + 8000704: f104 0414 add.w r4, r4, #20 + 8000708: f1c4 0520 rsb r5, r4, #32 + 800070c: fa00 f305 lsl.w r3, r0, r5 + 8000710: fa20 f004 lsr.w r0, r0, r4 + 8000714: fa01 f205 lsl.w r2, r1, r5 + 8000718: ea40 0002 orr.w r0, r0, r2 + 800071c: f001 4200 and.w r2, r1, #2147483648 ; 0x80000000 + 8000720: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000 + 8000724: eb10 70d3 adds.w r0, r0, r3, lsr #31 + 8000728: fa21 f604 lsr.w r6, r1, r4 + 800072c: eb42 0106 adc.w r1, r2, r6 + 8000730: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 + 8000734: bf08 it eq + 8000736: ea20 70d3 biceq.w r0, r0, r3, lsr #31 + 800073a: bd70 pop {r4, r5, r6, pc} + 800073c: f1c4 040c rsb r4, r4, #12 + 8000740: f1c4 0520 rsb r5, r4, #32 + 8000744: fa00 f304 lsl.w r3, r0, r4 + 8000748: fa20 f005 lsr.w r0, r0, r5 + 800074c: fa01 f204 lsl.w r2, r1, r4 + 8000750: ea40 0002 orr.w r0, r0, r2 + 8000754: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 + 8000758: eb10 70d3 adds.w r0, r0, r3, lsr #31 + 800075c: f141 0100 adc.w r1, r1, #0 + 8000760: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 + 8000764: bf08 it eq + 8000766: ea20 70d3 biceq.w r0, r0, r3, lsr #31 + 800076a: bd70 pop {r4, r5, r6, pc} + 800076c: f1c4 0520 rsb r5, r4, #32 + 8000770: fa00 f205 lsl.w r2, r0, r5 + 8000774: ea4e 0e02 orr.w lr, lr, r2 + 8000778: fa20 f304 lsr.w r3, r0, r4 + 800077c: fa01 f205 lsl.w r2, r1, r5 + 8000780: ea43 0302 orr.w r3, r3, r2 + 8000784: fa21 f004 lsr.w r0, r1, r4 + 8000788: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 + 800078c: fa21 f204 lsr.w r2, r1, r4 + 8000790: ea20 0002 bic.w r0, r0, r2 + 8000794: eb00 70d3 add.w r0, r0, r3, lsr #31 + 8000798: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 + 800079c: bf08 it eq + 800079e: ea20 70d3 biceq.w r0, r0, r3, lsr #31 + 80007a2: bd70 pop {r4, r5, r6, pc} + 80007a4: f094 0f00 teq r4, #0 + 80007a8: d10f bne.n 80007ca <__aeabi_dmul+0x1c2> + 80007aa: f001 4600 and.w r6, r1, #2147483648 ; 0x80000000 + 80007ae: 0040 lsls r0, r0, #1 + 80007b0: eb41 0101 adc.w r1, r1, r1 + 80007b4: f411 1f80 tst.w r1, #1048576 ; 0x100000 + 80007b8: bf08 it eq + 80007ba: 3c01 subeq r4, #1 + 80007bc: d0f7 beq.n 80007ae <__aeabi_dmul+0x1a6> + 80007be: ea41 0106 orr.w r1, r1, r6 + 80007c2: f095 0f00 teq r5, #0 + 80007c6: bf18 it ne + 80007c8: 4770 bxne lr + 80007ca: f003 4600 and.w r6, r3, #2147483648 ; 0x80000000 + 80007ce: 0052 lsls r2, r2, #1 + 80007d0: eb43 0303 adc.w r3, r3, r3 + 80007d4: f413 1f80 tst.w r3, #1048576 ; 0x100000 + 80007d8: bf08 it eq + 80007da: 3d01 subeq r5, #1 + 80007dc: d0f7 beq.n 80007ce <__aeabi_dmul+0x1c6> + 80007de: ea43 0306 orr.w r3, r3, r6 + 80007e2: 4770 bx lr + 80007e4: ea94 0f0c teq r4, ip + 80007e8: ea0c 5513 and.w r5, ip, r3, lsr #20 + 80007ec: bf18 it ne + 80007ee: ea95 0f0c teqne r5, ip + 80007f2: d00c beq.n 800080e <__aeabi_dmul+0x206> + 80007f4: ea50 0641 orrs.w r6, r0, r1, lsl #1 + 80007f8: bf18 it ne + 80007fa: ea52 0643 orrsne.w r6, r2, r3, lsl #1 + 80007fe: d1d1 bne.n 80007a4 <__aeabi_dmul+0x19c> + 8000800: ea81 0103 eor.w r1, r1, r3 + 8000804: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 + 8000808: f04f 0000 mov.w r0, #0 + 800080c: bd70 pop {r4, r5, r6, pc} + 800080e: ea50 0641 orrs.w r6, r0, r1, lsl #1 + 8000812: bf06 itte eq + 8000814: 4610 moveq r0, r2 + 8000816: 4619 moveq r1, r3 + 8000818: ea52 0643 orrsne.w r6, r2, r3, lsl #1 + 800081c: d019 beq.n 8000852 <__aeabi_dmul+0x24a> + 800081e: ea94 0f0c teq r4, ip + 8000822: d102 bne.n 800082a <__aeabi_dmul+0x222> + 8000824: ea50 3601 orrs.w r6, r0, r1, lsl #12 + 8000828: d113 bne.n 8000852 <__aeabi_dmul+0x24a> + 800082a: ea95 0f0c teq r5, ip + 800082e: d105 bne.n 800083c <__aeabi_dmul+0x234> + 8000830: ea52 3603 orrs.w r6, r2, r3, lsl #12 + 8000834: bf1c itt ne + 8000836: 4610 movne r0, r2 + 8000838: 4619 movne r1, r3 + 800083a: d10a bne.n 8000852 <__aeabi_dmul+0x24a> + 800083c: ea81 0103 eor.w r1, r1, r3 + 8000840: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 + 8000844: f041 41fe orr.w r1, r1, #2130706432 ; 0x7f000000 + 8000848: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000 + 800084c: f04f 0000 mov.w r0, #0 + 8000850: bd70 pop {r4, r5, r6, pc} + 8000852: f041 41fe orr.w r1, r1, #2130706432 ; 0x7f000000 + 8000856: f441 0178 orr.w r1, r1, #16252928 ; 0xf80000 + 800085a: bd70 pop {r4, r5, r6, pc} + +0800085c <__aeabi_ddiv>: + 800085c: b570 push {r4, r5, r6, lr} + 800085e: f04f 0cff mov.w ip, #255 ; 0xff + 8000862: f44c 6ce0 orr.w ip, ip, #1792 ; 0x700 + 8000866: ea1c 5411 ands.w r4, ip, r1, lsr #20 + 800086a: bf1d ittte ne + 800086c: ea1c 5513 andsne.w r5, ip, r3, lsr #20 + 8000870: ea94 0f0c teqne r4, ip + 8000874: ea95 0f0c teqne r5, ip + 8000878: f000 f8a7 bleq 80009ca <__aeabi_ddiv+0x16e> + 800087c: eba4 0405 sub.w r4, r4, r5 + 8000880: ea81 0e03 eor.w lr, r1, r3 + 8000884: ea52 3503 orrs.w r5, r2, r3, lsl #12 + 8000888: ea4f 3101 mov.w r1, r1, lsl #12 + 800088c: f000 8088 beq.w 80009a0 <__aeabi_ddiv+0x144> + 8000890: ea4f 3303 mov.w r3, r3, lsl #12 + 8000894: f04f 5580 mov.w r5, #268435456 ; 0x10000000 + 8000898: ea45 1313 orr.w r3, r5, r3, lsr #4 + 800089c: ea43 6312 orr.w r3, r3, r2, lsr #24 + 80008a0: ea4f 2202 mov.w r2, r2, lsl #8 + 80008a4: ea45 1511 orr.w r5, r5, r1, lsr #4 + 80008a8: ea45 6510 orr.w r5, r5, r0, lsr #24 + 80008ac: ea4f 2600 mov.w r6, r0, lsl #8 + 80008b0: f00e 4100 and.w r1, lr, #2147483648 ; 0x80000000 + 80008b4: 429d cmp r5, r3 + 80008b6: bf08 it eq + 80008b8: 4296 cmpeq r6, r2 + 80008ba: f144 04fd adc.w r4, r4, #253 ; 0xfd + 80008be: f504 7440 add.w r4, r4, #768 ; 0x300 + 80008c2: d202 bcs.n 80008ca <__aeabi_ddiv+0x6e> + 80008c4: 085b lsrs r3, r3, #1 + 80008c6: ea4f 0232 mov.w r2, r2, rrx + 80008ca: 1ab6 subs r6, r6, r2 + 80008cc: eb65 0503 sbc.w r5, r5, r3 + 80008d0: 085b lsrs r3, r3, #1 + 80008d2: ea4f 0232 mov.w r2, r2, rrx + 80008d6: f44f 1080 mov.w r0, #1048576 ; 0x100000 + 80008da: f44f 2c00 mov.w ip, #524288 ; 0x80000 + 80008de: ebb6 0e02 subs.w lr, r6, r2 + 80008e2: eb75 0e03 sbcs.w lr, r5, r3 + 80008e6: bf22 ittt cs + 80008e8: 1ab6 subcs r6, r6, r2 + 80008ea: 4675 movcs r5, lr + 80008ec: ea40 000c orrcs.w r0, r0, ip + 80008f0: 085b lsrs r3, r3, #1 + 80008f2: ea4f 0232 mov.w r2, r2, rrx + 80008f6: ebb6 0e02 subs.w lr, r6, r2 + 80008fa: eb75 0e03 sbcs.w lr, r5, r3 + 80008fe: bf22 ittt cs + 8000900: 1ab6 subcs r6, r6, r2 + 8000902: 4675 movcs r5, lr + 8000904: ea40 005c orrcs.w r0, r0, ip, lsr #1 + 8000908: 085b lsrs r3, r3, #1 + 800090a: ea4f 0232 mov.w r2, r2, rrx + 800090e: ebb6 0e02 subs.w lr, r6, r2 + 8000912: eb75 0e03 sbcs.w lr, r5, r3 + 8000916: bf22 ittt cs + 8000918: 1ab6 subcs r6, r6, r2 + 800091a: 4675 movcs r5, lr + 800091c: ea40 009c orrcs.w r0, r0, ip, lsr #2 + 8000920: 085b lsrs r3, r3, #1 + 8000922: ea4f 0232 mov.w r2, r2, rrx + 8000926: ebb6 0e02 subs.w lr, r6, r2 + 800092a: eb75 0e03 sbcs.w lr, r5, r3 + 800092e: bf22 ittt cs + 8000930: 1ab6 subcs r6, r6, r2 + 8000932: 4675 movcs r5, lr + 8000934: ea40 00dc orrcs.w r0, r0, ip, lsr #3 + 8000938: ea55 0e06 orrs.w lr, r5, r6 + 800093c: d018 beq.n 8000970 <__aeabi_ddiv+0x114> + 800093e: ea4f 1505 mov.w r5, r5, lsl #4 + 8000942: ea45 7516 orr.w r5, r5, r6, lsr #28 + 8000946: ea4f 1606 mov.w r6, r6, lsl #4 + 800094a: ea4f 03c3 mov.w r3, r3, lsl #3 + 800094e: ea43 7352 orr.w r3, r3, r2, lsr #29 + 8000952: ea4f 02c2 mov.w r2, r2, lsl #3 + 8000956: ea5f 1c1c movs.w ip, ip, lsr #4 + 800095a: d1c0 bne.n 80008de <__aeabi_ddiv+0x82> + 800095c: f411 1f80 tst.w r1, #1048576 ; 0x100000 + 8000960: d10b bne.n 800097a <__aeabi_ddiv+0x11e> + 8000962: ea41 0100 orr.w r1, r1, r0 + 8000966: f04f 0000 mov.w r0, #0 + 800096a: f04f 4c00 mov.w ip, #2147483648 ; 0x80000000 + 800096e: e7b6 b.n 80008de <__aeabi_ddiv+0x82> + 8000970: f411 1f80 tst.w r1, #1048576 ; 0x100000 + 8000974: bf04 itt eq + 8000976: 4301 orreq r1, r0 + 8000978: 2000 moveq r0, #0 + 800097a: f1b4 0cfd subs.w ip, r4, #253 ; 0xfd + 800097e: bf88 it hi + 8000980: f5bc 6fe0 cmphi.w ip, #1792 ; 0x700 + 8000984: f63f aeaf bhi.w 80006e6 <__aeabi_dmul+0xde> + 8000988: ebb5 0c03 subs.w ip, r5, r3 + 800098c: bf04 itt eq + 800098e: ebb6 0c02 subseq.w ip, r6, r2 + 8000992: ea5f 0c50 movseq.w ip, r0, lsr #1 + 8000996: f150 0000 adcs.w r0, r0, #0 + 800099a: eb41 5104 adc.w r1, r1, r4, lsl #20 + 800099e: bd70 pop {r4, r5, r6, pc} + 80009a0: f00e 4e00 and.w lr, lr, #2147483648 ; 0x80000000 + 80009a4: ea4e 3111 orr.w r1, lr, r1, lsr #12 + 80009a8: eb14 045c adds.w r4, r4, ip, lsr #1 + 80009ac: bfc2 ittt gt + 80009ae: ebd4 050c rsbsgt r5, r4, ip + 80009b2: ea41 5104 orrgt.w r1, r1, r4, lsl #20 + 80009b6: bd70 popgt {r4, r5, r6, pc} + 80009b8: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 + 80009bc: f04f 0e00 mov.w lr, #0 + 80009c0: 3c01 subs r4, #1 + 80009c2: e690 b.n 80006e6 <__aeabi_dmul+0xde> + 80009c4: ea45 0e06 orr.w lr, r5, r6 + 80009c8: e68d b.n 80006e6 <__aeabi_dmul+0xde> + 80009ca: ea0c 5513 and.w r5, ip, r3, lsr #20 + 80009ce: ea94 0f0c teq r4, ip + 80009d2: bf08 it eq + 80009d4: ea95 0f0c teqeq r5, ip + 80009d8: f43f af3b beq.w 8000852 <__aeabi_dmul+0x24a> + 80009dc: ea94 0f0c teq r4, ip + 80009e0: d10a bne.n 80009f8 <__aeabi_ddiv+0x19c> + 80009e2: ea50 3401 orrs.w r4, r0, r1, lsl #12 + 80009e6: f47f af34 bne.w 8000852 <__aeabi_dmul+0x24a> + 80009ea: ea95 0f0c teq r5, ip + 80009ee: f47f af25 bne.w 800083c <__aeabi_dmul+0x234> + 80009f2: 4610 mov r0, r2 + 80009f4: 4619 mov r1, r3 + 80009f6: e72c b.n 8000852 <__aeabi_dmul+0x24a> + 80009f8: ea95 0f0c teq r5, ip + 80009fc: d106 bne.n 8000a0c <__aeabi_ddiv+0x1b0> + 80009fe: ea52 3503 orrs.w r5, r2, r3, lsl #12 + 8000a02: f43f aefd beq.w 8000800 <__aeabi_dmul+0x1f8> + 8000a06: 4610 mov r0, r2 + 8000a08: 4619 mov r1, r3 + 8000a0a: e722 b.n 8000852 <__aeabi_dmul+0x24a> + 8000a0c: ea50 0641 orrs.w r6, r0, r1, lsl #1 + 8000a10: bf18 it ne + 8000a12: ea52 0643 orrsne.w r6, r2, r3, lsl #1 + 8000a16: f47f aec5 bne.w 80007a4 <__aeabi_dmul+0x19c> + 8000a1a: ea50 0441 orrs.w r4, r0, r1, lsl #1 + 8000a1e: f47f af0d bne.w 800083c <__aeabi_dmul+0x234> + 8000a22: ea52 0543 orrs.w r5, r2, r3, lsl #1 + 8000a26: f47f aeeb bne.w 8000800 <__aeabi_dmul+0x1f8> + 8000a2a: e712 b.n 8000852 <__aeabi_dmul+0x24a> + +08000a2c <__gedf2>: + 8000a2c: f04f 3cff mov.w ip, #4294967295 + 8000a30: e006 b.n 8000a40 <__cmpdf2+0x4> + 8000a32: bf00 nop + +08000a34 <__ledf2>: + 8000a34: f04f 0c01 mov.w ip, #1 + 8000a38: e002 b.n 8000a40 <__cmpdf2+0x4> + 8000a3a: bf00 nop + +08000a3c <__cmpdf2>: + 8000a3c: f04f 0c01 mov.w ip, #1 + 8000a40: f84d cd04 str.w ip, [sp, #-4]! + 8000a44: ea4f 0c41 mov.w ip, r1, lsl #1 + 8000a48: ea7f 5c6c mvns.w ip, ip, asr #21 + 8000a4c: ea4f 0c43 mov.w ip, r3, lsl #1 + 8000a50: bf18 it ne + 8000a52: ea7f 5c6c mvnsne.w ip, ip, asr #21 + 8000a56: d01b beq.n 8000a90 <__cmpdf2+0x54> + 8000a58: b001 add sp, #4 + 8000a5a: ea50 0c41 orrs.w ip, r0, r1, lsl #1 + 8000a5e: bf0c ite eq + 8000a60: ea52 0c43 orrseq.w ip, r2, r3, lsl #1 + 8000a64: ea91 0f03 teqne r1, r3 + 8000a68: bf02 ittt eq + 8000a6a: ea90 0f02 teqeq r0, r2 + 8000a6e: 2000 moveq r0, #0 + 8000a70: 4770 bxeq lr + 8000a72: f110 0f00 cmn.w r0, #0 + 8000a76: ea91 0f03 teq r1, r3 + 8000a7a: bf58 it pl + 8000a7c: 4299 cmppl r1, r3 + 8000a7e: bf08 it eq + 8000a80: 4290 cmpeq r0, r2 + 8000a82: bf2c ite cs + 8000a84: 17d8 asrcs r0, r3, #31 + 8000a86: ea6f 70e3 mvncc.w r0, r3, asr #31 + 8000a8a: f040 0001 orr.w r0, r0, #1 + 8000a8e: 4770 bx lr + 8000a90: ea4f 0c41 mov.w ip, r1, lsl #1 + 8000a94: ea7f 5c6c mvns.w ip, ip, asr #21 + 8000a98: d102 bne.n 8000aa0 <__cmpdf2+0x64> + 8000a9a: ea50 3c01 orrs.w ip, r0, r1, lsl #12 + 8000a9e: d107 bne.n 8000ab0 <__cmpdf2+0x74> + 8000aa0: ea4f 0c43 mov.w ip, r3, lsl #1 + 8000aa4: ea7f 5c6c mvns.w ip, ip, asr #21 + 8000aa8: d1d6 bne.n 8000a58 <__cmpdf2+0x1c> + 8000aaa: ea52 3c03 orrs.w ip, r2, r3, lsl #12 + 8000aae: d0d3 beq.n 8000a58 <__cmpdf2+0x1c> + 8000ab0: f85d 0b04 ldr.w r0, [sp], #4 + 8000ab4: 4770 bx lr + 8000ab6: bf00 nop + +08000ab8 <__aeabi_cdrcmple>: + 8000ab8: 4684 mov ip, r0 + 8000aba: 4610 mov r0, r2 + 8000abc: 4662 mov r2, ip + 8000abe: 468c mov ip, r1 + 8000ac0: 4619 mov r1, r3 + 8000ac2: 4663 mov r3, ip + 8000ac4: e000 b.n 8000ac8 <__aeabi_cdcmpeq> + 8000ac6: bf00 nop + +08000ac8 <__aeabi_cdcmpeq>: + 8000ac8: b501 push {r0, lr} + 8000aca: f7ff ffb7 bl 8000a3c <__cmpdf2> + 8000ace: 2800 cmp r0, #0 + 8000ad0: bf48 it mi + 8000ad2: f110 0f00 cmnmi.w r0, #0 + 8000ad6: bd01 pop {r0, pc} + +08000ad8 <__aeabi_dcmpeq>: + 8000ad8: f84d ed08 str.w lr, [sp, #-8]! + 8000adc: f7ff fff4 bl 8000ac8 <__aeabi_cdcmpeq> + 8000ae0: bf0c ite eq + 8000ae2: 2001 moveq r0, #1 + 8000ae4: 2000 movne r0, #0 + 8000ae6: f85d fb08 ldr.w pc, [sp], #8 + 8000aea: bf00 nop + +08000aec <__aeabi_dcmplt>: + 8000aec: f84d ed08 str.w lr, [sp, #-8]! + 8000af0: f7ff ffea bl 8000ac8 <__aeabi_cdcmpeq> + 8000af4: bf34 ite cc + 8000af6: 2001 movcc r0, #1 + 8000af8: 2000 movcs r0, #0 + 8000afa: f85d fb08 ldr.w pc, [sp], #8 + 8000afe: bf00 nop + +08000b00 <__aeabi_dcmple>: + 8000b00: f84d ed08 str.w lr, [sp, #-8]! + 8000b04: f7ff ffe0 bl 8000ac8 <__aeabi_cdcmpeq> + 8000b08: bf94 ite ls + 8000b0a: 2001 movls r0, #1 + 8000b0c: 2000 movhi r0, #0 + 8000b0e: f85d fb08 ldr.w pc, [sp], #8 + 8000b12: bf00 nop + +08000b14 <__aeabi_dcmpge>: + 8000b14: f84d ed08 str.w lr, [sp, #-8]! + 8000b18: f7ff ffce bl 8000ab8 <__aeabi_cdrcmple> + 8000b1c: bf94 ite ls + 8000b1e: 2001 movls r0, #1 + 8000b20: 2000 movhi r0, #0 + 8000b22: f85d fb08 ldr.w pc, [sp], #8 + 8000b26: bf00 nop + +08000b28 <__aeabi_dcmpgt>: + 8000b28: f84d ed08 str.w lr, [sp, #-8]! + 8000b2c: f7ff ffc4 bl 8000ab8 <__aeabi_cdrcmple> + 8000b30: bf34 ite cc + 8000b32: 2001 movcc r0, #1 + 8000b34: 2000 movcs r0, #0 + 8000b36: f85d fb08 ldr.w pc, [sp], #8 + 8000b3a: bf00 nop + +08000b3c <__aeabi_dcmpun>: + 8000b3c: ea4f 0c41 mov.w ip, r1, lsl #1 + 8000b40: ea7f 5c6c mvns.w ip, ip, asr #21 + 8000b44: d102 bne.n 8000b4c <__aeabi_dcmpun+0x10> + 8000b46: ea50 3c01 orrs.w ip, r0, r1, lsl #12 + 8000b4a: d10a bne.n 8000b62 <__aeabi_dcmpun+0x26> + 8000b4c: ea4f 0c43 mov.w ip, r3, lsl #1 + 8000b50: ea7f 5c6c mvns.w ip, ip, asr #21 + 8000b54: d102 bne.n 8000b5c <__aeabi_dcmpun+0x20> + 8000b56: ea52 3c03 orrs.w ip, r2, r3, lsl #12 + 8000b5a: d102 bne.n 8000b62 <__aeabi_dcmpun+0x26> + 8000b5c: f04f 0000 mov.w r0, #0 + 8000b60: 4770 bx lr + 8000b62: f04f 0001 mov.w r0, #1 + 8000b66: 4770 bx lr + +08000b68 <__aeabi_d2iz>: + 8000b68: ea4f 0241 mov.w r2, r1, lsl #1 + 8000b6c: f512 1200 adds.w r2, r2, #2097152 ; 0x200000 + 8000b70: d215 bcs.n 8000b9e <__aeabi_d2iz+0x36> + 8000b72: d511 bpl.n 8000b98 <__aeabi_d2iz+0x30> + 8000b74: f46f 7378 mvn.w r3, #992 ; 0x3e0 + 8000b78: ebb3 5262 subs.w r2, r3, r2, asr #21 + 8000b7c: d912 bls.n 8000ba4 <__aeabi_d2iz+0x3c> + 8000b7e: ea4f 23c1 mov.w r3, r1, lsl #11 + 8000b82: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 + 8000b86: ea43 5350 orr.w r3, r3, r0, lsr #21 + 8000b8a: f011 4f00 tst.w r1, #2147483648 ; 0x80000000 + 8000b8e: fa23 f002 lsr.w r0, r3, r2 + 8000b92: bf18 it ne + 8000b94: 4240 negne r0, r0 + 8000b96: 4770 bx lr + 8000b98: f04f 0000 mov.w r0, #0 + 8000b9c: 4770 bx lr + 8000b9e: ea50 3001 orrs.w r0, r0, r1, lsl #12 + 8000ba2: d105 bne.n 8000bb0 <__aeabi_d2iz+0x48> + 8000ba4: f011 4000 ands.w r0, r1, #2147483648 ; 0x80000000 + 8000ba8: bf08 it eq + 8000baa: f06f 4000 mvneq.w r0, #2147483648 ; 0x80000000 + 8000bae: 4770 bx lr + 8000bb0: f04f 0000 mov.w r0, #0 + 8000bb4: 4770 bx lr + 8000bb6: bf00 nop + +08000bb8 <__aeabi_d2uiz>: + 8000bb8: 004a lsls r2, r1, #1 + 8000bba: d211 bcs.n 8000be0 <__aeabi_d2uiz+0x28> + 8000bbc: f512 1200 adds.w r2, r2, #2097152 ; 0x200000 + 8000bc0: d211 bcs.n 8000be6 <__aeabi_d2uiz+0x2e> + 8000bc2: d50d bpl.n 8000be0 <__aeabi_d2uiz+0x28> + 8000bc4: f46f 7378 mvn.w r3, #992 ; 0x3e0 + 8000bc8: ebb3 5262 subs.w r2, r3, r2, asr #21 + 8000bcc: d40e bmi.n 8000bec <__aeabi_d2uiz+0x34> + 8000bce: ea4f 23c1 mov.w r3, r1, lsl #11 + 8000bd2: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 + 8000bd6: ea43 5350 orr.w r3, r3, r0, lsr #21 + 8000bda: fa23 f002 lsr.w r0, r3, r2 + 8000bde: 4770 bx lr + 8000be0: f04f 0000 mov.w r0, #0 + 8000be4: 4770 bx lr + 8000be6: ea50 3001 orrs.w r0, r0, r1, lsl #12 + 8000bea: d102 bne.n 8000bf2 <__aeabi_d2uiz+0x3a> + 8000bec: f04f 30ff mov.w r0, #4294967295 + 8000bf0: 4770 bx lr + 8000bf2: f04f 0000 mov.w r0, #0 + 8000bf6: 4770 bx lr + +08000bf8 <__aeabi_d2f>: + 8000bf8: ea4f 0241 mov.w r2, r1, lsl #1 + 8000bfc: f1b2 43e0 subs.w r3, r2, #1879048192 ; 0x70000000 + 8000c00: bf24 itt cs + 8000c02: f5b3 1c00 subscs.w ip, r3, #2097152 ; 0x200000 + 8000c06: f1dc 5cfe rsbscs ip, ip, #532676608 ; 0x1fc00000 + 8000c0a: d90d bls.n 8000c28 <__aeabi_d2f+0x30> + 8000c0c: f001 4c00 and.w ip, r1, #2147483648 ; 0x80000000 + 8000c10: ea4f 02c0 mov.w r2, r0, lsl #3 + 8000c14: ea4c 7050 orr.w r0, ip, r0, lsr #29 + 8000c18: f1b2 4f00 cmp.w r2, #2147483648 ; 0x80000000 + 8000c1c: eb40 0083 adc.w r0, r0, r3, lsl #2 + 8000c20: bf08 it eq + 8000c22: f020 0001 biceq.w r0, r0, #1 + 8000c26: 4770 bx lr + 8000c28: f011 4f80 tst.w r1, #1073741824 ; 0x40000000 + 8000c2c: d121 bne.n 8000c72 <__aeabi_d2f+0x7a> + 8000c2e: f113 7238 adds.w r2, r3, #48234496 ; 0x2e00000 + 8000c32: bfbc itt lt + 8000c34: f001 4000 andlt.w r0, r1, #2147483648 ; 0x80000000 + 8000c38: 4770 bxlt lr + 8000c3a: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 + 8000c3e: ea4f 5252 mov.w r2, r2, lsr #21 + 8000c42: f1c2 0218 rsb r2, r2, #24 + 8000c46: f1c2 0c20 rsb ip, r2, #32 + 8000c4a: fa10 f30c lsls.w r3, r0, ip + 8000c4e: fa20 f002 lsr.w r0, r0, r2 + 8000c52: bf18 it ne + 8000c54: f040 0001 orrne.w r0, r0, #1 + 8000c58: ea4f 23c1 mov.w r3, r1, lsl #11 + 8000c5c: ea4f 23d3 mov.w r3, r3, lsr #11 + 8000c60: fa03 fc0c lsl.w ip, r3, ip + 8000c64: ea40 000c orr.w r0, r0, ip + 8000c68: fa23 f302 lsr.w r3, r3, r2 + 8000c6c: ea4f 0343 mov.w r3, r3, lsl #1 + 8000c70: e7cc b.n 8000c0c <__aeabi_d2f+0x14> + 8000c72: ea7f 5362 mvns.w r3, r2, asr #21 + 8000c76: d107 bne.n 8000c88 <__aeabi_d2f+0x90> + 8000c78: ea50 3301 orrs.w r3, r0, r1, lsl #12 + 8000c7c: bf1e ittt ne + 8000c7e: f04f 40fe movne.w r0, #2130706432 ; 0x7f000000 + 8000c82: f440 0040 orrne.w r0, r0, #12582912 ; 0xc00000 + 8000c86: 4770 bxne lr + 8000c88: f001 4000 and.w r0, r1, #2147483648 ; 0x80000000 + 8000c8c: f040 40fe orr.w r0, r0, #2130706432 ; 0x7f000000 + 8000c90: f440 0000 orr.w r0, r0, #8388608 ; 0x800000 + 8000c94: 4770 bx lr + 8000c96: bf00 nop + +08000c98 <__aeabi_uldivmod>: + 8000c98: b953 cbnz r3, 8000cb0 <__aeabi_uldivmod+0x18> + 8000c9a: b94a cbnz r2, 8000cb0 <__aeabi_uldivmod+0x18> + 8000c9c: 2900 cmp r1, #0 + 8000c9e: bf08 it eq + 8000ca0: 2800 cmpeq r0, #0 + 8000ca2: bf1c itt ne + 8000ca4: f04f 31ff movne.w r1, #4294967295 + 8000ca8: f04f 30ff movne.w r0, #4294967295 + 8000cac: f000 b972 b.w 8000f94 <__aeabi_idiv0> + 8000cb0: f1ad 0c08 sub.w ip, sp, #8 + 8000cb4: e96d ce04 strd ip, lr, [sp, #-16]! + 8000cb8: f000 f806 bl 8000cc8 <__udivmoddi4> + 8000cbc: f8dd e004 ldr.w lr, [sp, #4] + 8000cc0: e9dd 2302 ldrd r2, r3, [sp, #8] + 8000cc4: b004 add sp, #16 + 8000cc6: 4770 bx lr + +08000cc8 <__udivmoddi4>: + 8000cc8: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 8000ccc: 9e08 ldr r6, [sp, #32] + 8000cce: 4604 mov r4, r0 + 8000cd0: 4688 mov r8, r1 + 8000cd2: 2b00 cmp r3, #0 + 8000cd4: d14b bne.n 8000d6e <__udivmoddi4+0xa6> + 8000cd6: 428a cmp r2, r1 + 8000cd8: 4615 mov r5, r2 + 8000cda: d967 bls.n 8000dac <__udivmoddi4+0xe4> + 8000cdc: fab2 f282 clz r2, r2 + 8000ce0: b14a cbz r2, 8000cf6 <__udivmoddi4+0x2e> + 8000ce2: f1c2 0720 rsb r7, r2, #32 + 8000ce6: fa01 f302 lsl.w r3, r1, r2 + 8000cea: fa20 f707 lsr.w r7, r0, r7 + 8000cee: 4095 lsls r5, r2 + 8000cf0: ea47 0803 orr.w r8, r7, r3 + 8000cf4: 4094 lsls r4, r2 + 8000cf6: ea4f 4e15 mov.w lr, r5, lsr #16 + 8000cfa: 0c23 lsrs r3, r4, #16 + 8000cfc: fbb8 f7fe udiv r7, r8, lr + 8000d00: fa1f fc85 uxth.w ip, r5 + 8000d04: fb0e 8817 mls r8, lr, r7, r8 + 8000d08: ea43 4308 orr.w r3, r3, r8, lsl #16 + 8000d0c: fb07 f10c mul.w r1, r7, ip + 8000d10: 4299 cmp r1, r3 + 8000d12: d909 bls.n 8000d28 <__udivmoddi4+0x60> + 8000d14: 18eb adds r3, r5, r3 + 8000d16: f107 30ff add.w r0, r7, #4294967295 + 8000d1a: f080 811b bcs.w 8000f54 <__udivmoddi4+0x28c> + 8000d1e: 4299 cmp r1, r3 + 8000d20: f240 8118 bls.w 8000f54 <__udivmoddi4+0x28c> + 8000d24: 3f02 subs r7, #2 + 8000d26: 442b add r3, r5 + 8000d28: 1a5b subs r3, r3, r1 + 8000d2a: b2a4 uxth r4, r4 + 8000d2c: fbb3 f0fe udiv r0, r3, lr + 8000d30: fb0e 3310 mls r3, lr, r0, r3 + 8000d34: ea44 4403 orr.w r4, r4, r3, lsl #16 + 8000d38: fb00 fc0c mul.w ip, r0, ip + 8000d3c: 45a4 cmp ip, r4 + 8000d3e: d909 bls.n 8000d54 <__udivmoddi4+0x8c> + 8000d40: 192c adds r4, r5, r4 + 8000d42: f100 33ff add.w r3, r0, #4294967295 + 8000d46: f080 8107 bcs.w 8000f58 <__udivmoddi4+0x290> + 8000d4a: 45a4 cmp ip, r4 + 8000d4c: f240 8104 bls.w 8000f58 <__udivmoddi4+0x290> + 8000d50: 3802 subs r0, #2 + 8000d52: 442c add r4, r5 + 8000d54: ea40 4007 orr.w r0, r0, r7, lsl #16 + 8000d58: eba4 040c sub.w r4, r4, ip + 8000d5c: 2700 movs r7, #0 + 8000d5e: b11e cbz r6, 8000d68 <__udivmoddi4+0xa0> + 8000d60: 40d4 lsrs r4, r2 + 8000d62: 2300 movs r3, #0 + 8000d64: e9c6 4300 strd r4, r3, [r6] + 8000d68: 4639 mov r1, r7 + 8000d6a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 8000d6e: 428b cmp r3, r1 + 8000d70: d909 bls.n 8000d86 <__udivmoddi4+0xbe> + 8000d72: 2e00 cmp r6, #0 + 8000d74: f000 80eb beq.w 8000f4e <__udivmoddi4+0x286> + 8000d78: 2700 movs r7, #0 + 8000d7a: e9c6 0100 strd r0, r1, [r6] + 8000d7e: 4638 mov r0, r7 + 8000d80: 4639 mov r1, r7 + 8000d82: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 8000d86: fab3 f783 clz r7, r3 + 8000d8a: 2f00 cmp r7, #0 + 8000d8c: d147 bne.n 8000e1e <__udivmoddi4+0x156> + 8000d8e: 428b cmp r3, r1 + 8000d90: d302 bcc.n 8000d98 <__udivmoddi4+0xd0> + 8000d92: 4282 cmp r2, r0 + 8000d94: f200 80fa bhi.w 8000f8c <__udivmoddi4+0x2c4> + 8000d98: 1a84 subs r4, r0, r2 + 8000d9a: eb61 0303 sbc.w r3, r1, r3 + 8000d9e: 2001 movs r0, #1 + 8000da0: 4698 mov r8, r3 + 8000da2: 2e00 cmp r6, #0 + 8000da4: d0e0 beq.n 8000d68 <__udivmoddi4+0xa0> + 8000da6: e9c6 4800 strd r4, r8, [r6] + 8000daa: e7dd b.n 8000d68 <__udivmoddi4+0xa0> + 8000dac: b902 cbnz r2, 8000db0 <__udivmoddi4+0xe8> + 8000dae: deff udf #255 ; 0xff + 8000db0: fab2 f282 clz r2, r2 + 8000db4: 2a00 cmp r2, #0 + 8000db6: f040 808f bne.w 8000ed8 <__udivmoddi4+0x210> + 8000dba: 1b49 subs r1, r1, r5 + 8000dbc: ea4f 4e15 mov.w lr, r5, lsr #16 + 8000dc0: fa1f f885 uxth.w r8, r5 + 8000dc4: 2701 movs r7, #1 + 8000dc6: fbb1 fcfe udiv ip, r1, lr + 8000dca: 0c23 lsrs r3, r4, #16 + 8000dcc: fb0e 111c mls r1, lr, ip, r1 + 8000dd0: ea43 4301 orr.w r3, r3, r1, lsl #16 + 8000dd4: fb08 f10c mul.w r1, r8, ip + 8000dd8: 4299 cmp r1, r3 + 8000dda: d907 bls.n 8000dec <__udivmoddi4+0x124> + 8000ddc: 18eb adds r3, r5, r3 + 8000dde: f10c 30ff add.w r0, ip, #4294967295 + 8000de2: d202 bcs.n 8000dea <__udivmoddi4+0x122> + 8000de4: 4299 cmp r1, r3 + 8000de6: f200 80cd bhi.w 8000f84 <__udivmoddi4+0x2bc> + 8000dea: 4684 mov ip, r0 + 8000dec: 1a59 subs r1, r3, r1 + 8000dee: b2a3 uxth r3, r4 + 8000df0: fbb1 f0fe udiv r0, r1, lr + 8000df4: fb0e 1410 mls r4, lr, r0, r1 + 8000df8: ea43 4404 orr.w r4, r3, r4, lsl #16 + 8000dfc: fb08 f800 mul.w r8, r8, r0 + 8000e00: 45a0 cmp r8, r4 + 8000e02: d907 bls.n 8000e14 <__udivmoddi4+0x14c> + 8000e04: 192c adds r4, r5, r4 + 8000e06: f100 33ff add.w r3, r0, #4294967295 + 8000e0a: d202 bcs.n 8000e12 <__udivmoddi4+0x14a> + 8000e0c: 45a0 cmp r8, r4 + 8000e0e: f200 80b6 bhi.w 8000f7e <__udivmoddi4+0x2b6> + 8000e12: 4618 mov r0, r3 + 8000e14: eba4 0408 sub.w r4, r4, r8 + 8000e18: ea40 400c orr.w r0, r0, ip, lsl #16 + 8000e1c: e79f b.n 8000d5e <__udivmoddi4+0x96> + 8000e1e: f1c7 0c20 rsb ip, r7, #32 + 8000e22: 40bb lsls r3, r7 + 8000e24: fa22 fe0c lsr.w lr, r2, ip + 8000e28: ea4e 0e03 orr.w lr, lr, r3 + 8000e2c: fa01 f407 lsl.w r4, r1, r7 + 8000e30: fa20 f50c lsr.w r5, r0, ip + 8000e34: fa21 f30c lsr.w r3, r1, ip + 8000e38: ea4f 481e mov.w r8, lr, lsr #16 + 8000e3c: 4325 orrs r5, r4 + 8000e3e: fbb3 f9f8 udiv r9, r3, r8 + 8000e42: 0c2c lsrs r4, r5, #16 + 8000e44: fb08 3319 mls r3, r8, r9, r3 + 8000e48: fa1f fa8e uxth.w sl, lr + 8000e4c: ea44 4303 orr.w r3, r4, r3, lsl #16 + 8000e50: fb09 f40a mul.w r4, r9, sl + 8000e54: 429c cmp r4, r3 + 8000e56: fa02 f207 lsl.w r2, r2, r7 + 8000e5a: fa00 f107 lsl.w r1, r0, r7 + 8000e5e: d90b bls.n 8000e78 <__udivmoddi4+0x1b0> + 8000e60: eb1e 0303 adds.w r3, lr, r3 + 8000e64: f109 30ff add.w r0, r9, #4294967295 + 8000e68: f080 8087 bcs.w 8000f7a <__udivmoddi4+0x2b2> + 8000e6c: 429c cmp r4, r3 + 8000e6e: f240 8084 bls.w 8000f7a <__udivmoddi4+0x2b2> + 8000e72: f1a9 0902 sub.w r9, r9, #2 + 8000e76: 4473 add r3, lr + 8000e78: 1b1b subs r3, r3, r4 + 8000e7a: b2ad uxth r5, r5 + 8000e7c: fbb3 f0f8 udiv r0, r3, r8 + 8000e80: fb08 3310 mls r3, r8, r0, r3 + 8000e84: ea45 4403 orr.w r4, r5, r3, lsl #16 + 8000e88: fb00 fa0a mul.w sl, r0, sl + 8000e8c: 45a2 cmp sl, r4 + 8000e8e: d908 bls.n 8000ea2 <__udivmoddi4+0x1da> + 8000e90: eb1e 0404 adds.w r4, lr, r4 + 8000e94: f100 33ff add.w r3, r0, #4294967295 + 8000e98: d26b bcs.n 8000f72 <__udivmoddi4+0x2aa> + 8000e9a: 45a2 cmp sl, r4 + 8000e9c: d969 bls.n 8000f72 <__udivmoddi4+0x2aa> + 8000e9e: 3802 subs r0, #2 + 8000ea0: 4474 add r4, lr + 8000ea2: ea40 4009 orr.w r0, r0, r9, lsl #16 + 8000ea6: fba0 8902 umull r8, r9, r0, r2 + 8000eaa: eba4 040a sub.w r4, r4, sl + 8000eae: 454c cmp r4, r9 + 8000eb0: 46c2 mov sl, r8 + 8000eb2: 464b mov r3, r9 + 8000eb4: d354 bcc.n 8000f60 <__udivmoddi4+0x298> + 8000eb6: d051 beq.n 8000f5c <__udivmoddi4+0x294> + 8000eb8: 2e00 cmp r6, #0 + 8000eba: d069 beq.n 8000f90 <__udivmoddi4+0x2c8> + 8000ebc: ebb1 050a subs.w r5, r1, sl + 8000ec0: eb64 0403 sbc.w r4, r4, r3 + 8000ec4: fa04 fc0c lsl.w ip, r4, ip + 8000ec8: 40fd lsrs r5, r7 + 8000eca: 40fc lsrs r4, r7 + 8000ecc: ea4c 0505 orr.w r5, ip, r5 + 8000ed0: e9c6 5400 strd r5, r4, [r6] + 8000ed4: 2700 movs r7, #0 + 8000ed6: e747 b.n 8000d68 <__udivmoddi4+0xa0> + 8000ed8: f1c2 0320 rsb r3, r2, #32 + 8000edc: fa20 f703 lsr.w r7, r0, r3 + 8000ee0: 4095 lsls r5, r2 + 8000ee2: fa01 f002 lsl.w r0, r1, r2 + 8000ee6: fa21 f303 lsr.w r3, r1, r3 + 8000eea: ea4f 4e15 mov.w lr, r5, lsr #16 + 8000eee: 4338 orrs r0, r7 + 8000ef0: 0c01 lsrs r1, r0, #16 + 8000ef2: fbb3 f7fe udiv r7, r3, lr + 8000ef6: fa1f f885 uxth.w r8, r5 + 8000efa: fb0e 3317 mls r3, lr, r7, r3 + 8000efe: ea41 4103 orr.w r1, r1, r3, lsl #16 + 8000f02: fb07 f308 mul.w r3, r7, r8 + 8000f06: 428b cmp r3, r1 + 8000f08: fa04 f402 lsl.w r4, r4, r2 + 8000f0c: d907 bls.n 8000f1e <__udivmoddi4+0x256> + 8000f0e: 1869 adds r1, r5, r1 + 8000f10: f107 3cff add.w ip, r7, #4294967295 + 8000f14: d22f bcs.n 8000f76 <__udivmoddi4+0x2ae> + 8000f16: 428b cmp r3, r1 + 8000f18: d92d bls.n 8000f76 <__udivmoddi4+0x2ae> + 8000f1a: 3f02 subs r7, #2 + 8000f1c: 4429 add r1, r5 + 8000f1e: 1acb subs r3, r1, r3 + 8000f20: b281 uxth r1, r0 + 8000f22: fbb3 f0fe udiv r0, r3, lr + 8000f26: fb0e 3310 mls r3, lr, r0, r3 + 8000f2a: ea41 4103 orr.w r1, r1, r3, lsl #16 + 8000f2e: fb00 f308 mul.w r3, r0, r8 + 8000f32: 428b cmp r3, r1 + 8000f34: d907 bls.n 8000f46 <__udivmoddi4+0x27e> + 8000f36: 1869 adds r1, r5, r1 + 8000f38: f100 3cff add.w ip, r0, #4294967295 + 8000f3c: d217 bcs.n 8000f6e <__udivmoddi4+0x2a6> + 8000f3e: 428b cmp r3, r1 + 8000f40: d915 bls.n 8000f6e <__udivmoddi4+0x2a6> + 8000f42: 3802 subs r0, #2 + 8000f44: 4429 add r1, r5 + 8000f46: 1ac9 subs r1, r1, r3 + 8000f48: ea40 4707 orr.w r7, r0, r7, lsl #16 + 8000f4c: e73b b.n 8000dc6 <__udivmoddi4+0xfe> + 8000f4e: 4637 mov r7, r6 + 8000f50: 4630 mov r0, r6 + 8000f52: e709 b.n 8000d68 <__udivmoddi4+0xa0> + 8000f54: 4607 mov r7, r0 + 8000f56: e6e7 b.n 8000d28 <__udivmoddi4+0x60> + 8000f58: 4618 mov r0, r3 + 8000f5a: e6fb b.n 8000d54 <__udivmoddi4+0x8c> + 8000f5c: 4541 cmp r1, r8 + 8000f5e: d2ab bcs.n 8000eb8 <__udivmoddi4+0x1f0> + 8000f60: ebb8 0a02 subs.w sl, r8, r2 + 8000f64: eb69 020e sbc.w r2, r9, lr + 8000f68: 3801 subs r0, #1 + 8000f6a: 4613 mov r3, r2 + 8000f6c: e7a4 b.n 8000eb8 <__udivmoddi4+0x1f0> + 8000f6e: 4660 mov r0, ip + 8000f70: e7e9 b.n 8000f46 <__udivmoddi4+0x27e> + 8000f72: 4618 mov r0, r3 + 8000f74: e795 b.n 8000ea2 <__udivmoddi4+0x1da> + 8000f76: 4667 mov r7, ip + 8000f78: e7d1 b.n 8000f1e <__udivmoddi4+0x256> + 8000f7a: 4681 mov r9, r0 + 8000f7c: e77c b.n 8000e78 <__udivmoddi4+0x1b0> + 8000f7e: 3802 subs r0, #2 + 8000f80: 442c add r4, r5 + 8000f82: e747 b.n 8000e14 <__udivmoddi4+0x14c> + 8000f84: f1ac 0c02 sub.w ip, ip, #2 + 8000f88: 442b add r3, r5 + 8000f8a: e72f b.n 8000dec <__udivmoddi4+0x124> + 8000f8c: 4638 mov r0, r7 + 8000f8e: e708 b.n 8000da2 <__udivmoddi4+0xda> + 8000f90: 4637 mov r7, r6 + 8000f92: e6e9 b.n 8000d68 <__udivmoddi4+0xa0> + +08000f94 <__aeabi_idiv0>: + 8000f94: 4770 bx lr + 8000f96: bf00 nop + +08000f98 : +extern I2C_HandleTypeDef hi2c1; +LSM303 eComp; +COMPASS_LEDS compLeds; + +void setup(void) +{ + 8000f98: b580 push {r7, lr} + 8000f9a: af00 add r7, sp, #0 + COMPASS_LEDS_Init(&compLeds); + 8000f9c: 481b ldr r0, [pc, #108] ; (800100c ) + 8000f9e: f000 fe55 bl 8001c4c + + if(!LSM303_Init(&eComp, &hi2c1)) + 8000fa2: 491b ldr r1, [pc, #108] ; (8001010 ) + 8000fa4: 481b ldr r0, [pc, #108] ; (8001014 ) + 8000fa6: f000 ff85 bl 8001eb4 + 8000faa: 4603 mov r3, r0 + 8000fac: 2b00 cmp r3, #0 + 8000fae: d102 bne.n 8000fb6 + printf("Failed to init eCompass\r\n"); + 8000fb0: 4819 ldr r0, [pc, #100] ; (8001018 ) + 8000fb2: f00a f94f bl 800b254 + + if(!LSM303_EnableTemperatureSensor(&eComp, true)) + 8000fb6: 2101 movs r1, #1 + 8000fb8: 4816 ldr r0, [pc, #88] ; (8001014 ) + 8000fba: f000 ff9a bl 8001ef2 + 8000fbe: 4603 mov r3, r0 + 8000fc0: 2b00 cmp r3, #0 + 8000fc2: d102 bne.n 8000fca + printf("Failed to enable temp sensor\r\n"); + 8000fc4: 4815 ldr r0, [pc, #84] ; (800101c ) + 8000fc6: f00a f945 bl 800b254 + + if(!LSM303_ApplyConfig(&eComp)) + 8000fca: 4812 ldr r0, [pc, #72] ; (8001014 ) + 8000fcc: f000 ffac bl 8001f28 + 8000fd0: 4603 mov r3, r0 + 8000fd2: 2b00 cmp r3, #0 + 8000fd4: d102 bne.n 8000fdc + printf("Failed to apply config\r\n"); + 8000fd6: 4812 ldr r0, [pc, #72] ; (8001020 ) + 8000fd8: f00a f93c bl 800b254 + + if(!LSM303_GetDeviceID(&eComp, id)) + 8000fdc: 4911 ldr r1, [pc, #68] ; (8001024 ) + 8000fde: 480d ldr r0, [pc, #52] ; (8001014 ) + 8000fe0: f000 ffee bl 8001fc0 + 8000fe4: 4603 mov r3, r0 + 8000fe6: 2b00 cmp r3, #0 + 8000fe8: d103 bne.n 8000ff2 + printf("Failed to retrieve id\r\n"); + 8000fea: 480f ldr r0, [pc, #60] ; (8001028 ) + 8000fec: f00a f932 bl 800b254 + else + printf("LSM303 ID : %#X,%#X,%#X\r\n", id[0], id[1], id[2]); +} + 8000ff0: e00a b.n 8001008 + printf("LSM303 ID : %#X,%#X,%#X\r\n", id[0], id[1], id[2]); + 8000ff2: 4b0c ldr r3, [pc, #48] ; (8001024 ) + 8000ff4: 781b ldrb r3, [r3, #0] + 8000ff6: 4619 mov r1, r3 + 8000ff8: 4b0a ldr r3, [pc, #40] ; (8001024 ) + 8000ffa: 785b ldrb r3, [r3, #1] + 8000ffc: 461a mov r2, r3 + 8000ffe: 4b09 ldr r3, [pc, #36] ; (8001024 ) + 8001000: 789b ldrb r3, [r3, #2] + 8001002: 480a ldr r0, [pc, #40] ; (800102c ) + 8001004: f00a f8b2 bl 800b16c +} + 8001008: bf00 nop + 800100a: bd80 pop {r7, pc} + 800100c: 20000244 .word 0x20000244 + 8001010: 20000294 .word 0x20000294 + 8001014: 2000023c .word 0x2000023c + 8001018: 0800e820 .word 0x0800e820 + 800101c: 0800e83c .word 0x0800e83c + 8001020: 0800e85c .word 0x0800e85c + 8001024: 20000224 .word 0x20000224 + 8001028: 0800e874 .word 0x0800e874 + 800102c: 0800e88c .word 0x0800e88c + +08001030 : + +void loop(void) +{ + 8001030: b590 push {r4, r7, lr} + 8001032: b083 sub sp, #12 + 8001034: af00 add r7, sp, #0 + if(HAL_GetTick() - ts_print > PRINT_RATE_MS) + 8001036: f001 f971 bl 800231c + 800103a: 4602 mov r2, r0 + 800103c: 4b50 ldr r3, [pc, #320] ; (8001180 ) + 800103e: 681b ldr r3, [r3, #0] + 8001040: 1ad3 subs r3, r2, r3 + 8001042: 2b64 cmp r3, #100 ; 0x64 + 8001044: d93a bls.n 80010bc + { + //Lets read the temperature : + float temperature = 0; + 8001046: f04f 0300 mov.w r3, #0 + 800104a: 607b str r3, [r7, #4] + + if(!LSM303_GetTemperature(&eComp, &temperature, NULL)) + 800104c: 1d3b adds r3, r7, #4 + 800104e: 2200 movs r2, #0 + 8001050: 4619 mov r1, r3 + 8001052: 484c ldr r0, [pc, #304] ; (8001184 ) + 8001054: f000 ffe8 bl 8002028 + 8001058: 4603 mov r3, r0 + 800105a: 2b00 cmp r3, #0 + 800105c: d103 bne.n 8001066 + printf("Failed to get temperature\r\n"); + 800105e: 484a ldr r0, [pc, #296] ; (8001188 ) + 8001060: f00a f8f8 bl 800b254 + 8001064: e00a b.n 800107c + else + printf("Temp is : %.3f\r\n", temperature); + 8001066: 687b ldr r3, [r7, #4] + 8001068: 4618 mov r0, r3 + 800106a: f7ff fa75 bl 8000558 <__aeabi_f2d> + 800106e: 4603 mov r3, r0 + 8001070: 460c mov r4, r1 + 8001072: 461a mov r2, r3 + 8001074: 4623 mov r3, r4 + 8001076: 4845 ldr r0, [pc, #276] ; (800118c ) + 8001078: f00a f878 bl 800b16c + + if(!LSM303_GetMagneticFieldData(&eComp, &x, &y, &z)) + 800107c: 4b44 ldr r3, [pc, #272] ; (8001190 ) + 800107e: 4a45 ldr r2, [pc, #276] ; (8001194 ) + 8001080: 4945 ldr r1, [pc, #276] ; (8001198 ) + 8001082: 4840 ldr r0, [pc, #256] ; (8001184 ) + 8001084: f001 f82a bl 80020dc + 8001088: 4603 mov r3, r0 + 800108a: 2b00 cmp r3, #0 + 800108c: d103 bne.n 8001096 + printf("Failed to get magnetic data\r\n"); + 800108e: 4843 ldr r0, [pc, #268] ; (800119c ) + 8001090: f00a f8e0 bl 800b254 + 8001094: e00d b.n 80010b2 + else + printf("x : %d, y : %d, z : %d\r\n", x, y, z); + 8001096: 4b40 ldr r3, [pc, #256] ; (8001198 ) + 8001098: f9b3 3000 ldrsh.w r3, [r3] + 800109c: 4619 mov r1, r3 + 800109e: 4b3d ldr r3, [pc, #244] ; (8001194 ) + 80010a0: f9b3 3000 ldrsh.w r3, [r3] + 80010a4: 461a mov r2, r3 + 80010a6: 4b3a ldr r3, [pc, #232] ; (8001190 ) + 80010a8: f9b3 3000 ldrsh.w r3, [r3] + 80010ac: 483c ldr r0, [pc, #240] ; (80011a0 ) + 80010ae: f00a f85d bl 800b16c + + ts_print = HAL_GetTick(); + 80010b2: f001 f933 bl 800231c + 80010b6: 4602 mov r2, r0 + 80010b8: 4b31 ldr r3, [pc, #196] ; (8001180 ) + 80010ba: 601a str r2, [r3, #0] + } + + if(x > 0 && x > abs(y) - 50) + 80010bc: 4b36 ldr r3, [pc, #216] ; (8001198 ) + 80010be: f9b3 3000 ldrsh.w r3, [r3] + 80010c2: 2b00 cmp r3, #0 + 80010c4: dd10 ble.n 80010e8 + 80010c6: 4b34 ldr r3, [pc, #208] ; (8001198 ) + 80010c8: f9b3 3000 ldrsh.w r3, [r3] + 80010cc: 461a mov r2, r3 + 80010ce: 4b31 ldr r3, [pc, #196] ; (8001194 ) + 80010d0: f9b3 3000 ldrsh.w r3, [r3] + 80010d4: 2b00 cmp r3, #0 + 80010d6: bfb8 it lt + 80010d8: 425b neglt r3, r3 + 80010da: 3b32 subs r3, #50 ; 0x32 + 80010dc: 429a cmp r2, r3 + 80010de: dd03 ble.n 80010e8 + COMPASS_LEDS_Light(&compLeds, NORTH); + 80010e0: 2101 movs r1, #1 + 80010e2: 4830 ldr r0, [pc, #192] ; (80011a4 ) + 80010e4: f000 fe1c bl 8001d20 + if(x < 0 && abs(x) > abs(y) - 50) + 80010e8: 4b2b ldr r3, [pc, #172] ; (8001198 ) + 80010ea: f9b3 3000 ldrsh.w r3, [r3] + 80010ee: 2b00 cmp r3, #0 + 80010f0: da13 bge.n 800111a + 80010f2: 4b29 ldr r3, [pc, #164] ; (8001198 ) + 80010f4: f9b3 3000 ldrsh.w r3, [r3] + 80010f8: ea83 72e3 eor.w r2, r3, r3, asr #31 + 80010fc: eba2 72e3 sub.w r2, r2, r3, asr #31 + 8001100: 4b24 ldr r3, [pc, #144] ; (8001194 ) + 8001102: f9b3 3000 ldrsh.w r3, [r3] + 8001106: 2b00 cmp r3, #0 + 8001108: bfb8 it lt + 800110a: 425b neglt r3, r3 + 800110c: 3b32 subs r3, #50 ; 0x32 + 800110e: 429a cmp r2, r3 + 8001110: dd03 ble.n 800111a + COMPASS_LEDS_Light(&compLeds, SOUTH); + 8001112: 2102 movs r1, #2 + 8001114: 4823 ldr r0, [pc, #140] ; (80011a4 ) + 8001116: f000 fe03 bl 8001d20 + if(y > 0 && y > abs(x) - 50) + 800111a: 4b1e ldr r3, [pc, #120] ; (8001194 ) + 800111c: f9b3 3000 ldrsh.w r3, [r3] + 8001120: 2b00 cmp r3, #0 + 8001122: dd10 ble.n 8001146 + 8001124: 4b1b ldr r3, [pc, #108] ; (8001194 ) + 8001126: f9b3 3000 ldrsh.w r3, [r3] + 800112a: 461a mov r2, r3 + 800112c: 4b1a ldr r3, [pc, #104] ; (8001198 ) + 800112e: f9b3 3000 ldrsh.w r3, [r3] + 8001132: 2b00 cmp r3, #0 + 8001134: bfb8 it lt + 8001136: 425b neglt r3, r3 + 8001138: 3b32 subs r3, #50 ; 0x32 + 800113a: 429a cmp r2, r3 + 800113c: dd03 ble.n 8001146 + COMPASS_LEDS_Light(&compLeds, EAST); + 800113e: 2108 movs r1, #8 + 8001140: 4818 ldr r0, [pc, #96] ; (80011a4 ) + 8001142: f000 fded bl 8001d20 + if(y < 0 && abs(y) > abs(x) - 50) + 8001146: 4b13 ldr r3, [pc, #76] ; (8001194 ) + 8001148: f9b3 3000 ldrsh.w r3, [r3] + 800114c: 2b00 cmp r3, #0 + 800114e: da13 bge.n 8001178 + 8001150: 4b10 ldr r3, [pc, #64] ; (8001194 ) + 8001152: f9b3 3000 ldrsh.w r3, [r3] + 8001156: ea83 72e3 eor.w r2, r3, r3, asr #31 + 800115a: eba2 72e3 sub.w r2, r2, r3, asr #31 + 800115e: 4b0e ldr r3, [pc, #56] ; (8001198 ) + 8001160: f9b3 3000 ldrsh.w r3, [r3] + 8001164: 2b00 cmp r3, #0 + 8001166: bfb8 it lt + 8001168: 425b neglt r3, r3 + 800116a: 3b32 subs r3, #50 ; 0x32 + 800116c: 429a cmp r2, r3 + 800116e: dd03 ble.n 8001178 + COMPASS_LEDS_Light(&compLeds, WEST); + 8001170: 2104 movs r1, #4 + 8001172: 480c ldr r0, [pc, #48] ; (80011a4 ) + 8001174: f000 fdd4 bl 8001d20 +} + 8001178: bf00 nop + 800117a: 370c adds r7, #12 + 800117c: 46bd mov sp, r7 + 800117e: bd90 pop {r4, r7, pc} + 8001180: 20000218 .word 0x20000218 + 8001184: 2000023c .word 0x2000023c + 8001188: 0800e8a8 .word 0x0800e8a8 + 800118c: 0800e8c4 .word 0x0800e8c4 + 8001190: 20000220 .word 0x20000220 + 8001194: 2000021e .word 0x2000021e + 8001198: 2000021c .word 0x2000021c + 800119c: 0800e8d8 .word 0x0800e8d8 + 80011a0: 0800e8f8 .word 0x0800e8f8 + 80011a4: 20000244 .word 0x20000244 + +080011a8 <__io_putchar>: +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +int __io_putchar(int ch) +{ + 80011a8: b580 push {r7, lr} + 80011aa: b082 sub sp, #8 + 80011ac: af00 add r7, sp, #0 + 80011ae: 6078 str r0, [r7, #4] + HAL_UART_Transmit(&huart2, (uint8_t*)&ch, 1, HAL_MAX_DELAY); + 80011b0: 1d39 adds r1, r7, #4 + 80011b2: f04f 33ff mov.w r3, #4294967295 + 80011b6: 2201 movs r2, #1 + 80011b8: 4803 ldr r0, [pc, #12] ; (80011c8 <__io_putchar+0x20>) + 80011ba: f005 fb02 bl 80067c2 + return ch; + 80011be: 687b ldr r3, [r7, #4] +} + 80011c0: 4618 mov r0, r3 + 80011c2: 3708 adds r7, #8 + 80011c4: 46bd mov sp, r7 + 80011c6: bd80 pop {r7, pc} + 80011c8: 20000340 .word 0x20000340 + +080011cc
: +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + 80011cc: b580 push {r7, lr} + 80011ce: af00 add r7, sp, #0 + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + 80011d0: f001 f83e bl 8002250 + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + 80011d4: f000 f816 bl 8001204 + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + 80011d8: f000 f984 bl 80014e4 + MX_I2C1_Init(); + 80011dc: f000 f896 bl 800130c + MX_I2S2_Init(); + 80011e0: f000 f8c2 bl 8001368 + MX_I2S3_Init(); + 80011e4: f000 f8ee bl 80013c4 + MX_SPI1_Init(); + 80011e8: f000 f91c bl 8001424 + MX_USB_HOST_Init(); + 80011ec: f008 fd8e bl 8009d0c + MX_USART2_UART_Init(); + 80011f0: f000 f94e bl 8001490 + /* USER CODE BEGIN 2 */ + setup(); + 80011f4: f7ff fed0 bl 8000f98 + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + /* USER CODE END WHILE */ + MX_USB_HOST_Process(); + 80011f8: f008 fdae bl 8009d58 + + /* USER CODE BEGIN 3 */ + loop(); + 80011fc: f7ff ff18 bl 8001030 + MX_USB_HOST_Process(); + 8001200: e7fa b.n 80011f8 + ... + +08001204 : +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + 8001204: b580 push {r7, lr} + 8001206: b098 sub sp, #96 ; 0x60 + 8001208: af00 add r7, sp, #0 + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + 800120a: f107 0330 add.w r3, r7, #48 ; 0x30 + 800120e: 2230 movs r2, #48 ; 0x30 + 8001210: 2100 movs r1, #0 + 8001212: 4618 mov r0, r3 + 8001214: f009 f8bc bl 800a390 + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + 8001218: f107 031c add.w r3, r7, #28 + 800121c: 2200 movs r2, #0 + 800121e: 601a str r2, [r3, #0] + 8001220: 605a str r2, [r3, #4] + 8001222: 609a str r2, [r3, #8] + 8001224: 60da str r2, [r3, #12] + 8001226: 611a str r2, [r3, #16] + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + 8001228: f107 0308 add.w r3, r7, #8 + 800122c: 2200 movs r2, #0 + 800122e: 601a str r2, [r3, #0] + 8001230: 605a str r2, [r3, #4] + 8001232: 609a str r2, [r3, #8] + 8001234: 60da str r2, [r3, #12] + 8001236: 611a str r2, [r3, #16] + + /** Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + 8001238: 2300 movs r3, #0 + 800123a: 607b str r3, [r7, #4] + 800123c: 4b31 ldr r3, [pc, #196] ; (8001304 ) + 800123e: 6c1b ldr r3, [r3, #64] ; 0x40 + 8001240: 4a30 ldr r2, [pc, #192] ; (8001304 ) + 8001242: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 8001246: 6413 str r3, [r2, #64] ; 0x40 + 8001248: 4b2e ldr r3, [pc, #184] ; (8001304 ) + 800124a: 6c1b ldr r3, [r3, #64] ; 0x40 + 800124c: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8001250: 607b str r3, [r7, #4] + 8001252: 687b ldr r3, [r7, #4] + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); + 8001254: 2300 movs r3, #0 + 8001256: 603b str r3, [r7, #0] + 8001258: 4b2b ldr r3, [pc, #172] ; (8001308 ) + 800125a: 681b ldr r3, [r3, #0] + 800125c: f423 4340 bic.w r3, r3, #49152 ; 0xc000 + 8001260: 4a29 ldr r2, [pc, #164] ; (8001308 ) + 8001262: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 8001266: 6013 str r3, [r2, #0] + 8001268: 4b27 ldr r3, [pc, #156] ; (8001308 ) + 800126a: 681b ldr r3, [r3, #0] + 800126c: f403 4340 and.w r3, r3, #49152 ; 0xc000 + 8001270: 603b str r3, [r7, #0] + 8001272: 683b ldr r3, [r7, #0] + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + 8001274: 2301 movs r3, #1 + 8001276: 633b str r3, [r7, #48] ; 0x30 + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + 8001278: f44f 3380 mov.w r3, #65536 ; 0x10000 + 800127c: 637b str r3, [r7, #52] ; 0x34 + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + 800127e: 2302 movs r3, #2 + 8001280: 64bb str r3, [r7, #72] ; 0x48 + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + 8001282: f44f 0380 mov.w r3, #4194304 ; 0x400000 + 8001286: 64fb str r3, [r7, #76] ; 0x4c + RCC_OscInitStruct.PLL.PLLM = 8; + 8001288: 2308 movs r3, #8 + 800128a: 653b str r3, [r7, #80] ; 0x50 + RCC_OscInitStruct.PLL.PLLN = 336; + 800128c: f44f 73a8 mov.w r3, #336 ; 0x150 + 8001290: 657b str r3, [r7, #84] ; 0x54 + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; + 8001292: 2304 movs r3, #4 + 8001294: 65bb str r3, [r7, #88] ; 0x58 + RCC_OscInitStruct.PLL.PLLQ = 7; + 8001296: 2307 movs r3, #7 + 8001298: 65fb str r3, [r7, #92] ; 0x5c + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + 800129a: f107 0330 add.w r3, r7, #48 ; 0x30 + 800129e: 4618 mov r0, r3 + 80012a0: f004 fc32 bl 8005b08 + 80012a4: 4603 mov r3, r0 + 80012a6: 2b00 cmp r3, #0 + 80012a8: d001 beq.n 80012ae + { + Error_Handler(); + 80012aa: f000 f9f5 bl 8001698 + } + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + 80012ae: 230f movs r3, #15 + 80012b0: 61fb str r3, [r7, #28] + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + 80012b2: 2302 movs r3, #2 + 80012b4: 623b str r3, [r7, #32] + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + 80012b6: 2300 movs r3, #0 + 80012b8: 627b str r3, [r7, #36] ; 0x24 + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; + 80012ba: f44f 5380 mov.w r3, #4096 ; 0x1000 + 80012be: 62bb str r3, [r7, #40] ; 0x28 + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + 80012c0: 2300 movs r3, #0 + 80012c2: 62fb str r3, [r7, #44] ; 0x2c + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) + 80012c4: f107 031c add.w r3, r7, #28 + 80012c8: 2102 movs r1, #2 + 80012ca: 4618 mov r0, r3 + 80012cc: f004 fe8c bl 8005fe8 + 80012d0: 4603 mov r3, r0 + 80012d2: 2b00 cmp r3, #0 + 80012d4: d001 beq.n 80012da + { + Error_Handler(); + 80012d6: f000 f9df bl 8001698 + } + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2S; + 80012da: 2301 movs r3, #1 + 80012dc: 60bb str r3, [r7, #8] + PeriphClkInitStruct.PLLI2S.PLLI2SN = 192; + 80012de: 23c0 movs r3, #192 ; 0xc0 + 80012e0: 60fb str r3, [r7, #12] + PeriphClkInitStruct.PLLI2S.PLLI2SR = 2; + 80012e2: 2302 movs r3, #2 + 80012e4: 613b str r3, [r7, #16] + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + 80012e6: f107 0308 add.w r3, r7, #8 + 80012ea: 4618 mov r0, r3 + 80012ec: f005 f86e bl 80063cc + 80012f0: 4603 mov r3, r0 + 80012f2: 2b00 cmp r3, #0 + 80012f4: d001 beq.n 80012fa + { + Error_Handler(); + 80012f6: f000 f9cf bl 8001698 + } +} + 80012fa: bf00 nop + 80012fc: 3760 adds r7, #96 ; 0x60 + 80012fe: 46bd mov sp, r7 + 8001300: bd80 pop {r7, pc} + 8001302: bf00 nop + 8001304: 40023800 .word 0x40023800 + 8001308: 40007000 .word 0x40007000 + +0800130c : + * @brief I2C1 Initialization Function + * @param None + * @retval None + */ +static void MX_I2C1_Init(void) +{ + 800130c: b580 push {r7, lr} + 800130e: af00 add r7, sp, #0 + /* USER CODE END I2C1_Init 0 */ + + /* USER CODE BEGIN I2C1_Init 1 */ + + /* USER CODE END I2C1_Init 1 */ + hi2c1.Instance = I2C1; + 8001310: 4b12 ldr r3, [pc, #72] ; (800135c ) + 8001312: 4a13 ldr r2, [pc, #76] ; (8001360 ) + 8001314: 601a str r2, [r3, #0] + hi2c1.Init.ClockSpeed = 100000; + 8001316: 4b11 ldr r3, [pc, #68] ; (800135c ) + 8001318: 4a12 ldr r2, [pc, #72] ; (8001364 ) + 800131a: 605a str r2, [r3, #4] + hi2c1.Init.DutyCycle = I2C_DUTYCYCLE_2; + 800131c: 4b0f ldr r3, [pc, #60] ; (800135c ) + 800131e: 2200 movs r2, #0 + 8001320: 609a str r2, [r3, #8] + hi2c1.Init.OwnAddress1 = 0; + 8001322: 4b0e ldr r3, [pc, #56] ; (800135c ) + 8001324: 2200 movs r2, #0 + 8001326: 60da str r2, [r3, #12] + hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + 8001328: 4b0c ldr r3, [pc, #48] ; (800135c ) + 800132a: f44f 4280 mov.w r2, #16384 ; 0x4000 + 800132e: 611a str r2, [r3, #16] + hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; + 8001330: 4b0a ldr r3, [pc, #40] ; (800135c ) + 8001332: 2200 movs r2, #0 + 8001334: 615a str r2, [r3, #20] + hi2c1.Init.OwnAddress2 = 0; + 8001336: 4b09 ldr r3, [pc, #36] ; (800135c ) + 8001338: 2200 movs r2, #0 + 800133a: 619a str r2, [r3, #24] + hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; + 800133c: 4b07 ldr r3, [pc, #28] ; (800135c ) + 800133e: 2200 movs r2, #0 + 8001340: 61da str r2, [r3, #28] + hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; + 8001342: 4b06 ldr r3, [pc, #24] ; (800135c ) + 8001344: 2200 movs r2, #0 + 8001346: 621a str r2, [r3, #32] + if (HAL_I2C_Init(&hi2c1) != HAL_OK) + 8001348: 4804 ldr r0, [pc, #16] ; (800135c ) + 800134a: f002 ffb3 bl 80042b4 + 800134e: 4603 mov r3, r0 + 8001350: 2b00 cmp r3, #0 + 8001352: d001 beq.n 8001358 + { + Error_Handler(); + 8001354: f000 f9a0 bl 8001698 + } + /* USER CODE BEGIN I2C1_Init 2 */ + + /* USER CODE END I2C1_Init 2 */ + +} + 8001358: bf00 nop + 800135a: bd80 pop {r7, pc} + 800135c: 20000294 .word 0x20000294 + 8001360: 40005400 .word 0x40005400 + 8001364: 000186a0 .word 0x000186a0 + +08001368 : + * @brief I2S2 Initialization Function + * @param None + * @retval None + */ +static void MX_I2S2_Init(void) +{ + 8001368: b580 push {r7, lr} + 800136a: af00 add r7, sp, #0 + /* USER CODE END I2S2_Init 0 */ + + /* USER CODE BEGIN I2S2_Init 1 */ + + /* USER CODE END I2S2_Init 1 */ + hi2s2.Instance = SPI2; + 800136c: 4b13 ldr r3, [pc, #76] ; (80013bc ) + 800136e: 4a14 ldr r2, [pc, #80] ; (80013c0 ) + 8001370: 601a str r2, [r3, #0] + hi2s2.Init.Mode = I2S_MODE_MASTER_TX; + 8001372: 4b12 ldr r3, [pc, #72] ; (80013bc ) + 8001374: f44f 7200 mov.w r2, #512 ; 0x200 + 8001378: 605a str r2, [r3, #4] + hi2s2.Init.Standard = I2S_STANDARD_PHILIPS; + 800137a: 4b10 ldr r3, [pc, #64] ; (80013bc ) + 800137c: 2200 movs r2, #0 + 800137e: 609a str r2, [r3, #8] + hi2s2.Init.DataFormat = I2S_DATAFORMAT_16B; + 8001380: 4b0e ldr r3, [pc, #56] ; (80013bc ) + 8001382: 2200 movs r2, #0 + 8001384: 60da str r2, [r3, #12] + hi2s2.Init.MCLKOutput = I2S_MCLKOUTPUT_DISABLE; + 8001386: 4b0d ldr r3, [pc, #52] ; (80013bc ) + 8001388: 2200 movs r2, #0 + 800138a: 611a str r2, [r3, #16] + hi2s2.Init.AudioFreq = I2S_AUDIOFREQ_8K; + 800138c: 4b0b ldr r3, [pc, #44] ; (80013bc ) + 800138e: f44f 52fa mov.w r2, #8000 ; 0x1f40 + 8001392: 615a str r2, [r3, #20] + hi2s2.Init.CPOL = I2S_CPOL_LOW; + 8001394: 4b09 ldr r3, [pc, #36] ; (80013bc ) + 8001396: 2200 movs r2, #0 + 8001398: 619a str r2, [r3, #24] + hi2s2.Init.ClockSource = I2S_CLOCK_PLL; + 800139a: 4b08 ldr r3, [pc, #32] ; (80013bc ) + 800139c: 2200 movs r2, #0 + 800139e: 61da str r2, [r3, #28] + hi2s2.Init.FullDuplexMode = I2S_FULLDUPLEXMODE_DISABLE; + 80013a0: 4b06 ldr r3, [pc, #24] ; (80013bc ) + 80013a2: 2200 movs r2, #0 + 80013a4: 621a str r2, [r3, #32] + if (HAL_I2S_Init(&hi2s2) != HAL_OK) + 80013a6: 4805 ldr r0, [pc, #20] ; (80013bc ) + 80013a8: f003 ff0e bl 80051c8 + 80013ac: 4603 mov r3, r0 + 80013ae: 2b00 cmp r3, #0 + 80013b0: d001 beq.n 80013b6 + { + Error_Handler(); + 80013b2: f000 f971 bl 8001698 + } + /* USER CODE BEGIN I2S2_Init 2 */ + + /* USER CODE END I2S2_Init 2 */ + +} + 80013b6: bf00 nop + 80013b8: bd80 pop {r7, pc} + 80013ba: bf00 nop + 80013bc: 20000380 .word 0x20000380 + 80013c0: 40003800 .word 0x40003800 + +080013c4 : + * @brief I2S3 Initialization Function + * @param None + * @retval None + */ +static void MX_I2S3_Init(void) +{ + 80013c4: b580 push {r7, lr} + 80013c6: af00 add r7, sp, #0 + /* USER CODE END I2S3_Init 0 */ + + /* USER CODE BEGIN I2S3_Init 1 */ + + /* USER CODE END I2S3_Init 1 */ + hi2s3.Instance = SPI3; + 80013c8: 4b13 ldr r3, [pc, #76] ; (8001418 ) + 80013ca: 4a14 ldr r2, [pc, #80] ; (800141c ) + 80013cc: 601a str r2, [r3, #0] + hi2s3.Init.Mode = I2S_MODE_MASTER_TX; + 80013ce: 4b12 ldr r3, [pc, #72] ; (8001418 ) + 80013d0: f44f 7200 mov.w r2, #512 ; 0x200 + 80013d4: 605a str r2, [r3, #4] + hi2s3.Init.Standard = I2S_STANDARD_PHILIPS; + 80013d6: 4b10 ldr r3, [pc, #64] ; (8001418 ) + 80013d8: 2200 movs r2, #0 + 80013da: 609a str r2, [r3, #8] + hi2s3.Init.DataFormat = I2S_DATAFORMAT_16B; + 80013dc: 4b0e ldr r3, [pc, #56] ; (8001418 ) + 80013de: 2200 movs r2, #0 + 80013e0: 60da str r2, [r3, #12] + hi2s3.Init.MCLKOutput = I2S_MCLKOUTPUT_ENABLE; + 80013e2: 4b0d ldr r3, [pc, #52] ; (8001418 ) + 80013e4: f44f 7200 mov.w r2, #512 ; 0x200 + 80013e8: 611a str r2, [r3, #16] + hi2s3.Init.AudioFreq = I2S_AUDIOFREQ_96K; + 80013ea: 4b0b ldr r3, [pc, #44] ; (8001418 ) + 80013ec: 4a0c ldr r2, [pc, #48] ; (8001420 ) + 80013ee: 615a str r2, [r3, #20] + hi2s3.Init.CPOL = I2S_CPOL_LOW; + 80013f0: 4b09 ldr r3, [pc, #36] ; (8001418 ) + 80013f2: 2200 movs r2, #0 + 80013f4: 619a str r2, [r3, #24] + hi2s3.Init.ClockSource = I2S_CLOCK_PLL; + 80013f6: 4b08 ldr r3, [pc, #32] ; (8001418 ) + 80013f8: 2200 movs r2, #0 + 80013fa: 61da str r2, [r3, #28] + hi2s3.Init.FullDuplexMode = I2S_FULLDUPLEXMODE_DISABLE; + 80013fc: 4b06 ldr r3, [pc, #24] ; (8001418 ) + 80013fe: 2200 movs r2, #0 + 8001400: 621a str r2, [r3, #32] + if (HAL_I2S_Init(&hi2s3) != HAL_OK) + 8001402: 4805 ldr r0, [pc, #20] ; (8001418 ) + 8001404: f003 fee0 bl 80051c8 + 8001408: 4603 mov r3, r0 + 800140a: 2b00 cmp r3, #0 + 800140c: d001 beq.n 8001412 + { + Error_Handler(); + 800140e: f000 f943 bl 8001698 + } + /* USER CODE BEGIN I2S3_Init 2 */ + + /* USER CODE END I2S3_Init 2 */ + +} + 8001412: bf00 nop + 8001414: bd80 pop {r7, pc} + 8001416: bf00 nop + 8001418: 200003c8 .word 0x200003c8 + 800141c: 40003c00 .word 0x40003c00 + 8001420: 00017700 .word 0x00017700 + +08001424 : + * @brief SPI1 Initialization Function + * @param None + * @retval None + */ +static void MX_SPI1_Init(void) +{ + 8001424: b580 push {r7, lr} + 8001426: af00 add r7, sp, #0 + + /* USER CODE BEGIN SPI1_Init 1 */ + + /* USER CODE END SPI1_Init 1 */ + /* SPI1 parameter configuration*/ + hspi1.Instance = SPI1; + 8001428: 4b17 ldr r3, [pc, #92] ; (8001488 ) + 800142a: 4a18 ldr r2, [pc, #96] ; (800148c ) + 800142c: 601a str r2, [r3, #0] + hspi1.Init.Mode = SPI_MODE_MASTER; + 800142e: 4b16 ldr r3, [pc, #88] ; (8001488 ) + 8001430: f44f 7282 mov.w r2, #260 ; 0x104 + 8001434: 605a str r2, [r3, #4] + hspi1.Init.Direction = SPI_DIRECTION_2LINES; + 8001436: 4b14 ldr r3, [pc, #80] ; (8001488 ) + 8001438: 2200 movs r2, #0 + 800143a: 609a str r2, [r3, #8] + hspi1.Init.DataSize = SPI_DATASIZE_8BIT; + 800143c: 4b12 ldr r3, [pc, #72] ; (8001488 ) + 800143e: 2200 movs r2, #0 + 8001440: 60da str r2, [r3, #12] + hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; + 8001442: 4b11 ldr r3, [pc, #68] ; (8001488 ) + 8001444: 2200 movs r2, #0 + 8001446: 611a str r2, [r3, #16] + hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; + 8001448: 4b0f ldr r3, [pc, #60] ; (8001488 ) + 800144a: 2200 movs r2, #0 + 800144c: 615a str r2, [r3, #20] + hspi1.Init.NSS = SPI_NSS_SOFT; + 800144e: 4b0e ldr r3, [pc, #56] ; (8001488 ) + 8001450: f44f 7200 mov.w r2, #512 ; 0x200 + 8001454: 619a str r2, [r3, #24] + hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + 8001456: 4b0c ldr r3, [pc, #48] ; (8001488 ) + 8001458: 2200 movs r2, #0 + 800145a: 61da str r2, [r3, #28] + hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; + 800145c: 4b0a ldr r3, [pc, #40] ; (8001488 ) + 800145e: 2200 movs r2, #0 + 8001460: 621a str r2, [r3, #32] + hspi1.Init.TIMode = SPI_TIMODE_DISABLE; + 8001462: 4b09 ldr r3, [pc, #36] ; (8001488 ) + 8001464: 2200 movs r2, #0 + 8001466: 625a str r2, [r3, #36] ; 0x24 + hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + 8001468: 4b07 ldr r3, [pc, #28] ; (8001488 ) + 800146a: 2200 movs r2, #0 + 800146c: 629a str r2, [r3, #40] ; 0x28 + hspi1.Init.CRCPolynomial = 10; + 800146e: 4b06 ldr r3, [pc, #24] ; (8001488 ) + 8001470: 220a movs r2, #10 + 8001472: 62da str r2, [r3, #44] ; 0x2c + if (HAL_SPI_Init(&hspi1) != HAL_OK) + 8001474: 4804 ldr r0, [pc, #16] ; (8001488 ) + 8001476: f005 f8f3 bl 8006660 + 800147a: 4603 mov r3, r0 + 800147c: 2b00 cmp r3, #0 + 800147e: d001 beq.n 8001484 + { + Error_Handler(); + 8001480: f000 f90a bl 8001698 + } + /* USER CODE BEGIN SPI1_Init 2 */ + + /* USER CODE END SPI1_Init 2 */ + +} + 8001484: bf00 nop + 8001486: bd80 pop {r7, pc} + 8001488: 200002e8 .word 0x200002e8 + 800148c: 40013000 .word 0x40013000 + +08001490 : + * @brief USART2 Initialization Function + * @param None + * @retval None + */ +static void MX_USART2_UART_Init(void) +{ + 8001490: b580 push {r7, lr} + 8001492: af00 add r7, sp, #0 + /* USER CODE END USART2_Init 0 */ + + /* USER CODE BEGIN USART2_Init 1 */ + + /* USER CODE END USART2_Init 1 */ + huart2.Instance = USART2; + 8001494: 4b11 ldr r3, [pc, #68] ; (80014dc ) + 8001496: 4a12 ldr r2, [pc, #72] ; (80014e0 ) + 8001498: 601a str r2, [r3, #0] + huart2.Init.BaudRate = 115200; + 800149a: 4b10 ldr r3, [pc, #64] ; (80014dc ) + 800149c: f44f 32e1 mov.w r2, #115200 ; 0x1c200 + 80014a0: 605a str r2, [r3, #4] + huart2.Init.WordLength = UART_WORDLENGTH_8B; + 80014a2: 4b0e ldr r3, [pc, #56] ; (80014dc ) + 80014a4: 2200 movs r2, #0 + 80014a6: 609a str r2, [r3, #8] + huart2.Init.StopBits = UART_STOPBITS_1; + 80014a8: 4b0c ldr r3, [pc, #48] ; (80014dc ) + 80014aa: 2200 movs r2, #0 + 80014ac: 60da str r2, [r3, #12] + huart2.Init.Parity = UART_PARITY_NONE; + 80014ae: 4b0b ldr r3, [pc, #44] ; (80014dc ) + 80014b0: 2200 movs r2, #0 + 80014b2: 611a str r2, [r3, #16] + huart2.Init.Mode = UART_MODE_TX_RX; + 80014b4: 4b09 ldr r3, [pc, #36] ; (80014dc ) + 80014b6: 220c movs r2, #12 + 80014b8: 615a str r2, [r3, #20] + huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; + 80014ba: 4b08 ldr r3, [pc, #32] ; (80014dc ) + 80014bc: 2200 movs r2, #0 + 80014be: 619a str r2, [r3, #24] + huart2.Init.OverSampling = UART_OVERSAMPLING_16; + 80014c0: 4b06 ldr r3, [pc, #24] ; (80014dc ) + 80014c2: 2200 movs r2, #0 + 80014c4: 61da str r2, [r3, #28] + if (HAL_UART_Init(&huart2) != HAL_OK) + 80014c6: 4805 ldr r0, [pc, #20] ; (80014dc ) + 80014c8: f005 f92e bl 8006728 + 80014cc: 4603 mov r3, r0 + 80014ce: 2b00 cmp r3, #0 + 80014d0: d001 beq.n 80014d6 + { + Error_Handler(); + 80014d2: f000 f8e1 bl 8001698 + } + /* USER CODE BEGIN USART2_Init 2 */ + + /* USER CODE END USART2_Init 2 */ + +} + 80014d6: bf00 nop + 80014d8: bd80 pop {r7, pc} + 80014da: bf00 nop + 80014dc: 20000340 .word 0x20000340 + 80014e0: 40004400 .word 0x40004400 + +080014e4 : + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + 80014e4: b580 push {r7, lr} + 80014e6: b08c sub sp, #48 ; 0x30 + 80014e8: af00 add r7, sp, #0 + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 80014ea: f107 031c add.w r3, r7, #28 + 80014ee: 2200 movs r2, #0 + 80014f0: 601a str r2, [r3, #0] + 80014f2: 605a str r2, [r3, #4] + 80014f4: 609a str r2, [r3, #8] + 80014f6: 60da str r2, [r3, #12] + 80014f8: 611a str r2, [r3, #16] + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOE_CLK_ENABLE(); + 80014fa: 2300 movs r3, #0 + 80014fc: 61bb str r3, [r7, #24] + 80014fe: 4b60 ldr r3, [pc, #384] ; (8001680 ) + 8001500: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001502: 4a5f ldr r2, [pc, #380] ; (8001680 ) + 8001504: f043 0310 orr.w r3, r3, #16 + 8001508: 6313 str r3, [r2, #48] ; 0x30 + 800150a: 4b5d ldr r3, [pc, #372] ; (8001680 ) + 800150c: 6b1b ldr r3, [r3, #48] ; 0x30 + 800150e: f003 0310 and.w r3, r3, #16 + 8001512: 61bb str r3, [r7, #24] + 8001514: 69bb ldr r3, [r7, #24] + __HAL_RCC_GPIOC_CLK_ENABLE(); + 8001516: 2300 movs r3, #0 + 8001518: 617b str r3, [r7, #20] + 800151a: 4b59 ldr r3, [pc, #356] ; (8001680 ) + 800151c: 6b1b ldr r3, [r3, #48] ; 0x30 + 800151e: 4a58 ldr r2, [pc, #352] ; (8001680 ) + 8001520: f043 0304 orr.w r3, r3, #4 + 8001524: 6313 str r3, [r2, #48] ; 0x30 + 8001526: 4b56 ldr r3, [pc, #344] ; (8001680 ) + 8001528: 6b1b ldr r3, [r3, #48] ; 0x30 + 800152a: f003 0304 and.w r3, r3, #4 + 800152e: 617b str r3, [r7, #20] + 8001530: 697b ldr r3, [r7, #20] + __HAL_RCC_GPIOH_CLK_ENABLE(); + 8001532: 2300 movs r3, #0 + 8001534: 613b str r3, [r7, #16] + 8001536: 4b52 ldr r3, [pc, #328] ; (8001680 ) + 8001538: 6b1b ldr r3, [r3, #48] ; 0x30 + 800153a: 4a51 ldr r2, [pc, #324] ; (8001680 ) + 800153c: f043 0380 orr.w r3, r3, #128 ; 0x80 + 8001540: 6313 str r3, [r2, #48] ; 0x30 + 8001542: 4b4f ldr r3, [pc, #316] ; (8001680 ) + 8001544: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001546: f003 0380 and.w r3, r3, #128 ; 0x80 + 800154a: 613b str r3, [r7, #16] + 800154c: 693b ldr r3, [r7, #16] + __HAL_RCC_GPIOA_CLK_ENABLE(); + 800154e: 2300 movs r3, #0 + 8001550: 60fb str r3, [r7, #12] + 8001552: 4b4b ldr r3, [pc, #300] ; (8001680 ) + 8001554: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001556: 4a4a ldr r2, [pc, #296] ; (8001680 ) + 8001558: f043 0301 orr.w r3, r3, #1 + 800155c: 6313 str r3, [r2, #48] ; 0x30 + 800155e: 4b48 ldr r3, [pc, #288] ; (8001680 ) + 8001560: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001562: f003 0301 and.w r3, r3, #1 + 8001566: 60fb str r3, [r7, #12] + 8001568: 68fb ldr r3, [r7, #12] + __HAL_RCC_GPIOB_CLK_ENABLE(); + 800156a: 2300 movs r3, #0 + 800156c: 60bb str r3, [r7, #8] + 800156e: 4b44 ldr r3, [pc, #272] ; (8001680 ) + 8001570: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001572: 4a43 ldr r2, [pc, #268] ; (8001680 ) + 8001574: f043 0302 orr.w r3, r3, #2 + 8001578: 6313 str r3, [r2, #48] ; 0x30 + 800157a: 4b41 ldr r3, [pc, #260] ; (8001680 ) + 800157c: 6b1b ldr r3, [r3, #48] ; 0x30 + 800157e: f003 0302 and.w r3, r3, #2 + 8001582: 60bb str r3, [r7, #8] + 8001584: 68bb ldr r3, [r7, #8] + __HAL_RCC_GPIOD_CLK_ENABLE(); + 8001586: 2300 movs r3, #0 + 8001588: 607b str r3, [r7, #4] + 800158a: 4b3d ldr r3, [pc, #244] ; (8001680 ) + 800158c: 6b1b ldr r3, [r3, #48] ; 0x30 + 800158e: 4a3c ldr r2, [pc, #240] ; (8001680 ) + 8001590: f043 0308 orr.w r3, r3, #8 + 8001594: 6313 str r3, [r2, #48] ; 0x30 + 8001596: 4b3a ldr r3, [pc, #232] ; (8001680 ) + 8001598: 6b1b ldr r3, [r3, #48] ; 0x30 + 800159a: f003 0308 and.w r3, r3, #8 + 800159e: 607b str r3, [r7, #4] + 80015a0: 687b ldr r3, [r7, #4] + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(CS_I2C_SPI_GPIO_Port, CS_I2C_SPI_Pin, GPIO_PIN_RESET); + 80015a2: 2200 movs r2, #0 + 80015a4: 2108 movs r1, #8 + 80015a6: 4837 ldr r0, [pc, #220] ; (8001684 ) + 80015a8: f001 f97a bl 80028a0 + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(OTG_FS_PowerSwitchOn_GPIO_Port, OTG_FS_PowerSwitchOn_Pin, GPIO_PIN_SET); + 80015ac: 2201 movs r2, #1 + 80015ae: 2101 movs r1, #1 + 80015b0: 4835 ldr r0, [pc, #212] ; (8001688 ) + 80015b2: f001 f975 bl 80028a0 + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOD, LD4_Pin|LD3_Pin|LD5_Pin|LD6_Pin + 80015b6: 2200 movs r2, #0 + 80015b8: f24f 0110 movw r1, #61456 ; 0xf010 + 80015bc: 4833 ldr r0, [pc, #204] ; (800168c ) + 80015be: f001 f96f bl 80028a0 + |Audio_RST_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pin : PE2 */ + GPIO_InitStruct.Pin = GPIO_PIN_2; + 80015c2: 2304 movs r3, #4 + 80015c4: 61fb str r3, [r7, #28] + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + 80015c6: 2300 movs r3, #0 + 80015c8: 623b str r3, [r7, #32] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80015ca: 2300 movs r3, #0 + 80015cc: 627b str r3, [r7, #36] ; 0x24 + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + 80015ce: f107 031c add.w r3, r7, #28 + 80015d2: 4619 mov r1, r3 + 80015d4: 482b ldr r0, [pc, #172] ; (8001684 ) + 80015d6: f000 ffe1 bl 800259c + + /*Configure GPIO pin : CS_I2C_SPI_Pin */ + GPIO_InitStruct.Pin = CS_I2C_SPI_Pin; + 80015da: 2308 movs r3, #8 + 80015dc: 61fb str r3, [r7, #28] + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 80015de: 2301 movs r3, #1 + 80015e0: 623b str r3, [r7, #32] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80015e2: 2300 movs r3, #0 + 80015e4: 627b str r3, [r7, #36] ; 0x24 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 80015e6: 2300 movs r3, #0 + 80015e8: 62bb str r3, [r7, #40] ; 0x28 + HAL_GPIO_Init(CS_I2C_SPI_GPIO_Port, &GPIO_InitStruct); + 80015ea: f107 031c add.w r3, r7, #28 + 80015ee: 4619 mov r1, r3 + 80015f0: 4824 ldr r0, [pc, #144] ; (8001684 ) + 80015f2: f000 ffd3 bl 800259c + + /*Configure GPIO pins : PE4 PE5 MEMS_INT2_Pin */ + GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|MEMS_INT2_Pin; + 80015f6: 2332 movs r3, #50 ; 0x32 + 80015f8: 61fb str r3, [r7, #28] + GPIO_InitStruct.Mode = GPIO_MODE_EVT_RISING; + 80015fa: 4b25 ldr r3, [pc, #148] ; (8001690 ) + 80015fc: 623b str r3, [r7, #32] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80015fe: 2300 movs r3, #0 + 8001600: 627b str r3, [r7, #36] ; 0x24 + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + 8001602: f107 031c add.w r3, r7, #28 + 8001606: 4619 mov r1, r3 + 8001608: 481e ldr r0, [pc, #120] ; (8001684 ) + 800160a: f000 ffc7 bl 800259c + + /*Configure GPIO pin : OTG_FS_PowerSwitchOn_Pin */ + GPIO_InitStruct.Pin = OTG_FS_PowerSwitchOn_Pin; + 800160e: 2301 movs r3, #1 + 8001610: 61fb str r3, [r7, #28] + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 8001612: 2301 movs r3, #1 + 8001614: 623b str r3, [r7, #32] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001616: 2300 movs r3, #0 + 8001618: 627b str r3, [r7, #36] ; 0x24 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 800161a: 2300 movs r3, #0 + 800161c: 62bb str r3, [r7, #40] ; 0x28 + HAL_GPIO_Init(OTG_FS_PowerSwitchOn_GPIO_Port, &GPIO_InitStruct); + 800161e: f107 031c add.w r3, r7, #28 + 8001622: 4619 mov r1, r3 + 8001624: 4818 ldr r0, [pc, #96] ; (8001688 ) + 8001626: f000 ffb9 bl 800259c + + /*Configure GPIO pin : B1_Pin */ + GPIO_InitStruct.Pin = B1_Pin; + 800162a: 2301 movs r3, #1 + 800162c: 61fb str r3, [r7, #28] + GPIO_InitStruct.Mode = GPIO_MODE_EVT_RISING; + 800162e: 4b18 ldr r3, [pc, #96] ; (8001690 ) + 8001630: 623b str r3, [r7, #32] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001632: 2300 movs r3, #0 + 8001634: 627b str r3, [r7, #36] ; 0x24 + HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct); + 8001636: f107 031c add.w r3, r7, #28 + 800163a: 4619 mov r1, r3 + 800163c: 4815 ldr r0, [pc, #84] ; (8001694 ) + 800163e: f000 ffad bl 800259c + + /*Configure GPIO pins : LD4_Pin LD3_Pin LD5_Pin LD6_Pin + Audio_RST_Pin */ + GPIO_InitStruct.Pin = LD4_Pin|LD3_Pin|LD5_Pin|LD6_Pin + 8001642: f24f 0310 movw r3, #61456 ; 0xf010 + 8001646: 61fb str r3, [r7, #28] + |Audio_RST_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 8001648: 2301 movs r3, #1 + 800164a: 623b str r3, [r7, #32] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800164c: 2300 movs r3, #0 + 800164e: 627b str r3, [r7, #36] ; 0x24 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8001650: 2300 movs r3, #0 + 8001652: 62bb str r3, [r7, #40] ; 0x28 + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + 8001654: f107 031c add.w r3, r7, #28 + 8001658: 4619 mov r1, r3 + 800165a: 480c ldr r0, [pc, #48] ; (800168c ) + 800165c: f000 ff9e bl 800259c + + /*Configure GPIO pin : OTG_FS_OverCurrent_Pin */ + GPIO_InitStruct.Pin = OTG_FS_OverCurrent_Pin; + 8001660: 2320 movs r3, #32 + 8001662: 61fb str r3, [r7, #28] + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + 8001664: 2300 movs r3, #0 + 8001666: 623b str r3, [r7, #32] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001668: 2300 movs r3, #0 + 800166a: 627b str r3, [r7, #36] ; 0x24 + HAL_GPIO_Init(OTG_FS_OverCurrent_GPIO_Port, &GPIO_InitStruct); + 800166c: f107 031c add.w r3, r7, #28 + 8001670: 4619 mov r1, r3 + 8001672: 4806 ldr r0, [pc, #24] ; (800168c ) + 8001674: f000 ff92 bl 800259c + +} + 8001678: bf00 nop + 800167a: 3730 adds r7, #48 ; 0x30 + 800167c: 46bd mov sp, r7 + 800167e: bd80 pop {r7, pc} + 8001680: 40023800 .word 0x40023800 + 8001684: 40021000 .word 0x40021000 + 8001688: 40020800 .word 0x40020800 + 800168c: 40020c00 .word 0x40020c00 + 8001690: 10120000 .word 0x10120000 + 8001694: 40020000 .word 0x40020000 + +08001698 : +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + 8001698: b480 push {r7} + 800169a: af00 add r7, sp, #0 + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); + 800169c: b672 cpsid i + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + 800169e: e7fe b.n 800169e + +080016a0 : +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + 80016a0: b580 push {r7, lr} + 80016a2: b082 sub sp, #8 + 80016a4: af00 add r7, sp, #0 + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_SYSCFG_CLK_ENABLE(); + 80016a6: 2300 movs r3, #0 + 80016a8: 607b str r3, [r7, #4] + 80016aa: 4b10 ldr r3, [pc, #64] ; (80016ec ) + 80016ac: 6c5b ldr r3, [r3, #68] ; 0x44 + 80016ae: 4a0f ldr r2, [pc, #60] ; (80016ec ) + 80016b0: f443 4380 orr.w r3, r3, #16384 ; 0x4000 + 80016b4: 6453 str r3, [r2, #68] ; 0x44 + 80016b6: 4b0d ldr r3, [pc, #52] ; (80016ec ) + 80016b8: 6c5b ldr r3, [r3, #68] ; 0x44 + 80016ba: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 80016be: 607b str r3, [r7, #4] + 80016c0: 687b ldr r3, [r7, #4] + __HAL_RCC_PWR_CLK_ENABLE(); + 80016c2: 2300 movs r3, #0 + 80016c4: 603b str r3, [r7, #0] + 80016c6: 4b09 ldr r3, [pc, #36] ; (80016ec ) + 80016c8: 6c1b ldr r3, [r3, #64] ; 0x40 + 80016ca: 4a08 ldr r2, [pc, #32] ; (80016ec ) + 80016cc: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 80016d0: 6413 str r3, [r2, #64] ; 0x40 + 80016d2: 4b06 ldr r3, [pc, #24] ; (80016ec ) + 80016d4: 6c1b ldr r3, [r3, #64] ; 0x40 + 80016d6: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 80016da: 603b str r3, [r7, #0] + 80016dc: 683b ldr r3, [r7, #0] + + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_0); + 80016de: 2007 movs r0, #7 + 80016e0: f000 ff1a bl 8002518 + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + 80016e4: bf00 nop + 80016e6: 3708 adds r7, #8 + 80016e8: 46bd mov sp, r7 + 80016ea: bd80 pop {r7, pc} + 80016ec: 40023800 .word 0x40023800 + +080016f0 : +* This function configures the hardware resources used in this example +* @param hi2c: I2C handle pointer +* @retval None +*/ +void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c) +{ + 80016f0: b580 push {r7, lr} + 80016f2: b08a sub sp, #40 ; 0x28 + 80016f4: af00 add r7, sp, #0 + 80016f6: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 80016f8: f107 0314 add.w r3, r7, #20 + 80016fc: 2200 movs r2, #0 + 80016fe: 601a str r2, [r3, #0] + 8001700: 605a str r2, [r3, #4] + 8001702: 609a str r2, [r3, #8] + 8001704: 60da str r2, [r3, #12] + 8001706: 611a str r2, [r3, #16] + if(hi2c->Instance==I2C1) + 8001708: 687b ldr r3, [r7, #4] + 800170a: 681b ldr r3, [r3, #0] + 800170c: 4a19 ldr r2, [pc, #100] ; (8001774 ) + 800170e: 4293 cmp r3, r2 + 8001710: d12c bne.n 800176c + { + /* USER CODE BEGIN I2C1_MspInit 0 */ + + /* USER CODE END I2C1_MspInit 0 */ + + __HAL_RCC_GPIOB_CLK_ENABLE(); + 8001712: 2300 movs r3, #0 + 8001714: 613b str r3, [r7, #16] + 8001716: 4b18 ldr r3, [pc, #96] ; (8001778 ) + 8001718: 6b1b ldr r3, [r3, #48] ; 0x30 + 800171a: 4a17 ldr r2, [pc, #92] ; (8001778 ) + 800171c: f043 0302 orr.w r3, r3, #2 + 8001720: 6313 str r3, [r2, #48] ; 0x30 + 8001722: 4b15 ldr r3, [pc, #84] ; (8001778 ) + 8001724: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001726: f003 0302 and.w r3, r3, #2 + 800172a: 613b str r3, [r7, #16] + 800172c: 693b ldr r3, [r7, #16] + /**I2C1 GPIO Configuration + PB6 ------> I2C1_SCL + PB9 ------> I2C1_SDA + */ + GPIO_InitStruct.Pin = Audio_SCL_Pin|Audio_SDA_Pin; + 800172e: f44f 7310 mov.w r3, #576 ; 0x240 + 8001732: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + 8001734: 2312 movs r3, #18 + 8001736: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_PULLUP; + 8001738: 2301 movs r3, #1 + 800173a: 61fb str r3, [r7, #28] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 800173c: 2300 movs r3, #0 + 800173e: 623b str r3, [r7, #32] + GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; + 8001740: 2304 movs r3, #4 + 8001742: 627b str r3, [r7, #36] ; 0x24 + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 8001744: f107 0314 add.w r3, r7, #20 + 8001748: 4619 mov r1, r3 + 800174a: 480c ldr r0, [pc, #48] ; (800177c ) + 800174c: f000 ff26 bl 800259c + + /* Peripheral clock enable */ + __HAL_RCC_I2C1_CLK_ENABLE(); + 8001750: 2300 movs r3, #0 + 8001752: 60fb str r3, [r7, #12] + 8001754: 4b08 ldr r3, [pc, #32] ; (8001778 ) + 8001756: 6c1b ldr r3, [r3, #64] ; 0x40 + 8001758: 4a07 ldr r2, [pc, #28] ; (8001778 ) + 800175a: f443 1300 orr.w r3, r3, #2097152 ; 0x200000 + 800175e: 6413 str r3, [r2, #64] ; 0x40 + 8001760: 4b05 ldr r3, [pc, #20] ; (8001778 ) + 8001762: 6c1b ldr r3, [r3, #64] ; 0x40 + 8001764: f403 1300 and.w r3, r3, #2097152 ; 0x200000 + 8001768: 60fb str r3, [r7, #12] + 800176a: 68fb ldr r3, [r7, #12] + /* USER CODE BEGIN I2C1_MspInit 1 */ + + /* USER CODE END I2C1_MspInit 1 */ + } + +} + 800176c: bf00 nop + 800176e: 3728 adds r7, #40 ; 0x28 + 8001770: 46bd mov sp, r7 + 8001772: bd80 pop {r7, pc} + 8001774: 40005400 .word 0x40005400 + 8001778: 40023800 .word 0x40023800 + 800177c: 40020400 .word 0x40020400 + +08001780 : +* This function configures the hardware resources used in this example +* @param hi2s: I2S handle pointer +* @retval None +*/ +void HAL_I2S_MspInit(I2S_HandleTypeDef* hi2s) +{ + 8001780: b580 push {r7, lr} + 8001782: b08e sub sp, #56 ; 0x38 + 8001784: af00 add r7, sp, #0 + 8001786: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8001788: f107 0324 add.w r3, r7, #36 ; 0x24 + 800178c: 2200 movs r2, #0 + 800178e: 601a str r2, [r3, #0] + 8001790: 605a str r2, [r3, #4] + 8001792: 609a str r2, [r3, #8] + 8001794: 60da str r2, [r3, #12] + 8001796: 611a str r2, [r3, #16] + if(hi2s->Instance==SPI2) + 8001798: 687b ldr r3, [r7, #4] + 800179a: 681b ldr r3, [r3, #0] + 800179c: 4a51 ldr r2, [pc, #324] ; (80018e4 ) + 800179e: 4293 cmp r3, r2 + 80017a0: d14b bne.n 800183a + { + /* USER CODE BEGIN SPI2_MspInit 0 */ + + /* USER CODE END SPI2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI2_CLK_ENABLE(); + 80017a2: 2300 movs r3, #0 + 80017a4: 623b str r3, [r7, #32] + 80017a6: 4b50 ldr r3, [pc, #320] ; (80018e8 ) + 80017a8: 6c1b ldr r3, [r3, #64] ; 0x40 + 80017aa: 4a4f ldr r2, [pc, #316] ; (80018e8 ) + 80017ac: f443 4380 orr.w r3, r3, #16384 ; 0x4000 + 80017b0: 6413 str r3, [r2, #64] ; 0x40 + 80017b2: 4b4d ldr r3, [pc, #308] ; (80018e8 ) + 80017b4: 6c1b ldr r3, [r3, #64] ; 0x40 + 80017b6: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 80017ba: 623b str r3, [r7, #32] + 80017bc: 6a3b ldr r3, [r7, #32] + + __HAL_RCC_GPIOC_CLK_ENABLE(); + 80017be: 2300 movs r3, #0 + 80017c0: 61fb str r3, [r7, #28] + 80017c2: 4b49 ldr r3, [pc, #292] ; (80018e8 ) + 80017c4: 6b1b ldr r3, [r3, #48] ; 0x30 + 80017c6: 4a48 ldr r2, [pc, #288] ; (80018e8 ) + 80017c8: f043 0304 orr.w r3, r3, #4 + 80017cc: 6313 str r3, [r2, #48] ; 0x30 + 80017ce: 4b46 ldr r3, [pc, #280] ; (80018e8 ) + 80017d0: 6b1b ldr r3, [r3, #48] ; 0x30 + 80017d2: f003 0304 and.w r3, r3, #4 + 80017d6: 61fb str r3, [r7, #28] + 80017d8: 69fb ldr r3, [r7, #28] + __HAL_RCC_GPIOB_CLK_ENABLE(); + 80017da: 2300 movs r3, #0 + 80017dc: 61bb str r3, [r7, #24] + 80017de: 4b42 ldr r3, [pc, #264] ; (80018e8 ) + 80017e0: 6b1b ldr r3, [r3, #48] ; 0x30 + 80017e2: 4a41 ldr r2, [pc, #260] ; (80018e8 ) + 80017e4: f043 0302 orr.w r3, r3, #2 + 80017e8: 6313 str r3, [r2, #48] ; 0x30 + 80017ea: 4b3f ldr r3, [pc, #252] ; (80018e8 ) + 80017ec: 6b1b ldr r3, [r3, #48] ; 0x30 + 80017ee: f003 0302 and.w r3, r3, #2 + 80017f2: 61bb str r3, [r7, #24] + 80017f4: 69bb ldr r3, [r7, #24] + /**I2S2 GPIO Configuration + PC3 ------> I2S2_SD + PB10 ------> I2S2_CK + PB12 ------> I2S2_WS + */ + GPIO_InitStruct.Pin = PDM_OUT_Pin; + 80017f6: 2308 movs r3, #8 + 80017f8: 627b str r3, [r7, #36] ; 0x24 + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 80017fa: 2302 movs r3, #2 + 80017fc: 62bb str r3, [r7, #40] ; 0x28 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80017fe: 2300 movs r3, #0 + 8001800: 62fb str r3, [r7, #44] ; 0x2c + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8001802: 2300 movs r3, #0 + 8001804: 633b str r3, [r7, #48] ; 0x30 + GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; + 8001806: 2305 movs r3, #5 + 8001808: 637b str r3, [r7, #52] ; 0x34 + HAL_GPIO_Init(PDM_OUT_GPIO_Port, &GPIO_InitStruct); + 800180a: f107 0324 add.w r3, r7, #36 ; 0x24 + 800180e: 4619 mov r1, r3 + 8001810: 4836 ldr r0, [pc, #216] ; (80018ec ) + 8001812: f000 fec3 bl 800259c + + GPIO_InitStruct.Pin = CLK_IN_Pin|GPIO_PIN_12; + 8001816: f44f 53a0 mov.w r3, #5120 ; 0x1400 + 800181a: 627b str r3, [r7, #36] ; 0x24 + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 800181c: 2302 movs r3, #2 + 800181e: 62bb str r3, [r7, #40] ; 0x28 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001820: 2300 movs r3, #0 + 8001822: 62fb str r3, [r7, #44] ; 0x2c + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8001824: 2300 movs r3, #0 + 8001826: 633b str r3, [r7, #48] ; 0x30 + GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; + 8001828: 2305 movs r3, #5 + 800182a: 637b str r3, [r7, #52] ; 0x34 + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 800182c: f107 0324 add.w r3, r7, #36 ; 0x24 + 8001830: 4619 mov r1, r3 + 8001832: 482f ldr r0, [pc, #188] ; (80018f0 ) + 8001834: f000 feb2 bl 800259c + /* USER CODE BEGIN SPI3_MspInit 1 */ + + /* USER CODE END SPI3_MspInit 1 */ + } + +} + 8001838: e04f b.n 80018da + else if(hi2s->Instance==SPI3) + 800183a: 687b ldr r3, [r7, #4] + 800183c: 681b ldr r3, [r3, #0] + 800183e: 4a2d ldr r2, [pc, #180] ; (80018f4 ) + 8001840: 4293 cmp r3, r2 + 8001842: d14a bne.n 80018da + __HAL_RCC_SPI3_CLK_ENABLE(); + 8001844: 2300 movs r3, #0 + 8001846: 617b str r3, [r7, #20] + 8001848: 4b27 ldr r3, [pc, #156] ; (80018e8 ) + 800184a: 6c1b ldr r3, [r3, #64] ; 0x40 + 800184c: 4a26 ldr r2, [pc, #152] ; (80018e8 ) + 800184e: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 8001852: 6413 str r3, [r2, #64] ; 0x40 + 8001854: 4b24 ldr r3, [pc, #144] ; (80018e8 ) + 8001856: 6c1b ldr r3, [r3, #64] ; 0x40 + 8001858: f403 4300 and.w r3, r3, #32768 ; 0x8000 + 800185c: 617b str r3, [r7, #20] + 800185e: 697b ldr r3, [r7, #20] + __HAL_RCC_GPIOA_CLK_ENABLE(); + 8001860: 2300 movs r3, #0 + 8001862: 613b str r3, [r7, #16] + 8001864: 4b20 ldr r3, [pc, #128] ; (80018e8 ) + 8001866: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001868: 4a1f ldr r2, [pc, #124] ; (80018e8 ) + 800186a: f043 0301 orr.w r3, r3, #1 + 800186e: 6313 str r3, [r2, #48] ; 0x30 + 8001870: 4b1d ldr r3, [pc, #116] ; (80018e8 ) + 8001872: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001874: f003 0301 and.w r3, r3, #1 + 8001878: 613b str r3, [r7, #16] + 800187a: 693b ldr r3, [r7, #16] + __HAL_RCC_GPIOC_CLK_ENABLE(); + 800187c: 2300 movs r3, #0 + 800187e: 60fb str r3, [r7, #12] + 8001880: 4b19 ldr r3, [pc, #100] ; (80018e8 ) + 8001882: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001884: 4a18 ldr r2, [pc, #96] ; (80018e8 ) + 8001886: f043 0304 orr.w r3, r3, #4 + 800188a: 6313 str r3, [r2, #48] ; 0x30 + 800188c: 4b16 ldr r3, [pc, #88] ; (80018e8 ) + 800188e: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001890: f003 0304 and.w r3, r3, #4 + 8001894: 60fb str r3, [r7, #12] + 8001896: 68fb ldr r3, [r7, #12] + GPIO_InitStruct.Pin = I2S3_WS_Pin; + 8001898: 2310 movs r3, #16 + 800189a: 627b str r3, [r7, #36] ; 0x24 + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 800189c: 2302 movs r3, #2 + 800189e: 62bb str r3, [r7, #40] ; 0x28 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80018a0: 2300 movs r3, #0 + 80018a2: 62fb str r3, [r7, #44] ; 0x2c + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 80018a4: 2300 movs r3, #0 + 80018a6: 633b str r3, [r7, #48] ; 0x30 + GPIO_InitStruct.Alternate = GPIO_AF6_SPI3; + 80018a8: 2306 movs r3, #6 + 80018aa: 637b str r3, [r7, #52] ; 0x34 + HAL_GPIO_Init(I2S3_WS_GPIO_Port, &GPIO_InitStruct); + 80018ac: f107 0324 add.w r3, r7, #36 ; 0x24 + 80018b0: 4619 mov r1, r3 + 80018b2: 4811 ldr r0, [pc, #68] ; (80018f8 ) + 80018b4: f000 fe72 bl 800259c + GPIO_InitStruct.Pin = I2S3_MCK_Pin|I2S3_SCK_Pin|I2S3_SD_Pin; + 80018b8: f44f 53a4 mov.w r3, #5248 ; 0x1480 + 80018bc: 627b str r3, [r7, #36] ; 0x24 + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 80018be: 2302 movs r3, #2 + 80018c0: 62bb str r3, [r7, #40] ; 0x28 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80018c2: 2300 movs r3, #0 + 80018c4: 62fb str r3, [r7, #44] ; 0x2c + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 80018c6: 2300 movs r3, #0 + 80018c8: 633b str r3, [r7, #48] ; 0x30 + GPIO_InitStruct.Alternate = GPIO_AF6_SPI3; + 80018ca: 2306 movs r3, #6 + 80018cc: 637b str r3, [r7, #52] ; 0x34 + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + 80018ce: f107 0324 add.w r3, r7, #36 ; 0x24 + 80018d2: 4619 mov r1, r3 + 80018d4: 4805 ldr r0, [pc, #20] ; (80018ec ) + 80018d6: f000 fe61 bl 800259c +} + 80018da: bf00 nop + 80018dc: 3738 adds r7, #56 ; 0x38 + 80018de: 46bd mov sp, r7 + 80018e0: bd80 pop {r7, pc} + 80018e2: bf00 nop + 80018e4: 40003800 .word 0x40003800 + 80018e8: 40023800 .word 0x40023800 + 80018ec: 40020800 .word 0x40020800 + 80018f0: 40020400 .word 0x40020400 + 80018f4: 40003c00 .word 0x40003c00 + 80018f8: 40020000 .word 0x40020000 + +080018fc : +* This function configures the hardware resources used in this example +* @param hspi: SPI handle pointer +* @retval None +*/ +void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) +{ + 80018fc: b580 push {r7, lr} + 80018fe: b08a sub sp, #40 ; 0x28 + 8001900: af00 add r7, sp, #0 + 8001902: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8001904: f107 0314 add.w r3, r7, #20 + 8001908: 2200 movs r2, #0 + 800190a: 601a str r2, [r3, #0] + 800190c: 605a str r2, [r3, #4] + 800190e: 609a str r2, [r3, #8] + 8001910: 60da str r2, [r3, #12] + 8001912: 611a str r2, [r3, #16] + if(hspi->Instance==SPI1) + 8001914: 687b ldr r3, [r7, #4] + 8001916: 681b ldr r3, [r3, #0] + 8001918: 4a19 ldr r2, [pc, #100] ; (8001980 ) + 800191a: 4293 cmp r3, r2 + 800191c: d12b bne.n 8001976 + { + /* USER CODE BEGIN SPI1_MspInit 0 */ + + /* USER CODE END SPI1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI1_CLK_ENABLE(); + 800191e: 2300 movs r3, #0 + 8001920: 613b str r3, [r7, #16] + 8001922: 4b18 ldr r3, [pc, #96] ; (8001984 ) + 8001924: 6c5b ldr r3, [r3, #68] ; 0x44 + 8001926: 4a17 ldr r2, [pc, #92] ; (8001984 ) + 8001928: f443 5380 orr.w r3, r3, #4096 ; 0x1000 + 800192c: 6453 str r3, [r2, #68] ; 0x44 + 800192e: 4b15 ldr r3, [pc, #84] ; (8001984 ) + 8001930: 6c5b ldr r3, [r3, #68] ; 0x44 + 8001932: f403 5380 and.w r3, r3, #4096 ; 0x1000 + 8001936: 613b str r3, [r7, #16] + 8001938: 693b ldr r3, [r7, #16] + + __HAL_RCC_GPIOA_CLK_ENABLE(); + 800193a: 2300 movs r3, #0 + 800193c: 60fb str r3, [r7, #12] + 800193e: 4b11 ldr r3, [pc, #68] ; (8001984 ) + 8001940: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001942: 4a10 ldr r2, [pc, #64] ; (8001984 ) + 8001944: f043 0301 orr.w r3, r3, #1 + 8001948: 6313 str r3, [r2, #48] ; 0x30 + 800194a: 4b0e ldr r3, [pc, #56] ; (8001984 ) + 800194c: 6b1b ldr r3, [r3, #48] ; 0x30 + 800194e: f003 0301 and.w r3, r3, #1 + 8001952: 60fb str r3, [r7, #12] + 8001954: 68fb ldr r3, [r7, #12] + /**SPI1 GPIO Configuration + PA5 ------> SPI1_SCK + PA6 ------> SPI1_MISO + PA7 ------> SPI1_MOSI + */ + GPIO_InitStruct.Pin = SPI1_SCK_Pin|SPI1_MISO_Pin|SPI1_MISOA7_Pin; + 8001956: 23e0 movs r3, #224 ; 0xe0 + 8001958: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 800195a: 2302 movs r3, #2 + 800195c: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800195e: 2300 movs r3, #0 + 8001960: 61fb str r3, [r7, #28] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 8001962: 2303 movs r3, #3 + 8001964: 623b str r3, [r7, #32] + GPIO_InitStruct.Alternate = GPIO_AF5_SPI1; + 8001966: 2305 movs r3, #5 + 8001968: 627b str r3, [r7, #36] ; 0x24 + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 800196a: f107 0314 add.w r3, r7, #20 + 800196e: 4619 mov r1, r3 + 8001970: 4805 ldr r0, [pc, #20] ; (8001988 ) + 8001972: f000 fe13 bl 800259c + /* USER CODE BEGIN SPI1_MspInit 1 */ + + /* USER CODE END SPI1_MspInit 1 */ + } + +} + 8001976: bf00 nop + 8001978: 3728 adds r7, #40 ; 0x28 + 800197a: 46bd mov sp, r7 + 800197c: bd80 pop {r7, pc} + 800197e: bf00 nop + 8001980: 40013000 .word 0x40013000 + 8001984: 40023800 .word 0x40023800 + 8001988: 40020000 .word 0x40020000 + +0800198c : +* This function configures the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspInit(UART_HandleTypeDef* huart) +{ + 800198c: b580 push {r7, lr} + 800198e: b08a sub sp, #40 ; 0x28 + 8001990: af00 add r7, sp, #0 + 8001992: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8001994: f107 0314 add.w r3, r7, #20 + 8001998: 2200 movs r2, #0 + 800199a: 601a str r2, [r3, #0] + 800199c: 605a str r2, [r3, #4] + 800199e: 609a str r2, [r3, #8] + 80019a0: 60da str r2, [r3, #12] + 80019a2: 611a str r2, [r3, #16] + if(huart->Instance==USART2) + 80019a4: 687b ldr r3, [r7, #4] + 80019a6: 681b ldr r3, [r3, #0] + 80019a8: 4a19 ldr r2, [pc, #100] ; (8001a10 ) + 80019aa: 4293 cmp r3, r2 + 80019ac: d12b bne.n 8001a06 + { + /* USER CODE BEGIN USART2_MspInit 0 */ + + /* USER CODE END USART2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_USART2_CLK_ENABLE(); + 80019ae: 2300 movs r3, #0 + 80019b0: 613b str r3, [r7, #16] + 80019b2: 4b18 ldr r3, [pc, #96] ; (8001a14 ) + 80019b4: 6c1b ldr r3, [r3, #64] ; 0x40 + 80019b6: 4a17 ldr r2, [pc, #92] ; (8001a14 ) + 80019b8: f443 3300 orr.w r3, r3, #131072 ; 0x20000 + 80019bc: 6413 str r3, [r2, #64] ; 0x40 + 80019be: 4b15 ldr r3, [pc, #84] ; (8001a14 ) + 80019c0: 6c1b ldr r3, [r3, #64] ; 0x40 + 80019c2: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 80019c6: 613b str r3, [r7, #16] + 80019c8: 693b ldr r3, [r7, #16] + + __HAL_RCC_GPIOA_CLK_ENABLE(); + 80019ca: 2300 movs r3, #0 + 80019cc: 60fb str r3, [r7, #12] + 80019ce: 4b11 ldr r3, [pc, #68] ; (8001a14 ) + 80019d0: 6b1b ldr r3, [r3, #48] ; 0x30 + 80019d2: 4a10 ldr r2, [pc, #64] ; (8001a14 ) + 80019d4: f043 0301 orr.w r3, r3, #1 + 80019d8: 6313 str r3, [r2, #48] ; 0x30 + 80019da: 4b0e ldr r3, [pc, #56] ; (8001a14 ) + 80019dc: 6b1b ldr r3, [r3, #48] ; 0x30 + 80019de: f003 0301 and.w r3, r3, #1 + 80019e2: 60fb str r3, [r7, #12] + 80019e4: 68fb ldr r3, [r7, #12] + /**USART2 GPIO Configuration + PA2 ------> USART2_TX + PA3 ------> USART2_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; + 80019e6: 230c movs r3, #12 + 80019e8: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 80019ea: 2302 movs r3, #2 + 80019ec: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80019ee: 2300 movs r3, #0 + 80019f0: 61fb str r3, [r7, #28] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 80019f2: 2303 movs r3, #3 + 80019f4: 623b str r3, [r7, #32] + GPIO_InitStruct.Alternate = GPIO_AF7_USART2; + 80019f6: 2307 movs r3, #7 + 80019f8: 627b str r3, [r7, #36] ; 0x24 + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 80019fa: f107 0314 add.w r3, r7, #20 + 80019fe: 4619 mov r1, r3 + 8001a00: 4805 ldr r0, [pc, #20] ; (8001a18 ) + 8001a02: f000 fdcb bl 800259c + /* USER CODE BEGIN USART2_MspInit 1 */ + + /* USER CODE END USART2_MspInit 1 */ + } + +} + 8001a06: bf00 nop + 8001a08: 3728 adds r7, #40 ; 0x28 + 8001a0a: 46bd mov sp, r7 + 8001a0c: bd80 pop {r7, pc} + 8001a0e: bf00 nop + 8001a10: 40004400 .word 0x40004400 + 8001a14: 40023800 .word 0x40023800 + 8001a18: 40020000 .word 0x40020000 + +08001a1c : +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + 8001a1c: b480 push {r7} + 8001a1e: af00 add r7, sp, #0 + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + 8001a20: e7fe b.n 8001a20 + +08001a22 : + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + 8001a22: b480 push {r7} + 8001a24: af00 add r7, sp, #0 + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + 8001a26: e7fe b.n 8001a26 + +08001a28 : + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + 8001a28: b480 push {r7} + 8001a2a: af00 add r7, sp, #0 + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + 8001a2c: e7fe b.n 8001a2c + +08001a2e : + +/** + * @brief This function handles Pre-fetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + 8001a2e: b480 push {r7} + 8001a30: af00 add r7, sp, #0 + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + 8001a32: e7fe b.n 8001a32 + +08001a34 : + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + 8001a34: b480 push {r7} + 8001a36: af00 add r7, sp, #0 + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + 8001a38: e7fe b.n 8001a38 + +08001a3a : + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + 8001a3a: b480 push {r7} + 8001a3c: af00 add r7, sp, #0 + + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ + + /* USER CODE END SVCall_IRQn 1 */ +} + 8001a3e: bf00 nop + 8001a40: 46bd mov sp, r7 + 8001a42: f85d 7b04 ldr.w r7, [sp], #4 + 8001a46: 4770 bx lr + +08001a48 : + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + 8001a48: b480 push {r7} + 8001a4a: af00 add r7, sp, #0 + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + 8001a4c: bf00 nop + 8001a4e: 46bd mov sp, r7 + 8001a50: f85d 7b04 ldr.w r7, [sp], #4 + 8001a54: 4770 bx lr + +08001a56 : + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + 8001a56: b480 push {r7} + 8001a58: af00 add r7, sp, #0 + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + 8001a5a: bf00 nop + 8001a5c: 46bd mov sp, r7 + 8001a5e: f85d 7b04 ldr.w r7, [sp], #4 + 8001a62: 4770 bx lr + +08001a64 : + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + 8001a64: b580 push {r7, lr} + 8001a66: af00 add r7, sp, #0 + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + 8001a68: f000 fc44 bl 80022f4 + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + 8001a6c: bf00 nop + 8001a6e: bd80 pop {r7, pc} + +08001a70 : + +/** + * @brief This function handles USB On The Go FS global interrupt. + */ +void OTG_FS_IRQHandler(void) +{ + 8001a70: b580 push {r7, lr} + 8001a72: af00 add r7, sp, #0 + /* USER CODE BEGIN OTG_FS_IRQn 0 */ + + /* USER CODE END OTG_FS_IRQn 0 */ + HAL_HCD_IRQHandler(&hhcd_USB_OTG_FS); + 8001a74: 4802 ldr r0, [pc, #8] ; (8001a80 ) + 8001a76: f001 f9bb bl 8002df0 + /* USER CODE BEGIN OTG_FS_IRQn 1 */ + + /* USER CODE END OTG_FS_IRQn 1 */ +} + 8001a7a: bf00 nop + 8001a7c: bd80 pop {r7, pc} + 8001a7e: bf00 nop + 8001a80: 200007ec .word 0x200007ec + +08001a84 <_read>: + _kill(status, -1); + while (1) {} /* Make sure we hang here */ +} + +__attribute__((weak)) int _read(int file, char *ptr, int len) +{ + 8001a84: b580 push {r7, lr} + 8001a86: b086 sub sp, #24 + 8001a88: af00 add r7, sp, #0 + 8001a8a: 60f8 str r0, [r7, #12] + 8001a8c: 60b9 str r1, [r7, #8] + 8001a8e: 607a str r2, [r7, #4] + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + 8001a90: 2300 movs r3, #0 + 8001a92: 617b str r3, [r7, #20] + 8001a94: e00a b.n 8001aac <_read+0x28> + { + *ptr++ = __io_getchar(); + 8001a96: f3af 8000 nop.w + 8001a9a: 4601 mov r1, r0 + 8001a9c: 68bb ldr r3, [r7, #8] + 8001a9e: 1c5a adds r2, r3, #1 + 8001aa0: 60ba str r2, [r7, #8] + 8001aa2: b2ca uxtb r2, r1 + 8001aa4: 701a strb r2, [r3, #0] + for (DataIdx = 0; DataIdx < len; DataIdx++) + 8001aa6: 697b ldr r3, [r7, #20] + 8001aa8: 3301 adds r3, #1 + 8001aaa: 617b str r3, [r7, #20] + 8001aac: 697a ldr r2, [r7, #20] + 8001aae: 687b ldr r3, [r7, #4] + 8001ab0: 429a cmp r2, r3 + 8001ab2: dbf0 blt.n 8001a96 <_read+0x12> + } + +return len; + 8001ab4: 687b ldr r3, [r7, #4] +} + 8001ab6: 4618 mov r0, r3 + 8001ab8: 3718 adds r7, #24 + 8001aba: 46bd mov sp, r7 + 8001abc: bd80 pop {r7, pc} + +08001abe <_write>: + +__attribute__((weak)) int _write(int file, char *ptr, int len) +{ + 8001abe: b580 push {r7, lr} + 8001ac0: b086 sub sp, #24 + 8001ac2: af00 add r7, sp, #0 + 8001ac4: 60f8 str r0, [r7, #12] + 8001ac6: 60b9 str r1, [r7, #8] + 8001ac8: 607a str r2, [r7, #4] + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + 8001aca: 2300 movs r3, #0 + 8001acc: 617b str r3, [r7, #20] + 8001ace: e009 b.n 8001ae4 <_write+0x26> + { + __io_putchar(*ptr++); + 8001ad0: 68bb ldr r3, [r7, #8] + 8001ad2: 1c5a adds r2, r3, #1 + 8001ad4: 60ba str r2, [r7, #8] + 8001ad6: 781b ldrb r3, [r3, #0] + 8001ad8: 4618 mov r0, r3 + 8001ada: f7ff fb65 bl 80011a8 <__io_putchar> + for (DataIdx = 0; DataIdx < len; DataIdx++) + 8001ade: 697b ldr r3, [r7, #20] + 8001ae0: 3301 adds r3, #1 + 8001ae2: 617b str r3, [r7, #20] + 8001ae4: 697a ldr r2, [r7, #20] + 8001ae6: 687b ldr r3, [r7, #4] + 8001ae8: 429a cmp r2, r3 + 8001aea: dbf1 blt.n 8001ad0 <_write+0x12> + } + return len; + 8001aec: 687b ldr r3, [r7, #4] +} + 8001aee: 4618 mov r0, r3 + 8001af0: 3718 adds r7, #24 + 8001af2: 46bd mov sp, r7 + 8001af4: bd80 pop {r7, pc} + +08001af6 <_close>: + +int _close(int file) +{ + 8001af6: b480 push {r7} + 8001af8: b083 sub sp, #12 + 8001afa: af00 add r7, sp, #0 + 8001afc: 6078 str r0, [r7, #4] + return -1; + 8001afe: f04f 33ff mov.w r3, #4294967295 +} + 8001b02: 4618 mov r0, r3 + 8001b04: 370c adds r7, #12 + 8001b06: 46bd mov sp, r7 + 8001b08: f85d 7b04 ldr.w r7, [sp], #4 + 8001b0c: 4770 bx lr + +08001b0e <_fstat>: + + +int _fstat(int file, struct stat *st) +{ + 8001b0e: b480 push {r7} + 8001b10: b083 sub sp, #12 + 8001b12: af00 add r7, sp, #0 + 8001b14: 6078 str r0, [r7, #4] + 8001b16: 6039 str r1, [r7, #0] + st->st_mode = S_IFCHR; + 8001b18: 683b ldr r3, [r7, #0] + 8001b1a: f44f 5200 mov.w r2, #8192 ; 0x2000 + 8001b1e: 605a str r2, [r3, #4] + return 0; + 8001b20: 2300 movs r3, #0 +} + 8001b22: 4618 mov r0, r3 + 8001b24: 370c adds r7, #12 + 8001b26: 46bd mov sp, r7 + 8001b28: f85d 7b04 ldr.w r7, [sp], #4 + 8001b2c: 4770 bx lr + +08001b2e <_isatty>: + +int _isatty(int file) +{ + 8001b2e: b480 push {r7} + 8001b30: b083 sub sp, #12 + 8001b32: af00 add r7, sp, #0 + 8001b34: 6078 str r0, [r7, #4] + return 1; + 8001b36: 2301 movs r3, #1 +} + 8001b38: 4618 mov r0, r3 + 8001b3a: 370c adds r7, #12 + 8001b3c: 46bd mov sp, r7 + 8001b3e: f85d 7b04 ldr.w r7, [sp], #4 + 8001b42: 4770 bx lr + +08001b44 <_lseek>: + +int _lseek(int file, int ptr, int dir) +{ + 8001b44: b480 push {r7} + 8001b46: b085 sub sp, #20 + 8001b48: af00 add r7, sp, #0 + 8001b4a: 60f8 str r0, [r7, #12] + 8001b4c: 60b9 str r1, [r7, #8] + 8001b4e: 607a str r2, [r7, #4] + return 0; + 8001b50: 2300 movs r3, #0 +} + 8001b52: 4618 mov r0, r3 + 8001b54: 3714 adds r7, #20 + 8001b56: 46bd mov sp, r7 + 8001b58: f85d 7b04 ldr.w r7, [sp], #4 + 8001b5c: 4770 bx lr + ... + +08001b60 <_sbrk>: + * + * @param incr Memory size + * @return Pointer to allocated memory + */ +void *_sbrk(ptrdiff_t incr) +{ + 8001b60: b580 push {r7, lr} + 8001b62: b086 sub sp, #24 + 8001b64: af00 add r7, sp, #0 + 8001b66: 6078 str r0, [r7, #4] + extern uint8_t _end; /* Symbol defined in the linker script */ + extern uint8_t _estack; /* Symbol defined in the linker script */ + extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ + const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; + 8001b68: 4a14 ldr r2, [pc, #80] ; (8001bbc <_sbrk+0x5c>) + 8001b6a: 4b15 ldr r3, [pc, #84] ; (8001bc0 <_sbrk+0x60>) + 8001b6c: 1ad3 subs r3, r2, r3 + 8001b6e: 617b str r3, [r7, #20] + const uint8_t *max_heap = (uint8_t *)stack_limit; + 8001b70: 697b ldr r3, [r7, #20] + 8001b72: 613b str r3, [r7, #16] + uint8_t *prev_heap_end; + + /* Initialize heap end at first call */ + if (NULL == __sbrk_heap_end) + 8001b74: 4b13 ldr r3, [pc, #76] ; (8001bc4 <_sbrk+0x64>) + 8001b76: 681b ldr r3, [r3, #0] + 8001b78: 2b00 cmp r3, #0 + 8001b7a: d102 bne.n 8001b82 <_sbrk+0x22> + { + __sbrk_heap_end = &_end; + 8001b7c: 4b11 ldr r3, [pc, #68] ; (8001bc4 <_sbrk+0x64>) + 8001b7e: 4a12 ldr r2, [pc, #72] ; (8001bc8 <_sbrk+0x68>) + 8001b80: 601a str r2, [r3, #0] + } + + /* Protect heap from growing into the reserved MSP stack */ + if (__sbrk_heap_end + incr > max_heap) + 8001b82: 4b10 ldr r3, [pc, #64] ; (8001bc4 <_sbrk+0x64>) + 8001b84: 681a ldr r2, [r3, #0] + 8001b86: 687b ldr r3, [r7, #4] + 8001b88: 4413 add r3, r2 + 8001b8a: 693a ldr r2, [r7, #16] + 8001b8c: 429a cmp r2, r3 + 8001b8e: d207 bcs.n 8001ba0 <_sbrk+0x40> + { + errno = ENOMEM; + 8001b90: f008 fbc4 bl 800a31c <__errno> + 8001b94: 4602 mov r2, r0 + 8001b96: 230c movs r3, #12 + 8001b98: 6013 str r3, [r2, #0] + return (void *)-1; + 8001b9a: f04f 33ff mov.w r3, #4294967295 + 8001b9e: e009 b.n 8001bb4 <_sbrk+0x54> + } + + prev_heap_end = __sbrk_heap_end; + 8001ba0: 4b08 ldr r3, [pc, #32] ; (8001bc4 <_sbrk+0x64>) + 8001ba2: 681b ldr r3, [r3, #0] + 8001ba4: 60fb str r3, [r7, #12] + __sbrk_heap_end += incr; + 8001ba6: 4b07 ldr r3, [pc, #28] ; (8001bc4 <_sbrk+0x64>) + 8001ba8: 681a ldr r2, [r3, #0] + 8001baa: 687b ldr r3, [r7, #4] + 8001bac: 4413 add r3, r2 + 8001bae: 4a05 ldr r2, [pc, #20] ; (8001bc4 <_sbrk+0x64>) + 8001bb0: 6013 str r3, [r2, #0] + + return (void *)prev_heap_end; + 8001bb2: 68fb ldr r3, [r7, #12] +} + 8001bb4: 4618 mov r0, r3 + 8001bb6: 3718 adds r7, #24 + 8001bb8: 46bd mov sp, r7 + 8001bba: bd80 pop {r7, pc} + 8001bbc: 20010000 .word 0x20010000 + 8001bc0: 00000400 .word 0x00000400 + 8001bc4: 20000228 .word 0x20000228 + 8001bc8: 20000ab8 .word 0x20000ab8 + +08001bcc : + * configuration. + * @param None + * @retval None + */ +void SystemInit(void) +{ + 8001bcc: b480 push {r7} + 8001bce: af00 add r7, sp, #0 + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + 8001bd0: 4b08 ldr r3, [pc, #32] ; (8001bf4 ) + 8001bd2: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8001bd6: 4a07 ldr r2, [pc, #28] ; (8001bf4 ) + 8001bd8: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000 + 8001bdc: f8c2 3088 str.w r3, [r2, #136] ; 0x88 + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ + 8001be0: 4b04 ldr r3, [pc, #16] ; (8001bf4 ) + 8001be2: f04f 6200 mov.w r2, #134217728 ; 0x8000000 + 8001be6: 609a str r2, [r3, #8] +#endif +} + 8001be8: bf00 nop + 8001bea: 46bd mov sp, r7 + 8001bec: f85d 7b04 ldr.w r7, [sp], #4 + 8001bf0: 4770 bx lr + 8001bf2: bf00 nop + 8001bf4: e000ed00 .word 0xe000ed00 + +08001bf8 : + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + 8001bf8: f8df d034 ldr.w sp, [pc, #52] ; 8001c30 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + 8001bfc: 2100 movs r1, #0 + b LoopCopyDataInit + 8001bfe: e003 b.n 8001c08 + +08001c00 : + +CopyDataInit: + ldr r3, =_sidata + 8001c00: 4b0c ldr r3, [pc, #48] ; (8001c34 ) + ldr r3, [r3, r1] + 8001c02: 585b ldr r3, [r3, r1] + str r3, [r0, r1] + 8001c04: 5043 str r3, [r0, r1] + adds r1, r1, #4 + 8001c06: 3104 adds r1, #4 + +08001c08 : + +LoopCopyDataInit: + ldr r0, =_sdata + 8001c08: 480b ldr r0, [pc, #44] ; (8001c38 ) + ldr r3, =_edata + 8001c0a: 4b0c ldr r3, [pc, #48] ; (8001c3c ) + adds r2, r0, r1 + 8001c0c: 1842 adds r2, r0, r1 + cmp r2, r3 + 8001c0e: 429a cmp r2, r3 + bcc CopyDataInit + 8001c10: d3f6 bcc.n 8001c00 + ldr r2, =_sbss + 8001c12: 4a0b ldr r2, [pc, #44] ; (8001c40 ) + b LoopFillZerobss + 8001c14: e002 b.n 8001c1c + +08001c16 : +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + 8001c16: 2300 movs r3, #0 + str r3, [r2], #4 + 8001c18: f842 3b04 str.w r3, [r2], #4 + +08001c1c : + +LoopFillZerobss: + ldr r3, = _ebss + 8001c1c: 4b09 ldr r3, [pc, #36] ; (8001c44 ) + cmp r2, r3 + 8001c1e: 429a cmp r2, r3 + bcc FillZerobss + 8001c20: d3f9 bcc.n 8001c16 + +/* Call the clock system intitialization function.*/ + bl SystemInit + 8001c22: f7ff ffd3 bl 8001bcc +/* Call static constructors */ + bl __libc_init_array + 8001c26: f008 fb7f bl 800a328 <__libc_init_array> +/* Call the application's entry point.*/ + bl main + 8001c2a: f7ff facf bl 80011cc
+ bx lr + 8001c2e: 4770 bx lr + ldr sp, =_estack /* set stack pointer */ + 8001c30: 20010000 .word 0x20010000 + ldr r3, =_sidata + 8001c34: 0800ec68 .word 0x0800ec68 + ldr r0, =_sdata + 8001c38: 20000000 .word 0x20000000 + ldr r3, =_edata + 8001c3c: 200001fc .word 0x200001fc + ldr r2, =_sbss + 8001c40: 200001fc .word 0x200001fc + ldr r3, = _ebss + 8001c44: 20000ab4 .word 0x20000ab4 + +08001c48 : + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + 8001c48: e7fe b.n 8001c48 + ... + +08001c4c : + */ + +#include "COMPASS_LEDS.h" + +bool COMPASS_LEDS_Init(COMPASS_LEDS *compassLeds) +{ + 8001c4c: b580 push {r7, lr} + 8001c4e: b082 sub sp, #8 + 8001c50: af00 add r7, sp, #0 + 8001c52: 6078 str r0, [r7, #4] + compassLeds->southLed.Pin = GPIO_PIN_15; + 8001c54: 687b ldr r3, [r7, #4] + 8001c56: f44f 4200 mov.w r2, #32768 ; 0x8000 + 8001c5a: 615a str r2, [r3, #20] + compassLeds->eastLed.Pin = GPIO_PIN_12; + 8001c5c: 687b ldr r3, [r7, #4] + 8001c5e: f44f 5280 mov.w r2, #4096 ; 0x1000 + 8001c62: 63da str r2, [r3, #60] ; 0x3c + compassLeds->northLed.Pin = GPIO_PIN_13; + 8001c64: 687b ldr r3, [r7, #4] + 8001c66: f44f 5200 mov.w r2, #8192 ; 0x2000 + 8001c6a: 601a str r2, [r3, #0] + compassLeds->westLed.Pin = GPIO_PIN_14; + 8001c6c: 687b ldr r3, [r7, #4] + 8001c6e: f44f 4280 mov.w r2, #16384 ; 0x4000 + 8001c72: 629a str r2, [r3, #40] ; 0x28 + + compassLeds->southLed.Mode = GPIO_MODE_OUTPUT_PP; + 8001c74: 687b ldr r3, [r7, #4] + 8001c76: 2201 movs r2, #1 + 8001c78: 619a str r2, [r3, #24] + compassLeds->eastLed.Mode = GPIO_MODE_OUTPUT_PP; + 8001c7a: 687b ldr r3, [r7, #4] + 8001c7c: 2201 movs r2, #1 + 8001c7e: 641a str r2, [r3, #64] ; 0x40 + compassLeds->northLed.Mode = GPIO_MODE_OUTPUT_PP; + 8001c80: 687b ldr r3, [r7, #4] + 8001c82: 2201 movs r2, #1 + 8001c84: 605a str r2, [r3, #4] + compassLeds->westLed.Mode = GPIO_MODE_OUTPUT_PP; + 8001c86: 687b ldr r3, [r7, #4] + 8001c88: 2201 movs r2, #1 + 8001c8a: 62da str r2, [r3, #44] ; 0x2c + + compassLeds->southLed.Speed = GPIO_SPEED_LOW; + 8001c8c: 687b ldr r3, [r7, #4] + 8001c8e: 2200 movs r2, #0 + 8001c90: 621a str r2, [r3, #32] + compassLeds->eastLed.Speed = GPIO_SPEED_LOW; + 8001c92: 687b ldr r3, [r7, #4] + 8001c94: 2200 movs r2, #0 + 8001c96: 649a str r2, [r3, #72] ; 0x48 + compassLeds->northLed.Speed = GPIO_SPEED_LOW; + 8001c98: 687b ldr r3, [r7, #4] + 8001c9a: 2200 movs r2, #0 + 8001c9c: 60da str r2, [r3, #12] + compassLeds->westLed.Speed = GPIO_SPEED_LOW; + 8001c9e: 687b ldr r3, [r7, #4] + 8001ca0: 2200 movs r2, #0 + 8001ca2: 635a str r2, [r3, #52] ; 0x34 + + HAL_GPIO_Init(GPIOD, &compassLeds->southLed); + 8001ca4: 687b ldr r3, [r7, #4] + 8001ca6: 3314 adds r3, #20 + 8001ca8: 4619 mov r1, r3 + 8001caa: 481c ldr r0, [pc, #112] ; (8001d1c ) + 8001cac: f000 fc76 bl 800259c + HAL_GPIO_Init(GPIOD, &compassLeds->eastLed); + 8001cb0: 687b ldr r3, [r7, #4] + 8001cb2: 333c adds r3, #60 ; 0x3c + 8001cb4: 4619 mov r1, r3 + 8001cb6: 4819 ldr r0, [pc, #100] ; (8001d1c ) + 8001cb8: f000 fc70 bl 800259c + HAL_GPIO_Init(GPIOD, &compassLeds->northLed); + 8001cbc: 687b ldr r3, [r7, #4] + 8001cbe: 4619 mov r1, r3 + 8001cc0: 4816 ldr r0, [pc, #88] ; (8001d1c ) + 8001cc2: f000 fc6b bl 800259c + HAL_GPIO_Init(GPIOD, &compassLeds->westLed); + 8001cc6: 687b ldr r3, [r7, #4] + 8001cc8: 3328 adds r3, #40 ; 0x28 + 8001cca: 4619 mov r1, r3 + 8001ccc: 4813 ldr r0, [pc, #76] ; (8001d1c ) + 8001cce: f000 fc65 bl 800259c + + HAL_GPIO_WritePin(GPIOD, compassLeds->southLed.Pin, GPIO_PIN_RESET); + 8001cd2: 687b ldr r3, [r7, #4] + 8001cd4: 695b ldr r3, [r3, #20] + 8001cd6: b29b uxth r3, r3 + 8001cd8: 2200 movs r2, #0 + 8001cda: 4619 mov r1, r3 + 8001cdc: 480f ldr r0, [pc, #60] ; (8001d1c ) + 8001cde: f000 fddf bl 80028a0 + HAL_GPIO_WritePin(GPIOD, compassLeds->eastLed.Pin, GPIO_PIN_RESET); + 8001ce2: 687b ldr r3, [r7, #4] + 8001ce4: 6bdb ldr r3, [r3, #60] ; 0x3c + 8001ce6: b29b uxth r3, r3 + 8001ce8: 2200 movs r2, #0 + 8001cea: 4619 mov r1, r3 + 8001cec: 480b ldr r0, [pc, #44] ; (8001d1c ) + 8001cee: f000 fdd7 bl 80028a0 + HAL_GPIO_WritePin(GPIOD, compassLeds->northLed.Pin, GPIO_PIN_RESET); + 8001cf2: 687b ldr r3, [r7, #4] + 8001cf4: 681b ldr r3, [r3, #0] + 8001cf6: b29b uxth r3, r3 + 8001cf8: 2200 movs r2, #0 + 8001cfa: 4619 mov r1, r3 + 8001cfc: 4807 ldr r0, [pc, #28] ; (8001d1c ) + 8001cfe: f000 fdcf bl 80028a0 + HAL_GPIO_WritePin(GPIOD, compassLeds->westLed.Pin, GPIO_PIN_RESET); + 8001d02: 687b ldr r3, [r7, #4] + 8001d04: 6a9b ldr r3, [r3, #40] ; 0x28 + 8001d06: b29b uxth r3, r3 + 8001d08: 2200 movs r2, #0 + 8001d0a: 4619 mov r1, r3 + 8001d0c: 4803 ldr r0, [pc, #12] ; (8001d1c ) + 8001d0e: f000 fdc7 bl 80028a0 + + return true; + 8001d12: 2301 movs r3, #1 +} + 8001d14: 4618 mov r0, r3 + 8001d16: 3708 adds r7, #8 + 8001d18: 46bd mov sp, r7 + 8001d1a: bd80 pop {r7, pc} + 8001d1c: 40020c00 .word 0x40020c00 + +08001d20 : + +bool COMPASS_LEDS_Light(COMPASS_LEDS *compassLeds, Heading heading) +{ + 8001d20: b580 push {r7, lr} + 8001d22: b082 sub sp, #8 + 8001d24: af00 add r7, sp, #0 + 8001d26: 6078 str r0, [r7, #4] + 8001d28: 460b mov r3, r1 + 8001d2a: 70fb strb r3, [r7, #3] + switch(heading) + 8001d2c: 78fb ldrb r3, [r7, #3] + 8001d2e: 3b01 subs r3, #1 + 8001d30: 2b07 cmp r3, #7 + 8001d32: f200 8097 bhi.w 8001e64 + 8001d36: a201 add r2, pc, #4 ; (adr r2, 8001d3c ) + 8001d38: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8001d3c: 08001d9f .word 0x08001d9f + 8001d40: 08001d5d .word 0x08001d5d + 8001d44: 08001e65 .word 0x08001e65 + 8001d48: 08001e23 .word 0x08001e23 + 8001d4c: 08001e65 .word 0x08001e65 + 8001d50: 08001e65 .word 0x08001e65 + 8001d54: 08001e65 .word 0x08001e65 + 8001d58: 08001de1 .word 0x08001de1 + { + case SOUTH: + HAL_GPIO_WritePin(GPIOD, compassLeds->southLed.Pin, GPIO_PIN_SET); + 8001d5c: 687b ldr r3, [r7, #4] + 8001d5e: 695b ldr r3, [r3, #20] + 8001d60: b29b uxth r3, r3 + 8001d62: 2201 movs r2, #1 + 8001d64: 4619 mov r1, r3 + 8001d66: 4852 ldr r0, [pc, #328] ; (8001eb0 ) + 8001d68: f000 fd9a bl 80028a0 + HAL_GPIO_WritePin(GPIOD, compassLeds->eastLed.Pin, GPIO_PIN_RESET); + 8001d6c: 687b ldr r3, [r7, #4] + 8001d6e: 6bdb ldr r3, [r3, #60] ; 0x3c + 8001d70: b29b uxth r3, r3 + 8001d72: 2200 movs r2, #0 + 8001d74: 4619 mov r1, r3 + 8001d76: 484e ldr r0, [pc, #312] ; (8001eb0 ) + 8001d78: f000 fd92 bl 80028a0 + HAL_GPIO_WritePin(GPIOD, compassLeds->northLed.Pin, GPIO_PIN_RESET); + 8001d7c: 687b ldr r3, [r7, #4] + 8001d7e: 681b ldr r3, [r3, #0] + 8001d80: b29b uxth r3, r3 + 8001d82: 2200 movs r2, #0 + 8001d84: 4619 mov r1, r3 + 8001d86: 484a ldr r0, [pc, #296] ; (8001eb0 ) + 8001d88: f000 fd8a bl 80028a0 + HAL_GPIO_WritePin(GPIOD, compassLeds->westLed.Pin, GPIO_PIN_RESET); + 8001d8c: 687b ldr r3, [r7, #4] + 8001d8e: 6a9b ldr r3, [r3, #40] ; 0x28 + 8001d90: b29b uxth r3, r3 + 8001d92: 2200 movs r2, #0 + 8001d94: 4619 mov r1, r3 + 8001d96: 4846 ldr r0, [pc, #280] ; (8001eb0 ) + 8001d98: f000 fd82 bl 80028a0 + break; + 8001d9c: e082 b.n 8001ea4 + case NORTH: + HAL_GPIO_WritePin(GPIOD, compassLeds->southLed.Pin, GPIO_PIN_RESET); + 8001d9e: 687b ldr r3, [r7, #4] + 8001da0: 695b ldr r3, [r3, #20] + 8001da2: b29b uxth r3, r3 + 8001da4: 2200 movs r2, #0 + 8001da6: 4619 mov r1, r3 + 8001da8: 4841 ldr r0, [pc, #260] ; (8001eb0 ) + 8001daa: f000 fd79 bl 80028a0 + HAL_GPIO_WritePin(GPIOD, compassLeds->eastLed.Pin, GPIO_PIN_RESET); + 8001dae: 687b ldr r3, [r7, #4] + 8001db0: 6bdb ldr r3, [r3, #60] ; 0x3c + 8001db2: b29b uxth r3, r3 + 8001db4: 2200 movs r2, #0 + 8001db6: 4619 mov r1, r3 + 8001db8: 483d ldr r0, [pc, #244] ; (8001eb0 ) + 8001dba: f000 fd71 bl 80028a0 + HAL_GPIO_WritePin(GPIOD, compassLeds->northLed.Pin, GPIO_PIN_SET); + 8001dbe: 687b ldr r3, [r7, #4] + 8001dc0: 681b ldr r3, [r3, #0] + 8001dc2: b29b uxth r3, r3 + 8001dc4: 2201 movs r2, #1 + 8001dc6: 4619 mov r1, r3 + 8001dc8: 4839 ldr r0, [pc, #228] ; (8001eb0 ) + 8001dca: f000 fd69 bl 80028a0 + HAL_GPIO_WritePin(GPIOD, compassLeds->westLed.Pin, GPIO_PIN_RESET); + 8001dce: 687b ldr r3, [r7, #4] + 8001dd0: 6a9b ldr r3, [r3, #40] ; 0x28 + 8001dd2: b29b uxth r3, r3 + 8001dd4: 2200 movs r2, #0 + 8001dd6: 4619 mov r1, r3 + 8001dd8: 4835 ldr r0, [pc, #212] ; (8001eb0 ) + 8001dda: f000 fd61 bl 80028a0 + break; + 8001dde: e061 b.n 8001ea4 + case EAST: + HAL_GPIO_WritePin(GPIOD, compassLeds->southLed.Pin, GPIO_PIN_RESET); + 8001de0: 687b ldr r3, [r7, #4] + 8001de2: 695b ldr r3, [r3, #20] + 8001de4: b29b uxth r3, r3 + 8001de6: 2200 movs r2, #0 + 8001de8: 4619 mov r1, r3 + 8001dea: 4831 ldr r0, [pc, #196] ; (8001eb0 ) + 8001dec: f000 fd58 bl 80028a0 + HAL_GPIO_WritePin(GPIOD, compassLeds->eastLed.Pin, GPIO_PIN_SET); + 8001df0: 687b ldr r3, [r7, #4] + 8001df2: 6bdb ldr r3, [r3, #60] ; 0x3c + 8001df4: b29b uxth r3, r3 + 8001df6: 2201 movs r2, #1 + 8001df8: 4619 mov r1, r3 + 8001dfa: 482d ldr r0, [pc, #180] ; (8001eb0 ) + 8001dfc: f000 fd50 bl 80028a0 + HAL_GPIO_WritePin(GPIOD, compassLeds->northLed.Pin, GPIO_PIN_RESET); + 8001e00: 687b ldr r3, [r7, #4] + 8001e02: 681b ldr r3, [r3, #0] + 8001e04: b29b uxth r3, r3 + 8001e06: 2200 movs r2, #0 + 8001e08: 4619 mov r1, r3 + 8001e0a: 4829 ldr r0, [pc, #164] ; (8001eb0 ) + 8001e0c: f000 fd48 bl 80028a0 + HAL_GPIO_WritePin(GPIOD, compassLeds->westLed.Pin, GPIO_PIN_RESET); + 8001e10: 687b ldr r3, [r7, #4] + 8001e12: 6a9b ldr r3, [r3, #40] ; 0x28 + 8001e14: b29b uxth r3, r3 + 8001e16: 2200 movs r2, #0 + 8001e18: 4619 mov r1, r3 + 8001e1a: 4825 ldr r0, [pc, #148] ; (8001eb0 ) + 8001e1c: f000 fd40 bl 80028a0 + break; + 8001e20: e040 b.n 8001ea4 + case WEST: + HAL_GPIO_WritePin(GPIOD, compassLeds->southLed.Pin, GPIO_PIN_RESET); + 8001e22: 687b ldr r3, [r7, #4] + 8001e24: 695b ldr r3, [r3, #20] + 8001e26: b29b uxth r3, r3 + 8001e28: 2200 movs r2, #0 + 8001e2a: 4619 mov r1, r3 + 8001e2c: 4820 ldr r0, [pc, #128] ; (8001eb0 ) + 8001e2e: f000 fd37 bl 80028a0 + HAL_GPIO_WritePin(GPIOD, compassLeds->eastLed.Pin, GPIO_PIN_RESET); + 8001e32: 687b ldr r3, [r7, #4] + 8001e34: 6bdb ldr r3, [r3, #60] ; 0x3c + 8001e36: b29b uxth r3, r3 + 8001e38: 2200 movs r2, #0 + 8001e3a: 4619 mov r1, r3 + 8001e3c: 481c ldr r0, [pc, #112] ; (8001eb0 ) + 8001e3e: f000 fd2f bl 80028a0 + HAL_GPIO_WritePin(GPIOD, compassLeds->northLed.Pin, GPIO_PIN_RESET); + 8001e42: 687b ldr r3, [r7, #4] + 8001e44: 681b ldr r3, [r3, #0] + 8001e46: b29b uxth r3, r3 + 8001e48: 2200 movs r2, #0 + 8001e4a: 4619 mov r1, r3 + 8001e4c: 4818 ldr r0, [pc, #96] ; (8001eb0 ) + 8001e4e: f000 fd27 bl 80028a0 + HAL_GPIO_WritePin(GPIOD, compassLeds->westLed.Pin, GPIO_PIN_SET); + 8001e52: 687b ldr r3, [r7, #4] + 8001e54: 6a9b ldr r3, [r3, #40] ; 0x28 + 8001e56: b29b uxth r3, r3 + 8001e58: 2201 movs r2, #1 + 8001e5a: 4619 mov r1, r3 + 8001e5c: 4814 ldr r0, [pc, #80] ; (8001eb0 ) + 8001e5e: f000 fd1f bl 80028a0 + break; + 8001e62: e01f b.n 8001ea4 + default: + HAL_GPIO_WritePin(GPIOD, compassLeds->southLed.Pin, GPIO_PIN_RESET); + 8001e64: 687b ldr r3, [r7, #4] + 8001e66: 695b ldr r3, [r3, #20] + 8001e68: b29b uxth r3, r3 + 8001e6a: 2200 movs r2, #0 + 8001e6c: 4619 mov r1, r3 + 8001e6e: 4810 ldr r0, [pc, #64] ; (8001eb0 ) + 8001e70: f000 fd16 bl 80028a0 + HAL_GPIO_WritePin(GPIOD, compassLeds->eastLed.Pin, GPIO_PIN_RESET); + 8001e74: 687b ldr r3, [r7, #4] + 8001e76: 6bdb ldr r3, [r3, #60] ; 0x3c + 8001e78: b29b uxth r3, r3 + 8001e7a: 2200 movs r2, #0 + 8001e7c: 4619 mov r1, r3 + 8001e7e: 480c ldr r0, [pc, #48] ; (8001eb0 ) + 8001e80: f000 fd0e bl 80028a0 + HAL_GPIO_WritePin(GPIOD, compassLeds->northLed.Pin, GPIO_PIN_RESET); + 8001e84: 687b ldr r3, [r7, #4] + 8001e86: 681b ldr r3, [r3, #0] + 8001e88: b29b uxth r3, r3 + 8001e8a: 2200 movs r2, #0 + 8001e8c: 4619 mov r1, r3 + 8001e8e: 4808 ldr r0, [pc, #32] ; (8001eb0 ) + 8001e90: f000 fd06 bl 80028a0 + HAL_GPIO_WritePin(GPIOD, compassLeds->westLed.Pin, GPIO_PIN_RESET); + 8001e94: 687b ldr r3, [r7, #4] + 8001e96: 6a9b ldr r3, [r3, #40] ; 0x28 + 8001e98: b29b uxth r3, r3 + 8001e9a: 2200 movs r2, #0 + 8001e9c: 4619 mov r1, r3 + 8001e9e: 4804 ldr r0, [pc, #16] ; (8001eb0 ) + 8001ea0: f000 fcfe bl 80028a0 + } + return true; + 8001ea4: 2301 movs r3, #1 +} + 8001ea6: 4618 mov r0, r3 + 8001ea8: 3708 adds r7, #8 + 8001eaa: 46bd mov sp, r7 + 8001eac: bd80 pop {r7, pc} + 8001eae: bf00 nop + 8001eb0: 40020c00 .word 0x40020c00 + +08001eb4 : +static const uint8_t _IRC_REG_M = 0x0C; +static const uint8_t _TEMP_OUT_H_M = 0x31; +static const uint8_t _TEMP_OUT_L_M = 0x32; + +bool LSM303_Init(LSM303 *device, I2C_HandleTypeDef *i2cHandler) +{ + 8001eb4: b480 push {r7} + 8001eb6: b083 sub sp, #12 + 8001eb8: af00 add r7, sp, #0 + 8001eba: 6078 str r0, [r7, #4] + 8001ebc: 6039 str r1, [r7, #0] + if(!device || !i2cHandler)return false; + 8001ebe: 687b ldr r3, [r7, #4] + 8001ec0: 2b00 cmp r3, #0 + 8001ec2: d002 beq.n 8001eca + 8001ec4: 683b ldr r3, [r7, #0] + 8001ec6: 2b00 cmp r3, #0 + 8001ec8: d101 bne.n 8001ece + 8001eca: 2300 movs r3, #0 + 8001ecc: e00b b.n 8001ee6 + + device->i2cHandler = i2cHandler; + 8001ece: 687b ldr r3, [r7, #4] + 8001ed0: 683a ldr r2, [r7, #0] + 8001ed2: 601a str r2, [r3, #0] + device->opMode = CONTINUOUS_CONVERSION; + 8001ed4: 687b ldr r3, [r7, #4] + 8001ed6: 2200 movs r2, #0 + 8001ed8: 711a strb r2, [r3, #4] + device->enableTempSensor = false; + 8001eda: 687a ldr r2, [r7, #4] + 8001edc: 7953 ldrb r3, [r2, #5] + 8001ede: f36f 0300 bfc r3, #0, #1 + 8001ee2: 7153 strb r3, [r2, #5] + + return true; + 8001ee4: 2301 movs r3, #1 +} + 8001ee6: 4618 mov r0, r3 + 8001ee8: 370c adds r7, #12 + 8001eea: 46bd mov sp, r7 + 8001eec: f85d 7b04 ldr.w r7, [sp], #4 + 8001ef0: 4770 bx lr + +08001ef2 : + +bool LSM303_EnableTemperatureSensor(LSM303 *device, bool enable) +{ + 8001ef2: b480 push {r7} + 8001ef4: b083 sub sp, #12 + 8001ef6: af00 add r7, sp, #0 + 8001ef8: 6078 str r0, [r7, #4] + 8001efa: 460b mov r3, r1 + 8001efc: 70fb strb r3, [r7, #3] + if(!device) return false; + 8001efe: 687b ldr r3, [r7, #4] + 8001f00: 2b00 cmp r3, #0 + 8001f02: d101 bne.n 8001f08 + 8001f04: 2300 movs r3, #0 + 8001f06: e009 b.n 8001f1c + + device->enableTempSensor = enable; + 8001f08: 78fb ldrb r3, [r7, #3] + 8001f0a: f003 0301 and.w r3, r3, #1 + 8001f0e: b2d9 uxtb r1, r3 + 8001f10: 687a ldr r2, [r7, #4] + 8001f12: 7953 ldrb r3, [r2, #5] + 8001f14: f361 0300 bfi r3, r1, #0, #1 + 8001f18: 7153 strb r3, [r2, #5] + + return true; + 8001f1a: 2301 movs r3, #1 +} + 8001f1c: 4618 mov r0, r3 + 8001f1e: 370c adds r7, #12 + 8001f20: 46bd mov sp, r7 + 8001f22: f85d 7b04 ldr.w r7, [sp], #4 + 8001f26: 4770 bx lr + +08001f28 : + + return true; +} + +bool LSM303_ApplyConfig(LSM303 *device) +{ + 8001f28: b580 push {r7, lr} + 8001f2a: b084 sub sp, #16 + 8001f2c: af00 add r7, sp, #0 + 8001f2e: 6078 str r0, [r7, #4] + if(!device) return false; + 8001f30: 687b ldr r3, [r7, #4] + 8001f32: 2b00 cmp r3, #0 + 8001f34: d101 bne.n 8001f3a + 8001f36: 2300 movs r3, #0 + 8001f38: e03d b.n 8001fb6 + + //We apply the temperature config + uint8_t data = 0; + 8001f3a: 2300 movs r3, #0 + 8001f3c: 73fb strb r3, [r7, #15] + if(!LSM303_ReadRegister(device, CRA_REG_M, &data)) + 8001f3e: f107 030f add.w r3, r7, #15 + 8001f42: 461a mov r2, r3 + 8001f44: 2100 movs r1, #0 + 8001f46: 6878 ldr r0, [r7, #4] + 8001f48: f000 f930 bl 80021ac + 8001f4c: 4603 mov r3, r0 + 8001f4e: 2b00 cmp r3, #0 + 8001f50: d101 bne.n 8001f56 + return false; + 8001f52: 2300 movs r3, #0 + 8001f54: e02f b.n 8001fb6 + + if(device->enableTempSensor) + 8001f56: 687b ldr r3, [r7, #4] + 8001f58: 795b ldrb r3, [r3, #5] + 8001f5a: f003 0301 and.w r3, r3, #1 + 8001f5e: b2db uxtb r3, r3 + 8001f60: 2b00 cmp r3, #0 + 8001f62: d00d beq.n 8001f80 + { + if(!LSM303_WriteRegister(device, CRA_REG_M, data | (1 << 7))) + 8001f64: 7bfb ldrb r3, [r7, #15] + 8001f66: f063 037f orn r3, r3, #127 ; 0x7f + 8001f6a: b2db uxtb r3, r3 + 8001f6c: 461a mov r2, r3 + 8001f6e: 2100 movs r1, #0 + 8001f70: 6878 ldr r0, [r7, #4] + 8001f72: f000 f94a bl 800220a + 8001f76: 4603 mov r3, r0 + 8001f78: 2b00 cmp r3, #0 + 8001f7a: d10f bne.n 8001f9c + return false; + 8001f7c: 2300 movs r3, #0 + 8001f7e: e01a b.n 8001fb6 + } + else + { + if(!LSM303_WriteRegister(device, CRA_REG_M, data & ~(1 << 7))) + 8001f80: 7bfb ldrb r3, [r7, #15] + 8001f82: f003 037f and.w r3, r3, #127 ; 0x7f + 8001f86: b2db uxtb r3, r3 + 8001f88: 461a mov r2, r3 + 8001f8a: 2100 movs r1, #0 + 8001f8c: 6878 ldr r0, [r7, #4] + 8001f8e: f000 f93c bl 800220a + 8001f92: 4603 mov r3, r0 + 8001f94: 2b00 cmp r3, #0 + 8001f96: d101 bne.n 8001f9c + return false; + 8001f98: 2300 movs r3, #0 + 8001f9a: e00c b.n 8001fb6 + } + + //We apply the operation mode + if(!LSM303_WriteRegister(device, MR_REG_M, device->opMode)) + 8001f9c: 687b ldr r3, [r7, #4] + 8001f9e: 791b ldrb r3, [r3, #4] + 8001fa0: 461a mov r2, r3 + 8001fa2: 2102 movs r1, #2 + 8001fa4: 6878 ldr r0, [r7, #4] + 8001fa6: f000 f930 bl 800220a + 8001faa: 4603 mov r3, r0 + 8001fac: 2b00 cmp r3, #0 + 8001fae: d101 bne.n 8001fb4 + return false; + 8001fb0: 2300 movs r3, #0 + 8001fb2: e000 b.n 8001fb6 + + return true; + 8001fb4: 2301 movs r3, #1 +} + 8001fb6: 4618 mov r0, r3 + 8001fb8: 3710 adds r7, #16 + 8001fba: 46bd mov sp, r7 + 8001fbc: bd80 pop {r7, pc} + ... + +08001fc0 : + +bool LSM303_GetDeviceID(LSM303 *device, uint8_t id[3]) +{ + 8001fc0: b580 push {r7, lr} + 8001fc2: b086 sub sp, #24 + 8001fc4: af02 add r7, sp, #8 + 8001fc6: 6078 str r0, [r7, #4] + 8001fc8: 6039 str r1, [r7, #0] + if(!device) return false; + 8001fca: 687b ldr r3, [r7, #4] + 8001fcc: 2b00 cmp r3, #0 + 8001fce: d101 bne.n 8001fd4 + 8001fd0: 2300 movs r3, #0 + 8001fd2: e022 b.n 800201a + + HAL_StatusTypeDef status = HAL_I2C_Master_Transmit(device->i2cHandler, LMS303DLHC_COMP_ADDR, (uint8_t *)&_IRA_REG_M, 1, HAL_MAX_DELAY); + 8001fd4: 687b ldr r3, [r7, #4] + 8001fd6: 6818 ldr r0, [r3, #0] + 8001fd8: 233c movs r3, #60 ; 0x3c + 8001fda: b299 uxth r1, r3 + 8001fdc: f04f 33ff mov.w r3, #4294967295 + 8001fe0: 9300 str r3, [sp, #0] + 8001fe2: 2301 movs r3, #1 + 8001fe4: 4a0f ldr r2, [pc, #60] ; (8002024 ) + 8001fe6: f002 fa9d bl 8004524 + 8001fea: 4603 mov r3, r0 + 8001fec: 73fb strb r3, [r7, #15] + if(status != HAL_OK) + 8001fee: 7bfb ldrb r3, [r7, #15] + 8001ff0: 2b00 cmp r3, #0 + 8001ff2: d001 beq.n 8001ff8 + return false; + 8001ff4: 2300 movs r3, #0 + 8001ff6: e010 b.n 800201a + + return HAL_I2C_Master_Receive(device->i2cHandler, LMS303DLHC_COMP_ADDR, id, 3, HAL_MAX_DELAY) == HAL_OK ? true : false; + 8001ff8: 687b ldr r3, [r7, #4] + 8001ffa: 6818 ldr r0, [r3, #0] + 8001ffc: 233c movs r3, #60 ; 0x3c + 8001ffe: b299 uxth r1, r3 + 8002000: f04f 33ff mov.w r3, #4294967295 + 8002004: 9300 str r3, [sp, #0] + 8002006: 2303 movs r3, #3 + 8002008: 683a ldr r2, [r7, #0] + 800200a: f002 fb89 bl 8004720 + 800200e: 4603 mov r3, r0 + 8002010: 2b00 cmp r3, #0 + 8002012: bf0c ite eq + 8002014: 2301 moveq r3, #1 + 8002016: 2300 movne r3, #0 + 8002018: b2db uxtb r3, r3 +} + 800201a: 4618 mov r0, r3 + 800201c: 3710 adds r7, #16 + 800201e: 46bd mov sp, r7 + 8002020: bd80 pop {r7, pc} + 8002022: bf00 nop + 8002024: 0800e931 .word 0x0800e931 + +08002028 : + +bool LSM303_GetTemperature(LSM303 *device, float *temperature, int16_t *rawValue) +{ + 8002028: b580 push {r7, lr} + 800202a: b088 sub sp, #32 + 800202c: af02 add r7, sp, #8 + 800202e: 60f8 str r0, [r7, #12] + 8002030: 60b9 str r1, [r7, #8] + 8002032: 607a str r2, [r7, #4] + if(!device) return false; + 8002034: 68fb ldr r3, [r7, #12] + 8002036: 2b00 cmp r3, #0 + 8002038: d101 bne.n 800203e + 800203a: 2300 movs r3, #0 + 800203c: e045 b.n 80020ca + uint8_t data[2]; + int16_t orderedData; + + HAL_StatusTypeDef status = HAL_I2C_Master_Transmit(device->i2cHandler, LMS303DLHC_COMP_ADDR, (uint8_t *)&_TEMP_OUT_H_M, 1, HAL_MAX_DELAY); + 800203e: 68fb ldr r3, [r7, #12] + 8002040: 6818 ldr r0, [r3, #0] + 8002042: 233c movs r3, #60 ; 0x3c + 8002044: b299 uxth r1, r3 + 8002046: f04f 33ff mov.w r3, #4294967295 + 800204a: 9300 str r3, [sp, #0] + 800204c: 2301 movs r3, #1 + 800204e: 4a21 ldr r2, [pc, #132] ; (80020d4 ) + 8002050: f002 fa68 bl 8004524 + 8002054: 4603 mov r3, r0 + 8002056: 75fb strb r3, [r7, #23] + if(status != HAL_OK) + 8002058: 7dfb ldrb r3, [r7, #23] + 800205a: 2b00 cmp r3, #0 + 800205c: d001 beq.n 8002062 + return false; + 800205e: 2300 movs r3, #0 + 8002060: e033 b.n 80020ca + + status = HAL_I2C_Master_Receive(device->i2cHandler, LMS303DLHC_COMP_ADDR, data, 2, HAL_MAX_DELAY); + 8002062: 68fb ldr r3, [r7, #12] + 8002064: 6818 ldr r0, [r3, #0] + 8002066: 233c movs r3, #60 ; 0x3c + 8002068: b299 uxth r1, r3 + 800206a: f107 0214 add.w r2, r7, #20 + 800206e: f04f 33ff mov.w r3, #4294967295 + 8002072: 9300 str r3, [sp, #0] + 8002074: 2302 movs r3, #2 + 8002076: f002 fb53 bl 8004720 + 800207a: 4603 mov r3, r0 + 800207c: 75fb strb r3, [r7, #23] + if(status != HAL_OK) + 800207e: 7dfb ldrb r3, [r7, #23] + 8002080: 2b00 cmp r3, #0 + 8002082: d001 beq.n 8002088 + return false; + 8002084: 2300 movs r3, #0 + 8002086: e020 b.n 80020ca + + //We switch the bytes... + ((uint8_t *)&orderedData)[0] = data[1]; + 8002088: f107 0312 add.w r3, r7, #18 + 800208c: 7d7a ldrb r2, [r7, #21] + 800208e: 701a strb r2, [r3, #0] + ((uint8_t *)&orderedData)[1] = data[0]; + 8002090: f107 0312 add.w r3, r7, #18 + 8002094: 3301 adds r3, #1 + 8002096: 7d3a ldrb r2, [r7, #20] + 8002098: 701a strb r2, [r3, #0] + + if(rawValue) + 800209a: 687b ldr r3, [r7, #4] + 800209c: 2b00 cmp r3, #0 + 800209e: d003 beq.n 80020a8 + *rawValue = orderedData; + 80020a0: f9b7 2012 ldrsh.w r2, [r7, #18] + 80020a4: 687b ldr r3, [r7, #4] + 80020a6: 801a strh r2, [r3, #0] + + if(temperature) + 80020a8: 68bb ldr r3, [r7, #8] + 80020aa: 2b00 cmp r3, #0 + 80020ac: d00c beq.n 80020c8 + *temperature = (float)orderedData / 256; + 80020ae: f9b7 3012 ldrsh.w r3, [r7, #18] + 80020b2: ee07 3a90 vmov s15, r3 + 80020b6: eeb8 7ae7 vcvt.f32.s32 s14, s15 + 80020ba: eddf 6a07 vldr s13, [pc, #28] ; 80020d8 + 80020be: eec7 7a26 vdiv.f32 s15, s14, s13 + 80020c2: 68bb ldr r3, [r7, #8] + 80020c4: edc3 7a00 vstr s15, [r3] + + return true; + 80020c8: 2301 movs r3, #1 +} + 80020ca: 4618 mov r0, r3 + 80020cc: 3718 adds r7, #24 + 80020ce: 46bd mov sp, r7 + 80020d0: bd80 pop {r7, pc} + 80020d2: bf00 nop + 80020d4: 0800e932 .word 0x0800e932 + 80020d8: 43800000 .word 0x43800000 + +080020dc : + +bool LSM303_GetMagneticFieldData(LSM303 *device, int16_t *xAxis, int16_t *yAxis, int16_t *zAxis) +{ + 80020dc: b580 push {r7, lr} + 80020de: b08a sub sp, #40 ; 0x28 + 80020e0: af02 add r7, sp, #8 + 80020e2: 60f8 str r0, [r7, #12] + 80020e4: 60b9 str r1, [r7, #8] + 80020e6: 607a str r2, [r7, #4] + 80020e8: 603b str r3, [r7, #0] + if(!device) return false; + 80020ea: 68fb ldr r3, [r7, #12] + 80020ec: 2b00 cmp r3, #0 + 80020ee: d101 bne.n 80020f4 + 80020f0: 2300 movs r3, #0 + 80020f2: e055 b.n 80021a0 + + uint8_t data[6]; + int16_t x,y,z; + + HAL_StatusTypeDef status = HAL_I2C_Master_Transmit(device->i2cHandler, LMS303DLHC_COMP_ADDR, (uint8_t *)&_OUT_X_H_M, 1, HAL_MAX_DELAY); + 80020f4: 68fb ldr r3, [r7, #12] + 80020f6: 6818 ldr r0, [r3, #0] + 80020f8: 233c movs r3, #60 ; 0x3c + 80020fa: b299 uxth r1, r3 + 80020fc: f04f 33ff mov.w r3, #4294967295 + 8002100: 9300 str r3, [sp, #0] + 8002102: 2301 movs r3, #1 + 8002104: 4a28 ldr r2, [pc, #160] ; (80021a8 ) + 8002106: f002 fa0d bl 8004524 + 800210a: 4603 mov r3, r0 + 800210c: 77fb strb r3, [r7, #31] + if(status != HAL_OK) + 800210e: 7ffb ldrb r3, [r7, #31] + 8002110: 2b00 cmp r3, #0 + 8002112: d001 beq.n 8002118 + return false; + 8002114: 2300 movs r3, #0 + 8002116: e043 b.n 80021a0 + + //We now read all six registers + status = HAL_I2C_Master_Receive(device->i2cHandler, LMS303DLHC_COMP_ADDR, data, 8, HAL_MAX_DELAY); + 8002118: 68fb ldr r3, [r7, #12] + 800211a: 6818 ldr r0, [r3, #0] + 800211c: 233c movs r3, #60 ; 0x3c + 800211e: b299 uxth r1, r3 + 8002120: f107 0218 add.w r2, r7, #24 + 8002124: f04f 33ff mov.w r3, #4294967295 + 8002128: 9300 str r3, [sp, #0] + 800212a: 2308 movs r3, #8 + 800212c: f002 faf8 bl 8004720 + 8002130: 4603 mov r3, r0 + 8002132: 77fb strb r3, [r7, #31] + if(status != HAL_OK) + 8002134: 7ffb ldrb r3, [r7, #31] + 8002136: 2b00 cmp r3, #0 + 8002138: d001 beq.n 800213e + return false; + 800213a: 2300 movs r3, #0 + 800213c: e030 b.n 80021a0 + + //We switch the bytes... + ((uint8_t *)&x)[0] = data[1]; + 800213e: f107 0316 add.w r3, r7, #22 + 8002142: 7e7a ldrb r2, [r7, #25] + 8002144: 701a strb r2, [r3, #0] + ((uint8_t *)&x)[1] = data[0]; + 8002146: f107 0316 add.w r3, r7, #22 + 800214a: 3301 adds r3, #1 + 800214c: 7e3a ldrb r2, [r7, #24] + 800214e: 701a strb r2, [r3, #0] + ((uint8_t *)&z)[0] = data[3]; + 8002150: f107 0312 add.w r3, r7, #18 + 8002154: 7efa ldrb r2, [r7, #27] + 8002156: 701a strb r2, [r3, #0] + ((uint8_t *)&z)[1] = data[2]; + 8002158: f107 0312 add.w r3, r7, #18 + 800215c: 3301 adds r3, #1 + 800215e: 7eba ldrb r2, [r7, #26] + 8002160: 701a strb r2, [r3, #0] + ((uint8_t *)&y)[0] = data[5]; + 8002162: f107 0314 add.w r3, r7, #20 + 8002166: 7f7a ldrb r2, [r7, #29] + 8002168: 701a strb r2, [r3, #0] + ((uint8_t *)&y)[1] = data[4]; + 800216a: f107 0314 add.w r3, r7, #20 + 800216e: 3301 adds r3, #1 + 8002170: 7f3a ldrb r2, [r7, #28] + 8002172: 701a strb r2, [r3, #0] + + if(xAxis) + 8002174: 68bb ldr r3, [r7, #8] + 8002176: 2b00 cmp r3, #0 + 8002178: d003 beq.n 8002182 + *xAxis = x; + 800217a: f9b7 2016 ldrsh.w r2, [r7, #22] + 800217e: 68bb ldr r3, [r7, #8] + 8002180: 801a strh r2, [r3, #0] + if(yAxis) + 8002182: 687b ldr r3, [r7, #4] + 8002184: 2b00 cmp r3, #0 + 8002186: d003 beq.n 8002190 + *yAxis = y; + 8002188: f9b7 2014 ldrsh.w r2, [r7, #20] + 800218c: 687b ldr r3, [r7, #4] + 800218e: 801a strh r2, [r3, #0] + if(zAxis) + 8002190: 683b ldr r3, [r7, #0] + 8002192: 2b00 cmp r3, #0 + 8002194: d003 beq.n 800219e + *zAxis = z; + 8002196: f9b7 2012 ldrsh.w r2, [r7, #18] + 800219a: 683b ldr r3, [r7, #0] + 800219c: 801a strh r2, [r3, #0] + + return true; + 800219e: 2301 movs r3, #1 +} + 80021a0: 4618 mov r0, r3 + 80021a2: 3720 adds r7, #32 + 80021a4: 46bd mov sp, r7 + 80021a6: bd80 pop {r7, pc} + 80021a8: 0800e930 .word 0x0800e930 + +080021ac : + +bool LSM303_ReadRegister(LSM303 *device, uint8_t registerAddr, uint8_t *data) +{ + 80021ac: b580 push {r7, lr} + 80021ae: b088 sub sp, #32 + 80021b0: af02 add r7, sp, #8 + 80021b2: 60f8 str r0, [r7, #12] + 80021b4: 460b mov r3, r1 + 80021b6: 607a str r2, [r7, #4] + 80021b8: 72fb strb r3, [r7, #11] + HAL_StatusTypeDef status = HAL_I2C_Master_Transmit(device->i2cHandler, LMS303DLHC_COMP_ADDR, ®isterAddr, 1, HAL_MAX_DELAY); + 80021ba: 68fb ldr r3, [r7, #12] + 80021bc: 6818 ldr r0, [r3, #0] + 80021be: 233c movs r3, #60 ; 0x3c + 80021c0: b299 uxth r1, r3 + 80021c2: f107 020b add.w r2, r7, #11 + 80021c6: f04f 33ff mov.w r3, #4294967295 + 80021ca: 9300 str r3, [sp, #0] + 80021cc: 2301 movs r3, #1 + 80021ce: f002 f9a9 bl 8004524 + 80021d2: 4603 mov r3, r0 + 80021d4: 75fb strb r3, [r7, #23] + if(status != HAL_OK) + 80021d6: 7dfb ldrb r3, [r7, #23] + 80021d8: 2b00 cmp r3, #0 + 80021da: d001 beq.n 80021e0 + return false; + 80021dc: 2300 movs r3, #0 + 80021de: e010 b.n 8002202 + return HAL_I2C_Master_Receive(device->i2cHandler, LMS303DLHC_COMP_ADDR, data, 1, HAL_MAX_DELAY) == HAL_OK ? true : false; + 80021e0: 68fb ldr r3, [r7, #12] + 80021e2: 6818 ldr r0, [r3, #0] + 80021e4: 233c movs r3, #60 ; 0x3c + 80021e6: b299 uxth r1, r3 + 80021e8: f04f 33ff mov.w r3, #4294967295 + 80021ec: 9300 str r3, [sp, #0] + 80021ee: 2301 movs r3, #1 + 80021f0: 687a ldr r2, [r7, #4] + 80021f2: f002 fa95 bl 8004720 + 80021f6: 4603 mov r3, r0 + 80021f8: 2b00 cmp r3, #0 + 80021fa: bf0c ite eq + 80021fc: 2301 moveq r3, #1 + 80021fe: 2300 movne r3, #0 + 8002200: b2db uxtb r3, r3 +} + 8002202: 4618 mov r0, r3 + 8002204: 3718 adds r7, #24 + 8002206: 46bd mov sp, r7 + 8002208: bd80 pop {r7, pc} + +0800220a : + +bool LSM303_WriteRegister(LSM303 *device, uint8_t registerAddr, uint8_t data) +{ + 800220a: b580 push {r7, lr} + 800220c: b086 sub sp, #24 + 800220e: af02 add r7, sp, #8 + 8002210: 6078 str r0, [r7, #4] + 8002212: 460b mov r3, r1 + 8002214: 70fb strb r3, [r7, #3] + 8002216: 4613 mov r3, r2 + 8002218: 70bb strb r3, [r7, #2] + uint8_t regAndData[] = {registerAddr, data}; + 800221a: 78fb ldrb r3, [r7, #3] + 800221c: 733b strb r3, [r7, #12] + 800221e: 78bb ldrb r3, [r7, #2] + 8002220: 737b strb r3, [r7, #13] + return HAL_I2C_Master_Transmit(device->i2cHandler, LMS303DLHC_COMP_ADDR, regAndData, 2, HAL_MAX_DELAY) == HAL_OK ? true : false; + 8002222: 687b ldr r3, [r7, #4] + 8002224: 6818 ldr r0, [r3, #0] + 8002226: 233c movs r3, #60 ; 0x3c + 8002228: b299 uxth r1, r3 + 800222a: f107 020c add.w r2, r7, #12 + 800222e: f04f 33ff mov.w r3, #4294967295 + 8002232: 9300 str r3, [sp, #0] + 8002234: 2302 movs r3, #2 + 8002236: f002 f975 bl 8004524 + 800223a: 4603 mov r3, r0 + 800223c: 2b00 cmp r3, #0 + 800223e: bf0c ite eq + 8002240: 2301 moveq r3, #1 + 8002242: 2300 movne r3, #0 + 8002244: b2db uxtb r3, r3 +} + 8002246: 4618 mov r0, r3 + 8002248: 3710 adds r7, #16 + 800224a: 46bd mov sp, r7 + 800224c: bd80 pop {r7, pc} + ... + +08002250 : + * need to ensure that the SysTick time base is always set to 1 millisecond + * to have correct HAL operation. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + 8002250: b580 push {r7, lr} + 8002252: af00 add r7, sp, #0 + /* Configure Flash prefetch, Instruction cache, Data cache */ +#if (INSTRUCTION_CACHE_ENABLE != 0U) + __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); + 8002254: 4b0e ldr r3, [pc, #56] ; (8002290 ) + 8002256: 681b ldr r3, [r3, #0] + 8002258: 4a0d ldr r2, [pc, #52] ; (8002290 ) + 800225a: f443 7300 orr.w r3, r3, #512 ; 0x200 + 800225e: 6013 str r3, [r2, #0] +#endif /* INSTRUCTION_CACHE_ENABLE */ + +#if (DATA_CACHE_ENABLE != 0U) + __HAL_FLASH_DATA_CACHE_ENABLE(); + 8002260: 4b0b ldr r3, [pc, #44] ; (8002290 ) + 8002262: 681b ldr r3, [r3, #0] + 8002264: 4a0a ldr r2, [pc, #40] ; (8002290 ) + 8002266: f443 6380 orr.w r3, r3, #1024 ; 0x400 + 800226a: 6013 str r3, [r2, #0] +#endif /* DATA_CACHE_ENABLE */ + +#if (PREFETCH_ENABLE != 0U) + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); + 800226c: 4b08 ldr r3, [pc, #32] ; (8002290 ) + 800226e: 681b ldr r3, [r3, #0] + 8002270: 4a07 ldr r2, [pc, #28] ; (8002290 ) + 8002272: f443 7380 orr.w r3, r3, #256 ; 0x100 + 8002276: 6013 str r3, [r2, #0] +#endif /* PREFETCH_ENABLE */ + + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + 8002278: 2003 movs r0, #3 + 800227a: f000 f94d bl 8002518 + + /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ + HAL_InitTick(TICK_INT_PRIORITY); + 800227e: 2000 movs r0, #0 + 8002280: f000 f808 bl 8002294 + + /* Init the low level hardware */ + HAL_MspInit(); + 8002284: f7ff fa0c bl 80016a0 + + /* Return function status */ + return HAL_OK; + 8002288: 2300 movs r3, #0 +} + 800228a: 4618 mov r0, r3 + 800228c: bd80 pop {r7, pc} + 800228e: bf00 nop + 8002290: 40023c00 .word 0x40023c00 + +08002294 : + * implementation in user file. + * @param TickPriority Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + 8002294: b580 push {r7, lr} + 8002296: b082 sub sp, #8 + 8002298: af00 add r7, sp, #0 + 800229a: 6078 str r0, [r7, #4] + /* Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) + 800229c: 4b12 ldr r3, [pc, #72] ; (80022e8 ) + 800229e: 681a ldr r2, [r3, #0] + 80022a0: 4b12 ldr r3, [pc, #72] ; (80022ec ) + 80022a2: 781b ldrb r3, [r3, #0] + 80022a4: 4619 mov r1, r3 + 80022a6: f44f 737a mov.w r3, #1000 ; 0x3e8 + 80022aa: fbb3 f3f1 udiv r3, r3, r1 + 80022ae: fbb2 f3f3 udiv r3, r2, r3 + 80022b2: 4618 mov r0, r3 + 80022b4: f000 f965 bl 8002582 + 80022b8: 4603 mov r3, r0 + 80022ba: 2b00 cmp r3, #0 + 80022bc: d001 beq.n 80022c2 + { + return HAL_ERROR; + 80022be: 2301 movs r3, #1 + 80022c0: e00e b.n 80022e0 + } + + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + 80022c2: 687b ldr r3, [r7, #4] + 80022c4: 2b0f cmp r3, #15 + 80022c6: d80a bhi.n 80022de + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + 80022c8: 2200 movs r2, #0 + 80022ca: 6879 ldr r1, [r7, #4] + 80022cc: f04f 30ff mov.w r0, #4294967295 + 80022d0: f000 f92d bl 800252e + uwTickPrio = TickPriority; + 80022d4: 4a06 ldr r2, [pc, #24] ; (80022f0 ) + 80022d6: 687b ldr r3, [r7, #4] + 80022d8: 6013 str r3, [r2, #0] + { + return HAL_ERROR; + } + + /* Return function status */ + return HAL_OK; + 80022da: 2300 movs r3, #0 + 80022dc: e000 b.n 80022e0 + return HAL_ERROR; + 80022de: 2301 movs r3, #1 +} + 80022e0: 4618 mov r0, r3 + 80022e2: 3708 adds r7, #8 + 80022e4: 46bd mov sp, r7 + 80022e6: bd80 pop {r7, pc} + 80022e8: 20000000 .word 0x20000000 + 80022ec: 20000008 .word 0x20000008 + 80022f0: 20000004 .word 0x20000004 + +080022f4 : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + 80022f4: b480 push {r7} + 80022f6: af00 add r7, sp, #0 + uwTick += uwTickFreq; + 80022f8: 4b06 ldr r3, [pc, #24] ; (8002314 ) + 80022fa: 781b ldrb r3, [r3, #0] + 80022fc: 461a mov r2, r3 + 80022fe: 4b06 ldr r3, [pc, #24] ; (8002318 ) + 8002300: 681b ldr r3, [r3, #0] + 8002302: 4413 add r3, r2 + 8002304: 4a04 ldr r2, [pc, #16] ; (8002318 ) + 8002306: 6013 str r3, [r2, #0] +} + 8002308: bf00 nop + 800230a: 46bd mov sp, r7 + 800230c: f85d 7b04 ldr.w r7, [sp], #4 + 8002310: 4770 bx lr + 8002312: bf00 nop + 8002314: 20000008 .word 0x20000008 + 8002318: 20000410 .word 0x20000410 + +0800231c : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + 800231c: b480 push {r7} + 800231e: af00 add r7, sp, #0 + return uwTick; + 8002320: 4b03 ldr r3, [pc, #12] ; (8002330 ) + 8002322: 681b ldr r3, [r3, #0] +} + 8002324: 4618 mov r0, r3 + 8002326: 46bd mov sp, r7 + 8002328: f85d 7b04 ldr.w r7, [sp], #4 + 800232c: 4770 bx lr + 800232e: bf00 nop + 8002330: 20000410 .word 0x20000410 + +08002334 : + * implementations in user file. + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void HAL_Delay(uint32_t Delay) +{ + 8002334: b580 push {r7, lr} + 8002336: b084 sub sp, #16 + 8002338: af00 add r7, sp, #0 + 800233a: 6078 str r0, [r7, #4] + uint32_t tickstart = HAL_GetTick(); + 800233c: f7ff ffee bl 800231c + 8002340: 60b8 str r0, [r7, #8] + uint32_t wait = Delay; + 8002342: 687b ldr r3, [r7, #4] + 8002344: 60fb str r3, [r7, #12] + + /* Add a freq to guarantee minimum wait */ + if (wait < HAL_MAX_DELAY) + 8002346: 68fb ldr r3, [r7, #12] + 8002348: f1b3 3fff cmp.w r3, #4294967295 + 800234c: d005 beq.n 800235a + { + wait += (uint32_t)(uwTickFreq); + 800234e: 4b09 ldr r3, [pc, #36] ; (8002374 ) + 8002350: 781b ldrb r3, [r3, #0] + 8002352: 461a mov r2, r3 + 8002354: 68fb ldr r3, [r7, #12] + 8002356: 4413 add r3, r2 + 8002358: 60fb str r3, [r7, #12] + } + + while((HAL_GetTick() - tickstart) < wait) + 800235a: bf00 nop + 800235c: f7ff ffde bl 800231c + 8002360: 4602 mov r2, r0 + 8002362: 68bb ldr r3, [r7, #8] + 8002364: 1ad3 subs r3, r2, r3 + 8002366: 68fa ldr r2, [r7, #12] + 8002368: 429a cmp r2, r3 + 800236a: d8f7 bhi.n 800235c + { + } +} + 800236c: bf00 nop + 800236e: 3710 adds r7, #16 + 8002370: 46bd mov sp, r7 + 8002372: bd80 pop {r7, pc} + 8002374: 20000008 .word 0x20000008 + +08002378 <__NVIC_SetPriorityGrouping>: + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + 8002378: b480 push {r7} + 800237a: b085 sub sp, #20 + 800237c: af00 add r7, sp, #0 + 800237e: 6078 str r0, [r7, #4] + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 8002380: 687b ldr r3, [r7, #4] + 8002382: f003 0307 and.w r3, r3, #7 + 8002386: 60fb str r3, [r7, #12] + + reg_value = SCB->AIRCR; /* read old register configuration */ + 8002388: 4b0c ldr r3, [pc, #48] ; (80023bc <__NVIC_SetPriorityGrouping+0x44>) + 800238a: 68db ldr r3, [r3, #12] + 800238c: 60bb str r3, [r7, #8] + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + 800238e: 68ba ldr r2, [r7, #8] + 8002390: f64f 03ff movw r3, #63743 ; 0xf8ff + 8002394: 4013 ands r3, r2 + 8002396: 60bb str r3, [r7, #8] + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + 8002398: 68fb ldr r3, [r7, #12] + 800239a: 021a lsls r2, r3, #8 + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + 800239c: 68bb ldr r3, [r7, #8] + 800239e: 4313 orrs r3, r2 + reg_value = (reg_value | + 80023a0: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 + 80023a4: f443 3300 orr.w r3, r3, #131072 ; 0x20000 + 80023a8: 60bb str r3, [r7, #8] + SCB->AIRCR = reg_value; + 80023aa: 4a04 ldr r2, [pc, #16] ; (80023bc <__NVIC_SetPriorityGrouping+0x44>) + 80023ac: 68bb ldr r3, [r7, #8] + 80023ae: 60d3 str r3, [r2, #12] +} + 80023b0: bf00 nop + 80023b2: 3714 adds r7, #20 + 80023b4: 46bd mov sp, r7 + 80023b6: f85d 7b04 ldr.w r7, [sp], #4 + 80023ba: 4770 bx lr + 80023bc: e000ed00 .word 0xe000ed00 + +080023c0 <__NVIC_GetPriorityGrouping>: + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + 80023c0: b480 push {r7} + 80023c2: af00 add r7, sp, #0 + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); + 80023c4: 4b04 ldr r3, [pc, #16] ; (80023d8 <__NVIC_GetPriorityGrouping+0x18>) + 80023c6: 68db ldr r3, [r3, #12] + 80023c8: 0a1b lsrs r3, r3, #8 + 80023ca: f003 0307 and.w r3, r3, #7 +} + 80023ce: 4618 mov r0, r3 + 80023d0: 46bd mov sp, r7 + 80023d2: f85d 7b04 ldr.w r7, [sp], #4 + 80023d6: 4770 bx lr + 80023d8: e000ed00 .word 0xe000ed00 + +080023dc <__NVIC_EnableIRQ>: + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + 80023dc: b480 push {r7} + 80023de: b083 sub sp, #12 + 80023e0: af00 add r7, sp, #0 + 80023e2: 4603 mov r3, r0 + 80023e4: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 80023e6: f997 3007 ldrsb.w r3, [r7, #7] + 80023ea: 2b00 cmp r3, #0 + 80023ec: db0b blt.n 8002406 <__NVIC_EnableIRQ+0x2a> + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 80023ee: 79fb ldrb r3, [r7, #7] + 80023f0: f003 021f and.w r2, r3, #31 + 80023f4: 4907 ldr r1, [pc, #28] ; (8002414 <__NVIC_EnableIRQ+0x38>) + 80023f6: f997 3007 ldrsb.w r3, [r7, #7] + 80023fa: 095b lsrs r3, r3, #5 + 80023fc: 2001 movs r0, #1 + 80023fe: fa00 f202 lsl.w r2, r0, r2 + 8002402: f841 2023 str.w r2, [r1, r3, lsl #2] + } +} + 8002406: bf00 nop + 8002408: 370c adds r7, #12 + 800240a: 46bd mov sp, r7 + 800240c: f85d 7b04 ldr.w r7, [sp], #4 + 8002410: 4770 bx lr + 8002412: bf00 nop + 8002414: e000e100 .word 0xe000e100 + +08002418 <__NVIC_SetPriority>: + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + 8002418: b480 push {r7} + 800241a: b083 sub sp, #12 + 800241c: af00 add r7, sp, #0 + 800241e: 4603 mov r3, r0 + 8002420: 6039 str r1, [r7, #0] + 8002422: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 8002424: f997 3007 ldrsb.w r3, [r7, #7] + 8002428: 2b00 cmp r3, #0 + 800242a: db0a blt.n 8002442 <__NVIC_SetPriority+0x2a> + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 800242c: 683b ldr r3, [r7, #0] + 800242e: b2da uxtb r2, r3 + 8002430: 490c ldr r1, [pc, #48] ; (8002464 <__NVIC_SetPriority+0x4c>) + 8002432: f997 3007 ldrsb.w r3, [r7, #7] + 8002436: 0112 lsls r2, r2, #4 + 8002438: b2d2 uxtb r2, r2 + 800243a: 440b add r3, r1 + 800243c: f883 2300 strb.w r2, [r3, #768] ; 0x300 + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + 8002440: e00a b.n 8002458 <__NVIC_SetPriority+0x40> + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 8002442: 683b ldr r3, [r7, #0] + 8002444: b2da uxtb r2, r3 + 8002446: 4908 ldr r1, [pc, #32] ; (8002468 <__NVIC_SetPriority+0x50>) + 8002448: 79fb ldrb r3, [r7, #7] + 800244a: f003 030f and.w r3, r3, #15 + 800244e: 3b04 subs r3, #4 + 8002450: 0112 lsls r2, r2, #4 + 8002452: b2d2 uxtb r2, r2 + 8002454: 440b add r3, r1 + 8002456: 761a strb r2, [r3, #24] +} + 8002458: bf00 nop + 800245a: 370c adds r7, #12 + 800245c: 46bd mov sp, r7 + 800245e: f85d 7b04 ldr.w r7, [sp], #4 + 8002462: 4770 bx lr + 8002464: e000e100 .word 0xe000e100 + 8002468: e000ed00 .word 0xe000ed00 + +0800246c : + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 800246c: b480 push {r7} + 800246e: b089 sub sp, #36 ; 0x24 + 8002470: af00 add r7, sp, #0 + 8002472: 60f8 str r0, [r7, #12] + 8002474: 60b9 str r1, [r7, #8] + 8002476: 607a str r2, [r7, #4] + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 8002478: 68fb ldr r3, [r7, #12] + 800247a: f003 0307 and.w r3, r3, #7 + 800247e: 61fb str r3, [r7, #28] + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + 8002480: 69fb ldr r3, [r7, #28] + 8002482: f1c3 0307 rsb r3, r3, #7 + 8002486: 2b04 cmp r3, #4 + 8002488: bf28 it cs + 800248a: 2304 movcs r3, #4 + 800248c: 61bb str r3, [r7, #24] + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + 800248e: 69fb ldr r3, [r7, #28] + 8002490: 3304 adds r3, #4 + 8002492: 2b06 cmp r3, #6 + 8002494: d902 bls.n 800249c + 8002496: 69fb ldr r3, [r7, #28] + 8002498: 3b03 subs r3, #3 + 800249a: e000 b.n 800249e + 800249c: 2300 movs r3, #0 + 800249e: 617b str r3, [r7, #20] + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 80024a0: f04f 32ff mov.w r2, #4294967295 + 80024a4: 69bb ldr r3, [r7, #24] + 80024a6: fa02 f303 lsl.w r3, r2, r3 + 80024aa: 43da mvns r2, r3 + 80024ac: 68bb ldr r3, [r7, #8] + 80024ae: 401a ands r2, r3 + 80024b0: 697b ldr r3, [r7, #20] + 80024b2: 409a lsls r2, r3 + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + 80024b4: f04f 31ff mov.w r1, #4294967295 + 80024b8: 697b ldr r3, [r7, #20] + 80024ba: fa01 f303 lsl.w r3, r1, r3 + 80024be: 43d9 mvns r1, r3 + 80024c0: 687b ldr r3, [r7, #4] + 80024c2: 400b ands r3, r1 + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 80024c4: 4313 orrs r3, r2 + ); +} + 80024c6: 4618 mov r0, r3 + 80024c8: 3724 adds r7, #36 ; 0x24 + 80024ca: 46bd mov sp, r7 + 80024cc: f85d 7b04 ldr.w r7, [sp], #4 + 80024d0: 4770 bx lr + ... + +080024d4 : + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + 80024d4: b580 push {r7, lr} + 80024d6: b082 sub sp, #8 + 80024d8: af00 add r7, sp, #0 + 80024da: 6078 str r0, [r7, #4] + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + 80024dc: 687b ldr r3, [r7, #4] + 80024de: 3b01 subs r3, #1 + 80024e0: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 + 80024e4: d301 bcc.n 80024ea + { + return (1UL); /* Reload value impossible */ + 80024e6: 2301 movs r3, #1 + 80024e8: e00f b.n 800250a + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + 80024ea: 4a0a ldr r2, [pc, #40] ; (8002514 ) + 80024ec: 687b ldr r3, [r7, #4] + 80024ee: 3b01 subs r3, #1 + 80024f0: 6053 str r3, [r2, #4] + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + 80024f2: 210f movs r1, #15 + 80024f4: f04f 30ff mov.w r0, #4294967295 + 80024f8: f7ff ff8e bl 8002418 <__NVIC_SetPriority> + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + 80024fc: 4b05 ldr r3, [pc, #20] ; (8002514 ) + 80024fe: 2200 movs r2, #0 + 8002500: 609a str r2, [r3, #8] + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + 8002502: 4b04 ldr r3, [pc, #16] ; (8002514 ) + 8002504: 2207 movs r2, #7 + 8002506: 601a str r2, [r3, #0] + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ + 8002508: 2300 movs r3, #0 +} + 800250a: 4618 mov r0, r3 + 800250c: 3708 adds r7, #8 + 800250e: 46bd mov sp, r7 + 8002510: bd80 pop {r7, pc} + 8002512: bf00 nop + 8002514: e000e010 .word 0xe000e010 + +08002518 : + * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + 8002518: b580 push {r7, lr} + 800251a: b082 sub sp, #8 + 800251c: af00 add r7, sp, #0 + 800251e: 6078 str r0, [r7, #4] + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + NVIC_SetPriorityGrouping(PriorityGroup); + 8002520: 6878 ldr r0, [r7, #4] + 8002522: f7ff ff29 bl 8002378 <__NVIC_SetPriorityGrouping> +} + 8002526: bf00 nop + 8002528: 3708 adds r7, #8 + 800252a: 46bd mov sp, r7 + 800252c: bd80 pop {r7, pc} + +0800252e : + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 800252e: b580 push {r7, lr} + 8002530: b086 sub sp, #24 + 8002532: af00 add r7, sp, #0 + 8002534: 4603 mov r3, r0 + 8002536: 60b9 str r1, [r7, #8] + 8002538: 607a str r2, [r7, #4] + 800253a: 73fb strb r3, [r7, #15] + uint32_t prioritygroup = 0x00U; + 800253c: 2300 movs r3, #0 + 800253e: 617b str r3, [r7, #20] + + /* Check the parameters */ + assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + + prioritygroup = NVIC_GetPriorityGrouping(); + 8002540: f7ff ff3e bl 80023c0 <__NVIC_GetPriorityGrouping> + 8002544: 6178 str r0, [r7, #20] + + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); + 8002546: 687a ldr r2, [r7, #4] + 8002548: 68b9 ldr r1, [r7, #8] + 800254a: 6978 ldr r0, [r7, #20] + 800254c: f7ff ff8e bl 800246c + 8002550: 4602 mov r2, r0 + 8002552: f997 300f ldrsb.w r3, [r7, #15] + 8002556: 4611 mov r1, r2 + 8002558: 4618 mov r0, r3 + 800255a: f7ff ff5d bl 8002418 <__NVIC_SetPriority> +} + 800255e: bf00 nop + 8002560: 3718 adds r7, #24 + 8002562: 46bd mov sp, r7 + 8002564: bd80 pop {r7, pc} + +08002566 : + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + 8002566: b580 push {r7, lr} + 8002568: b082 sub sp, #8 + 800256a: af00 add r7, sp, #0 + 800256c: 4603 mov r3, r0 + 800256e: 71fb strb r3, [r7, #7] + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); + 8002570: f997 3007 ldrsb.w r3, [r7, #7] + 8002574: 4618 mov r0, r3 + 8002576: f7ff ff31 bl 80023dc <__NVIC_EnableIRQ> +} + 800257a: bf00 nop + 800257c: 3708 adds r7, #8 + 800257e: 46bd mov sp, r7 + 8002580: bd80 pop {r7, pc} + +08002582 : + * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + 8002582: b580 push {r7, lr} + 8002584: b082 sub sp, #8 + 8002586: af00 add r7, sp, #0 + 8002588: 6078 str r0, [r7, #4] + return SysTick_Config(TicksNumb); + 800258a: 6878 ldr r0, [r7, #4] + 800258c: f7ff ffa2 bl 80024d4 + 8002590: 4603 mov r3, r0 +} + 8002592: 4618 mov r0, r3 + 8002594: 3708 adds r7, #8 + 8002596: 46bd mov sp, r7 + 8002598: bd80 pop {r7, pc} + ... + +0800259c : + * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + 800259c: b480 push {r7} + 800259e: b089 sub sp, #36 ; 0x24 + 80025a0: af00 add r7, sp, #0 + 80025a2: 6078 str r0, [r7, #4] + 80025a4: 6039 str r1, [r7, #0] + uint32_t position; + uint32_t ioposition = 0x00U; + 80025a6: 2300 movs r3, #0 + 80025a8: 617b str r3, [r7, #20] + uint32_t iocurrent = 0x00U; + 80025aa: 2300 movs r3, #0 + 80025ac: 613b str r3, [r7, #16] + uint32_t temp = 0x00U; + 80025ae: 2300 movs r3, #0 + 80025b0: 61bb str r3, [r7, #24] + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Configure the port pins */ + for(position = 0U; position < GPIO_NUMBER; position++) + 80025b2: 2300 movs r3, #0 + 80025b4: 61fb str r3, [r7, #28] + 80025b6: e159 b.n 800286c + { + /* Get the IO position */ + ioposition = 0x01U << position; + 80025b8: 2201 movs r2, #1 + 80025ba: 69fb ldr r3, [r7, #28] + 80025bc: fa02 f303 lsl.w r3, r2, r3 + 80025c0: 617b str r3, [r7, #20] + /* Get the current IO position */ + iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; + 80025c2: 683b ldr r3, [r7, #0] + 80025c4: 681b ldr r3, [r3, #0] + 80025c6: 697a ldr r2, [r7, #20] + 80025c8: 4013 ands r3, r2 + 80025ca: 613b str r3, [r7, #16] + + if(iocurrent == ioposition) + 80025cc: 693a ldr r2, [r7, #16] + 80025ce: 697b ldr r3, [r7, #20] + 80025d0: 429a cmp r2, r3 + 80025d2: f040 8148 bne.w 8002866 + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Output or Alternate function mode selection */ + if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || + 80025d6: 683b ldr r3, [r7, #0] + 80025d8: 685b ldr r3, [r3, #4] + 80025da: 2b01 cmp r3, #1 + 80025dc: d00b beq.n 80025f6 + 80025de: 683b ldr r3, [r7, #0] + 80025e0: 685b ldr r3, [r3, #4] + 80025e2: 2b02 cmp r3, #2 + 80025e4: d007 beq.n 80025f6 + (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + 80025e6: 683b ldr r3, [r7, #0] + 80025e8: 685b ldr r3, [r3, #4] + if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || + 80025ea: 2b11 cmp r3, #17 + 80025ec: d003 beq.n 80025f6 + (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + 80025ee: 683b ldr r3, [r7, #0] + 80025f0: 685b ldr r3, [r3, #4] + 80025f2: 2b12 cmp r3, #18 + 80025f4: d130 bne.n 8002658 + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + /* Configure the IO Speed */ + temp = GPIOx->OSPEEDR; + 80025f6: 687b ldr r3, [r7, #4] + 80025f8: 689b ldr r3, [r3, #8] + 80025fa: 61bb str r3, [r7, #24] + temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U)); + 80025fc: 69fb ldr r3, [r7, #28] + 80025fe: 005b lsls r3, r3, #1 + 8002600: 2203 movs r2, #3 + 8002602: fa02 f303 lsl.w r3, r2, r3 + 8002606: 43db mvns r3, r3 + 8002608: 69ba ldr r2, [r7, #24] + 800260a: 4013 ands r3, r2 + 800260c: 61bb str r3, [r7, #24] + temp |= (GPIO_Init->Speed << (position * 2U)); + 800260e: 683b ldr r3, [r7, #0] + 8002610: 68da ldr r2, [r3, #12] + 8002612: 69fb ldr r3, [r7, #28] + 8002614: 005b lsls r3, r3, #1 + 8002616: fa02 f303 lsl.w r3, r2, r3 + 800261a: 69ba ldr r2, [r7, #24] + 800261c: 4313 orrs r3, r2 + 800261e: 61bb str r3, [r7, #24] + GPIOx->OSPEEDR = temp; + 8002620: 687b ldr r3, [r7, #4] + 8002622: 69ba ldr r2, [r7, #24] + 8002624: 609a str r2, [r3, #8] + + /* Configure the IO Output Type */ + temp = GPIOx->OTYPER; + 8002626: 687b ldr r3, [r7, #4] + 8002628: 685b ldr r3, [r3, #4] + 800262a: 61bb str r3, [r7, #24] + temp &= ~(GPIO_OTYPER_OT_0 << position) ; + 800262c: 2201 movs r2, #1 + 800262e: 69fb ldr r3, [r7, #28] + 8002630: fa02 f303 lsl.w r3, r2, r3 + 8002634: 43db mvns r3, r3 + 8002636: 69ba ldr r2, [r7, #24] + 8002638: 4013 ands r3, r2 + 800263a: 61bb str r3, [r7, #24] + temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position); + 800263c: 683b ldr r3, [r7, #0] + 800263e: 685b ldr r3, [r3, #4] + 8002640: 091b lsrs r3, r3, #4 + 8002642: f003 0201 and.w r2, r3, #1 + 8002646: 69fb ldr r3, [r7, #28] + 8002648: fa02 f303 lsl.w r3, r2, r3 + 800264c: 69ba ldr r2, [r7, #24] + 800264e: 4313 orrs r3, r2 + 8002650: 61bb str r3, [r7, #24] + GPIOx->OTYPER = temp; + 8002652: 687b ldr r3, [r7, #4] + 8002654: 69ba ldr r2, [r7, #24] + 8002656: 605a str r2, [r3, #4] + } + + /* Activate the Pull-up or Pull down resistor for the current IO */ + temp = GPIOx->PUPDR; + 8002658: 687b ldr r3, [r7, #4] + 800265a: 68db ldr r3, [r3, #12] + 800265c: 61bb str r3, [r7, #24] + temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U)); + 800265e: 69fb ldr r3, [r7, #28] + 8002660: 005b lsls r3, r3, #1 + 8002662: 2203 movs r2, #3 + 8002664: fa02 f303 lsl.w r3, r2, r3 + 8002668: 43db mvns r3, r3 + 800266a: 69ba ldr r2, [r7, #24] + 800266c: 4013 ands r3, r2 + 800266e: 61bb str r3, [r7, #24] + temp |= ((GPIO_Init->Pull) << (position * 2U)); + 8002670: 683b ldr r3, [r7, #0] + 8002672: 689a ldr r2, [r3, #8] + 8002674: 69fb ldr r3, [r7, #28] + 8002676: 005b lsls r3, r3, #1 + 8002678: fa02 f303 lsl.w r3, r2, r3 + 800267c: 69ba ldr r2, [r7, #24] + 800267e: 4313 orrs r3, r2 + 8002680: 61bb str r3, [r7, #24] + GPIOx->PUPDR = temp; + 8002682: 687b ldr r3, [r7, #4] + 8002684: 69ba ldr r2, [r7, #24] + 8002686: 60da str r2, [r3, #12] + + /* In case of Alternate function mode selection */ + if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + 8002688: 683b ldr r3, [r7, #0] + 800268a: 685b ldr r3, [r3, #4] + 800268c: 2b02 cmp r3, #2 + 800268e: d003 beq.n 8002698 + 8002690: 683b ldr r3, [r7, #0] + 8002692: 685b ldr r3, [r3, #4] + 8002694: 2b12 cmp r3, #18 + 8002696: d123 bne.n 80026e0 + { + /* Check the Alternate function parameter */ + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + /* Configure Alternate function mapped with the current IO */ + temp = GPIOx->AFR[position >> 3U]; + 8002698: 69fb ldr r3, [r7, #28] + 800269a: 08da lsrs r2, r3, #3 + 800269c: 687b ldr r3, [r7, #4] + 800269e: 3208 adds r2, #8 + 80026a0: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 80026a4: 61bb str r3, [r7, #24] + temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ; + 80026a6: 69fb ldr r3, [r7, #28] + 80026a8: f003 0307 and.w r3, r3, #7 + 80026ac: 009b lsls r3, r3, #2 + 80026ae: 220f movs r2, #15 + 80026b0: fa02 f303 lsl.w r3, r2, r3 + 80026b4: 43db mvns r3, r3 + 80026b6: 69ba ldr r2, [r7, #24] + 80026b8: 4013 ands r3, r2 + 80026ba: 61bb str r3, [r7, #24] + temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U)); + 80026bc: 683b ldr r3, [r7, #0] + 80026be: 691a ldr r2, [r3, #16] + 80026c0: 69fb ldr r3, [r7, #28] + 80026c2: f003 0307 and.w r3, r3, #7 + 80026c6: 009b lsls r3, r3, #2 + 80026c8: fa02 f303 lsl.w r3, r2, r3 + 80026cc: 69ba ldr r2, [r7, #24] + 80026ce: 4313 orrs r3, r2 + 80026d0: 61bb str r3, [r7, #24] + GPIOx->AFR[position >> 3U] = temp; + 80026d2: 69fb ldr r3, [r7, #28] + 80026d4: 08da lsrs r2, r3, #3 + 80026d6: 687b ldr r3, [r7, #4] + 80026d8: 3208 adds r2, #8 + 80026da: 69b9 ldr r1, [r7, #24] + 80026dc: f843 1022 str.w r1, [r3, r2, lsl #2] + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + 80026e0: 687b ldr r3, [r7, #4] + 80026e2: 681b ldr r3, [r3, #0] + 80026e4: 61bb str r3, [r7, #24] + temp &= ~(GPIO_MODER_MODER0 << (position * 2U)); + 80026e6: 69fb ldr r3, [r7, #28] + 80026e8: 005b lsls r3, r3, #1 + 80026ea: 2203 movs r2, #3 + 80026ec: fa02 f303 lsl.w r3, r2, r3 + 80026f0: 43db mvns r3, r3 + 80026f2: 69ba ldr r2, [r7, #24] + 80026f4: 4013 ands r3, r2 + 80026f6: 61bb str r3, [r7, #24] + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); + 80026f8: 683b ldr r3, [r7, #0] + 80026fa: 685b ldr r3, [r3, #4] + 80026fc: f003 0203 and.w r2, r3, #3 + 8002700: 69fb ldr r3, [r7, #28] + 8002702: 005b lsls r3, r3, #1 + 8002704: fa02 f303 lsl.w r3, r2, r3 + 8002708: 69ba ldr r2, [r7, #24] + 800270a: 4313 orrs r3, r2 + 800270c: 61bb str r3, [r7, #24] + GPIOx->MODER = temp; + 800270e: 687b ldr r3, [r7, #4] + 8002710: 69ba ldr r2, [r7, #24] + 8002712: 601a str r2, [r3, #0] + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) + 8002714: 683b ldr r3, [r7, #0] + 8002716: 685b ldr r3, [r3, #4] + 8002718: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 800271c: 2b00 cmp r3, #0 + 800271e: f000 80a2 beq.w 8002866 + { + /* Enable SYSCFG Clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + 8002722: 2300 movs r3, #0 + 8002724: 60fb str r3, [r7, #12] + 8002726: 4b56 ldr r3, [pc, #344] ; (8002880 ) + 8002728: 6c5b ldr r3, [r3, #68] ; 0x44 + 800272a: 4a55 ldr r2, [pc, #340] ; (8002880 ) + 800272c: f443 4380 orr.w r3, r3, #16384 ; 0x4000 + 8002730: 6453 str r3, [r2, #68] ; 0x44 + 8002732: 4b53 ldr r3, [pc, #332] ; (8002880 ) + 8002734: 6c5b ldr r3, [r3, #68] ; 0x44 + 8002736: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 800273a: 60fb str r3, [r7, #12] + 800273c: 68fb ldr r3, [r7, #12] + + temp = SYSCFG->EXTICR[position >> 2U]; + 800273e: 4a51 ldr r2, [pc, #324] ; (8002884 ) + 8002740: 69fb ldr r3, [r7, #28] + 8002742: 089b lsrs r3, r3, #2 + 8002744: 3302 adds r3, #2 + 8002746: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 800274a: 61bb str r3, [r7, #24] + temp &= ~(0x0FU << (4U * (position & 0x03U))); + 800274c: 69fb ldr r3, [r7, #28] + 800274e: f003 0303 and.w r3, r3, #3 + 8002752: 009b lsls r3, r3, #2 + 8002754: 220f movs r2, #15 + 8002756: fa02 f303 lsl.w r3, r2, r3 + 800275a: 43db mvns r3, r3 + 800275c: 69ba ldr r2, [r7, #24] + 800275e: 4013 ands r3, r2 + 8002760: 61bb str r3, [r7, #24] + temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))); + 8002762: 687b ldr r3, [r7, #4] + 8002764: 4a48 ldr r2, [pc, #288] ; (8002888 ) + 8002766: 4293 cmp r3, r2 + 8002768: d019 beq.n 800279e + 800276a: 687b ldr r3, [r7, #4] + 800276c: 4a47 ldr r2, [pc, #284] ; (800288c ) + 800276e: 4293 cmp r3, r2 + 8002770: d013 beq.n 800279a + 8002772: 687b ldr r3, [r7, #4] + 8002774: 4a46 ldr r2, [pc, #280] ; (8002890 ) + 8002776: 4293 cmp r3, r2 + 8002778: d00d beq.n 8002796 + 800277a: 687b ldr r3, [r7, #4] + 800277c: 4a45 ldr r2, [pc, #276] ; (8002894 ) + 800277e: 4293 cmp r3, r2 + 8002780: d007 beq.n 8002792 + 8002782: 687b ldr r3, [r7, #4] + 8002784: 4a44 ldr r2, [pc, #272] ; (8002898 ) + 8002786: 4293 cmp r3, r2 + 8002788: d101 bne.n 800278e + 800278a: 2304 movs r3, #4 + 800278c: e008 b.n 80027a0 + 800278e: 2307 movs r3, #7 + 8002790: e006 b.n 80027a0 + 8002792: 2303 movs r3, #3 + 8002794: e004 b.n 80027a0 + 8002796: 2302 movs r3, #2 + 8002798: e002 b.n 80027a0 + 800279a: 2301 movs r3, #1 + 800279c: e000 b.n 80027a0 + 800279e: 2300 movs r3, #0 + 80027a0: 69fa ldr r2, [r7, #28] + 80027a2: f002 0203 and.w r2, r2, #3 + 80027a6: 0092 lsls r2, r2, #2 + 80027a8: 4093 lsls r3, r2 + 80027aa: 69ba ldr r2, [r7, #24] + 80027ac: 4313 orrs r3, r2 + 80027ae: 61bb str r3, [r7, #24] + SYSCFG->EXTICR[position >> 2U] = temp; + 80027b0: 4934 ldr r1, [pc, #208] ; (8002884 ) + 80027b2: 69fb ldr r3, [r7, #28] + 80027b4: 089b lsrs r3, r3, #2 + 80027b6: 3302 adds r3, #2 + 80027b8: 69ba ldr r2, [r7, #24] + 80027ba: f841 2023 str.w r2, [r1, r3, lsl #2] + + /* Clear EXTI line configuration */ + temp = EXTI->IMR; + 80027be: 4b37 ldr r3, [pc, #220] ; (800289c ) + 80027c0: 681b ldr r3, [r3, #0] + 80027c2: 61bb str r3, [r7, #24] + temp &= ~((uint32_t)iocurrent); + 80027c4: 693b ldr r3, [r7, #16] + 80027c6: 43db mvns r3, r3 + 80027c8: 69ba ldr r2, [r7, #24] + 80027ca: 4013 ands r3, r2 + 80027cc: 61bb str r3, [r7, #24] + if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) + 80027ce: 683b ldr r3, [r7, #0] + 80027d0: 685b ldr r3, [r3, #4] + 80027d2: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 80027d6: 2b00 cmp r3, #0 + 80027d8: d003 beq.n 80027e2 + { + temp |= iocurrent; + 80027da: 69ba ldr r2, [r7, #24] + 80027dc: 693b ldr r3, [r7, #16] + 80027de: 4313 orrs r3, r2 + 80027e0: 61bb str r3, [r7, #24] + } + EXTI->IMR = temp; + 80027e2: 4a2e ldr r2, [pc, #184] ; (800289c ) + 80027e4: 69bb ldr r3, [r7, #24] + 80027e6: 6013 str r3, [r2, #0] + + temp = EXTI->EMR; + 80027e8: 4b2c ldr r3, [pc, #176] ; (800289c ) + 80027ea: 685b ldr r3, [r3, #4] + 80027ec: 61bb str r3, [r7, #24] + temp &= ~((uint32_t)iocurrent); + 80027ee: 693b ldr r3, [r7, #16] + 80027f0: 43db mvns r3, r3 + 80027f2: 69ba ldr r2, [r7, #24] + 80027f4: 4013 ands r3, r2 + 80027f6: 61bb str r3, [r7, #24] + if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) + 80027f8: 683b ldr r3, [r7, #0] + 80027fa: 685b ldr r3, [r3, #4] + 80027fc: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8002800: 2b00 cmp r3, #0 + 8002802: d003 beq.n 800280c + { + temp |= iocurrent; + 8002804: 69ba ldr r2, [r7, #24] + 8002806: 693b ldr r3, [r7, #16] + 8002808: 4313 orrs r3, r2 + 800280a: 61bb str r3, [r7, #24] + } + EXTI->EMR = temp; + 800280c: 4a23 ldr r2, [pc, #140] ; (800289c ) + 800280e: 69bb ldr r3, [r7, #24] + 8002810: 6053 str r3, [r2, #4] + + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR; + 8002812: 4b22 ldr r3, [pc, #136] ; (800289c ) + 8002814: 689b ldr r3, [r3, #8] + 8002816: 61bb str r3, [r7, #24] + temp &= ~((uint32_t)iocurrent); + 8002818: 693b ldr r3, [r7, #16] + 800281a: 43db mvns r3, r3 + 800281c: 69ba ldr r2, [r7, #24] + 800281e: 4013 ands r3, r2 + 8002820: 61bb str r3, [r7, #24] + if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) + 8002822: 683b ldr r3, [r7, #0] + 8002824: 685b ldr r3, [r3, #4] + 8002826: f403 1380 and.w r3, r3, #1048576 ; 0x100000 + 800282a: 2b00 cmp r3, #0 + 800282c: d003 beq.n 8002836 + { + temp |= iocurrent; + 800282e: 69ba ldr r2, [r7, #24] + 8002830: 693b ldr r3, [r7, #16] + 8002832: 4313 orrs r3, r2 + 8002834: 61bb str r3, [r7, #24] + } + EXTI->RTSR = temp; + 8002836: 4a19 ldr r2, [pc, #100] ; (800289c ) + 8002838: 69bb ldr r3, [r7, #24] + 800283a: 6093 str r3, [r2, #8] + + temp = EXTI->FTSR; + 800283c: 4b17 ldr r3, [pc, #92] ; (800289c ) + 800283e: 68db ldr r3, [r3, #12] + 8002840: 61bb str r3, [r7, #24] + temp &= ~((uint32_t)iocurrent); + 8002842: 693b ldr r3, [r7, #16] + 8002844: 43db mvns r3, r3 + 8002846: 69ba ldr r2, [r7, #24] + 8002848: 4013 ands r3, r2 + 800284a: 61bb str r3, [r7, #24] + if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) + 800284c: 683b ldr r3, [r7, #0] + 800284e: 685b ldr r3, [r3, #4] + 8002850: f403 1300 and.w r3, r3, #2097152 ; 0x200000 + 8002854: 2b00 cmp r3, #0 + 8002856: d003 beq.n 8002860 + { + temp |= iocurrent; + 8002858: 69ba ldr r2, [r7, #24] + 800285a: 693b ldr r3, [r7, #16] + 800285c: 4313 orrs r3, r2 + 800285e: 61bb str r3, [r7, #24] + } + EXTI->FTSR = temp; + 8002860: 4a0e ldr r2, [pc, #56] ; (800289c ) + 8002862: 69bb ldr r3, [r7, #24] + 8002864: 60d3 str r3, [r2, #12] + for(position = 0U; position < GPIO_NUMBER; position++) + 8002866: 69fb ldr r3, [r7, #28] + 8002868: 3301 adds r3, #1 + 800286a: 61fb str r3, [r7, #28] + 800286c: 69fb ldr r3, [r7, #28] + 800286e: 2b0f cmp r3, #15 + 8002870: f67f aea2 bls.w 80025b8 + } + } + } +} + 8002874: bf00 nop + 8002876: 3724 adds r7, #36 ; 0x24 + 8002878: 46bd mov sp, r7 + 800287a: f85d 7b04 ldr.w r7, [sp], #4 + 800287e: 4770 bx lr + 8002880: 40023800 .word 0x40023800 + 8002884: 40013800 .word 0x40013800 + 8002888: 40020000 .word 0x40020000 + 800288c: 40020400 .word 0x40020400 + 8002890: 40020800 .word 0x40020800 + 8002894: 40020c00 .word 0x40020c00 + 8002898: 40021000 .word 0x40021000 + 800289c: 40013c00 .word 0x40013c00 + +080028a0 : + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + 80028a0: b480 push {r7} + 80028a2: b083 sub sp, #12 + 80028a4: af00 add r7, sp, #0 + 80028a6: 6078 str r0, [r7, #4] + 80028a8: 460b mov r3, r1 + 80028aa: 807b strh r3, [r7, #2] + 80028ac: 4613 mov r3, r2 + 80028ae: 707b strb r3, [r7, #1] + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if(PinState != GPIO_PIN_RESET) + 80028b0: 787b ldrb r3, [r7, #1] + 80028b2: 2b00 cmp r3, #0 + 80028b4: d003 beq.n 80028be + { + GPIOx->BSRR = GPIO_Pin; + 80028b6: 887a ldrh r2, [r7, #2] + 80028b8: 687b ldr r3, [r7, #4] + 80028ba: 619a str r2, [r3, #24] + } + else + { + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; + } +} + 80028bc: e003 b.n 80028c6 + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; + 80028be: 887b ldrh r3, [r7, #2] + 80028c0: 041a lsls r2, r3, #16 + 80028c2: 687b ldr r3, [r7, #4] + 80028c4: 619a str r2, [r3, #24] +} + 80028c6: bf00 nop + 80028c8: 370c adds r7, #12 + 80028ca: 46bd mov sp, r7 + 80028cc: f85d 7b04 ldr.w r7, [sp], #4 + 80028d0: 4770 bx lr + +080028d2 : + * @brief Initialize the host driver. + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd) +{ + 80028d2: b5f0 push {r4, r5, r6, r7, lr} + 80028d4: b08f sub sp, #60 ; 0x3c + 80028d6: af0a add r7, sp, #40 ; 0x28 + 80028d8: 6078 str r0, [r7, #4] + USB_OTG_GlobalTypeDef *USBx; + + /* Check the HCD handle allocation */ + if (hhcd == NULL) + 80028da: 687b ldr r3, [r7, #4] + 80028dc: 2b00 cmp r3, #0 + 80028de: d101 bne.n 80028e4 + { + return HAL_ERROR; + 80028e0: 2301 movs r3, #1 + 80028e2: e054 b.n 800298e + } + + /* Check the parameters */ + assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance)); + + USBx = hhcd->Instance; + 80028e4: 687b ldr r3, [r7, #4] + 80028e6: 681b ldr r3, [r3, #0] + 80028e8: 60fb str r3, [r7, #12] + + if (hhcd->State == HAL_HCD_STATE_RESET) + 80028ea: 687b ldr r3, [r7, #4] + 80028ec: f893 32b9 ldrb.w r3, [r3, #697] ; 0x2b9 + 80028f0: b2db uxtb r3, r3 + 80028f2: 2b00 cmp r3, #0 + 80028f4: d106 bne.n 8002904 + { + /* Allocate lock resource and initialize it */ + hhcd->Lock = HAL_UNLOCKED; + 80028f6: 687b ldr r3, [r7, #4] + 80028f8: 2200 movs r2, #0 + 80028fa: f883 22b8 strb.w r2, [r3, #696] ; 0x2b8 + + /* Init the low level hardware */ + hhcd->MspInitCallback(hhcd); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_HCD_MspInit(hhcd); + 80028fe: 6878 ldr r0, [r7, #4] + 8002900: f007 fa62 bl 8009dc8 +#endif /* (USE_HAL_HCD_REGISTER_CALLBACKS) */ + } + + hhcd->State = HAL_HCD_STATE_BUSY; + 8002904: 687b ldr r3, [r7, #4] + 8002906: 2203 movs r2, #3 + 8002908: f883 22b9 strb.w r2, [r3, #697] ; 0x2b9 + + /* Disable DMA mode for FS instance */ + if ((USBx->CID & (0x1U << 8)) == 0U) + 800290c: 68fb ldr r3, [r7, #12] + 800290e: 6bdb ldr r3, [r3, #60] ; 0x3c + 8002910: f403 7380 and.w r3, r3, #256 ; 0x100 + 8002914: 2b00 cmp r3, #0 + 8002916: d102 bne.n 800291e + { + hhcd->Init.dma_enable = 0U; + 8002918: 687b ldr r3, [r7, #4] + 800291a: 2200 movs r2, #0 + 800291c: 611a str r2, [r3, #16] + } + + /* Disable the Interrupts */ + __HAL_HCD_DISABLE(hhcd); + 800291e: 687b ldr r3, [r7, #4] + 8002920: 681b ldr r3, [r3, #0] + 8002922: 4618 mov r0, r3 + 8002924: f004 fc1e bl 8007164 + + /* Init the Core (common init.) */ + (void)USB_CoreInit(hhcd->Instance, hhcd->Init); + 8002928: 687b ldr r3, [r7, #4] + 800292a: 681b ldr r3, [r3, #0] + 800292c: 603b str r3, [r7, #0] + 800292e: 687e ldr r6, [r7, #4] + 8002930: 466d mov r5, sp + 8002932: f106 0410 add.w r4, r6, #16 + 8002936: cc0f ldmia r4!, {r0, r1, r2, r3} + 8002938: c50f stmia r5!, {r0, r1, r2, r3} + 800293a: cc0f ldmia r4!, {r0, r1, r2, r3} + 800293c: c50f stmia r5!, {r0, r1, r2, r3} + 800293e: e894 0003 ldmia.w r4, {r0, r1} + 8002942: e885 0003 stmia.w r5, {r0, r1} + 8002946: 1d33 adds r3, r6, #4 + 8002948: cb0e ldmia r3, {r1, r2, r3} + 800294a: 6838 ldr r0, [r7, #0] + 800294c: f004 fb98 bl 8007080 + + /* Force Host Mode*/ + (void)USB_SetCurrentMode(hhcd->Instance, USB_HOST_MODE); + 8002950: 687b ldr r3, [r7, #4] + 8002952: 681b ldr r3, [r3, #0] + 8002954: 2101 movs r1, #1 + 8002956: 4618 mov r0, r3 + 8002958: f004 fc15 bl 8007186 + + /* Init Host */ + (void)USB_HostInit(hhcd->Instance, hhcd->Init); + 800295c: 687b ldr r3, [r7, #4] + 800295e: 681b ldr r3, [r3, #0] + 8002960: 603b str r3, [r7, #0] + 8002962: 687e ldr r6, [r7, #4] + 8002964: 466d mov r5, sp + 8002966: f106 0410 add.w r4, r6, #16 + 800296a: cc0f ldmia r4!, {r0, r1, r2, r3} + 800296c: c50f stmia r5!, {r0, r1, r2, r3} + 800296e: cc0f ldmia r4!, {r0, r1, r2, r3} + 8002970: c50f stmia r5!, {r0, r1, r2, r3} + 8002972: e894 0003 ldmia.w r4, {r0, r1} + 8002976: e885 0003 stmia.w r5, {r0, r1} + 800297a: 1d33 adds r3, r6, #4 + 800297c: cb0e ldmia r3, {r1, r2, r3} + 800297e: 6838 ldr r0, [r7, #0] + 8002980: f004 fd28 bl 80073d4 + + hhcd->State = HAL_HCD_STATE_READY; + 8002984: 687b ldr r3, [r7, #4] + 8002986: 2201 movs r2, #1 + 8002988: f883 22b9 strb.w r2, [r3, #697] ; 0x2b9 + + return HAL_OK; + 800298c: 2300 movs r3, #0 +} + 800298e: 4618 mov r0, r3 + 8002990: 3714 adds r7, #20 + 8002992: 46bd mov sp, r7 + 8002994: bdf0 pop {r4, r5, r6, r7, pc} + +08002996 : + uint8_t epnum, + uint8_t dev_address, + uint8_t speed, + uint8_t ep_type, + uint16_t mps) +{ + 8002996: b590 push {r4, r7, lr} + 8002998: b089 sub sp, #36 ; 0x24 + 800299a: af04 add r7, sp, #16 + 800299c: 6078 str r0, [r7, #4] + 800299e: 4608 mov r0, r1 + 80029a0: 4611 mov r1, r2 + 80029a2: 461a mov r2, r3 + 80029a4: 4603 mov r3, r0 + 80029a6: 70fb strb r3, [r7, #3] + 80029a8: 460b mov r3, r1 + 80029aa: 70bb strb r3, [r7, #2] + 80029ac: 4613 mov r3, r2 + 80029ae: 707b strb r3, [r7, #1] + HAL_StatusTypeDef status; + + __HAL_LOCK(hhcd); + 80029b0: 687b ldr r3, [r7, #4] + 80029b2: f893 32b8 ldrb.w r3, [r3, #696] ; 0x2b8 + 80029b6: 2b01 cmp r3, #1 + 80029b8: d101 bne.n 80029be + 80029ba: 2302 movs r3, #2 + 80029bc: e07f b.n 8002abe + 80029be: 687b ldr r3, [r7, #4] + 80029c0: 2201 movs r2, #1 + 80029c2: f883 22b8 strb.w r2, [r3, #696] ; 0x2b8 + hhcd->hc[ch_num].do_ping = 0U; + 80029c6: 78fa ldrb r2, [r7, #3] + 80029c8: 6879 ldr r1, [r7, #4] + 80029ca: 4613 mov r3, r2 + 80029cc: 009b lsls r3, r3, #2 + 80029ce: 4413 add r3, r2 + 80029d0: 00db lsls r3, r3, #3 + 80029d2: 440b add r3, r1 + 80029d4: 333d adds r3, #61 ; 0x3d + 80029d6: 2200 movs r2, #0 + 80029d8: 701a strb r2, [r3, #0] + hhcd->hc[ch_num].dev_addr = dev_address; + 80029da: 78fa ldrb r2, [r7, #3] + 80029dc: 6879 ldr r1, [r7, #4] + 80029de: 4613 mov r3, r2 + 80029e0: 009b lsls r3, r3, #2 + 80029e2: 4413 add r3, r2 + 80029e4: 00db lsls r3, r3, #3 + 80029e6: 440b add r3, r1 + 80029e8: 3338 adds r3, #56 ; 0x38 + 80029ea: 787a ldrb r2, [r7, #1] + 80029ec: 701a strb r2, [r3, #0] + hhcd->hc[ch_num].max_packet = mps; + 80029ee: 78fa ldrb r2, [r7, #3] + 80029f0: 6879 ldr r1, [r7, #4] + 80029f2: 4613 mov r3, r2 + 80029f4: 009b lsls r3, r3, #2 + 80029f6: 4413 add r3, r2 + 80029f8: 00db lsls r3, r3, #3 + 80029fa: 440b add r3, r1 + 80029fc: 3340 adds r3, #64 ; 0x40 + 80029fe: 8d3a ldrh r2, [r7, #40] ; 0x28 + 8002a00: 801a strh r2, [r3, #0] + hhcd->hc[ch_num].ch_num = ch_num; + 8002a02: 78fa ldrb r2, [r7, #3] + 8002a04: 6879 ldr r1, [r7, #4] + 8002a06: 4613 mov r3, r2 + 8002a08: 009b lsls r3, r3, #2 + 8002a0a: 4413 add r3, r2 + 8002a0c: 00db lsls r3, r3, #3 + 8002a0e: 440b add r3, r1 + 8002a10: 3339 adds r3, #57 ; 0x39 + 8002a12: 78fa ldrb r2, [r7, #3] + 8002a14: 701a strb r2, [r3, #0] + hhcd->hc[ch_num].ep_type = ep_type; + 8002a16: 78fa ldrb r2, [r7, #3] + 8002a18: 6879 ldr r1, [r7, #4] + 8002a1a: 4613 mov r3, r2 + 8002a1c: 009b lsls r3, r3, #2 + 8002a1e: 4413 add r3, r2 + 8002a20: 00db lsls r3, r3, #3 + 8002a22: 440b add r3, r1 + 8002a24: 333f adds r3, #63 ; 0x3f + 8002a26: f897 2024 ldrb.w r2, [r7, #36] ; 0x24 + 8002a2a: 701a strb r2, [r3, #0] + hhcd->hc[ch_num].ep_num = epnum & 0x7FU; + 8002a2c: 78fa ldrb r2, [r7, #3] + 8002a2e: 78bb ldrb r3, [r7, #2] + 8002a30: f003 037f and.w r3, r3, #127 ; 0x7f + 8002a34: b2d8 uxtb r0, r3 + 8002a36: 6879 ldr r1, [r7, #4] + 8002a38: 4613 mov r3, r2 + 8002a3a: 009b lsls r3, r3, #2 + 8002a3c: 4413 add r3, r2 + 8002a3e: 00db lsls r3, r3, #3 + 8002a40: 440b add r3, r1 + 8002a42: 333a adds r3, #58 ; 0x3a + 8002a44: 4602 mov r2, r0 + 8002a46: 701a strb r2, [r3, #0] + + if ((epnum & 0x80U) == 0x80U) + 8002a48: f997 3002 ldrsb.w r3, [r7, #2] + 8002a4c: 2b00 cmp r3, #0 + 8002a4e: da0a bge.n 8002a66 + { + hhcd->hc[ch_num].ep_is_in = 1U; + 8002a50: 78fa ldrb r2, [r7, #3] + 8002a52: 6879 ldr r1, [r7, #4] + 8002a54: 4613 mov r3, r2 + 8002a56: 009b lsls r3, r3, #2 + 8002a58: 4413 add r3, r2 + 8002a5a: 00db lsls r3, r3, #3 + 8002a5c: 440b add r3, r1 + 8002a5e: 333b adds r3, #59 ; 0x3b + 8002a60: 2201 movs r2, #1 + 8002a62: 701a strb r2, [r3, #0] + 8002a64: e009 b.n 8002a7a + } + else + { + hhcd->hc[ch_num].ep_is_in = 0U; + 8002a66: 78fa ldrb r2, [r7, #3] + 8002a68: 6879 ldr r1, [r7, #4] + 8002a6a: 4613 mov r3, r2 + 8002a6c: 009b lsls r3, r3, #2 + 8002a6e: 4413 add r3, r2 + 8002a70: 00db lsls r3, r3, #3 + 8002a72: 440b add r3, r1 + 8002a74: 333b adds r3, #59 ; 0x3b + 8002a76: 2200 movs r2, #0 + 8002a78: 701a strb r2, [r3, #0] + } + + hhcd->hc[ch_num].speed = speed; + 8002a7a: 78fa ldrb r2, [r7, #3] + 8002a7c: 6879 ldr r1, [r7, #4] + 8002a7e: 4613 mov r3, r2 + 8002a80: 009b lsls r3, r3, #2 + 8002a82: 4413 add r3, r2 + 8002a84: 00db lsls r3, r3, #3 + 8002a86: 440b add r3, r1 + 8002a88: 333c adds r3, #60 ; 0x3c + 8002a8a: f897 2020 ldrb.w r2, [r7, #32] + 8002a8e: 701a strb r2, [r3, #0] + + status = USB_HC_Init(hhcd->Instance, + 8002a90: 687b ldr r3, [r7, #4] + 8002a92: 6818 ldr r0, [r3, #0] + 8002a94: 787c ldrb r4, [r7, #1] + 8002a96: 78ba ldrb r2, [r7, #2] + 8002a98: 78f9 ldrb r1, [r7, #3] + 8002a9a: 8d3b ldrh r3, [r7, #40] ; 0x28 + 8002a9c: 9302 str r3, [sp, #8] + 8002a9e: f897 3024 ldrb.w r3, [r7, #36] ; 0x24 + 8002aa2: 9301 str r3, [sp, #4] + 8002aa4: f897 3020 ldrb.w r3, [r7, #32] + 8002aa8: 9300 str r3, [sp, #0] + 8002aaa: 4623 mov r3, r4 + 8002aac: f004 fe14 bl 80076d8 + 8002ab0: 4603 mov r3, r0 + 8002ab2: 73fb strb r3, [r7, #15] + epnum, + dev_address, + speed, + ep_type, + mps); + __HAL_UNLOCK(hhcd); + 8002ab4: 687b ldr r3, [r7, #4] + 8002ab6: 2200 movs r2, #0 + 8002ab8: f883 22b8 strb.w r2, [r3, #696] ; 0x2b8 + + return status; + 8002abc: 7bfb ldrb r3, [r7, #15] +} + 8002abe: 4618 mov r0, r3 + 8002ac0: 3714 adds r7, #20 + 8002ac2: 46bd mov sp, r7 + 8002ac4: bd90 pop {r4, r7, pc} + +08002ac6 : + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num) +{ + 8002ac6: b580 push {r7, lr} + 8002ac8: b084 sub sp, #16 + 8002aca: af00 add r7, sp, #0 + 8002acc: 6078 str r0, [r7, #4] + 8002ace: 460b mov r3, r1 + 8002ad0: 70fb strb r3, [r7, #3] + HAL_StatusTypeDef status = HAL_OK; + 8002ad2: 2300 movs r3, #0 + 8002ad4: 73fb strb r3, [r7, #15] + + __HAL_LOCK(hhcd); + 8002ad6: 687b ldr r3, [r7, #4] + 8002ad8: f893 32b8 ldrb.w r3, [r3, #696] ; 0x2b8 + 8002adc: 2b01 cmp r3, #1 + 8002ade: d101 bne.n 8002ae4 + 8002ae0: 2302 movs r3, #2 + 8002ae2: e00f b.n 8002b04 + 8002ae4: 687b ldr r3, [r7, #4] + 8002ae6: 2201 movs r2, #1 + 8002ae8: f883 22b8 strb.w r2, [r3, #696] ; 0x2b8 + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + 8002aec: 687b ldr r3, [r7, #4] + 8002aee: 681b ldr r3, [r3, #0] + 8002af0: 78fa ldrb r2, [r7, #3] + 8002af2: 4611 mov r1, r2 + 8002af4: 4618 mov r0, r3 + 8002af6: f005 f850 bl 8007b9a + __HAL_UNLOCK(hhcd); + 8002afa: 687b ldr r3, [r7, #4] + 8002afc: 2200 movs r2, #0 + 8002afe: f883 22b8 strb.w r2, [r3, #696] ; 0x2b8 + + return status; + 8002b02: 7bfb ldrb r3, [r7, #15] +} + 8002b04: 4618 mov r0, r3 + 8002b06: 3710 adds r7, #16 + 8002b08: 46bd mov sp, r7 + 8002b0a: bd80 pop {r7, pc} + +08002b0c : + uint8_t ep_type, + uint8_t token, + uint8_t *pbuff, + uint16_t length, + uint8_t do_ping) +{ + 8002b0c: b580 push {r7, lr} + 8002b0e: b082 sub sp, #8 + 8002b10: af00 add r7, sp, #0 + 8002b12: 6078 str r0, [r7, #4] + 8002b14: 4608 mov r0, r1 + 8002b16: 4611 mov r1, r2 + 8002b18: 461a mov r2, r3 + 8002b1a: 4603 mov r3, r0 + 8002b1c: 70fb strb r3, [r7, #3] + 8002b1e: 460b mov r3, r1 + 8002b20: 70bb strb r3, [r7, #2] + 8002b22: 4613 mov r3, r2 + 8002b24: 707b strb r3, [r7, #1] + hhcd->hc[ch_num].ep_is_in = direction; + 8002b26: 78fa ldrb r2, [r7, #3] + 8002b28: 6879 ldr r1, [r7, #4] + 8002b2a: 4613 mov r3, r2 + 8002b2c: 009b lsls r3, r3, #2 + 8002b2e: 4413 add r3, r2 + 8002b30: 00db lsls r3, r3, #3 + 8002b32: 440b add r3, r1 + 8002b34: 333b adds r3, #59 ; 0x3b + 8002b36: 78ba ldrb r2, [r7, #2] + 8002b38: 701a strb r2, [r3, #0] + hhcd->hc[ch_num].ep_type = ep_type; + 8002b3a: 78fa ldrb r2, [r7, #3] + 8002b3c: 6879 ldr r1, [r7, #4] + 8002b3e: 4613 mov r3, r2 + 8002b40: 009b lsls r3, r3, #2 + 8002b42: 4413 add r3, r2 + 8002b44: 00db lsls r3, r3, #3 + 8002b46: 440b add r3, r1 + 8002b48: 333f adds r3, #63 ; 0x3f + 8002b4a: 787a ldrb r2, [r7, #1] + 8002b4c: 701a strb r2, [r3, #0] + + if (token == 0U) + 8002b4e: 7c3b ldrb r3, [r7, #16] + 8002b50: 2b00 cmp r3, #0 + 8002b52: d114 bne.n 8002b7e + { + hhcd->hc[ch_num].data_pid = HC_PID_SETUP; + 8002b54: 78fa ldrb r2, [r7, #3] + 8002b56: 6879 ldr r1, [r7, #4] + 8002b58: 4613 mov r3, r2 + 8002b5a: 009b lsls r3, r3, #2 + 8002b5c: 4413 add r3, r2 + 8002b5e: 00db lsls r3, r3, #3 + 8002b60: 440b add r3, r1 + 8002b62: 3342 adds r3, #66 ; 0x42 + 8002b64: 2203 movs r2, #3 + 8002b66: 701a strb r2, [r3, #0] + hhcd->hc[ch_num].do_ping = do_ping; + 8002b68: 78fa ldrb r2, [r7, #3] + 8002b6a: 6879 ldr r1, [r7, #4] + 8002b6c: 4613 mov r3, r2 + 8002b6e: 009b lsls r3, r3, #2 + 8002b70: 4413 add r3, r2 + 8002b72: 00db lsls r3, r3, #3 + 8002b74: 440b add r3, r1 + 8002b76: 333d adds r3, #61 ; 0x3d + 8002b78: 7f3a ldrb r2, [r7, #28] + 8002b7a: 701a strb r2, [r3, #0] + 8002b7c: e009 b.n 8002b92 + } + else + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + 8002b7e: 78fa ldrb r2, [r7, #3] + 8002b80: 6879 ldr r1, [r7, #4] + 8002b82: 4613 mov r3, r2 + 8002b84: 009b lsls r3, r3, #2 + 8002b86: 4413 add r3, r2 + 8002b88: 00db lsls r3, r3, #3 + 8002b8a: 440b add r3, r1 + 8002b8c: 3342 adds r3, #66 ; 0x42 + 8002b8e: 2202 movs r2, #2 + 8002b90: 701a strb r2, [r3, #0] + } + + /* Manage Data Toggle */ + switch (ep_type) + 8002b92: 787b ldrb r3, [r7, #1] + 8002b94: 2b03 cmp r3, #3 + 8002b96: f200 80d6 bhi.w 8002d46 + 8002b9a: a201 add r2, pc, #4 ; (adr r2, 8002ba0 ) + 8002b9c: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8002ba0: 08002bb1 .word 0x08002bb1 + 8002ba4: 08002d31 .word 0x08002d31 + 8002ba8: 08002c1d .word 0x08002c1d + 8002bac: 08002ca7 .word 0x08002ca7 + { + case EP_TYPE_CTRL: + if ((token == 1U) && (direction == 0U)) /*send data */ + 8002bb0: 7c3b ldrb r3, [r7, #16] + 8002bb2: 2b01 cmp r3, #1 + 8002bb4: f040 80c9 bne.w 8002d4a + 8002bb8: 78bb ldrb r3, [r7, #2] + 8002bba: 2b00 cmp r3, #0 + 8002bbc: f040 80c5 bne.w 8002d4a + { + if (length == 0U) + 8002bc0: 8b3b ldrh r3, [r7, #24] + 8002bc2: 2b00 cmp r3, #0 + 8002bc4: d109 bne.n 8002bda + { + /* For Status OUT stage, Length==0, Status Out PID = 1 */ + hhcd->hc[ch_num].toggle_out = 1U; + 8002bc6: 78fa ldrb r2, [r7, #3] + 8002bc8: 6879 ldr r1, [r7, #4] + 8002bca: 4613 mov r3, r2 + 8002bcc: 009b lsls r3, r3, #2 + 8002bce: 4413 add r3, r2 + 8002bd0: 00db lsls r3, r3, #3 + 8002bd2: 440b add r3, r1 + 8002bd4: 3351 adds r3, #81 ; 0x51 + 8002bd6: 2201 movs r2, #1 + 8002bd8: 701a strb r2, [r3, #0] + } + + /* Set the Data Toggle bit as per the Flag */ + if (hhcd->hc[ch_num].toggle_out == 0U) + 8002bda: 78fa ldrb r2, [r7, #3] + 8002bdc: 6879 ldr r1, [r7, #4] + 8002bde: 4613 mov r3, r2 + 8002be0: 009b lsls r3, r3, #2 + 8002be2: 4413 add r3, r2 + 8002be4: 00db lsls r3, r3, #3 + 8002be6: 440b add r3, r1 + 8002be8: 3351 adds r3, #81 ; 0x51 + 8002bea: 781b ldrb r3, [r3, #0] + 8002bec: 2b00 cmp r3, #0 + 8002bee: d10a bne.n 8002c06 + { + /* Put the PID 0 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + 8002bf0: 78fa ldrb r2, [r7, #3] + 8002bf2: 6879 ldr r1, [r7, #4] + 8002bf4: 4613 mov r3, r2 + 8002bf6: 009b lsls r3, r3, #2 + 8002bf8: 4413 add r3, r2 + 8002bfa: 00db lsls r3, r3, #3 + 8002bfc: 440b add r3, r1 + 8002bfe: 3342 adds r3, #66 ; 0x42 + 8002c00: 2200 movs r2, #0 + 8002c02: 701a strb r2, [r3, #0] + { + /* Put the PID 1 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + } + break; + 8002c04: e0a1 b.n 8002d4a + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + 8002c06: 78fa ldrb r2, [r7, #3] + 8002c08: 6879 ldr r1, [r7, #4] + 8002c0a: 4613 mov r3, r2 + 8002c0c: 009b lsls r3, r3, #2 + 8002c0e: 4413 add r3, r2 + 8002c10: 00db lsls r3, r3, #3 + 8002c12: 440b add r3, r1 + 8002c14: 3342 adds r3, #66 ; 0x42 + 8002c16: 2202 movs r2, #2 + 8002c18: 701a strb r2, [r3, #0] + break; + 8002c1a: e096 b.n 8002d4a + + case EP_TYPE_BULK: + if (direction == 0U) + 8002c1c: 78bb ldrb r3, [r7, #2] + 8002c1e: 2b00 cmp r3, #0 + 8002c20: d120 bne.n 8002c64 + { + /* Set the Data Toggle bit as per the Flag */ + if (hhcd->hc[ch_num].toggle_out == 0U) + 8002c22: 78fa ldrb r2, [r7, #3] + 8002c24: 6879 ldr r1, [r7, #4] + 8002c26: 4613 mov r3, r2 + 8002c28: 009b lsls r3, r3, #2 + 8002c2a: 4413 add r3, r2 + 8002c2c: 00db lsls r3, r3, #3 + 8002c2e: 440b add r3, r1 + 8002c30: 3351 adds r3, #81 ; 0x51 + 8002c32: 781b ldrb r3, [r3, #0] + 8002c34: 2b00 cmp r3, #0 + 8002c36: d10a bne.n 8002c4e + { + /* Put the PID 0 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + 8002c38: 78fa ldrb r2, [r7, #3] + 8002c3a: 6879 ldr r1, [r7, #4] + 8002c3c: 4613 mov r3, r2 + 8002c3e: 009b lsls r3, r3, #2 + 8002c40: 4413 add r3, r2 + 8002c42: 00db lsls r3, r3, #3 + 8002c44: 440b add r3, r1 + 8002c46: 3342 adds r3, #66 ; 0x42 + 8002c48: 2200 movs r2, #0 + 8002c4a: 701a strb r2, [r3, #0] + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + } + + break; + 8002c4c: e07e b.n 8002d4c + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + 8002c4e: 78fa ldrb r2, [r7, #3] + 8002c50: 6879 ldr r1, [r7, #4] + 8002c52: 4613 mov r3, r2 + 8002c54: 009b lsls r3, r3, #2 + 8002c56: 4413 add r3, r2 + 8002c58: 00db lsls r3, r3, #3 + 8002c5a: 440b add r3, r1 + 8002c5c: 3342 adds r3, #66 ; 0x42 + 8002c5e: 2202 movs r2, #2 + 8002c60: 701a strb r2, [r3, #0] + break; + 8002c62: e073 b.n 8002d4c + if (hhcd->hc[ch_num].toggle_in == 0U) + 8002c64: 78fa ldrb r2, [r7, #3] + 8002c66: 6879 ldr r1, [r7, #4] + 8002c68: 4613 mov r3, r2 + 8002c6a: 009b lsls r3, r3, #2 + 8002c6c: 4413 add r3, r2 + 8002c6e: 00db lsls r3, r3, #3 + 8002c70: 440b add r3, r1 + 8002c72: 3350 adds r3, #80 ; 0x50 + 8002c74: 781b ldrb r3, [r3, #0] + 8002c76: 2b00 cmp r3, #0 + 8002c78: d10a bne.n 8002c90 + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + 8002c7a: 78fa ldrb r2, [r7, #3] + 8002c7c: 6879 ldr r1, [r7, #4] + 8002c7e: 4613 mov r3, r2 + 8002c80: 009b lsls r3, r3, #2 + 8002c82: 4413 add r3, r2 + 8002c84: 00db lsls r3, r3, #3 + 8002c86: 440b add r3, r1 + 8002c88: 3342 adds r3, #66 ; 0x42 + 8002c8a: 2200 movs r2, #0 + 8002c8c: 701a strb r2, [r3, #0] + break; + 8002c8e: e05d b.n 8002d4c + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + 8002c90: 78fa ldrb r2, [r7, #3] + 8002c92: 6879 ldr r1, [r7, #4] + 8002c94: 4613 mov r3, r2 + 8002c96: 009b lsls r3, r3, #2 + 8002c98: 4413 add r3, r2 + 8002c9a: 00db lsls r3, r3, #3 + 8002c9c: 440b add r3, r1 + 8002c9e: 3342 adds r3, #66 ; 0x42 + 8002ca0: 2202 movs r2, #2 + 8002ca2: 701a strb r2, [r3, #0] + break; + 8002ca4: e052 b.n 8002d4c + case EP_TYPE_INTR: + if (direction == 0U) + 8002ca6: 78bb ldrb r3, [r7, #2] + 8002ca8: 2b00 cmp r3, #0 + 8002caa: d120 bne.n 8002cee + { + /* Set the Data Toggle bit as per the Flag */ + if (hhcd->hc[ch_num].toggle_out == 0U) + 8002cac: 78fa ldrb r2, [r7, #3] + 8002cae: 6879 ldr r1, [r7, #4] + 8002cb0: 4613 mov r3, r2 + 8002cb2: 009b lsls r3, r3, #2 + 8002cb4: 4413 add r3, r2 + 8002cb6: 00db lsls r3, r3, #3 + 8002cb8: 440b add r3, r1 + 8002cba: 3351 adds r3, #81 ; 0x51 + 8002cbc: 781b ldrb r3, [r3, #0] + 8002cbe: 2b00 cmp r3, #0 + 8002cc0: d10a bne.n 8002cd8 + { + /* Put the PID 0 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + 8002cc2: 78fa ldrb r2, [r7, #3] + 8002cc4: 6879 ldr r1, [r7, #4] + 8002cc6: 4613 mov r3, r2 + 8002cc8: 009b lsls r3, r3, #2 + 8002cca: 4413 add r3, r2 + 8002ccc: 00db lsls r3, r3, #3 + 8002cce: 440b add r3, r1 + 8002cd0: 3342 adds r3, #66 ; 0x42 + 8002cd2: 2200 movs r2, #0 + 8002cd4: 701a strb r2, [r3, #0] + else + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + } + break; + 8002cd6: e039 b.n 8002d4c + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + 8002cd8: 78fa ldrb r2, [r7, #3] + 8002cda: 6879 ldr r1, [r7, #4] + 8002cdc: 4613 mov r3, r2 + 8002cde: 009b lsls r3, r3, #2 + 8002ce0: 4413 add r3, r2 + 8002ce2: 00db lsls r3, r3, #3 + 8002ce4: 440b add r3, r1 + 8002ce6: 3342 adds r3, #66 ; 0x42 + 8002ce8: 2202 movs r2, #2 + 8002cea: 701a strb r2, [r3, #0] + break; + 8002cec: e02e b.n 8002d4c + if (hhcd->hc[ch_num].toggle_in == 0U) + 8002cee: 78fa ldrb r2, [r7, #3] + 8002cf0: 6879 ldr r1, [r7, #4] + 8002cf2: 4613 mov r3, r2 + 8002cf4: 009b lsls r3, r3, #2 + 8002cf6: 4413 add r3, r2 + 8002cf8: 00db lsls r3, r3, #3 + 8002cfa: 440b add r3, r1 + 8002cfc: 3350 adds r3, #80 ; 0x50 + 8002cfe: 781b ldrb r3, [r3, #0] + 8002d00: 2b00 cmp r3, #0 + 8002d02: d10a bne.n 8002d1a + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + 8002d04: 78fa ldrb r2, [r7, #3] + 8002d06: 6879 ldr r1, [r7, #4] + 8002d08: 4613 mov r3, r2 + 8002d0a: 009b lsls r3, r3, #2 + 8002d0c: 4413 add r3, r2 + 8002d0e: 00db lsls r3, r3, #3 + 8002d10: 440b add r3, r1 + 8002d12: 3342 adds r3, #66 ; 0x42 + 8002d14: 2200 movs r2, #0 + 8002d16: 701a strb r2, [r3, #0] + break; + 8002d18: e018 b.n 8002d4c + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + 8002d1a: 78fa ldrb r2, [r7, #3] + 8002d1c: 6879 ldr r1, [r7, #4] + 8002d1e: 4613 mov r3, r2 + 8002d20: 009b lsls r3, r3, #2 + 8002d22: 4413 add r3, r2 + 8002d24: 00db lsls r3, r3, #3 + 8002d26: 440b add r3, r1 + 8002d28: 3342 adds r3, #66 ; 0x42 + 8002d2a: 2202 movs r2, #2 + 8002d2c: 701a strb r2, [r3, #0] + break; + 8002d2e: e00d b.n 8002d4c + + case EP_TYPE_ISOC: + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + 8002d30: 78fa ldrb r2, [r7, #3] + 8002d32: 6879 ldr r1, [r7, #4] + 8002d34: 4613 mov r3, r2 + 8002d36: 009b lsls r3, r3, #2 + 8002d38: 4413 add r3, r2 + 8002d3a: 00db lsls r3, r3, #3 + 8002d3c: 440b add r3, r1 + 8002d3e: 3342 adds r3, #66 ; 0x42 + 8002d40: 2200 movs r2, #0 + 8002d42: 701a strb r2, [r3, #0] + break; + 8002d44: e002 b.n 8002d4c + + default: + break; + 8002d46: bf00 nop + 8002d48: e000 b.n 8002d4c + break; + 8002d4a: bf00 nop + } + + hhcd->hc[ch_num].xfer_buff = pbuff; + 8002d4c: 78fa ldrb r2, [r7, #3] + 8002d4e: 6879 ldr r1, [r7, #4] + 8002d50: 4613 mov r3, r2 + 8002d52: 009b lsls r3, r3, #2 + 8002d54: 4413 add r3, r2 + 8002d56: 00db lsls r3, r3, #3 + 8002d58: 440b add r3, r1 + 8002d5a: 3344 adds r3, #68 ; 0x44 + 8002d5c: 697a ldr r2, [r7, #20] + 8002d5e: 601a str r2, [r3, #0] + hhcd->hc[ch_num].xfer_len = length; + 8002d60: 78fa ldrb r2, [r7, #3] + 8002d62: 8b39 ldrh r1, [r7, #24] + 8002d64: 6878 ldr r0, [r7, #4] + 8002d66: 4613 mov r3, r2 + 8002d68: 009b lsls r3, r3, #2 + 8002d6a: 4413 add r3, r2 + 8002d6c: 00db lsls r3, r3, #3 + 8002d6e: 4403 add r3, r0 + 8002d70: 3348 adds r3, #72 ; 0x48 + 8002d72: 6019 str r1, [r3, #0] + hhcd->hc[ch_num].urb_state = URB_IDLE; + 8002d74: 78fa ldrb r2, [r7, #3] + 8002d76: 6879 ldr r1, [r7, #4] + 8002d78: 4613 mov r3, r2 + 8002d7a: 009b lsls r3, r3, #2 + 8002d7c: 4413 add r3, r2 + 8002d7e: 00db lsls r3, r3, #3 + 8002d80: 440b add r3, r1 + 8002d82: 335c adds r3, #92 ; 0x5c + 8002d84: 2200 movs r2, #0 + 8002d86: 701a strb r2, [r3, #0] + hhcd->hc[ch_num].xfer_count = 0U; + 8002d88: 78fa ldrb r2, [r7, #3] + 8002d8a: 6879 ldr r1, [r7, #4] + 8002d8c: 4613 mov r3, r2 + 8002d8e: 009b lsls r3, r3, #2 + 8002d90: 4413 add r3, r2 + 8002d92: 00db lsls r3, r3, #3 + 8002d94: 440b add r3, r1 + 8002d96: 334c adds r3, #76 ; 0x4c + 8002d98: 2200 movs r2, #0 + 8002d9a: 601a str r2, [r3, #0] + hhcd->hc[ch_num].ch_num = ch_num; + 8002d9c: 78fa ldrb r2, [r7, #3] + 8002d9e: 6879 ldr r1, [r7, #4] + 8002da0: 4613 mov r3, r2 + 8002da2: 009b lsls r3, r3, #2 + 8002da4: 4413 add r3, r2 + 8002da6: 00db lsls r3, r3, #3 + 8002da8: 440b add r3, r1 + 8002daa: 3339 adds r3, #57 ; 0x39 + 8002dac: 78fa ldrb r2, [r7, #3] + 8002dae: 701a strb r2, [r3, #0] + hhcd->hc[ch_num].state = HC_IDLE; + 8002db0: 78fa ldrb r2, [r7, #3] + 8002db2: 6879 ldr r1, [r7, #4] + 8002db4: 4613 mov r3, r2 + 8002db6: 009b lsls r3, r3, #2 + 8002db8: 4413 add r3, r2 + 8002dba: 00db lsls r3, r3, #3 + 8002dbc: 440b add r3, r1 + 8002dbe: 335d adds r3, #93 ; 0x5d + 8002dc0: 2200 movs r2, #0 + 8002dc2: 701a strb r2, [r3, #0] + + return USB_HC_StartXfer(hhcd->Instance, &hhcd->hc[ch_num], (uint8_t)hhcd->Init.dma_enable); + 8002dc4: 687b ldr r3, [r7, #4] + 8002dc6: 6818 ldr r0, [r3, #0] + 8002dc8: 78fa ldrb r2, [r7, #3] + 8002dca: 4613 mov r3, r2 + 8002dcc: 009b lsls r3, r3, #2 + 8002dce: 4413 add r3, r2 + 8002dd0: 00db lsls r3, r3, #3 + 8002dd2: 3338 adds r3, #56 ; 0x38 + 8002dd4: 687a ldr r2, [r7, #4] + 8002dd6: 18d1 adds r1, r2, r3 + 8002dd8: 687b ldr r3, [r7, #4] + 8002dda: 691b ldr r3, [r3, #16] + 8002ddc: b2db uxtb r3, r3 + 8002dde: 461a mov r2, r3 + 8002de0: f004 fd84 bl 80078ec + 8002de4: 4603 mov r3, r0 +} + 8002de6: 4618 mov r0, r3 + 8002de8: 3708 adds r7, #8 + 8002dea: 46bd mov sp, r7 + 8002dec: bd80 pop {r7, pc} + 8002dee: bf00 nop + +08002df0 : + * @brief Handle HCD interrupt request. + * @param hhcd HCD handle + * @retval None + */ +void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) +{ + 8002df0: b580 push {r7, lr} + 8002df2: b086 sub sp, #24 + 8002df4: af00 add r7, sp, #0 + 8002df6: 6078 str r0, [r7, #4] + USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + 8002df8: 687b ldr r3, [r7, #4] + 8002dfa: 681b ldr r3, [r3, #0] + 8002dfc: 613b str r3, [r7, #16] + uint32_t USBx_BASE = (uint32_t)USBx; + 8002dfe: 693b ldr r3, [r7, #16] + 8002e00: 60fb str r3, [r7, #12] + uint32_t i, interrupt; + + /* Ensure that we are in device mode */ + if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST) + 8002e02: 687b ldr r3, [r7, #4] + 8002e04: 681b ldr r3, [r3, #0] + 8002e06: 4618 mov r0, r3 + 8002e08: f004 faa1 bl 800734e + 8002e0c: 4603 mov r3, r0 + 8002e0e: 2b01 cmp r3, #1 + 8002e10: f040 80ef bne.w 8002ff2 + { + /* Avoid spurious interrupt */ + if (__HAL_HCD_IS_INVALID_INTERRUPT(hhcd)) + 8002e14: 687b ldr r3, [r7, #4] + 8002e16: 681b ldr r3, [r3, #0] + 8002e18: 4618 mov r0, r3 + 8002e1a: f004 fa85 bl 8007328 + 8002e1e: 4603 mov r3, r0 + 8002e20: 2b00 cmp r3, #0 + 8002e22: f000 80e5 beq.w 8002ff0 + { + return; + } + + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) + 8002e26: 687b ldr r3, [r7, #4] + 8002e28: 681b ldr r3, [r3, #0] + 8002e2a: 4618 mov r0, r3 + 8002e2c: f004 fa7c bl 8007328 + 8002e30: 4603 mov r3, r0 + 8002e32: f403 1300 and.w r3, r3, #2097152 ; 0x200000 + 8002e36: f5b3 1f00 cmp.w r3, #2097152 ; 0x200000 + 8002e3a: d104 bne.n 8002e46 + { + /* Incorrect mode, acknowledge the interrupt */ + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); + 8002e3c: 687b ldr r3, [r7, #4] + 8002e3e: 681b ldr r3, [r3, #0] + 8002e40: f44f 1200 mov.w r2, #2097152 ; 0x200000 + 8002e44: 615a str r2, [r3, #20] + } + + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR)) + 8002e46: 687b ldr r3, [r7, #4] + 8002e48: 681b ldr r3, [r3, #0] + 8002e4a: 4618 mov r0, r3 + 8002e4c: f004 fa6c bl 8007328 + 8002e50: 4603 mov r3, r0 + 8002e52: f403 1380 and.w r3, r3, #1048576 ; 0x100000 + 8002e56: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 + 8002e5a: d104 bne.n 8002e66 + { + /* Incorrect mode, acknowledge the interrupt */ + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR); + 8002e5c: 687b ldr r3, [r7, #4] + 8002e5e: 681b ldr r3, [r3, #0] + 8002e60: f44f 1280 mov.w r2, #1048576 ; 0x100000 + 8002e64: 615a str r2, [r3, #20] + } + + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE)) + 8002e66: 687b ldr r3, [r7, #4] + 8002e68: 681b ldr r3, [r3, #0] + 8002e6a: 4618 mov r0, r3 + 8002e6c: f004 fa5c bl 8007328 + 8002e70: 4603 mov r3, r0 + 8002e72: f003 6380 and.w r3, r3, #67108864 ; 0x4000000 + 8002e76: f1b3 6f80 cmp.w r3, #67108864 ; 0x4000000 + 8002e7a: d104 bne.n 8002e86 + { + /* Incorrect mode, acknowledge the interrupt */ + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE); + 8002e7c: 687b ldr r3, [r7, #4] + 8002e7e: 681b ldr r3, [r3, #0] + 8002e80: f04f 6280 mov.w r2, #67108864 ; 0x4000000 + 8002e84: 615a str r2, [r3, #20] + } + + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS)) + 8002e86: 687b ldr r3, [r7, #4] + 8002e88: 681b ldr r3, [r3, #0] + 8002e8a: 4618 mov r0, r3 + 8002e8c: f004 fa4c bl 8007328 + 8002e90: 4603 mov r3, r0 + 8002e92: f003 0302 and.w r3, r3, #2 + 8002e96: 2b02 cmp r3, #2 + 8002e98: d103 bne.n 8002ea2 + { + /* Incorrect mode, acknowledge the interrupt */ + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_MMIS); + 8002e9a: 687b ldr r3, [r7, #4] + 8002e9c: 681b ldr r3, [r3, #0] + 8002e9e: 2202 movs r2, #2 + 8002ea0: 615a str r2, [r3, #20] + } + + /* Handle Host Disconnect Interrupts */ + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT)) + 8002ea2: 687b ldr r3, [r7, #4] + 8002ea4: 681b ldr r3, [r3, #0] + 8002ea6: 4618 mov r0, r3 + 8002ea8: f004 fa3e bl 8007328 + 8002eac: 4603 mov r3, r0 + 8002eae: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 + 8002eb2: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 + 8002eb6: d115 bne.n 8002ee4 + { + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT); + 8002eb8: 687b ldr r3, [r7, #4] + 8002eba: 681b ldr r3, [r3, #0] + 8002ebc: f04f 5200 mov.w r2, #536870912 ; 0x20000000 + 8002ec0: 615a str r2, [r3, #20] + + if ((USBx_HPRT0 & USB_OTG_HPRT_PCSTS) == 0U) + 8002ec2: 68fb ldr r3, [r7, #12] + 8002ec4: f503 6388 add.w r3, r3, #1088 ; 0x440 + 8002ec8: 681b ldr r3, [r3, #0] + 8002eca: f003 0301 and.w r3, r3, #1 + 8002ece: 2b00 cmp r3, #0 + 8002ed0: d108 bne.n 8002ee4 + { + /* Handle Host Port Disconnect Interrupt */ +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->DisconnectCallback(hhcd); +#else + HAL_HCD_Disconnect_Callback(hhcd); + 8002ed2: 6878 ldr r0, [r7, #4] + 8002ed4: f006 fff6 bl 8009ec4 +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + + (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ); + 8002ed8: 687b ldr r3, [r7, #4] + 8002eda: 681b ldr r3, [r3, #0] + 8002edc: 2101 movs r1, #1 + 8002ede: 4618 mov r0, r3 + 8002ee0: f004 fb34 bl 800754c + } + } + + /* Handle Host Port Interrupts */ + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HPRTINT)) + 8002ee4: 687b ldr r3, [r7, #4] + 8002ee6: 681b ldr r3, [r3, #0] + 8002ee8: 4618 mov r0, r3 + 8002eea: f004 fa1d bl 8007328 + 8002eee: 4603 mov r3, r0 + 8002ef0: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 + 8002ef4: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 + 8002ef8: d102 bne.n 8002f00 + { + HCD_Port_IRQHandler(hhcd); + 8002efa: 6878 ldr r0, [r7, #4] + 8002efc: f001 f966 bl 80041cc + } + + /* Handle Host SOF Interrupt */ + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_SOF)) + 8002f00: 687b ldr r3, [r7, #4] + 8002f02: 681b ldr r3, [r3, #0] + 8002f04: 4618 mov r0, r3 + 8002f06: f004 fa0f bl 8007328 + 8002f0a: 4603 mov r3, r0 + 8002f0c: f003 0308 and.w r3, r3, #8 + 8002f10: 2b08 cmp r3, #8 + 8002f12: d106 bne.n 8002f22 + { +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->SOFCallback(hhcd); +#else + HAL_HCD_SOF_Callback(hhcd); + 8002f14: 6878 ldr r0, [r7, #4] + 8002f16: f006 ffb9 bl 8009e8c +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF); + 8002f1a: 687b ldr r3, [r7, #4] + 8002f1c: 681b ldr r3, [r3, #0] + 8002f1e: 2208 movs r2, #8 + 8002f20: 615a str r2, [r3, #20] + } + + /* Handle Host channel Interrupt */ + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT)) + 8002f22: 687b ldr r3, [r7, #4] + 8002f24: 681b ldr r3, [r3, #0] + 8002f26: 4618 mov r0, r3 + 8002f28: f004 f9fe bl 8007328 + 8002f2c: 4603 mov r3, r0 + 8002f2e: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 8002f32: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000 + 8002f36: d138 bne.n 8002faa + { + interrupt = USB_HC_ReadInterrupt(hhcd->Instance); + 8002f38: 687b ldr r3, [r7, #4] + 8002f3a: 681b ldr r3, [r3, #0] + 8002f3c: 4618 mov r0, r3 + 8002f3e: f004 fe1b bl 8007b78 + 8002f42: 60b8 str r0, [r7, #8] + for (i = 0U; i < hhcd->Init.Host_channels; i++) + 8002f44: 2300 movs r3, #0 + 8002f46: 617b str r3, [r7, #20] + 8002f48: e025 b.n 8002f96 + { + if ((interrupt & (1UL << (i & 0xFU))) != 0U) + 8002f4a: 697b ldr r3, [r7, #20] + 8002f4c: f003 030f and.w r3, r3, #15 + 8002f50: 68ba ldr r2, [r7, #8] + 8002f52: fa22 f303 lsr.w r3, r2, r3 + 8002f56: f003 0301 and.w r3, r3, #1 + 8002f5a: 2b00 cmp r3, #0 + 8002f5c: d018 beq.n 8002f90 + { + if ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_EPDIR) == USB_OTG_HCCHAR_EPDIR) + 8002f5e: 697b ldr r3, [r7, #20] + 8002f60: 015a lsls r2, r3, #5 + 8002f62: 68fb ldr r3, [r7, #12] + 8002f64: 4413 add r3, r2 + 8002f66: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8002f6a: 681b ldr r3, [r3, #0] + 8002f6c: f403 4300 and.w r3, r3, #32768 ; 0x8000 + 8002f70: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 + 8002f74: d106 bne.n 8002f84 + { + HCD_HC_IN_IRQHandler(hhcd, (uint8_t)i); + 8002f76: 697b ldr r3, [r7, #20] + 8002f78: b2db uxtb r3, r3 + 8002f7a: 4619 mov r1, r3 + 8002f7c: 6878 ldr r0, [r7, #4] + 8002f7e: f000 f8cf bl 8003120 + 8002f82: e005 b.n 8002f90 + } + else + { + HCD_HC_OUT_IRQHandler(hhcd, (uint8_t)i); + 8002f84: 697b ldr r3, [r7, #20] + 8002f86: b2db uxtb r3, r3 + 8002f88: 4619 mov r1, r3 + 8002f8a: 6878 ldr r0, [r7, #4] + 8002f8c: f000 fcfd bl 800398a + for (i = 0U; i < hhcd->Init.Host_channels; i++) + 8002f90: 697b ldr r3, [r7, #20] + 8002f92: 3301 adds r3, #1 + 8002f94: 617b str r3, [r7, #20] + 8002f96: 687b ldr r3, [r7, #4] + 8002f98: 689b ldr r3, [r3, #8] + 8002f9a: 697a ldr r2, [r7, #20] + 8002f9c: 429a cmp r2, r3 + 8002f9e: d3d4 bcc.n 8002f4a + } + } + } + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT); + 8002fa0: 687b ldr r3, [r7, #4] + 8002fa2: 681b ldr r3, [r3, #0] + 8002fa4: f04f 7200 mov.w r2, #33554432 ; 0x2000000 + 8002fa8: 615a str r2, [r3, #20] + } + + /* Handle Rx Queue Level Interrupts */ + if ((__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) != 0U) + 8002faa: 687b ldr r3, [r7, #4] + 8002fac: 681b ldr r3, [r3, #0] + 8002fae: 4618 mov r0, r3 + 8002fb0: f004 f9ba bl 8007328 + 8002fb4: 4603 mov r3, r0 + 8002fb6: f003 0310 and.w r3, r3, #16 + 8002fba: 2b10 cmp r3, #16 + 8002fbc: d101 bne.n 8002fc2 + 8002fbe: 2301 movs r3, #1 + 8002fc0: e000 b.n 8002fc4 + 8002fc2: 2300 movs r3, #0 + 8002fc4: 2b00 cmp r3, #0 + 8002fc6: d014 beq.n 8002ff2 + { + USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); + 8002fc8: 687b ldr r3, [r7, #4] + 8002fca: 681b ldr r3, [r3, #0] + 8002fcc: 699a ldr r2, [r3, #24] + 8002fce: 687b ldr r3, [r7, #4] + 8002fd0: 681b ldr r3, [r3, #0] + 8002fd2: f022 0210 bic.w r2, r2, #16 + 8002fd6: 619a str r2, [r3, #24] + + HCD_RXQLVL_IRQHandler(hhcd); + 8002fd8: 6878 ldr r0, [r7, #4] + 8002fda: f001 f84b bl 8004074 + + USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); + 8002fde: 687b ldr r3, [r7, #4] + 8002fe0: 681b ldr r3, [r3, #0] + 8002fe2: 699a ldr r2, [r3, #24] + 8002fe4: 687b ldr r3, [r7, #4] + 8002fe6: 681b ldr r3, [r3, #0] + 8002fe8: f042 0210 orr.w r2, r2, #16 + 8002fec: 619a str r2, [r3, #24] + 8002fee: e000 b.n 8002ff2 + return; + 8002ff0: bf00 nop + } + } +} + 8002ff2: 3718 adds r7, #24 + 8002ff4: 46bd mov sp, r7 + 8002ff6: bd80 pop {r7, pc} + +08002ff8 : + * @brief Start the host driver. + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd) +{ + 8002ff8: b580 push {r7, lr} + 8002ffa: b082 sub sp, #8 + 8002ffc: af00 add r7, sp, #0 + 8002ffe: 6078 str r0, [r7, #4] + __HAL_LOCK(hhcd); + 8003000: 687b ldr r3, [r7, #4] + 8003002: f893 32b8 ldrb.w r3, [r3, #696] ; 0x2b8 + 8003006: 2b01 cmp r3, #1 + 8003008: d101 bne.n 800300e + 800300a: 2302 movs r3, #2 + 800300c: e013 b.n 8003036 + 800300e: 687b ldr r3, [r7, #4] + 8003010: 2201 movs r2, #1 + 8003012: f883 22b8 strb.w r2, [r3, #696] ; 0x2b8 + __HAL_HCD_ENABLE(hhcd); + 8003016: 687b ldr r3, [r7, #4] + 8003018: 681b ldr r3, [r3, #0] + 800301a: 4618 mov r0, r3 + 800301c: f004 f891 bl 8007142 + (void)USB_DriveVbus(hhcd->Instance, 1U); + 8003020: 687b ldr r3, [r7, #4] + 8003022: 681b ldr r3, [r3, #0] + 8003024: 2101 movs r1, #1 + 8003026: 4618 mov r0, r3 + 8003028: f004 faf4 bl 8007614 + __HAL_UNLOCK(hhcd); + 800302c: 687b ldr r3, [r7, #4] + 800302e: 2200 movs r2, #0 + 8003030: f883 22b8 strb.w r2, [r3, #696] ; 0x2b8 + + return HAL_OK; + 8003034: 2300 movs r3, #0 +} + 8003036: 4618 mov r0, r3 + 8003038: 3708 adds r7, #8 + 800303a: 46bd mov sp, r7 + 800303c: bd80 pop {r7, pc} + +0800303e : + * @param hhcd HCD handle + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd) +{ + 800303e: b580 push {r7, lr} + 8003040: b082 sub sp, #8 + 8003042: af00 add r7, sp, #0 + 8003044: 6078 str r0, [r7, #4] + __HAL_LOCK(hhcd); + 8003046: 687b ldr r3, [r7, #4] + 8003048: f893 32b8 ldrb.w r3, [r3, #696] ; 0x2b8 + 800304c: 2b01 cmp r3, #1 + 800304e: d101 bne.n 8003054 + 8003050: 2302 movs r3, #2 + 8003052: e00d b.n 8003070 + 8003054: 687b ldr r3, [r7, #4] + 8003056: 2201 movs r2, #1 + 8003058: f883 22b8 strb.w r2, [r3, #696] ; 0x2b8 + (void)USB_StopHost(hhcd->Instance); + 800305c: 687b ldr r3, [r7, #4] + 800305e: 681b ldr r3, [r3, #0] + 8003060: 4618 mov r0, r3 + 8003062: f004 fed5 bl 8007e10 + __HAL_UNLOCK(hhcd); + 8003066: 687b ldr r3, [r7, #4] + 8003068: 2200 movs r2, #0 + 800306a: f883 22b8 strb.w r2, [r3, #696] ; 0x2b8 + + return HAL_OK; + 800306e: 2300 movs r3, #0 +} + 8003070: 4618 mov r0, r3 + 8003072: 3708 adds r7, #8 + 8003074: 46bd mov sp, r7 + 8003076: bd80 pop {r7, pc} + +08003078 : + * @brief Reset the host port. + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd) +{ + 8003078: b580 push {r7, lr} + 800307a: b082 sub sp, #8 + 800307c: af00 add r7, sp, #0 + 800307e: 6078 str r0, [r7, #4] + return (USB_ResetPort(hhcd->Instance)); + 8003080: 687b ldr r3, [r7, #4] + 8003082: 681b ldr r3, [r3, #0] + 8003084: 4618 mov r0, r3 + 8003086: f004 fa9b bl 80075c0 + 800308a: 4603 mov r3, r0 +} + 800308c: 4618 mov r0, r3 + 800308e: 3708 adds r7, #8 + 8003090: 46bd mov sp, r7 + 8003092: bd80 pop {r7, pc} + +08003094 : + * URB_NYET/ + * URB_ERROR/ + * URB_STALL + */ +HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum) +{ + 8003094: b480 push {r7} + 8003096: b083 sub sp, #12 + 8003098: af00 add r7, sp, #0 + 800309a: 6078 str r0, [r7, #4] + 800309c: 460b mov r3, r1 + 800309e: 70fb strb r3, [r7, #3] + return hhcd->hc[chnum].urb_state; + 80030a0: 78fa ldrb r2, [r7, #3] + 80030a2: 6879 ldr r1, [r7, #4] + 80030a4: 4613 mov r3, r2 + 80030a6: 009b lsls r3, r3, #2 + 80030a8: 4413 add r3, r2 + 80030aa: 00db lsls r3, r3, #3 + 80030ac: 440b add r3, r1 + 80030ae: 335c adds r3, #92 ; 0x5c + 80030b0: 781b ldrb r3, [r3, #0] +} + 80030b2: 4618 mov r0, r3 + 80030b4: 370c adds r7, #12 + 80030b6: 46bd mov sp, r7 + 80030b8: f85d 7b04 ldr.w r7, [sp], #4 + 80030bc: 4770 bx lr + +080030be : + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @retval last transfer size in byte + */ +uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum) +{ + 80030be: b480 push {r7} + 80030c0: b083 sub sp, #12 + 80030c2: af00 add r7, sp, #0 + 80030c4: 6078 str r0, [r7, #4] + 80030c6: 460b mov r3, r1 + 80030c8: 70fb strb r3, [r7, #3] + return hhcd->hc[chnum].xfer_count; + 80030ca: 78fa ldrb r2, [r7, #3] + 80030cc: 6879 ldr r1, [r7, #4] + 80030ce: 4613 mov r3, r2 + 80030d0: 009b lsls r3, r3, #2 + 80030d2: 4413 add r3, r2 + 80030d4: 00db lsls r3, r3, #3 + 80030d6: 440b add r3, r1 + 80030d8: 334c adds r3, #76 ; 0x4c + 80030da: 681b ldr r3, [r3, #0] +} + 80030dc: 4618 mov r0, r3 + 80030de: 370c adds r7, #12 + 80030e0: 46bd mov sp, r7 + 80030e2: f85d 7b04 ldr.w r7, [sp], #4 + 80030e6: 4770 bx lr + +080030e8 : + * @brief Return the current Host frame number. + * @param hhcd HCD handle + * @retval Current Host frame number + */ +uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd) +{ + 80030e8: b580 push {r7, lr} + 80030ea: b082 sub sp, #8 + 80030ec: af00 add r7, sp, #0 + 80030ee: 6078 str r0, [r7, #4] + return (USB_GetCurrentFrame(hhcd->Instance)); + 80030f0: 687b ldr r3, [r7, #4] + 80030f2: 681b ldr r3, [r3, #0] + 80030f4: 4618 mov r0, r3 + 80030f6: f004 fadd bl 80076b4 + 80030fa: 4603 mov r3, r0 +} + 80030fc: 4618 mov r0, r3 + 80030fe: 3708 adds r7, #8 + 8003100: 46bd mov sp, r7 + 8003102: bd80 pop {r7, pc} + +08003104 : + * @brief Return the Host enumeration speed. + * @param hhcd HCD handle + * @retval Enumeration speed + */ +uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd) +{ + 8003104: b580 push {r7, lr} + 8003106: b082 sub sp, #8 + 8003108: af00 add r7, sp, #0 + 800310a: 6078 str r0, [r7, #4] + return (USB_GetHostSpeed(hhcd->Instance)); + 800310c: 687b ldr r3, [r7, #4] + 800310e: 681b ldr r3, [r3, #0] + 8003110: 4618 mov r0, r3 + 8003112: f004 fab8 bl 8007686 + 8003116: 4603 mov r3, r0 +} + 8003118: 4618 mov r0, r3 + 800311a: 3708 adds r7, #8 + 800311c: 46bd mov sp, r7 + 800311e: bd80 pop {r7, pc} + +08003120 : + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @retval none + */ +static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) +{ + 8003120: b580 push {r7, lr} + 8003122: b086 sub sp, #24 + 8003124: af00 add r7, sp, #0 + 8003126: 6078 str r0, [r7, #4] + 8003128: 460b mov r3, r1 + 800312a: 70fb strb r3, [r7, #3] + USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + 800312c: 687b ldr r3, [r7, #4] + 800312e: 681b ldr r3, [r3, #0] + 8003130: 617b str r3, [r7, #20] + uint32_t USBx_BASE = (uint32_t)USBx; + 8003132: 697b ldr r3, [r7, #20] + 8003134: 613b str r3, [r7, #16] + uint32_t ch_num = (uint32_t)chnum; + 8003136: 78fb ldrb r3, [r7, #3] + 8003138: 60fb str r3, [r7, #12] + + uint32_t tmpreg; + + if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR) + 800313a: 68fb ldr r3, [r7, #12] + 800313c: 015a lsls r2, r3, #5 + 800313e: 693b ldr r3, [r7, #16] + 8003140: 4413 add r3, r2 + 8003142: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8003146: 689b ldr r3, [r3, #8] + 8003148: f003 0304 and.w r3, r3, #4 + 800314c: 2b04 cmp r3, #4 + 800314e: d119 bne.n 8003184 + { + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR); + 8003150: 68fb ldr r3, [r7, #12] + 8003152: 015a lsls r2, r3, #5 + 8003154: 693b ldr r3, [r7, #16] + 8003156: 4413 add r3, r2 + 8003158: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 800315c: 461a mov r2, r3 + 800315e: 2304 movs r3, #4 + 8003160: 6093 str r3, [r2, #8] + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + 8003162: 68fb ldr r3, [r7, #12] + 8003164: 015a lsls r2, r3, #5 + 8003166: 693b ldr r3, [r7, #16] + 8003168: 4413 add r3, r2 + 800316a: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 800316e: 68db ldr r3, [r3, #12] + 8003170: 68fa ldr r2, [r7, #12] + 8003172: 0151 lsls r1, r2, #5 + 8003174: 693a ldr r2, [r7, #16] + 8003176: 440a add r2, r1 + 8003178: f502 62a0 add.w r2, r2, #1280 ; 0x500 + 800317c: f043 0302 orr.w r3, r3, #2 + 8003180: 60d3 str r3, [r2, #12] + 8003182: e0ce b.n 8003322 + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_BBERR) == USB_OTG_HCINT_BBERR) + 8003184: 68fb ldr r3, [r7, #12] + 8003186: 015a lsls r2, r3, #5 + 8003188: 693b ldr r3, [r7, #16] + 800318a: 4413 add r3, r2 + 800318c: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8003190: 689b ldr r3, [r3, #8] + 8003192: f403 7380 and.w r3, r3, #256 ; 0x100 + 8003196: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 800319a: d12c bne.n 80031f6 + { + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_BBERR); + 800319c: 68fb ldr r3, [r7, #12] + 800319e: 015a lsls r2, r3, #5 + 80031a0: 693b ldr r3, [r7, #16] + 80031a2: 4413 add r3, r2 + 80031a4: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 80031a8: 461a mov r2, r3 + 80031aa: f44f 7380 mov.w r3, #256 ; 0x100 + 80031ae: 6093 str r3, [r2, #8] + hhcd->hc[ch_num].state = HC_BBLERR; + 80031b0: 6879 ldr r1, [r7, #4] + 80031b2: 68fa ldr r2, [r7, #12] + 80031b4: 4613 mov r3, r2 + 80031b6: 009b lsls r3, r3, #2 + 80031b8: 4413 add r3, r2 + 80031ba: 00db lsls r3, r3, #3 + 80031bc: 440b add r3, r1 + 80031be: 335d adds r3, #93 ; 0x5d + 80031c0: 2207 movs r2, #7 + 80031c2: 701a strb r2, [r3, #0] + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + 80031c4: 68fb ldr r3, [r7, #12] + 80031c6: 015a lsls r2, r3, #5 + 80031c8: 693b ldr r3, [r7, #16] + 80031ca: 4413 add r3, r2 + 80031cc: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 80031d0: 68db ldr r3, [r3, #12] + 80031d2: 68fa ldr r2, [r7, #12] + 80031d4: 0151 lsls r1, r2, #5 + 80031d6: 693a ldr r2, [r7, #16] + 80031d8: 440a add r2, r1 + 80031da: f502 62a0 add.w r2, r2, #1280 ; 0x500 + 80031de: f043 0302 orr.w r3, r3, #2 + 80031e2: 60d3 str r3, [r2, #12] + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + 80031e4: 687b ldr r3, [r7, #4] + 80031e6: 681b ldr r3, [r3, #0] + 80031e8: 68fa ldr r2, [r7, #12] + 80031ea: b2d2 uxtb r2, r2 + 80031ec: 4611 mov r1, r2 + 80031ee: 4618 mov r0, r3 + 80031f0: f004 fcd3 bl 8007b9a + 80031f4: e095 b.n 8003322 + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK) + 80031f6: 68fb ldr r3, [r7, #12] + 80031f8: 015a lsls r2, r3, #5 + 80031fa: 693b ldr r3, [r7, #16] + 80031fc: 4413 add r3, r2 + 80031fe: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8003202: 689b ldr r3, [r3, #8] + 8003204: f003 0320 and.w r3, r3, #32 + 8003208: 2b20 cmp r3, #32 + 800320a: d109 bne.n 8003220 + { + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_ACK); + 800320c: 68fb ldr r3, [r7, #12] + 800320e: 015a lsls r2, r3, #5 + 8003210: 693b ldr r3, [r7, #16] + 8003212: 4413 add r3, r2 + 8003214: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8003218: 461a mov r2, r3 + 800321a: 2320 movs r3, #32 + 800321c: 6093 str r3, [r2, #8] + 800321e: e080 b.n 8003322 + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL) + 8003220: 68fb ldr r3, [r7, #12] + 8003222: 015a lsls r2, r3, #5 + 8003224: 693b ldr r3, [r7, #16] + 8003226: 4413 add r3, r2 + 8003228: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 800322c: 689b ldr r3, [r3, #8] + 800322e: f003 0308 and.w r3, r3, #8 + 8003232: 2b08 cmp r3, #8 + 8003234: d134 bne.n 80032a0 + { + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + 8003236: 68fb ldr r3, [r7, #12] + 8003238: 015a lsls r2, r3, #5 + 800323a: 693b ldr r3, [r7, #16] + 800323c: 4413 add r3, r2 + 800323e: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8003242: 68db ldr r3, [r3, #12] + 8003244: 68fa ldr r2, [r7, #12] + 8003246: 0151 lsls r1, r2, #5 + 8003248: 693a ldr r2, [r7, #16] + 800324a: 440a add r2, r1 + 800324c: f502 62a0 add.w r2, r2, #1280 ; 0x500 + 8003250: f043 0302 orr.w r3, r3, #2 + 8003254: 60d3 str r3, [r2, #12] + hhcd->hc[ch_num].state = HC_STALL; + 8003256: 6879 ldr r1, [r7, #4] + 8003258: 68fa ldr r2, [r7, #12] + 800325a: 4613 mov r3, r2 + 800325c: 009b lsls r3, r3, #2 + 800325e: 4413 add r3, r2 + 8003260: 00db lsls r3, r3, #3 + 8003262: 440b add r3, r1 + 8003264: 335d adds r3, #93 ; 0x5d + 8003266: 2205 movs r2, #5 + 8003268: 701a strb r2, [r3, #0] + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); + 800326a: 68fb ldr r3, [r7, #12] + 800326c: 015a lsls r2, r3, #5 + 800326e: 693b ldr r3, [r7, #16] + 8003270: 4413 add r3, r2 + 8003272: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8003276: 461a mov r2, r3 + 8003278: 2310 movs r3, #16 + 800327a: 6093 str r3, [r2, #8] + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL); + 800327c: 68fb ldr r3, [r7, #12] + 800327e: 015a lsls r2, r3, #5 + 8003280: 693b ldr r3, [r7, #16] + 8003282: 4413 add r3, r2 + 8003284: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8003288: 461a mov r2, r3 + 800328a: 2308 movs r3, #8 + 800328c: 6093 str r3, [r2, #8] + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + 800328e: 687b ldr r3, [r7, #4] + 8003290: 681b ldr r3, [r3, #0] + 8003292: 68fa ldr r2, [r7, #12] + 8003294: b2d2 uxtb r2, r2 + 8003296: 4611 mov r1, r2 + 8003298: 4618 mov r0, r3 + 800329a: f004 fc7e bl 8007b9a + 800329e: e040 b.n 8003322 + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR) + 80032a0: 68fb ldr r3, [r7, #12] + 80032a2: 015a lsls r2, r3, #5 + 80032a4: 693b ldr r3, [r7, #16] + 80032a6: 4413 add r3, r2 + 80032a8: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 80032ac: 689b ldr r3, [r3, #8] + 80032ae: f403 6380 and.w r3, r3, #1024 ; 0x400 + 80032b2: f5b3 6f80 cmp.w r3, #1024 ; 0x400 + 80032b6: d134 bne.n 8003322 + { + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + 80032b8: 68fb ldr r3, [r7, #12] + 80032ba: 015a lsls r2, r3, #5 + 80032bc: 693b ldr r3, [r7, #16] + 80032be: 4413 add r3, r2 + 80032c0: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 80032c4: 68db ldr r3, [r3, #12] + 80032c6: 68fa ldr r2, [r7, #12] + 80032c8: 0151 lsls r1, r2, #5 + 80032ca: 693a ldr r2, [r7, #16] + 80032cc: 440a add r2, r1 + 80032ce: f502 62a0 add.w r2, r2, #1280 ; 0x500 + 80032d2: f043 0302 orr.w r3, r3, #2 + 80032d6: 60d3 str r3, [r2, #12] + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + 80032d8: 687b ldr r3, [r7, #4] + 80032da: 681b ldr r3, [r3, #0] + 80032dc: 68fa ldr r2, [r7, #12] + 80032de: b2d2 uxtb r2, r2 + 80032e0: 4611 mov r1, r2 + 80032e2: 4618 mov r0, r3 + 80032e4: f004 fc59 bl 8007b9a + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); + 80032e8: 68fb ldr r3, [r7, #12] + 80032ea: 015a lsls r2, r3, #5 + 80032ec: 693b ldr r3, [r7, #16] + 80032ee: 4413 add r3, r2 + 80032f0: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 80032f4: 461a mov r2, r3 + 80032f6: 2310 movs r3, #16 + 80032f8: 6093 str r3, [r2, #8] + hhcd->hc[ch_num].state = HC_DATATGLERR; + 80032fa: 6879 ldr r1, [r7, #4] + 80032fc: 68fa ldr r2, [r7, #12] + 80032fe: 4613 mov r3, r2 + 8003300: 009b lsls r3, r3, #2 + 8003302: 4413 add r3, r2 + 8003304: 00db lsls r3, r3, #3 + 8003306: 440b add r3, r1 + 8003308: 335d adds r3, #93 ; 0x5d + 800330a: 2208 movs r2, #8 + 800330c: 701a strb r2, [r3, #0] + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR); + 800330e: 68fb ldr r3, [r7, #12] + 8003310: 015a lsls r2, r3, #5 + 8003312: 693b ldr r3, [r7, #16] + 8003314: 4413 add r3, r2 + 8003316: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 800331a: 461a mov r2, r3 + 800331c: f44f 6380 mov.w r3, #1024 ; 0x400 + 8003320: 6093 str r3, [r2, #8] + else + { + /* ... */ + } + + if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR) + 8003322: 68fb ldr r3, [r7, #12] + 8003324: 015a lsls r2, r3, #5 + 8003326: 693b ldr r3, [r7, #16] + 8003328: 4413 add r3, r2 + 800332a: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 800332e: 689b ldr r3, [r3, #8] + 8003330: f403 7300 and.w r3, r3, #512 ; 0x200 + 8003334: f5b3 7f00 cmp.w r3, #512 ; 0x200 + 8003338: d122 bne.n 8003380 + { + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + 800333a: 68fb ldr r3, [r7, #12] + 800333c: 015a lsls r2, r3, #5 + 800333e: 693b ldr r3, [r7, #16] + 8003340: 4413 add r3, r2 + 8003342: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8003346: 68db ldr r3, [r3, #12] + 8003348: 68fa ldr r2, [r7, #12] + 800334a: 0151 lsls r1, r2, #5 + 800334c: 693a ldr r2, [r7, #16] + 800334e: 440a add r2, r1 + 8003350: f502 62a0 add.w r2, r2, #1280 ; 0x500 + 8003354: f043 0302 orr.w r3, r3, #2 + 8003358: 60d3 str r3, [r2, #12] + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + 800335a: 687b ldr r3, [r7, #4] + 800335c: 681b ldr r3, [r3, #0] + 800335e: 68fa ldr r2, [r7, #12] + 8003360: b2d2 uxtb r2, r2 + 8003362: 4611 mov r1, r2 + 8003364: 4618 mov r0, r3 + 8003366: f004 fc18 bl 8007b9a + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR); + 800336a: 68fb ldr r3, [r7, #12] + 800336c: 015a lsls r2, r3, #5 + 800336e: 693b ldr r3, [r7, #16] + 8003370: 4413 add r3, r2 + 8003372: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8003376: 461a mov r2, r3 + 8003378: f44f 7300 mov.w r3, #512 ; 0x200 + 800337c: 6093 str r3, [r2, #8] + } + else + { + /* ... */ + } +} + 800337e: e300 b.n 8003982 + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC) + 8003380: 68fb ldr r3, [r7, #12] + 8003382: 015a lsls r2, r3, #5 + 8003384: 693b ldr r3, [r7, #16] + 8003386: 4413 add r3, r2 + 8003388: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 800338c: 689b ldr r3, [r3, #8] + 800338e: f003 0301 and.w r3, r3, #1 + 8003392: 2b01 cmp r3, #1 + 8003394: f040 80fd bne.w 8003592 + if (hhcd->Init.dma_enable != 0U) + 8003398: 687b ldr r3, [r7, #4] + 800339a: 691b ldr r3, [r3, #16] + 800339c: 2b00 cmp r3, #0 + 800339e: d01b beq.n 80033d8 + hhcd->hc[ch_num].xfer_count = hhcd->hc[ch_num].xfer_len - \ + 80033a0: 6879 ldr r1, [r7, #4] + 80033a2: 68fa ldr r2, [r7, #12] + 80033a4: 4613 mov r3, r2 + 80033a6: 009b lsls r3, r3, #2 + 80033a8: 4413 add r3, r2 + 80033aa: 00db lsls r3, r3, #3 + 80033ac: 440b add r3, r1 + 80033ae: 3348 adds r3, #72 ; 0x48 + 80033b0: 681a ldr r2, [r3, #0] + (USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ); + 80033b2: 68fb ldr r3, [r7, #12] + 80033b4: 0159 lsls r1, r3, #5 + 80033b6: 693b ldr r3, [r7, #16] + 80033b8: 440b add r3, r1 + 80033ba: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 80033be: 691b ldr r3, [r3, #16] + 80033c0: f3c3 0312 ubfx r3, r3, #0, #19 + hhcd->hc[ch_num].xfer_count = hhcd->hc[ch_num].xfer_len - \ + 80033c4: 1ad1 subs r1, r2, r3 + 80033c6: 6878 ldr r0, [r7, #4] + 80033c8: 68fa ldr r2, [r7, #12] + 80033ca: 4613 mov r3, r2 + 80033cc: 009b lsls r3, r3, #2 + 80033ce: 4413 add r3, r2 + 80033d0: 00db lsls r3, r3, #3 + 80033d2: 4403 add r3, r0 + 80033d4: 334c adds r3, #76 ; 0x4c + 80033d6: 6019 str r1, [r3, #0] + hhcd->hc[ch_num].state = HC_XFRC; + 80033d8: 6879 ldr r1, [r7, #4] + 80033da: 68fa ldr r2, [r7, #12] + 80033dc: 4613 mov r3, r2 + 80033de: 009b lsls r3, r3, #2 + 80033e0: 4413 add r3, r2 + 80033e2: 00db lsls r3, r3, #3 + 80033e4: 440b add r3, r1 + 80033e6: 335d adds r3, #93 ; 0x5d + 80033e8: 2201 movs r2, #1 + 80033ea: 701a strb r2, [r3, #0] + hhcd->hc[ch_num].ErrCnt = 0U; + 80033ec: 6879 ldr r1, [r7, #4] + 80033ee: 68fa ldr r2, [r7, #12] + 80033f0: 4613 mov r3, r2 + 80033f2: 009b lsls r3, r3, #2 + 80033f4: 4413 add r3, r2 + 80033f6: 00db lsls r3, r3, #3 + 80033f8: 440b add r3, r1 + 80033fa: 3358 adds r3, #88 ; 0x58 + 80033fc: 2200 movs r2, #0 + 80033fe: 601a str r2, [r3, #0] + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC); + 8003400: 68fb ldr r3, [r7, #12] + 8003402: 015a lsls r2, r3, #5 + 8003404: 693b ldr r3, [r7, #16] + 8003406: 4413 add r3, r2 + 8003408: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 800340c: 461a mov r2, r3 + 800340e: 2301 movs r3, #1 + 8003410: 6093 str r3, [r2, #8] + if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) || + 8003412: 6879 ldr r1, [r7, #4] + 8003414: 68fa ldr r2, [r7, #12] + 8003416: 4613 mov r3, r2 + 8003418: 009b lsls r3, r3, #2 + 800341a: 4413 add r3, r2 + 800341c: 00db lsls r3, r3, #3 + 800341e: 440b add r3, r1 + 8003420: 333f adds r3, #63 ; 0x3f + 8003422: 781b ldrb r3, [r3, #0] + 8003424: 2b00 cmp r3, #0 + 8003426: d00a beq.n 800343e + (hhcd->hc[ch_num].ep_type == EP_TYPE_BULK)) + 8003428: 6879 ldr r1, [r7, #4] + 800342a: 68fa ldr r2, [r7, #12] + 800342c: 4613 mov r3, r2 + 800342e: 009b lsls r3, r3, #2 + 8003430: 4413 add r3, r2 + 8003432: 00db lsls r3, r3, #3 + 8003434: 440b add r3, r1 + 8003436: 333f adds r3, #63 ; 0x3f + 8003438: 781b ldrb r3, [r3, #0] + if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) || + 800343a: 2b02 cmp r3, #2 + 800343c: d121 bne.n 8003482 + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + 800343e: 68fb ldr r3, [r7, #12] + 8003440: 015a lsls r2, r3, #5 + 8003442: 693b ldr r3, [r7, #16] + 8003444: 4413 add r3, r2 + 8003446: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 800344a: 68db ldr r3, [r3, #12] + 800344c: 68fa ldr r2, [r7, #12] + 800344e: 0151 lsls r1, r2, #5 + 8003450: 693a ldr r2, [r7, #16] + 8003452: 440a add r2, r1 + 8003454: f502 62a0 add.w r2, r2, #1280 ; 0x500 + 8003458: f043 0302 orr.w r3, r3, #2 + 800345c: 60d3 str r3, [r2, #12] + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + 800345e: 687b ldr r3, [r7, #4] + 8003460: 681b ldr r3, [r3, #0] + 8003462: 68fa ldr r2, [r7, #12] + 8003464: b2d2 uxtb r2, r2 + 8003466: 4611 mov r1, r2 + 8003468: 4618 mov r0, r3 + 800346a: f004 fb96 bl 8007b9a + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); + 800346e: 68fb ldr r3, [r7, #12] + 8003470: 015a lsls r2, r3, #5 + 8003472: 693b ldr r3, [r7, #16] + 8003474: 4413 add r3, r2 + 8003476: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 800347a: 461a mov r2, r3 + 800347c: 2310 movs r3, #16 + 800347e: 6093 str r3, [r2, #8] + 8003480: e070 b.n 8003564 + else if (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR) + 8003482: 6879 ldr r1, [r7, #4] + 8003484: 68fa ldr r2, [r7, #12] + 8003486: 4613 mov r3, r2 + 8003488: 009b lsls r3, r3, #2 + 800348a: 4413 add r3, r2 + 800348c: 00db lsls r3, r3, #3 + 800348e: 440b add r3, r1 + 8003490: 333f adds r3, #63 ; 0x3f + 8003492: 781b ldrb r3, [r3, #0] + 8003494: 2b03 cmp r3, #3 + 8003496: d12a bne.n 80034ee + USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM; + 8003498: 68fb ldr r3, [r7, #12] + 800349a: 015a lsls r2, r3, #5 + 800349c: 693b ldr r3, [r7, #16] + 800349e: 4413 add r3, r2 + 80034a0: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 80034a4: 681b ldr r3, [r3, #0] + 80034a6: 68fa ldr r2, [r7, #12] + 80034a8: 0151 lsls r1, r2, #5 + 80034aa: 693a ldr r2, [r7, #16] + 80034ac: 440a add r2, r1 + 80034ae: f502 62a0 add.w r2, r2, #1280 ; 0x500 + 80034b2: f043 5300 orr.w r3, r3, #536870912 ; 0x20000000 + 80034b6: 6013 str r3, [r2, #0] + hhcd->hc[ch_num].urb_state = URB_DONE; + 80034b8: 6879 ldr r1, [r7, #4] + 80034ba: 68fa ldr r2, [r7, #12] + 80034bc: 4613 mov r3, r2 + 80034be: 009b lsls r3, r3, #2 + 80034c0: 4413 add r3, r2 + 80034c2: 00db lsls r3, r3, #3 + 80034c4: 440b add r3, r1 + 80034c6: 335c adds r3, #92 ; 0x5c + 80034c8: 2201 movs r2, #1 + 80034ca: 701a strb r2, [r3, #0] + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); + 80034cc: 68fb ldr r3, [r7, #12] + 80034ce: b2d8 uxtb r0, r3 + 80034d0: 6879 ldr r1, [r7, #4] + 80034d2: 68fa ldr r2, [r7, #12] + 80034d4: 4613 mov r3, r2 + 80034d6: 009b lsls r3, r3, #2 + 80034d8: 4413 add r3, r2 + 80034da: 00db lsls r3, r3, #3 + 80034dc: 440b add r3, r1 + 80034de: 335c adds r3, #92 ; 0x5c + 80034e0: 781b ldrb r3, [r3, #0] + 80034e2: 461a mov r2, r3 + 80034e4: 4601 mov r1, r0 + 80034e6: 6878 ldr r0, [r7, #4] + 80034e8: f006 fcfa bl 8009ee0 + 80034ec: e03a b.n 8003564 + else if (hhcd->hc[ch_num].ep_type == EP_TYPE_ISOC) + 80034ee: 6879 ldr r1, [r7, #4] + 80034f0: 68fa ldr r2, [r7, #12] + 80034f2: 4613 mov r3, r2 + 80034f4: 009b lsls r3, r3, #2 + 80034f6: 4413 add r3, r2 + 80034f8: 00db lsls r3, r3, #3 + 80034fa: 440b add r3, r1 + 80034fc: 333f adds r3, #63 ; 0x3f + 80034fe: 781b ldrb r3, [r3, #0] + 8003500: 2b01 cmp r3, #1 + 8003502: d12f bne.n 8003564 + hhcd->hc[ch_num].urb_state = URB_DONE; + 8003504: 6879 ldr r1, [r7, #4] + 8003506: 68fa ldr r2, [r7, #12] + 8003508: 4613 mov r3, r2 + 800350a: 009b lsls r3, r3, #2 + 800350c: 4413 add r3, r2 + 800350e: 00db lsls r3, r3, #3 + 8003510: 440b add r3, r1 + 8003512: 335c adds r3, #92 ; 0x5c + 8003514: 2201 movs r2, #1 + 8003516: 701a strb r2, [r3, #0] + hhcd->hc[ch_num].toggle_in ^= 1U; + 8003518: 6879 ldr r1, [r7, #4] + 800351a: 68fa ldr r2, [r7, #12] + 800351c: 4613 mov r3, r2 + 800351e: 009b lsls r3, r3, #2 + 8003520: 4413 add r3, r2 + 8003522: 00db lsls r3, r3, #3 + 8003524: 440b add r3, r1 + 8003526: 3350 adds r3, #80 ; 0x50 + 8003528: 781b ldrb r3, [r3, #0] + 800352a: f083 0301 eor.w r3, r3, #1 + 800352e: b2d8 uxtb r0, r3 + 8003530: 6879 ldr r1, [r7, #4] + 8003532: 68fa ldr r2, [r7, #12] + 8003534: 4613 mov r3, r2 + 8003536: 009b lsls r3, r3, #2 + 8003538: 4413 add r3, r2 + 800353a: 00db lsls r3, r3, #3 + 800353c: 440b add r3, r1 + 800353e: 3350 adds r3, #80 ; 0x50 + 8003540: 4602 mov r2, r0 + 8003542: 701a strb r2, [r3, #0] + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); + 8003544: 68fb ldr r3, [r7, #12] + 8003546: b2d8 uxtb r0, r3 + 8003548: 6879 ldr r1, [r7, #4] + 800354a: 68fa ldr r2, [r7, #12] + 800354c: 4613 mov r3, r2 + 800354e: 009b lsls r3, r3, #2 + 8003550: 4413 add r3, r2 + 8003552: 00db lsls r3, r3, #3 + 8003554: 440b add r3, r1 + 8003556: 335c adds r3, #92 ; 0x5c + 8003558: 781b ldrb r3, [r3, #0] + 800355a: 461a mov r2, r3 + 800355c: 4601 mov r1, r0 + 800355e: 6878 ldr r0, [r7, #4] + 8003560: f006 fcbe bl 8009ee0 + hhcd->hc[ch_num].toggle_in ^= 1U; + 8003564: 6879 ldr r1, [r7, #4] + 8003566: 68fa ldr r2, [r7, #12] + 8003568: 4613 mov r3, r2 + 800356a: 009b lsls r3, r3, #2 + 800356c: 4413 add r3, r2 + 800356e: 00db lsls r3, r3, #3 + 8003570: 440b add r3, r1 + 8003572: 3350 adds r3, #80 ; 0x50 + 8003574: 781b ldrb r3, [r3, #0] + 8003576: f083 0301 eor.w r3, r3, #1 + 800357a: b2d8 uxtb r0, r3 + 800357c: 6879 ldr r1, [r7, #4] + 800357e: 68fa ldr r2, [r7, #12] + 8003580: 4613 mov r3, r2 + 8003582: 009b lsls r3, r3, #2 + 8003584: 4413 add r3, r2 + 8003586: 00db lsls r3, r3, #3 + 8003588: 440b add r3, r1 + 800358a: 3350 adds r3, #80 ; 0x50 + 800358c: 4602 mov r2, r0 + 800358e: 701a strb r2, [r3, #0] +} + 8003590: e1f7 b.n 8003982 + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH) + 8003592: 68fb ldr r3, [r7, #12] + 8003594: 015a lsls r2, r3, #5 + 8003596: 693b ldr r3, [r7, #16] + 8003598: 4413 add r3, r2 + 800359a: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 800359e: 689b ldr r3, [r3, #8] + 80035a0: f003 0302 and.w r3, r3, #2 + 80035a4: 2b02 cmp r3, #2 + 80035a6: f040 811a bne.w 80037de + __HAL_HCD_MASK_HALT_HC_INT(ch_num); + 80035aa: 68fb ldr r3, [r7, #12] + 80035ac: 015a lsls r2, r3, #5 + 80035ae: 693b ldr r3, [r7, #16] + 80035b0: 4413 add r3, r2 + 80035b2: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 80035b6: 68db ldr r3, [r3, #12] + 80035b8: 68fa ldr r2, [r7, #12] + 80035ba: 0151 lsls r1, r2, #5 + 80035bc: 693a ldr r2, [r7, #16] + 80035be: 440a add r2, r1 + 80035c0: f502 62a0 add.w r2, r2, #1280 ; 0x500 + 80035c4: f023 0302 bic.w r3, r3, #2 + 80035c8: 60d3 str r3, [r2, #12] + if (hhcd->hc[ch_num].state == HC_XFRC) + 80035ca: 6879 ldr r1, [r7, #4] + 80035cc: 68fa ldr r2, [r7, #12] + 80035ce: 4613 mov r3, r2 + 80035d0: 009b lsls r3, r3, #2 + 80035d2: 4413 add r3, r2 + 80035d4: 00db lsls r3, r3, #3 + 80035d6: 440b add r3, r1 + 80035d8: 335d adds r3, #93 ; 0x5d + 80035da: 781b ldrb r3, [r3, #0] + 80035dc: 2b01 cmp r3, #1 + 80035de: d10a bne.n 80035f6 + hhcd->hc[ch_num].urb_state = URB_DONE; + 80035e0: 6879 ldr r1, [r7, #4] + 80035e2: 68fa ldr r2, [r7, #12] + 80035e4: 4613 mov r3, r2 + 80035e6: 009b lsls r3, r3, #2 + 80035e8: 4413 add r3, r2 + 80035ea: 00db lsls r3, r3, #3 + 80035ec: 440b add r3, r1 + 80035ee: 335c adds r3, #92 ; 0x5c + 80035f0: 2201 movs r2, #1 + 80035f2: 701a strb r2, [r3, #0] + 80035f4: e0d9 b.n 80037aa + else if (hhcd->hc[ch_num].state == HC_STALL) + 80035f6: 6879 ldr r1, [r7, #4] + 80035f8: 68fa ldr r2, [r7, #12] + 80035fa: 4613 mov r3, r2 + 80035fc: 009b lsls r3, r3, #2 + 80035fe: 4413 add r3, r2 + 8003600: 00db lsls r3, r3, #3 + 8003602: 440b add r3, r1 + 8003604: 335d adds r3, #93 ; 0x5d + 8003606: 781b ldrb r3, [r3, #0] + 8003608: 2b05 cmp r3, #5 + 800360a: d10a bne.n 8003622 + hhcd->hc[ch_num].urb_state = URB_STALL; + 800360c: 6879 ldr r1, [r7, #4] + 800360e: 68fa ldr r2, [r7, #12] + 8003610: 4613 mov r3, r2 + 8003612: 009b lsls r3, r3, #2 + 8003614: 4413 add r3, r2 + 8003616: 00db lsls r3, r3, #3 + 8003618: 440b add r3, r1 + 800361a: 335c adds r3, #92 ; 0x5c + 800361c: 2205 movs r2, #5 + 800361e: 701a strb r2, [r3, #0] + 8003620: e0c3 b.n 80037aa + else if ((hhcd->hc[ch_num].state == HC_XACTERR) || + 8003622: 6879 ldr r1, [r7, #4] + 8003624: 68fa ldr r2, [r7, #12] + 8003626: 4613 mov r3, r2 + 8003628: 009b lsls r3, r3, #2 + 800362a: 4413 add r3, r2 + 800362c: 00db lsls r3, r3, #3 + 800362e: 440b add r3, r1 + 8003630: 335d adds r3, #93 ; 0x5d + 8003632: 781b ldrb r3, [r3, #0] + 8003634: 2b06 cmp r3, #6 + 8003636: d00a beq.n 800364e + (hhcd->hc[ch_num].state == HC_DATATGLERR)) + 8003638: 6879 ldr r1, [r7, #4] + 800363a: 68fa ldr r2, [r7, #12] + 800363c: 4613 mov r3, r2 + 800363e: 009b lsls r3, r3, #2 + 8003640: 4413 add r3, r2 + 8003642: 00db lsls r3, r3, #3 + 8003644: 440b add r3, r1 + 8003646: 335d adds r3, #93 ; 0x5d + 8003648: 781b ldrb r3, [r3, #0] + else if ((hhcd->hc[ch_num].state == HC_XACTERR) || + 800364a: 2b08 cmp r3, #8 + 800364c: d156 bne.n 80036fc + hhcd->hc[ch_num].ErrCnt++; + 800364e: 6879 ldr r1, [r7, #4] + 8003650: 68fa ldr r2, [r7, #12] + 8003652: 4613 mov r3, r2 + 8003654: 009b lsls r3, r3, #2 + 8003656: 4413 add r3, r2 + 8003658: 00db lsls r3, r3, #3 + 800365a: 440b add r3, r1 + 800365c: 3358 adds r3, #88 ; 0x58 + 800365e: 681b ldr r3, [r3, #0] + 8003660: 1c59 adds r1, r3, #1 + 8003662: 6878 ldr r0, [r7, #4] + 8003664: 68fa ldr r2, [r7, #12] + 8003666: 4613 mov r3, r2 + 8003668: 009b lsls r3, r3, #2 + 800366a: 4413 add r3, r2 + 800366c: 00db lsls r3, r3, #3 + 800366e: 4403 add r3, r0 + 8003670: 3358 adds r3, #88 ; 0x58 + 8003672: 6019 str r1, [r3, #0] + if (hhcd->hc[ch_num].ErrCnt > 3U) + 8003674: 6879 ldr r1, [r7, #4] + 8003676: 68fa ldr r2, [r7, #12] + 8003678: 4613 mov r3, r2 + 800367a: 009b lsls r3, r3, #2 + 800367c: 4413 add r3, r2 + 800367e: 00db lsls r3, r3, #3 + 8003680: 440b add r3, r1 + 8003682: 3358 adds r3, #88 ; 0x58 + 8003684: 681b ldr r3, [r3, #0] + 8003686: 2b03 cmp r3, #3 + 8003688: d914 bls.n 80036b4 + hhcd->hc[ch_num].ErrCnt = 0U; + 800368a: 6879 ldr r1, [r7, #4] + 800368c: 68fa ldr r2, [r7, #12] + 800368e: 4613 mov r3, r2 + 8003690: 009b lsls r3, r3, #2 + 8003692: 4413 add r3, r2 + 8003694: 00db lsls r3, r3, #3 + 8003696: 440b add r3, r1 + 8003698: 3358 adds r3, #88 ; 0x58 + 800369a: 2200 movs r2, #0 + 800369c: 601a str r2, [r3, #0] + hhcd->hc[ch_num].urb_state = URB_ERROR; + 800369e: 6879 ldr r1, [r7, #4] + 80036a0: 68fa ldr r2, [r7, #12] + 80036a2: 4613 mov r3, r2 + 80036a4: 009b lsls r3, r3, #2 + 80036a6: 4413 add r3, r2 + 80036a8: 00db lsls r3, r3, #3 + 80036aa: 440b add r3, r1 + 80036ac: 335c adds r3, #92 ; 0x5c + 80036ae: 2204 movs r2, #4 + 80036b0: 701a strb r2, [r3, #0] + 80036b2: e009 b.n 80036c8 + hhcd->hc[ch_num].urb_state = URB_NOTREADY; + 80036b4: 6879 ldr r1, [r7, #4] + 80036b6: 68fa ldr r2, [r7, #12] + 80036b8: 4613 mov r3, r2 + 80036ba: 009b lsls r3, r3, #2 + 80036bc: 4413 add r3, r2 + 80036be: 00db lsls r3, r3, #3 + 80036c0: 440b add r3, r1 + 80036c2: 335c adds r3, #92 ; 0x5c + 80036c4: 2202 movs r2, #2 + 80036c6: 701a strb r2, [r3, #0] + tmpreg = USBx_HC(ch_num)->HCCHAR; + 80036c8: 68fb ldr r3, [r7, #12] + 80036ca: 015a lsls r2, r3, #5 + 80036cc: 693b ldr r3, [r7, #16] + 80036ce: 4413 add r3, r2 + 80036d0: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 80036d4: 681b ldr r3, [r3, #0] + 80036d6: 60bb str r3, [r7, #8] + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + 80036d8: 68bb ldr r3, [r7, #8] + 80036da: f023 4380 bic.w r3, r3, #1073741824 ; 0x40000000 + 80036de: 60bb str r3, [r7, #8] + tmpreg |= USB_OTG_HCCHAR_CHENA; + 80036e0: 68bb ldr r3, [r7, #8] + 80036e2: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 + 80036e6: 60bb str r3, [r7, #8] + USBx_HC(ch_num)->HCCHAR = tmpreg; + 80036e8: 68fb ldr r3, [r7, #12] + 80036ea: 015a lsls r2, r3, #5 + 80036ec: 693b ldr r3, [r7, #16] + 80036ee: 4413 add r3, r2 + 80036f0: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 80036f4: 461a mov r2, r3 + 80036f6: 68bb ldr r3, [r7, #8] + 80036f8: 6013 str r3, [r2, #0] + 80036fa: e056 b.n 80037aa + else if (hhcd->hc[ch_num].state == HC_NAK) + 80036fc: 6879 ldr r1, [r7, #4] + 80036fe: 68fa ldr r2, [r7, #12] + 8003700: 4613 mov r3, r2 + 8003702: 009b lsls r3, r3, #2 + 8003704: 4413 add r3, r2 + 8003706: 00db lsls r3, r3, #3 + 8003708: 440b add r3, r1 + 800370a: 335d adds r3, #93 ; 0x5d + 800370c: 781b ldrb r3, [r3, #0] + 800370e: 2b03 cmp r3, #3 + 8003710: d123 bne.n 800375a + hhcd->hc[ch_num].urb_state = URB_NOTREADY; + 8003712: 6879 ldr r1, [r7, #4] + 8003714: 68fa ldr r2, [r7, #12] + 8003716: 4613 mov r3, r2 + 8003718: 009b lsls r3, r3, #2 + 800371a: 4413 add r3, r2 + 800371c: 00db lsls r3, r3, #3 + 800371e: 440b add r3, r1 + 8003720: 335c adds r3, #92 ; 0x5c + 8003722: 2202 movs r2, #2 + 8003724: 701a strb r2, [r3, #0] + tmpreg = USBx_HC(ch_num)->HCCHAR; + 8003726: 68fb ldr r3, [r7, #12] + 8003728: 015a lsls r2, r3, #5 + 800372a: 693b ldr r3, [r7, #16] + 800372c: 4413 add r3, r2 + 800372e: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8003732: 681b ldr r3, [r3, #0] + 8003734: 60bb str r3, [r7, #8] + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + 8003736: 68bb ldr r3, [r7, #8] + 8003738: f023 4380 bic.w r3, r3, #1073741824 ; 0x40000000 + 800373c: 60bb str r3, [r7, #8] + tmpreg |= USB_OTG_HCCHAR_CHENA; + 800373e: 68bb ldr r3, [r7, #8] + 8003740: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 + 8003744: 60bb str r3, [r7, #8] + USBx_HC(ch_num)->HCCHAR = tmpreg; + 8003746: 68fb ldr r3, [r7, #12] + 8003748: 015a lsls r2, r3, #5 + 800374a: 693b ldr r3, [r7, #16] + 800374c: 4413 add r3, r2 + 800374e: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8003752: 461a mov r2, r3 + 8003754: 68bb ldr r3, [r7, #8] + 8003756: 6013 str r3, [r2, #0] + 8003758: e027 b.n 80037aa + else if (hhcd->hc[ch_num].state == HC_BBLERR) + 800375a: 6879 ldr r1, [r7, #4] + 800375c: 68fa ldr r2, [r7, #12] + 800375e: 4613 mov r3, r2 + 8003760: 009b lsls r3, r3, #2 + 8003762: 4413 add r3, r2 + 8003764: 00db lsls r3, r3, #3 + 8003766: 440b add r3, r1 + 8003768: 335d adds r3, #93 ; 0x5d + 800376a: 781b ldrb r3, [r3, #0] + 800376c: 2b07 cmp r3, #7 + 800376e: d11c bne.n 80037aa + hhcd->hc[ch_num].ErrCnt++; + 8003770: 6879 ldr r1, [r7, #4] + 8003772: 68fa ldr r2, [r7, #12] + 8003774: 4613 mov r3, r2 + 8003776: 009b lsls r3, r3, #2 + 8003778: 4413 add r3, r2 + 800377a: 00db lsls r3, r3, #3 + 800377c: 440b add r3, r1 + 800377e: 3358 adds r3, #88 ; 0x58 + 8003780: 681b ldr r3, [r3, #0] + 8003782: 1c59 adds r1, r3, #1 + 8003784: 6878 ldr r0, [r7, #4] + 8003786: 68fa ldr r2, [r7, #12] + 8003788: 4613 mov r3, r2 + 800378a: 009b lsls r3, r3, #2 + 800378c: 4413 add r3, r2 + 800378e: 00db lsls r3, r3, #3 + 8003790: 4403 add r3, r0 + 8003792: 3358 adds r3, #88 ; 0x58 + 8003794: 6019 str r1, [r3, #0] + hhcd->hc[ch_num].urb_state = URB_ERROR; + 8003796: 6879 ldr r1, [r7, #4] + 8003798: 68fa ldr r2, [r7, #12] + 800379a: 4613 mov r3, r2 + 800379c: 009b lsls r3, r3, #2 + 800379e: 4413 add r3, r2 + 80037a0: 00db lsls r3, r3, #3 + 80037a2: 440b add r3, r1 + 80037a4: 335c adds r3, #92 ; 0x5c + 80037a6: 2204 movs r2, #4 + 80037a8: 701a strb r2, [r3, #0] + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH); + 80037aa: 68fb ldr r3, [r7, #12] + 80037ac: 015a lsls r2, r3, #5 + 80037ae: 693b ldr r3, [r7, #16] + 80037b0: 4413 add r3, r2 + 80037b2: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 80037b6: 461a mov r2, r3 + 80037b8: 2302 movs r3, #2 + 80037ba: 6093 str r3, [r2, #8] + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); + 80037bc: 68fb ldr r3, [r7, #12] + 80037be: b2d8 uxtb r0, r3 + 80037c0: 6879 ldr r1, [r7, #4] + 80037c2: 68fa ldr r2, [r7, #12] + 80037c4: 4613 mov r3, r2 + 80037c6: 009b lsls r3, r3, #2 + 80037c8: 4413 add r3, r2 + 80037ca: 00db lsls r3, r3, #3 + 80037cc: 440b add r3, r1 + 80037ce: 335c adds r3, #92 ; 0x5c + 80037d0: 781b ldrb r3, [r3, #0] + 80037d2: 461a mov r2, r3 + 80037d4: 4601 mov r1, r0 + 80037d6: 6878 ldr r0, [r7, #4] + 80037d8: f006 fb82 bl 8009ee0 +} + 80037dc: e0d1 b.n 8003982 + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR) + 80037de: 68fb ldr r3, [r7, #12] + 80037e0: 015a lsls r2, r3, #5 + 80037e2: 693b ldr r3, [r7, #16] + 80037e4: 4413 add r3, r2 + 80037e6: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 80037ea: 689b ldr r3, [r3, #8] + 80037ec: f003 0380 and.w r3, r3, #128 ; 0x80 + 80037f0: 2b80 cmp r3, #128 ; 0x80 + 80037f2: d13e bne.n 8003872 + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + 80037f4: 68fb ldr r3, [r7, #12] + 80037f6: 015a lsls r2, r3, #5 + 80037f8: 693b ldr r3, [r7, #16] + 80037fa: 4413 add r3, r2 + 80037fc: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8003800: 68db ldr r3, [r3, #12] + 8003802: 68fa ldr r2, [r7, #12] + 8003804: 0151 lsls r1, r2, #5 + 8003806: 693a ldr r2, [r7, #16] + 8003808: 440a add r2, r1 + 800380a: f502 62a0 add.w r2, r2, #1280 ; 0x500 + 800380e: f043 0302 orr.w r3, r3, #2 + 8003812: 60d3 str r3, [r2, #12] + hhcd->hc[ch_num].ErrCnt++; + 8003814: 6879 ldr r1, [r7, #4] + 8003816: 68fa ldr r2, [r7, #12] + 8003818: 4613 mov r3, r2 + 800381a: 009b lsls r3, r3, #2 + 800381c: 4413 add r3, r2 + 800381e: 00db lsls r3, r3, #3 + 8003820: 440b add r3, r1 + 8003822: 3358 adds r3, #88 ; 0x58 + 8003824: 681b ldr r3, [r3, #0] + 8003826: 1c59 adds r1, r3, #1 + 8003828: 6878 ldr r0, [r7, #4] + 800382a: 68fa ldr r2, [r7, #12] + 800382c: 4613 mov r3, r2 + 800382e: 009b lsls r3, r3, #2 + 8003830: 4413 add r3, r2 + 8003832: 00db lsls r3, r3, #3 + 8003834: 4403 add r3, r0 + 8003836: 3358 adds r3, #88 ; 0x58 + 8003838: 6019 str r1, [r3, #0] + hhcd->hc[ch_num].state = HC_XACTERR; + 800383a: 6879 ldr r1, [r7, #4] + 800383c: 68fa ldr r2, [r7, #12] + 800383e: 4613 mov r3, r2 + 8003840: 009b lsls r3, r3, #2 + 8003842: 4413 add r3, r2 + 8003844: 00db lsls r3, r3, #3 + 8003846: 440b add r3, r1 + 8003848: 335d adds r3, #93 ; 0x5d + 800384a: 2206 movs r2, #6 + 800384c: 701a strb r2, [r3, #0] + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + 800384e: 687b ldr r3, [r7, #4] + 8003850: 681b ldr r3, [r3, #0] + 8003852: 68fa ldr r2, [r7, #12] + 8003854: b2d2 uxtb r2, r2 + 8003856: 4611 mov r1, r2 + 8003858: 4618 mov r0, r3 + 800385a: f004 f99e bl 8007b9a + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR); + 800385e: 68fb ldr r3, [r7, #12] + 8003860: 015a lsls r2, r3, #5 + 8003862: 693b ldr r3, [r7, #16] + 8003864: 4413 add r3, r2 + 8003866: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 800386a: 461a mov r2, r3 + 800386c: 2380 movs r3, #128 ; 0x80 + 800386e: 6093 str r3, [r2, #8] +} + 8003870: e087 b.n 8003982 + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK) + 8003872: 68fb ldr r3, [r7, #12] + 8003874: 015a lsls r2, r3, #5 + 8003876: 693b ldr r3, [r7, #16] + 8003878: 4413 add r3, r2 + 800387a: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 800387e: 689b ldr r3, [r3, #8] + 8003880: f003 0310 and.w r3, r3, #16 + 8003884: 2b10 cmp r3, #16 + 8003886: d17c bne.n 8003982 + if (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR) + 8003888: 6879 ldr r1, [r7, #4] + 800388a: 68fa ldr r2, [r7, #12] + 800388c: 4613 mov r3, r2 + 800388e: 009b lsls r3, r3, #2 + 8003890: 4413 add r3, r2 + 8003892: 00db lsls r3, r3, #3 + 8003894: 440b add r3, r1 + 8003896: 333f adds r3, #63 ; 0x3f + 8003898: 781b ldrb r3, [r3, #0] + 800389a: 2b03 cmp r3, #3 + 800389c: d122 bne.n 80038e4 + hhcd->hc[ch_num].ErrCnt = 0U; + 800389e: 6879 ldr r1, [r7, #4] + 80038a0: 68fa ldr r2, [r7, #12] + 80038a2: 4613 mov r3, r2 + 80038a4: 009b lsls r3, r3, #2 + 80038a6: 4413 add r3, r2 + 80038a8: 00db lsls r3, r3, #3 + 80038aa: 440b add r3, r1 + 80038ac: 3358 adds r3, #88 ; 0x58 + 80038ae: 2200 movs r2, #0 + 80038b0: 601a str r2, [r3, #0] + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + 80038b2: 68fb ldr r3, [r7, #12] + 80038b4: 015a lsls r2, r3, #5 + 80038b6: 693b ldr r3, [r7, #16] + 80038b8: 4413 add r3, r2 + 80038ba: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 80038be: 68db ldr r3, [r3, #12] + 80038c0: 68fa ldr r2, [r7, #12] + 80038c2: 0151 lsls r1, r2, #5 + 80038c4: 693a ldr r2, [r7, #16] + 80038c6: 440a add r2, r1 + 80038c8: f502 62a0 add.w r2, r2, #1280 ; 0x500 + 80038cc: f043 0302 orr.w r3, r3, #2 + 80038d0: 60d3 str r3, [r2, #12] + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + 80038d2: 687b ldr r3, [r7, #4] + 80038d4: 681b ldr r3, [r3, #0] + 80038d6: 68fa ldr r2, [r7, #12] + 80038d8: b2d2 uxtb r2, r2 + 80038da: 4611 mov r1, r2 + 80038dc: 4618 mov r0, r3 + 80038de: f004 f95c bl 8007b9a + 80038e2: e045 b.n 8003970 + else if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) || + 80038e4: 6879 ldr r1, [r7, #4] + 80038e6: 68fa ldr r2, [r7, #12] + 80038e8: 4613 mov r3, r2 + 80038ea: 009b lsls r3, r3, #2 + 80038ec: 4413 add r3, r2 + 80038ee: 00db lsls r3, r3, #3 + 80038f0: 440b add r3, r1 + 80038f2: 333f adds r3, #63 ; 0x3f + 80038f4: 781b ldrb r3, [r3, #0] + 80038f6: 2b00 cmp r3, #0 + 80038f8: d00a beq.n 8003910 + (hhcd->hc[ch_num].ep_type == EP_TYPE_BULK)) + 80038fa: 6879 ldr r1, [r7, #4] + 80038fc: 68fa ldr r2, [r7, #12] + 80038fe: 4613 mov r3, r2 + 8003900: 009b lsls r3, r3, #2 + 8003902: 4413 add r3, r2 + 8003904: 00db lsls r3, r3, #3 + 8003906: 440b add r3, r1 + 8003908: 333f adds r3, #63 ; 0x3f + 800390a: 781b ldrb r3, [r3, #0] + else if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) || + 800390c: 2b02 cmp r3, #2 + 800390e: d12f bne.n 8003970 + hhcd->hc[ch_num].ErrCnt = 0U; + 8003910: 6879 ldr r1, [r7, #4] + 8003912: 68fa ldr r2, [r7, #12] + 8003914: 4613 mov r3, r2 + 8003916: 009b lsls r3, r3, #2 + 8003918: 4413 add r3, r2 + 800391a: 00db lsls r3, r3, #3 + 800391c: 440b add r3, r1 + 800391e: 3358 adds r3, #88 ; 0x58 + 8003920: 2200 movs r2, #0 + 8003922: 601a str r2, [r3, #0] + if (hhcd->Init.dma_enable == 0U) + 8003924: 687b ldr r3, [r7, #4] + 8003926: 691b ldr r3, [r3, #16] + 8003928: 2b00 cmp r3, #0 + 800392a: d121 bne.n 8003970 + hhcd->hc[ch_num].state = HC_NAK; + 800392c: 6879 ldr r1, [r7, #4] + 800392e: 68fa ldr r2, [r7, #12] + 8003930: 4613 mov r3, r2 + 8003932: 009b lsls r3, r3, #2 + 8003934: 4413 add r3, r2 + 8003936: 00db lsls r3, r3, #3 + 8003938: 440b add r3, r1 + 800393a: 335d adds r3, #93 ; 0x5d + 800393c: 2203 movs r2, #3 + 800393e: 701a strb r2, [r3, #0] + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + 8003940: 68fb ldr r3, [r7, #12] + 8003942: 015a lsls r2, r3, #5 + 8003944: 693b ldr r3, [r7, #16] + 8003946: 4413 add r3, r2 + 8003948: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 800394c: 68db ldr r3, [r3, #12] + 800394e: 68fa ldr r2, [r7, #12] + 8003950: 0151 lsls r1, r2, #5 + 8003952: 693a ldr r2, [r7, #16] + 8003954: 440a add r2, r1 + 8003956: f502 62a0 add.w r2, r2, #1280 ; 0x500 + 800395a: f043 0302 orr.w r3, r3, #2 + 800395e: 60d3 str r3, [r2, #12] + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + 8003960: 687b ldr r3, [r7, #4] + 8003962: 681b ldr r3, [r3, #0] + 8003964: 68fa ldr r2, [r7, #12] + 8003966: b2d2 uxtb r2, r2 + 8003968: 4611 mov r1, r2 + 800396a: 4618 mov r0, r3 + 800396c: f004 f915 bl 8007b9a + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); + 8003970: 68fb ldr r3, [r7, #12] + 8003972: 015a lsls r2, r3, #5 + 8003974: 693b ldr r3, [r7, #16] + 8003976: 4413 add r3, r2 + 8003978: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 800397c: 461a mov r2, r3 + 800397e: 2310 movs r3, #16 + 8003980: 6093 str r3, [r2, #8] +} + 8003982: bf00 nop + 8003984: 3718 adds r7, #24 + 8003986: 46bd mov sp, r7 + 8003988: bd80 pop {r7, pc} + +0800398a : + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @retval none + */ +static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) +{ + 800398a: b580 push {r7, lr} + 800398c: b086 sub sp, #24 + 800398e: af00 add r7, sp, #0 + 8003990: 6078 str r0, [r7, #4] + 8003992: 460b mov r3, r1 + 8003994: 70fb strb r3, [r7, #3] + USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + 8003996: 687b ldr r3, [r7, #4] + 8003998: 681b ldr r3, [r3, #0] + 800399a: 617b str r3, [r7, #20] + uint32_t USBx_BASE = (uint32_t)USBx; + 800399c: 697b ldr r3, [r7, #20] + 800399e: 613b str r3, [r7, #16] + uint32_t ch_num = (uint32_t)chnum; + 80039a0: 78fb ldrb r3, [r7, #3] + 80039a2: 60fb str r3, [r7, #12] + uint32_t tmpreg; + + if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR) + 80039a4: 68fb ldr r3, [r7, #12] + 80039a6: 015a lsls r2, r3, #5 + 80039a8: 693b ldr r3, [r7, #16] + 80039aa: 4413 add r3, r2 + 80039ac: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 80039b0: 689b ldr r3, [r3, #8] + 80039b2: f003 0304 and.w r3, r3, #4 + 80039b6: 2b04 cmp r3, #4 + 80039b8: d119 bne.n 80039ee + { + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR); + 80039ba: 68fb ldr r3, [r7, #12] + 80039bc: 015a lsls r2, r3, #5 + 80039be: 693b ldr r3, [r7, #16] + 80039c0: 4413 add r3, r2 + 80039c2: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 80039c6: 461a mov r2, r3 + 80039c8: 2304 movs r3, #4 + 80039ca: 6093 str r3, [r2, #8] + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + 80039cc: 68fb ldr r3, [r7, #12] + 80039ce: 015a lsls r2, r3, #5 + 80039d0: 693b ldr r3, [r7, #16] + 80039d2: 4413 add r3, r2 + 80039d4: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 80039d8: 68db ldr r3, [r3, #12] + 80039da: 68fa ldr r2, [r7, #12] + 80039dc: 0151 lsls r1, r2, #5 + 80039de: 693a ldr r2, [r7, #16] + 80039e0: 440a add r2, r1 + 80039e2: f502 62a0 add.w r2, r2, #1280 ; 0x500 + 80039e6: f043 0302 orr.w r3, r3, #2 + 80039ea: 60d3 str r3, [r2, #12] + } + else + { + /* ... */ + } +} + 80039ec: e33e b.n 800406c + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK) + 80039ee: 68fb ldr r3, [r7, #12] + 80039f0: 015a lsls r2, r3, #5 + 80039f2: 693b ldr r3, [r7, #16] + 80039f4: 4413 add r3, r2 + 80039f6: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 80039fa: 689b ldr r3, [r3, #8] + 80039fc: f003 0320 and.w r3, r3, #32 + 8003a00: 2b20 cmp r3, #32 + 8003a02: d141 bne.n 8003a88 + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_ACK); + 8003a04: 68fb ldr r3, [r7, #12] + 8003a06: 015a lsls r2, r3, #5 + 8003a08: 693b ldr r3, [r7, #16] + 8003a0a: 4413 add r3, r2 + 8003a0c: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8003a10: 461a mov r2, r3 + 8003a12: 2320 movs r3, #32 + 8003a14: 6093 str r3, [r2, #8] + if (hhcd->hc[ch_num].do_ping == 1U) + 8003a16: 6879 ldr r1, [r7, #4] + 8003a18: 68fa ldr r2, [r7, #12] + 8003a1a: 4613 mov r3, r2 + 8003a1c: 009b lsls r3, r3, #2 + 8003a1e: 4413 add r3, r2 + 8003a20: 00db lsls r3, r3, #3 + 8003a22: 440b add r3, r1 + 8003a24: 333d adds r3, #61 ; 0x3d + 8003a26: 781b ldrb r3, [r3, #0] + 8003a28: 2b01 cmp r3, #1 + 8003a2a: f040 831f bne.w 800406c + hhcd->hc[ch_num].do_ping = 0U; + 8003a2e: 6879 ldr r1, [r7, #4] + 8003a30: 68fa ldr r2, [r7, #12] + 8003a32: 4613 mov r3, r2 + 8003a34: 009b lsls r3, r3, #2 + 8003a36: 4413 add r3, r2 + 8003a38: 00db lsls r3, r3, #3 + 8003a3a: 440b add r3, r1 + 8003a3c: 333d adds r3, #61 ; 0x3d + 8003a3e: 2200 movs r2, #0 + 8003a40: 701a strb r2, [r3, #0] + hhcd->hc[ch_num].urb_state = URB_NOTREADY; + 8003a42: 6879 ldr r1, [r7, #4] + 8003a44: 68fa ldr r2, [r7, #12] + 8003a46: 4613 mov r3, r2 + 8003a48: 009b lsls r3, r3, #2 + 8003a4a: 4413 add r3, r2 + 8003a4c: 00db lsls r3, r3, #3 + 8003a4e: 440b add r3, r1 + 8003a50: 335c adds r3, #92 ; 0x5c + 8003a52: 2202 movs r2, #2 + 8003a54: 701a strb r2, [r3, #0] + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + 8003a56: 68fb ldr r3, [r7, #12] + 8003a58: 015a lsls r2, r3, #5 + 8003a5a: 693b ldr r3, [r7, #16] + 8003a5c: 4413 add r3, r2 + 8003a5e: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8003a62: 68db ldr r3, [r3, #12] + 8003a64: 68fa ldr r2, [r7, #12] + 8003a66: 0151 lsls r1, r2, #5 + 8003a68: 693a ldr r2, [r7, #16] + 8003a6a: 440a add r2, r1 + 8003a6c: f502 62a0 add.w r2, r2, #1280 ; 0x500 + 8003a70: f043 0302 orr.w r3, r3, #2 + 8003a74: 60d3 str r3, [r2, #12] + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + 8003a76: 687b ldr r3, [r7, #4] + 8003a78: 681b ldr r3, [r3, #0] + 8003a7a: 68fa ldr r2, [r7, #12] + 8003a7c: b2d2 uxtb r2, r2 + 8003a7e: 4611 mov r1, r2 + 8003a80: 4618 mov r0, r3 + 8003a82: f004 f88a bl 8007b9a +} + 8003a86: e2f1 b.n 800406c + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NYET) == USB_OTG_HCINT_NYET) + 8003a88: 68fb ldr r3, [r7, #12] + 8003a8a: 015a lsls r2, r3, #5 + 8003a8c: 693b ldr r3, [r7, #16] + 8003a8e: 4413 add r3, r2 + 8003a90: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8003a94: 689b ldr r3, [r3, #8] + 8003a96: f003 0340 and.w r3, r3, #64 ; 0x40 + 8003a9a: 2b40 cmp r3, #64 ; 0x40 + 8003a9c: d13f bne.n 8003b1e + hhcd->hc[ch_num].state = HC_NYET; + 8003a9e: 6879 ldr r1, [r7, #4] + 8003aa0: 68fa ldr r2, [r7, #12] + 8003aa2: 4613 mov r3, r2 + 8003aa4: 009b lsls r3, r3, #2 + 8003aa6: 4413 add r3, r2 + 8003aa8: 00db lsls r3, r3, #3 + 8003aaa: 440b add r3, r1 + 8003aac: 335d adds r3, #93 ; 0x5d + 8003aae: 2204 movs r2, #4 + 8003ab0: 701a strb r2, [r3, #0] + hhcd->hc[ch_num].do_ping = 1U; + 8003ab2: 6879 ldr r1, [r7, #4] + 8003ab4: 68fa ldr r2, [r7, #12] + 8003ab6: 4613 mov r3, r2 + 8003ab8: 009b lsls r3, r3, #2 + 8003aba: 4413 add r3, r2 + 8003abc: 00db lsls r3, r3, #3 + 8003abe: 440b add r3, r1 + 8003ac0: 333d adds r3, #61 ; 0x3d + 8003ac2: 2201 movs r2, #1 + 8003ac4: 701a strb r2, [r3, #0] + hhcd->hc[ch_num].ErrCnt = 0U; + 8003ac6: 6879 ldr r1, [r7, #4] + 8003ac8: 68fa ldr r2, [r7, #12] + 8003aca: 4613 mov r3, r2 + 8003acc: 009b lsls r3, r3, #2 + 8003ace: 4413 add r3, r2 + 8003ad0: 00db lsls r3, r3, #3 + 8003ad2: 440b add r3, r1 + 8003ad4: 3358 adds r3, #88 ; 0x58 + 8003ad6: 2200 movs r2, #0 + 8003ad8: 601a str r2, [r3, #0] + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + 8003ada: 68fb ldr r3, [r7, #12] + 8003adc: 015a lsls r2, r3, #5 + 8003ade: 693b ldr r3, [r7, #16] + 8003ae0: 4413 add r3, r2 + 8003ae2: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8003ae6: 68db ldr r3, [r3, #12] + 8003ae8: 68fa ldr r2, [r7, #12] + 8003aea: 0151 lsls r1, r2, #5 + 8003aec: 693a ldr r2, [r7, #16] + 8003aee: 440a add r2, r1 + 8003af0: f502 62a0 add.w r2, r2, #1280 ; 0x500 + 8003af4: f043 0302 orr.w r3, r3, #2 + 8003af8: 60d3 str r3, [r2, #12] + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + 8003afa: 687b ldr r3, [r7, #4] + 8003afc: 681b ldr r3, [r3, #0] + 8003afe: 68fa ldr r2, [r7, #12] + 8003b00: b2d2 uxtb r2, r2 + 8003b02: 4611 mov r1, r2 + 8003b04: 4618 mov r0, r3 + 8003b06: f004 f848 bl 8007b9a + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET); + 8003b0a: 68fb ldr r3, [r7, #12] + 8003b0c: 015a lsls r2, r3, #5 + 8003b0e: 693b ldr r3, [r7, #16] + 8003b10: 4413 add r3, r2 + 8003b12: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8003b16: 461a mov r2, r3 + 8003b18: 2340 movs r3, #64 ; 0x40 + 8003b1a: 6093 str r3, [r2, #8] +} + 8003b1c: e2a6 b.n 800406c + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR) + 8003b1e: 68fb ldr r3, [r7, #12] + 8003b20: 015a lsls r2, r3, #5 + 8003b22: 693b ldr r3, [r7, #16] + 8003b24: 4413 add r3, r2 + 8003b26: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8003b2a: 689b ldr r3, [r3, #8] + 8003b2c: f403 7300 and.w r3, r3, #512 ; 0x200 + 8003b30: f5b3 7f00 cmp.w r3, #512 ; 0x200 + 8003b34: d122 bne.n 8003b7c + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + 8003b36: 68fb ldr r3, [r7, #12] + 8003b38: 015a lsls r2, r3, #5 + 8003b3a: 693b ldr r3, [r7, #16] + 8003b3c: 4413 add r3, r2 + 8003b3e: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8003b42: 68db ldr r3, [r3, #12] + 8003b44: 68fa ldr r2, [r7, #12] + 8003b46: 0151 lsls r1, r2, #5 + 8003b48: 693a ldr r2, [r7, #16] + 8003b4a: 440a add r2, r1 + 8003b4c: f502 62a0 add.w r2, r2, #1280 ; 0x500 + 8003b50: f043 0302 orr.w r3, r3, #2 + 8003b54: 60d3 str r3, [r2, #12] + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + 8003b56: 687b ldr r3, [r7, #4] + 8003b58: 681b ldr r3, [r3, #0] + 8003b5a: 68fa ldr r2, [r7, #12] + 8003b5c: b2d2 uxtb r2, r2 + 8003b5e: 4611 mov r1, r2 + 8003b60: 4618 mov r0, r3 + 8003b62: f004 f81a bl 8007b9a + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR); + 8003b66: 68fb ldr r3, [r7, #12] + 8003b68: 015a lsls r2, r3, #5 + 8003b6a: 693b ldr r3, [r7, #16] + 8003b6c: 4413 add r3, r2 + 8003b6e: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8003b72: 461a mov r2, r3 + 8003b74: f44f 7300 mov.w r3, #512 ; 0x200 + 8003b78: 6093 str r3, [r2, #8] +} + 8003b7a: e277 b.n 800406c + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC) + 8003b7c: 68fb ldr r3, [r7, #12] + 8003b7e: 015a lsls r2, r3, #5 + 8003b80: 693b ldr r3, [r7, #16] + 8003b82: 4413 add r3, r2 + 8003b84: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8003b88: 689b ldr r3, [r3, #8] + 8003b8a: f003 0301 and.w r3, r3, #1 + 8003b8e: 2b01 cmp r3, #1 + 8003b90: d135 bne.n 8003bfe + hhcd->hc[ch_num].ErrCnt = 0U; + 8003b92: 6879 ldr r1, [r7, #4] + 8003b94: 68fa ldr r2, [r7, #12] + 8003b96: 4613 mov r3, r2 + 8003b98: 009b lsls r3, r3, #2 + 8003b9a: 4413 add r3, r2 + 8003b9c: 00db lsls r3, r3, #3 + 8003b9e: 440b add r3, r1 + 8003ba0: 3358 adds r3, #88 ; 0x58 + 8003ba2: 2200 movs r2, #0 + 8003ba4: 601a str r2, [r3, #0] + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + 8003ba6: 68fb ldr r3, [r7, #12] + 8003ba8: 015a lsls r2, r3, #5 + 8003baa: 693b ldr r3, [r7, #16] + 8003bac: 4413 add r3, r2 + 8003bae: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8003bb2: 68db ldr r3, [r3, #12] + 8003bb4: 68fa ldr r2, [r7, #12] + 8003bb6: 0151 lsls r1, r2, #5 + 8003bb8: 693a ldr r2, [r7, #16] + 8003bba: 440a add r2, r1 + 8003bbc: f502 62a0 add.w r2, r2, #1280 ; 0x500 + 8003bc0: f043 0302 orr.w r3, r3, #2 + 8003bc4: 60d3 str r3, [r2, #12] + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + 8003bc6: 687b ldr r3, [r7, #4] + 8003bc8: 681b ldr r3, [r3, #0] + 8003bca: 68fa ldr r2, [r7, #12] + 8003bcc: b2d2 uxtb r2, r2 + 8003bce: 4611 mov r1, r2 + 8003bd0: 4618 mov r0, r3 + 8003bd2: f003 ffe2 bl 8007b9a + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC); + 8003bd6: 68fb ldr r3, [r7, #12] + 8003bd8: 015a lsls r2, r3, #5 + 8003bda: 693b ldr r3, [r7, #16] + 8003bdc: 4413 add r3, r2 + 8003bde: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8003be2: 461a mov r2, r3 + 8003be4: 2301 movs r3, #1 + 8003be6: 6093 str r3, [r2, #8] + hhcd->hc[ch_num].state = HC_XFRC; + 8003be8: 6879 ldr r1, [r7, #4] + 8003bea: 68fa ldr r2, [r7, #12] + 8003bec: 4613 mov r3, r2 + 8003bee: 009b lsls r3, r3, #2 + 8003bf0: 4413 add r3, r2 + 8003bf2: 00db lsls r3, r3, #3 + 8003bf4: 440b add r3, r1 + 8003bf6: 335d adds r3, #93 ; 0x5d + 8003bf8: 2201 movs r2, #1 + 8003bfa: 701a strb r2, [r3, #0] +} + 8003bfc: e236 b.n 800406c + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL) + 8003bfe: 68fb ldr r3, [r7, #12] + 8003c00: 015a lsls r2, r3, #5 + 8003c02: 693b ldr r3, [r7, #16] + 8003c04: 4413 add r3, r2 + 8003c06: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8003c0a: 689b ldr r3, [r3, #8] + 8003c0c: f003 0308 and.w r3, r3, #8 + 8003c10: 2b08 cmp r3, #8 + 8003c12: d12b bne.n 8003c6c + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL); + 8003c14: 68fb ldr r3, [r7, #12] + 8003c16: 015a lsls r2, r3, #5 + 8003c18: 693b ldr r3, [r7, #16] + 8003c1a: 4413 add r3, r2 + 8003c1c: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8003c20: 461a mov r2, r3 + 8003c22: 2308 movs r3, #8 + 8003c24: 6093 str r3, [r2, #8] + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + 8003c26: 68fb ldr r3, [r7, #12] + 8003c28: 015a lsls r2, r3, #5 + 8003c2a: 693b ldr r3, [r7, #16] + 8003c2c: 4413 add r3, r2 + 8003c2e: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8003c32: 68db ldr r3, [r3, #12] + 8003c34: 68fa ldr r2, [r7, #12] + 8003c36: 0151 lsls r1, r2, #5 + 8003c38: 693a ldr r2, [r7, #16] + 8003c3a: 440a add r2, r1 + 8003c3c: f502 62a0 add.w r2, r2, #1280 ; 0x500 + 8003c40: f043 0302 orr.w r3, r3, #2 + 8003c44: 60d3 str r3, [r2, #12] + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + 8003c46: 687b ldr r3, [r7, #4] + 8003c48: 681b ldr r3, [r3, #0] + 8003c4a: 68fa ldr r2, [r7, #12] + 8003c4c: b2d2 uxtb r2, r2 + 8003c4e: 4611 mov r1, r2 + 8003c50: 4618 mov r0, r3 + 8003c52: f003 ffa2 bl 8007b9a + hhcd->hc[ch_num].state = HC_STALL; + 8003c56: 6879 ldr r1, [r7, #4] + 8003c58: 68fa ldr r2, [r7, #12] + 8003c5a: 4613 mov r3, r2 + 8003c5c: 009b lsls r3, r3, #2 + 8003c5e: 4413 add r3, r2 + 8003c60: 00db lsls r3, r3, #3 + 8003c62: 440b add r3, r1 + 8003c64: 335d adds r3, #93 ; 0x5d + 8003c66: 2205 movs r2, #5 + 8003c68: 701a strb r2, [r3, #0] +} + 8003c6a: e1ff b.n 800406c + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK) + 8003c6c: 68fb ldr r3, [r7, #12] + 8003c6e: 015a lsls r2, r3, #5 + 8003c70: 693b ldr r3, [r7, #16] + 8003c72: 4413 add r3, r2 + 8003c74: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8003c78: 689b ldr r3, [r3, #8] + 8003c7a: f003 0310 and.w r3, r3, #16 + 8003c7e: 2b10 cmp r3, #16 + 8003c80: d155 bne.n 8003d2e + hhcd->hc[ch_num].ErrCnt = 0U; + 8003c82: 6879 ldr r1, [r7, #4] + 8003c84: 68fa ldr r2, [r7, #12] + 8003c86: 4613 mov r3, r2 + 8003c88: 009b lsls r3, r3, #2 + 8003c8a: 4413 add r3, r2 + 8003c8c: 00db lsls r3, r3, #3 + 8003c8e: 440b add r3, r1 + 8003c90: 3358 adds r3, #88 ; 0x58 + 8003c92: 2200 movs r2, #0 + 8003c94: 601a str r2, [r3, #0] + hhcd->hc[ch_num].state = HC_NAK; + 8003c96: 6879 ldr r1, [r7, #4] + 8003c98: 68fa ldr r2, [r7, #12] + 8003c9a: 4613 mov r3, r2 + 8003c9c: 009b lsls r3, r3, #2 + 8003c9e: 4413 add r3, r2 + 8003ca0: 00db lsls r3, r3, #3 + 8003ca2: 440b add r3, r1 + 8003ca4: 335d adds r3, #93 ; 0x5d + 8003ca6: 2203 movs r2, #3 + 8003ca8: 701a strb r2, [r3, #0] + if (hhcd->hc[ch_num].do_ping == 0U) + 8003caa: 6879 ldr r1, [r7, #4] + 8003cac: 68fa ldr r2, [r7, #12] + 8003cae: 4613 mov r3, r2 + 8003cb0: 009b lsls r3, r3, #2 + 8003cb2: 4413 add r3, r2 + 8003cb4: 00db lsls r3, r3, #3 + 8003cb6: 440b add r3, r1 + 8003cb8: 333d adds r3, #61 ; 0x3d + 8003cba: 781b ldrb r3, [r3, #0] + 8003cbc: 2b00 cmp r3, #0 + 8003cbe: d114 bne.n 8003cea + if (hhcd->hc[ch_num].speed == HCD_SPEED_HIGH) + 8003cc0: 6879 ldr r1, [r7, #4] + 8003cc2: 68fa ldr r2, [r7, #12] + 8003cc4: 4613 mov r3, r2 + 8003cc6: 009b lsls r3, r3, #2 + 8003cc8: 4413 add r3, r2 + 8003cca: 00db lsls r3, r3, #3 + 8003ccc: 440b add r3, r1 + 8003cce: 333c adds r3, #60 ; 0x3c + 8003cd0: 781b ldrb r3, [r3, #0] + 8003cd2: 2b00 cmp r3, #0 + 8003cd4: d109 bne.n 8003cea + hhcd->hc[ch_num].do_ping = 1U; + 8003cd6: 6879 ldr r1, [r7, #4] + 8003cd8: 68fa ldr r2, [r7, #12] + 8003cda: 4613 mov r3, r2 + 8003cdc: 009b lsls r3, r3, #2 + 8003cde: 4413 add r3, r2 + 8003ce0: 00db lsls r3, r3, #3 + 8003ce2: 440b add r3, r1 + 8003ce4: 333d adds r3, #61 ; 0x3d + 8003ce6: 2201 movs r2, #1 + 8003ce8: 701a strb r2, [r3, #0] + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + 8003cea: 68fb ldr r3, [r7, #12] + 8003cec: 015a lsls r2, r3, #5 + 8003cee: 693b ldr r3, [r7, #16] + 8003cf0: 4413 add r3, r2 + 8003cf2: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8003cf6: 68db ldr r3, [r3, #12] + 8003cf8: 68fa ldr r2, [r7, #12] + 8003cfa: 0151 lsls r1, r2, #5 + 8003cfc: 693a ldr r2, [r7, #16] + 8003cfe: 440a add r2, r1 + 8003d00: f502 62a0 add.w r2, r2, #1280 ; 0x500 + 8003d04: f043 0302 orr.w r3, r3, #2 + 8003d08: 60d3 str r3, [r2, #12] + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + 8003d0a: 687b ldr r3, [r7, #4] + 8003d0c: 681b ldr r3, [r3, #0] + 8003d0e: 68fa ldr r2, [r7, #12] + 8003d10: b2d2 uxtb r2, r2 + 8003d12: 4611 mov r1, r2 + 8003d14: 4618 mov r0, r3 + 8003d16: f003 ff40 bl 8007b9a + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); + 8003d1a: 68fb ldr r3, [r7, #12] + 8003d1c: 015a lsls r2, r3, #5 + 8003d1e: 693b ldr r3, [r7, #16] + 8003d20: 4413 add r3, r2 + 8003d22: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8003d26: 461a mov r2, r3 + 8003d28: 2310 movs r3, #16 + 8003d2a: 6093 str r3, [r2, #8] +} + 8003d2c: e19e b.n 800406c + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR) + 8003d2e: 68fb ldr r3, [r7, #12] + 8003d30: 015a lsls r2, r3, #5 + 8003d32: 693b ldr r3, [r7, #16] + 8003d34: 4413 add r3, r2 + 8003d36: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8003d3a: 689b ldr r3, [r3, #8] + 8003d3c: f003 0380 and.w r3, r3, #128 ; 0x80 + 8003d40: 2b80 cmp r3, #128 ; 0x80 + 8003d42: d12b bne.n 8003d9c + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + 8003d44: 68fb ldr r3, [r7, #12] + 8003d46: 015a lsls r2, r3, #5 + 8003d48: 693b ldr r3, [r7, #16] + 8003d4a: 4413 add r3, r2 + 8003d4c: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8003d50: 68db ldr r3, [r3, #12] + 8003d52: 68fa ldr r2, [r7, #12] + 8003d54: 0151 lsls r1, r2, #5 + 8003d56: 693a ldr r2, [r7, #16] + 8003d58: 440a add r2, r1 + 8003d5a: f502 62a0 add.w r2, r2, #1280 ; 0x500 + 8003d5e: f043 0302 orr.w r3, r3, #2 + 8003d62: 60d3 str r3, [r2, #12] + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + 8003d64: 687b ldr r3, [r7, #4] + 8003d66: 681b ldr r3, [r3, #0] + 8003d68: 68fa ldr r2, [r7, #12] + 8003d6a: b2d2 uxtb r2, r2 + 8003d6c: 4611 mov r1, r2 + 8003d6e: 4618 mov r0, r3 + 8003d70: f003 ff13 bl 8007b9a + hhcd->hc[ch_num].state = HC_XACTERR; + 8003d74: 6879 ldr r1, [r7, #4] + 8003d76: 68fa ldr r2, [r7, #12] + 8003d78: 4613 mov r3, r2 + 8003d7a: 009b lsls r3, r3, #2 + 8003d7c: 4413 add r3, r2 + 8003d7e: 00db lsls r3, r3, #3 + 8003d80: 440b add r3, r1 + 8003d82: 335d adds r3, #93 ; 0x5d + 8003d84: 2206 movs r2, #6 + 8003d86: 701a strb r2, [r3, #0] + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR); + 8003d88: 68fb ldr r3, [r7, #12] + 8003d8a: 015a lsls r2, r3, #5 + 8003d8c: 693b ldr r3, [r7, #16] + 8003d8e: 4413 add r3, r2 + 8003d90: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8003d94: 461a mov r2, r3 + 8003d96: 2380 movs r3, #128 ; 0x80 + 8003d98: 6093 str r3, [r2, #8] +} + 8003d9a: e167 b.n 800406c + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR) + 8003d9c: 68fb ldr r3, [r7, #12] + 8003d9e: 015a lsls r2, r3, #5 + 8003da0: 693b ldr r3, [r7, #16] + 8003da2: 4413 add r3, r2 + 8003da4: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8003da8: 689b ldr r3, [r3, #8] + 8003daa: f403 6380 and.w r3, r3, #1024 ; 0x400 + 8003dae: f5b3 6f80 cmp.w r3, #1024 ; 0x400 + 8003db2: d135 bne.n 8003e20 + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + 8003db4: 68fb ldr r3, [r7, #12] + 8003db6: 015a lsls r2, r3, #5 + 8003db8: 693b ldr r3, [r7, #16] + 8003dba: 4413 add r3, r2 + 8003dbc: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8003dc0: 68db ldr r3, [r3, #12] + 8003dc2: 68fa ldr r2, [r7, #12] + 8003dc4: 0151 lsls r1, r2, #5 + 8003dc6: 693a ldr r2, [r7, #16] + 8003dc8: 440a add r2, r1 + 8003dca: f502 62a0 add.w r2, r2, #1280 ; 0x500 + 8003dce: f043 0302 orr.w r3, r3, #2 + 8003dd2: 60d3 str r3, [r2, #12] + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + 8003dd4: 687b ldr r3, [r7, #4] + 8003dd6: 681b ldr r3, [r3, #0] + 8003dd8: 68fa ldr r2, [r7, #12] + 8003dda: b2d2 uxtb r2, r2 + 8003ddc: 4611 mov r1, r2 + 8003dde: 4618 mov r0, r3 + 8003de0: f003 fedb bl 8007b9a + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); + 8003de4: 68fb ldr r3, [r7, #12] + 8003de6: 015a lsls r2, r3, #5 + 8003de8: 693b ldr r3, [r7, #16] + 8003dea: 4413 add r3, r2 + 8003dec: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8003df0: 461a mov r2, r3 + 8003df2: 2310 movs r3, #16 + 8003df4: 6093 str r3, [r2, #8] + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR); + 8003df6: 68fb ldr r3, [r7, #12] + 8003df8: 015a lsls r2, r3, #5 + 8003dfa: 693b ldr r3, [r7, #16] + 8003dfc: 4413 add r3, r2 + 8003dfe: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8003e02: 461a mov r2, r3 + 8003e04: f44f 6380 mov.w r3, #1024 ; 0x400 + 8003e08: 6093 str r3, [r2, #8] + hhcd->hc[ch_num].state = HC_DATATGLERR; + 8003e0a: 6879 ldr r1, [r7, #4] + 8003e0c: 68fa ldr r2, [r7, #12] + 8003e0e: 4613 mov r3, r2 + 8003e10: 009b lsls r3, r3, #2 + 8003e12: 4413 add r3, r2 + 8003e14: 00db lsls r3, r3, #3 + 8003e16: 440b add r3, r1 + 8003e18: 335d adds r3, #93 ; 0x5d + 8003e1a: 2208 movs r2, #8 + 8003e1c: 701a strb r2, [r3, #0] +} + 8003e1e: e125 b.n 800406c + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH) + 8003e20: 68fb ldr r3, [r7, #12] + 8003e22: 015a lsls r2, r3, #5 + 8003e24: 693b ldr r3, [r7, #16] + 8003e26: 4413 add r3, r2 + 8003e28: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8003e2c: 689b ldr r3, [r3, #8] + 8003e2e: f003 0302 and.w r3, r3, #2 + 8003e32: 2b02 cmp r3, #2 + 8003e34: f040 811a bne.w 800406c + __HAL_HCD_MASK_HALT_HC_INT(ch_num); + 8003e38: 68fb ldr r3, [r7, #12] + 8003e3a: 015a lsls r2, r3, #5 + 8003e3c: 693b ldr r3, [r7, #16] + 8003e3e: 4413 add r3, r2 + 8003e40: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8003e44: 68db ldr r3, [r3, #12] + 8003e46: 68fa ldr r2, [r7, #12] + 8003e48: 0151 lsls r1, r2, #5 + 8003e4a: 693a ldr r2, [r7, #16] + 8003e4c: 440a add r2, r1 + 8003e4e: f502 62a0 add.w r2, r2, #1280 ; 0x500 + 8003e52: f023 0302 bic.w r3, r3, #2 + 8003e56: 60d3 str r3, [r2, #12] + if (hhcd->hc[ch_num].state == HC_XFRC) + 8003e58: 6879 ldr r1, [r7, #4] + 8003e5a: 68fa ldr r2, [r7, #12] + 8003e5c: 4613 mov r3, r2 + 8003e5e: 009b lsls r3, r3, #2 + 8003e60: 4413 add r3, r2 + 8003e62: 00db lsls r3, r3, #3 + 8003e64: 440b add r3, r1 + 8003e66: 335d adds r3, #93 ; 0x5d + 8003e68: 781b ldrb r3, [r3, #0] + 8003e6a: 2b01 cmp r3, #1 + 8003e6c: d137 bne.n 8003ede + hhcd->hc[ch_num].urb_state = URB_DONE; + 8003e6e: 6879 ldr r1, [r7, #4] + 8003e70: 68fa ldr r2, [r7, #12] + 8003e72: 4613 mov r3, r2 + 8003e74: 009b lsls r3, r3, #2 + 8003e76: 4413 add r3, r2 + 8003e78: 00db lsls r3, r3, #3 + 8003e7a: 440b add r3, r1 + 8003e7c: 335c adds r3, #92 ; 0x5c + 8003e7e: 2201 movs r2, #1 + 8003e80: 701a strb r2, [r3, #0] + if ((hhcd->hc[ch_num].ep_type == EP_TYPE_BULK) || + 8003e82: 6879 ldr r1, [r7, #4] + 8003e84: 68fa ldr r2, [r7, #12] + 8003e86: 4613 mov r3, r2 + 8003e88: 009b lsls r3, r3, #2 + 8003e8a: 4413 add r3, r2 + 8003e8c: 00db lsls r3, r3, #3 + 8003e8e: 440b add r3, r1 + 8003e90: 333f adds r3, #63 ; 0x3f + 8003e92: 781b ldrb r3, [r3, #0] + 8003e94: 2b02 cmp r3, #2 + 8003e96: d00b beq.n 8003eb0 + (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR)) + 8003e98: 6879 ldr r1, [r7, #4] + 8003e9a: 68fa ldr r2, [r7, #12] + 8003e9c: 4613 mov r3, r2 + 8003e9e: 009b lsls r3, r3, #2 + 8003ea0: 4413 add r3, r2 + 8003ea2: 00db lsls r3, r3, #3 + 8003ea4: 440b add r3, r1 + 8003ea6: 333f adds r3, #63 ; 0x3f + 8003ea8: 781b ldrb r3, [r3, #0] + if ((hhcd->hc[ch_num].ep_type == EP_TYPE_BULK) || + 8003eaa: 2b03 cmp r3, #3 + 8003eac: f040 80c5 bne.w 800403a + hhcd->hc[ch_num].toggle_out ^= 1U; + 8003eb0: 6879 ldr r1, [r7, #4] + 8003eb2: 68fa ldr r2, [r7, #12] + 8003eb4: 4613 mov r3, r2 + 8003eb6: 009b lsls r3, r3, #2 + 8003eb8: 4413 add r3, r2 + 8003eba: 00db lsls r3, r3, #3 + 8003ebc: 440b add r3, r1 + 8003ebe: 3351 adds r3, #81 ; 0x51 + 8003ec0: 781b ldrb r3, [r3, #0] + 8003ec2: f083 0301 eor.w r3, r3, #1 + 8003ec6: b2d8 uxtb r0, r3 + 8003ec8: 6879 ldr r1, [r7, #4] + 8003eca: 68fa ldr r2, [r7, #12] + 8003ecc: 4613 mov r3, r2 + 8003ece: 009b lsls r3, r3, #2 + 8003ed0: 4413 add r3, r2 + 8003ed2: 00db lsls r3, r3, #3 + 8003ed4: 440b add r3, r1 + 8003ed6: 3351 adds r3, #81 ; 0x51 + 8003ed8: 4602 mov r2, r0 + 8003eda: 701a strb r2, [r3, #0] + 8003edc: e0ad b.n 800403a + else if (hhcd->hc[ch_num].state == HC_NAK) + 8003ede: 6879 ldr r1, [r7, #4] + 8003ee0: 68fa ldr r2, [r7, #12] + 8003ee2: 4613 mov r3, r2 + 8003ee4: 009b lsls r3, r3, #2 + 8003ee6: 4413 add r3, r2 + 8003ee8: 00db lsls r3, r3, #3 + 8003eea: 440b add r3, r1 + 8003eec: 335d adds r3, #93 ; 0x5d + 8003eee: 781b ldrb r3, [r3, #0] + 8003ef0: 2b03 cmp r3, #3 + 8003ef2: d10a bne.n 8003f0a + hhcd->hc[ch_num].urb_state = URB_NOTREADY; + 8003ef4: 6879 ldr r1, [r7, #4] + 8003ef6: 68fa ldr r2, [r7, #12] + 8003ef8: 4613 mov r3, r2 + 8003efa: 009b lsls r3, r3, #2 + 8003efc: 4413 add r3, r2 + 8003efe: 00db lsls r3, r3, #3 + 8003f00: 440b add r3, r1 + 8003f02: 335c adds r3, #92 ; 0x5c + 8003f04: 2202 movs r2, #2 + 8003f06: 701a strb r2, [r3, #0] + 8003f08: e097 b.n 800403a + else if (hhcd->hc[ch_num].state == HC_NYET) + 8003f0a: 6879 ldr r1, [r7, #4] + 8003f0c: 68fa ldr r2, [r7, #12] + 8003f0e: 4613 mov r3, r2 + 8003f10: 009b lsls r3, r3, #2 + 8003f12: 4413 add r3, r2 + 8003f14: 00db lsls r3, r3, #3 + 8003f16: 440b add r3, r1 + 8003f18: 335d adds r3, #93 ; 0x5d + 8003f1a: 781b ldrb r3, [r3, #0] + 8003f1c: 2b04 cmp r3, #4 + 8003f1e: d10a bne.n 8003f36 + hhcd->hc[ch_num].urb_state = URB_NOTREADY; + 8003f20: 6879 ldr r1, [r7, #4] + 8003f22: 68fa ldr r2, [r7, #12] + 8003f24: 4613 mov r3, r2 + 8003f26: 009b lsls r3, r3, #2 + 8003f28: 4413 add r3, r2 + 8003f2a: 00db lsls r3, r3, #3 + 8003f2c: 440b add r3, r1 + 8003f2e: 335c adds r3, #92 ; 0x5c + 8003f30: 2202 movs r2, #2 + 8003f32: 701a strb r2, [r3, #0] + 8003f34: e081 b.n 800403a + else if (hhcd->hc[ch_num].state == HC_STALL) + 8003f36: 6879 ldr r1, [r7, #4] + 8003f38: 68fa ldr r2, [r7, #12] + 8003f3a: 4613 mov r3, r2 + 8003f3c: 009b lsls r3, r3, #2 + 8003f3e: 4413 add r3, r2 + 8003f40: 00db lsls r3, r3, #3 + 8003f42: 440b add r3, r1 + 8003f44: 335d adds r3, #93 ; 0x5d + 8003f46: 781b ldrb r3, [r3, #0] + 8003f48: 2b05 cmp r3, #5 + 8003f4a: d10a bne.n 8003f62 + hhcd->hc[ch_num].urb_state = URB_STALL; + 8003f4c: 6879 ldr r1, [r7, #4] + 8003f4e: 68fa ldr r2, [r7, #12] + 8003f50: 4613 mov r3, r2 + 8003f52: 009b lsls r3, r3, #2 + 8003f54: 4413 add r3, r2 + 8003f56: 00db lsls r3, r3, #3 + 8003f58: 440b add r3, r1 + 8003f5a: 335c adds r3, #92 ; 0x5c + 8003f5c: 2205 movs r2, #5 + 8003f5e: 701a strb r2, [r3, #0] + 8003f60: e06b b.n 800403a + else if ((hhcd->hc[ch_num].state == HC_XACTERR) || + 8003f62: 6879 ldr r1, [r7, #4] + 8003f64: 68fa ldr r2, [r7, #12] + 8003f66: 4613 mov r3, r2 + 8003f68: 009b lsls r3, r3, #2 + 8003f6a: 4413 add r3, r2 + 8003f6c: 00db lsls r3, r3, #3 + 8003f6e: 440b add r3, r1 + 8003f70: 335d adds r3, #93 ; 0x5d + 8003f72: 781b ldrb r3, [r3, #0] + 8003f74: 2b06 cmp r3, #6 + 8003f76: d00a beq.n 8003f8e + (hhcd->hc[ch_num].state == HC_DATATGLERR)) + 8003f78: 6879 ldr r1, [r7, #4] + 8003f7a: 68fa ldr r2, [r7, #12] + 8003f7c: 4613 mov r3, r2 + 8003f7e: 009b lsls r3, r3, #2 + 8003f80: 4413 add r3, r2 + 8003f82: 00db lsls r3, r3, #3 + 8003f84: 440b add r3, r1 + 8003f86: 335d adds r3, #93 ; 0x5d + 8003f88: 781b ldrb r3, [r3, #0] + else if ((hhcd->hc[ch_num].state == HC_XACTERR) || + 8003f8a: 2b08 cmp r3, #8 + 8003f8c: d155 bne.n 800403a + hhcd->hc[ch_num].ErrCnt++; + 8003f8e: 6879 ldr r1, [r7, #4] + 8003f90: 68fa ldr r2, [r7, #12] + 8003f92: 4613 mov r3, r2 + 8003f94: 009b lsls r3, r3, #2 + 8003f96: 4413 add r3, r2 + 8003f98: 00db lsls r3, r3, #3 + 8003f9a: 440b add r3, r1 + 8003f9c: 3358 adds r3, #88 ; 0x58 + 8003f9e: 681b ldr r3, [r3, #0] + 8003fa0: 1c59 adds r1, r3, #1 + 8003fa2: 6878 ldr r0, [r7, #4] + 8003fa4: 68fa ldr r2, [r7, #12] + 8003fa6: 4613 mov r3, r2 + 8003fa8: 009b lsls r3, r3, #2 + 8003faa: 4413 add r3, r2 + 8003fac: 00db lsls r3, r3, #3 + 8003fae: 4403 add r3, r0 + 8003fb0: 3358 adds r3, #88 ; 0x58 + 8003fb2: 6019 str r1, [r3, #0] + if (hhcd->hc[ch_num].ErrCnt > 3U) + 8003fb4: 6879 ldr r1, [r7, #4] + 8003fb6: 68fa ldr r2, [r7, #12] + 8003fb8: 4613 mov r3, r2 + 8003fba: 009b lsls r3, r3, #2 + 8003fbc: 4413 add r3, r2 + 8003fbe: 00db lsls r3, r3, #3 + 8003fc0: 440b add r3, r1 + 8003fc2: 3358 adds r3, #88 ; 0x58 + 8003fc4: 681b ldr r3, [r3, #0] + 8003fc6: 2b03 cmp r3, #3 + 8003fc8: d914 bls.n 8003ff4 + hhcd->hc[ch_num].ErrCnt = 0U; + 8003fca: 6879 ldr r1, [r7, #4] + 8003fcc: 68fa ldr r2, [r7, #12] + 8003fce: 4613 mov r3, r2 + 8003fd0: 009b lsls r3, r3, #2 + 8003fd2: 4413 add r3, r2 + 8003fd4: 00db lsls r3, r3, #3 + 8003fd6: 440b add r3, r1 + 8003fd8: 3358 adds r3, #88 ; 0x58 + 8003fda: 2200 movs r2, #0 + 8003fdc: 601a str r2, [r3, #0] + hhcd->hc[ch_num].urb_state = URB_ERROR; + 8003fde: 6879 ldr r1, [r7, #4] + 8003fe0: 68fa ldr r2, [r7, #12] + 8003fe2: 4613 mov r3, r2 + 8003fe4: 009b lsls r3, r3, #2 + 8003fe6: 4413 add r3, r2 + 8003fe8: 00db lsls r3, r3, #3 + 8003fea: 440b add r3, r1 + 8003fec: 335c adds r3, #92 ; 0x5c + 8003fee: 2204 movs r2, #4 + 8003ff0: 701a strb r2, [r3, #0] + 8003ff2: e009 b.n 8004008 + hhcd->hc[ch_num].urb_state = URB_NOTREADY; + 8003ff4: 6879 ldr r1, [r7, #4] + 8003ff6: 68fa ldr r2, [r7, #12] + 8003ff8: 4613 mov r3, r2 + 8003ffa: 009b lsls r3, r3, #2 + 8003ffc: 4413 add r3, r2 + 8003ffe: 00db lsls r3, r3, #3 + 8004000: 440b add r3, r1 + 8004002: 335c adds r3, #92 ; 0x5c + 8004004: 2202 movs r2, #2 + 8004006: 701a strb r2, [r3, #0] + tmpreg = USBx_HC(ch_num)->HCCHAR; + 8004008: 68fb ldr r3, [r7, #12] + 800400a: 015a lsls r2, r3, #5 + 800400c: 693b ldr r3, [r7, #16] + 800400e: 4413 add r3, r2 + 8004010: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8004014: 681b ldr r3, [r3, #0] + 8004016: 60bb str r3, [r7, #8] + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + 8004018: 68bb ldr r3, [r7, #8] + 800401a: f023 4380 bic.w r3, r3, #1073741824 ; 0x40000000 + 800401e: 60bb str r3, [r7, #8] + tmpreg |= USB_OTG_HCCHAR_CHENA; + 8004020: 68bb ldr r3, [r7, #8] + 8004022: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 + 8004026: 60bb str r3, [r7, #8] + USBx_HC(ch_num)->HCCHAR = tmpreg; + 8004028: 68fb ldr r3, [r7, #12] + 800402a: 015a lsls r2, r3, #5 + 800402c: 693b ldr r3, [r7, #16] + 800402e: 4413 add r3, r2 + 8004030: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8004034: 461a mov r2, r3 + 8004036: 68bb ldr r3, [r7, #8] + 8004038: 6013 str r3, [r2, #0] + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH); + 800403a: 68fb ldr r3, [r7, #12] + 800403c: 015a lsls r2, r3, #5 + 800403e: 693b ldr r3, [r7, #16] + 8004040: 4413 add r3, r2 + 8004042: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8004046: 461a mov r2, r3 + 8004048: 2302 movs r3, #2 + 800404a: 6093 str r3, [r2, #8] + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); + 800404c: 68fb ldr r3, [r7, #12] + 800404e: b2d8 uxtb r0, r3 + 8004050: 6879 ldr r1, [r7, #4] + 8004052: 68fa ldr r2, [r7, #12] + 8004054: 4613 mov r3, r2 + 8004056: 009b lsls r3, r3, #2 + 8004058: 4413 add r3, r2 + 800405a: 00db lsls r3, r3, #3 + 800405c: 440b add r3, r1 + 800405e: 335c adds r3, #92 ; 0x5c + 8004060: 781b ldrb r3, [r3, #0] + 8004062: 461a mov r2, r3 + 8004064: 4601 mov r1, r0 + 8004066: 6878 ldr r0, [r7, #4] + 8004068: f005 ff3a bl 8009ee0 +} + 800406c: bf00 nop + 800406e: 3718 adds r7, #24 + 8004070: 46bd mov sp, r7 + 8004072: bd80 pop {r7, pc} + +08004074 : + * @brief Handle Rx Queue Level interrupt requests. + * @param hhcd HCD handle + * @retval none + */ +static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd) +{ + 8004074: b580 push {r7, lr} + 8004076: b08a sub sp, #40 ; 0x28 + 8004078: af00 add r7, sp, #0 + 800407a: 6078 str r0, [r7, #4] + USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + 800407c: 687b ldr r3, [r7, #4] + 800407e: 681b ldr r3, [r3, #0] + 8004080: 627b str r3, [r7, #36] ; 0x24 + uint32_t USBx_BASE = (uint32_t)USBx; + 8004082: 6a7b ldr r3, [r7, #36] ; 0x24 + 8004084: 623b str r3, [r7, #32] + uint32_t pktcnt; + uint32_t temp; + uint32_t tmpreg; + uint32_t ch_num; + + temp = hhcd->Instance->GRXSTSP; + 8004086: 687b ldr r3, [r7, #4] + 8004088: 681b ldr r3, [r3, #0] + 800408a: 6a1b ldr r3, [r3, #32] + 800408c: 61fb str r3, [r7, #28] + ch_num = temp & USB_OTG_GRXSTSP_EPNUM; + 800408e: 69fb ldr r3, [r7, #28] + 8004090: f003 030f and.w r3, r3, #15 + 8004094: 61bb str r3, [r7, #24] + pktsts = (temp & USB_OTG_GRXSTSP_PKTSTS) >> 17; + 8004096: 69fb ldr r3, [r7, #28] + 8004098: 0c5b lsrs r3, r3, #17 + 800409a: f003 030f and.w r3, r3, #15 + 800409e: 617b str r3, [r7, #20] + pktcnt = (temp & USB_OTG_GRXSTSP_BCNT) >> 4; + 80040a0: 69fb ldr r3, [r7, #28] + 80040a2: 091b lsrs r3, r3, #4 + 80040a4: f3c3 030a ubfx r3, r3, #0, #11 + 80040a8: 613b str r3, [r7, #16] + + switch (pktsts) + 80040aa: 697b ldr r3, [r7, #20] + 80040ac: 2b02 cmp r3, #2 + 80040ae: d003 beq.n 80040b8 + 80040b0: 2b05 cmp r3, #5 + 80040b2: f000 8082 beq.w 80041ba + break; + + case GRXSTS_PKTSTS_IN_XFER_COMP: + case GRXSTS_PKTSTS_CH_HALTED: + default: + break; + 80040b6: e083 b.n 80041c0 + if ((pktcnt > 0U) && (hhcd->hc[ch_num].xfer_buff != (void *)0)) + 80040b8: 693b ldr r3, [r7, #16] + 80040ba: 2b00 cmp r3, #0 + 80040bc: d07f beq.n 80041be + 80040be: 6879 ldr r1, [r7, #4] + 80040c0: 69ba ldr r2, [r7, #24] + 80040c2: 4613 mov r3, r2 + 80040c4: 009b lsls r3, r3, #2 + 80040c6: 4413 add r3, r2 + 80040c8: 00db lsls r3, r3, #3 + 80040ca: 440b add r3, r1 + 80040cc: 3344 adds r3, #68 ; 0x44 + 80040ce: 681b ldr r3, [r3, #0] + 80040d0: 2b00 cmp r3, #0 + 80040d2: d074 beq.n 80041be + (void)USB_ReadPacket(hhcd->Instance, hhcd->hc[ch_num].xfer_buff, (uint16_t)pktcnt); + 80040d4: 687b ldr r3, [r7, #4] + 80040d6: 6818 ldr r0, [r3, #0] + 80040d8: 6879 ldr r1, [r7, #4] + 80040da: 69ba ldr r2, [r7, #24] + 80040dc: 4613 mov r3, r2 + 80040de: 009b lsls r3, r3, #2 + 80040e0: 4413 add r3, r2 + 80040e2: 00db lsls r3, r3, #3 + 80040e4: 440b add r3, r1 + 80040e6: 3344 adds r3, #68 ; 0x44 + 80040e8: 681b ldr r3, [r3, #0] + 80040ea: 693a ldr r2, [r7, #16] + 80040ec: b292 uxth r2, r2 + 80040ee: 4619 mov r1, r3 + 80040f0: f003 f8f1 bl 80072d6 + hhcd->hc[ch_num].xfer_buff += pktcnt; + 80040f4: 6879 ldr r1, [r7, #4] + 80040f6: 69ba ldr r2, [r7, #24] + 80040f8: 4613 mov r3, r2 + 80040fa: 009b lsls r3, r3, #2 + 80040fc: 4413 add r3, r2 + 80040fe: 00db lsls r3, r3, #3 + 8004100: 440b add r3, r1 + 8004102: 3344 adds r3, #68 ; 0x44 + 8004104: 681a ldr r2, [r3, #0] + 8004106: 693b ldr r3, [r7, #16] + 8004108: 18d1 adds r1, r2, r3 + 800410a: 6878 ldr r0, [r7, #4] + 800410c: 69ba ldr r2, [r7, #24] + 800410e: 4613 mov r3, r2 + 8004110: 009b lsls r3, r3, #2 + 8004112: 4413 add r3, r2 + 8004114: 00db lsls r3, r3, #3 + 8004116: 4403 add r3, r0 + 8004118: 3344 adds r3, #68 ; 0x44 + 800411a: 6019 str r1, [r3, #0] + hhcd->hc[ch_num].xfer_count += pktcnt; + 800411c: 6879 ldr r1, [r7, #4] + 800411e: 69ba ldr r2, [r7, #24] + 8004120: 4613 mov r3, r2 + 8004122: 009b lsls r3, r3, #2 + 8004124: 4413 add r3, r2 + 8004126: 00db lsls r3, r3, #3 + 8004128: 440b add r3, r1 + 800412a: 334c adds r3, #76 ; 0x4c + 800412c: 681a ldr r2, [r3, #0] + 800412e: 693b ldr r3, [r7, #16] + 8004130: 18d1 adds r1, r2, r3 + 8004132: 6878 ldr r0, [r7, #4] + 8004134: 69ba ldr r2, [r7, #24] + 8004136: 4613 mov r3, r2 + 8004138: 009b lsls r3, r3, #2 + 800413a: 4413 add r3, r2 + 800413c: 00db lsls r3, r3, #3 + 800413e: 4403 add r3, r0 + 8004140: 334c adds r3, #76 ; 0x4c + 8004142: 6019 str r1, [r3, #0] + if ((USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0U) + 8004144: 69bb ldr r3, [r7, #24] + 8004146: 015a lsls r2, r3, #5 + 8004148: 6a3b ldr r3, [r7, #32] + 800414a: 4413 add r3, r2 + 800414c: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8004150: 691a ldr r2, [r3, #16] + 8004152: 4b1d ldr r3, [pc, #116] ; (80041c8 ) + 8004154: 4013 ands r3, r2 + 8004156: 2b00 cmp r3, #0 + 8004158: d031 beq.n 80041be + tmpreg = USBx_HC(ch_num)->HCCHAR; + 800415a: 69bb ldr r3, [r7, #24] + 800415c: 015a lsls r2, r3, #5 + 800415e: 6a3b ldr r3, [r7, #32] + 8004160: 4413 add r3, r2 + 8004162: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8004166: 681b ldr r3, [r3, #0] + 8004168: 60fb str r3, [r7, #12] + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + 800416a: 68fb ldr r3, [r7, #12] + 800416c: f023 4380 bic.w r3, r3, #1073741824 ; 0x40000000 + 8004170: 60fb str r3, [r7, #12] + tmpreg |= USB_OTG_HCCHAR_CHENA; + 8004172: 68fb ldr r3, [r7, #12] + 8004174: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 + 8004178: 60fb str r3, [r7, #12] + USBx_HC(ch_num)->HCCHAR = tmpreg; + 800417a: 69bb ldr r3, [r7, #24] + 800417c: 015a lsls r2, r3, #5 + 800417e: 6a3b ldr r3, [r7, #32] + 8004180: 4413 add r3, r2 + 8004182: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8004186: 461a mov r2, r3 + 8004188: 68fb ldr r3, [r7, #12] + 800418a: 6013 str r3, [r2, #0] + hhcd->hc[ch_num].toggle_in ^= 1U; + 800418c: 6879 ldr r1, [r7, #4] + 800418e: 69ba ldr r2, [r7, #24] + 8004190: 4613 mov r3, r2 + 8004192: 009b lsls r3, r3, #2 + 8004194: 4413 add r3, r2 + 8004196: 00db lsls r3, r3, #3 + 8004198: 440b add r3, r1 + 800419a: 3350 adds r3, #80 ; 0x50 + 800419c: 781b ldrb r3, [r3, #0] + 800419e: f083 0301 eor.w r3, r3, #1 + 80041a2: b2d8 uxtb r0, r3 + 80041a4: 6879 ldr r1, [r7, #4] + 80041a6: 69ba ldr r2, [r7, #24] + 80041a8: 4613 mov r3, r2 + 80041aa: 009b lsls r3, r3, #2 + 80041ac: 4413 add r3, r2 + 80041ae: 00db lsls r3, r3, #3 + 80041b0: 440b add r3, r1 + 80041b2: 3350 adds r3, #80 ; 0x50 + 80041b4: 4602 mov r2, r0 + 80041b6: 701a strb r2, [r3, #0] + break; + 80041b8: e001 b.n 80041be + break; + 80041ba: bf00 nop + 80041bc: e000 b.n 80041c0 + break; + 80041be: bf00 nop + } +} + 80041c0: bf00 nop + 80041c2: 3728 adds r7, #40 ; 0x28 + 80041c4: 46bd mov sp, r7 + 80041c6: bd80 pop {r7, pc} + 80041c8: 1ff80000 .word 0x1ff80000 + +080041cc : + * @brief Handle Host Port interrupt requests. + * @param hhcd HCD handle + * @retval None + */ +static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) +{ + 80041cc: b580 push {r7, lr} + 80041ce: b086 sub sp, #24 + 80041d0: af00 add r7, sp, #0 + 80041d2: 6078 str r0, [r7, #4] + USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + 80041d4: 687b ldr r3, [r7, #4] + 80041d6: 681b ldr r3, [r3, #0] + 80041d8: 617b str r3, [r7, #20] + uint32_t USBx_BASE = (uint32_t)USBx; + 80041da: 697b ldr r3, [r7, #20] + 80041dc: 613b str r3, [r7, #16] + __IO uint32_t hprt0, hprt0_dup; + + /* Handle Host Port Interrupts */ + hprt0 = USBx_HPRT0; + 80041de: 693b ldr r3, [r7, #16] + 80041e0: f503 6388 add.w r3, r3, #1088 ; 0x440 + 80041e4: 681b ldr r3, [r3, #0] + 80041e6: 60fb str r3, [r7, #12] + hprt0_dup = USBx_HPRT0; + 80041e8: 693b ldr r3, [r7, #16] + 80041ea: f503 6388 add.w r3, r3, #1088 ; 0x440 + 80041ee: 681b ldr r3, [r3, #0] + 80041f0: 60bb str r3, [r7, #8] + + hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | \ + 80041f2: 68bb ldr r3, [r7, #8] + 80041f4: f023 032e bic.w r3, r3, #46 ; 0x2e + 80041f8: 60bb str r3, [r7, #8] + USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); + + /* Check whether Port Connect detected */ + if ((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET) + 80041fa: 68fb ldr r3, [r7, #12] + 80041fc: f003 0302 and.w r3, r3, #2 + 8004200: 2b02 cmp r3, #2 + 8004202: d10b bne.n 800421c + { + if ((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS) + 8004204: 68fb ldr r3, [r7, #12] + 8004206: f003 0301 and.w r3, r3, #1 + 800420a: 2b01 cmp r3, #1 + 800420c: d102 bne.n 8004214 + { +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->ConnectCallback(hhcd); +#else + HAL_HCD_Connect_Callback(hhcd); + 800420e: 6878 ldr r0, [r7, #4] + 8004210: f005 fe4a bl 8009ea8 +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + hprt0_dup |= USB_OTG_HPRT_PCDET; + 8004214: 68bb ldr r3, [r7, #8] + 8004216: f043 0302 orr.w r3, r3, #2 + 800421a: 60bb str r3, [r7, #8] + } + + /* Check whether Port Enable Changed */ + if ((hprt0 & USB_OTG_HPRT_PENCHNG) == USB_OTG_HPRT_PENCHNG) + 800421c: 68fb ldr r3, [r7, #12] + 800421e: f003 0308 and.w r3, r3, #8 + 8004222: 2b08 cmp r3, #8 + 8004224: d132 bne.n 800428c + { + hprt0_dup |= USB_OTG_HPRT_PENCHNG; + 8004226: 68bb ldr r3, [r7, #8] + 8004228: f043 0308 orr.w r3, r3, #8 + 800422c: 60bb str r3, [r7, #8] + + if ((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA) + 800422e: 68fb ldr r3, [r7, #12] + 8004230: f003 0304 and.w r3, r3, #4 + 8004234: 2b04 cmp r3, #4 + 8004236: d126 bne.n 8004286 + { + if (hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY) + 8004238: 687b ldr r3, [r7, #4] + 800423a: 699b ldr r3, [r3, #24] + 800423c: 2b02 cmp r3, #2 + 800423e: d113 bne.n 8004268 + { + if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17)) + 8004240: 68fb ldr r3, [r7, #12] + 8004242: f403 23c0 and.w r3, r3, #393216 ; 0x60000 + 8004246: f5b3 2f80 cmp.w r3, #262144 ; 0x40000 + 800424a: d106 bne.n 800425a + { + (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_6_MHZ); + 800424c: 687b ldr r3, [r7, #4] + 800424e: 681b ldr r3, [r3, #0] + 8004250: 2102 movs r1, #2 + 8004252: 4618 mov r0, r3 + 8004254: f003 f97a bl 800754c + 8004258: e011 b.n 800427e + } + else + { + (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ); + 800425a: 687b ldr r3, [r7, #4] + 800425c: 681b ldr r3, [r3, #0] + 800425e: 2101 movs r1, #1 + 8004260: 4618 mov r0, r3 + 8004262: f003 f973 bl 800754c + 8004266: e00a b.n 800427e + } + } + else + { + if (hhcd->Init.speed == HCD_SPEED_FULL) + 8004268: 687b ldr r3, [r7, #4] + 800426a: 68db ldr r3, [r3, #12] + 800426c: 2b01 cmp r3, #1 + 800426e: d106 bne.n 800427e + { + USBx_HOST->HFIR = 60000U; + 8004270: 693b ldr r3, [r7, #16] + 8004272: f503 6380 add.w r3, r3, #1024 ; 0x400 + 8004276: 461a mov r2, r3 + 8004278: f64e 2360 movw r3, #60000 ; 0xea60 + 800427c: 6053 str r3, [r2, #4] + } + } +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->PortEnabledCallback(hhcd); +#else + HAL_HCD_PortEnabled_Callback(hhcd); + 800427e: 6878 ldr r0, [r7, #4] + 8004280: f005 fe3c bl 8009efc + 8004284: e002 b.n 800428c + else + { +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->PortDisabledCallback(hhcd); +#else + HAL_HCD_PortDisabled_Callback(hhcd); + 8004286: 6878 ldr r0, [r7, #4] + 8004288: f005 fe46 bl 8009f18 +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + } + + /* Check for an overcurrent */ + if ((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG) + 800428c: 68fb ldr r3, [r7, #12] + 800428e: f003 0320 and.w r3, r3, #32 + 8004292: 2b20 cmp r3, #32 + 8004294: d103 bne.n 800429e + { + hprt0_dup |= USB_OTG_HPRT_POCCHNG; + 8004296: 68bb ldr r3, [r7, #8] + 8004298: f043 0320 orr.w r3, r3, #32 + 800429c: 60bb str r3, [r7, #8] + } + + /* Clear Port Interrupts */ + USBx_HPRT0 = hprt0_dup; + 800429e: 693b ldr r3, [r7, #16] + 80042a0: f503 6388 add.w r3, r3, #1088 ; 0x440 + 80042a4: 461a mov r2, r3 + 80042a6: 68bb ldr r3, [r7, #8] + 80042a8: 6013 str r3, [r2, #0] +} + 80042aa: bf00 nop + 80042ac: 3718 adds r7, #24 + 80042ae: 46bd mov sp, r7 + 80042b0: bd80 pop {r7, pc} + ... + +080042b4 : + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) +{ + 80042b4: b580 push {r7, lr} + 80042b6: b084 sub sp, #16 + 80042b8: af00 add r7, sp, #0 + 80042ba: 6078 str r0, [r7, #4] + uint32_t freqrange; + uint32_t pclk1; + + /* Check the I2C handle allocation */ + if (hi2c == NULL) + 80042bc: 687b ldr r3, [r7, #4] + 80042be: 2b00 cmp r3, #0 + 80042c0: d101 bne.n 80042c6 + { + return HAL_ERROR; + 80042c2: 2301 movs r3, #1 + 80042c4: e11f b.n 8004506 + assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); + assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); + assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); + assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); + + if (hi2c->State == HAL_I2C_STATE_RESET) + 80042c6: 687b ldr r3, [r7, #4] + 80042c8: f893 303d ldrb.w r3, [r3, #61] ; 0x3d + 80042cc: b2db uxtb r3, r3 + 80042ce: 2b00 cmp r3, #0 + 80042d0: d106 bne.n 80042e0 + { + /* Allocate lock resource and initialize it */ + hi2c->Lock = HAL_UNLOCKED; + 80042d2: 687b ldr r3, [r7, #4] + 80042d4: 2200 movs r2, #0 + 80042d6: f883 203c strb.w r2, [r3, #60] ; 0x3c + + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + hi2c->MspInitCallback(hi2c); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_I2C_MspInit(hi2c); + 80042da: 6878 ldr r0, [r7, #4] + 80042dc: f7fd fa08 bl 80016f0 +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + + hi2c->State = HAL_I2C_STATE_BUSY; + 80042e0: 687b ldr r3, [r7, #4] + 80042e2: 2224 movs r2, #36 ; 0x24 + 80042e4: f883 203d strb.w r2, [r3, #61] ; 0x3d + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + 80042e8: 687b ldr r3, [r7, #4] + 80042ea: 681b ldr r3, [r3, #0] + 80042ec: 681a ldr r2, [r3, #0] + 80042ee: 687b ldr r3, [r7, #4] + 80042f0: 681b ldr r3, [r3, #0] + 80042f2: f022 0201 bic.w r2, r2, #1 + 80042f6: 601a str r2, [r3, #0] + + /*Reset I2C*/ + hi2c->Instance->CR1 |= I2C_CR1_SWRST; + 80042f8: 687b ldr r3, [r7, #4] + 80042fa: 681b ldr r3, [r3, #0] + 80042fc: 681a ldr r2, [r3, #0] + 80042fe: 687b ldr r3, [r7, #4] + 8004300: 681b ldr r3, [r3, #0] + 8004302: f442 4200 orr.w r2, r2, #32768 ; 0x8000 + 8004306: 601a str r2, [r3, #0] + hi2c->Instance->CR1 &= ~I2C_CR1_SWRST; + 8004308: 687b ldr r3, [r7, #4] + 800430a: 681b ldr r3, [r3, #0] + 800430c: 681a ldr r2, [r3, #0] + 800430e: 687b ldr r3, [r7, #4] + 8004310: 681b ldr r3, [r3, #0] + 8004312: f422 4200 bic.w r2, r2, #32768 ; 0x8000 + 8004316: 601a str r2, [r3, #0] + + /* Get PCLK1 frequency */ + pclk1 = HAL_RCC_GetPCLK1Freq(); + 8004318: f002 f830 bl 800637c + 800431c: 60f8 str r0, [r7, #12] + + /* Check the minimum allowed PCLK1 frequency */ + if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U) + 800431e: 687b ldr r3, [r7, #4] + 8004320: 685b ldr r3, [r3, #4] + 8004322: 4a7b ldr r2, [pc, #492] ; (8004510 ) + 8004324: 4293 cmp r3, r2 + 8004326: d807 bhi.n 8004338 + 8004328: 68fb ldr r3, [r7, #12] + 800432a: 4a7a ldr r2, [pc, #488] ; (8004514 ) + 800432c: 4293 cmp r3, r2 + 800432e: bf94 ite ls + 8004330: 2301 movls r3, #1 + 8004332: 2300 movhi r3, #0 + 8004334: b2db uxtb r3, r3 + 8004336: e006 b.n 8004346 + 8004338: 68fb ldr r3, [r7, #12] + 800433a: 4a77 ldr r2, [pc, #476] ; (8004518 ) + 800433c: 4293 cmp r3, r2 + 800433e: bf94 ite ls + 8004340: 2301 movls r3, #1 + 8004342: 2300 movhi r3, #0 + 8004344: b2db uxtb r3, r3 + 8004346: 2b00 cmp r3, #0 + 8004348: d001 beq.n 800434e + { + return HAL_ERROR; + 800434a: 2301 movs r3, #1 + 800434c: e0db b.n 8004506 + } + + /* Calculate frequency range */ + freqrange = I2C_FREQRANGE(pclk1); + 800434e: 68fb ldr r3, [r7, #12] + 8004350: 4a72 ldr r2, [pc, #456] ; (800451c ) + 8004352: fba2 2303 umull r2, r3, r2, r3 + 8004356: 0c9b lsrs r3, r3, #18 + 8004358: 60bb str r3, [r7, #8] + + /*---------------------------- I2Cx CR2 Configuration ----------------------*/ + /* Configure I2Cx: Frequency range */ + MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange); + 800435a: 687b ldr r3, [r7, #4] + 800435c: 681b ldr r3, [r3, #0] + 800435e: 685b ldr r3, [r3, #4] + 8004360: f023 013f bic.w r1, r3, #63 ; 0x3f + 8004364: 687b ldr r3, [r7, #4] + 8004366: 681b ldr r3, [r3, #0] + 8004368: 68ba ldr r2, [r7, #8] + 800436a: 430a orrs r2, r1 + 800436c: 605a str r2, [r3, #4] + + /*---------------------------- I2Cx TRISE Configuration --------------------*/ + /* Configure I2Cx: Rise Time */ + MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed)); + 800436e: 687b ldr r3, [r7, #4] + 8004370: 681b ldr r3, [r3, #0] + 8004372: 6a1b ldr r3, [r3, #32] + 8004374: f023 013f bic.w r1, r3, #63 ; 0x3f + 8004378: 687b ldr r3, [r7, #4] + 800437a: 685b ldr r3, [r3, #4] + 800437c: 4a64 ldr r2, [pc, #400] ; (8004510 ) + 800437e: 4293 cmp r3, r2 + 8004380: d802 bhi.n 8004388 + 8004382: 68bb ldr r3, [r7, #8] + 8004384: 3301 adds r3, #1 + 8004386: e009 b.n 800439c + 8004388: 68bb ldr r3, [r7, #8] + 800438a: f44f 7296 mov.w r2, #300 ; 0x12c + 800438e: fb02 f303 mul.w r3, r2, r3 + 8004392: 4a63 ldr r2, [pc, #396] ; (8004520 ) + 8004394: fba2 2303 umull r2, r3, r2, r3 + 8004398: 099b lsrs r3, r3, #6 + 800439a: 3301 adds r3, #1 + 800439c: 687a ldr r2, [r7, #4] + 800439e: 6812 ldr r2, [r2, #0] + 80043a0: 430b orrs r3, r1 + 80043a2: 6213 str r3, [r2, #32] + + /*---------------------------- I2Cx CCR Configuration ----------------------*/ + /* Configure I2Cx: Speed */ + MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle)); + 80043a4: 687b ldr r3, [r7, #4] + 80043a6: 681b ldr r3, [r3, #0] + 80043a8: 69db ldr r3, [r3, #28] + 80043aa: f423 424f bic.w r2, r3, #52992 ; 0xcf00 + 80043ae: f022 02ff bic.w r2, r2, #255 ; 0xff + 80043b2: 687b ldr r3, [r7, #4] + 80043b4: 685b ldr r3, [r3, #4] + 80043b6: 4956 ldr r1, [pc, #344] ; (8004510 ) + 80043b8: 428b cmp r3, r1 + 80043ba: d80d bhi.n 80043d8 + 80043bc: 68fb ldr r3, [r7, #12] + 80043be: 1e59 subs r1, r3, #1 + 80043c0: 687b ldr r3, [r7, #4] + 80043c2: 685b ldr r3, [r3, #4] + 80043c4: 005b lsls r3, r3, #1 + 80043c6: fbb1 f3f3 udiv r3, r1, r3 + 80043ca: 3301 adds r3, #1 + 80043cc: f3c3 030b ubfx r3, r3, #0, #12 + 80043d0: 2b04 cmp r3, #4 + 80043d2: bf38 it cc + 80043d4: 2304 movcc r3, #4 + 80043d6: e04f b.n 8004478 + 80043d8: 687b ldr r3, [r7, #4] + 80043da: 689b ldr r3, [r3, #8] + 80043dc: 2b00 cmp r3, #0 + 80043de: d111 bne.n 8004404 + 80043e0: 68fb ldr r3, [r7, #12] + 80043e2: 1e58 subs r0, r3, #1 + 80043e4: 687b ldr r3, [r7, #4] + 80043e6: 6859 ldr r1, [r3, #4] + 80043e8: 460b mov r3, r1 + 80043ea: 005b lsls r3, r3, #1 + 80043ec: 440b add r3, r1 + 80043ee: fbb0 f3f3 udiv r3, r0, r3 + 80043f2: 3301 adds r3, #1 + 80043f4: f3c3 030b ubfx r3, r3, #0, #12 + 80043f8: 2b00 cmp r3, #0 + 80043fa: bf0c ite eq + 80043fc: 2301 moveq r3, #1 + 80043fe: 2300 movne r3, #0 + 8004400: b2db uxtb r3, r3 + 8004402: e012 b.n 800442a + 8004404: 68fb ldr r3, [r7, #12] + 8004406: 1e58 subs r0, r3, #1 + 8004408: 687b ldr r3, [r7, #4] + 800440a: 6859 ldr r1, [r3, #4] + 800440c: 460b mov r3, r1 + 800440e: 009b lsls r3, r3, #2 + 8004410: 440b add r3, r1 + 8004412: 0099 lsls r1, r3, #2 + 8004414: 440b add r3, r1 + 8004416: fbb0 f3f3 udiv r3, r0, r3 + 800441a: 3301 adds r3, #1 + 800441c: f3c3 030b ubfx r3, r3, #0, #12 + 8004420: 2b00 cmp r3, #0 + 8004422: bf0c ite eq + 8004424: 2301 moveq r3, #1 + 8004426: 2300 movne r3, #0 + 8004428: b2db uxtb r3, r3 + 800442a: 2b00 cmp r3, #0 + 800442c: d001 beq.n 8004432 + 800442e: 2301 movs r3, #1 + 8004430: e022 b.n 8004478 + 8004432: 687b ldr r3, [r7, #4] + 8004434: 689b ldr r3, [r3, #8] + 8004436: 2b00 cmp r3, #0 + 8004438: d10e bne.n 8004458 + 800443a: 68fb ldr r3, [r7, #12] + 800443c: 1e58 subs r0, r3, #1 + 800443e: 687b ldr r3, [r7, #4] + 8004440: 6859 ldr r1, [r3, #4] + 8004442: 460b mov r3, r1 + 8004444: 005b lsls r3, r3, #1 + 8004446: 440b add r3, r1 + 8004448: fbb0 f3f3 udiv r3, r0, r3 + 800444c: 3301 adds r3, #1 + 800444e: f3c3 030b ubfx r3, r3, #0, #12 + 8004452: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 8004456: e00f b.n 8004478 + 8004458: 68fb ldr r3, [r7, #12] + 800445a: 1e58 subs r0, r3, #1 + 800445c: 687b ldr r3, [r7, #4] + 800445e: 6859 ldr r1, [r3, #4] + 8004460: 460b mov r3, r1 + 8004462: 009b lsls r3, r3, #2 + 8004464: 440b add r3, r1 + 8004466: 0099 lsls r1, r3, #2 + 8004468: 440b add r3, r1 + 800446a: fbb0 f3f3 udiv r3, r0, r3 + 800446e: 3301 adds r3, #1 + 8004470: f3c3 030b ubfx r3, r3, #0, #12 + 8004474: f443 4340 orr.w r3, r3, #49152 ; 0xc000 + 8004478: 6879 ldr r1, [r7, #4] + 800447a: 6809 ldr r1, [r1, #0] + 800447c: 4313 orrs r3, r2 + 800447e: 61cb str r3, [r1, #28] + + /*---------------------------- I2Cx CR1 Configuration ----------------------*/ + /* Configure I2Cx: Generalcall and NoStretch mode */ + MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode)); + 8004480: 687b ldr r3, [r7, #4] + 8004482: 681b ldr r3, [r3, #0] + 8004484: 681b ldr r3, [r3, #0] + 8004486: f023 01c0 bic.w r1, r3, #192 ; 0xc0 + 800448a: 687b ldr r3, [r7, #4] + 800448c: 69da ldr r2, [r3, #28] + 800448e: 687b ldr r3, [r7, #4] + 8004490: 6a1b ldr r3, [r3, #32] + 8004492: 431a orrs r2, r3 + 8004494: 687b ldr r3, [r7, #4] + 8004496: 681b ldr r3, [r3, #0] + 8004498: 430a orrs r2, r1 + 800449a: 601a str r2, [r3, #0] + + /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ + /* Configure I2Cx: Own Address1 and addressing mode */ + MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1)); + 800449c: 687b ldr r3, [r7, #4] + 800449e: 681b ldr r3, [r3, #0] + 80044a0: 689b ldr r3, [r3, #8] + 80044a2: f423 4303 bic.w r3, r3, #33536 ; 0x8300 + 80044a6: f023 03ff bic.w r3, r3, #255 ; 0xff + 80044aa: 687a ldr r2, [r7, #4] + 80044ac: 6911 ldr r1, [r2, #16] + 80044ae: 687a ldr r2, [r7, #4] + 80044b0: 68d2 ldr r2, [r2, #12] + 80044b2: 4311 orrs r1, r2 + 80044b4: 687a ldr r2, [r7, #4] + 80044b6: 6812 ldr r2, [r2, #0] + 80044b8: 430b orrs r3, r1 + 80044ba: 6093 str r3, [r2, #8] + + /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ + /* Configure I2Cx: Dual mode and Own Address2 */ + MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2)); + 80044bc: 687b ldr r3, [r7, #4] + 80044be: 681b ldr r3, [r3, #0] + 80044c0: 68db ldr r3, [r3, #12] + 80044c2: f023 01ff bic.w r1, r3, #255 ; 0xff + 80044c6: 687b ldr r3, [r7, #4] + 80044c8: 695a ldr r2, [r3, #20] + 80044ca: 687b ldr r3, [r7, #4] + 80044cc: 699b ldr r3, [r3, #24] + 80044ce: 431a orrs r2, r3 + 80044d0: 687b ldr r3, [r7, #4] + 80044d2: 681b ldr r3, [r3, #0] + 80044d4: 430a orrs r2, r1 + 80044d6: 60da str r2, [r3, #12] + + /* Enable the selected I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + 80044d8: 687b ldr r3, [r7, #4] + 80044da: 681b ldr r3, [r3, #0] + 80044dc: 681a ldr r2, [r3, #0] + 80044de: 687b ldr r3, [r7, #4] + 80044e0: 681b ldr r3, [r3, #0] + 80044e2: f042 0201 orr.w r2, r2, #1 + 80044e6: 601a str r2, [r3, #0] + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 80044e8: 687b ldr r3, [r7, #4] + 80044ea: 2200 movs r2, #0 + 80044ec: 641a str r2, [r3, #64] ; 0x40 + hi2c->State = HAL_I2C_STATE_READY; + 80044ee: 687b ldr r3, [r7, #4] + 80044f0: 2220 movs r2, #32 + 80044f2: f883 203d strb.w r2, [r3, #61] ; 0x3d + hi2c->PreviousState = I2C_STATE_NONE; + 80044f6: 687b ldr r3, [r7, #4] + 80044f8: 2200 movs r2, #0 + 80044fa: 631a str r2, [r3, #48] ; 0x30 + hi2c->Mode = HAL_I2C_MODE_NONE; + 80044fc: 687b ldr r3, [r7, #4] + 80044fe: 2200 movs r2, #0 + 8004500: f883 203e strb.w r2, [r3, #62] ; 0x3e + + return HAL_OK; + 8004504: 2300 movs r3, #0 +} + 8004506: 4618 mov r0, r3 + 8004508: 3710 adds r7, #16 + 800450a: 46bd mov sp, r7 + 800450c: bd80 pop {r7, pc} + 800450e: bf00 nop + 8004510: 000186a0 .word 0x000186a0 + 8004514: 001e847f .word 0x001e847f + 8004518: 003d08ff .word 0x003d08ff + 800451c: 431bde83 .word 0x431bde83 + 8004520: 10624dd3 .word 0x10624dd3 + +08004524 : + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + 8004524: b580 push {r7, lr} + 8004526: b088 sub sp, #32 + 8004528: af02 add r7, sp, #8 + 800452a: 60f8 str r0, [r7, #12] + 800452c: 607a str r2, [r7, #4] + 800452e: 461a mov r2, r3 + 8004530: 460b mov r3, r1 + 8004532: 817b strh r3, [r7, #10] + 8004534: 4613 mov r3, r2 + 8004536: 813b strh r3, [r7, #8] + /* Init tickstart for timeout management*/ + uint32_t tickstart = HAL_GetTick(); + 8004538: f7fd fef0 bl 800231c + 800453c: 6178 str r0, [r7, #20] + + if (hi2c->State == HAL_I2C_STATE_READY) + 800453e: 68fb ldr r3, [r7, #12] + 8004540: f893 303d ldrb.w r3, [r3, #61] ; 0x3d + 8004544: b2db uxtb r3, r3 + 8004546: 2b20 cmp r3, #32 + 8004548: f040 80e0 bne.w 800470c + { + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) + 800454c: 697b ldr r3, [r7, #20] + 800454e: 9300 str r3, [sp, #0] + 8004550: 2319 movs r3, #25 + 8004552: 2201 movs r2, #1 + 8004554: 4970 ldr r1, [pc, #448] ; (8004718 ) + 8004556: 68f8 ldr r0, [r7, #12] + 8004558: f000 fc58 bl 8004e0c + 800455c: 4603 mov r3, r0 + 800455e: 2b00 cmp r3, #0 + 8004560: d001 beq.n 8004566 + { + return HAL_BUSY; + 8004562: 2302 movs r3, #2 + 8004564: e0d3 b.n 800470e + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + 8004566: 68fb ldr r3, [r7, #12] + 8004568: f893 303c ldrb.w r3, [r3, #60] ; 0x3c + 800456c: 2b01 cmp r3, #1 + 800456e: d101 bne.n 8004574 + 8004570: 2302 movs r3, #2 + 8004572: e0cc b.n 800470e + 8004574: 68fb ldr r3, [r7, #12] + 8004576: 2201 movs r2, #1 + 8004578: f883 203c strb.w r2, [r3, #60] ; 0x3c + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + 800457c: 68fb ldr r3, [r7, #12] + 800457e: 681b ldr r3, [r3, #0] + 8004580: 681b ldr r3, [r3, #0] + 8004582: f003 0301 and.w r3, r3, #1 + 8004586: 2b01 cmp r3, #1 + 8004588: d007 beq.n 800459a + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + 800458a: 68fb ldr r3, [r7, #12] + 800458c: 681b ldr r3, [r3, #0] + 800458e: 681a ldr r2, [r3, #0] + 8004590: 68fb ldr r3, [r7, #12] + 8004592: 681b ldr r3, [r3, #0] + 8004594: f042 0201 orr.w r2, r2, #1 + 8004598: 601a str r2, [r3, #0] + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + 800459a: 68fb ldr r3, [r7, #12] + 800459c: 681b ldr r3, [r3, #0] + 800459e: 681a ldr r2, [r3, #0] + 80045a0: 68fb ldr r3, [r7, #12] + 80045a2: 681b ldr r3, [r3, #0] + 80045a4: f422 6200 bic.w r2, r2, #2048 ; 0x800 + 80045a8: 601a str r2, [r3, #0] + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + 80045aa: 68fb ldr r3, [r7, #12] + 80045ac: 2221 movs r2, #33 ; 0x21 + 80045ae: f883 203d strb.w r2, [r3, #61] ; 0x3d + hi2c->Mode = HAL_I2C_MODE_MASTER; + 80045b2: 68fb ldr r3, [r7, #12] + 80045b4: 2210 movs r2, #16 + 80045b6: f883 203e strb.w r2, [r3, #62] ; 0x3e + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 80045ba: 68fb ldr r3, [r7, #12] + 80045bc: 2200 movs r2, #0 + 80045be: 641a str r2, [r3, #64] ; 0x40 + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + 80045c0: 68fb ldr r3, [r7, #12] + 80045c2: 687a ldr r2, [r7, #4] + 80045c4: 625a str r2, [r3, #36] ; 0x24 + hi2c->XferCount = Size; + 80045c6: 68fb ldr r3, [r7, #12] + 80045c8: 893a ldrh r2, [r7, #8] + 80045ca: 855a strh r2, [r3, #42] ; 0x2a + hi2c->XferSize = hi2c->XferCount; + 80045cc: 68fb ldr r3, [r7, #12] + 80045ce: 8d5b ldrh r3, [r3, #42] ; 0x2a + 80045d0: b29a uxth r2, r3 + 80045d2: 68fb ldr r3, [r7, #12] + 80045d4: 851a strh r2, [r3, #40] ; 0x28 + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 80045d6: 68fb ldr r3, [r7, #12] + 80045d8: 4a50 ldr r2, [pc, #320] ; (800471c ) + 80045da: 62da str r2, [r3, #44] ; 0x2c + + /* Send Slave Address */ + if (I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK) + 80045dc: 8979 ldrh r1, [r7, #10] + 80045de: 697b ldr r3, [r7, #20] + 80045e0: 6a3a ldr r2, [r7, #32] + 80045e2: 68f8 ldr r0, [r7, #12] + 80045e4: f000 fac2 bl 8004b6c + 80045e8: 4603 mov r3, r0 + 80045ea: 2b00 cmp r3, #0 + 80045ec: d001 beq.n 80045f2 + { + return HAL_ERROR; + 80045ee: 2301 movs r3, #1 + 80045f0: e08d b.n 800470e + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + 80045f2: 2300 movs r3, #0 + 80045f4: 613b str r3, [r7, #16] + 80045f6: 68fb ldr r3, [r7, #12] + 80045f8: 681b ldr r3, [r3, #0] + 80045fa: 695b ldr r3, [r3, #20] + 80045fc: 613b str r3, [r7, #16] + 80045fe: 68fb ldr r3, [r7, #12] + 8004600: 681b ldr r3, [r3, #0] + 8004602: 699b ldr r3, [r3, #24] + 8004604: 613b str r3, [r7, #16] + 8004606: 693b ldr r3, [r7, #16] + + while (hi2c->XferSize > 0U) + 8004608: e066 b.n 80046d8 + { + /* Wait until TXE flag is set */ + if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + 800460a: 697a ldr r2, [r7, #20] + 800460c: 6a39 ldr r1, [r7, #32] + 800460e: 68f8 ldr r0, [r7, #12] + 8004610: f000 fcd2 bl 8004fb8 + 8004614: 4603 mov r3, r0 + 8004616: 2b00 cmp r3, #0 + 8004618: d00d beq.n 8004636 + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + 800461a: 68fb ldr r3, [r7, #12] + 800461c: 6c1b ldr r3, [r3, #64] ; 0x40 + 800461e: 2b04 cmp r3, #4 + 8004620: d107 bne.n 8004632 + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + 8004622: 68fb ldr r3, [r7, #12] + 8004624: 681b ldr r3, [r3, #0] + 8004626: 681a ldr r2, [r3, #0] + 8004628: 68fb ldr r3, [r7, #12] + 800462a: 681b ldr r3, [r3, #0] + 800462c: f442 7200 orr.w r2, r2, #512 ; 0x200 + 8004630: 601a str r2, [r3, #0] + } + return HAL_ERROR; + 8004632: 2301 movs r3, #1 + 8004634: e06b b.n 800470e + } + + /* Write data to DR */ + hi2c->Instance->DR = *hi2c->pBuffPtr; + 8004636: 68fb ldr r3, [r7, #12] + 8004638: 6a5b ldr r3, [r3, #36] ; 0x24 + 800463a: 781a ldrb r2, [r3, #0] + 800463c: 68fb ldr r3, [r7, #12] + 800463e: 681b ldr r3, [r3, #0] + 8004640: 611a str r2, [r3, #16] + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + 8004642: 68fb ldr r3, [r7, #12] + 8004644: 6a5b ldr r3, [r3, #36] ; 0x24 + 8004646: 1c5a adds r2, r3, #1 + 8004648: 68fb ldr r3, [r7, #12] + 800464a: 625a str r2, [r3, #36] ; 0x24 + + /* Update counter */ + hi2c->XferCount--; + 800464c: 68fb ldr r3, [r7, #12] + 800464e: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8004650: b29b uxth r3, r3 + 8004652: 3b01 subs r3, #1 + 8004654: b29a uxth r2, r3 + 8004656: 68fb ldr r3, [r7, #12] + 8004658: 855a strh r2, [r3, #42] ; 0x2a + hi2c->XferSize--; + 800465a: 68fb ldr r3, [r7, #12] + 800465c: 8d1b ldrh r3, [r3, #40] ; 0x28 + 800465e: 3b01 subs r3, #1 + 8004660: b29a uxth r2, r3 + 8004662: 68fb ldr r3, [r7, #12] + 8004664: 851a strh r2, [r3, #40] ; 0x28 + + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) + 8004666: 68fb ldr r3, [r7, #12] + 8004668: 681b ldr r3, [r3, #0] + 800466a: 695b ldr r3, [r3, #20] + 800466c: f003 0304 and.w r3, r3, #4 + 8004670: 2b04 cmp r3, #4 + 8004672: d11b bne.n 80046ac + 8004674: 68fb ldr r3, [r7, #12] + 8004676: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8004678: 2b00 cmp r3, #0 + 800467a: d017 beq.n 80046ac + { + /* Write data to DR */ + hi2c->Instance->DR = *hi2c->pBuffPtr; + 800467c: 68fb ldr r3, [r7, #12] + 800467e: 6a5b ldr r3, [r3, #36] ; 0x24 + 8004680: 781a ldrb r2, [r3, #0] + 8004682: 68fb ldr r3, [r7, #12] + 8004684: 681b ldr r3, [r3, #0] + 8004686: 611a str r2, [r3, #16] + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + 8004688: 68fb ldr r3, [r7, #12] + 800468a: 6a5b ldr r3, [r3, #36] ; 0x24 + 800468c: 1c5a adds r2, r3, #1 + 800468e: 68fb ldr r3, [r7, #12] + 8004690: 625a str r2, [r3, #36] ; 0x24 + + /* Update counter */ + hi2c->XferCount--; + 8004692: 68fb ldr r3, [r7, #12] + 8004694: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8004696: b29b uxth r3, r3 + 8004698: 3b01 subs r3, #1 + 800469a: b29a uxth r2, r3 + 800469c: 68fb ldr r3, [r7, #12] + 800469e: 855a strh r2, [r3, #42] ; 0x2a + hi2c->XferSize--; + 80046a0: 68fb ldr r3, [r7, #12] + 80046a2: 8d1b ldrh r3, [r3, #40] ; 0x28 + 80046a4: 3b01 subs r3, #1 + 80046a6: b29a uxth r2, r3 + 80046a8: 68fb ldr r3, [r7, #12] + 80046aa: 851a strh r2, [r3, #40] ; 0x28 + } + + /* Wait until BTF flag is set */ + if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + 80046ac: 697a ldr r2, [r7, #20] + 80046ae: 6a39 ldr r1, [r7, #32] + 80046b0: 68f8 ldr r0, [r7, #12] + 80046b2: f000 fcc2 bl 800503a + 80046b6: 4603 mov r3, r0 + 80046b8: 2b00 cmp r3, #0 + 80046ba: d00d beq.n 80046d8 + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + 80046bc: 68fb ldr r3, [r7, #12] + 80046be: 6c1b ldr r3, [r3, #64] ; 0x40 + 80046c0: 2b04 cmp r3, #4 + 80046c2: d107 bne.n 80046d4 + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + 80046c4: 68fb ldr r3, [r7, #12] + 80046c6: 681b ldr r3, [r3, #0] + 80046c8: 681a ldr r2, [r3, #0] + 80046ca: 68fb ldr r3, [r7, #12] + 80046cc: 681b ldr r3, [r3, #0] + 80046ce: f442 7200 orr.w r2, r2, #512 ; 0x200 + 80046d2: 601a str r2, [r3, #0] + } + return HAL_ERROR; + 80046d4: 2301 movs r3, #1 + 80046d6: e01a b.n 800470e + while (hi2c->XferSize > 0U) + 80046d8: 68fb ldr r3, [r7, #12] + 80046da: 8d1b ldrh r3, [r3, #40] ; 0x28 + 80046dc: 2b00 cmp r3, #0 + 80046de: d194 bne.n 800460a + } + } + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + 80046e0: 68fb ldr r3, [r7, #12] + 80046e2: 681b ldr r3, [r3, #0] + 80046e4: 681a ldr r2, [r3, #0] + 80046e6: 68fb ldr r3, [r7, #12] + 80046e8: 681b ldr r3, [r3, #0] + 80046ea: f442 7200 orr.w r2, r2, #512 ; 0x200 + 80046ee: 601a str r2, [r3, #0] + + hi2c->State = HAL_I2C_STATE_READY; + 80046f0: 68fb ldr r3, [r7, #12] + 80046f2: 2220 movs r2, #32 + 80046f4: f883 203d strb.w r2, [r3, #61] ; 0x3d + hi2c->Mode = HAL_I2C_MODE_NONE; + 80046f8: 68fb ldr r3, [r7, #12] + 80046fa: 2200 movs r2, #0 + 80046fc: f883 203e strb.w r2, [r3, #62] ; 0x3e + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 8004700: 68fb ldr r3, [r7, #12] + 8004702: 2200 movs r2, #0 + 8004704: f883 203c strb.w r2, [r3, #60] ; 0x3c + + return HAL_OK; + 8004708: 2300 movs r3, #0 + 800470a: e000 b.n 800470e + } + else + { + return HAL_BUSY; + 800470c: 2302 movs r3, #2 + } +} + 800470e: 4618 mov r0, r3 + 8004710: 3718 adds r7, #24 + 8004712: 46bd mov sp, r7 + 8004714: bd80 pop {r7, pc} + 8004716: bf00 nop + 8004718: 00100002 .word 0x00100002 + 800471c: ffff0000 .word 0xffff0000 + +08004720 : + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + 8004720: b580 push {r7, lr} + 8004722: b08c sub sp, #48 ; 0x30 + 8004724: af02 add r7, sp, #8 + 8004726: 60f8 str r0, [r7, #12] + 8004728: 607a str r2, [r7, #4] + 800472a: 461a mov r2, r3 + 800472c: 460b mov r3, r1 + 800472e: 817b strh r3, [r7, #10] + 8004730: 4613 mov r3, r2 + 8004732: 813b strh r3, [r7, #8] + /* Init tickstart for timeout management*/ + uint32_t tickstart = HAL_GetTick(); + 8004734: f7fd fdf2 bl 800231c + 8004738: 6278 str r0, [r7, #36] ; 0x24 + + if (hi2c->State == HAL_I2C_STATE_READY) + 800473a: 68fb ldr r3, [r7, #12] + 800473c: f893 303d ldrb.w r3, [r3, #61] ; 0x3d + 8004740: b2db uxtb r3, r3 + 8004742: 2b20 cmp r3, #32 + 8004744: f040 820b bne.w 8004b5e + { + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) + 8004748: 6a7b ldr r3, [r7, #36] ; 0x24 + 800474a: 9300 str r3, [sp, #0] + 800474c: 2319 movs r3, #25 + 800474e: 2201 movs r2, #1 + 8004750: 497c ldr r1, [pc, #496] ; (8004944 ) + 8004752: 68f8 ldr r0, [r7, #12] + 8004754: f000 fb5a bl 8004e0c + 8004758: 4603 mov r3, r0 + 800475a: 2b00 cmp r3, #0 + 800475c: d001 beq.n 8004762 + { + return HAL_BUSY; + 800475e: 2302 movs r3, #2 + 8004760: e1fe b.n 8004b60 + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + 8004762: 68fb ldr r3, [r7, #12] + 8004764: f893 303c ldrb.w r3, [r3, #60] ; 0x3c + 8004768: 2b01 cmp r3, #1 + 800476a: d101 bne.n 8004770 + 800476c: 2302 movs r3, #2 + 800476e: e1f7 b.n 8004b60 + 8004770: 68fb ldr r3, [r7, #12] + 8004772: 2201 movs r2, #1 + 8004774: f883 203c strb.w r2, [r3, #60] ; 0x3c + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + 8004778: 68fb ldr r3, [r7, #12] + 800477a: 681b ldr r3, [r3, #0] + 800477c: 681b ldr r3, [r3, #0] + 800477e: f003 0301 and.w r3, r3, #1 + 8004782: 2b01 cmp r3, #1 + 8004784: d007 beq.n 8004796 + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + 8004786: 68fb ldr r3, [r7, #12] + 8004788: 681b ldr r3, [r3, #0] + 800478a: 681a ldr r2, [r3, #0] + 800478c: 68fb ldr r3, [r7, #12] + 800478e: 681b ldr r3, [r3, #0] + 8004790: f042 0201 orr.w r2, r2, #1 + 8004794: 601a str r2, [r3, #0] + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + 8004796: 68fb ldr r3, [r7, #12] + 8004798: 681b ldr r3, [r3, #0] + 800479a: 681a ldr r2, [r3, #0] + 800479c: 68fb ldr r3, [r7, #12] + 800479e: 681b ldr r3, [r3, #0] + 80047a0: f422 6200 bic.w r2, r2, #2048 ; 0x800 + 80047a4: 601a str r2, [r3, #0] + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + 80047a6: 68fb ldr r3, [r7, #12] + 80047a8: 2222 movs r2, #34 ; 0x22 + 80047aa: f883 203d strb.w r2, [r3, #61] ; 0x3d + hi2c->Mode = HAL_I2C_MODE_MASTER; + 80047ae: 68fb ldr r3, [r7, #12] + 80047b0: 2210 movs r2, #16 + 80047b2: f883 203e strb.w r2, [r3, #62] ; 0x3e + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 80047b6: 68fb ldr r3, [r7, #12] + 80047b8: 2200 movs r2, #0 + 80047ba: 641a str r2, [r3, #64] ; 0x40 + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + 80047bc: 68fb ldr r3, [r7, #12] + 80047be: 687a ldr r2, [r7, #4] + 80047c0: 625a str r2, [r3, #36] ; 0x24 + hi2c->XferCount = Size; + 80047c2: 68fb ldr r3, [r7, #12] + 80047c4: 893a ldrh r2, [r7, #8] + 80047c6: 855a strh r2, [r3, #42] ; 0x2a + hi2c->XferSize = hi2c->XferCount; + 80047c8: 68fb ldr r3, [r7, #12] + 80047ca: 8d5b ldrh r3, [r3, #42] ; 0x2a + 80047cc: b29a uxth r2, r3 + 80047ce: 68fb ldr r3, [r7, #12] + 80047d0: 851a strh r2, [r3, #40] ; 0x28 + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 80047d2: 68fb ldr r3, [r7, #12] + 80047d4: 4a5c ldr r2, [pc, #368] ; (8004948 ) + 80047d6: 62da str r2, [r3, #44] ; 0x2c + + /* Send Slave Address */ + if (I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK) + 80047d8: 8979 ldrh r1, [r7, #10] + 80047da: 6a7b ldr r3, [r7, #36] ; 0x24 + 80047dc: 6b3a ldr r2, [r7, #48] ; 0x30 + 80047de: 68f8 ldr r0, [r7, #12] + 80047e0: f000 fa46 bl 8004c70 + 80047e4: 4603 mov r3, r0 + 80047e6: 2b00 cmp r3, #0 + 80047e8: d001 beq.n 80047ee + { + return HAL_ERROR; + 80047ea: 2301 movs r3, #1 + 80047ec: e1b8 b.n 8004b60 + } + + if (hi2c->XferSize == 0U) + 80047ee: 68fb ldr r3, [r7, #12] + 80047f0: 8d1b ldrh r3, [r3, #40] ; 0x28 + 80047f2: 2b00 cmp r3, #0 + 80047f4: d113 bne.n 800481e + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + 80047f6: 2300 movs r3, #0 + 80047f8: 623b str r3, [r7, #32] + 80047fa: 68fb ldr r3, [r7, #12] + 80047fc: 681b ldr r3, [r3, #0] + 80047fe: 695b ldr r3, [r3, #20] + 8004800: 623b str r3, [r7, #32] + 8004802: 68fb ldr r3, [r7, #12] + 8004804: 681b ldr r3, [r3, #0] + 8004806: 699b ldr r3, [r3, #24] + 8004808: 623b str r3, [r7, #32] + 800480a: 6a3b ldr r3, [r7, #32] + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + 800480c: 68fb ldr r3, [r7, #12] + 800480e: 681b ldr r3, [r3, #0] + 8004810: 681a ldr r2, [r3, #0] + 8004812: 68fb ldr r3, [r7, #12] + 8004814: 681b ldr r3, [r3, #0] + 8004816: f442 7200 orr.w r2, r2, #512 ; 0x200 + 800481a: 601a str r2, [r3, #0] + 800481c: e18c b.n 8004b38 + } + else if (hi2c->XferSize == 1U) + 800481e: 68fb ldr r3, [r7, #12] + 8004820: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8004822: 2b01 cmp r3, #1 + 8004824: d11b bne.n 800485e + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + 8004826: 68fb ldr r3, [r7, #12] + 8004828: 681b ldr r3, [r3, #0] + 800482a: 681a ldr r2, [r3, #0] + 800482c: 68fb ldr r3, [r7, #12] + 800482e: 681b ldr r3, [r3, #0] + 8004830: f422 6280 bic.w r2, r2, #1024 ; 0x400 + 8004834: 601a str r2, [r3, #0] + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + 8004836: 2300 movs r3, #0 + 8004838: 61fb str r3, [r7, #28] + 800483a: 68fb ldr r3, [r7, #12] + 800483c: 681b ldr r3, [r3, #0] + 800483e: 695b ldr r3, [r3, #20] + 8004840: 61fb str r3, [r7, #28] + 8004842: 68fb ldr r3, [r7, #12] + 8004844: 681b ldr r3, [r3, #0] + 8004846: 699b ldr r3, [r3, #24] + 8004848: 61fb str r3, [r7, #28] + 800484a: 69fb ldr r3, [r7, #28] + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + 800484c: 68fb ldr r3, [r7, #12] + 800484e: 681b ldr r3, [r3, #0] + 8004850: 681a ldr r2, [r3, #0] + 8004852: 68fb ldr r3, [r7, #12] + 8004854: 681b ldr r3, [r3, #0] + 8004856: f442 7200 orr.w r2, r2, #512 ; 0x200 + 800485a: 601a str r2, [r3, #0] + 800485c: e16c b.n 8004b38 + } + else if (hi2c->XferSize == 2U) + 800485e: 68fb ldr r3, [r7, #12] + 8004860: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8004862: 2b02 cmp r3, #2 + 8004864: d11b bne.n 800489e + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + 8004866: 68fb ldr r3, [r7, #12] + 8004868: 681b ldr r3, [r3, #0] + 800486a: 681a ldr r2, [r3, #0] + 800486c: 68fb ldr r3, [r7, #12] + 800486e: 681b ldr r3, [r3, #0] + 8004870: f422 6280 bic.w r2, r2, #1024 ; 0x400 + 8004874: 601a str r2, [r3, #0] + + /* Enable Pos */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + 8004876: 68fb ldr r3, [r7, #12] + 8004878: 681b ldr r3, [r3, #0] + 800487a: 681a ldr r2, [r3, #0] + 800487c: 68fb ldr r3, [r7, #12] + 800487e: 681b ldr r3, [r3, #0] + 8004880: f442 6200 orr.w r2, r2, #2048 ; 0x800 + 8004884: 601a str r2, [r3, #0] + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + 8004886: 2300 movs r3, #0 + 8004888: 61bb str r3, [r7, #24] + 800488a: 68fb ldr r3, [r7, #12] + 800488c: 681b ldr r3, [r3, #0] + 800488e: 695b ldr r3, [r3, #20] + 8004890: 61bb str r3, [r7, #24] + 8004892: 68fb ldr r3, [r7, #12] + 8004894: 681b ldr r3, [r3, #0] + 8004896: 699b ldr r3, [r3, #24] + 8004898: 61bb str r3, [r7, #24] + 800489a: 69bb ldr r3, [r7, #24] + 800489c: e14c b.n 8004b38 + } + else + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + 800489e: 68fb ldr r3, [r7, #12] + 80048a0: 681b ldr r3, [r3, #0] + 80048a2: 681a ldr r2, [r3, #0] + 80048a4: 68fb ldr r3, [r7, #12] + 80048a6: 681b ldr r3, [r3, #0] + 80048a8: f442 6280 orr.w r2, r2, #1024 ; 0x400 + 80048ac: 601a str r2, [r3, #0] + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + 80048ae: 2300 movs r3, #0 + 80048b0: 617b str r3, [r7, #20] + 80048b2: 68fb ldr r3, [r7, #12] + 80048b4: 681b ldr r3, [r3, #0] + 80048b6: 695b ldr r3, [r3, #20] + 80048b8: 617b str r3, [r7, #20] + 80048ba: 68fb ldr r3, [r7, #12] + 80048bc: 681b ldr r3, [r3, #0] + 80048be: 699b ldr r3, [r3, #24] + 80048c0: 617b str r3, [r7, #20] + 80048c2: 697b ldr r3, [r7, #20] + } + + while (hi2c->XferSize > 0U) + 80048c4: e138 b.n 8004b38 + { + if (hi2c->XferSize <= 3U) + 80048c6: 68fb ldr r3, [r7, #12] + 80048c8: 8d1b ldrh r3, [r3, #40] ; 0x28 + 80048ca: 2b03 cmp r3, #3 + 80048cc: f200 80f1 bhi.w 8004ab2 + { + /* One byte */ + if (hi2c->XferSize == 1U) + 80048d0: 68fb ldr r3, [r7, #12] + 80048d2: 8d1b ldrh r3, [r3, #40] ; 0x28 + 80048d4: 2b01 cmp r3, #1 + 80048d6: d123 bne.n 8004920 + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + 80048d8: 6a7a ldr r2, [r7, #36] ; 0x24 + 80048da: 6b39 ldr r1, [r7, #48] ; 0x30 + 80048dc: 68f8 ldr r0, [r7, #12] + 80048de: f000 fbed bl 80050bc + 80048e2: 4603 mov r3, r0 + 80048e4: 2b00 cmp r3, #0 + 80048e6: d001 beq.n 80048ec + { + return HAL_ERROR; + 80048e8: 2301 movs r3, #1 + 80048ea: e139 b.n 8004b60 + } + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + 80048ec: 68fb ldr r3, [r7, #12] + 80048ee: 681b ldr r3, [r3, #0] + 80048f0: 691a ldr r2, [r3, #16] + 80048f2: 68fb ldr r3, [r7, #12] + 80048f4: 6a5b ldr r3, [r3, #36] ; 0x24 + 80048f6: b2d2 uxtb r2, r2 + 80048f8: 701a strb r2, [r3, #0] + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + 80048fa: 68fb ldr r3, [r7, #12] + 80048fc: 6a5b ldr r3, [r3, #36] ; 0x24 + 80048fe: 1c5a adds r2, r3, #1 + 8004900: 68fb ldr r3, [r7, #12] + 8004902: 625a str r2, [r3, #36] ; 0x24 + + /* Update counter */ + hi2c->XferSize--; + 8004904: 68fb ldr r3, [r7, #12] + 8004906: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8004908: 3b01 subs r3, #1 + 800490a: b29a uxth r2, r3 + 800490c: 68fb ldr r3, [r7, #12] + 800490e: 851a strh r2, [r3, #40] ; 0x28 + hi2c->XferCount--; + 8004910: 68fb ldr r3, [r7, #12] + 8004912: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8004914: b29b uxth r3, r3 + 8004916: 3b01 subs r3, #1 + 8004918: b29a uxth r2, r3 + 800491a: 68fb ldr r3, [r7, #12] + 800491c: 855a strh r2, [r3, #42] ; 0x2a + 800491e: e10b b.n 8004b38 + } + /* Two bytes */ + else if (hi2c->XferSize == 2U) + 8004920: 68fb ldr r3, [r7, #12] + 8004922: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8004924: 2b02 cmp r3, #2 + 8004926: d14e bne.n 80049c6 + { + /* Wait until BTF flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) + 8004928: 6a7b ldr r3, [r7, #36] ; 0x24 + 800492a: 9300 str r3, [sp, #0] + 800492c: 6b3b ldr r3, [r7, #48] ; 0x30 + 800492e: 2200 movs r2, #0 + 8004930: 4906 ldr r1, [pc, #24] ; (800494c ) + 8004932: 68f8 ldr r0, [r7, #12] + 8004934: f000 fa6a bl 8004e0c + 8004938: 4603 mov r3, r0 + 800493a: 2b00 cmp r3, #0 + 800493c: d008 beq.n 8004950 + { + return HAL_ERROR; + 800493e: 2301 movs r3, #1 + 8004940: e10e b.n 8004b60 + 8004942: bf00 nop + 8004944: 00100002 .word 0x00100002 + 8004948: ffff0000 .word 0xffff0000 + 800494c: 00010004 .word 0x00010004 + } + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + 8004950: 68fb ldr r3, [r7, #12] + 8004952: 681b ldr r3, [r3, #0] + 8004954: 681a ldr r2, [r3, #0] + 8004956: 68fb ldr r3, [r7, #12] + 8004958: 681b ldr r3, [r3, #0] + 800495a: f442 7200 orr.w r2, r2, #512 ; 0x200 + 800495e: 601a str r2, [r3, #0] + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + 8004960: 68fb ldr r3, [r7, #12] + 8004962: 681b ldr r3, [r3, #0] + 8004964: 691a ldr r2, [r3, #16] + 8004966: 68fb ldr r3, [r7, #12] + 8004968: 6a5b ldr r3, [r3, #36] ; 0x24 + 800496a: b2d2 uxtb r2, r2 + 800496c: 701a strb r2, [r3, #0] + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + 800496e: 68fb ldr r3, [r7, #12] + 8004970: 6a5b ldr r3, [r3, #36] ; 0x24 + 8004972: 1c5a adds r2, r3, #1 + 8004974: 68fb ldr r3, [r7, #12] + 8004976: 625a str r2, [r3, #36] ; 0x24 + + /* Update counter */ + hi2c->XferSize--; + 8004978: 68fb ldr r3, [r7, #12] + 800497a: 8d1b ldrh r3, [r3, #40] ; 0x28 + 800497c: 3b01 subs r3, #1 + 800497e: b29a uxth r2, r3 + 8004980: 68fb ldr r3, [r7, #12] + 8004982: 851a strh r2, [r3, #40] ; 0x28 + hi2c->XferCount--; + 8004984: 68fb ldr r3, [r7, #12] + 8004986: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8004988: b29b uxth r3, r3 + 800498a: 3b01 subs r3, #1 + 800498c: b29a uxth r2, r3 + 800498e: 68fb ldr r3, [r7, #12] + 8004990: 855a strh r2, [r3, #42] ; 0x2a + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + 8004992: 68fb ldr r3, [r7, #12] + 8004994: 681b ldr r3, [r3, #0] + 8004996: 691a ldr r2, [r3, #16] + 8004998: 68fb ldr r3, [r7, #12] + 800499a: 6a5b ldr r3, [r3, #36] ; 0x24 + 800499c: b2d2 uxtb r2, r2 + 800499e: 701a strb r2, [r3, #0] + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + 80049a0: 68fb ldr r3, [r7, #12] + 80049a2: 6a5b ldr r3, [r3, #36] ; 0x24 + 80049a4: 1c5a adds r2, r3, #1 + 80049a6: 68fb ldr r3, [r7, #12] + 80049a8: 625a str r2, [r3, #36] ; 0x24 + + /* Update counter */ + hi2c->XferSize--; + 80049aa: 68fb ldr r3, [r7, #12] + 80049ac: 8d1b ldrh r3, [r3, #40] ; 0x28 + 80049ae: 3b01 subs r3, #1 + 80049b0: b29a uxth r2, r3 + 80049b2: 68fb ldr r3, [r7, #12] + 80049b4: 851a strh r2, [r3, #40] ; 0x28 + hi2c->XferCount--; + 80049b6: 68fb ldr r3, [r7, #12] + 80049b8: 8d5b ldrh r3, [r3, #42] ; 0x2a + 80049ba: b29b uxth r3, r3 + 80049bc: 3b01 subs r3, #1 + 80049be: b29a uxth r2, r3 + 80049c0: 68fb ldr r3, [r7, #12] + 80049c2: 855a strh r2, [r3, #42] ; 0x2a + 80049c4: e0b8 b.n 8004b38 + } + /* 3 Last bytes */ + else + { + /* Wait until BTF flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) + 80049c6: 6a7b ldr r3, [r7, #36] ; 0x24 + 80049c8: 9300 str r3, [sp, #0] + 80049ca: 6b3b ldr r3, [r7, #48] ; 0x30 + 80049cc: 2200 movs r2, #0 + 80049ce: 4966 ldr r1, [pc, #408] ; (8004b68 ) + 80049d0: 68f8 ldr r0, [r7, #12] + 80049d2: f000 fa1b bl 8004e0c + 80049d6: 4603 mov r3, r0 + 80049d8: 2b00 cmp r3, #0 + 80049da: d001 beq.n 80049e0 + { + return HAL_ERROR; + 80049dc: 2301 movs r3, #1 + 80049de: e0bf b.n 8004b60 + } + + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + 80049e0: 68fb ldr r3, [r7, #12] + 80049e2: 681b ldr r3, [r3, #0] + 80049e4: 681a ldr r2, [r3, #0] + 80049e6: 68fb ldr r3, [r7, #12] + 80049e8: 681b ldr r3, [r3, #0] + 80049ea: f422 6280 bic.w r2, r2, #1024 ; 0x400 + 80049ee: 601a str r2, [r3, #0] + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + 80049f0: 68fb ldr r3, [r7, #12] + 80049f2: 681b ldr r3, [r3, #0] + 80049f4: 691a ldr r2, [r3, #16] + 80049f6: 68fb ldr r3, [r7, #12] + 80049f8: 6a5b ldr r3, [r3, #36] ; 0x24 + 80049fa: b2d2 uxtb r2, r2 + 80049fc: 701a strb r2, [r3, #0] + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + 80049fe: 68fb ldr r3, [r7, #12] + 8004a00: 6a5b ldr r3, [r3, #36] ; 0x24 + 8004a02: 1c5a adds r2, r3, #1 + 8004a04: 68fb ldr r3, [r7, #12] + 8004a06: 625a str r2, [r3, #36] ; 0x24 + + /* Update counter */ + hi2c->XferSize--; + 8004a08: 68fb ldr r3, [r7, #12] + 8004a0a: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8004a0c: 3b01 subs r3, #1 + 8004a0e: b29a uxth r2, r3 + 8004a10: 68fb ldr r3, [r7, #12] + 8004a12: 851a strh r2, [r3, #40] ; 0x28 + hi2c->XferCount--; + 8004a14: 68fb ldr r3, [r7, #12] + 8004a16: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8004a18: b29b uxth r3, r3 + 8004a1a: 3b01 subs r3, #1 + 8004a1c: b29a uxth r2, r3 + 8004a1e: 68fb ldr r3, [r7, #12] + 8004a20: 855a strh r2, [r3, #42] ; 0x2a + + /* Wait until BTF flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) + 8004a22: 6a7b ldr r3, [r7, #36] ; 0x24 + 8004a24: 9300 str r3, [sp, #0] + 8004a26: 6b3b ldr r3, [r7, #48] ; 0x30 + 8004a28: 2200 movs r2, #0 + 8004a2a: 494f ldr r1, [pc, #316] ; (8004b68 ) + 8004a2c: 68f8 ldr r0, [r7, #12] + 8004a2e: f000 f9ed bl 8004e0c + 8004a32: 4603 mov r3, r0 + 8004a34: 2b00 cmp r3, #0 + 8004a36: d001 beq.n 8004a3c + { + return HAL_ERROR; + 8004a38: 2301 movs r3, #1 + 8004a3a: e091 b.n 8004b60 + } + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + 8004a3c: 68fb ldr r3, [r7, #12] + 8004a3e: 681b ldr r3, [r3, #0] + 8004a40: 681a ldr r2, [r3, #0] + 8004a42: 68fb ldr r3, [r7, #12] + 8004a44: 681b ldr r3, [r3, #0] + 8004a46: f442 7200 orr.w r2, r2, #512 ; 0x200 + 8004a4a: 601a str r2, [r3, #0] + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + 8004a4c: 68fb ldr r3, [r7, #12] + 8004a4e: 681b ldr r3, [r3, #0] + 8004a50: 691a ldr r2, [r3, #16] + 8004a52: 68fb ldr r3, [r7, #12] + 8004a54: 6a5b ldr r3, [r3, #36] ; 0x24 + 8004a56: b2d2 uxtb r2, r2 + 8004a58: 701a strb r2, [r3, #0] + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + 8004a5a: 68fb ldr r3, [r7, #12] + 8004a5c: 6a5b ldr r3, [r3, #36] ; 0x24 + 8004a5e: 1c5a adds r2, r3, #1 + 8004a60: 68fb ldr r3, [r7, #12] + 8004a62: 625a str r2, [r3, #36] ; 0x24 + + /* Update counter */ + hi2c->XferSize--; + 8004a64: 68fb ldr r3, [r7, #12] + 8004a66: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8004a68: 3b01 subs r3, #1 + 8004a6a: b29a uxth r2, r3 + 8004a6c: 68fb ldr r3, [r7, #12] + 8004a6e: 851a strh r2, [r3, #40] ; 0x28 + hi2c->XferCount--; + 8004a70: 68fb ldr r3, [r7, #12] + 8004a72: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8004a74: b29b uxth r3, r3 + 8004a76: 3b01 subs r3, #1 + 8004a78: b29a uxth r2, r3 + 8004a7a: 68fb ldr r3, [r7, #12] + 8004a7c: 855a strh r2, [r3, #42] ; 0x2a + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + 8004a7e: 68fb ldr r3, [r7, #12] + 8004a80: 681b ldr r3, [r3, #0] + 8004a82: 691a ldr r2, [r3, #16] + 8004a84: 68fb ldr r3, [r7, #12] + 8004a86: 6a5b ldr r3, [r3, #36] ; 0x24 + 8004a88: b2d2 uxtb r2, r2 + 8004a8a: 701a strb r2, [r3, #0] + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + 8004a8c: 68fb ldr r3, [r7, #12] + 8004a8e: 6a5b ldr r3, [r3, #36] ; 0x24 + 8004a90: 1c5a adds r2, r3, #1 + 8004a92: 68fb ldr r3, [r7, #12] + 8004a94: 625a str r2, [r3, #36] ; 0x24 + + /* Update counter */ + hi2c->XferSize--; + 8004a96: 68fb ldr r3, [r7, #12] + 8004a98: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8004a9a: 3b01 subs r3, #1 + 8004a9c: b29a uxth r2, r3 + 8004a9e: 68fb ldr r3, [r7, #12] + 8004aa0: 851a strh r2, [r3, #40] ; 0x28 + hi2c->XferCount--; + 8004aa2: 68fb ldr r3, [r7, #12] + 8004aa4: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8004aa6: b29b uxth r3, r3 + 8004aa8: 3b01 subs r3, #1 + 8004aaa: b29a uxth r2, r3 + 8004aac: 68fb ldr r3, [r7, #12] + 8004aae: 855a strh r2, [r3, #42] ; 0x2a + 8004ab0: e042 b.n 8004b38 + } + } + else + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + 8004ab2: 6a7a ldr r2, [r7, #36] ; 0x24 + 8004ab4: 6b39 ldr r1, [r7, #48] ; 0x30 + 8004ab6: 68f8 ldr r0, [r7, #12] + 8004ab8: f000 fb00 bl 80050bc + 8004abc: 4603 mov r3, r0 + 8004abe: 2b00 cmp r3, #0 + 8004ac0: d001 beq.n 8004ac6 + { + return HAL_ERROR; + 8004ac2: 2301 movs r3, #1 + 8004ac4: e04c b.n 8004b60 + } + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + 8004ac6: 68fb ldr r3, [r7, #12] + 8004ac8: 681b ldr r3, [r3, #0] + 8004aca: 691a ldr r2, [r3, #16] + 8004acc: 68fb ldr r3, [r7, #12] + 8004ace: 6a5b ldr r3, [r3, #36] ; 0x24 + 8004ad0: b2d2 uxtb r2, r2 + 8004ad2: 701a strb r2, [r3, #0] + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + 8004ad4: 68fb ldr r3, [r7, #12] + 8004ad6: 6a5b ldr r3, [r3, #36] ; 0x24 + 8004ad8: 1c5a adds r2, r3, #1 + 8004ada: 68fb ldr r3, [r7, #12] + 8004adc: 625a str r2, [r3, #36] ; 0x24 + + /* Update counter */ + hi2c->XferSize--; + 8004ade: 68fb ldr r3, [r7, #12] + 8004ae0: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8004ae2: 3b01 subs r3, #1 + 8004ae4: b29a uxth r2, r3 + 8004ae6: 68fb ldr r3, [r7, #12] + 8004ae8: 851a strh r2, [r3, #40] ; 0x28 + hi2c->XferCount--; + 8004aea: 68fb ldr r3, [r7, #12] + 8004aec: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8004aee: b29b uxth r3, r3 + 8004af0: 3b01 subs r3, #1 + 8004af2: b29a uxth r2, r3 + 8004af4: 68fb ldr r3, [r7, #12] + 8004af6: 855a strh r2, [r3, #42] ; 0x2a + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) + 8004af8: 68fb ldr r3, [r7, #12] + 8004afa: 681b ldr r3, [r3, #0] + 8004afc: 695b ldr r3, [r3, #20] + 8004afe: f003 0304 and.w r3, r3, #4 + 8004b02: 2b04 cmp r3, #4 + 8004b04: d118 bne.n 8004b38 + { + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + 8004b06: 68fb ldr r3, [r7, #12] + 8004b08: 681b ldr r3, [r3, #0] + 8004b0a: 691a ldr r2, [r3, #16] + 8004b0c: 68fb ldr r3, [r7, #12] + 8004b0e: 6a5b ldr r3, [r3, #36] ; 0x24 + 8004b10: b2d2 uxtb r2, r2 + 8004b12: 701a strb r2, [r3, #0] + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + 8004b14: 68fb ldr r3, [r7, #12] + 8004b16: 6a5b ldr r3, [r3, #36] ; 0x24 + 8004b18: 1c5a adds r2, r3, #1 + 8004b1a: 68fb ldr r3, [r7, #12] + 8004b1c: 625a str r2, [r3, #36] ; 0x24 + + /* Update counter */ + hi2c->XferSize--; + 8004b1e: 68fb ldr r3, [r7, #12] + 8004b20: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8004b22: 3b01 subs r3, #1 + 8004b24: b29a uxth r2, r3 + 8004b26: 68fb ldr r3, [r7, #12] + 8004b28: 851a strh r2, [r3, #40] ; 0x28 + hi2c->XferCount--; + 8004b2a: 68fb ldr r3, [r7, #12] + 8004b2c: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8004b2e: b29b uxth r3, r3 + 8004b30: 3b01 subs r3, #1 + 8004b32: b29a uxth r2, r3 + 8004b34: 68fb ldr r3, [r7, #12] + 8004b36: 855a strh r2, [r3, #42] ; 0x2a + while (hi2c->XferSize > 0U) + 8004b38: 68fb ldr r3, [r7, #12] + 8004b3a: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8004b3c: 2b00 cmp r3, #0 + 8004b3e: f47f aec2 bne.w 80048c6 + } + } + } + + hi2c->State = HAL_I2C_STATE_READY; + 8004b42: 68fb ldr r3, [r7, #12] + 8004b44: 2220 movs r2, #32 + 8004b46: f883 203d strb.w r2, [r3, #61] ; 0x3d + hi2c->Mode = HAL_I2C_MODE_NONE; + 8004b4a: 68fb ldr r3, [r7, #12] + 8004b4c: 2200 movs r2, #0 + 8004b4e: f883 203e strb.w r2, [r3, #62] ; 0x3e + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 8004b52: 68fb ldr r3, [r7, #12] + 8004b54: 2200 movs r2, #0 + 8004b56: f883 203c strb.w r2, [r3, #60] ; 0x3c + + return HAL_OK; + 8004b5a: 2300 movs r3, #0 + 8004b5c: e000 b.n 8004b60 + } + else + { + return HAL_BUSY; + 8004b5e: 2302 movs r3, #2 + } +} + 8004b60: 4618 mov r0, r3 + 8004b62: 3728 adds r7, #40 ; 0x28 + 8004b64: 46bd mov sp, r7 + 8004b66: bd80 pop {r7, pc} + 8004b68: 00010004 .word 0x00010004 + +08004b6c : + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart) +{ + 8004b6c: b580 push {r7, lr} + 8004b6e: b088 sub sp, #32 + 8004b70: af02 add r7, sp, #8 + 8004b72: 60f8 str r0, [r7, #12] + 8004b74: 607a str r2, [r7, #4] + 8004b76: 603b str r3, [r7, #0] + 8004b78: 460b mov r3, r1 + 8004b7a: 817b strh r3, [r7, #10] + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + uint32_t CurrentXferOptions = hi2c->XferOptions; + 8004b7c: 68fb ldr r3, [r7, #12] + 8004b7e: 6adb ldr r3, [r3, #44] ; 0x2c + 8004b80: 617b str r3, [r7, #20] + + /* Generate Start condition if first transfer */ + if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME)) + 8004b82: 697b ldr r3, [r7, #20] + 8004b84: 2b08 cmp r3, #8 + 8004b86: d006 beq.n 8004b96 + 8004b88: 697b ldr r3, [r7, #20] + 8004b8a: 2b01 cmp r3, #1 + 8004b8c: d003 beq.n 8004b96 + 8004b8e: 697b ldr r3, [r7, #20] + 8004b90: f513 3f80 cmn.w r3, #65536 ; 0x10000 + 8004b94: d108 bne.n 8004ba8 + { + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + 8004b96: 68fb ldr r3, [r7, #12] + 8004b98: 681b ldr r3, [r3, #0] + 8004b9a: 681a ldr r2, [r3, #0] + 8004b9c: 68fb ldr r3, [r7, #12] + 8004b9e: 681b ldr r3, [r3, #0] + 8004ba0: f442 7280 orr.w r2, r2, #256 ; 0x100 + 8004ba4: 601a str r2, [r3, #0] + 8004ba6: e00b b.n 8004bc0 + } + else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) + 8004ba8: 68fb ldr r3, [r7, #12] + 8004baa: 6b1b ldr r3, [r3, #48] ; 0x30 + 8004bac: 2b12 cmp r3, #18 + 8004bae: d107 bne.n 8004bc0 + { + /* Generate ReStart */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + 8004bb0: 68fb ldr r3, [r7, #12] + 8004bb2: 681b ldr r3, [r3, #0] + 8004bb4: 681a ldr r2, [r3, #0] + 8004bb6: 68fb ldr r3, [r7, #12] + 8004bb8: 681b ldr r3, [r3, #0] + 8004bba: f442 7280 orr.w r2, r2, #256 ; 0x100 + 8004bbe: 601a str r2, [r3, #0] + { + /* Do nothing */ + } + + /* Wait until SB flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) + 8004bc0: 683b ldr r3, [r7, #0] + 8004bc2: 9300 str r3, [sp, #0] + 8004bc4: 687b ldr r3, [r7, #4] + 8004bc6: 2200 movs r2, #0 + 8004bc8: f04f 1101 mov.w r1, #65537 ; 0x10001 + 8004bcc: 68f8 ldr r0, [r7, #12] + 8004bce: f000 f91d bl 8004e0c + 8004bd2: 4603 mov r3, r0 + 8004bd4: 2b00 cmp r3, #0 + 8004bd6: d00d beq.n 8004bf4 + { + if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) + 8004bd8: 68fb ldr r3, [r7, #12] + 8004bda: 681b ldr r3, [r3, #0] + 8004bdc: 681b ldr r3, [r3, #0] + 8004bde: f403 7380 and.w r3, r3, #256 ; 0x100 + 8004be2: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 8004be6: d103 bne.n 8004bf0 + { + hi2c->ErrorCode = HAL_I2C_WRONG_START; + 8004be8: 68fb ldr r3, [r7, #12] + 8004bea: f44f 7200 mov.w r2, #512 ; 0x200 + 8004bee: 641a str r2, [r3, #64] ; 0x40 + } + return HAL_TIMEOUT; + 8004bf0: 2303 movs r3, #3 + 8004bf2: e035 b.n 8004c60 + } + + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + 8004bf4: 68fb ldr r3, [r7, #12] + 8004bf6: 691b ldr r3, [r3, #16] + 8004bf8: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 + 8004bfc: d108 bne.n 8004c10 + { + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); + 8004bfe: 897b ldrh r3, [r7, #10] + 8004c00: b2db uxtb r3, r3 + 8004c02: 461a mov r2, r3 + 8004c04: 68fb ldr r3, [r7, #12] + 8004c06: 681b ldr r3, [r3, #0] + 8004c08: f002 02fe and.w r2, r2, #254 ; 0xfe + 8004c0c: 611a str r2, [r3, #16] + 8004c0e: e01b b.n 8004c48 + } + else + { + /* Send header of slave address */ + hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress); + 8004c10: 897b ldrh r3, [r7, #10] + 8004c12: 11db asrs r3, r3, #7 + 8004c14: b2db uxtb r3, r3 + 8004c16: f003 0306 and.w r3, r3, #6 + 8004c1a: b2db uxtb r3, r3 + 8004c1c: f063 030f orn r3, r3, #15 + 8004c20: b2da uxtb r2, r3 + 8004c22: 68fb ldr r3, [r7, #12] + 8004c24: 681b ldr r3, [r3, #0] + 8004c26: 611a str r2, [r3, #16] + + /* Wait until ADD10 flag is set */ + if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK) + 8004c28: 683b ldr r3, [r7, #0] + 8004c2a: 687a ldr r2, [r7, #4] + 8004c2c: 490e ldr r1, [pc, #56] ; (8004c68 ) + 8004c2e: 68f8 ldr r0, [r7, #12] + 8004c30: f000 f943 bl 8004eba + 8004c34: 4603 mov r3, r0 + 8004c36: 2b00 cmp r3, #0 + 8004c38: d001 beq.n 8004c3e + { + return HAL_ERROR; + 8004c3a: 2301 movs r3, #1 + 8004c3c: e010 b.n 8004c60 + } + + /* Send slave address */ + hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress); + 8004c3e: 897b ldrh r3, [r7, #10] + 8004c40: b2da uxtb r2, r3 + 8004c42: 68fb ldr r3, [r7, #12] + 8004c44: 681b ldr r3, [r3, #0] + 8004c46: 611a str r2, [r3, #16] + } + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) + 8004c48: 683b ldr r3, [r7, #0] + 8004c4a: 687a ldr r2, [r7, #4] + 8004c4c: 4907 ldr r1, [pc, #28] ; (8004c6c ) + 8004c4e: 68f8 ldr r0, [r7, #12] + 8004c50: f000 f933 bl 8004eba + 8004c54: 4603 mov r3, r0 + 8004c56: 2b00 cmp r3, #0 + 8004c58: d001 beq.n 8004c5e + { + return HAL_ERROR; + 8004c5a: 2301 movs r3, #1 + 8004c5c: e000 b.n 8004c60 + } + + return HAL_OK; + 8004c5e: 2300 movs r3, #0 +} + 8004c60: 4618 mov r0, r3 + 8004c62: 3718 adds r7, #24 + 8004c64: 46bd mov sp, r7 + 8004c66: bd80 pop {r7, pc} + 8004c68: 00010008 .word 0x00010008 + 8004c6c: 00010002 .word 0x00010002 + +08004c70 : + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart) +{ + 8004c70: b580 push {r7, lr} + 8004c72: b088 sub sp, #32 + 8004c74: af02 add r7, sp, #8 + 8004c76: 60f8 str r0, [r7, #12] + 8004c78: 607a str r2, [r7, #4] + 8004c7a: 603b str r3, [r7, #0] + 8004c7c: 460b mov r3, r1 + 8004c7e: 817b strh r3, [r7, #10] + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + uint32_t CurrentXferOptions = hi2c->XferOptions; + 8004c80: 68fb ldr r3, [r7, #12] + 8004c82: 6adb ldr r3, [r3, #44] ; 0x2c + 8004c84: 617b str r3, [r7, #20] + + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + 8004c86: 68fb ldr r3, [r7, #12] + 8004c88: 681b ldr r3, [r3, #0] + 8004c8a: 681a ldr r2, [r3, #0] + 8004c8c: 68fb ldr r3, [r7, #12] + 8004c8e: 681b ldr r3, [r3, #0] + 8004c90: f442 6280 orr.w r2, r2, #1024 ; 0x400 + 8004c94: 601a str r2, [r3, #0] + + /* Generate Start condition if first transfer */ + if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME)) + 8004c96: 697b ldr r3, [r7, #20] + 8004c98: 2b08 cmp r3, #8 + 8004c9a: d006 beq.n 8004caa + 8004c9c: 697b ldr r3, [r7, #20] + 8004c9e: 2b01 cmp r3, #1 + 8004ca0: d003 beq.n 8004caa + 8004ca2: 697b ldr r3, [r7, #20] + 8004ca4: f513 3f80 cmn.w r3, #65536 ; 0x10000 + 8004ca8: d108 bne.n 8004cbc + { + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + 8004caa: 68fb ldr r3, [r7, #12] + 8004cac: 681b ldr r3, [r3, #0] + 8004cae: 681a ldr r2, [r3, #0] + 8004cb0: 68fb ldr r3, [r7, #12] + 8004cb2: 681b ldr r3, [r3, #0] + 8004cb4: f442 7280 orr.w r2, r2, #256 ; 0x100 + 8004cb8: 601a str r2, [r3, #0] + 8004cba: e00b b.n 8004cd4 + } + else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) + 8004cbc: 68fb ldr r3, [r7, #12] + 8004cbe: 6b1b ldr r3, [r3, #48] ; 0x30 + 8004cc0: 2b11 cmp r3, #17 + 8004cc2: d107 bne.n 8004cd4 + { + /* Generate ReStart */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + 8004cc4: 68fb ldr r3, [r7, #12] + 8004cc6: 681b ldr r3, [r3, #0] + 8004cc8: 681a ldr r2, [r3, #0] + 8004cca: 68fb ldr r3, [r7, #12] + 8004ccc: 681b ldr r3, [r3, #0] + 8004cce: f442 7280 orr.w r2, r2, #256 ; 0x100 + 8004cd2: 601a str r2, [r3, #0] + { + /* Do nothing */ + } + + /* Wait until SB flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) + 8004cd4: 683b ldr r3, [r7, #0] + 8004cd6: 9300 str r3, [sp, #0] + 8004cd8: 687b ldr r3, [r7, #4] + 8004cda: 2200 movs r2, #0 + 8004cdc: f04f 1101 mov.w r1, #65537 ; 0x10001 + 8004ce0: 68f8 ldr r0, [r7, #12] + 8004ce2: f000 f893 bl 8004e0c + 8004ce6: 4603 mov r3, r0 + 8004ce8: 2b00 cmp r3, #0 + 8004cea: d00d beq.n 8004d08 + { + if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) + 8004cec: 68fb ldr r3, [r7, #12] + 8004cee: 681b ldr r3, [r3, #0] + 8004cf0: 681b ldr r3, [r3, #0] + 8004cf2: f403 7380 and.w r3, r3, #256 ; 0x100 + 8004cf6: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 8004cfa: d103 bne.n 8004d04 + { + hi2c->ErrorCode = HAL_I2C_WRONG_START; + 8004cfc: 68fb ldr r3, [r7, #12] + 8004cfe: f44f 7200 mov.w r2, #512 ; 0x200 + 8004d02: 641a str r2, [r3, #64] ; 0x40 + } + return HAL_TIMEOUT; + 8004d04: 2303 movs r3, #3 + 8004d06: e079 b.n 8004dfc + } + + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + 8004d08: 68fb ldr r3, [r7, #12] + 8004d0a: 691b ldr r3, [r3, #16] + 8004d0c: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 + 8004d10: d108 bne.n 8004d24 + { + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress); + 8004d12: 897b ldrh r3, [r7, #10] + 8004d14: b2db uxtb r3, r3 + 8004d16: f043 0301 orr.w r3, r3, #1 + 8004d1a: b2da uxtb r2, r3 + 8004d1c: 68fb ldr r3, [r7, #12] + 8004d1e: 681b ldr r3, [r3, #0] + 8004d20: 611a str r2, [r3, #16] + 8004d22: e05f b.n 8004de4 + } + else + { + /* Send header of slave address */ + hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress); + 8004d24: 897b ldrh r3, [r7, #10] + 8004d26: 11db asrs r3, r3, #7 + 8004d28: b2db uxtb r3, r3 + 8004d2a: f003 0306 and.w r3, r3, #6 + 8004d2e: b2db uxtb r3, r3 + 8004d30: f063 030f orn r3, r3, #15 + 8004d34: b2da uxtb r2, r3 + 8004d36: 68fb ldr r3, [r7, #12] + 8004d38: 681b ldr r3, [r3, #0] + 8004d3a: 611a str r2, [r3, #16] + + /* Wait until ADD10 flag is set */ + if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK) + 8004d3c: 683b ldr r3, [r7, #0] + 8004d3e: 687a ldr r2, [r7, #4] + 8004d40: 4930 ldr r1, [pc, #192] ; (8004e04 ) + 8004d42: 68f8 ldr r0, [r7, #12] + 8004d44: f000 f8b9 bl 8004eba + 8004d48: 4603 mov r3, r0 + 8004d4a: 2b00 cmp r3, #0 + 8004d4c: d001 beq.n 8004d52 + { + return HAL_ERROR; + 8004d4e: 2301 movs r3, #1 + 8004d50: e054 b.n 8004dfc + } + + /* Send slave address */ + hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress); + 8004d52: 897b ldrh r3, [r7, #10] + 8004d54: b2da uxtb r2, r3 + 8004d56: 68fb ldr r3, [r7, #12] + 8004d58: 681b ldr r3, [r3, #0] + 8004d5a: 611a str r2, [r3, #16] + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) + 8004d5c: 683b ldr r3, [r7, #0] + 8004d5e: 687a ldr r2, [r7, #4] + 8004d60: 4929 ldr r1, [pc, #164] ; (8004e08 ) + 8004d62: 68f8 ldr r0, [r7, #12] + 8004d64: f000 f8a9 bl 8004eba + 8004d68: 4603 mov r3, r0 + 8004d6a: 2b00 cmp r3, #0 + 8004d6c: d001 beq.n 8004d72 + { + return HAL_ERROR; + 8004d6e: 2301 movs r3, #1 + 8004d70: e044 b.n 8004dfc + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + 8004d72: 2300 movs r3, #0 + 8004d74: 613b str r3, [r7, #16] + 8004d76: 68fb ldr r3, [r7, #12] + 8004d78: 681b ldr r3, [r3, #0] + 8004d7a: 695b ldr r3, [r3, #20] + 8004d7c: 613b str r3, [r7, #16] + 8004d7e: 68fb ldr r3, [r7, #12] + 8004d80: 681b ldr r3, [r3, #0] + 8004d82: 699b ldr r3, [r3, #24] + 8004d84: 613b str r3, [r7, #16] + 8004d86: 693b ldr r3, [r7, #16] + + /* Generate Restart */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + 8004d88: 68fb ldr r3, [r7, #12] + 8004d8a: 681b ldr r3, [r3, #0] + 8004d8c: 681a ldr r2, [r3, #0] + 8004d8e: 68fb ldr r3, [r7, #12] + 8004d90: 681b ldr r3, [r3, #0] + 8004d92: f442 7280 orr.w r2, r2, #256 ; 0x100 + 8004d96: 601a str r2, [r3, #0] + + /* Wait until SB flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) + 8004d98: 683b ldr r3, [r7, #0] + 8004d9a: 9300 str r3, [sp, #0] + 8004d9c: 687b ldr r3, [r7, #4] + 8004d9e: 2200 movs r2, #0 + 8004da0: f04f 1101 mov.w r1, #65537 ; 0x10001 + 8004da4: 68f8 ldr r0, [r7, #12] + 8004da6: f000 f831 bl 8004e0c + 8004daa: 4603 mov r3, r0 + 8004dac: 2b00 cmp r3, #0 + 8004dae: d00d beq.n 8004dcc + { + if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) + 8004db0: 68fb ldr r3, [r7, #12] + 8004db2: 681b ldr r3, [r3, #0] + 8004db4: 681b ldr r3, [r3, #0] + 8004db6: f403 7380 and.w r3, r3, #256 ; 0x100 + 8004dba: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 8004dbe: d103 bne.n 8004dc8 + { + hi2c->ErrorCode = HAL_I2C_WRONG_START; + 8004dc0: 68fb ldr r3, [r7, #12] + 8004dc2: f44f 7200 mov.w r2, #512 ; 0x200 + 8004dc6: 641a str r2, [r3, #64] ; 0x40 + } + return HAL_TIMEOUT; + 8004dc8: 2303 movs r3, #3 + 8004dca: e017 b.n 8004dfc + } + + /* Send header of slave address */ + hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress); + 8004dcc: 897b ldrh r3, [r7, #10] + 8004dce: 11db asrs r3, r3, #7 + 8004dd0: b2db uxtb r3, r3 + 8004dd2: f003 0306 and.w r3, r3, #6 + 8004dd6: b2db uxtb r3, r3 + 8004dd8: f063 030e orn r3, r3, #14 + 8004ddc: b2da uxtb r2, r3 + 8004dde: 68fb ldr r3, [r7, #12] + 8004de0: 681b ldr r3, [r3, #0] + 8004de2: 611a str r2, [r3, #16] + } + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) + 8004de4: 683b ldr r3, [r7, #0] + 8004de6: 687a ldr r2, [r7, #4] + 8004de8: 4907 ldr r1, [pc, #28] ; (8004e08 ) + 8004dea: 68f8 ldr r0, [r7, #12] + 8004dec: f000 f865 bl 8004eba + 8004df0: 4603 mov r3, r0 + 8004df2: 2b00 cmp r3, #0 + 8004df4: d001 beq.n 8004dfa + { + return HAL_ERROR; + 8004df6: 2301 movs r3, #1 + 8004df8: e000 b.n 8004dfc + } + + return HAL_OK; + 8004dfa: 2300 movs r3, #0 +} + 8004dfc: 4618 mov r0, r3 + 8004dfe: 3718 adds r7, #24 + 8004e00: 46bd mov sp, r7 + 8004e02: bd80 pop {r7, pc} + 8004e04: 00010008 .word 0x00010008 + 8004e08: 00010002 .word 0x00010002 + +08004e0c : + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) +{ + 8004e0c: b580 push {r7, lr} + 8004e0e: b084 sub sp, #16 + 8004e10: af00 add r7, sp, #0 + 8004e12: 60f8 str r0, [r7, #12] + 8004e14: 60b9 str r1, [r7, #8] + 8004e16: 603b str r3, [r7, #0] + 8004e18: 4613 mov r3, r2 + 8004e1a: 71fb strb r3, [r7, #7] + /* Wait until flag is set */ + while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) + 8004e1c: e025 b.n 8004e6a + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + 8004e1e: 683b ldr r3, [r7, #0] + 8004e20: f1b3 3fff cmp.w r3, #4294967295 + 8004e24: d021 beq.n 8004e6a + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + 8004e26: f7fd fa79 bl 800231c + 8004e2a: 4602 mov r2, r0 + 8004e2c: 69bb ldr r3, [r7, #24] + 8004e2e: 1ad3 subs r3, r2, r3 + 8004e30: 683a ldr r2, [r7, #0] + 8004e32: 429a cmp r2, r3 + 8004e34: d302 bcc.n 8004e3c + 8004e36: 683b ldr r3, [r7, #0] + 8004e38: 2b00 cmp r3, #0 + 8004e3a: d116 bne.n 8004e6a + { + hi2c->PreviousState = I2C_STATE_NONE; + 8004e3c: 68fb ldr r3, [r7, #12] + 8004e3e: 2200 movs r2, #0 + 8004e40: 631a str r2, [r3, #48] ; 0x30 + hi2c->State = HAL_I2C_STATE_READY; + 8004e42: 68fb ldr r3, [r7, #12] + 8004e44: 2220 movs r2, #32 + 8004e46: f883 203d strb.w r2, [r3, #61] ; 0x3d + hi2c->Mode = HAL_I2C_MODE_NONE; + 8004e4a: 68fb ldr r3, [r7, #12] + 8004e4c: 2200 movs r2, #0 + 8004e4e: f883 203e strb.w r2, [r3, #62] ; 0x3e + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + 8004e52: 68fb ldr r3, [r7, #12] + 8004e54: 6c1b ldr r3, [r3, #64] ; 0x40 + 8004e56: f043 0220 orr.w r2, r3, #32 + 8004e5a: 68fb ldr r3, [r7, #12] + 8004e5c: 641a str r2, [r3, #64] ; 0x40 + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 8004e5e: 68fb ldr r3, [r7, #12] + 8004e60: 2200 movs r2, #0 + 8004e62: f883 203c strb.w r2, [r3, #60] ; 0x3c + + return HAL_ERROR; + 8004e66: 2301 movs r3, #1 + 8004e68: e023 b.n 8004eb2 + while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) + 8004e6a: 68bb ldr r3, [r7, #8] + 8004e6c: 0c1b lsrs r3, r3, #16 + 8004e6e: b2db uxtb r3, r3 + 8004e70: 2b01 cmp r3, #1 + 8004e72: d10d bne.n 8004e90 + 8004e74: 68fb ldr r3, [r7, #12] + 8004e76: 681b ldr r3, [r3, #0] + 8004e78: 695b ldr r3, [r3, #20] + 8004e7a: 43da mvns r2, r3 + 8004e7c: 68bb ldr r3, [r7, #8] + 8004e7e: 4013 ands r3, r2 + 8004e80: b29b uxth r3, r3 + 8004e82: 2b00 cmp r3, #0 + 8004e84: bf0c ite eq + 8004e86: 2301 moveq r3, #1 + 8004e88: 2300 movne r3, #0 + 8004e8a: b2db uxtb r3, r3 + 8004e8c: 461a mov r2, r3 + 8004e8e: e00c b.n 8004eaa + 8004e90: 68fb ldr r3, [r7, #12] + 8004e92: 681b ldr r3, [r3, #0] + 8004e94: 699b ldr r3, [r3, #24] + 8004e96: 43da mvns r2, r3 + 8004e98: 68bb ldr r3, [r7, #8] + 8004e9a: 4013 ands r3, r2 + 8004e9c: b29b uxth r3, r3 + 8004e9e: 2b00 cmp r3, #0 + 8004ea0: bf0c ite eq + 8004ea2: 2301 moveq r3, #1 + 8004ea4: 2300 movne r3, #0 + 8004ea6: b2db uxtb r3, r3 + 8004ea8: 461a mov r2, r3 + 8004eaa: 79fb ldrb r3, [r7, #7] + 8004eac: 429a cmp r2, r3 + 8004eae: d0b6 beq.n 8004e1e + } + } + } + return HAL_OK; + 8004eb0: 2300 movs r3, #0 +} + 8004eb2: 4618 mov r0, r3 + 8004eb4: 3710 adds r7, #16 + 8004eb6: 46bd mov sp, r7 + 8004eb8: bd80 pop {r7, pc} + +08004eba : + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart) +{ + 8004eba: b580 push {r7, lr} + 8004ebc: b084 sub sp, #16 + 8004ebe: af00 add r7, sp, #0 + 8004ec0: 60f8 str r0, [r7, #12] + 8004ec2: 60b9 str r1, [r7, #8] + 8004ec4: 607a str r2, [r7, #4] + 8004ec6: 603b str r3, [r7, #0] + while (__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET) + 8004ec8: e051 b.n 8004f6e + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + 8004eca: 68fb ldr r3, [r7, #12] + 8004ecc: 681b ldr r3, [r3, #0] + 8004ece: 695b ldr r3, [r3, #20] + 8004ed0: f403 6380 and.w r3, r3, #1024 ; 0x400 + 8004ed4: f5b3 6f80 cmp.w r3, #1024 ; 0x400 + 8004ed8: d123 bne.n 8004f22 + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + 8004eda: 68fb ldr r3, [r7, #12] + 8004edc: 681b ldr r3, [r3, #0] + 8004ede: 681a ldr r2, [r3, #0] + 8004ee0: 68fb ldr r3, [r7, #12] + 8004ee2: 681b ldr r3, [r3, #0] + 8004ee4: f442 7200 orr.w r2, r2, #512 ; 0x200 + 8004ee8: 601a str r2, [r3, #0] + + /* Clear AF Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + 8004eea: 68fb ldr r3, [r7, #12] + 8004eec: 681b ldr r3, [r3, #0] + 8004eee: f46f 6280 mvn.w r2, #1024 ; 0x400 + 8004ef2: 615a str r2, [r3, #20] + + hi2c->PreviousState = I2C_STATE_NONE; + 8004ef4: 68fb ldr r3, [r7, #12] + 8004ef6: 2200 movs r2, #0 + 8004ef8: 631a str r2, [r3, #48] ; 0x30 + hi2c->State = HAL_I2C_STATE_READY; + 8004efa: 68fb ldr r3, [r7, #12] + 8004efc: 2220 movs r2, #32 + 8004efe: f883 203d strb.w r2, [r3, #61] ; 0x3d + hi2c->Mode = HAL_I2C_MODE_NONE; + 8004f02: 68fb ldr r3, [r7, #12] + 8004f04: 2200 movs r2, #0 + 8004f06: f883 203e strb.w r2, [r3, #62] ; 0x3e + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + 8004f0a: 68fb ldr r3, [r7, #12] + 8004f0c: 6c1b ldr r3, [r3, #64] ; 0x40 + 8004f0e: f043 0204 orr.w r2, r3, #4 + 8004f12: 68fb ldr r3, [r7, #12] + 8004f14: 641a str r2, [r3, #64] ; 0x40 + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 8004f16: 68fb ldr r3, [r7, #12] + 8004f18: 2200 movs r2, #0 + 8004f1a: f883 203c strb.w r2, [r3, #60] ; 0x3c + + return HAL_ERROR; + 8004f1e: 2301 movs r3, #1 + 8004f20: e046 b.n 8004fb0 + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + 8004f22: 687b ldr r3, [r7, #4] + 8004f24: f1b3 3fff cmp.w r3, #4294967295 + 8004f28: d021 beq.n 8004f6e + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + 8004f2a: f7fd f9f7 bl 800231c + 8004f2e: 4602 mov r2, r0 + 8004f30: 683b ldr r3, [r7, #0] + 8004f32: 1ad3 subs r3, r2, r3 + 8004f34: 687a ldr r2, [r7, #4] + 8004f36: 429a cmp r2, r3 + 8004f38: d302 bcc.n 8004f40 + 8004f3a: 687b ldr r3, [r7, #4] + 8004f3c: 2b00 cmp r3, #0 + 8004f3e: d116 bne.n 8004f6e + { + hi2c->PreviousState = I2C_STATE_NONE; + 8004f40: 68fb ldr r3, [r7, #12] + 8004f42: 2200 movs r2, #0 + 8004f44: 631a str r2, [r3, #48] ; 0x30 + hi2c->State = HAL_I2C_STATE_READY; + 8004f46: 68fb ldr r3, [r7, #12] + 8004f48: 2220 movs r2, #32 + 8004f4a: f883 203d strb.w r2, [r3, #61] ; 0x3d + hi2c->Mode = HAL_I2C_MODE_NONE; + 8004f4e: 68fb ldr r3, [r7, #12] + 8004f50: 2200 movs r2, #0 + 8004f52: f883 203e strb.w r2, [r3, #62] ; 0x3e + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + 8004f56: 68fb ldr r3, [r7, #12] + 8004f58: 6c1b ldr r3, [r3, #64] ; 0x40 + 8004f5a: f043 0220 orr.w r2, r3, #32 + 8004f5e: 68fb ldr r3, [r7, #12] + 8004f60: 641a str r2, [r3, #64] ; 0x40 + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 8004f62: 68fb ldr r3, [r7, #12] + 8004f64: 2200 movs r2, #0 + 8004f66: f883 203c strb.w r2, [r3, #60] ; 0x3c + + return HAL_ERROR; + 8004f6a: 2301 movs r3, #1 + 8004f6c: e020 b.n 8004fb0 + while (__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET) + 8004f6e: 68bb ldr r3, [r7, #8] + 8004f70: 0c1b lsrs r3, r3, #16 + 8004f72: b2db uxtb r3, r3 + 8004f74: 2b01 cmp r3, #1 + 8004f76: d10c bne.n 8004f92 + 8004f78: 68fb ldr r3, [r7, #12] + 8004f7a: 681b ldr r3, [r3, #0] + 8004f7c: 695b ldr r3, [r3, #20] + 8004f7e: 43da mvns r2, r3 + 8004f80: 68bb ldr r3, [r7, #8] + 8004f82: 4013 ands r3, r2 + 8004f84: b29b uxth r3, r3 + 8004f86: 2b00 cmp r3, #0 + 8004f88: bf14 ite ne + 8004f8a: 2301 movne r3, #1 + 8004f8c: 2300 moveq r3, #0 + 8004f8e: b2db uxtb r3, r3 + 8004f90: e00b b.n 8004faa + 8004f92: 68fb ldr r3, [r7, #12] + 8004f94: 681b ldr r3, [r3, #0] + 8004f96: 699b ldr r3, [r3, #24] + 8004f98: 43da mvns r2, r3 + 8004f9a: 68bb ldr r3, [r7, #8] + 8004f9c: 4013 ands r3, r2 + 8004f9e: b29b uxth r3, r3 + 8004fa0: 2b00 cmp r3, #0 + 8004fa2: bf14 ite ne + 8004fa4: 2301 movne r3, #1 + 8004fa6: 2300 moveq r3, #0 + 8004fa8: b2db uxtb r3, r3 + 8004faa: 2b00 cmp r3, #0 + 8004fac: d18d bne.n 8004eca + } + } + } + return HAL_OK; + 8004fae: 2300 movs r3, #0 +} + 8004fb0: 4618 mov r0, r3 + 8004fb2: 3710 adds r7, #16 + 8004fb4: 46bd mov sp, r7 + 8004fb6: bd80 pop {r7, pc} + +08004fb8 : + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + 8004fb8: b580 push {r7, lr} + 8004fba: b084 sub sp, #16 + 8004fbc: af00 add r7, sp, #0 + 8004fbe: 60f8 str r0, [r7, #12] + 8004fc0: 60b9 str r1, [r7, #8] + 8004fc2: 607a str r2, [r7, #4] + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) + 8004fc4: e02d b.n 8005022 + { + /* Check if a NACK is detected */ + if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) + 8004fc6: 68f8 ldr r0, [r7, #12] + 8004fc8: f000 f8ce bl 8005168 + 8004fcc: 4603 mov r3, r0 + 8004fce: 2b00 cmp r3, #0 + 8004fd0: d001 beq.n 8004fd6 + { + return HAL_ERROR; + 8004fd2: 2301 movs r3, #1 + 8004fd4: e02d b.n 8005032 + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + 8004fd6: 68bb ldr r3, [r7, #8] + 8004fd8: f1b3 3fff cmp.w r3, #4294967295 + 8004fdc: d021 beq.n 8005022 + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + 8004fde: f7fd f99d bl 800231c + 8004fe2: 4602 mov r2, r0 + 8004fe4: 687b ldr r3, [r7, #4] + 8004fe6: 1ad3 subs r3, r2, r3 + 8004fe8: 68ba ldr r2, [r7, #8] + 8004fea: 429a cmp r2, r3 + 8004fec: d302 bcc.n 8004ff4 + 8004fee: 68bb ldr r3, [r7, #8] + 8004ff0: 2b00 cmp r3, #0 + 8004ff2: d116 bne.n 8005022 + { + hi2c->PreviousState = I2C_STATE_NONE; + 8004ff4: 68fb ldr r3, [r7, #12] + 8004ff6: 2200 movs r2, #0 + 8004ff8: 631a str r2, [r3, #48] ; 0x30 + hi2c->State = HAL_I2C_STATE_READY; + 8004ffa: 68fb ldr r3, [r7, #12] + 8004ffc: 2220 movs r2, #32 + 8004ffe: f883 203d strb.w r2, [r3, #61] ; 0x3d + hi2c->Mode = HAL_I2C_MODE_NONE; + 8005002: 68fb ldr r3, [r7, #12] + 8005004: 2200 movs r2, #0 + 8005006: f883 203e strb.w r2, [r3, #62] ; 0x3e + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + 800500a: 68fb ldr r3, [r7, #12] + 800500c: 6c1b ldr r3, [r3, #64] ; 0x40 + 800500e: f043 0220 orr.w r2, r3, #32 + 8005012: 68fb ldr r3, [r7, #12] + 8005014: 641a str r2, [r3, #64] ; 0x40 + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 8005016: 68fb ldr r3, [r7, #12] + 8005018: 2200 movs r2, #0 + 800501a: f883 203c strb.w r2, [r3, #60] ; 0x3c + + return HAL_ERROR; + 800501e: 2301 movs r3, #1 + 8005020: e007 b.n 8005032 + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) + 8005022: 68fb ldr r3, [r7, #12] + 8005024: 681b ldr r3, [r3, #0] + 8005026: 695b ldr r3, [r3, #20] + 8005028: f003 0380 and.w r3, r3, #128 ; 0x80 + 800502c: 2b80 cmp r3, #128 ; 0x80 + 800502e: d1ca bne.n 8004fc6 + } + } + } + return HAL_OK; + 8005030: 2300 movs r3, #0 +} + 8005032: 4618 mov r0, r3 + 8005034: 3710 adds r7, #16 + 8005036: 46bd mov sp, r7 + 8005038: bd80 pop {r7, pc} + +0800503a : + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + 800503a: b580 push {r7, lr} + 800503c: b084 sub sp, #16 + 800503e: af00 add r7, sp, #0 + 8005040: 60f8 str r0, [r7, #12] + 8005042: 60b9 str r1, [r7, #8] + 8005044: 607a str r2, [r7, #4] + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET) + 8005046: e02d b.n 80050a4 + { + /* Check if a NACK is detected */ + if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) + 8005048: 68f8 ldr r0, [r7, #12] + 800504a: f000 f88d bl 8005168 + 800504e: 4603 mov r3, r0 + 8005050: 2b00 cmp r3, #0 + 8005052: d001 beq.n 8005058 + { + return HAL_ERROR; + 8005054: 2301 movs r3, #1 + 8005056: e02d b.n 80050b4 + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + 8005058: 68bb ldr r3, [r7, #8] + 800505a: f1b3 3fff cmp.w r3, #4294967295 + 800505e: d021 beq.n 80050a4 + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + 8005060: f7fd f95c bl 800231c + 8005064: 4602 mov r2, r0 + 8005066: 687b ldr r3, [r7, #4] + 8005068: 1ad3 subs r3, r2, r3 + 800506a: 68ba ldr r2, [r7, #8] + 800506c: 429a cmp r2, r3 + 800506e: d302 bcc.n 8005076 + 8005070: 68bb ldr r3, [r7, #8] + 8005072: 2b00 cmp r3, #0 + 8005074: d116 bne.n 80050a4 + { + hi2c->PreviousState = I2C_STATE_NONE; + 8005076: 68fb ldr r3, [r7, #12] + 8005078: 2200 movs r2, #0 + 800507a: 631a str r2, [r3, #48] ; 0x30 + hi2c->State = HAL_I2C_STATE_READY; + 800507c: 68fb ldr r3, [r7, #12] + 800507e: 2220 movs r2, #32 + 8005080: f883 203d strb.w r2, [r3, #61] ; 0x3d + hi2c->Mode = HAL_I2C_MODE_NONE; + 8005084: 68fb ldr r3, [r7, #12] + 8005086: 2200 movs r2, #0 + 8005088: f883 203e strb.w r2, [r3, #62] ; 0x3e + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + 800508c: 68fb ldr r3, [r7, #12] + 800508e: 6c1b ldr r3, [r3, #64] ; 0x40 + 8005090: f043 0220 orr.w r2, r3, #32 + 8005094: 68fb ldr r3, [r7, #12] + 8005096: 641a str r2, [r3, #64] ; 0x40 + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 8005098: 68fb ldr r3, [r7, #12] + 800509a: 2200 movs r2, #0 + 800509c: f883 203c strb.w r2, [r3, #60] ; 0x3c + + return HAL_ERROR; + 80050a0: 2301 movs r3, #1 + 80050a2: e007 b.n 80050b4 + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET) + 80050a4: 68fb ldr r3, [r7, #12] + 80050a6: 681b ldr r3, [r3, #0] + 80050a8: 695b ldr r3, [r3, #20] + 80050aa: f003 0304 and.w r3, r3, #4 + 80050ae: 2b04 cmp r3, #4 + 80050b0: d1ca bne.n 8005048 + } + } + } + return HAL_OK; + 80050b2: 2300 movs r3, #0 +} + 80050b4: 4618 mov r0, r3 + 80050b6: 3710 adds r7, #16 + 80050b8: 46bd mov sp, r7 + 80050ba: bd80 pop {r7, pc} + +080050bc : + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + 80050bc: b580 push {r7, lr} + 80050be: b084 sub sp, #16 + 80050c0: af00 add r7, sp, #0 + 80050c2: 60f8 str r0, [r7, #12] + 80050c4: 60b9 str r1, [r7, #8] + 80050c6: 607a str r2, [r7, #4] + + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) + 80050c8: e042 b.n 8005150 + { + /* Check if a STOPF is detected */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + 80050ca: 68fb ldr r3, [r7, #12] + 80050cc: 681b ldr r3, [r3, #0] + 80050ce: 695b ldr r3, [r3, #20] + 80050d0: f003 0310 and.w r3, r3, #16 + 80050d4: 2b10 cmp r3, #16 + 80050d6: d119 bne.n 800510c + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + 80050d8: 68fb ldr r3, [r7, #12] + 80050da: 681b ldr r3, [r3, #0] + 80050dc: f06f 0210 mvn.w r2, #16 + 80050e0: 615a str r2, [r3, #20] + + hi2c->PreviousState = I2C_STATE_NONE; + 80050e2: 68fb ldr r3, [r7, #12] + 80050e4: 2200 movs r2, #0 + 80050e6: 631a str r2, [r3, #48] ; 0x30 + hi2c->State = HAL_I2C_STATE_READY; + 80050e8: 68fb ldr r3, [r7, #12] + 80050ea: 2220 movs r2, #32 + 80050ec: f883 203d strb.w r2, [r3, #61] ; 0x3d + hi2c->Mode = HAL_I2C_MODE_NONE; + 80050f0: 68fb ldr r3, [r7, #12] + 80050f2: 2200 movs r2, #0 + 80050f4: f883 203e strb.w r2, [r3, #62] ; 0x3e + hi2c->ErrorCode |= HAL_I2C_ERROR_NONE; + 80050f8: 68fb ldr r3, [r7, #12] + 80050fa: 6c1a ldr r2, [r3, #64] ; 0x40 + 80050fc: 68fb ldr r3, [r7, #12] + 80050fe: 641a str r2, [r3, #64] ; 0x40 + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 8005100: 68fb ldr r3, [r7, #12] + 8005102: 2200 movs r2, #0 + 8005104: f883 203c strb.w r2, [r3, #60] ; 0x3c + + return HAL_ERROR; + 8005108: 2301 movs r3, #1 + 800510a: e029 b.n 8005160 + } + + /* Check for the Timeout */ + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + 800510c: f7fd f906 bl 800231c + 8005110: 4602 mov r2, r0 + 8005112: 687b ldr r3, [r7, #4] + 8005114: 1ad3 subs r3, r2, r3 + 8005116: 68ba ldr r2, [r7, #8] + 8005118: 429a cmp r2, r3 + 800511a: d302 bcc.n 8005122 + 800511c: 68bb ldr r3, [r7, #8] + 800511e: 2b00 cmp r3, #0 + 8005120: d116 bne.n 8005150 + { + hi2c->PreviousState = I2C_STATE_NONE; + 8005122: 68fb ldr r3, [r7, #12] + 8005124: 2200 movs r2, #0 + 8005126: 631a str r2, [r3, #48] ; 0x30 + hi2c->State = HAL_I2C_STATE_READY; + 8005128: 68fb ldr r3, [r7, #12] + 800512a: 2220 movs r2, #32 + 800512c: f883 203d strb.w r2, [r3, #61] ; 0x3d + hi2c->Mode = HAL_I2C_MODE_NONE; + 8005130: 68fb ldr r3, [r7, #12] + 8005132: 2200 movs r2, #0 + 8005134: f883 203e strb.w r2, [r3, #62] ; 0x3e + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + 8005138: 68fb ldr r3, [r7, #12] + 800513a: 6c1b ldr r3, [r3, #64] ; 0x40 + 800513c: f043 0220 orr.w r2, r3, #32 + 8005140: 68fb ldr r3, [r7, #12] + 8005142: 641a str r2, [r3, #64] ; 0x40 + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 8005144: 68fb ldr r3, [r7, #12] + 8005146: 2200 movs r2, #0 + 8005148: f883 203c strb.w r2, [r3, #60] ; 0x3c + + return HAL_ERROR; + 800514c: 2301 movs r3, #1 + 800514e: e007 b.n 8005160 + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) + 8005150: 68fb ldr r3, [r7, #12] + 8005152: 681b ldr r3, [r3, #0] + 8005154: 695b ldr r3, [r3, #20] + 8005156: f003 0340 and.w r3, r3, #64 ; 0x40 + 800515a: 2b40 cmp r3, #64 ; 0x40 + 800515c: d1b5 bne.n 80050ca + } + } + return HAL_OK; + 800515e: 2300 movs r3, #0 +} + 8005160: 4618 mov r0, r3 + 8005162: 3710 adds r7, #16 + 8005164: 46bd mov sp, r7 + 8005166: bd80 pop {r7, pc} + +08005168 : + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c) +{ + 8005168: b480 push {r7} + 800516a: b083 sub sp, #12 + 800516c: af00 add r7, sp, #0 + 800516e: 6078 str r0, [r7, #4] + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + 8005170: 687b ldr r3, [r7, #4] + 8005172: 681b ldr r3, [r3, #0] + 8005174: 695b ldr r3, [r3, #20] + 8005176: f403 6380 and.w r3, r3, #1024 ; 0x400 + 800517a: f5b3 6f80 cmp.w r3, #1024 ; 0x400 + 800517e: d11b bne.n 80051b8 + { + /* Clear NACKF Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + 8005180: 687b ldr r3, [r7, #4] + 8005182: 681b ldr r3, [r3, #0] + 8005184: f46f 6280 mvn.w r2, #1024 ; 0x400 + 8005188: 615a str r2, [r3, #20] + + hi2c->PreviousState = I2C_STATE_NONE; + 800518a: 687b ldr r3, [r7, #4] + 800518c: 2200 movs r2, #0 + 800518e: 631a str r2, [r3, #48] ; 0x30 + hi2c->State = HAL_I2C_STATE_READY; + 8005190: 687b ldr r3, [r7, #4] + 8005192: 2220 movs r2, #32 + 8005194: f883 203d strb.w r2, [r3, #61] ; 0x3d + hi2c->Mode = HAL_I2C_MODE_NONE; + 8005198: 687b ldr r3, [r7, #4] + 800519a: 2200 movs r2, #0 + 800519c: f883 203e strb.w r2, [r3, #62] ; 0x3e + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + 80051a0: 687b ldr r3, [r7, #4] + 80051a2: 6c1b ldr r3, [r3, #64] ; 0x40 + 80051a4: f043 0204 orr.w r2, r3, #4 + 80051a8: 687b ldr r3, [r7, #4] + 80051aa: 641a str r2, [r3, #64] ; 0x40 + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 80051ac: 687b ldr r3, [r7, #4] + 80051ae: 2200 movs r2, #0 + 80051b0: f883 203c strb.w r2, [r3, #60] ; 0x3c + + return HAL_ERROR; + 80051b4: 2301 movs r3, #1 + 80051b6: e000 b.n 80051ba + } + return HAL_OK; + 80051b8: 2300 movs r3, #0 +} + 80051ba: 4618 mov r0, r3 + 80051bc: 370c adds r7, #12 + 80051be: 46bd mov sp, r7 + 80051c0: f85d 7b04 ldr.w r7, [sp], #4 + 80051c4: 4770 bx lr + ... + +080051c8 : + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) +{ + 80051c8: b580 push {r7, lr} + 80051ca: b088 sub sp, #32 + 80051cc: af00 add r7, sp, #0 + 80051ce: 6078 str r0, [r7, #4] +#if defined (SPI_I2S_FULLDUPLEX_SUPPORT) + uint16_t tmpreg; +#endif + + /* Check the I2S handle allocation */ + if (hi2s == NULL) + 80051d0: 687b ldr r3, [r7, #4] + 80051d2: 2b00 cmp r3, #0 + 80051d4: d101 bne.n 80051da + { + return HAL_ERROR; + 80051d6: 2301 movs r3, #1 + 80051d8: e128 b.n 800542c + assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput)); + assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq)); + assert_param(IS_I2S_CPOL(hi2s->Init.CPOL)); + assert_param(IS_I2S_CLOCKSOURCE(hi2s->Init.ClockSource)); + + if (hi2s->State == HAL_I2S_STATE_RESET) + 80051da: 687b ldr r3, [r7, #4] + 80051dc: f893 3041 ldrb.w r3, [r3, #65] ; 0x41 + 80051e0: b2db uxtb r3, r3 + 80051e2: 2b00 cmp r3, #0 + 80051e4: d109 bne.n 80051fa + { + /* Allocate lock resource and initialize it */ + hi2s->Lock = HAL_UNLOCKED; + 80051e6: 687b ldr r3, [r7, #4] + 80051e8: 2200 movs r2, #0 + 80051ea: f883 2040 strb.w r2, [r3, #64] ; 0x40 + + /* Initialize Default I2S IrqHandler ISR */ + hi2s->IrqHandlerISR = I2S_IRQHandler; + 80051ee: 687b ldr r3, [r7, #4] + 80051f0: 4a90 ldr r2, [pc, #576] ; (8005434 ) + 80051f2: 635a str r2, [r3, #52] ; 0x34 + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + hi2s->MspInitCallback(hi2s); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_I2S_MspInit(hi2s); + 80051f4: 6878 ldr r0, [r7, #4] + 80051f6: f7fc fac3 bl 8001780 +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } + + hi2s->State = HAL_I2S_STATE_BUSY; + 80051fa: 687b ldr r3, [r7, #4] + 80051fc: 2202 movs r2, #2 + 80051fe: f883 2041 strb.w r2, [r3, #65] ; 0x41 + + /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/ + /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ + CLEAR_BIT(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \ + 8005202: 687b ldr r3, [r7, #4] + 8005204: 681b ldr r3, [r3, #0] + 8005206: 69db ldr r3, [r3, #28] + 8005208: 687a ldr r2, [r7, #4] + 800520a: 6812 ldr r2, [r2, #0] + 800520c: f423 637b bic.w r3, r3, #4016 ; 0xfb0 + 8005210: f023 030f bic.w r3, r3, #15 + 8005214: 61d3 str r3, [r2, #28] + SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \ + SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD)); + hi2s->Instance->I2SPR = 0x0002U; + 8005216: 687b ldr r3, [r7, #4] + 8005218: 681b ldr r3, [r3, #0] + 800521a: 2202 movs r2, #2 + 800521c: 621a str r2, [r3, #32] + + /*----------------------- I2SPR: I2SDIV and ODD Calculation -----------------*/ + /* If the requested audio frequency is not the default, compute the prescaler */ + if (hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT) + 800521e: 687b ldr r3, [r7, #4] + 8005220: 695b ldr r3, [r3, #20] + 8005222: 2b02 cmp r3, #2 + 8005224: d060 beq.n 80052e8 + { + /* Check the frame length (For the Prescaler computing) ********************/ + if (hi2s->Init.DataFormat == I2S_DATAFORMAT_16B) + 8005226: 687b ldr r3, [r7, #4] + 8005228: 68db ldr r3, [r3, #12] + 800522a: 2b00 cmp r3, #0 + 800522c: d102 bne.n 8005234 + { + /* Packet length is 16 bits */ + packetlength = 16U; + 800522e: 2310 movs r3, #16 + 8005230: 617b str r3, [r7, #20] + 8005232: e001 b.n 8005238 + } + else + { + /* Packet length is 32 bits */ + packetlength = 32U; + 8005234: 2320 movs r3, #32 + 8005236: 617b str r3, [r7, #20] + } + + /* I2S standard */ + if (hi2s->Init.Standard <= I2S_STANDARD_LSB) + 8005238: 687b ldr r3, [r7, #4] + 800523a: 689b ldr r3, [r3, #8] + 800523c: 2b20 cmp r3, #32 + 800523e: d802 bhi.n 8005246 + { + /* In I2S standard packet lenght is multiplied by 2 */ + packetlength = packetlength * 2U; + 8005240: 697b ldr r3, [r7, #20] + 8005242: 005b lsls r3, r3, #1 + 8005244: 617b str r3, [r7, #20] + else + { + i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S_APB2); + } +#else + i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S); + 8005246: 2001 movs r0, #1 + 8005248: f001 f9ae bl 80065a8 + 800524c: 60f8 str r0, [r7, #12] +#endif + + /* Compute the Real divider depending on the MCLK output state, with a floating point */ + if (hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE) + 800524e: 687b ldr r3, [r7, #4] + 8005250: 691b ldr r3, [r3, #16] + 8005252: f5b3 7f00 cmp.w r3, #512 ; 0x200 + 8005256: d125 bne.n 80052a4 + { + /* MCLK output is enabled */ + if (hi2s->Init.DataFormat != I2S_DATAFORMAT_16B) + 8005258: 687b ldr r3, [r7, #4] + 800525a: 68db ldr r3, [r3, #12] + 800525c: 2b00 cmp r3, #0 + 800525e: d010 beq.n 8005282 + { + tmp = (uint32_t)(((((i2sclk / (packetlength * 4U)) * 10U) / hi2s->Init.AudioFreq)) + 5U); + 8005260: 697b ldr r3, [r7, #20] + 8005262: 009b lsls r3, r3, #2 + 8005264: 68fa ldr r2, [r7, #12] + 8005266: fbb2 f2f3 udiv r2, r2, r3 + 800526a: 4613 mov r3, r2 + 800526c: 009b lsls r3, r3, #2 + 800526e: 4413 add r3, r2 + 8005270: 005b lsls r3, r3, #1 + 8005272: 461a mov r2, r3 + 8005274: 687b ldr r3, [r7, #4] + 8005276: 695b ldr r3, [r3, #20] + 8005278: fbb2 f3f3 udiv r3, r2, r3 + 800527c: 3305 adds r3, #5 + 800527e: 613b str r3, [r7, #16] + 8005280: e01f b.n 80052c2 + } + else + { + tmp = (uint32_t)(((((i2sclk / (packetlength * 8U)) * 10U) / hi2s->Init.AudioFreq)) + 5U); + 8005282: 697b ldr r3, [r7, #20] + 8005284: 00db lsls r3, r3, #3 + 8005286: 68fa ldr r2, [r7, #12] + 8005288: fbb2 f2f3 udiv r2, r2, r3 + 800528c: 4613 mov r3, r2 + 800528e: 009b lsls r3, r3, #2 + 8005290: 4413 add r3, r2 + 8005292: 005b lsls r3, r3, #1 + 8005294: 461a mov r2, r3 + 8005296: 687b ldr r3, [r7, #4] + 8005298: 695b ldr r3, [r3, #20] + 800529a: fbb2 f3f3 udiv r3, r2, r3 + 800529e: 3305 adds r3, #5 + 80052a0: 613b str r3, [r7, #16] + 80052a2: e00e b.n 80052c2 + } + } + else + { + /* MCLK output is disabled */ + tmp = (uint32_t)(((((i2sclk / packetlength) * 10U) / hi2s->Init.AudioFreq)) + 5U); + 80052a4: 68fa ldr r2, [r7, #12] + 80052a6: 697b ldr r3, [r7, #20] + 80052a8: fbb2 f2f3 udiv r2, r2, r3 + 80052ac: 4613 mov r3, r2 + 80052ae: 009b lsls r3, r3, #2 + 80052b0: 4413 add r3, r2 + 80052b2: 005b lsls r3, r3, #1 + 80052b4: 461a mov r2, r3 + 80052b6: 687b ldr r3, [r7, #4] + 80052b8: 695b ldr r3, [r3, #20] + 80052ba: fbb2 f3f3 udiv r3, r2, r3 + 80052be: 3305 adds r3, #5 + 80052c0: 613b str r3, [r7, #16] + } + + /* Remove the flatting point */ + tmp = tmp / 10U; + 80052c2: 693b ldr r3, [r7, #16] + 80052c4: 4a5c ldr r2, [pc, #368] ; (8005438 ) + 80052c6: fba2 2303 umull r2, r3, r2, r3 + 80052ca: 08db lsrs r3, r3, #3 + 80052cc: 613b str r3, [r7, #16] + + /* Check the parity of the divider */ + i2sodd = (uint32_t)(tmp & (uint32_t)1U); + 80052ce: 693b ldr r3, [r7, #16] + 80052d0: f003 0301 and.w r3, r3, #1 + 80052d4: 61bb str r3, [r7, #24] + + /* Compute the i2sdiv prescaler */ + i2sdiv = (uint32_t)((tmp - i2sodd) / 2U); + 80052d6: 693a ldr r2, [r7, #16] + 80052d8: 69bb ldr r3, [r7, #24] + 80052da: 1ad3 subs r3, r2, r3 + 80052dc: 085b lsrs r3, r3, #1 + 80052de: 61fb str r3, [r7, #28] + + /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ + i2sodd = (uint32_t)(i2sodd << 8U); + 80052e0: 69bb ldr r3, [r7, #24] + 80052e2: 021b lsls r3, r3, #8 + 80052e4: 61bb str r3, [r7, #24] + 80052e6: e003 b.n 80052f0 + } + else + { + /* Set the default values */ + i2sdiv = 2U; + 80052e8: 2302 movs r3, #2 + 80052ea: 61fb str r3, [r7, #28] + i2sodd = 0U; + 80052ec: 2300 movs r3, #0 + 80052ee: 61bb str r3, [r7, #24] + } + + /* Test if the divider is 1 or 0 or greater than 0xFF */ + if ((i2sdiv < 2U) || (i2sdiv > 0xFFU)) + 80052f0: 69fb ldr r3, [r7, #28] + 80052f2: 2b01 cmp r3, #1 + 80052f4: d902 bls.n 80052fc + 80052f6: 69fb ldr r3, [r7, #28] + 80052f8: 2bff cmp r3, #255 ; 0xff + 80052fa: d907 bls.n 800530c + { + /* Set the error code and execute error callback*/ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_PRESCALER); + 80052fc: 687b ldr r3, [r7, #4] + 80052fe: 6c5b ldr r3, [r3, #68] ; 0x44 + 8005300: f043 0210 orr.w r2, r3, #16 + 8005304: 687b ldr r3, [r7, #4] + 8005306: 645a str r2, [r3, #68] ; 0x44 + return HAL_ERROR; + 8005308: 2301 movs r3, #1 + 800530a: e08f b.n 800542c + } + + /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/ + + /* Write to SPIx I2SPR register the computed value */ + hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput)); + 800530c: 687b ldr r3, [r7, #4] + 800530e: 691a ldr r2, [r3, #16] + 8005310: 69bb ldr r3, [r7, #24] + 8005312: ea42 0103 orr.w r1, r2, r3 + 8005316: 687b ldr r3, [r7, #4] + 8005318: 681b ldr r3, [r3, #0] + 800531a: 69fa ldr r2, [r7, #28] + 800531c: 430a orrs r2, r1 + 800531e: 621a str r2, [r3, #32] + + /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ + /* And configure the I2S with the I2S_InitStruct values */ + MODIFY_REG(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \ + 8005320: 687b ldr r3, [r7, #4] + 8005322: 681b ldr r3, [r3, #0] + 8005324: 69db ldr r3, [r3, #28] + 8005326: f423 637b bic.w r3, r3, #4016 ; 0xfb0 + 800532a: f023 030f bic.w r3, r3, #15 + 800532e: 687a ldr r2, [r7, #4] + 8005330: 6851 ldr r1, [r2, #4] + 8005332: 687a ldr r2, [r7, #4] + 8005334: 6892 ldr r2, [r2, #8] + 8005336: 4311 orrs r1, r2 + 8005338: 687a ldr r2, [r7, #4] + 800533a: 68d2 ldr r2, [r2, #12] + 800533c: 4311 orrs r1, r2 + 800533e: 687a ldr r2, [r7, #4] + 8005340: 6992 ldr r2, [r2, #24] + 8005342: 430a orrs r2, r1 + 8005344: 431a orrs r2, r3 + 8005346: 687b ldr r3, [r7, #4] + 8005348: 681b ldr r3, [r3, #0] + 800534a: f442 6200 orr.w r2, r2, #2048 ; 0x800 + 800534e: 61da str r2, [r3, #28] +#if defined (SPI_I2S_FULLDUPLEX_SUPPORT) + + /* Configure the I2S extended if the full duplex mode is enabled */ + assert_param(IS_I2S_FULLDUPLEX_MODE(hi2s->Init.FullDuplexMode)); + + if (hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE) + 8005350: 687b ldr r3, [r7, #4] + 8005352: 6a1b ldr r3, [r3, #32] + 8005354: 2b01 cmp r3, #1 + 8005356: d161 bne.n 800541c + { + /* Set FullDuplex I2S IrqHandler ISR if FULLDUPLEXMODE is enabled */ + hi2s->IrqHandlerISR = HAL_I2SEx_FullDuplex_IRQHandler; + 8005358: 687b ldr r3, [r7, #4] + 800535a: 4a38 ldr r2, [pc, #224] ; (800543c ) + 800535c: 635a str r2, [r3, #52] ; 0x34 + + /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ + CLEAR_BIT(I2SxEXT(hi2s->Instance)->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \ + 800535e: 687b ldr r3, [r7, #4] + 8005360: 681b ldr r3, [r3, #0] + 8005362: 4a37 ldr r2, [pc, #220] ; (8005440 ) + 8005364: 4293 cmp r3, r2 + 8005366: d101 bne.n 800536c + 8005368: 4b36 ldr r3, [pc, #216] ; (8005444 ) + 800536a: e001 b.n 8005370 + 800536c: f04f 2340 mov.w r3, #1073758208 ; 0x40004000 + 8005370: 69db ldr r3, [r3, #28] + 8005372: 687a ldr r2, [r7, #4] + 8005374: 6812 ldr r2, [r2, #0] + 8005376: 4932 ldr r1, [pc, #200] ; (8005440 ) + 8005378: 428a cmp r2, r1 + 800537a: d101 bne.n 8005380 + 800537c: 4a31 ldr r2, [pc, #196] ; (8005444 ) + 800537e: e001 b.n 8005384 + 8005380: f04f 2240 mov.w r2, #1073758208 ; 0x40004000 + 8005384: f423 637b bic.w r3, r3, #4016 ; 0xfb0 + 8005388: f023 030f bic.w r3, r3, #15 + 800538c: 61d3 str r3, [r2, #28] + SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \ + SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD)); + I2SxEXT(hi2s->Instance)->I2SPR = 2U; + 800538e: 687b ldr r3, [r7, #4] + 8005390: 681b ldr r3, [r3, #0] + 8005392: 4a2b ldr r2, [pc, #172] ; (8005440 ) + 8005394: 4293 cmp r3, r2 + 8005396: d101 bne.n 800539c + 8005398: 4b2a ldr r3, [pc, #168] ; (8005444 ) + 800539a: e001 b.n 80053a0 + 800539c: f04f 2340 mov.w r3, #1073758208 ; 0x40004000 + 80053a0: 2202 movs r2, #2 + 80053a2: 621a str r2, [r3, #32] + + /* Get the I2SCFGR register value */ + tmpreg = I2SxEXT(hi2s->Instance)->I2SCFGR; + 80053a4: 687b ldr r3, [r7, #4] + 80053a6: 681b ldr r3, [r3, #0] + 80053a8: 4a25 ldr r2, [pc, #148] ; (8005440 ) + 80053aa: 4293 cmp r3, r2 + 80053ac: d101 bne.n 80053b2 + 80053ae: 4b25 ldr r3, [pc, #148] ; (8005444 ) + 80053b0: e001 b.n 80053b6 + 80053b2: f04f 2340 mov.w r3, #1073758208 ; 0x40004000 + 80053b6: 69db ldr r3, [r3, #28] + 80053b8: 817b strh r3, [r7, #10] + + /* Get the mode to be configured for the extended I2S */ + if ((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX)) + 80053ba: 687b ldr r3, [r7, #4] + 80053bc: 685b ldr r3, [r3, #4] + 80053be: f5b3 7f00 cmp.w r3, #512 ; 0x200 + 80053c2: d003 beq.n 80053cc + 80053c4: 687b ldr r3, [r7, #4] + 80053c6: 685b ldr r3, [r3, #4] + 80053c8: 2b00 cmp r3, #0 + 80053ca: d103 bne.n 80053d4 + { + tmp = I2S_MODE_SLAVE_RX; + 80053cc: f44f 7380 mov.w r3, #256 ; 0x100 + 80053d0: 613b str r3, [r7, #16] + 80053d2: e001 b.n 80053d8 + } + else /* I2S_MODE_MASTER_RX || I2S_MODE_SLAVE_RX */ + { + tmp = I2S_MODE_SLAVE_TX; + 80053d4: 2300 movs r3, #0 + 80053d6: 613b str r3, [r7, #16] + } + + /* Configure the I2S Slave with the I2S Master parameter values */ + tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(tmp | \ + 80053d8: 693b ldr r3, [r7, #16] + 80053da: b29a uxth r2, r3 + (uint16_t)(hi2s->Init.Standard | (uint16_t)(hi2s->Init.DataFormat | \ + 80053dc: 687b ldr r3, [r7, #4] + 80053de: 689b ldr r3, [r3, #8] + 80053e0: b299 uxth r1, r3 + 80053e2: 687b ldr r3, [r7, #4] + 80053e4: 68db ldr r3, [r3, #12] + 80053e6: b298 uxth r0, r3 + (uint16_t)hi2s->Init.CPOL)))); + 80053e8: 687b ldr r3, [r7, #4] + 80053ea: 699b ldr r3, [r3, #24] + 80053ec: b29b uxth r3, r3 + (uint16_t)(hi2s->Init.Standard | (uint16_t)(hi2s->Init.DataFormat | \ + 80053ee: 4303 orrs r3, r0 + 80053f0: b29b uxth r3, r3 + 80053f2: 430b orrs r3, r1 + 80053f4: b29b uxth r3, r3 + tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(tmp | \ + 80053f6: 4313 orrs r3, r2 + 80053f8: b29a uxth r2, r3 + 80053fa: 897b ldrh r3, [r7, #10] + 80053fc: 4313 orrs r3, r2 + 80053fe: b29b uxth r3, r3 + 8005400: f443 6300 orr.w r3, r3, #2048 ; 0x800 + 8005404: 817b strh r3, [r7, #10] + + /* Write to SPIx I2SCFGR */ + WRITE_REG(I2SxEXT(hi2s->Instance)->I2SCFGR, tmpreg); + 8005406: 687b ldr r3, [r7, #4] + 8005408: 681b ldr r3, [r3, #0] + 800540a: 4a0d ldr r2, [pc, #52] ; (8005440 ) + 800540c: 4293 cmp r3, r2 + 800540e: d101 bne.n 8005414 + 8005410: 4b0c ldr r3, [pc, #48] ; (8005444 ) + 8005412: e001 b.n 8005418 + 8005414: f04f 2340 mov.w r3, #1073758208 ; 0x40004000 + 8005418: 897a ldrh r2, [r7, #10] + 800541a: 61da str r2, [r3, #28] + } +#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */ + + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + 800541c: 687b ldr r3, [r7, #4] + 800541e: 2200 movs r2, #0 + 8005420: 645a str r2, [r3, #68] ; 0x44 + hi2s->State = HAL_I2S_STATE_READY; + 8005422: 687b ldr r3, [r7, #4] + 8005424: 2201 movs r2, #1 + 8005426: f883 2041 strb.w r2, [r3, #65] ; 0x41 + + return HAL_OK; + 800542a: 2300 movs r3, #0 +} + 800542c: 4618 mov r0, r3 + 800542e: 3720 adds r7, #32 + 8005430: 46bd mov sp, r7 + 8005432: bd80 pop {r7, pc} + 8005434: 0800553f .word 0x0800553f + 8005438: cccccccd .word 0xcccccccd + 800543c: 08005655 .word 0x08005655 + 8005440: 40003800 .word 0x40003800 + 8005444: 40003400 .word 0x40003400 + +08005448 : + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +__weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s) +{ + 8005448: b480 push {r7} + 800544a: b083 sub sp, #12 + 800544c: af00 add r7, sp, #0 + 800544e: 6078 str r0, [r7, #4] + UNUSED(hi2s); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2S_TxCpltCallback could be implemented in the user file + */ +} + 8005450: bf00 nop + 8005452: 370c adds r7, #12 + 8005454: 46bd mov sp, r7 + 8005456: f85d 7b04 ldr.w r7, [sp], #4 + 800545a: 4770 bx lr + +0800545c : + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +__weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s) +{ + 800545c: b480 push {r7} + 800545e: b083 sub sp, #12 + 8005460: af00 add r7, sp, #0 + 8005462: 6078 str r0, [r7, #4] + UNUSED(hi2s); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2S_RxCpltCallback could be implemented in the user file + */ +} + 8005464: bf00 nop + 8005466: 370c adds r7, #12 + 8005468: 46bd mov sp, r7 + 800546a: f85d 7b04 ldr.w r7, [sp], #4 + 800546e: 4770 bx lr + +08005470 : + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +__weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s) +{ + 8005470: b480 push {r7} + 8005472: b083 sub sp, #12 + 8005474: af00 add r7, sp, #0 + 8005476: 6078 str r0, [r7, #4] + UNUSED(hi2s); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2S_ErrorCallback could be implemented in the user file + */ +} + 8005478: bf00 nop + 800547a: 370c adds r7, #12 + 800547c: 46bd mov sp, r7 + 800547e: f85d 7b04 ldr.w r7, [sp], #4 + 8005482: 4770 bx lr + +08005484 : + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s) +{ + 8005484: b580 push {r7, lr} + 8005486: b082 sub sp, #8 + 8005488: af00 add r7, sp, #0 + 800548a: 6078 str r0, [r7, #4] + /* Transmit data */ + hi2s->Instance->DR = (*hi2s->pTxBuffPtr); + 800548c: 687b ldr r3, [r7, #4] + 800548e: 6a5b ldr r3, [r3, #36] ; 0x24 + 8005490: 881a ldrh r2, [r3, #0] + 8005492: 687b ldr r3, [r7, #4] + 8005494: 681b ldr r3, [r3, #0] + 8005496: 60da str r2, [r3, #12] + hi2s->pTxBuffPtr++; + 8005498: 687b ldr r3, [r7, #4] + 800549a: 6a5b ldr r3, [r3, #36] ; 0x24 + 800549c: 1c9a adds r2, r3, #2 + 800549e: 687b ldr r3, [r7, #4] + 80054a0: 625a str r2, [r3, #36] ; 0x24 + hi2s->TxXferCount--; + 80054a2: 687b ldr r3, [r7, #4] + 80054a4: 8d5b ldrh r3, [r3, #42] ; 0x2a + 80054a6: b29b uxth r3, r3 + 80054a8: 3b01 subs r3, #1 + 80054aa: b29a uxth r2, r3 + 80054ac: 687b ldr r3, [r7, #4] + 80054ae: 855a strh r2, [r3, #42] ; 0x2a + + if (hi2s->TxXferCount == 0U) + 80054b0: 687b ldr r3, [r7, #4] + 80054b2: 8d5b ldrh r3, [r3, #42] ; 0x2a + 80054b4: b29b uxth r3, r3 + 80054b6: 2b00 cmp r3, #0 + 80054b8: d10e bne.n 80054d8 + { + /* Disable TXE and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); + 80054ba: 687b ldr r3, [r7, #4] + 80054bc: 681b ldr r3, [r3, #0] + 80054be: 685a ldr r2, [r3, #4] + 80054c0: 687b ldr r3, [r7, #4] + 80054c2: 681b ldr r3, [r3, #0] + 80054c4: f022 02a0 bic.w r2, r2, #160 ; 0xa0 + 80054c8: 605a str r2, [r3, #4] + + hi2s->State = HAL_I2S_STATE_READY; + 80054ca: 687b ldr r3, [r7, #4] + 80054cc: 2201 movs r2, #1 + 80054ce: f883 2041 strb.w r2, [r3, #65] ; 0x41 + /* Call user Tx complete callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + hi2s->TxCpltCallback(hi2s); +#else + HAL_I2S_TxCpltCallback(hi2s); + 80054d2: 6878 ldr r0, [r7, #4] + 80054d4: f7ff ffb8 bl 8005448 +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } +} + 80054d8: bf00 nop + 80054da: 3708 adds r7, #8 + 80054dc: 46bd mov sp, r7 + 80054de: bd80 pop {r7, pc} + +080054e0 : + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s) +{ + 80054e0: b580 push {r7, lr} + 80054e2: b082 sub sp, #8 + 80054e4: af00 add r7, sp, #0 + 80054e6: 6078 str r0, [r7, #4] + /* Receive data */ + (*hi2s->pRxBuffPtr) = (uint16_t)hi2s->Instance->DR; + 80054e8: 687b ldr r3, [r7, #4] + 80054ea: 681b ldr r3, [r3, #0] + 80054ec: 68da ldr r2, [r3, #12] + 80054ee: 687b ldr r3, [r7, #4] + 80054f0: 6adb ldr r3, [r3, #44] ; 0x2c + 80054f2: b292 uxth r2, r2 + 80054f4: 801a strh r2, [r3, #0] + hi2s->pRxBuffPtr++; + 80054f6: 687b ldr r3, [r7, #4] + 80054f8: 6adb ldr r3, [r3, #44] ; 0x2c + 80054fa: 1c9a adds r2, r3, #2 + 80054fc: 687b ldr r3, [r7, #4] + 80054fe: 62da str r2, [r3, #44] ; 0x2c + hi2s->RxXferCount--; + 8005500: 687b ldr r3, [r7, #4] + 8005502: 8e5b ldrh r3, [r3, #50] ; 0x32 + 8005504: b29b uxth r3, r3 + 8005506: 3b01 subs r3, #1 + 8005508: b29a uxth r2, r3 + 800550a: 687b ldr r3, [r7, #4] + 800550c: 865a strh r2, [r3, #50] ; 0x32 + + if (hi2s->RxXferCount == 0U) + 800550e: 687b ldr r3, [r7, #4] + 8005510: 8e5b ldrh r3, [r3, #50] ; 0x32 + 8005512: b29b uxth r3, r3 + 8005514: 2b00 cmp r3, #0 + 8005516: d10e bne.n 8005536 + { + /* Disable RXNE and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); + 8005518: 687b ldr r3, [r7, #4] + 800551a: 681b ldr r3, [r3, #0] + 800551c: 685a ldr r2, [r3, #4] + 800551e: 687b ldr r3, [r7, #4] + 8005520: 681b ldr r3, [r3, #0] + 8005522: f022 0260 bic.w r2, r2, #96 ; 0x60 + 8005526: 605a str r2, [r3, #4] + + hi2s->State = HAL_I2S_STATE_READY; + 8005528: 687b ldr r3, [r7, #4] + 800552a: 2201 movs r2, #1 + 800552c: f883 2041 strb.w r2, [r3, #65] ; 0x41 + /* Call user Rx complete callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + hi2s->RxCpltCallback(hi2s); +#else + HAL_I2S_RxCpltCallback(hi2s); + 8005530: 6878 ldr r0, [r7, #4] + 8005532: f7ff ff93 bl 800545c +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } +} + 8005536: bf00 nop + 8005538: 3708 adds r7, #8 + 800553a: 46bd mov sp, r7 + 800553c: bd80 pop {r7, pc} + +0800553e : + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +static void I2S_IRQHandler(I2S_HandleTypeDef *hi2s) +{ + 800553e: b580 push {r7, lr} + 8005540: b086 sub sp, #24 + 8005542: af00 add r7, sp, #0 + 8005544: 6078 str r0, [r7, #4] + __IO uint32_t i2ssr = hi2s->Instance->SR; + 8005546: 687b ldr r3, [r7, #4] + 8005548: 681b ldr r3, [r3, #0] + 800554a: 689b ldr r3, [r3, #8] + 800554c: 617b str r3, [r7, #20] + + if (hi2s->State == HAL_I2S_STATE_BUSY_RX) + 800554e: 687b ldr r3, [r7, #4] + 8005550: f893 3041 ldrb.w r3, [r3, #65] ; 0x41 + 8005554: b2db uxtb r3, r3 + 8005556: 2b04 cmp r3, #4 + 8005558: d13a bne.n 80055d0 + { + /* I2S in mode Receiver ------------------------------------------------*/ + if (((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET)) + 800555a: 697b ldr r3, [r7, #20] + 800555c: f003 0301 and.w r3, r3, #1 + 8005560: 2b01 cmp r3, #1 + 8005562: d109 bne.n 8005578 + 8005564: 687b ldr r3, [r7, #4] + 8005566: 681b ldr r3, [r3, #0] + 8005568: 685b ldr r3, [r3, #4] + 800556a: f003 0340 and.w r3, r3, #64 ; 0x40 + 800556e: 2b40 cmp r3, #64 ; 0x40 + 8005570: d102 bne.n 8005578 + { + I2S_Receive_IT(hi2s); + 8005572: 6878 ldr r0, [r7, #4] + 8005574: f7ff ffb4 bl 80054e0 + } + + /* I2S Overrun error interrupt occurred -------------------------------------*/ + if (((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) + 8005578: 697b ldr r3, [r7, #20] + 800557a: f003 0340 and.w r3, r3, #64 ; 0x40 + 800557e: 2b40 cmp r3, #64 ; 0x40 + 8005580: d126 bne.n 80055d0 + 8005582: 687b ldr r3, [r7, #4] + 8005584: 681b ldr r3, [r3, #0] + 8005586: 685b ldr r3, [r3, #4] + 8005588: f003 0320 and.w r3, r3, #32 + 800558c: 2b20 cmp r3, #32 + 800558e: d11f bne.n 80055d0 + { + /* Disable RXNE and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); + 8005590: 687b ldr r3, [r7, #4] + 8005592: 681b ldr r3, [r3, #0] + 8005594: 685a ldr r2, [r3, #4] + 8005596: 687b ldr r3, [r7, #4] + 8005598: 681b ldr r3, [r3, #0] + 800559a: f022 0260 bic.w r2, r2, #96 ; 0x60 + 800559e: 605a str r2, [r3, #4] + + /* Clear Overrun flag */ + __HAL_I2S_CLEAR_OVRFLAG(hi2s); + 80055a0: 2300 movs r3, #0 + 80055a2: 613b str r3, [r7, #16] + 80055a4: 687b ldr r3, [r7, #4] + 80055a6: 681b ldr r3, [r3, #0] + 80055a8: 68db ldr r3, [r3, #12] + 80055aa: 613b str r3, [r7, #16] + 80055ac: 687b ldr r3, [r7, #4] + 80055ae: 681b ldr r3, [r3, #0] + 80055b0: 689b ldr r3, [r3, #8] + 80055b2: 613b str r3, [r7, #16] + 80055b4: 693b ldr r3, [r7, #16] + + /* Set the I2S State ready */ + hi2s->State = HAL_I2S_STATE_READY; + 80055b6: 687b ldr r3, [r7, #4] + 80055b8: 2201 movs r2, #1 + 80055ba: f883 2041 strb.w r2, [r3, #65] ; 0x41 + + + /* Set the error code and execute error callback*/ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR); + 80055be: 687b ldr r3, [r7, #4] + 80055c0: 6c5b ldr r3, [r3, #68] ; 0x44 + 80055c2: f043 0202 orr.w r2, r3, #2 + 80055c6: 687b ldr r3, [r7, #4] + 80055c8: 645a str r2, [r3, #68] ; 0x44 + /* Call user error callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + hi2s->ErrorCallback(hi2s); +#else + HAL_I2S_ErrorCallback(hi2s); + 80055ca: 6878 ldr r0, [r7, #4] + 80055cc: f7ff ff50 bl 8005470 +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } + } + + if (hi2s->State == HAL_I2S_STATE_BUSY_TX) + 80055d0: 687b ldr r3, [r7, #4] + 80055d2: f893 3041 ldrb.w r3, [r3, #65] ; 0x41 + 80055d6: b2db uxtb r3, r3 + 80055d8: 2b03 cmp r3, #3 + 80055da: d136 bne.n 800564a + { + /* I2S in mode Transmitter -----------------------------------------------*/ + if (((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET)) + 80055dc: 697b ldr r3, [r7, #20] + 80055de: f003 0302 and.w r3, r3, #2 + 80055e2: 2b02 cmp r3, #2 + 80055e4: d109 bne.n 80055fa + 80055e6: 687b ldr r3, [r7, #4] + 80055e8: 681b ldr r3, [r3, #0] + 80055ea: 685b ldr r3, [r3, #4] + 80055ec: f003 0380 and.w r3, r3, #128 ; 0x80 + 80055f0: 2b80 cmp r3, #128 ; 0x80 + 80055f2: d102 bne.n 80055fa + { + I2S_Transmit_IT(hi2s); + 80055f4: 6878 ldr r0, [r7, #4] + 80055f6: f7ff ff45 bl 8005484 + } + + /* I2S Underrun error interrupt occurred --------------------------------*/ + if (((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) + 80055fa: 697b ldr r3, [r7, #20] + 80055fc: f003 0308 and.w r3, r3, #8 + 8005600: 2b08 cmp r3, #8 + 8005602: d122 bne.n 800564a + 8005604: 687b ldr r3, [r7, #4] + 8005606: 681b ldr r3, [r3, #0] + 8005608: 685b ldr r3, [r3, #4] + 800560a: f003 0320 and.w r3, r3, #32 + 800560e: 2b20 cmp r3, #32 + 8005610: d11b bne.n 800564a + { + /* Disable TXE and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); + 8005612: 687b ldr r3, [r7, #4] + 8005614: 681b ldr r3, [r3, #0] + 8005616: 685a ldr r2, [r3, #4] + 8005618: 687b ldr r3, [r7, #4] + 800561a: 681b ldr r3, [r3, #0] + 800561c: f022 02a0 bic.w r2, r2, #160 ; 0xa0 + 8005620: 605a str r2, [r3, #4] + + /* Clear Underrun flag */ + __HAL_I2S_CLEAR_UDRFLAG(hi2s); + 8005622: 2300 movs r3, #0 + 8005624: 60fb str r3, [r7, #12] + 8005626: 687b ldr r3, [r7, #4] + 8005628: 681b ldr r3, [r3, #0] + 800562a: 689b ldr r3, [r3, #8] + 800562c: 60fb str r3, [r7, #12] + 800562e: 68fb ldr r3, [r7, #12] + + /* Set the I2S State ready */ + hi2s->State = HAL_I2S_STATE_READY; + 8005630: 687b ldr r3, [r7, #4] + 8005632: 2201 movs r2, #1 + 8005634: f883 2041 strb.w r2, [r3, #65] ; 0x41 + + /* Set the error code and execute error callback*/ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR); + 8005638: 687b ldr r3, [r7, #4] + 800563a: 6c5b ldr r3, [r3, #68] ; 0x44 + 800563c: f043 0204 orr.w r2, r3, #4 + 8005640: 687b ldr r3, [r7, #4] + 8005642: 645a str r2, [r3, #68] ; 0x44 + /* Call user error callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + hi2s->ErrorCallback(hi2s); +#else + HAL_I2S_ErrorCallback(hi2s); + 8005644: 6878 ldr r0, [r7, #4] + 8005646: f7ff ff13 bl 8005470 +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } + } +} + 800564a: bf00 nop + 800564c: 3718 adds r7, #24 + 800564e: 46bd mov sp, r7 + 8005650: bd80 pop {r7, pc} + ... + +08005654 : + * @brief This function handles I2S/I2Sext interrupt requests in full-duplex mode. + * @param hi2s I2S handle + * @retval HAL status + */ +void HAL_I2SEx_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s) +{ + 8005654: b580 push {r7, lr} + 8005656: b088 sub sp, #32 + 8005658: af00 add r7, sp, #0 + 800565a: 6078 str r0, [r7, #4] + __IO uint32_t i2ssr = hi2s->Instance->SR; + 800565c: 687b ldr r3, [r7, #4] + 800565e: 681b ldr r3, [r3, #0] + 8005660: 689b ldr r3, [r3, #8] + 8005662: 61fb str r3, [r7, #28] + __IO uint32_t i2sextsr = I2SxEXT(hi2s->Instance)->SR; + 8005664: 687b ldr r3, [r7, #4] + 8005666: 681b ldr r3, [r3, #0] + 8005668: 4aa2 ldr r2, [pc, #648] ; (80058f4 ) + 800566a: 4293 cmp r3, r2 + 800566c: d101 bne.n 8005672 + 800566e: 4ba2 ldr r3, [pc, #648] ; (80058f8 ) + 8005670: e001 b.n 8005676 + 8005672: f04f 2340 mov.w r3, #1073758208 ; 0x40004000 + 8005676: 689b ldr r3, [r3, #8] + 8005678: 61bb str r3, [r7, #24] + __IO uint32_t i2scr2 = hi2s->Instance->CR2; + 800567a: 687b ldr r3, [r7, #4] + 800567c: 681b ldr r3, [r3, #0] + 800567e: 685b ldr r3, [r3, #4] + 8005680: 617b str r3, [r7, #20] + __IO uint32_t i2sextcr2 = I2SxEXT(hi2s->Instance)->CR2; + 8005682: 687b ldr r3, [r7, #4] + 8005684: 681b ldr r3, [r3, #0] + 8005686: 4a9b ldr r2, [pc, #620] ; (80058f4 ) + 8005688: 4293 cmp r3, r2 + 800568a: d101 bne.n 8005690 + 800568c: 4b9a ldr r3, [pc, #616] ; (80058f8 ) + 800568e: e001 b.n 8005694 + 8005690: f04f 2340 mov.w r3, #1073758208 ; 0x40004000 + 8005694: 685b ldr r3, [r3, #4] + 8005696: 613b str r3, [r7, #16] + + /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */ + if ((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX)) + 8005698: 687b ldr r3, [r7, #4] + 800569a: 685b ldr r3, [r3, #4] + 800569c: f5b3 7f00 cmp.w r3, #512 ; 0x200 + 80056a0: d004 beq.n 80056ac + 80056a2: 687b ldr r3, [r7, #4] + 80056a4: 685b ldr r3, [r3, #4] + 80056a6: 2b00 cmp r3, #0 + 80056a8: f040 8099 bne.w 80057de + { + /* I2S in mode Transmitter -------------------------------------------------*/ + if (((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && ((i2scr2 & I2S_IT_TXE) != RESET)) + 80056ac: 69fb ldr r3, [r7, #28] + 80056ae: f003 0302 and.w r3, r3, #2 + 80056b2: 2b02 cmp r3, #2 + 80056b4: d107 bne.n 80056c6 + 80056b6: 697b ldr r3, [r7, #20] + 80056b8: f003 0380 and.w r3, r3, #128 ; 0x80 + 80056bc: 2b00 cmp r3, #0 + 80056be: d002 beq.n 80056c6 + { + /* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX, + the I2S TXE interrupt will be generated to manage the full-duplex transmit phase. */ + I2SEx_TxISR_I2S(hi2s); + 80056c0: 6878 ldr r0, [r7, #4] + 80056c2: f000 f925 bl 8005910 + } + + /* I2Sext in mode Receiver -----------------------------------------------*/ + if (((i2sextsr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && ((i2sextcr2 & I2S_IT_RXNE) != RESET)) + 80056c6: 69bb ldr r3, [r7, #24] + 80056c8: f003 0301 and.w r3, r3, #1 + 80056cc: 2b01 cmp r3, #1 + 80056ce: d107 bne.n 80056e0 + 80056d0: 693b ldr r3, [r7, #16] + 80056d2: f003 0340 and.w r3, r3, #64 ; 0x40 + 80056d6: 2b00 cmp r3, #0 + 80056d8: d002 beq.n 80056e0 + { + /* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX, + the I2Sext RXNE interrupt will be generated to manage the full-duplex receive phase. */ + I2SEx_RxISR_I2SExt(hi2s); + 80056da: 6878 ldr r0, [r7, #4] + 80056dc: f000 f9c8 bl 8005a70 + } + + /* I2Sext Overrun error interrupt occurred --------------------------------*/ + if (((i2sextsr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && ((i2sextcr2 & I2S_IT_ERR) != RESET)) + 80056e0: 69bb ldr r3, [r7, #24] + 80056e2: f003 0340 and.w r3, r3, #64 ; 0x40 + 80056e6: 2b40 cmp r3, #64 ; 0x40 + 80056e8: d13a bne.n 8005760 + 80056ea: 693b ldr r3, [r7, #16] + 80056ec: f003 0320 and.w r3, r3, #32 + 80056f0: 2b00 cmp r3, #0 + 80056f2: d035 beq.n 8005760 + { + /* Disable RXNE and ERR interrupt */ + __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); + 80056f4: 687b ldr r3, [r7, #4] + 80056f6: 681b ldr r3, [r3, #0] + 80056f8: 4a7e ldr r2, [pc, #504] ; (80058f4 ) + 80056fa: 4293 cmp r3, r2 + 80056fc: d101 bne.n 8005702 + 80056fe: 4b7e ldr r3, [pc, #504] ; (80058f8 ) + 8005700: e001 b.n 8005706 + 8005702: f04f 2340 mov.w r3, #1073758208 ; 0x40004000 + 8005706: 685a ldr r2, [r3, #4] + 8005708: 687b ldr r3, [r7, #4] + 800570a: 681b ldr r3, [r3, #0] + 800570c: 4979 ldr r1, [pc, #484] ; (80058f4 ) + 800570e: 428b cmp r3, r1 + 8005710: d101 bne.n 8005716 + 8005712: 4b79 ldr r3, [pc, #484] ; (80058f8 ) + 8005714: e001 b.n 800571a + 8005716: f04f 2340 mov.w r3, #1073758208 ; 0x40004000 + 800571a: f022 0260 bic.w r2, r2, #96 ; 0x60 + 800571e: 605a str r2, [r3, #4] + + /* Disable TXE and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); + 8005720: 687b ldr r3, [r7, #4] + 8005722: 681b ldr r3, [r3, #0] + 8005724: 685a ldr r2, [r3, #4] + 8005726: 687b ldr r3, [r7, #4] + 8005728: 681b ldr r3, [r3, #0] + 800572a: f022 02a0 bic.w r2, r2, #160 ; 0xa0 + 800572e: 605a str r2, [r3, #4] + + /* Clear Overrun flag */ + __HAL_I2S_CLEAR_OVRFLAG(hi2s); + 8005730: 2300 movs r3, #0 + 8005732: 60fb str r3, [r7, #12] + 8005734: 687b ldr r3, [r7, #4] + 8005736: 681b ldr r3, [r3, #0] + 8005738: 68db ldr r3, [r3, #12] + 800573a: 60fb str r3, [r7, #12] + 800573c: 687b ldr r3, [r7, #4] + 800573e: 681b ldr r3, [r3, #0] + 8005740: 689b ldr r3, [r3, #8] + 8005742: 60fb str r3, [r7, #12] + 8005744: 68fb ldr r3, [r7, #12] + + /* Set the I2S State ready */ + hi2s->State = HAL_I2S_STATE_READY; + 8005746: 687b ldr r3, [r7, #4] + 8005748: 2201 movs r2, #1 + 800574a: f883 2041 strb.w r2, [r3, #65] ; 0x41 + + /* Set the error code and execute error callback*/ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR); + 800574e: 687b ldr r3, [r7, #4] + 8005750: 6c5b ldr r3, [r3, #68] ; 0x44 + 8005752: f043 0202 orr.w r2, r3, #2 + 8005756: 687b ldr r3, [r7, #4] + 8005758: 645a str r2, [r3, #68] ; 0x44 + /* Call user error callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + hi2s->ErrorCallback(hi2s); +#else + HAL_I2S_ErrorCallback(hi2s); + 800575a: 6878 ldr r0, [r7, #4] + 800575c: f7ff fe88 bl 8005470 +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } + + /* I2S Underrun error interrupt occurred ----------------------------------*/ + if (((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && ((i2scr2 & I2S_IT_ERR) != RESET)) + 8005760: 69fb ldr r3, [r7, #28] + 8005762: f003 0308 and.w r3, r3, #8 + 8005766: 2b08 cmp r3, #8 + 8005768: f040 80be bne.w 80058e8 + 800576c: 697b ldr r3, [r7, #20] + 800576e: f003 0320 and.w r3, r3, #32 + 8005772: 2b00 cmp r3, #0 + 8005774: f000 80b8 beq.w 80058e8 + { + /* Disable TXE and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); + 8005778: 687b ldr r3, [r7, #4] + 800577a: 681b ldr r3, [r3, #0] + 800577c: 685a ldr r2, [r3, #4] + 800577e: 687b ldr r3, [r7, #4] + 8005780: 681b ldr r3, [r3, #0] + 8005782: f022 02a0 bic.w r2, r2, #160 ; 0xa0 + 8005786: 605a str r2, [r3, #4] + + /* Disable RXNE and ERR interrupt */ + __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); + 8005788: 687b ldr r3, [r7, #4] + 800578a: 681b ldr r3, [r3, #0] + 800578c: 4a59 ldr r2, [pc, #356] ; (80058f4 ) + 800578e: 4293 cmp r3, r2 + 8005790: d101 bne.n 8005796 + 8005792: 4b59 ldr r3, [pc, #356] ; (80058f8 ) + 8005794: e001 b.n 800579a + 8005796: f04f 2340 mov.w r3, #1073758208 ; 0x40004000 + 800579a: 685a ldr r2, [r3, #4] + 800579c: 687b ldr r3, [r7, #4] + 800579e: 681b ldr r3, [r3, #0] + 80057a0: 4954 ldr r1, [pc, #336] ; (80058f4 ) + 80057a2: 428b cmp r3, r1 + 80057a4: d101 bne.n 80057aa + 80057a6: 4b54 ldr r3, [pc, #336] ; (80058f8 ) + 80057a8: e001 b.n 80057ae + 80057aa: f04f 2340 mov.w r3, #1073758208 ; 0x40004000 + 80057ae: f022 0260 bic.w r2, r2, #96 ; 0x60 + 80057b2: 605a str r2, [r3, #4] + + /* Clear underrun flag */ + __HAL_I2S_CLEAR_UDRFLAG(hi2s); + 80057b4: 2300 movs r3, #0 + 80057b6: 60bb str r3, [r7, #8] + 80057b8: 687b ldr r3, [r7, #4] + 80057ba: 681b ldr r3, [r3, #0] + 80057bc: 689b ldr r3, [r3, #8] + 80057be: 60bb str r3, [r7, #8] + 80057c0: 68bb ldr r3, [r7, #8] + + /* Set the I2S State ready */ + hi2s->State = HAL_I2S_STATE_READY; + 80057c2: 687b ldr r3, [r7, #4] + 80057c4: 2201 movs r2, #1 + 80057c6: f883 2041 strb.w r2, [r3, #65] ; 0x41 + + /* Set the error code and execute error callback*/ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR); + 80057ca: 687b ldr r3, [r7, #4] + 80057cc: 6c5b ldr r3, [r3, #68] ; 0x44 + 80057ce: f043 0204 orr.w r2, r3, #4 + 80057d2: 687b ldr r3, [r7, #4] + 80057d4: 645a str r2, [r3, #68] ; 0x44 + /* Call user error callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + hi2s->ErrorCallback(hi2s); +#else + HAL_I2S_ErrorCallback(hi2s); + 80057d6: 6878 ldr r0, [r7, #4] + 80057d8: f7ff fe4a bl 8005470 + if (((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && ((i2scr2 & I2S_IT_ERR) != RESET)) + 80057dc: e084 b.n 80058e8 + } + /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */ + else + { + /* I2Sext in mode Transmitter ----------------------------------------------*/ + if (((i2sextsr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && ((i2sextcr2 & I2S_IT_TXE) != RESET)) + 80057de: 69bb ldr r3, [r7, #24] + 80057e0: f003 0302 and.w r3, r3, #2 + 80057e4: 2b02 cmp r3, #2 + 80057e6: d107 bne.n 80057f8 + 80057e8: 693b ldr r3, [r7, #16] + 80057ea: f003 0380 and.w r3, r3, #128 ; 0x80 + 80057ee: 2b00 cmp r3, #0 + 80057f0: d002 beq.n 80057f8 + { + /* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX, + the I2Sext TXE interrupt will be generated to manage the full-duplex transmit phase. */ + I2SEx_TxISR_I2SExt(hi2s); + 80057f2: 6878 ldr r0, [r7, #4] + 80057f4: f000 f8be bl 8005974 + } + + /* I2S in mode Receiver --------------------------------------------------*/ + if (((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && ((i2scr2 & I2S_IT_RXNE) != RESET)) + 80057f8: 69fb ldr r3, [r7, #28] + 80057fa: f003 0301 and.w r3, r3, #1 + 80057fe: 2b01 cmp r3, #1 + 8005800: d107 bne.n 8005812 + 8005802: 697b ldr r3, [r7, #20] + 8005804: f003 0340 and.w r3, r3, #64 ; 0x40 + 8005808: 2b00 cmp r3, #0 + 800580a: d002 beq.n 8005812 + { + /* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX, + the I2S RXNE interrupt will be generated to manage the full-duplex receive phase. */ + I2SEx_RxISR_I2S(hi2s); + 800580c: 6878 ldr r0, [r7, #4] + 800580e: f000 f8fd bl 8005a0c + } + + /* I2S Overrun error interrupt occurred -------------------------------------*/ + if (((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && ((i2scr2 & I2S_IT_ERR) != RESET)) + 8005812: 69fb ldr r3, [r7, #28] + 8005814: f003 0340 and.w r3, r3, #64 ; 0x40 + 8005818: 2b40 cmp r3, #64 ; 0x40 + 800581a: d12f bne.n 800587c + 800581c: 697b ldr r3, [r7, #20] + 800581e: f003 0320 and.w r3, r3, #32 + 8005822: 2b00 cmp r3, #0 + 8005824: d02a beq.n 800587c + { + /* Disable RXNE and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); + 8005826: 687b ldr r3, [r7, #4] + 8005828: 681b ldr r3, [r3, #0] + 800582a: 685a ldr r2, [r3, #4] + 800582c: 687b ldr r3, [r7, #4] + 800582e: 681b ldr r3, [r3, #0] + 8005830: f022 0260 bic.w r2, r2, #96 ; 0x60 + 8005834: 605a str r2, [r3, #4] + + /* Disable TXE and ERR interrupt */ + __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); + 8005836: 687b ldr r3, [r7, #4] + 8005838: 681b ldr r3, [r3, #0] + 800583a: 4a2e ldr r2, [pc, #184] ; (80058f4 ) + 800583c: 4293 cmp r3, r2 + 800583e: d101 bne.n 8005844 + 8005840: 4b2d ldr r3, [pc, #180] ; (80058f8 ) + 8005842: e001 b.n 8005848 + 8005844: f04f 2340 mov.w r3, #1073758208 ; 0x40004000 + 8005848: 685a ldr r2, [r3, #4] + 800584a: 687b ldr r3, [r7, #4] + 800584c: 681b ldr r3, [r3, #0] + 800584e: 4929 ldr r1, [pc, #164] ; (80058f4 ) + 8005850: 428b cmp r3, r1 + 8005852: d101 bne.n 8005858 + 8005854: 4b28 ldr r3, [pc, #160] ; (80058f8 ) + 8005856: e001 b.n 800585c + 8005858: f04f 2340 mov.w r3, #1073758208 ; 0x40004000 + 800585c: f022 02a0 bic.w r2, r2, #160 ; 0xa0 + 8005860: 605a str r2, [r3, #4] + + /* Set the I2S State ready */ + hi2s->State = HAL_I2S_STATE_READY; + 8005862: 687b ldr r3, [r7, #4] + 8005864: 2201 movs r2, #1 + 8005866: f883 2041 strb.w r2, [r3, #65] ; 0x41 + + /* Set the error code and execute error callback*/ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR); + 800586a: 687b ldr r3, [r7, #4] + 800586c: 6c5b ldr r3, [r3, #68] ; 0x44 + 800586e: f043 0202 orr.w r2, r3, #2 + 8005872: 687b ldr r3, [r7, #4] + 8005874: 645a str r2, [r3, #68] ; 0x44 + /* Call user error callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + hi2s->ErrorCallback(hi2s); +#else + HAL_I2S_ErrorCallback(hi2s); + 8005876: 6878 ldr r0, [r7, #4] + 8005878: f7ff fdfa bl 8005470 +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } + + /* I2Sext Underrun error interrupt occurred -------------------------------*/ + if (((i2sextsr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && ((i2sextcr2 & I2S_IT_ERR) != RESET)) + 800587c: 69bb ldr r3, [r7, #24] + 800587e: f003 0308 and.w r3, r3, #8 + 8005882: 2b08 cmp r3, #8 + 8005884: d131 bne.n 80058ea + 8005886: 693b ldr r3, [r7, #16] + 8005888: f003 0320 and.w r3, r3, #32 + 800588c: 2b00 cmp r3, #0 + 800588e: d02c beq.n 80058ea + { + /* Disable TXE and ERR interrupt */ + __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); + 8005890: 687b ldr r3, [r7, #4] + 8005892: 681b ldr r3, [r3, #0] + 8005894: 4a17 ldr r2, [pc, #92] ; (80058f4 ) + 8005896: 4293 cmp r3, r2 + 8005898: d101 bne.n 800589e + 800589a: 4b17 ldr r3, [pc, #92] ; (80058f8 ) + 800589c: e001 b.n 80058a2 + 800589e: f04f 2340 mov.w r3, #1073758208 ; 0x40004000 + 80058a2: 685a ldr r2, [r3, #4] + 80058a4: 687b ldr r3, [r7, #4] + 80058a6: 681b ldr r3, [r3, #0] + 80058a8: 4912 ldr r1, [pc, #72] ; (80058f4 ) + 80058aa: 428b cmp r3, r1 + 80058ac: d101 bne.n 80058b2 + 80058ae: 4b12 ldr r3, [pc, #72] ; (80058f8 ) + 80058b0: e001 b.n 80058b6 + 80058b2: f04f 2340 mov.w r3, #1073758208 ; 0x40004000 + 80058b6: f022 02a0 bic.w r2, r2, #160 ; 0xa0 + 80058ba: 605a str r2, [r3, #4] + + /* Disable RXNE and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); + 80058bc: 687b ldr r3, [r7, #4] + 80058be: 681b ldr r3, [r3, #0] + 80058c0: 685a ldr r2, [r3, #4] + 80058c2: 687b ldr r3, [r7, #4] + 80058c4: 681b ldr r3, [r3, #0] + 80058c6: f022 0260 bic.w r2, r2, #96 ; 0x60 + 80058ca: 605a str r2, [r3, #4] + + /* Set the I2S State ready */ + hi2s->State = HAL_I2S_STATE_READY; + 80058cc: 687b ldr r3, [r7, #4] + 80058ce: 2201 movs r2, #1 + 80058d0: f883 2041 strb.w r2, [r3, #65] ; 0x41 + + /* Set the error code and execute error callback*/ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR); + 80058d4: 687b ldr r3, [r7, #4] + 80058d6: 6c5b ldr r3, [r3, #68] ; 0x44 + 80058d8: f043 0204 orr.w r2, r3, #4 + 80058dc: 687b ldr r3, [r7, #4] + 80058de: 645a str r2, [r3, #68] ; 0x44 + /* Call user error callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + hi2s->ErrorCallback(hi2s); +#else + HAL_I2S_ErrorCallback(hi2s); + 80058e0: 6878 ldr r0, [r7, #4] + 80058e2: f7ff fdc5 bl 8005470 +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } + } +} + 80058e6: e000 b.n 80058ea + if (((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && ((i2scr2 & I2S_IT_ERR) != RESET)) + 80058e8: bf00 nop +} + 80058ea: bf00 nop + 80058ec: 3720 adds r7, #32 + 80058ee: 46bd mov sp, r7 + 80058f0: bd80 pop {r7, pc} + 80058f2: bf00 nop + 80058f4: 40003800 .word 0x40003800 + 80058f8: 40003400 .word 0x40003400 + +080058fc : + * @brief Tx and Rx Transfer completed callback + * @param hi2s I2S handle + * @retval None + */ +__weak void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s) +{ + 80058fc: b480 push {r7} + 80058fe: b083 sub sp, #12 + 8005900: af00 add r7, sp, #0 + 8005902: 6078 str r0, [r7, #4] + UNUSED(hi2s); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2SEx_TxRxCpltCallback could be implemented in the user file + */ +} + 8005904: bf00 nop + 8005906: 370c adds r7, #12 + 8005908: 46bd mov sp, r7 + 800590a: f85d 7b04 ldr.w r7, [sp], #4 + 800590e: 4770 bx lr + +08005910 : + * @brief I2S Full-Duplex IT handler transmit function + * @param hi2s I2S handle + * @retval None + */ +static void I2SEx_TxISR_I2S(I2S_HandleTypeDef *hi2s) +{ + 8005910: b580 push {r7, lr} + 8005912: b082 sub sp, #8 + 8005914: af00 add r7, sp, #0 + 8005916: 6078 str r0, [r7, #4] + /* Write Data on DR register */ + hi2s->Instance->DR = (*hi2s->pTxBuffPtr++); + 8005918: 687b ldr r3, [r7, #4] + 800591a: 6a5b ldr r3, [r3, #36] ; 0x24 + 800591c: 1c99 adds r1, r3, #2 + 800591e: 687a ldr r2, [r7, #4] + 8005920: 6251 str r1, [r2, #36] ; 0x24 + 8005922: 881a ldrh r2, [r3, #0] + 8005924: 687b ldr r3, [r7, #4] + 8005926: 681b ldr r3, [r3, #0] + 8005928: 60da str r2, [r3, #12] + hi2s->TxXferCount--; + 800592a: 687b ldr r3, [r7, #4] + 800592c: 8d5b ldrh r3, [r3, #42] ; 0x2a + 800592e: b29b uxth r3, r3 + 8005930: 3b01 subs r3, #1 + 8005932: b29a uxth r2, r3 + 8005934: 687b ldr r3, [r7, #4] + 8005936: 855a strh r2, [r3, #42] ; 0x2a + + if (hi2s->TxXferCount == 0U) + 8005938: 687b ldr r3, [r7, #4] + 800593a: 8d5b ldrh r3, [r3, #42] ; 0x2a + 800593c: b29b uxth r3, r3 + 800593e: 2b00 cmp r3, #0 + 8005940: d113 bne.n 800596a + { + /* Disable TXE and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); + 8005942: 687b ldr r3, [r7, #4] + 8005944: 681b ldr r3, [r3, #0] + 8005946: 685a ldr r2, [r3, #4] + 8005948: 687b ldr r3, [r7, #4] + 800594a: 681b ldr r3, [r3, #0] + 800594c: f022 02a0 bic.w r2, r2, #160 ; 0xa0 + 8005950: 605a str r2, [r3, #4] + + if (hi2s->RxXferCount == 0U) + 8005952: 687b ldr r3, [r7, #4] + 8005954: 8e5b ldrh r3, [r3, #50] ; 0x32 + 8005956: b29b uxth r3, r3 + 8005958: 2b00 cmp r3, #0 + 800595a: d106 bne.n 800596a + { + hi2s->State = HAL_I2S_STATE_READY; + 800595c: 687b ldr r3, [r7, #4] + 800595e: 2201 movs r2, #1 + 8005960: f883 2041 strb.w r2, [r3, #65] ; 0x41 + /* Call user TxRx complete callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + hi2s->TxRxCpltCallback(hi2s); +#else + HAL_I2SEx_TxRxCpltCallback(hi2s); + 8005964: 6878 ldr r0, [r7, #4] + 8005966: f7ff ffc9 bl 80058fc +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } + } +} + 800596a: bf00 nop + 800596c: 3708 adds r7, #8 + 800596e: 46bd mov sp, r7 + 8005970: bd80 pop {r7, pc} + ... + +08005974 : + * @brief I2SExt Full-Duplex IT handler transmit function + * @param hi2s I2S handle + * @retval None + */ +static void I2SEx_TxISR_I2SExt(I2S_HandleTypeDef *hi2s) +{ + 8005974: b580 push {r7, lr} + 8005976: b082 sub sp, #8 + 8005978: af00 add r7, sp, #0 + 800597a: 6078 str r0, [r7, #4] + /* Write Data on DR register */ + I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++); + 800597c: 687b ldr r3, [r7, #4] + 800597e: 6a5b ldr r3, [r3, #36] ; 0x24 + 8005980: 1c99 adds r1, r3, #2 + 8005982: 687a ldr r2, [r7, #4] + 8005984: 6251 str r1, [r2, #36] ; 0x24 + 8005986: 8819 ldrh r1, [r3, #0] + 8005988: 687b ldr r3, [r7, #4] + 800598a: 681b ldr r3, [r3, #0] + 800598c: 4a1d ldr r2, [pc, #116] ; (8005a04 ) + 800598e: 4293 cmp r3, r2 + 8005990: d101 bne.n 8005996 + 8005992: 4b1d ldr r3, [pc, #116] ; (8005a08 ) + 8005994: e001 b.n 800599a + 8005996: f04f 2340 mov.w r3, #1073758208 ; 0x40004000 + 800599a: 460a mov r2, r1 + 800599c: 60da str r2, [r3, #12] + hi2s->TxXferCount--; + 800599e: 687b ldr r3, [r7, #4] + 80059a0: 8d5b ldrh r3, [r3, #42] ; 0x2a + 80059a2: b29b uxth r3, r3 + 80059a4: 3b01 subs r3, #1 + 80059a6: b29a uxth r2, r3 + 80059a8: 687b ldr r3, [r7, #4] + 80059aa: 855a strh r2, [r3, #42] ; 0x2a + + if (hi2s->TxXferCount == 0U) + 80059ac: 687b ldr r3, [r7, #4] + 80059ae: 8d5b ldrh r3, [r3, #42] ; 0x2a + 80059b0: b29b uxth r3, r3 + 80059b2: 2b00 cmp r3, #0 + 80059b4: d121 bne.n 80059fa + { + /* Disable I2Sext TXE and ERR interrupt */ + __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); + 80059b6: 687b ldr r3, [r7, #4] + 80059b8: 681b ldr r3, [r3, #0] + 80059ba: 4a12 ldr r2, [pc, #72] ; (8005a04 ) + 80059bc: 4293 cmp r3, r2 + 80059be: d101 bne.n 80059c4 + 80059c0: 4b11 ldr r3, [pc, #68] ; (8005a08 ) + 80059c2: e001 b.n 80059c8 + 80059c4: f04f 2340 mov.w r3, #1073758208 ; 0x40004000 + 80059c8: 685a ldr r2, [r3, #4] + 80059ca: 687b ldr r3, [r7, #4] + 80059cc: 681b ldr r3, [r3, #0] + 80059ce: 490d ldr r1, [pc, #52] ; (8005a04 ) + 80059d0: 428b cmp r3, r1 + 80059d2: d101 bne.n 80059d8 + 80059d4: 4b0c ldr r3, [pc, #48] ; (8005a08 ) + 80059d6: e001 b.n 80059dc + 80059d8: f04f 2340 mov.w r3, #1073758208 ; 0x40004000 + 80059dc: f022 02a0 bic.w r2, r2, #160 ; 0xa0 + 80059e0: 605a str r2, [r3, #4] + + if (hi2s->RxXferCount == 0U) + 80059e2: 687b ldr r3, [r7, #4] + 80059e4: 8e5b ldrh r3, [r3, #50] ; 0x32 + 80059e6: b29b uxth r3, r3 + 80059e8: 2b00 cmp r3, #0 + 80059ea: d106 bne.n 80059fa + { + hi2s->State = HAL_I2S_STATE_READY; + 80059ec: 687b ldr r3, [r7, #4] + 80059ee: 2201 movs r2, #1 + 80059f0: f883 2041 strb.w r2, [r3, #65] ; 0x41 + /* Call user TxRx complete callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + hi2s->TxRxCpltCallback(hi2s); +#else + HAL_I2SEx_TxRxCpltCallback(hi2s); + 80059f4: 6878 ldr r0, [r7, #4] + 80059f6: f7ff ff81 bl 80058fc +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } + } +} + 80059fa: bf00 nop + 80059fc: 3708 adds r7, #8 + 80059fe: 46bd mov sp, r7 + 8005a00: bd80 pop {r7, pc} + 8005a02: bf00 nop + 8005a04: 40003800 .word 0x40003800 + 8005a08: 40003400 .word 0x40003400 + +08005a0c : + * @brief I2S Full-Duplex IT handler receive function + * @param hi2s I2S handle + * @retval None + */ +static void I2SEx_RxISR_I2S(I2S_HandleTypeDef *hi2s) +{ + 8005a0c: b580 push {r7, lr} + 8005a0e: b082 sub sp, #8 + 8005a10: af00 add r7, sp, #0 + 8005a12: 6078 str r0, [r7, #4] + /* Read Data from DR register */ + (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR; + 8005a14: 687b ldr r3, [r7, #4] + 8005a16: 681b ldr r3, [r3, #0] + 8005a18: 68d8 ldr r0, [r3, #12] + 8005a1a: 687b ldr r3, [r7, #4] + 8005a1c: 6adb ldr r3, [r3, #44] ; 0x2c + 8005a1e: 1c99 adds r1, r3, #2 + 8005a20: 687a ldr r2, [r7, #4] + 8005a22: 62d1 str r1, [r2, #44] ; 0x2c + 8005a24: b282 uxth r2, r0 + 8005a26: 801a strh r2, [r3, #0] + hi2s->RxXferCount--; + 8005a28: 687b ldr r3, [r7, #4] + 8005a2a: 8e5b ldrh r3, [r3, #50] ; 0x32 + 8005a2c: b29b uxth r3, r3 + 8005a2e: 3b01 subs r3, #1 + 8005a30: b29a uxth r2, r3 + 8005a32: 687b ldr r3, [r7, #4] + 8005a34: 865a strh r2, [r3, #50] ; 0x32 + + if (hi2s->RxXferCount == 0U) + 8005a36: 687b ldr r3, [r7, #4] + 8005a38: 8e5b ldrh r3, [r3, #50] ; 0x32 + 8005a3a: b29b uxth r3, r3 + 8005a3c: 2b00 cmp r3, #0 + 8005a3e: d113 bne.n 8005a68 + { + /* Disable RXNE and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); + 8005a40: 687b ldr r3, [r7, #4] + 8005a42: 681b ldr r3, [r3, #0] + 8005a44: 685a ldr r2, [r3, #4] + 8005a46: 687b ldr r3, [r7, #4] + 8005a48: 681b ldr r3, [r3, #0] + 8005a4a: f022 0260 bic.w r2, r2, #96 ; 0x60 + 8005a4e: 605a str r2, [r3, #4] + + if (hi2s->TxXferCount == 0U) + 8005a50: 687b ldr r3, [r7, #4] + 8005a52: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8005a54: b29b uxth r3, r3 + 8005a56: 2b00 cmp r3, #0 + 8005a58: d106 bne.n 8005a68 + { + hi2s->State = HAL_I2S_STATE_READY; + 8005a5a: 687b ldr r3, [r7, #4] + 8005a5c: 2201 movs r2, #1 + 8005a5e: f883 2041 strb.w r2, [r3, #65] ; 0x41 + /* Call user TxRx complete callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + hi2s->TxRxCpltCallback(hi2s); +#else + HAL_I2SEx_TxRxCpltCallback(hi2s); + 8005a62: 6878 ldr r0, [r7, #4] + 8005a64: f7ff ff4a bl 80058fc +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } + } +} + 8005a68: bf00 nop + 8005a6a: 3708 adds r7, #8 + 8005a6c: 46bd mov sp, r7 + 8005a6e: bd80 pop {r7, pc} + +08005a70 : + * @brief I2SExt Full-Duplex IT handler receive function + * @param hi2s I2S handle + * @retval None + */ +static void I2SEx_RxISR_I2SExt(I2S_HandleTypeDef *hi2s) +{ + 8005a70: b580 push {r7, lr} + 8005a72: b082 sub sp, #8 + 8005a74: af00 add r7, sp, #0 + 8005a76: 6078 str r0, [r7, #4] + /* Read Data from DR register */ + (*hi2s->pRxBuffPtr++) = I2SxEXT(hi2s->Instance)->DR; + 8005a78: 687b ldr r3, [r7, #4] + 8005a7a: 681b ldr r3, [r3, #0] + 8005a7c: 4a20 ldr r2, [pc, #128] ; (8005b00 ) + 8005a7e: 4293 cmp r3, r2 + 8005a80: d101 bne.n 8005a86 + 8005a82: 4b20 ldr r3, [pc, #128] ; (8005b04 ) + 8005a84: e001 b.n 8005a8a + 8005a86: f04f 2340 mov.w r3, #1073758208 ; 0x40004000 + 8005a8a: 68d8 ldr r0, [r3, #12] + 8005a8c: 687b ldr r3, [r7, #4] + 8005a8e: 6adb ldr r3, [r3, #44] ; 0x2c + 8005a90: 1c99 adds r1, r3, #2 + 8005a92: 687a ldr r2, [r7, #4] + 8005a94: 62d1 str r1, [r2, #44] ; 0x2c + 8005a96: b282 uxth r2, r0 + 8005a98: 801a strh r2, [r3, #0] + hi2s->RxXferCount--; + 8005a9a: 687b ldr r3, [r7, #4] + 8005a9c: 8e5b ldrh r3, [r3, #50] ; 0x32 + 8005a9e: b29b uxth r3, r3 + 8005aa0: 3b01 subs r3, #1 + 8005aa2: b29a uxth r2, r3 + 8005aa4: 687b ldr r3, [r7, #4] + 8005aa6: 865a strh r2, [r3, #50] ; 0x32 + + if (hi2s->RxXferCount == 0U) + 8005aa8: 687b ldr r3, [r7, #4] + 8005aaa: 8e5b ldrh r3, [r3, #50] ; 0x32 + 8005aac: b29b uxth r3, r3 + 8005aae: 2b00 cmp r3, #0 + 8005ab0: d121 bne.n 8005af6 + { + /* Disable I2Sext RXNE and ERR interrupt */ + __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); + 8005ab2: 687b ldr r3, [r7, #4] + 8005ab4: 681b ldr r3, [r3, #0] + 8005ab6: 4a12 ldr r2, [pc, #72] ; (8005b00 ) + 8005ab8: 4293 cmp r3, r2 + 8005aba: d101 bne.n 8005ac0 + 8005abc: 4b11 ldr r3, [pc, #68] ; (8005b04 ) + 8005abe: e001 b.n 8005ac4 + 8005ac0: f04f 2340 mov.w r3, #1073758208 ; 0x40004000 + 8005ac4: 685a ldr r2, [r3, #4] + 8005ac6: 687b ldr r3, [r7, #4] + 8005ac8: 681b ldr r3, [r3, #0] + 8005aca: 490d ldr r1, [pc, #52] ; (8005b00 ) + 8005acc: 428b cmp r3, r1 + 8005ace: d101 bne.n 8005ad4 + 8005ad0: 4b0c ldr r3, [pc, #48] ; (8005b04 ) + 8005ad2: e001 b.n 8005ad8 + 8005ad4: f04f 2340 mov.w r3, #1073758208 ; 0x40004000 + 8005ad8: f022 0260 bic.w r2, r2, #96 ; 0x60 + 8005adc: 605a str r2, [r3, #4] + + if (hi2s->TxXferCount == 0U) + 8005ade: 687b ldr r3, [r7, #4] + 8005ae0: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8005ae2: b29b uxth r3, r3 + 8005ae4: 2b00 cmp r3, #0 + 8005ae6: d106 bne.n 8005af6 + { + hi2s->State = HAL_I2S_STATE_READY; + 8005ae8: 687b ldr r3, [r7, #4] + 8005aea: 2201 movs r2, #1 + 8005aec: f883 2041 strb.w r2, [r3, #65] ; 0x41 + /* Call user TxRx complete callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + hi2s->TxRxCpltCallback(hi2s); +#else + HAL_I2SEx_TxRxCpltCallback(hi2s); + 8005af0: 6878 ldr r0, [r7, #4] + 8005af2: f7ff ff03 bl 80058fc +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } + } +} + 8005af6: bf00 nop + 8005af8: 3708 adds r7, #8 + 8005afa: 46bd mov sp, r7 + 8005afc: bd80 pop {r7, pc} + 8005afe: bf00 nop + 8005b00: 40003800 .word 0x40003800 + 8005b04: 40003400 .word 0x40003400 + +08005b08 : + * supported by this API. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + 8005b08: b580 push {r7, lr} + 8005b0a: b086 sub sp, #24 + 8005b0c: af00 add r7, sp, #0 + 8005b0e: 6078 str r0, [r7, #4] + uint32_t tickstart, pll_config; + + /* Check Null pointer */ + if(RCC_OscInitStruct == NULL) + 8005b10: 687b ldr r3, [r7, #4] + 8005b12: 2b00 cmp r3, #0 + 8005b14: d101 bne.n 8005b1a + { + return HAL_ERROR; + 8005b16: 2301 movs r3, #1 + 8005b18: e25b b.n 8005fd2 + } + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + /*------------------------------- HSE Configuration ------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + 8005b1a: 687b ldr r3, [r7, #4] + 8005b1c: 681b ldr r3, [r3, #0] + 8005b1e: f003 0301 and.w r3, r3, #1 + 8005b22: 2b00 cmp r3, #0 + 8005b24: d075 beq.n 8005c12 + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\ + 8005b26: 4ba3 ldr r3, [pc, #652] ; (8005db4 ) + 8005b28: 689b ldr r3, [r3, #8] + 8005b2a: f003 030c and.w r3, r3, #12 + 8005b2e: 2b04 cmp r3, #4 + 8005b30: d00c beq.n 8005b4c + ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) + 8005b32: 4ba0 ldr r3, [pc, #640] ; (8005db4 ) + 8005b34: 689b ldr r3, [r3, #8] + 8005b36: f003 030c and.w r3, r3, #12 + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\ + 8005b3a: 2b08 cmp r3, #8 + 8005b3c: d112 bne.n 8005b64 + ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) + 8005b3e: 4b9d ldr r3, [pc, #628] ; (8005db4 ) + 8005b40: 685b ldr r3, [r3, #4] + 8005b42: f403 0380 and.w r3, r3, #4194304 ; 0x400000 + 8005b46: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 + 8005b4a: d10b bne.n 8005b64 + { + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 8005b4c: 4b99 ldr r3, [pc, #612] ; (8005db4 ) + 8005b4e: 681b ldr r3, [r3, #0] + 8005b50: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8005b54: 2b00 cmp r3, #0 + 8005b56: d05b beq.n 8005c10 + 8005b58: 687b ldr r3, [r7, #4] + 8005b5a: 685b ldr r3, [r3, #4] + 8005b5c: 2b00 cmp r3, #0 + 8005b5e: d157 bne.n 8005c10 + { + return HAL_ERROR; + 8005b60: 2301 movs r3, #1 + 8005b62: e236 b.n 8005fd2 + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + 8005b64: 687b ldr r3, [r7, #4] + 8005b66: 685b ldr r3, [r3, #4] + 8005b68: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 8005b6c: d106 bne.n 8005b7c + 8005b6e: 4b91 ldr r3, [pc, #580] ; (8005db4 ) + 8005b70: 681b ldr r3, [r3, #0] + 8005b72: 4a90 ldr r2, [pc, #576] ; (8005db4 ) + 8005b74: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 8005b78: 6013 str r3, [r2, #0] + 8005b7a: e01d b.n 8005bb8 + 8005b7c: 687b ldr r3, [r7, #4] + 8005b7e: 685b ldr r3, [r3, #4] + 8005b80: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 + 8005b84: d10c bne.n 8005ba0 + 8005b86: 4b8b ldr r3, [pc, #556] ; (8005db4 ) + 8005b88: 681b ldr r3, [r3, #0] + 8005b8a: 4a8a ldr r2, [pc, #552] ; (8005db4 ) + 8005b8c: f443 2380 orr.w r3, r3, #262144 ; 0x40000 + 8005b90: 6013 str r3, [r2, #0] + 8005b92: 4b88 ldr r3, [pc, #544] ; (8005db4 ) + 8005b94: 681b ldr r3, [r3, #0] + 8005b96: 4a87 ldr r2, [pc, #540] ; (8005db4 ) + 8005b98: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 8005b9c: 6013 str r3, [r2, #0] + 8005b9e: e00b b.n 8005bb8 + 8005ba0: 4b84 ldr r3, [pc, #528] ; (8005db4 ) + 8005ba2: 681b ldr r3, [r3, #0] + 8005ba4: 4a83 ldr r2, [pc, #524] ; (8005db4 ) + 8005ba6: f423 3380 bic.w r3, r3, #65536 ; 0x10000 + 8005baa: 6013 str r3, [r2, #0] + 8005bac: 4b81 ldr r3, [pc, #516] ; (8005db4 ) + 8005bae: 681b ldr r3, [r3, #0] + 8005bb0: 4a80 ldr r2, [pc, #512] ; (8005db4 ) + 8005bb2: f423 2380 bic.w r3, r3, #262144 ; 0x40000 + 8005bb6: 6013 str r3, [r2, #0] + + /* Check the HSE State */ + if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF) + 8005bb8: 687b ldr r3, [r7, #4] + 8005bba: 685b ldr r3, [r3, #4] + 8005bbc: 2b00 cmp r3, #0 + 8005bbe: d013 beq.n 8005be8 + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8005bc0: f7fc fbac bl 800231c + 8005bc4: 6138 str r0, [r7, #16] + + /* Wait till HSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + 8005bc6: e008 b.n 8005bda + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + 8005bc8: f7fc fba8 bl 800231c + 8005bcc: 4602 mov r2, r0 + 8005bce: 693b ldr r3, [r7, #16] + 8005bd0: 1ad3 subs r3, r2, r3 + 8005bd2: 2b64 cmp r3, #100 ; 0x64 + 8005bd4: d901 bls.n 8005bda + { + return HAL_TIMEOUT; + 8005bd6: 2303 movs r3, #3 + 8005bd8: e1fb b.n 8005fd2 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + 8005bda: 4b76 ldr r3, [pc, #472] ; (8005db4 ) + 8005bdc: 681b ldr r3, [r3, #0] + 8005bde: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8005be2: 2b00 cmp r3, #0 + 8005be4: d0f0 beq.n 8005bc8 + 8005be6: e014 b.n 8005c12 + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8005be8: f7fc fb98 bl 800231c + 8005bec: 6138 str r0, [r7, #16] + + /* Wait till HSE is bypassed or disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + 8005bee: e008 b.n 8005c02 + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + 8005bf0: f7fc fb94 bl 800231c + 8005bf4: 4602 mov r2, r0 + 8005bf6: 693b ldr r3, [r7, #16] + 8005bf8: 1ad3 subs r3, r2, r3 + 8005bfa: 2b64 cmp r3, #100 ; 0x64 + 8005bfc: d901 bls.n 8005c02 + { + return HAL_TIMEOUT; + 8005bfe: 2303 movs r3, #3 + 8005c00: e1e7 b.n 8005fd2 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + 8005c02: 4b6c ldr r3, [pc, #432] ; (8005db4 ) + 8005c04: 681b ldr r3, [r3, #0] + 8005c06: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8005c0a: 2b00 cmp r3, #0 + 8005c0c: d1f0 bne.n 8005bf0 + 8005c0e: e000 b.n 8005c12 + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 8005c10: bf00 nop + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + 8005c12: 687b ldr r3, [r7, #4] + 8005c14: 681b ldr r3, [r3, #0] + 8005c16: f003 0302 and.w r3, r3, #2 + 8005c1a: 2b00 cmp r3, #0 + 8005c1c: d063 beq.n 8005ce6 + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\ + 8005c1e: 4b65 ldr r3, [pc, #404] ; (8005db4 ) + 8005c20: 689b ldr r3, [r3, #8] + 8005c22: f003 030c and.w r3, r3, #12 + 8005c26: 2b00 cmp r3, #0 + 8005c28: d00b beq.n 8005c42 + ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) + 8005c2a: 4b62 ldr r3, [pc, #392] ; (8005db4 ) + 8005c2c: 689b ldr r3, [r3, #8] + 8005c2e: f003 030c and.w r3, r3, #12 + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\ + 8005c32: 2b08 cmp r3, #8 + 8005c34: d11c bne.n 8005c70 + ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) + 8005c36: 4b5f ldr r3, [pc, #380] ; (8005db4 ) + 8005c38: 685b ldr r3, [r3, #4] + 8005c3a: f403 0380 and.w r3, r3, #4194304 ; 0x400000 + 8005c3e: 2b00 cmp r3, #0 + 8005c40: d116 bne.n 8005c70 + { + /* When HSI is used as system clock it will not disabled */ + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + 8005c42: 4b5c ldr r3, [pc, #368] ; (8005db4 ) + 8005c44: 681b ldr r3, [r3, #0] + 8005c46: f003 0302 and.w r3, r3, #2 + 8005c4a: 2b00 cmp r3, #0 + 8005c4c: d005 beq.n 8005c5a + 8005c4e: 687b ldr r3, [r7, #4] + 8005c50: 68db ldr r3, [r3, #12] + 8005c52: 2b01 cmp r3, #1 + 8005c54: d001 beq.n 8005c5a + { + return HAL_ERROR; + 8005c56: 2301 movs r3, #1 + 8005c58: e1bb b.n 8005fd2 + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 8005c5a: 4b56 ldr r3, [pc, #344] ; (8005db4 ) + 8005c5c: 681b ldr r3, [r3, #0] + 8005c5e: f023 02f8 bic.w r2, r3, #248 ; 0xf8 + 8005c62: 687b ldr r3, [r7, #4] + 8005c64: 691b ldr r3, [r3, #16] + 8005c66: 00db lsls r3, r3, #3 + 8005c68: 4952 ldr r1, [pc, #328] ; (8005db4 ) + 8005c6a: 4313 orrs r3, r2 + 8005c6c: 600b str r3, [r1, #0] + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + 8005c6e: e03a b.n 8005ce6 + } + } + else + { + /* Check the HSI State */ + if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF) + 8005c70: 687b ldr r3, [r7, #4] + 8005c72: 68db ldr r3, [r3, #12] + 8005c74: 2b00 cmp r3, #0 + 8005c76: d020 beq.n 8005cba + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + 8005c78: 4b4f ldr r3, [pc, #316] ; (8005db8 ) + 8005c7a: 2201 movs r2, #1 + 8005c7c: 601a str r2, [r3, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8005c7e: f7fc fb4d bl 800231c + 8005c82: 6138 str r0, [r7, #16] + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + 8005c84: e008 b.n 8005c98 + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + 8005c86: f7fc fb49 bl 800231c + 8005c8a: 4602 mov r2, r0 + 8005c8c: 693b ldr r3, [r7, #16] + 8005c8e: 1ad3 subs r3, r2, r3 + 8005c90: 2b02 cmp r3, #2 + 8005c92: d901 bls.n 8005c98 + { + return HAL_TIMEOUT; + 8005c94: 2303 movs r3, #3 + 8005c96: e19c b.n 8005fd2 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + 8005c98: 4b46 ldr r3, [pc, #280] ; (8005db4 ) + 8005c9a: 681b ldr r3, [r3, #0] + 8005c9c: f003 0302 and.w r3, r3, #2 + 8005ca0: 2b00 cmp r3, #0 + 8005ca2: d0f0 beq.n 8005c86 + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 8005ca4: 4b43 ldr r3, [pc, #268] ; (8005db4 ) + 8005ca6: 681b ldr r3, [r3, #0] + 8005ca8: f023 02f8 bic.w r2, r3, #248 ; 0xf8 + 8005cac: 687b ldr r3, [r7, #4] + 8005cae: 691b ldr r3, [r3, #16] + 8005cb0: 00db lsls r3, r3, #3 + 8005cb2: 4940 ldr r1, [pc, #256] ; (8005db4 ) + 8005cb4: 4313 orrs r3, r2 + 8005cb6: 600b str r3, [r1, #0] + 8005cb8: e015 b.n 8005ce6 + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + 8005cba: 4b3f ldr r3, [pc, #252] ; (8005db8 ) + 8005cbc: 2200 movs r2, #0 + 8005cbe: 601a str r2, [r3, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8005cc0: f7fc fb2c bl 800231c + 8005cc4: 6138 str r0, [r7, #16] + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + 8005cc6: e008 b.n 8005cda + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + 8005cc8: f7fc fb28 bl 800231c + 8005ccc: 4602 mov r2, r0 + 8005cce: 693b ldr r3, [r7, #16] + 8005cd0: 1ad3 subs r3, r2, r3 + 8005cd2: 2b02 cmp r3, #2 + 8005cd4: d901 bls.n 8005cda + { + return HAL_TIMEOUT; + 8005cd6: 2303 movs r3, #3 + 8005cd8: e17b b.n 8005fd2 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + 8005cda: 4b36 ldr r3, [pc, #216] ; (8005db4 ) + 8005cdc: 681b ldr r3, [r3, #0] + 8005cde: f003 0302 and.w r3, r3, #2 + 8005ce2: 2b00 cmp r3, #0 + 8005ce4: d1f0 bne.n 8005cc8 + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + 8005ce6: 687b ldr r3, [r7, #4] + 8005ce8: 681b ldr r3, [r3, #0] + 8005cea: f003 0308 and.w r3, r3, #8 + 8005cee: 2b00 cmp r3, #0 + 8005cf0: d030 beq.n 8005d54 + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF) + 8005cf2: 687b ldr r3, [r7, #4] + 8005cf4: 695b ldr r3, [r3, #20] + 8005cf6: 2b00 cmp r3, #0 + 8005cf8: d016 beq.n 8005d28 + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + 8005cfa: 4b30 ldr r3, [pc, #192] ; (8005dbc ) + 8005cfc: 2201 movs r2, #1 + 8005cfe: 601a str r2, [r3, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8005d00: f7fc fb0c bl 800231c + 8005d04: 6138 str r0, [r7, #16] + + /* Wait till LSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + 8005d06: e008 b.n 8005d1a + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + 8005d08: f7fc fb08 bl 800231c + 8005d0c: 4602 mov r2, r0 + 8005d0e: 693b ldr r3, [r7, #16] + 8005d10: 1ad3 subs r3, r2, r3 + 8005d12: 2b02 cmp r3, #2 + 8005d14: d901 bls.n 8005d1a + { + return HAL_TIMEOUT; + 8005d16: 2303 movs r3, #3 + 8005d18: e15b b.n 8005fd2 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + 8005d1a: 4b26 ldr r3, [pc, #152] ; (8005db4 ) + 8005d1c: 6f5b ldr r3, [r3, #116] ; 0x74 + 8005d1e: f003 0302 and.w r3, r3, #2 + 8005d22: 2b00 cmp r3, #0 + 8005d24: d0f0 beq.n 8005d08 + 8005d26: e015 b.n 8005d54 + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + 8005d28: 4b24 ldr r3, [pc, #144] ; (8005dbc ) + 8005d2a: 2200 movs r2, #0 + 8005d2c: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8005d2e: f7fc faf5 bl 800231c + 8005d32: 6138 str r0, [r7, #16] + + /* Wait till LSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + 8005d34: e008 b.n 8005d48 + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + 8005d36: f7fc faf1 bl 800231c + 8005d3a: 4602 mov r2, r0 + 8005d3c: 693b ldr r3, [r7, #16] + 8005d3e: 1ad3 subs r3, r2, r3 + 8005d40: 2b02 cmp r3, #2 + 8005d42: d901 bls.n 8005d48 + { + return HAL_TIMEOUT; + 8005d44: 2303 movs r3, #3 + 8005d46: e144 b.n 8005fd2 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + 8005d48: 4b1a ldr r3, [pc, #104] ; (8005db4 ) + 8005d4a: 6f5b ldr r3, [r3, #116] ; 0x74 + 8005d4c: f003 0302 and.w r3, r3, #2 + 8005d50: 2b00 cmp r3, #0 + 8005d52: d1f0 bne.n 8005d36 + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + 8005d54: 687b ldr r3, [r7, #4] + 8005d56: 681b ldr r3, [r3, #0] + 8005d58: f003 0304 and.w r3, r3, #4 + 8005d5c: 2b00 cmp r3, #0 + 8005d5e: f000 80a0 beq.w 8005ea2 + { + FlagStatus pwrclkchanged = RESET; + 8005d62: 2300 movs r3, #0 + 8005d64: 75fb strb r3, [r7, #23] + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + 8005d66: 4b13 ldr r3, [pc, #76] ; (8005db4 ) + 8005d68: 6c1b ldr r3, [r3, #64] ; 0x40 + 8005d6a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8005d6e: 2b00 cmp r3, #0 + 8005d70: d10f bne.n 8005d92 + { + __HAL_RCC_PWR_CLK_ENABLE(); + 8005d72: 2300 movs r3, #0 + 8005d74: 60bb str r3, [r7, #8] + 8005d76: 4b0f ldr r3, [pc, #60] ; (8005db4 ) + 8005d78: 6c1b ldr r3, [r3, #64] ; 0x40 + 8005d7a: 4a0e ldr r2, [pc, #56] ; (8005db4 ) + 8005d7c: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 8005d80: 6413 str r3, [r2, #64] ; 0x40 + 8005d82: 4b0c ldr r3, [pc, #48] ; (8005db4 ) + 8005d84: 6c1b ldr r3, [r3, #64] ; 0x40 + 8005d86: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8005d8a: 60bb str r3, [r7, #8] + 8005d8c: 68bb ldr r3, [r7, #8] + pwrclkchanged = SET; + 8005d8e: 2301 movs r3, #1 + 8005d90: 75fb strb r3, [r7, #23] + } + + if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 8005d92: 4b0b ldr r3, [pc, #44] ; (8005dc0 ) + 8005d94: 681b ldr r3, [r3, #0] + 8005d96: f403 7380 and.w r3, r3, #256 ; 0x100 + 8005d9a: 2b00 cmp r3, #0 + 8005d9c: d121 bne.n 8005de2 + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + 8005d9e: 4b08 ldr r3, [pc, #32] ; (8005dc0 ) + 8005da0: 681b ldr r3, [r3, #0] + 8005da2: 4a07 ldr r2, [pc, #28] ; (8005dc0 ) + 8005da4: f443 7380 orr.w r3, r3, #256 ; 0x100 + 8005da8: 6013 str r3, [r2, #0] + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + 8005daa: f7fc fab7 bl 800231c + 8005dae: 6138 str r0, [r7, #16] + + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 8005db0: e011 b.n 8005dd6 + 8005db2: bf00 nop + 8005db4: 40023800 .word 0x40023800 + 8005db8: 42470000 .word 0x42470000 + 8005dbc: 42470e80 .word 0x42470e80 + 8005dc0: 40007000 .word 0x40007000 + { + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 8005dc4: f7fc faaa bl 800231c + 8005dc8: 4602 mov r2, r0 + 8005dca: 693b ldr r3, [r7, #16] + 8005dcc: 1ad3 subs r3, r2, r3 + 8005dce: 2b02 cmp r3, #2 + 8005dd0: d901 bls.n 8005dd6 + { + return HAL_TIMEOUT; + 8005dd2: 2303 movs r3, #3 + 8005dd4: e0fd b.n 8005fd2 + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 8005dd6: 4b81 ldr r3, [pc, #516] ; (8005fdc ) + 8005dd8: 681b ldr r3, [r3, #0] + 8005dda: f403 7380 and.w r3, r3, #256 ; 0x100 + 8005dde: 2b00 cmp r3, #0 + 8005de0: d0f0 beq.n 8005dc4 + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + 8005de2: 687b ldr r3, [r7, #4] + 8005de4: 689b ldr r3, [r3, #8] + 8005de6: 2b01 cmp r3, #1 + 8005de8: d106 bne.n 8005df8 + 8005dea: 4b7d ldr r3, [pc, #500] ; (8005fe0 ) + 8005dec: 6f1b ldr r3, [r3, #112] ; 0x70 + 8005dee: 4a7c ldr r2, [pc, #496] ; (8005fe0 ) + 8005df0: f043 0301 orr.w r3, r3, #1 + 8005df4: 6713 str r3, [r2, #112] ; 0x70 + 8005df6: e01c b.n 8005e32 + 8005df8: 687b ldr r3, [r7, #4] + 8005dfa: 689b ldr r3, [r3, #8] + 8005dfc: 2b05 cmp r3, #5 + 8005dfe: d10c bne.n 8005e1a + 8005e00: 4b77 ldr r3, [pc, #476] ; (8005fe0 ) + 8005e02: 6f1b ldr r3, [r3, #112] ; 0x70 + 8005e04: 4a76 ldr r2, [pc, #472] ; (8005fe0 ) + 8005e06: f043 0304 orr.w r3, r3, #4 + 8005e0a: 6713 str r3, [r2, #112] ; 0x70 + 8005e0c: 4b74 ldr r3, [pc, #464] ; (8005fe0 ) + 8005e0e: 6f1b ldr r3, [r3, #112] ; 0x70 + 8005e10: 4a73 ldr r2, [pc, #460] ; (8005fe0 ) + 8005e12: f043 0301 orr.w r3, r3, #1 + 8005e16: 6713 str r3, [r2, #112] ; 0x70 + 8005e18: e00b b.n 8005e32 + 8005e1a: 4b71 ldr r3, [pc, #452] ; (8005fe0 ) + 8005e1c: 6f1b ldr r3, [r3, #112] ; 0x70 + 8005e1e: 4a70 ldr r2, [pc, #448] ; (8005fe0 ) + 8005e20: f023 0301 bic.w r3, r3, #1 + 8005e24: 6713 str r3, [r2, #112] ; 0x70 + 8005e26: 4b6e ldr r3, [pc, #440] ; (8005fe0 ) + 8005e28: 6f1b ldr r3, [r3, #112] ; 0x70 + 8005e2a: 4a6d ldr r2, [pc, #436] ; (8005fe0 ) + 8005e2c: f023 0304 bic.w r3, r3, #4 + 8005e30: 6713 str r3, [r2, #112] ; 0x70 + /* Check the LSE State */ + if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) + 8005e32: 687b ldr r3, [r7, #4] + 8005e34: 689b ldr r3, [r3, #8] + 8005e36: 2b00 cmp r3, #0 + 8005e38: d015 beq.n 8005e66 + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8005e3a: f7fc fa6f bl 800231c + 8005e3e: 6138 str r0, [r7, #16] + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 8005e40: e00a b.n 8005e58 + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 8005e42: f7fc fa6b bl 800231c + 8005e46: 4602 mov r2, r0 + 8005e48: 693b ldr r3, [r7, #16] + 8005e4a: 1ad3 subs r3, r2, r3 + 8005e4c: f241 3288 movw r2, #5000 ; 0x1388 + 8005e50: 4293 cmp r3, r2 + 8005e52: d901 bls.n 8005e58 + { + return HAL_TIMEOUT; + 8005e54: 2303 movs r3, #3 + 8005e56: e0bc b.n 8005fd2 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 8005e58: 4b61 ldr r3, [pc, #388] ; (8005fe0 ) + 8005e5a: 6f1b ldr r3, [r3, #112] ; 0x70 + 8005e5c: f003 0302 and.w r3, r3, #2 + 8005e60: 2b00 cmp r3, #0 + 8005e62: d0ee beq.n 8005e42 + 8005e64: e014 b.n 8005e90 + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8005e66: f7fc fa59 bl 800231c + 8005e6a: 6138 str r0, [r7, #16] + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + 8005e6c: e00a b.n 8005e84 + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 8005e6e: f7fc fa55 bl 800231c + 8005e72: 4602 mov r2, r0 + 8005e74: 693b ldr r3, [r7, #16] + 8005e76: 1ad3 subs r3, r2, r3 + 8005e78: f241 3288 movw r2, #5000 ; 0x1388 + 8005e7c: 4293 cmp r3, r2 + 8005e7e: d901 bls.n 8005e84 + { + return HAL_TIMEOUT; + 8005e80: 2303 movs r3, #3 + 8005e82: e0a6 b.n 8005fd2 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + 8005e84: 4b56 ldr r3, [pc, #344] ; (8005fe0 ) + 8005e86: 6f1b ldr r3, [r3, #112] ; 0x70 + 8005e88: f003 0302 and.w r3, r3, #2 + 8005e8c: 2b00 cmp r3, #0 + 8005e8e: d1ee bne.n 8005e6e + } + } + } + + /* Restore clock configuration if changed */ + if(pwrclkchanged == SET) + 8005e90: 7dfb ldrb r3, [r7, #23] + 8005e92: 2b01 cmp r3, #1 + 8005e94: d105 bne.n 8005ea2 + { + __HAL_RCC_PWR_CLK_DISABLE(); + 8005e96: 4b52 ldr r3, [pc, #328] ; (8005fe0 ) + 8005e98: 6c1b ldr r3, [r3, #64] ; 0x40 + 8005e9a: 4a51 ldr r2, [pc, #324] ; (8005fe0 ) + 8005e9c: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 + 8005ea0: 6413 str r3, [r2, #64] ; 0x40 + } + } + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + 8005ea2: 687b ldr r3, [r7, #4] + 8005ea4: 699b ldr r3, [r3, #24] + 8005ea6: 2b00 cmp r3, #0 + 8005ea8: f000 8092 beq.w 8005fd0 + { + /* Check if the PLL is used as system clock or not */ + if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) + 8005eac: 4b4c ldr r3, [pc, #304] ; (8005fe0 ) + 8005eae: 689b ldr r3, [r3, #8] + 8005eb0: f003 030c and.w r3, r3, #12 + 8005eb4: 2b08 cmp r3, #8 + 8005eb6: d05c beq.n 8005f72 + { + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + 8005eb8: 687b ldr r3, [r7, #4] + 8005eba: 699b ldr r3, [r3, #24] + 8005ebc: 2b02 cmp r3, #2 + 8005ebe: d141 bne.n 8005f44 + assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); + assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); + assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 8005ec0: 4b48 ldr r3, [pc, #288] ; (8005fe4 ) + 8005ec2: 2200 movs r2, #0 + 8005ec4: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8005ec6: f7fc fa29 bl 800231c + 8005eca: 6138 str r0, [r7, #16] + + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 8005ecc: e008 b.n 8005ee0 + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 8005ece: f7fc fa25 bl 800231c + 8005ed2: 4602 mov r2, r0 + 8005ed4: 693b ldr r3, [r7, #16] + 8005ed6: 1ad3 subs r3, r2, r3 + 8005ed8: 2b02 cmp r3, #2 + 8005eda: d901 bls.n 8005ee0 + { + return HAL_TIMEOUT; + 8005edc: 2303 movs r3, #3 + 8005ede: e078 b.n 8005fd2 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 8005ee0: 4b3f ldr r3, [pc, #252] ; (8005fe0 ) + 8005ee2: 681b ldr r3, [r3, #0] + 8005ee4: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 8005ee8: 2b00 cmp r3, #0 + 8005eea: d1f0 bne.n 8005ece + } + } + + /* Configure the main PLL clock source, multiplication and division factors. */ + WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \ + 8005eec: 687b ldr r3, [r7, #4] + 8005eee: 69da ldr r2, [r3, #28] + 8005ef0: 687b ldr r3, [r7, #4] + 8005ef2: 6a1b ldr r3, [r3, #32] + 8005ef4: 431a orrs r2, r3 + 8005ef6: 687b ldr r3, [r7, #4] + 8005ef8: 6a5b ldr r3, [r3, #36] ; 0x24 + 8005efa: 019b lsls r3, r3, #6 + 8005efc: 431a orrs r2, r3 + 8005efe: 687b ldr r3, [r7, #4] + 8005f00: 6a9b ldr r3, [r3, #40] ; 0x28 + 8005f02: 085b lsrs r3, r3, #1 + 8005f04: 3b01 subs r3, #1 + 8005f06: 041b lsls r3, r3, #16 + 8005f08: 431a orrs r2, r3 + 8005f0a: 687b ldr r3, [r7, #4] + 8005f0c: 6adb ldr r3, [r3, #44] ; 0x2c + 8005f0e: 061b lsls r3, r3, #24 + 8005f10: 4933 ldr r1, [pc, #204] ; (8005fe0 ) + 8005f12: 4313 orrs r3, r2 + 8005f14: 604b str r3, [r1, #4] + RCC_OscInitStruct->PLL.PLLM | \ + (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \ + (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \ + (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos))); + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + 8005f16: 4b33 ldr r3, [pc, #204] ; (8005fe4 ) + 8005f18: 2201 movs r2, #1 + 8005f1a: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8005f1c: f7fc f9fe bl 800231c + 8005f20: 6138 str r0, [r7, #16] + + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 8005f22: e008 b.n 8005f36 + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 8005f24: f7fc f9fa bl 800231c + 8005f28: 4602 mov r2, r0 + 8005f2a: 693b ldr r3, [r7, #16] + 8005f2c: 1ad3 subs r3, r2, r3 + 8005f2e: 2b02 cmp r3, #2 + 8005f30: d901 bls.n 8005f36 + { + return HAL_TIMEOUT; + 8005f32: 2303 movs r3, #3 + 8005f34: e04d b.n 8005fd2 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 8005f36: 4b2a ldr r3, [pc, #168] ; (8005fe0 ) + 8005f38: 681b ldr r3, [r3, #0] + 8005f3a: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 8005f3e: 2b00 cmp r3, #0 + 8005f40: d0f0 beq.n 8005f24 + 8005f42: e045 b.n 8005fd0 + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 8005f44: 4b27 ldr r3, [pc, #156] ; (8005fe4 ) + 8005f46: 2200 movs r2, #0 + 8005f48: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8005f4a: f7fc f9e7 bl 800231c + 8005f4e: 6138 str r0, [r7, #16] + + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 8005f50: e008 b.n 8005f64 + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 8005f52: f7fc f9e3 bl 800231c + 8005f56: 4602 mov r2, r0 + 8005f58: 693b ldr r3, [r7, #16] + 8005f5a: 1ad3 subs r3, r2, r3 + 8005f5c: 2b02 cmp r3, #2 + 8005f5e: d901 bls.n 8005f64 + { + return HAL_TIMEOUT; + 8005f60: 2303 movs r3, #3 + 8005f62: e036 b.n 8005fd2 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 8005f64: 4b1e ldr r3, [pc, #120] ; (8005fe0 ) + 8005f66: 681b ldr r3, [r3, #0] + 8005f68: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 8005f6c: 2b00 cmp r3, #0 + 8005f6e: d1f0 bne.n 8005f52 + 8005f70: e02e b.n 8005fd0 + } + } + else + { + /* Check if there is a request to disable the PLL used as System clock source */ + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) + 8005f72: 687b ldr r3, [r7, #4] + 8005f74: 699b ldr r3, [r3, #24] + 8005f76: 2b01 cmp r3, #1 + 8005f78: d101 bne.n 8005f7e + { + return HAL_ERROR; + 8005f7a: 2301 movs r3, #1 + 8005f7c: e029 b.n 8005fd2 + } + else + { + /* Do not return HAL_ERROR if request repeats the current configuration */ + pll_config = RCC->PLLCFGR; + 8005f7e: 4b18 ldr r3, [pc, #96] ; (8005fe0 ) + 8005f80: 685b ldr r3, [r3, #4] + 8005f82: 60fb str r3, [r7, #12] + if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 8005f84: 68fb ldr r3, [r7, #12] + 8005f86: f403 0280 and.w r2, r3, #4194304 ; 0x400000 + 8005f8a: 687b ldr r3, [r7, #4] + 8005f8c: 69db ldr r3, [r3, #28] + 8005f8e: 429a cmp r2, r3 + 8005f90: d11c bne.n 8005fcc + (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || + 8005f92: 68fb ldr r3, [r7, #12] + 8005f94: f003 023f and.w r2, r3, #63 ; 0x3f + 8005f98: 687b ldr r3, [r7, #4] + 8005f9a: 6a1b ldr r3, [r3, #32] + if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 8005f9c: 429a cmp r2, r3 + 8005f9e: d115 bne.n 8005fcc + (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != RCC_OscInitStruct->PLL.PLLN) || + 8005fa0: 68fa ldr r2, [r7, #12] + 8005fa2: f647 73c0 movw r3, #32704 ; 0x7fc0 + 8005fa6: 4013 ands r3, r2 + 8005fa8: 687a ldr r2, [r7, #4] + 8005faa: 6a52 ldr r2, [r2, #36] ; 0x24 + (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || + 8005fac: 4293 cmp r3, r2 + 8005fae: d10d bne.n 8005fcc + (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) || + 8005fb0: 68fb ldr r3, [r7, #12] + 8005fb2: f403 3240 and.w r2, r3, #196608 ; 0x30000 + 8005fb6: 687b ldr r3, [r7, #4] + 8005fb8: 6a9b ldr r3, [r3, #40] ; 0x28 + (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != RCC_OscInitStruct->PLL.PLLN) || + 8005fba: 429a cmp r2, r3 + 8005fbc: d106 bne.n 8005fcc + (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ)) + 8005fbe: 68fb ldr r3, [r7, #12] + 8005fc0: f003 6270 and.w r2, r3, #251658240 ; 0xf000000 + 8005fc4: 687b ldr r3, [r7, #4] + 8005fc6: 6adb ldr r3, [r3, #44] ; 0x2c + (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) || + 8005fc8: 429a cmp r2, r3 + 8005fca: d001 beq.n 8005fd0 + { + return HAL_ERROR; + 8005fcc: 2301 movs r3, #1 + 8005fce: e000 b.n 8005fd2 + } + } + } + } + return HAL_OK; + 8005fd0: 2300 movs r3, #0 +} + 8005fd2: 4618 mov r0, r3 + 8005fd4: 3718 adds r7, #24 + 8005fd6: 46bd mov sp, r7 + 8005fd8: bd80 pop {r7, pc} + 8005fda: bf00 nop + 8005fdc: 40007000 .word 0x40007000 + 8005fe0: 40023800 .word 0x40023800 + 8005fe4: 42470060 .word 0x42470060 + +08005fe8 : + * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency + * (for more details refer to section above "Initialization/de-initialization functions") + * @retval None + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + 8005fe8: b580 push {r7, lr} + 8005fea: b084 sub sp, #16 + 8005fec: af00 add r7, sp, #0 + 8005fee: 6078 str r0, [r7, #4] + 8005ff0: 6039 str r1, [r7, #0] + uint32_t tickstart; + + /* Check Null pointer */ + if(RCC_ClkInitStruct == NULL) + 8005ff2: 687b ldr r3, [r7, #4] + 8005ff4: 2b00 cmp r3, #0 + 8005ff6: d101 bne.n 8005ffc + { + return HAL_ERROR; + 8005ff8: 2301 movs r3, #1 + 8005ffa: e0cc b.n 8006196 + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. */ + + /* Increasing the number of wait states because of higher CPU frequency */ + if(FLatency > __HAL_FLASH_GET_LATENCY()) + 8005ffc: 4b68 ldr r3, [pc, #416] ; (80061a0 ) + 8005ffe: 681b ldr r3, [r3, #0] + 8006000: f003 030f and.w r3, r3, #15 + 8006004: 683a ldr r2, [r7, #0] + 8006006: 429a cmp r2, r3 + 8006008: d90c bls.n 8006024 + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 800600a: 4b65 ldr r3, [pc, #404] ; (80061a0 ) + 800600c: 683a ldr r2, [r7, #0] + 800600e: b2d2 uxtb r2, r2 + 8006010: 701a strb r2, [r3, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != FLatency) + 8006012: 4b63 ldr r3, [pc, #396] ; (80061a0 ) + 8006014: 681b ldr r3, [r3, #0] + 8006016: f003 030f and.w r3, r3, #15 + 800601a: 683a ldr r2, [r7, #0] + 800601c: 429a cmp r2, r3 + 800601e: d001 beq.n 8006024 + { + return HAL_ERROR; + 8006020: 2301 movs r3, #1 + 8006022: e0b8 b.n 8006196 + } + } + + /*-------------------------- HCLK Configuration --------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + 8006024: 687b ldr r3, [r7, #4] + 8006026: 681b ldr r3, [r3, #0] + 8006028: f003 0302 and.w r3, r3, #2 + 800602c: 2b00 cmp r3, #0 + 800602e: d020 beq.n 8006072 + { + /* Set the highest APBx dividers in order to ensure that we do not go through + a non-spec phase whatever we decrease or increase HCLK. */ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 8006030: 687b ldr r3, [r7, #4] + 8006032: 681b ldr r3, [r3, #0] + 8006034: f003 0304 and.w r3, r3, #4 + 8006038: 2b00 cmp r3, #0 + 800603a: d005 beq.n 8006048 + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); + 800603c: 4b59 ldr r3, [pc, #356] ; (80061a4 ) + 800603e: 689b ldr r3, [r3, #8] + 8006040: 4a58 ldr r2, [pc, #352] ; (80061a4 ) + 8006042: f443 53e0 orr.w r3, r3, #7168 ; 0x1c00 + 8006046: 6093 str r3, [r2, #8] + } + + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + 8006048: 687b ldr r3, [r7, #4] + 800604a: 681b ldr r3, [r3, #0] + 800604c: f003 0308 and.w r3, r3, #8 + 8006050: 2b00 cmp r3, #0 + 8006052: d005 beq.n 8006060 + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); + 8006054: 4b53 ldr r3, [pc, #332] ; (80061a4 ) + 8006056: 689b ldr r3, [r3, #8] + 8006058: 4a52 ldr r2, [pc, #328] ; (80061a4 ) + 800605a: f443 4360 orr.w r3, r3, #57344 ; 0xe000 + 800605e: 6093 str r3, [r2, #8] + } + + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + 8006060: 4b50 ldr r3, [pc, #320] ; (80061a4 ) + 8006062: 689b ldr r3, [r3, #8] + 8006064: f023 02f0 bic.w r2, r3, #240 ; 0xf0 + 8006068: 687b ldr r3, [r7, #4] + 800606a: 689b ldr r3, [r3, #8] + 800606c: 494d ldr r1, [pc, #308] ; (80061a4 ) + 800606e: 4313 orrs r3, r2 + 8006070: 608b str r3, [r1, #8] + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + 8006072: 687b ldr r3, [r7, #4] + 8006074: 681b ldr r3, [r3, #0] + 8006076: f003 0301 and.w r3, r3, #1 + 800607a: 2b00 cmp r3, #0 + 800607c: d044 beq.n 8006108 + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + 800607e: 687b ldr r3, [r7, #4] + 8006080: 685b ldr r3, [r3, #4] + 8006082: 2b01 cmp r3, #1 + 8006084: d107 bne.n 8006096 + { + /* Check the HSE ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + 8006086: 4b47 ldr r3, [pc, #284] ; (80061a4 ) + 8006088: 681b ldr r3, [r3, #0] + 800608a: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 800608e: 2b00 cmp r3, #0 + 8006090: d119 bne.n 80060c6 + { + return HAL_ERROR; + 8006092: 2301 movs r3, #1 + 8006094: e07f b.n 8006196 + } + } + /* PLL is selected as System Clock Source */ + else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || + 8006096: 687b ldr r3, [r7, #4] + 8006098: 685b ldr r3, [r3, #4] + 800609a: 2b02 cmp r3, #2 + 800609c: d003 beq.n 80060a6 + (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK)) + 800609e: 687b ldr r3, [r7, #4] + 80060a0: 685b ldr r3, [r3, #4] + else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || + 80060a2: 2b03 cmp r3, #3 + 80060a4: d107 bne.n 80060b6 + { + /* Check the PLL ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 80060a6: 4b3f ldr r3, [pc, #252] ; (80061a4 ) + 80060a8: 681b ldr r3, [r3, #0] + 80060aa: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 80060ae: 2b00 cmp r3, #0 + 80060b0: d109 bne.n 80060c6 + { + return HAL_ERROR; + 80060b2: 2301 movs r3, #1 + 80060b4: e06f b.n 8006196 + } + /* HSI is selected as System Clock Source */ + else + { + /* Check the HSI ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + 80060b6: 4b3b ldr r3, [pc, #236] ; (80061a4 ) + 80060b8: 681b ldr r3, [r3, #0] + 80060ba: f003 0302 and.w r3, r3, #2 + 80060be: 2b00 cmp r3, #0 + 80060c0: d101 bne.n 80060c6 + { + return HAL_ERROR; + 80060c2: 2301 movs r3, #1 + 80060c4: e067 b.n 8006196 + } + } + + __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); + 80060c6: 4b37 ldr r3, [pc, #220] ; (80061a4 ) + 80060c8: 689b ldr r3, [r3, #8] + 80060ca: f023 0203 bic.w r2, r3, #3 + 80060ce: 687b ldr r3, [r7, #4] + 80060d0: 685b ldr r3, [r3, #4] + 80060d2: 4934 ldr r1, [pc, #208] ; (80061a4 ) + 80060d4: 4313 orrs r3, r2 + 80060d6: 608b str r3, [r1, #8] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80060d8: f7fc f920 bl 800231c + 80060dc: 60f8 str r0, [r7, #12] + + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + 80060de: e00a b.n 80060f6 + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + 80060e0: f7fc f91c bl 800231c + 80060e4: 4602 mov r2, r0 + 80060e6: 68fb ldr r3, [r7, #12] + 80060e8: 1ad3 subs r3, r2, r3 + 80060ea: f241 3288 movw r2, #5000 ; 0x1388 + 80060ee: 4293 cmp r3, r2 + 80060f0: d901 bls.n 80060f6 + { + return HAL_TIMEOUT; + 80060f2: 2303 movs r3, #3 + 80060f4: e04f b.n 8006196 + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + 80060f6: 4b2b ldr r3, [pc, #172] ; (80061a4 ) + 80060f8: 689b ldr r3, [r3, #8] + 80060fa: f003 020c and.w r2, r3, #12 + 80060fe: 687b ldr r3, [r7, #4] + 8006100: 685b ldr r3, [r3, #4] + 8006102: 009b lsls r3, r3, #2 + 8006104: 429a cmp r2, r3 + 8006106: d1eb bne.n 80060e0 + } + } + } + + /* Decreasing the number of wait states because of lower CPU frequency */ + if(FLatency < __HAL_FLASH_GET_LATENCY()) + 8006108: 4b25 ldr r3, [pc, #148] ; (80061a0 ) + 800610a: 681b ldr r3, [r3, #0] + 800610c: f003 030f and.w r3, r3, #15 + 8006110: 683a ldr r2, [r7, #0] + 8006112: 429a cmp r2, r3 + 8006114: d20c bcs.n 8006130 + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 8006116: 4b22 ldr r3, [pc, #136] ; (80061a0 ) + 8006118: 683a ldr r2, [r7, #0] + 800611a: b2d2 uxtb r2, r2 + 800611c: 701a strb r2, [r3, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != FLatency) + 800611e: 4b20 ldr r3, [pc, #128] ; (80061a0 ) + 8006120: 681b ldr r3, [r3, #0] + 8006122: f003 030f and.w r3, r3, #15 + 8006126: 683a ldr r2, [r7, #0] + 8006128: 429a cmp r2, r3 + 800612a: d001 beq.n 8006130 + { + return HAL_ERROR; + 800612c: 2301 movs r3, #1 + 800612e: e032 b.n 8006196 + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 8006130: 687b ldr r3, [r7, #4] + 8006132: 681b ldr r3, [r3, #0] + 8006134: f003 0304 and.w r3, r3, #4 + 8006138: 2b00 cmp r3, #0 + 800613a: d008 beq.n 800614e + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); + 800613c: 4b19 ldr r3, [pc, #100] ; (80061a4 ) + 800613e: 689b ldr r3, [r3, #8] + 8006140: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00 + 8006144: 687b ldr r3, [r7, #4] + 8006146: 68db ldr r3, [r3, #12] + 8006148: 4916 ldr r1, [pc, #88] ; (80061a4 ) + 800614a: 4313 orrs r3, r2 + 800614c: 608b str r3, [r1, #8] + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + 800614e: 687b ldr r3, [r7, #4] + 8006150: 681b ldr r3, [r3, #0] + 8006152: f003 0308 and.w r3, r3, #8 + 8006156: 2b00 cmp r3, #0 + 8006158: d009 beq.n 800616e + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); + 800615a: 4b12 ldr r3, [pc, #72] ; (80061a4 ) + 800615c: 689b ldr r3, [r3, #8] + 800615e: f423 4260 bic.w r2, r3, #57344 ; 0xe000 + 8006162: 687b ldr r3, [r7, #4] + 8006164: 691b ldr r3, [r3, #16] + 8006166: 00db lsls r3, r3, #3 + 8006168: 490e ldr r1, [pc, #56] ; (80061a4 ) + 800616a: 4313 orrs r3, r2 + 800616c: 608b str r3, [r1, #8] + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos]; + 800616e: f000 f821 bl 80061b4 + 8006172: 4601 mov r1, r0 + 8006174: 4b0b ldr r3, [pc, #44] ; (80061a4 ) + 8006176: 689b ldr r3, [r3, #8] + 8006178: 091b lsrs r3, r3, #4 + 800617a: f003 030f and.w r3, r3, #15 + 800617e: 4a0a ldr r2, [pc, #40] ; (80061a8 ) + 8006180: 5cd3 ldrb r3, [r2, r3] + 8006182: fa21 f303 lsr.w r3, r1, r3 + 8006186: 4a09 ldr r2, [pc, #36] ; (80061ac ) + 8006188: 6013 str r3, [r2, #0] + + /* Configure the source of time base considering new system clocks settings */ + HAL_InitTick (uwTickPrio); + 800618a: 4b09 ldr r3, [pc, #36] ; (80061b0 ) + 800618c: 681b ldr r3, [r3, #0] + 800618e: 4618 mov r0, r3 + 8006190: f7fc f880 bl 8002294 + + return HAL_OK; + 8006194: 2300 movs r3, #0 +} + 8006196: 4618 mov r0, r3 + 8006198: 3710 adds r7, #16 + 800619a: 46bd mov sp, r7 + 800619c: bd80 pop {r7, pc} + 800619e: bf00 nop + 80061a0: 40023c00 .word 0x40023c00 + 80061a4: 40023800 .word 0x40023800 + 80061a8: 0800e918 .word 0x0800e918 + 80061ac: 20000000 .word 0x20000000 + 80061b0: 20000004 .word 0x20000004 + +080061b4 : + * + * + * @retval SYSCLK frequency + */ +__weak uint32_t HAL_RCC_GetSysClockFreq(void) +{ + 80061b4: b5f0 push {r4, r5, r6, r7, lr} + 80061b6: b085 sub sp, #20 + 80061b8: af00 add r7, sp, #0 + uint32_t pllm = 0U, pllvco = 0U, pllp = 0U; + 80061ba: 2300 movs r3, #0 + 80061bc: 607b str r3, [r7, #4] + 80061be: 2300 movs r3, #0 + 80061c0: 60fb str r3, [r7, #12] + 80061c2: 2300 movs r3, #0 + 80061c4: 603b str r3, [r7, #0] + uint32_t sysclockfreq = 0U; + 80061c6: 2300 movs r3, #0 + 80061c8: 60bb str r3, [r7, #8] + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR & RCC_CFGR_SWS) + 80061ca: 4b63 ldr r3, [pc, #396] ; (8006358 ) + 80061cc: 689b ldr r3, [r3, #8] + 80061ce: f003 030c and.w r3, r3, #12 + 80061d2: 2b04 cmp r3, #4 + 80061d4: d007 beq.n 80061e6 + 80061d6: 2b08 cmp r3, #8 + 80061d8: d008 beq.n 80061ec + 80061da: 2b00 cmp r3, #0 + 80061dc: f040 80b4 bne.w 8006348 + { + case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ + { + sysclockfreq = HSI_VALUE; + 80061e0: 4b5e ldr r3, [pc, #376] ; (800635c ) + 80061e2: 60bb str r3, [r7, #8] + break; + 80061e4: e0b3 b.n 800634e + } + case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ + { + sysclockfreq = HSE_VALUE; + 80061e6: 4b5e ldr r3, [pc, #376] ; (8006360 ) + 80061e8: 60bb str r3, [r7, #8] + break; + 80061ea: e0b0 b.n 800634e + } + case RCC_CFGR_SWS_PLL: /* PLL used as system clock source */ + { + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + SYSCLK = PLL_VCO / PLLP */ + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + 80061ec: 4b5a ldr r3, [pc, #360] ; (8006358 ) + 80061ee: 685b ldr r3, [r3, #4] + 80061f0: f003 033f and.w r3, r3, #63 ; 0x3f + 80061f4: 607b str r3, [r7, #4] + if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) + 80061f6: 4b58 ldr r3, [pc, #352] ; (8006358 ) + 80061f8: 685b ldr r3, [r3, #4] + 80061fa: f403 0380 and.w r3, r3, #4194304 ; 0x400000 + 80061fe: 2b00 cmp r3, #0 + 8006200: d04a beq.n 8006298 + { + /* HSE used as PLL clock source */ + pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); + 8006202: 4b55 ldr r3, [pc, #340] ; (8006358 ) + 8006204: 685b ldr r3, [r3, #4] + 8006206: 099b lsrs r3, r3, #6 + 8006208: f04f 0400 mov.w r4, #0 + 800620c: f240 11ff movw r1, #511 ; 0x1ff + 8006210: f04f 0200 mov.w r2, #0 + 8006214: ea03 0501 and.w r5, r3, r1 + 8006218: ea04 0602 and.w r6, r4, r2 + 800621c: 4629 mov r1, r5 + 800621e: 4632 mov r2, r6 + 8006220: f04f 0300 mov.w r3, #0 + 8006224: f04f 0400 mov.w r4, #0 + 8006228: 0154 lsls r4, r2, #5 + 800622a: ea44 64d1 orr.w r4, r4, r1, lsr #27 + 800622e: 014b lsls r3, r1, #5 + 8006230: 4619 mov r1, r3 + 8006232: 4622 mov r2, r4 + 8006234: 1b49 subs r1, r1, r5 + 8006236: eb62 0206 sbc.w r2, r2, r6 + 800623a: f04f 0300 mov.w r3, #0 + 800623e: f04f 0400 mov.w r4, #0 + 8006242: 0194 lsls r4, r2, #6 + 8006244: ea44 6491 orr.w r4, r4, r1, lsr #26 + 8006248: 018b lsls r3, r1, #6 + 800624a: 1a5b subs r3, r3, r1 + 800624c: eb64 0402 sbc.w r4, r4, r2 + 8006250: f04f 0100 mov.w r1, #0 + 8006254: f04f 0200 mov.w r2, #0 + 8006258: 00e2 lsls r2, r4, #3 + 800625a: ea42 7253 orr.w r2, r2, r3, lsr #29 + 800625e: 00d9 lsls r1, r3, #3 + 8006260: 460b mov r3, r1 + 8006262: 4614 mov r4, r2 + 8006264: 195b adds r3, r3, r5 + 8006266: eb44 0406 adc.w r4, r4, r6 + 800626a: f04f 0100 mov.w r1, #0 + 800626e: f04f 0200 mov.w r2, #0 + 8006272: 0262 lsls r2, r4, #9 + 8006274: ea42 52d3 orr.w r2, r2, r3, lsr #23 + 8006278: 0259 lsls r1, r3, #9 + 800627a: 460b mov r3, r1 + 800627c: 4614 mov r4, r2 + 800627e: 4618 mov r0, r3 + 8006280: 4621 mov r1, r4 + 8006282: 687b ldr r3, [r7, #4] + 8006284: f04f 0400 mov.w r4, #0 + 8006288: 461a mov r2, r3 + 800628a: 4623 mov r3, r4 + 800628c: f7fa fd04 bl 8000c98 <__aeabi_uldivmod> + 8006290: 4603 mov r3, r0 + 8006292: 460c mov r4, r1 + 8006294: 60fb str r3, [r7, #12] + 8006296: e049 b.n 800632c + } + else + { + /* HSI used as PLL clock source */ + pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); + 8006298: 4b2f ldr r3, [pc, #188] ; (8006358 ) + 800629a: 685b ldr r3, [r3, #4] + 800629c: 099b lsrs r3, r3, #6 + 800629e: f04f 0400 mov.w r4, #0 + 80062a2: f240 11ff movw r1, #511 ; 0x1ff + 80062a6: f04f 0200 mov.w r2, #0 + 80062aa: ea03 0501 and.w r5, r3, r1 + 80062ae: ea04 0602 and.w r6, r4, r2 + 80062b2: 4629 mov r1, r5 + 80062b4: 4632 mov r2, r6 + 80062b6: f04f 0300 mov.w r3, #0 + 80062ba: f04f 0400 mov.w r4, #0 + 80062be: 0154 lsls r4, r2, #5 + 80062c0: ea44 64d1 orr.w r4, r4, r1, lsr #27 + 80062c4: 014b lsls r3, r1, #5 + 80062c6: 4619 mov r1, r3 + 80062c8: 4622 mov r2, r4 + 80062ca: 1b49 subs r1, r1, r5 + 80062cc: eb62 0206 sbc.w r2, r2, r6 + 80062d0: f04f 0300 mov.w r3, #0 + 80062d4: f04f 0400 mov.w r4, #0 + 80062d8: 0194 lsls r4, r2, #6 + 80062da: ea44 6491 orr.w r4, r4, r1, lsr #26 + 80062de: 018b lsls r3, r1, #6 + 80062e0: 1a5b subs r3, r3, r1 + 80062e2: eb64 0402 sbc.w r4, r4, r2 + 80062e6: f04f 0100 mov.w r1, #0 + 80062ea: f04f 0200 mov.w r2, #0 + 80062ee: 00e2 lsls r2, r4, #3 + 80062f0: ea42 7253 orr.w r2, r2, r3, lsr #29 + 80062f4: 00d9 lsls r1, r3, #3 + 80062f6: 460b mov r3, r1 + 80062f8: 4614 mov r4, r2 + 80062fa: 195b adds r3, r3, r5 + 80062fc: eb44 0406 adc.w r4, r4, r6 + 8006300: f04f 0100 mov.w r1, #0 + 8006304: f04f 0200 mov.w r2, #0 + 8006308: 02a2 lsls r2, r4, #10 + 800630a: ea42 5293 orr.w r2, r2, r3, lsr #22 + 800630e: 0299 lsls r1, r3, #10 + 8006310: 460b mov r3, r1 + 8006312: 4614 mov r4, r2 + 8006314: 4618 mov r0, r3 + 8006316: 4621 mov r1, r4 + 8006318: 687b ldr r3, [r7, #4] + 800631a: f04f 0400 mov.w r4, #0 + 800631e: 461a mov r2, r3 + 8006320: 4623 mov r3, r4 + 8006322: f7fa fcb9 bl 8000c98 <__aeabi_uldivmod> + 8006326: 4603 mov r3, r0 + 8006328: 460c mov r4, r1 + 800632a: 60fb str r3, [r7, #12] + } + pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U); + 800632c: 4b0a ldr r3, [pc, #40] ; (8006358 ) + 800632e: 685b ldr r3, [r3, #4] + 8006330: 0c1b lsrs r3, r3, #16 + 8006332: f003 0303 and.w r3, r3, #3 + 8006336: 3301 adds r3, #1 + 8006338: 005b lsls r3, r3, #1 + 800633a: 603b str r3, [r7, #0] + + sysclockfreq = pllvco/pllp; + 800633c: 68fa ldr r2, [r7, #12] + 800633e: 683b ldr r3, [r7, #0] + 8006340: fbb2 f3f3 udiv r3, r2, r3 + 8006344: 60bb str r3, [r7, #8] + break; + 8006346: e002 b.n 800634e + } + default: + { + sysclockfreq = HSI_VALUE; + 8006348: 4b04 ldr r3, [pc, #16] ; (800635c ) + 800634a: 60bb str r3, [r7, #8] + break; + 800634c: bf00 nop + } + } + return sysclockfreq; + 800634e: 68bb ldr r3, [r7, #8] +} + 8006350: 4618 mov r0, r3 + 8006352: 3714 adds r7, #20 + 8006354: 46bd mov sp, r7 + 8006356: bdf0 pop {r4, r5, r6, r7, pc} + 8006358: 40023800 .word 0x40023800 + 800635c: 00f42400 .word 0x00f42400 + 8006360: 007a1200 .word 0x007a1200 + +08006364 : + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * and updated within this function + * @retval HCLK frequency + */ +uint32_t HAL_RCC_GetHCLKFreq(void) +{ + 8006364: b480 push {r7} + 8006366: af00 add r7, sp, #0 + return SystemCoreClock; + 8006368: 4b03 ldr r3, [pc, #12] ; (8006378 ) + 800636a: 681b ldr r3, [r3, #0] +} + 800636c: 4618 mov r0, r3 + 800636e: 46bd mov sp, r7 + 8006370: f85d 7b04 ldr.w r7, [sp], #4 + 8006374: 4770 bx lr + 8006376: bf00 nop + 8006378: 20000000 .word 0x20000000 + +0800637c : + * @note Each time PCLK1 changes, this function must be called to update the + * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK1 frequency + */ +uint32_t HAL_RCC_GetPCLK1Freq(void) +{ + 800637c: b580 push {r7, lr} + 800637e: af00 add r7, sp, #0 + /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]); + 8006380: f7ff fff0 bl 8006364 + 8006384: 4601 mov r1, r0 + 8006386: 4b05 ldr r3, [pc, #20] ; (800639c ) + 8006388: 689b ldr r3, [r3, #8] + 800638a: 0a9b lsrs r3, r3, #10 + 800638c: f003 0307 and.w r3, r3, #7 + 8006390: 4a03 ldr r2, [pc, #12] ; (80063a0 ) + 8006392: 5cd3 ldrb r3, [r2, r3] + 8006394: fa21 f303 lsr.w r3, r1, r3 +} + 8006398: 4618 mov r0, r3 + 800639a: bd80 pop {r7, pc} + 800639c: 40023800 .word 0x40023800 + 80063a0: 0800e928 .word 0x0800e928 + +080063a4 : + * @note Each time PCLK2 changes, this function must be called to update the + * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK2 frequency + */ +uint32_t HAL_RCC_GetPCLK2Freq(void) +{ + 80063a4: b580 push {r7, lr} + 80063a6: af00 add r7, sp, #0 + /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]); + 80063a8: f7ff ffdc bl 8006364 + 80063ac: 4601 mov r1, r0 + 80063ae: 4b05 ldr r3, [pc, #20] ; (80063c4 ) + 80063b0: 689b ldr r3, [r3, #8] + 80063b2: 0b5b lsrs r3, r3, #13 + 80063b4: f003 0307 and.w r3, r3, #7 + 80063b8: 4a03 ldr r2, [pc, #12] ; (80063c8 ) + 80063ba: 5cd3 ldrb r3, [r2, r3] + 80063bc: fa21 f303 lsr.w r3, r1, r3 +} + 80063c0: 4618 mov r0, r3 + 80063c2: bd80 pop {r7, pc} + 80063c4: 40023800 .word 0x40023800 + 80063c8: 0800e928 .word 0x0800e928 + +080063cc : + * domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + 80063cc: b580 push {r7, lr} + 80063ce: b086 sub sp, #24 + 80063d0: af00 add r7, sp, #0 + 80063d2: 6078 str r0, [r7, #4] + uint32_t tickstart = 0U; + 80063d4: 2300 movs r3, #0 + 80063d6: 617b str r3, [r7, #20] + uint32_t tmpreg1 = 0U; + 80063d8: 2300 movs r3, #0 + 80063da: 613b str r3, [r7, #16] + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*---------------------------- I2S configuration ---------------------------*/ + if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || + 80063dc: 687b ldr r3, [r7, #4] + 80063de: 681b ldr r3, [r3, #0] + 80063e0: f003 0301 and.w r3, r3, #1 + 80063e4: 2b00 cmp r3, #0 + 80063e6: d105 bne.n 80063f4 + (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)) + 80063e8: 687b ldr r3, [r7, #4] + 80063ea: 681b ldr r3, [r3, #0] + 80063ec: f003 0304 and.w r3, r3, #4 + if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || + 80063f0: 2b00 cmp r3, #0 + 80063f2: d035 beq.n 8006460 + assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); +#if defined(STM32F411xE) + assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM)); +#endif /* STM32F411xE */ + /* Disable the PLLI2S */ + __HAL_RCC_PLLI2S_DISABLE(); + 80063f4: 4b67 ldr r3, [pc, #412] ; (8006594 ) + 80063f6: 2200 movs r2, #0 + 80063f8: 601a str r2, [r3, #0] + /* Get tick */ + tickstart = HAL_GetTick(); + 80063fa: f7fb ff8f bl 800231c + 80063fe: 6178 str r0, [r7, #20] + /* Wait till PLLI2S is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + 8006400: e008 b.n 8006414 + { + if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) + 8006402: f7fb ff8b bl 800231c + 8006406: 4602 mov r2, r0 + 8006408: 697b ldr r3, [r7, #20] + 800640a: 1ad3 subs r3, r2, r3 + 800640c: 2b02 cmp r3, #2 + 800640e: d901 bls.n 8006414 + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + 8006410: 2303 movs r3, #3 + 8006412: e0ba b.n 800658a + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + 8006414: 4b60 ldr r3, [pc, #384] ; (8006598 ) + 8006416: 681b ldr r3, [r3, #0] + 8006418: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 + 800641c: 2b00 cmp r3, #0 + 800641e: d1f0 bne.n 8006402 + __HAL_RCC_PLLI2S_I2SCLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SR); +#else + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLM) */ + /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR); + 8006420: 687b ldr r3, [r7, #4] + 8006422: 685b ldr r3, [r3, #4] + 8006424: 019a lsls r2, r3, #6 + 8006426: 687b ldr r3, [r7, #4] + 8006428: 689b ldr r3, [r3, #8] + 800642a: 071b lsls r3, r3, #28 + 800642c: 495a ldr r1, [pc, #360] ; (8006598 ) + 800642e: 4313 orrs r3, r2 + 8006430: f8c1 3084 str.w r3, [r1, #132] ; 0x84 +#endif /* STM32F411xE */ + + /* Enable the PLLI2S */ + __HAL_RCC_PLLI2S_ENABLE(); + 8006434: 4b57 ldr r3, [pc, #348] ; (8006594 ) + 8006436: 2201 movs r2, #1 + 8006438: 601a str r2, [r3, #0] + /* Get tick */ + tickstart = HAL_GetTick(); + 800643a: f7fb ff6f bl 800231c + 800643e: 6178 str r0, [r7, #20] + /* Wait till PLLI2S is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + 8006440: e008 b.n 8006454 + { + if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) + 8006442: f7fb ff6b bl 800231c + 8006446: 4602 mov r2, r0 + 8006448: 697b ldr r3, [r7, #20] + 800644a: 1ad3 subs r3, r2, r3 + 800644c: 2b02 cmp r3, #2 + 800644e: d901 bls.n 8006454 + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + 8006450: 2303 movs r3, #3 + 8006452: e09a b.n 800658a + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + 8006454: 4b50 ldr r3, [pc, #320] ; (8006598 ) + 8006456: 681b ldr r3, [r3, #0] + 8006458: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 + 800645c: 2b00 cmp r3, #0 + 800645e: d0f0 beq.n 8006442 + } + } + } + + /*---------------------------- RTC configuration ---------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) + 8006460: 687b ldr r3, [r7, #4] + 8006462: 681b ldr r3, [r3, #0] + 8006464: f003 0302 and.w r3, r3, #2 + 8006468: 2b00 cmp r3, #0 + 800646a: f000 8083 beq.w 8006574 + { + /* Check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + /* Enable Power Clock*/ + __HAL_RCC_PWR_CLK_ENABLE(); + 800646e: 2300 movs r3, #0 + 8006470: 60fb str r3, [r7, #12] + 8006472: 4b49 ldr r3, [pc, #292] ; (8006598 ) + 8006474: 6c1b ldr r3, [r3, #64] ; 0x40 + 8006476: 4a48 ldr r2, [pc, #288] ; (8006598 ) + 8006478: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 800647c: 6413 str r3, [r2, #64] ; 0x40 + 800647e: 4b46 ldr r3, [pc, #280] ; (8006598 ) + 8006480: 6c1b ldr r3, [r3, #64] ; 0x40 + 8006482: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8006486: 60fb str r3, [r7, #12] + 8006488: 68fb ldr r3, [r7, #12] + + /* Enable write access to Backup domain */ + PWR->CR |= PWR_CR_DBP; + 800648a: 4b44 ldr r3, [pc, #272] ; (800659c ) + 800648c: 681b ldr r3, [r3, #0] + 800648e: 4a43 ldr r2, [pc, #268] ; (800659c ) + 8006490: f443 7380 orr.w r3, r3, #256 ; 0x100 + 8006494: 6013 str r3, [r2, #0] + + /* Get tick */ + tickstart = HAL_GetTick(); + 8006496: f7fb ff41 bl 800231c + 800649a: 6178 str r0, [r7, #20] + + while((PWR->CR & PWR_CR_DBP) == RESET) + 800649c: e008 b.n 80064b0 + { + if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) + 800649e: f7fb ff3d bl 800231c + 80064a2: 4602 mov r2, r0 + 80064a4: 697b ldr r3, [r7, #20] + 80064a6: 1ad3 subs r3, r2, r3 + 80064a8: 2b02 cmp r3, #2 + 80064aa: d901 bls.n 80064b0 + { + return HAL_TIMEOUT; + 80064ac: 2303 movs r3, #3 + 80064ae: e06c b.n 800658a + while((PWR->CR & PWR_CR_DBP) == RESET) + 80064b0: 4b3a ldr r3, [pc, #232] ; (800659c ) + 80064b2: 681b ldr r3, [r3, #0] + 80064b4: f403 7380 and.w r3, r3, #256 ; 0x100 + 80064b8: 2b00 cmp r3, #0 + 80064ba: d0f0 beq.n 800649e + } + } + /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ + tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL); + 80064bc: 4b36 ldr r3, [pc, #216] ; (8006598 ) + 80064be: 6f1b ldr r3, [r3, #112] ; 0x70 + 80064c0: f403 7340 and.w r3, r3, #768 ; 0x300 + 80064c4: 613b str r3, [r7, #16] + if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) + 80064c6: 693b ldr r3, [r7, #16] + 80064c8: 2b00 cmp r3, #0 + 80064ca: d02f beq.n 800652c + 80064cc: 687b ldr r3, [r7, #4] + 80064ce: 68db ldr r3, [r3, #12] + 80064d0: f403 7340 and.w r3, r3, #768 ; 0x300 + 80064d4: 693a ldr r2, [r7, #16] + 80064d6: 429a cmp r2, r3 + 80064d8: d028 beq.n 800652c + { + /* Store the content of BDCR register before the reset of Backup Domain */ + tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + 80064da: 4b2f ldr r3, [pc, #188] ; (8006598 ) + 80064dc: 6f1b ldr r3, [r3, #112] ; 0x70 + 80064de: f423 7340 bic.w r3, r3, #768 ; 0x300 + 80064e2: 613b str r3, [r7, #16] + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + 80064e4: 4b2e ldr r3, [pc, #184] ; (80065a0 ) + 80064e6: 2201 movs r2, #1 + 80064e8: 601a str r2, [r3, #0] + __HAL_RCC_BACKUPRESET_RELEASE(); + 80064ea: 4b2d ldr r3, [pc, #180] ; (80065a0 ) + 80064ec: 2200 movs r2, #0 + 80064ee: 601a str r2, [r3, #0] + /* Restore the Content of BDCR register */ + RCC->BDCR = tmpreg1; + 80064f0: 4a29 ldr r2, [pc, #164] ; (8006598 ) + 80064f2: 693b ldr r3, [r7, #16] + 80064f4: 6713 str r3, [r2, #112] ; 0x70 + + /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ + if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) + 80064f6: 4b28 ldr r3, [pc, #160] ; (8006598 ) + 80064f8: 6f1b ldr r3, [r3, #112] ; 0x70 + 80064fa: f003 0301 and.w r3, r3, #1 + 80064fe: 2b01 cmp r3, #1 + 8006500: d114 bne.n 800652c + { + /* Get tick */ + tickstart = HAL_GetTick(); + 8006502: f7fb ff0b bl 800231c + 8006506: 6178 str r0, [r7, #20] + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 8006508: e00a b.n 8006520 + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 800650a: f7fb ff07 bl 800231c + 800650e: 4602 mov r2, r0 + 8006510: 697b ldr r3, [r7, #20] + 8006512: 1ad3 subs r3, r2, r3 + 8006514: f241 3288 movw r2, #5000 ; 0x1388 + 8006518: 4293 cmp r3, r2 + 800651a: d901 bls.n 8006520 + { + return HAL_TIMEOUT; + 800651c: 2303 movs r3, #3 + 800651e: e034 b.n 800658a + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 8006520: 4b1d ldr r3, [pc, #116] ; (8006598 ) + 8006522: 6f1b ldr r3, [r3, #112] ; 0x70 + 8006524: f003 0302 and.w r3, r3, #2 + 8006528: 2b00 cmp r3, #0 + 800652a: d0ee beq.n 800650a + } + } + } + } + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + 800652c: 687b ldr r3, [r7, #4] + 800652e: 68db ldr r3, [r3, #12] + 8006530: f403 7340 and.w r3, r3, #768 ; 0x300 + 8006534: f5b3 7f40 cmp.w r3, #768 ; 0x300 + 8006538: d10d bne.n 8006556 + 800653a: 4b17 ldr r3, [pc, #92] ; (8006598 ) + 800653c: 689b ldr r3, [r3, #8] + 800653e: f423 12f8 bic.w r2, r3, #2031616 ; 0x1f0000 + 8006542: 687b ldr r3, [r7, #4] + 8006544: 68db ldr r3, [r3, #12] + 8006546: f023 4370 bic.w r3, r3, #4026531840 ; 0xf0000000 + 800654a: f423 7340 bic.w r3, r3, #768 ; 0x300 + 800654e: 4912 ldr r1, [pc, #72] ; (8006598 ) + 8006550: 4313 orrs r3, r2 + 8006552: 608b str r3, [r1, #8] + 8006554: e005 b.n 8006562 + 8006556: 4b10 ldr r3, [pc, #64] ; (8006598 ) + 8006558: 689b ldr r3, [r3, #8] + 800655a: 4a0f ldr r2, [pc, #60] ; (8006598 ) + 800655c: f423 13f8 bic.w r3, r3, #2031616 ; 0x1f0000 + 8006560: 6093 str r3, [r2, #8] + 8006562: 4b0d ldr r3, [pc, #52] ; (8006598 ) + 8006564: 6f1a ldr r2, [r3, #112] ; 0x70 + 8006566: 687b ldr r3, [r7, #4] + 8006568: 68db ldr r3, [r3, #12] + 800656a: f3c3 030b ubfx r3, r3, #0, #12 + 800656e: 490a ldr r1, [pc, #40] ; (8006598 ) + 8006570: 4313 orrs r3, r2 + 8006572: 670b str r3, [r1, #112] ; 0x70 + } +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) + /*---------------------------- TIM configuration ---------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) + 8006574: 687b ldr r3, [r7, #4] + 8006576: 681b ldr r3, [r3, #0] + 8006578: f003 0308 and.w r3, r3, #8 + 800657c: 2b00 cmp r3, #0 + 800657e: d003 beq.n 8006588 + { + __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); + 8006580: 687b ldr r3, [r7, #4] + 8006582: 7c1a ldrb r2, [r3, #16] + 8006584: 4b07 ldr r3, [pc, #28] ; (80065a4 ) + 8006586: 601a str r2, [r3, #0] + } +#endif /* STM32F401xC || STM32F401xE || STM32F411xE */ + return HAL_OK; + 8006588: 2300 movs r3, #0 +} + 800658a: 4618 mov r0, r3 + 800658c: 3718 adds r7, #24 + 800658e: 46bd mov sp, r7 + 8006590: bd80 pop {r7, pc} + 8006592: bf00 nop + 8006594: 42470068 .word 0x42470068 + 8006598: 40023800 .word 0x40023800 + 800659c: 40007000 .word 0x40007000 + 80065a0: 42470e40 .word 0x42470e40 + 80065a4: 424711e0 .word 0x424711e0 + +080065a8 : + * This parameter can be one of the following values: + * @arg RCC_PERIPHCLK_I2S: I2S peripheral clock + * @retval Frequency in KHz + */ +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) +{ + 80065a8: b480 push {r7} + 80065aa: b087 sub sp, #28 + 80065ac: af00 add r7, sp, #0 + 80065ae: 6078 str r0, [r7, #4] + /* This variable used to store the I2S clock frequency (value in Hz) */ + uint32_t frequency = 0U; + 80065b0: 2300 movs r3, #0 + 80065b2: 617b str r3, [r7, #20] + /* This variable used to store the VCO Input (value in Hz) */ + uint32_t vcoinput = 0U; + 80065b4: 2300 movs r3, #0 + 80065b6: 613b str r3, [r7, #16] + uint32_t srcclk = 0U; + 80065b8: 2300 movs r3, #0 + 80065ba: 60fb str r3, [r7, #12] + /* This variable used to store the VCO Output (value in Hz) */ + uint32_t vcooutput = 0U; + 80065bc: 2300 movs r3, #0 + 80065be: 60bb str r3, [r7, #8] + switch (PeriphClk) + 80065c0: 687b ldr r3, [r7, #4] + 80065c2: 2b01 cmp r3, #1 + 80065c4: d13d bne.n 8006642 + { + case RCC_PERIPHCLK_I2S: + { + /* Get the current I2S source */ + srcclk = __HAL_RCC_GET_I2S_SOURCE(); + 80065c6: 4b22 ldr r3, [pc, #136] ; (8006650 ) + 80065c8: 689b ldr r3, [r3, #8] + 80065ca: f403 0300 and.w r3, r3, #8388608 ; 0x800000 + 80065ce: 60fb str r3, [r7, #12] + switch (srcclk) + 80065d0: 68fb ldr r3, [r7, #12] + 80065d2: 2b00 cmp r3, #0 + 80065d4: d004 beq.n 80065e0 + 80065d6: 2b01 cmp r3, #1 + 80065d8: d12f bne.n 800663a + { + /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ + case RCC_I2SCLKSOURCE_EXT: + { + /* Set the I2S clock to the external clock value */ + frequency = EXTERNAL_CLOCK_VALUE; + 80065da: 4b1e ldr r3, [pc, #120] ; (8006654 ) + 80065dc: 617b str r3, [r7, #20] + break; + 80065de: e02f b.n 8006640 + vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); + } +#else + /* Configure the PLLI2S division factor */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ + if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + 80065e0: 4b1b ldr r3, [pc, #108] ; (8006650 ) + 80065e2: 685b ldr r3, [r3, #4] + 80065e4: f403 0380 and.w r3, r3, #4194304 ; 0x400000 + 80065e8: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 + 80065ec: d108 bne.n 8006600 + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + 80065ee: 4b18 ldr r3, [pc, #96] ; (8006650 ) + 80065f0: 685b ldr r3, [r3, #4] + 80065f2: f003 033f and.w r3, r3, #63 ; 0x3f + 80065f6: 4a18 ldr r2, [pc, #96] ; (8006658 ) + 80065f8: fbb2 f3f3 udiv r3, r2, r3 + 80065fc: 613b str r3, [r7, #16] + 80065fe: e007 b.n 8006610 + } + else + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + 8006600: 4b13 ldr r3, [pc, #76] ; (8006650 ) + 8006602: 685b ldr r3, [r3, #4] + 8006604: f003 033f and.w r3, r3, #63 ; 0x3f + 8006608: 4a14 ldr r2, [pc, #80] ; (800665c ) + 800660a: fbb2 f3f3 udiv r3, r2, r3 + 800660e: 613b str r3, [r7, #16] + } +#endif /* STM32F411xE */ + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U))); + 8006610: 4b0f ldr r3, [pc, #60] ; (8006650 ) + 8006612: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 8006616: 099b lsrs r3, r3, #6 + 8006618: f3c3 0208 ubfx r2, r3, #0, #9 + 800661c: 693b ldr r3, [r7, #16] + 800661e: fb02 f303 mul.w r3, r2, r3 + 8006622: 60bb str r3, [r7, #8] + /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */ + frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U))); + 8006624: 4b0a ldr r3, [pc, #40] ; (8006650 ) + 8006626: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 800662a: 0f1b lsrs r3, r3, #28 + 800662c: f003 0307 and.w r3, r3, #7 + 8006630: 68ba ldr r2, [r7, #8] + 8006632: fbb2 f3f3 udiv r3, r2, r3 + 8006636: 617b str r3, [r7, #20] + break; + 8006638: e002 b.n 8006640 + } + /* Clock not enabled for I2S*/ + default: + { + frequency = 0U; + 800663a: 2300 movs r3, #0 + 800663c: 617b str r3, [r7, #20] + break; + 800663e: bf00 nop + } + } + break; + 8006640: bf00 nop + } + } + return frequency; + 8006642: 697b ldr r3, [r7, #20] +} + 8006644: 4618 mov r0, r3 + 8006646: 371c adds r7, #28 + 8006648: 46bd mov sp, r7 + 800664a: f85d 7b04 ldr.w r7, [sp], #4 + 800664e: 4770 bx lr + 8006650: 40023800 .word 0x40023800 + 8006654: 00bb8000 .word 0x00bb8000 + 8006658: 007a1200 .word 0x007a1200 + 800665c: 00f42400 .word 0x00f42400 + +08006660 : + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) +{ + 8006660: b580 push {r7, lr} + 8006662: b082 sub sp, #8 + 8006664: af00 add r7, sp, #0 + 8006666: 6078 str r0, [r7, #4] + /* Check the SPI handle allocation */ + if (hspi == NULL) + 8006668: 687b ldr r3, [r7, #4] + 800666a: 2b00 cmp r3, #0 + 800666c: d101 bne.n 8006672 + { + return HAL_ERROR; + 800666e: 2301 movs r3, #1 + 8006670: e056 b.n 8006720 + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); + } +#else + hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + 8006672: 687b ldr r3, [r7, #4] + 8006674: 2200 movs r2, #0 + 8006676: 629a str r2, [r3, #40] ; 0x28 +#endif /* USE_SPI_CRC */ + + if (hspi->State == HAL_SPI_STATE_RESET) + 8006678: 687b ldr r3, [r7, #4] + 800667a: f893 3051 ldrb.w r3, [r3, #81] ; 0x51 + 800667e: b2db uxtb r3, r3 + 8006680: 2b00 cmp r3, #0 + 8006682: d106 bne.n 8006692 + { + /* Allocate lock resource and initialize it */ + hspi->Lock = HAL_UNLOCKED; + 8006684: 687b ldr r3, [r7, #4] + 8006686: 2200 movs r2, #0 + 8006688: f883 2050 strb.w r2, [r3, #80] ; 0x50 + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + hspi->MspInitCallback(hspi); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_SPI_MspInit(hspi); + 800668c: 6878 ldr r0, [r7, #4] + 800668e: f7fb f935 bl 80018fc +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + + hspi->State = HAL_SPI_STATE_BUSY; + 8006692: 687b ldr r3, [r7, #4] + 8006694: 2202 movs r2, #2 + 8006696: f883 2051 strb.w r2, [r3, #81] ; 0x51 + + /* Disable the selected SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + 800669a: 687b ldr r3, [r7, #4] + 800669c: 681b ldr r3, [r3, #0] + 800669e: 681a ldr r2, [r3, #0] + 80066a0: 687b ldr r3, [r7, #4] + 80066a2: 681b ldr r3, [r3, #0] + 80066a4: f022 0240 bic.w r2, r2, #64 ; 0x40 + 80066a8: 601a str r2, [r3, #0] + + /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ + /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management, + Communication speed, First bit and CRC calculation state */ + WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize | + 80066aa: 687b ldr r3, [r7, #4] + 80066ac: 685a ldr r2, [r3, #4] + 80066ae: 687b ldr r3, [r7, #4] + 80066b0: 689b ldr r3, [r3, #8] + 80066b2: 431a orrs r2, r3 + 80066b4: 687b ldr r3, [r7, #4] + 80066b6: 68db ldr r3, [r3, #12] + 80066b8: 431a orrs r2, r3 + 80066ba: 687b ldr r3, [r7, #4] + 80066bc: 691b ldr r3, [r3, #16] + 80066be: 431a orrs r2, r3 + 80066c0: 687b ldr r3, [r7, #4] + 80066c2: 695b ldr r3, [r3, #20] + 80066c4: 431a orrs r2, r3 + 80066c6: 687b ldr r3, [r7, #4] + 80066c8: 699b ldr r3, [r3, #24] + 80066ca: f403 7300 and.w r3, r3, #512 ; 0x200 + 80066ce: 431a orrs r2, r3 + 80066d0: 687b ldr r3, [r7, #4] + 80066d2: 69db ldr r3, [r3, #28] + 80066d4: 431a orrs r2, r3 + 80066d6: 687b ldr r3, [r7, #4] + 80066d8: 6a1b ldr r3, [r3, #32] + 80066da: ea42 0103 orr.w r1, r2, r3 + 80066de: 687b ldr r3, [r7, #4] + 80066e0: 6a9a ldr r2, [r3, #40] ; 0x28 + 80066e2: 687b ldr r3, [r7, #4] + 80066e4: 681b ldr r3, [r3, #0] + 80066e6: 430a orrs r2, r1 + 80066e8: 601a str r2, [r3, #0] + hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) | + hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation)); + + /* Configure : NSS management, TI Mode */ + WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode)); + 80066ea: 687b ldr r3, [r7, #4] + 80066ec: 699b ldr r3, [r3, #24] + 80066ee: 0c1b lsrs r3, r3, #16 + 80066f0: f003 0104 and.w r1, r3, #4 + 80066f4: 687b ldr r3, [r7, #4] + 80066f6: 6a5a ldr r2, [r3, #36] ; 0x24 + 80066f8: 687b ldr r3, [r7, #4] + 80066fa: 681b ldr r3, [r3, #0] + 80066fc: 430a orrs r2, r1 + 80066fe: 605a str r2, [r3, #4] + } +#endif /* USE_SPI_CRC */ + +#if defined(SPI_I2SCFGR_I2SMOD) + /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ + CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); + 8006700: 687b ldr r3, [r7, #4] + 8006702: 681b ldr r3, [r3, #0] + 8006704: 69da ldr r2, [r3, #28] + 8006706: 687b ldr r3, [r7, #4] + 8006708: 681b ldr r3, [r3, #0] + 800670a: f422 6200 bic.w r2, r2, #2048 ; 0x800 + 800670e: 61da str r2, [r3, #28] +#endif /* SPI_I2SCFGR_I2SMOD */ + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 8006710: 687b ldr r3, [r7, #4] + 8006712: 2200 movs r2, #0 + 8006714: 655a str r2, [r3, #84] ; 0x54 + hspi->State = HAL_SPI_STATE_READY; + 8006716: 687b ldr r3, [r7, #4] + 8006718: 2201 movs r2, #1 + 800671a: f883 2051 strb.w r2, [r3, #81] ; 0x51 + + return HAL_OK; + 800671e: 2300 movs r3, #0 +} + 8006720: 4618 mov r0, r3 + 8006722: 3708 adds r7, #8 + 8006724: 46bd mov sp, r7 + 8006726: bd80 pop {r7, pc} + +08006728 : + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) +{ + 8006728: b580 push {r7, lr} + 800672a: b082 sub sp, #8 + 800672c: af00 add r7, sp, #0 + 800672e: 6078 str r0, [r7, #4] + /* Check the UART handle allocation */ + if (huart == NULL) + 8006730: 687b ldr r3, [r7, #4] + 8006732: 2b00 cmp r3, #0 + 8006734: d101 bne.n 800673a + { + return HAL_ERROR; + 8006736: 2301 movs r3, #1 + 8006738: e03f b.n 80067ba + assert_param(IS_UART_INSTANCE(huart->Instance)); + } + assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); + assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); + + if (huart->gState == HAL_UART_STATE_RESET) + 800673a: 687b ldr r3, [r7, #4] + 800673c: f893 3039 ldrb.w r3, [r3, #57] ; 0x39 + 8006740: b2db uxtb r3, r3 + 8006742: 2b00 cmp r3, #0 + 8006744: d106 bne.n 8006754 + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + 8006746: 687b ldr r3, [r7, #4] + 8006748: 2200 movs r2, #0 + 800674a: f883 2038 strb.w r2, [r3, #56] ; 0x38 + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); + 800674e: 6878 ldr r0, [r7, #4] + 8006750: f7fb f91c bl 800198c +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + 8006754: 687b ldr r3, [r7, #4] + 8006756: 2224 movs r2, #36 ; 0x24 + 8006758: f883 2039 strb.w r2, [r3, #57] ; 0x39 + + /* Disable the peripheral */ + __HAL_UART_DISABLE(huart); + 800675c: 687b ldr r3, [r7, #4] + 800675e: 681b ldr r3, [r3, #0] + 8006760: 68da ldr r2, [r3, #12] + 8006762: 687b ldr r3, [r7, #4] + 8006764: 681b ldr r3, [r3, #0] + 8006766: f422 5200 bic.w r2, r2, #8192 ; 0x2000 + 800676a: 60da str r2, [r3, #12] + + /* Set the UART Communication parameters */ + UART_SetConfig(huart); + 800676c: 6878 ldr r0, [r7, #4] + 800676e: f000 f90b bl 8006988 + + /* In asynchronous mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + 8006772: 687b ldr r3, [r7, #4] + 8006774: 681b ldr r3, [r3, #0] + 8006776: 691a ldr r2, [r3, #16] + 8006778: 687b ldr r3, [r7, #4] + 800677a: 681b ldr r3, [r3, #0] + 800677c: f422 4290 bic.w r2, r2, #18432 ; 0x4800 + 8006780: 611a str r2, [r3, #16] + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + 8006782: 687b ldr r3, [r7, #4] + 8006784: 681b ldr r3, [r3, #0] + 8006786: 695a ldr r2, [r3, #20] + 8006788: 687b ldr r3, [r7, #4] + 800678a: 681b ldr r3, [r3, #0] + 800678c: f022 022a bic.w r2, r2, #42 ; 0x2a + 8006790: 615a str r2, [r3, #20] + + /* Enable the peripheral */ + __HAL_UART_ENABLE(huart); + 8006792: 687b ldr r3, [r7, #4] + 8006794: 681b ldr r3, [r3, #0] + 8006796: 68da ldr r2, [r3, #12] + 8006798: 687b ldr r3, [r7, #4] + 800679a: 681b ldr r3, [r3, #0] + 800679c: f442 5200 orr.w r2, r2, #8192 ; 0x2000 + 80067a0: 60da str r2, [r3, #12] + + /* Initialize the UART state */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + 80067a2: 687b ldr r3, [r7, #4] + 80067a4: 2200 movs r2, #0 + 80067a6: 63da str r2, [r3, #60] ; 0x3c + huart->gState = HAL_UART_STATE_READY; + 80067a8: 687b ldr r3, [r7, #4] + 80067aa: 2220 movs r2, #32 + 80067ac: f883 2039 strb.w r2, [r3, #57] ; 0x39 + huart->RxState = HAL_UART_STATE_READY; + 80067b0: 687b ldr r3, [r7, #4] + 80067b2: 2220 movs r2, #32 + 80067b4: f883 203a strb.w r2, [r3, #58] ; 0x3a + + return HAL_OK; + 80067b8: 2300 movs r3, #0 +} + 80067ba: 4618 mov r0, r3 + 80067bc: 3708 adds r7, #8 + 80067be: 46bd mov sp, r7 + 80067c0: bd80 pop {r7, pc} + +080067c2 : + * @param Size Amount of data elements (u8 or u16) to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + 80067c2: b580 push {r7, lr} + 80067c4: b088 sub sp, #32 + 80067c6: af02 add r7, sp, #8 + 80067c8: 60f8 str r0, [r7, #12] + 80067ca: 60b9 str r1, [r7, #8] + 80067cc: 603b str r3, [r7, #0] + 80067ce: 4613 mov r3, r2 + 80067d0: 80fb strh r3, [r7, #6] + uint16_t *tmp; + uint32_t tickstart = 0U; + 80067d2: 2300 movs r3, #0 + 80067d4: 617b str r3, [r7, #20] + + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + 80067d6: 68fb ldr r3, [r7, #12] + 80067d8: f893 3039 ldrb.w r3, [r3, #57] ; 0x39 + 80067dc: b2db uxtb r3, r3 + 80067de: 2b20 cmp r3, #32 + 80067e0: f040 8083 bne.w 80068ea + { + if ((pData == NULL) || (Size == 0U)) + 80067e4: 68bb ldr r3, [r7, #8] + 80067e6: 2b00 cmp r3, #0 + 80067e8: d002 beq.n 80067f0 + 80067ea: 88fb ldrh r3, [r7, #6] + 80067ec: 2b00 cmp r3, #0 + 80067ee: d101 bne.n 80067f4 + { + return HAL_ERROR; + 80067f0: 2301 movs r3, #1 + 80067f2: e07b b.n 80068ec + } + + /* Process Locked */ + __HAL_LOCK(huart); + 80067f4: 68fb ldr r3, [r7, #12] + 80067f6: f893 3038 ldrb.w r3, [r3, #56] ; 0x38 + 80067fa: 2b01 cmp r3, #1 + 80067fc: d101 bne.n 8006802 + 80067fe: 2302 movs r3, #2 + 8006800: e074 b.n 80068ec + 8006802: 68fb ldr r3, [r7, #12] + 8006804: 2201 movs r2, #1 + 8006806: f883 2038 strb.w r2, [r3, #56] ; 0x38 + + huart->ErrorCode = HAL_UART_ERROR_NONE; + 800680a: 68fb ldr r3, [r7, #12] + 800680c: 2200 movs r2, #0 + 800680e: 63da str r2, [r3, #60] ; 0x3c + huart->gState = HAL_UART_STATE_BUSY_TX; + 8006810: 68fb ldr r3, [r7, #12] + 8006812: 2221 movs r2, #33 ; 0x21 + 8006814: f883 2039 strb.w r2, [r3, #57] ; 0x39 + + /* Init tickstart for timeout managment */ + tickstart = HAL_GetTick(); + 8006818: f7fb fd80 bl 800231c + 800681c: 6178 str r0, [r7, #20] + + huart->TxXferSize = Size; + 800681e: 68fb ldr r3, [r7, #12] + 8006820: 88fa ldrh r2, [r7, #6] + 8006822: 849a strh r2, [r3, #36] ; 0x24 + huart->TxXferCount = Size; + 8006824: 68fb ldr r3, [r7, #12] + 8006826: 88fa ldrh r2, [r7, #6] + 8006828: 84da strh r2, [r3, #38] ; 0x26 + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + 800682a: 68fb ldr r3, [r7, #12] + 800682c: 2200 movs r2, #0 + 800682e: f883 2038 strb.w r2, [r3, #56] ; 0x38 + + while (huart->TxXferCount > 0U) + 8006832: e042 b.n 80068ba + { + huart->TxXferCount--; + 8006834: 68fb ldr r3, [r7, #12] + 8006836: 8cdb ldrh r3, [r3, #38] ; 0x26 + 8006838: b29b uxth r3, r3 + 800683a: 3b01 subs r3, #1 + 800683c: b29a uxth r2, r3 + 800683e: 68fb ldr r3, [r7, #12] + 8006840: 84da strh r2, [r3, #38] ; 0x26 + if (huart->Init.WordLength == UART_WORDLENGTH_9B) + 8006842: 68fb ldr r3, [r7, #12] + 8006844: 689b ldr r3, [r3, #8] + 8006846: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 + 800684a: d122 bne.n 8006892 + { + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + 800684c: 683b ldr r3, [r7, #0] + 800684e: 9300 str r3, [sp, #0] + 8006850: 697b ldr r3, [r7, #20] + 8006852: 2200 movs r2, #0 + 8006854: 2180 movs r1, #128 ; 0x80 + 8006856: 68f8 ldr r0, [r7, #12] + 8006858: f000 f84c bl 80068f4 + 800685c: 4603 mov r3, r0 + 800685e: 2b00 cmp r3, #0 + 8006860: d001 beq.n 8006866 + { + return HAL_TIMEOUT; + 8006862: 2303 movs r3, #3 + 8006864: e042 b.n 80068ec + } + tmp = (uint16_t *) pData; + 8006866: 68bb ldr r3, [r7, #8] + 8006868: 613b str r3, [r7, #16] + huart->Instance->DR = (*tmp & (uint16_t)0x01FF); + 800686a: 693b ldr r3, [r7, #16] + 800686c: 881b ldrh r3, [r3, #0] + 800686e: 461a mov r2, r3 + 8006870: 68fb ldr r3, [r7, #12] + 8006872: 681b ldr r3, [r3, #0] + 8006874: f3c2 0208 ubfx r2, r2, #0, #9 + 8006878: 605a str r2, [r3, #4] + if (huart->Init.Parity == UART_PARITY_NONE) + 800687a: 68fb ldr r3, [r7, #12] + 800687c: 691b ldr r3, [r3, #16] + 800687e: 2b00 cmp r3, #0 + 8006880: d103 bne.n 800688a + { + pData += 2U; + 8006882: 68bb ldr r3, [r7, #8] + 8006884: 3302 adds r3, #2 + 8006886: 60bb str r3, [r7, #8] + 8006888: e017 b.n 80068ba + } + else + { + pData += 1U; + 800688a: 68bb ldr r3, [r7, #8] + 800688c: 3301 adds r3, #1 + 800688e: 60bb str r3, [r7, #8] + 8006890: e013 b.n 80068ba + } + } + else + { + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + 8006892: 683b ldr r3, [r7, #0] + 8006894: 9300 str r3, [sp, #0] + 8006896: 697b ldr r3, [r7, #20] + 8006898: 2200 movs r2, #0 + 800689a: 2180 movs r1, #128 ; 0x80 + 800689c: 68f8 ldr r0, [r7, #12] + 800689e: f000 f829 bl 80068f4 + 80068a2: 4603 mov r3, r0 + 80068a4: 2b00 cmp r3, #0 + 80068a6: d001 beq.n 80068ac + { + return HAL_TIMEOUT; + 80068a8: 2303 movs r3, #3 + 80068aa: e01f b.n 80068ec + } + huart->Instance->DR = (*pData++ & (uint8_t)0xFF); + 80068ac: 68bb ldr r3, [r7, #8] + 80068ae: 1c5a adds r2, r3, #1 + 80068b0: 60ba str r2, [r7, #8] + 80068b2: 781a ldrb r2, [r3, #0] + 80068b4: 68fb ldr r3, [r7, #12] + 80068b6: 681b ldr r3, [r3, #0] + 80068b8: 605a str r2, [r3, #4] + while (huart->TxXferCount > 0U) + 80068ba: 68fb ldr r3, [r7, #12] + 80068bc: 8cdb ldrh r3, [r3, #38] ; 0x26 + 80068be: b29b uxth r3, r3 + 80068c0: 2b00 cmp r3, #0 + 80068c2: d1b7 bne.n 8006834 + } + } + + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) + 80068c4: 683b ldr r3, [r7, #0] + 80068c6: 9300 str r3, [sp, #0] + 80068c8: 697b ldr r3, [r7, #20] + 80068ca: 2200 movs r2, #0 + 80068cc: 2140 movs r1, #64 ; 0x40 + 80068ce: 68f8 ldr r0, [r7, #12] + 80068d0: f000 f810 bl 80068f4 + 80068d4: 4603 mov r3, r0 + 80068d6: 2b00 cmp r3, #0 + 80068d8: d001 beq.n 80068de + { + return HAL_TIMEOUT; + 80068da: 2303 movs r3, #3 + 80068dc: e006 b.n 80068ec + } + + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + 80068de: 68fb ldr r3, [r7, #12] + 80068e0: 2220 movs r2, #32 + 80068e2: f883 2039 strb.w r2, [r3, #57] ; 0x39 + + return HAL_OK; + 80068e6: 2300 movs r3, #0 + 80068e8: e000 b.n 80068ec + } + else + { + return HAL_BUSY; + 80068ea: 2302 movs r3, #2 + } +} + 80068ec: 4618 mov r0, r3 + 80068ee: 3718 adds r7, #24 + 80068f0: 46bd mov sp, r7 + 80068f2: bd80 pop {r7, pc} + +080068f4 : + * @param Tickstart Tick start value + * @param Timeout Timeout duration + * @retval HAL status + */ +static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) +{ + 80068f4: b580 push {r7, lr} + 80068f6: b084 sub sp, #16 + 80068f8: af00 add r7, sp, #0 + 80068fa: 60f8 str r0, [r7, #12] + 80068fc: 60b9 str r1, [r7, #8] + 80068fe: 603b str r3, [r7, #0] + 8006900: 4613 mov r3, r2 + 8006902: 71fb strb r3, [r7, #7] + /* Wait until flag is set */ + while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) + 8006904: e02c b.n 8006960 + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + 8006906: 69bb ldr r3, [r7, #24] + 8006908: f1b3 3fff cmp.w r3, #4294967295 + 800690c: d028 beq.n 8006960 + { + if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) + 800690e: 69bb ldr r3, [r7, #24] + 8006910: 2b00 cmp r3, #0 + 8006912: d007 beq.n 8006924 + 8006914: f7fb fd02 bl 800231c + 8006918: 4602 mov r2, r0 + 800691a: 683b ldr r3, [r7, #0] + 800691c: 1ad3 subs r3, r2, r3 + 800691e: 69ba ldr r2, [r7, #24] + 8006920: 429a cmp r2, r3 + 8006922: d21d bcs.n 8006960 + { + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); + 8006924: 68fb ldr r3, [r7, #12] + 8006926: 681b ldr r3, [r3, #0] + 8006928: 68da ldr r2, [r3, #12] + 800692a: 68fb ldr r3, [r7, #12] + 800692c: 681b ldr r3, [r3, #0] + 800692e: f422 72d0 bic.w r2, r2, #416 ; 0x1a0 + 8006932: 60da str r2, [r3, #12] + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 8006934: 68fb ldr r3, [r7, #12] + 8006936: 681b ldr r3, [r3, #0] + 8006938: 695a ldr r2, [r3, #20] + 800693a: 68fb ldr r3, [r7, #12] + 800693c: 681b ldr r3, [r3, #0] + 800693e: f022 0201 bic.w r2, r2, #1 + 8006942: 615a str r2, [r3, #20] + + huart->gState = HAL_UART_STATE_READY; + 8006944: 68fb ldr r3, [r7, #12] + 8006946: 2220 movs r2, #32 + 8006948: f883 2039 strb.w r2, [r3, #57] ; 0x39 + huart->RxState = HAL_UART_STATE_READY; + 800694c: 68fb ldr r3, [r7, #12] + 800694e: 2220 movs r2, #32 + 8006950: f883 203a strb.w r2, [r3, #58] ; 0x3a + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + 8006954: 68fb ldr r3, [r7, #12] + 8006956: 2200 movs r2, #0 + 8006958: f883 2038 strb.w r2, [r3, #56] ; 0x38 + + return HAL_TIMEOUT; + 800695c: 2303 movs r3, #3 + 800695e: e00f b.n 8006980 + while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) + 8006960: 68fb ldr r3, [r7, #12] + 8006962: 681b ldr r3, [r3, #0] + 8006964: 681a ldr r2, [r3, #0] + 8006966: 68bb ldr r3, [r7, #8] + 8006968: 4013 ands r3, r2 + 800696a: 68ba ldr r2, [r7, #8] + 800696c: 429a cmp r2, r3 + 800696e: bf0c ite eq + 8006970: 2301 moveq r3, #1 + 8006972: 2300 movne r3, #0 + 8006974: b2db uxtb r3, r3 + 8006976: 461a mov r2, r3 + 8006978: 79fb ldrb r3, [r7, #7] + 800697a: 429a cmp r2, r3 + 800697c: d0c3 beq.n 8006906 + } + } + } + return HAL_OK; + 800697e: 2300 movs r3, #0 +} + 8006980: 4618 mov r0, r3 + 8006982: 3710 adds r7, #16 + 8006984: 46bd mov sp, r7 + 8006986: bd80 pop {r7, pc} + +08006988 : + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +static void UART_SetConfig(UART_HandleTypeDef *huart) +{ + 8006988: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 800698c: b085 sub sp, #20 + 800698e: af00 add r7, sp, #0 + 8006990: 6078 str r0, [r7, #4] + assert_param(IS_UART_MODE(huart->Init.Mode)); + + /*-------------------------- USART CR2 Configuration -----------------------*/ + /* Configure the UART Stop Bits: Set STOP[13:12] bits + according to huart->Init.StopBits value */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); + 8006992: 687b ldr r3, [r7, #4] + 8006994: 681b ldr r3, [r3, #0] + 8006996: 691b ldr r3, [r3, #16] + 8006998: f423 5140 bic.w r1, r3, #12288 ; 0x3000 + 800699c: 687b ldr r3, [r7, #4] + 800699e: 68da ldr r2, [r3, #12] + 80069a0: 687b ldr r3, [r7, #4] + 80069a2: 681b ldr r3, [r3, #0] + 80069a4: 430a orrs r2, r1 + 80069a6: 611a str r2, [r3, #16] + Set the M bits according to huart->Init.WordLength value + Set PCE and PS bits according to huart->Init.Parity value + Set TE and RE bits according to huart->Init.Mode value + Set OVER8 bit according to huart->Init.OverSampling value */ + + tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; + 80069a8: 687b ldr r3, [r7, #4] + 80069aa: 689a ldr r2, [r3, #8] + 80069ac: 687b ldr r3, [r7, #4] + 80069ae: 691b ldr r3, [r3, #16] + 80069b0: 431a orrs r2, r3 + 80069b2: 687b ldr r3, [r7, #4] + 80069b4: 695b ldr r3, [r3, #20] + 80069b6: 431a orrs r2, r3 + 80069b8: 687b ldr r3, [r7, #4] + 80069ba: 69db ldr r3, [r3, #28] + 80069bc: 4313 orrs r3, r2 + 80069be: 60fb str r3, [r7, #12] + MODIFY_REG(huart->Instance->CR1, + 80069c0: 687b ldr r3, [r7, #4] + 80069c2: 681b ldr r3, [r3, #0] + 80069c4: 68db ldr r3, [r3, #12] + 80069c6: f423 4316 bic.w r3, r3, #38400 ; 0x9600 + 80069ca: f023 030c bic.w r3, r3, #12 + 80069ce: 687a ldr r2, [r7, #4] + 80069d0: 6812 ldr r2, [r2, #0] + 80069d2: 68f9 ldr r1, [r7, #12] + 80069d4: 430b orrs r3, r1 + 80069d6: 60d3 str r3, [r2, #12] + (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), + tmpreg); + + /*-------------------------- USART CR3 Configuration -----------------------*/ + /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ + MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); + 80069d8: 687b ldr r3, [r7, #4] + 80069da: 681b ldr r3, [r3, #0] + 80069dc: 695b ldr r3, [r3, #20] + 80069de: f423 7140 bic.w r1, r3, #768 ; 0x300 + 80069e2: 687b ldr r3, [r7, #4] + 80069e4: 699a ldr r2, [r3, #24] + 80069e6: 687b ldr r3, [r7, #4] + 80069e8: 681b ldr r3, [r3, #0] + 80069ea: 430a orrs r2, r1 + 80069ec: 615a str r2, [r3, #20] + + /* Check the Over Sampling */ + if (huart->Init.OverSampling == UART_OVERSAMPLING_8) + 80069ee: 687b ldr r3, [r7, #4] + 80069f0: 69db ldr r3, [r3, #28] + 80069f2: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 + 80069f6: f040 818b bne.w 8006d10 + { + pclk = HAL_RCC_GetPCLK2Freq(); + huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate); + } +#elif defined(USART6) + if ((huart->Instance == USART1) || (huart->Instance == USART6)) + 80069fa: 687b ldr r3, [r7, #4] + 80069fc: 681b ldr r3, [r3, #0] + 80069fe: 4ac1 ldr r2, [pc, #772] ; (8006d04 ) + 8006a00: 4293 cmp r3, r2 + 8006a02: d005 beq.n 8006a10 + 8006a04: 687b ldr r3, [r7, #4] + 8006a06: 681b ldr r3, [r3, #0] + 8006a08: 4abf ldr r2, [pc, #764] ; (8006d08 ) + 8006a0a: 4293 cmp r3, r2 + 8006a0c: f040 80bd bne.w 8006b8a + { + pclk = HAL_RCC_GetPCLK2Freq(); + 8006a10: f7ff fcc8 bl 80063a4 + 8006a14: 60b8 str r0, [r7, #8] + huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate); + 8006a16: 68bb ldr r3, [r7, #8] + 8006a18: 461d mov r5, r3 + 8006a1a: f04f 0600 mov.w r6, #0 + 8006a1e: 46a8 mov r8, r5 + 8006a20: 46b1 mov r9, r6 + 8006a22: eb18 0308 adds.w r3, r8, r8 + 8006a26: eb49 0409 adc.w r4, r9, r9 + 8006a2a: 4698 mov r8, r3 + 8006a2c: 46a1 mov r9, r4 + 8006a2e: eb18 0805 adds.w r8, r8, r5 + 8006a32: eb49 0906 adc.w r9, r9, r6 + 8006a36: f04f 0100 mov.w r1, #0 + 8006a3a: f04f 0200 mov.w r2, #0 + 8006a3e: ea4f 02c9 mov.w r2, r9, lsl #3 + 8006a42: ea42 7258 orr.w r2, r2, r8, lsr #29 + 8006a46: ea4f 01c8 mov.w r1, r8, lsl #3 + 8006a4a: 4688 mov r8, r1 + 8006a4c: 4691 mov r9, r2 + 8006a4e: eb18 0005 adds.w r0, r8, r5 + 8006a52: eb49 0106 adc.w r1, r9, r6 + 8006a56: 687b ldr r3, [r7, #4] + 8006a58: 685b ldr r3, [r3, #4] + 8006a5a: 461d mov r5, r3 + 8006a5c: f04f 0600 mov.w r6, #0 + 8006a60: 196b adds r3, r5, r5 + 8006a62: eb46 0406 adc.w r4, r6, r6 + 8006a66: 461a mov r2, r3 + 8006a68: 4623 mov r3, r4 + 8006a6a: f7fa f915 bl 8000c98 <__aeabi_uldivmod> + 8006a6e: 4603 mov r3, r0 + 8006a70: 460c mov r4, r1 + 8006a72: 461a mov r2, r3 + 8006a74: 4ba5 ldr r3, [pc, #660] ; (8006d0c ) + 8006a76: fba3 2302 umull r2, r3, r3, r2 + 8006a7a: 095b lsrs r3, r3, #5 + 8006a7c: ea4f 1803 mov.w r8, r3, lsl #4 + 8006a80: 68bb ldr r3, [r7, #8] + 8006a82: 461d mov r5, r3 + 8006a84: f04f 0600 mov.w r6, #0 + 8006a88: 46a9 mov r9, r5 + 8006a8a: 46b2 mov sl, r6 + 8006a8c: eb19 0309 adds.w r3, r9, r9 + 8006a90: eb4a 040a adc.w r4, sl, sl + 8006a94: 4699 mov r9, r3 + 8006a96: 46a2 mov sl, r4 + 8006a98: eb19 0905 adds.w r9, r9, r5 + 8006a9c: eb4a 0a06 adc.w sl, sl, r6 + 8006aa0: f04f 0100 mov.w r1, #0 + 8006aa4: f04f 0200 mov.w r2, #0 + 8006aa8: ea4f 02ca mov.w r2, sl, lsl #3 + 8006aac: ea42 7259 orr.w r2, r2, r9, lsr #29 + 8006ab0: ea4f 01c9 mov.w r1, r9, lsl #3 + 8006ab4: 4689 mov r9, r1 + 8006ab6: 4692 mov sl, r2 + 8006ab8: eb19 0005 adds.w r0, r9, r5 + 8006abc: eb4a 0106 adc.w r1, sl, r6 + 8006ac0: 687b ldr r3, [r7, #4] + 8006ac2: 685b ldr r3, [r3, #4] + 8006ac4: 461d mov r5, r3 + 8006ac6: f04f 0600 mov.w r6, #0 + 8006aca: 196b adds r3, r5, r5 + 8006acc: eb46 0406 adc.w r4, r6, r6 + 8006ad0: 461a mov r2, r3 + 8006ad2: 4623 mov r3, r4 + 8006ad4: f7fa f8e0 bl 8000c98 <__aeabi_uldivmod> + 8006ad8: 4603 mov r3, r0 + 8006ada: 460c mov r4, r1 + 8006adc: 461a mov r2, r3 + 8006ade: 4b8b ldr r3, [pc, #556] ; (8006d0c ) + 8006ae0: fba3 1302 umull r1, r3, r3, r2 + 8006ae4: 095b lsrs r3, r3, #5 + 8006ae6: 2164 movs r1, #100 ; 0x64 + 8006ae8: fb01 f303 mul.w r3, r1, r3 + 8006aec: 1ad3 subs r3, r2, r3 + 8006aee: 00db lsls r3, r3, #3 + 8006af0: 3332 adds r3, #50 ; 0x32 + 8006af2: 4a86 ldr r2, [pc, #536] ; (8006d0c ) + 8006af4: fba2 2303 umull r2, r3, r2, r3 + 8006af8: 095b lsrs r3, r3, #5 + 8006afa: 005b lsls r3, r3, #1 + 8006afc: f403 73f8 and.w r3, r3, #496 ; 0x1f0 + 8006b00: 4498 add r8, r3 + 8006b02: 68bb ldr r3, [r7, #8] + 8006b04: 461d mov r5, r3 + 8006b06: f04f 0600 mov.w r6, #0 + 8006b0a: 46a9 mov r9, r5 + 8006b0c: 46b2 mov sl, r6 + 8006b0e: eb19 0309 adds.w r3, r9, r9 + 8006b12: eb4a 040a adc.w r4, sl, sl + 8006b16: 4699 mov r9, r3 + 8006b18: 46a2 mov sl, r4 + 8006b1a: eb19 0905 adds.w r9, r9, r5 + 8006b1e: eb4a 0a06 adc.w sl, sl, r6 + 8006b22: f04f 0100 mov.w r1, #0 + 8006b26: f04f 0200 mov.w r2, #0 + 8006b2a: ea4f 02ca mov.w r2, sl, lsl #3 + 8006b2e: ea42 7259 orr.w r2, r2, r9, lsr #29 + 8006b32: ea4f 01c9 mov.w r1, r9, lsl #3 + 8006b36: 4689 mov r9, r1 + 8006b38: 4692 mov sl, r2 + 8006b3a: eb19 0005 adds.w r0, r9, r5 + 8006b3e: eb4a 0106 adc.w r1, sl, r6 + 8006b42: 687b ldr r3, [r7, #4] + 8006b44: 685b ldr r3, [r3, #4] + 8006b46: 461d mov r5, r3 + 8006b48: f04f 0600 mov.w r6, #0 + 8006b4c: 196b adds r3, r5, r5 + 8006b4e: eb46 0406 adc.w r4, r6, r6 + 8006b52: 461a mov r2, r3 + 8006b54: 4623 mov r3, r4 + 8006b56: f7fa f89f bl 8000c98 <__aeabi_uldivmod> + 8006b5a: 4603 mov r3, r0 + 8006b5c: 460c mov r4, r1 + 8006b5e: 461a mov r2, r3 + 8006b60: 4b6a ldr r3, [pc, #424] ; (8006d0c ) + 8006b62: fba3 1302 umull r1, r3, r3, r2 + 8006b66: 095b lsrs r3, r3, #5 + 8006b68: 2164 movs r1, #100 ; 0x64 + 8006b6a: fb01 f303 mul.w r3, r1, r3 + 8006b6e: 1ad3 subs r3, r2, r3 + 8006b70: 00db lsls r3, r3, #3 + 8006b72: 3332 adds r3, #50 ; 0x32 + 8006b74: 4a65 ldr r2, [pc, #404] ; (8006d0c ) + 8006b76: fba2 2303 umull r2, r3, r2, r3 + 8006b7a: 095b lsrs r3, r3, #5 + 8006b7c: f003 0207 and.w r2, r3, #7 + 8006b80: 687b ldr r3, [r7, #4] + 8006b82: 681b ldr r3, [r3, #0] + 8006b84: 4442 add r2, r8 + 8006b86: 609a str r2, [r3, #8] + 8006b88: e26f b.n 800706a + huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate); + } +#endif /* USART6 */ + else + { + pclk = HAL_RCC_GetPCLK1Freq(); + 8006b8a: f7ff fbf7 bl 800637c + 8006b8e: 60b8 str r0, [r7, #8] + huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate); + 8006b90: 68bb ldr r3, [r7, #8] + 8006b92: 461d mov r5, r3 + 8006b94: f04f 0600 mov.w r6, #0 + 8006b98: 46a8 mov r8, r5 + 8006b9a: 46b1 mov r9, r6 + 8006b9c: eb18 0308 adds.w r3, r8, r8 + 8006ba0: eb49 0409 adc.w r4, r9, r9 + 8006ba4: 4698 mov r8, r3 + 8006ba6: 46a1 mov r9, r4 + 8006ba8: eb18 0805 adds.w r8, r8, r5 + 8006bac: eb49 0906 adc.w r9, r9, r6 + 8006bb0: f04f 0100 mov.w r1, #0 + 8006bb4: f04f 0200 mov.w r2, #0 + 8006bb8: ea4f 02c9 mov.w r2, r9, lsl #3 + 8006bbc: ea42 7258 orr.w r2, r2, r8, lsr #29 + 8006bc0: ea4f 01c8 mov.w r1, r8, lsl #3 + 8006bc4: 4688 mov r8, r1 + 8006bc6: 4691 mov r9, r2 + 8006bc8: eb18 0005 adds.w r0, r8, r5 + 8006bcc: eb49 0106 adc.w r1, r9, r6 + 8006bd0: 687b ldr r3, [r7, #4] + 8006bd2: 685b ldr r3, [r3, #4] + 8006bd4: 461d mov r5, r3 + 8006bd6: f04f 0600 mov.w r6, #0 + 8006bda: 196b adds r3, r5, r5 + 8006bdc: eb46 0406 adc.w r4, r6, r6 + 8006be0: 461a mov r2, r3 + 8006be2: 4623 mov r3, r4 + 8006be4: f7fa f858 bl 8000c98 <__aeabi_uldivmod> + 8006be8: 4603 mov r3, r0 + 8006bea: 460c mov r4, r1 + 8006bec: 461a mov r2, r3 + 8006bee: 4b47 ldr r3, [pc, #284] ; (8006d0c ) + 8006bf0: fba3 2302 umull r2, r3, r3, r2 + 8006bf4: 095b lsrs r3, r3, #5 + 8006bf6: ea4f 1803 mov.w r8, r3, lsl #4 + 8006bfa: 68bb ldr r3, [r7, #8] + 8006bfc: 461d mov r5, r3 + 8006bfe: f04f 0600 mov.w r6, #0 + 8006c02: 46a9 mov r9, r5 + 8006c04: 46b2 mov sl, r6 + 8006c06: eb19 0309 adds.w r3, r9, r9 + 8006c0a: eb4a 040a adc.w r4, sl, sl + 8006c0e: 4699 mov r9, r3 + 8006c10: 46a2 mov sl, r4 + 8006c12: eb19 0905 adds.w r9, r9, r5 + 8006c16: eb4a 0a06 adc.w sl, sl, r6 + 8006c1a: f04f 0100 mov.w r1, #0 + 8006c1e: f04f 0200 mov.w r2, #0 + 8006c22: ea4f 02ca mov.w r2, sl, lsl #3 + 8006c26: ea42 7259 orr.w r2, r2, r9, lsr #29 + 8006c2a: ea4f 01c9 mov.w r1, r9, lsl #3 + 8006c2e: 4689 mov r9, r1 + 8006c30: 4692 mov sl, r2 + 8006c32: eb19 0005 adds.w r0, r9, r5 + 8006c36: eb4a 0106 adc.w r1, sl, r6 + 8006c3a: 687b ldr r3, [r7, #4] + 8006c3c: 685b ldr r3, [r3, #4] + 8006c3e: 461d mov r5, r3 + 8006c40: f04f 0600 mov.w r6, #0 + 8006c44: 196b adds r3, r5, r5 + 8006c46: eb46 0406 adc.w r4, r6, r6 + 8006c4a: 461a mov r2, r3 + 8006c4c: 4623 mov r3, r4 + 8006c4e: f7fa f823 bl 8000c98 <__aeabi_uldivmod> + 8006c52: 4603 mov r3, r0 + 8006c54: 460c mov r4, r1 + 8006c56: 461a mov r2, r3 + 8006c58: 4b2c ldr r3, [pc, #176] ; (8006d0c ) + 8006c5a: fba3 1302 umull r1, r3, r3, r2 + 8006c5e: 095b lsrs r3, r3, #5 + 8006c60: 2164 movs r1, #100 ; 0x64 + 8006c62: fb01 f303 mul.w r3, r1, r3 + 8006c66: 1ad3 subs r3, r2, r3 + 8006c68: 00db lsls r3, r3, #3 + 8006c6a: 3332 adds r3, #50 ; 0x32 + 8006c6c: 4a27 ldr r2, [pc, #156] ; (8006d0c ) + 8006c6e: fba2 2303 umull r2, r3, r2, r3 + 8006c72: 095b lsrs r3, r3, #5 + 8006c74: 005b lsls r3, r3, #1 + 8006c76: f403 73f8 and.w r3, r3, #496 ; 0x1f0 + 8006c7a: 4498 add r8, r3 + 8006c7c: 68bb ldr r3, [r7, #8] + 8006c7e: 461d mov r5, r3 + 8006c80: f04f 0600 mov.w r6, #0 + 8006c84: 46a9 mov r9, r5 + 8006c86: 46b2 mov sl, r6 + 8006c88: eb19 0309 adds.w r3, r9, r9 + 8006c8c: eb4a 040a adc.w r4, sl, sl + 8006c90: 4699 mov r9, r3 + 8006c92: 46a2 mov sl, r4 + 8006c94: eb19 0905 adds.w r9, r9, r5 + 8006c98: eb4a 0a06 adc.w sl, sl, r6 + 8006c9c: f04f 0100 mov.w r1, #0 + 8006ca0: f04f 0200 mov.w r2, #0 + 8006ca4: ea4f 02ca mov.w r2, sl, lsl #3 + 8006ca8: ea42 7259 orr.w r2, r2, r9, lsr #29 + 8006cac: ea4f 01c9 mov.w r1, r9, lsl #3 + 8006cb0: 4689 mov r9, r1 + 8006cb2: 4692 mov sl, r2 + 8006cb4: eb19 0005 adds.w r0, r9, r5 + 8006cb8: eb4a 0106 adc.w r1, sl, r6 + 8006cbc: 687b ldr r3, [r7, #4] + 8006cbe: 685b ldr r3, [r3, #4] + 8006cc0: 461d mov r5, r3 + 8006cc2: f04f 0600 mov.w r6, #0 + 8006cc6: 196b adds r3, r5, r5 + 8006cc8: eb46 0406 adc.w r4, r6, r6 + 8006ccc: 461a mov r2, r3 + 8006cce: 4623 mov r3, r4 + 8006cd0: f7f9 ffe2 bl 8000c98 <__aeabi_uldivmod> + 8006cd4: 4603 mov r3, r0 + 8006cd6: 460c mov r4, r1 + 8006cd8: 461a mov r2, r3 + 8006cda: 4b0c ldr r3, [pc, #48] ; (8006d0c ) + 8006cdc: fba3 1302 umull r1, r3, r3, r2 + 8006ce0: 095b lsrs r3, r3, #5 + 8006ce2: 2164 movs r1, #100 ; 0x64 + 8006ce4: fb01 f303 mul.w r3, r1, r3 + 8006ce8: 1ad3 subs r3, r2, r3 + 8006cea: 00db lsls r3, r3, #3 + 8006cec: 3332 adds r3, #50 ; 0x32 + 8006cee: 4a07 ldr r2, [pc, #28] ; (8006d0c ) + 8006cf0: fba2 2303 umull r2, r3, r2, r3 + 8006cf4: 095b lsrs r3, r3, #5 + 8006cf6: f003 0207 and.w r2, r3, #7 + 8006cfa: 687b ldr r3, [r7, #4] + 8006cfc: 681b ldr r3, [r3, #0] + 8006cfe: 4442 add r2, r8 + 8006d00: 609a str r2, [r3, #8] + { + pclk = HAL_RCC_GetPCLK1Freq(); + huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); + } + } +} + 8006d02: e1b2 b.n 800706a + 8006d04: 40011000 .word 0x40011000 + 8006d08: 40011400 .word 0x40011400 + 8006d0c: 51eb851f .word 0x51eb851f + if ((huart->Instance == USART1) || (huart->Instance == USART6)) + 8006d10: 687b ldr r3, [r7, #4] + 8006d12: 681b ldr r3, [r3, #0] + 8006d14: 4ad7 ldr r2, [pc, #860] ; (8007074 ) + 8006d16: 4293 cmp r3, r2 + 8006d18: d005 beq.n 8006d26 + 8006d1a: 687b ldr r3, [r7, #4] + 8006d1c: 681b ldr r3, [r3, #0] + 8006d1e: 4ad6 ldr r2, [pc, #856] ; (8007078 ) + 8006d20: 4293 cmp r3, r2 + 8006d22: f040 80d1 bne.w 8006ec8 + pclk = HAL_RCC_GetPCLK2Freq(); + 8006d26: f7ff fb3d bl 80063a4 + 8006d2a: 60b8 str r0, [r7, #8] + huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); + 8006d2c: 68bb ldr r3, [r7, #8] + 8006d2e: 469a mov sl, r3 + 8006d30: f04f 0b00 mov.w fp, #0 + 8006d34: 46d0 mov r8, sl + 8006d36: 46d9 mov r9, fp + 8006d38: eb18 0308 adds.w r3, r8, r8 + 8006d3c: eb49 0409 adc.w r4, r9, r9 + 8006d40: 4698 mov r8, r3 + 8006d42: 46a1 mov r9, r4 + 8006d44: eb18 080a adds.w r8, r8, sl + 8006d48: eb49 090b adc.w r9, r9, fp + 8006d4c: f04f 0100 mov.w r1, #0 + 8006d50: f04f 0200 mov.w r2, #0 + 8006d54: ea4f 02c9 mov.w r2, r9, lsl #3 + 8006d58: ea42 7258 orr.w r2, r2, r8, lsr #29 + 8006d5c: ea4f 01c8 mov.w r1, r8, lsl #3 + 8006d60: 4688 mov r8, r1 + 8006d62: 4691 mov r9, r2 + 8006d64: eb1a 0508 adds.w r5, sl, r8 + 8006d68: eb4b 0609 adc.w r6, fp, r9 + 8006d6c: 687b ldr r3, [r7, #4] + 8006d6e: 685b ldr r3, [r3, #4] + 8006d70: 4619 mov r1, r3 + 8006d72: f04f 0200 mov.w r2, #0 + 8006d76: f04f 0300 mov.w r3, #0 + 8006d7a: f04f 0400 mov.w r4, #0 + 8006d7e: 0094 lsls r4, r2, #2 + 8006d80: ea44 7491 orr.w r4, r4, r1, lsr #30 + 8006d84: 008b lsls r3, r1, #2 + 8006d86: 461a mov r2, r3 + 8006d88: 4623 mov r3, r4 + 8006d8a: 4628 mov r0, r5 + 8006d8c: 4631 mov r1, r6 + 8006d8e: f7f9 ff83 bl 8000c98 <__aeabi_uldivmod> + 8006d92: 4603 mov r3, r0 + 8006d94: 460c mov r4, r1 + 8006d96: 461a mov r2, r3 + 8006d98: 4bb8 ldr r3, [pc, #736] ; (800707c ) + 8006d9a: fba3 2302 umull r2, r3, r3, r2 + 8006d9e: 095b lsrs r3, r3, #5 + 8006da0: ea4f 1803 mov.w r8, r3, lsl #4 + 8006da4: 68bb ldr r3, [r7, #8] + 8006da6: 469b mov fp, r3 + 8006da8: f04f 0c00 mov.w ip, #0 + 8006dac: 46d9 mov r9, fp + 8006dae: 46e2 mov sl, ip + 8006db0: eb19 0309 adds.w r3, r9, r9 + 8006db4: eb4a 040a adc.w r4, sl, sl + 8006db8: 4699 mov r9, r3 + 8006dba: 46a2 mov sl, r4 + 8006dbc: eb19 090b adds.w r9, r9, fp + 8006dc0: eb4a 0a0c adc.w sl, sl, ip + 8006dc4: f04f 0100 mov.w r1, #0 + 8006dc8: f04f 0200 mov.w r2, #0 + 8006dcc: ea4f 02ca mov.w r2, sl, lsl #3 + 8006dd0: ea42 7259 orr.w r2, r2, r9, lsr #29 + 8006dd4: ea4f 01c9 mov.w r1, r9, lsl #3 + 8006dd8: 4689 mov r9, r1 + 8006dda: 4692 mov sl, r2 + 8006ddc: eb1b 0509 adds.w r5, fp, r9 + 8006de0: eb4c 060a adc.w r6, ip, sl + 8006de4: 687b ldr r3, [r7, #4] + 8006de6: 685b ldr r3, [r3, #4] + 8006de8: 4619 mov r1, r3 + 8006dea: f04f 0200 mov.w r2, #0 + 8006dee: f04f 0300 mov.w r3, #0 + 8006df2: f04f 0400 mov.w r4, #0 + 8006df6: 0094 lsls r4, r2, #2 + 8006df8: ea44 7491 orr.w r4, r4, r1, lsr #30 + 8006dfc: 008b lsls r3, r1, #2 + 8006dfe: 461a mov r2, r3 + 8006e00: 4623 mov r3, r4 + 8006e02: 4628 mov r0, r5 + 8006e04: 4631 mov r1, r6 + 8006e06: f7f9 ff47 bl 8000c98 <__aeabi_uldivmod> + 8006e0a: 4603 mov r3, r0 + 8006e0c: 460c mov r4, r1 + 8006e0e: 461a mov r2, r3 + 8006e10: 4b9a ldr r3, [pc, #616] ; (800707c ) + 8006e12: fba3 1302 umull r1, r3, r3, r2 + 8006e16: 095b lsrs r3, r3, #5 + 8006e18: 2164 movs r1, #100 ; 0x64 + 8006e1a: fb01 f303 mul.w r3, r1, r3 + 8006e1e: 1ad3 subs r3, r2, r3 + 8006e20: 011b lsls r3, r3, #4 + 8006e22: 3332 adds r3, #50 ; 0x32 + 8006e24: 4a95 ldr r2, [pc, #596] ; (800707c ) + 8006e26: fba2 2303 umull r2, r3, r2, r3 + 8006e2a: 095b lsrs r3, r3, #5 + 8006e2c: f003 03f0 and.w r3, r3, #240 ; 0xf0 + 8006e30: 4498 add r8, r3 + 8006e32: 68bb ldr r3, [r7, #8] + 8006e34: 469b mov fp, r3 + 8006e36: f04f 0c00 mov.w ip, #0 + 8006e3a: 46d9 mov r9, fp + 8006e3c: 46e2 mov sl, ip + 8006e3e: eb19 0309 adds.w r3, r9, r9 + 8006e42: eb4a 040a adc.w r4, sl, sl + 8006e46: 4699 mov r9, r3 + 8006e48: 46a2 mov sl, r4 + 8006e4a: eb19 090b adds.w r9, r9, fp + 8006e4e: eb4a 0a0c adc.w sl, sl, ip + 8006e52: f04f 0100 mov.w r1, #0 + 8006e56: f04f 0200 mov.w r2, #0 + 8006e5a: ea4f 02ca mov.w r2, sl, lsl #3 + 8006e5e: ea42 7259 orr.w r2, r2, r9, lsr #29 + 8006e62: ea4f 01c9 mov.w r1, r9, lsl #3 + 8006e66: 4689 mov r9, r1 + 8006e68: 4692 mov sl, r2 + 8006e6a: eb1b 0509 adds.w r5, fp, r9 + 8006e6e: eb4c 060a adc.w r6, ip, sl + 8006e72: 687b ldr r3, [r7, #4] + 8006e74: 685b ldr r3, [r3, #4] + 8006e76: 4619 mov r1, r3 + 8006e78: f04f 0200 mov.w r2, #0 + 8006e7c: f04f 0300 mov.w r3, #0 + 8006e80: f04f 0400 mov.w r4, #0 + 8006e84: 0094 lsls r4, r2, #2 + 8006e86: ea44 7491 orr.w r4, r4, r1, lsr #30 + 8006e8a: 008b lsls r3, r1, #2 + 8006e8c: 461a mov r2, r3 + 8006e8e: 4623 mov r3, r4 + 8006e90: 4628 mov r0, r5 + 8006e92: 4631 mov r1, r6 + 8006e94: f7f9 ff00 bl 8000c98 <__aeabi_uldivmod> + 8006e98: 4603 mov r3, r0 + 8006e9a: 460c mov r4, r1 + 8006e9c: 461a mov r2, r3 + 8006e9e: 4b77 ldr r3, [pc, #476] ; (800707c ) + 8006ea0: fba3 1302 umull r1, r3, r3, r2 + 8006ea4: 095b lsrs r3, r3, #5 + 8006ea6: 2164 movs r1, #100 ; 0x64 + 8006ea8: fb01 f303 mul.w r3, r1, r3 + 8006eac: 1ad3 subs r3, r2, r3 + 8006eae: 011b lsls r3, r3, #4 + 8006eb0: 3332 adds r3, #50 ; 0x32 + 8006eb2: 4a72 ldr r2, [pc, #456] ; (800707c ) + 8006eb4: fba2 2303 umull r2, r3, r2, r3 + 8006eb8: 095b lsrs r3, r3, #5 + 8006eba: f003 020f and.w r2, r3, #15 + 8006ebe: 687b ldr r3, [r7, #4] + 8006ec0: 681b ldr r3, [r3, #0] + 8006ec2: 4442 add r2, r8 + 8006ec4: 609a str r2, [r3, #8] + 8006ec6: e0d0 b.n 800706a + pclk = HAL_RCC_GetPCLK1Freq(); + 8006ec8: f7ff fa58 bl 800637c + 8006ecc: 60b8 str r0, [r7, #8] + huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); + 8006ece: 68bb ldr r3, [r7, #8] + 8006ed0: 469a mov sl, r3 + 8006ed2: f04f 0b00 mov.w fp, #0 + 8006ed6: 46d0 mov r8, sl + 8006ed8: 46d9 mov r9, fp + 8006eda: eb18 0308 adds.w r3, r8, r8 + 8006ede: eb49 0409 adc.w r4, r9, r9 + 8006ee2: 4698 mov r8, r3 + 8006ee4: 46a1 mov r9, r4 + 8006ee6: eb18 080a adds.w r8, r8, sl + 8006eea: eb49 090b adc.w r9, r9, fp + 8006eee: f04f 0100 mov.w r1, #0 + 8006ef2: f04f 0200 mov.w r2, #0 + 8006ef6: ea4f 02c9 mov.w r2, r9, lsl #3 + 8006efa: ea42 7258 orr.w r2, r2, r8, lsr #29 + 8006efe: ea4f 01c8 mov.w r1, r8, lsl #3 + 8006f02: 4688 mov r8, r1 + 8006f04: 4691 mov r9, r2 + 8006f06: eb1a 0508 adds.w r5, sl, r8 + 8006f0a: eb4b 0609 adc.w r6, fp, r9 + 8006f0e: 687b ldr r3, [r7, #4] + 8006f10: 685b ldr r3, [r3, #4] + 8006f12: 4619 mov r1, r3 + 8006f14: f04f 0200 mov.w r2, #0 + 8006f18: f04f 0300 mov.w r3, #0 + 8006f1c: f04f 0400 mov.w r4, #0 + 8006f20: 0094 lsls r4, r2, #2 + 8006f22: ea44 7491 orr.w r4, r4, r1, lsr #30 + 8006f26: 008b lsls r3, r1, #2 + 8006f28: 461a mov r2, r3 + 8006f2a: 4623 mov r3, r4 + 8006f2c: 4628 mov r0, r5 + 8006f2e: 4631 mov r1, r6 + 8006f30: f7f9 feb2 bl 8000c98 <__aeabi_uldivmod> + 8006f34: 4603 mov r3, r0 + 8006f36: 460c mov r4, r1 + 8006f38: 461a mov r2, r3 + 8006f3a: 4b50 ldr r3, [pc, #320] ; (800707c ) + 8006f3c: fba3 2302 umull r2, r3, r3, r2 + 8006f40: 095b lsrs r3, r3, #5 + 8006f42: ea4f 1803 mov.w r8, r3, lsl #4 + 8006f46: 68bb ldr r3, [r7, #8] + 8006f48: 469b mov fp, r3 + 8006f4a: f04f 0c00 mov.w ip, #0 + 8006f4e: 46d9 mov r9, fp + 8006f50: 46e2 mov sl, ip + 8006f52: eb19 0309 adds.w r3, r9, r9 + 8006f56: eb4a 040a adc.w r4, sl, sl + 8006f5a: 4699 mov r9, r3 + 8006f5c: 46a2 mov sl, r4 + 8006f5e: eb19 090b adds.w r9, r9, fp + 8006f62: eb4a 0a0c adc.w sl, sl, ip + 8006f66: f04f 0100 mov.w r1, #0 + 8006f6a: f04f 0200 mov.w r2, #0 + 8006f6e: ea4f 02ca mov.w r2, sl, lsl #3 + 8006f72: ea42 7259 orr.w r2, r2, r9, lsr #29 + 8006f76: ea4f 01c9 mov.w r1, r9, lsl #3 + 8006f7a: 4689 mov r9, r1 + 8006f7c: 4692 mov sl, r2 + 8006f7e: eb1b 0509 adds.w r5, fp, r9 + 8006f82: eb4c 060a adc.w r6, ip, sl + 8006f86: 687b ldr r3, [r7, #4] + 8006f88: 685b ldr r3, [r3, #4] + 8006f8a: 4619 mov r1, r3 + 8006f8c: f04f 0200 mov.w r2, #0 + 8006f90: f04f 0300 mov.w r3, #0 + 8006f94: f04f 0400 mov.w r4, #0 + 8006f98: 0094 lsls r4, r2, #2 + 8006f9a: ea44 7491 orr.w r4, r4, r1, lsr #30 + 8006f9e: 008b lsls r3, r1, #2 + 8006fa0: 461a mov r2, r3 + 8006fa2: 4623 mov r3, r4 + 8006fa4: 4628 mov r0, r5 + 8006fa6: 4631 mov r1, r6 + 8006fa8: f7f9 fe76 bl 8000c98 <__aeabi_uldivmod> + 8006fac: 4603 mov r3, r0 + 8006fae: 460c mov r4, r1 + 8006fb0: 461a mov r2, r3 + 8006fb2: 4b32 ldr r3, [pc, #200] ; (800707c ) + 8006fb4: fba3 1302 umull r1, r3, r3, r2 + 8006fb8: 095b lsrs r3, r3, #5 + 8006fba: 2164 movs r1, #100 ; 0x64 + 8006fbc: fb01 f303 mul.w r3, r1, r3 + 8006fc0: 1ad3 subs r3, r2, r3 + 8006fc2: 011b lsls r3, r3, #4 + 8006fc4: 3332 adds r3, #50 ; 0x32 + 8006fc6: 4a2d ldr r2, [pc, #180] ; (800707c ) + 8006fc8: fba2 2303 umull r2, r3, r2, r3 + 8006fcc: 095b lsrs r3, r3, #5 + 8006fce: f003 03f0 and.w r3, r3, #240 ; 0xf0 + 8006fd2: 4498 add r8, r3 + 8006fd4: 68bb ldr r3, [r7, #8] + 8006fd6: 469b mov fp, r3 + 8006fd8: f04f 0c00 mov.w ip, #0 + 8006fdc: 46d9 mov r9, fp + 8006fde: 46e2 mov sl, ip + 8006fe0: eb19 0309 adds.w r3, r9, r9 + 8006fe4: eb4a 040a adc.w r4, sl, sl + 8006fe8: 4699 mov r9, r3 + 8006fea: 46a2 mov sl, r4 + 8006fec: eb19 090b adds.w r9, r9, fp + 8006ff0: eb4a 0a0c adc.w sl, sl, ip + 8006ff4: f04f 0100 mov.w r1, #0 + 8006ff8: f04f 0200 mov.w r2, #0 + 8006ffc: ea4f 02ca mov.w r2, sl, lsl #3 + 8007000: ea42 7259 orr.w r2, r2, r9, lsr #29 + 8007004: ea4f 01c9 mov.w r1, r9, lsl #3 + 8007008: 4689 mov r9, r1 + 800700a: 4692 mov sl, r2 + 800700c: eb1b 0509 adds.w r5, fp, r9 + 8007010: eb4c 060a adc.w r6, ip, sl + 8007014: 687b ldr r3, [r7, #4] + 8007016: 685b ldr r3, [r3, #4] + 8007018: 4619 mov r1, r3 + 800701a: f04f 0200 mov.w r2, #0 + 800701e: f04f 0300 mov.w r3, #0 + 8007022: f04f 0400 mov.w r4, #0 + 8007026: 0094 lsls r4, r2, #2 + 8007028: ea44 7491 orr.w r4, r4, r1, lsr #30 + 800702c: 008b lsls r3, r1, #2 + 800702e: 461a mov r2, r3 + 8007030: 4623 mov r3, r4 + 8007032: 4628 mov r0, r5 + 8007034: 4631 mov r1, r6 + 8007036: f7f9 fe2f bl 8000c98 <__aeabi_uldivmod> + 800703a: 4603 mov r3, r0 + 800703c: 460c mov r4, r1 + 800703e: 461a mov r2, r3 + 8007040: 4b0e ldr r3, [pc, #56] ; (800707c ) + 8007042: fba3 1302 umull r1, r3, r3, r2 + 8007046: 095b lsrs r3, r3, #5 + 8007048: 2164 movs r1, #100 ; 0x64 + 800704a: fb01 f303 mul.w r3, r1, r3 + 800704e: 1ad3 subs r3, r2, r3 + 8007050: 011b lsls r3, r3, #4 + 8007052: 3332 adds r3, #50 ; 0x32 + 8007054: 4a09 ldr r2, [pc, #36] ; (800707c ) + 8007056: fba2 2303 umull r2, r3, r2, r3 + 800705a: 095b lsrs r3, r3, #5 + 800705c: f003 020f and.w r2, r3, #15 + 8007060: 687b ldr r3, [r7, #4] + 8007062: 681b ldr r3, [r3, #0] + 8007064: 4442 add r2, r8 + 8007066: 609a str r2, [r3, #8] +} + 8007068: e7ff b.n 800706a + 800706a: bf00 nop + 800706c: 3714 adds r7, #20 + 800706e: 46bd mov sp, r7 + 8007070: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 8007074: 40011000 .word 0x40011000 + 8007078: 40011400 .word 0x40011400 + 800707c: 51eb851f .word 0x51eb851f + +08007080 : + * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains + * the configuration information for the specified USBx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) +{ + 8007080: b084 sub sp, #16 + 8007082: b580 push {r7, lr} + 8007084: b084 sub sp, #16 + 8007086: af00 add r7, sp, #0 + 8007088: 6078 str r0, [r7, #4] + 800708a: f107 001c add.w r0, r7, #28 + 800708e: e880 000e stmia.w r0, {r1, r2, r3} + HAL_StatusTypeDef ret; + + if (cfg.phy_itface == USB_OTG_ULPI_PHY) + 8007092: 6b3b ldr r3, [r7, #48] ; 0x30 + 8007094: 2b01 cmp r3, #1 + 8007096: d122 bne.n 80070de + { + USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); + 8007098: 687b ldr r3, [r7, #4] + 800709a: 6b9b ldr r3, [r3, #56] ; 0x38 + 800709c: f423 3280 bic.w r2, r3, #65536 ; 0x10000 + 80070a0: 687b ldr r3, [r7, #4] + 80070a2: 639a str r2, [r3, #56] ; 0x38 + + /* Init The ULPI Interface */ + USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL); + 80070a4: 687b ldr r3, [r7, #4] + 80070a6: 68db ldr r3, [r3, #12] + 80070a8: f423 0384 bic.w r3, r3, #4325376 ; 0x420000 + 80070ac: f023 0340 bic.w r3, r3, #64 ; 0x40 + 80070b0: 687a ldr r2, [r7, #4] + 80070b2: 60d3 str r3, [r2, #12] + + /* Select vbus source */ + USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI); + 80070b4: 687b ldr r3, [r7, #4] + 80070b6: 68db ldr r3, [r3, #12] + 80070b8: f423 1240 bic.w r2, r3, #3145728 ; 0x300000 + 80070bc: 687b ldr r3, [r7, #4] + 80070be: 60da str r2, [r3, #12] + if (cfg.use_external_vbus == 1U) + 80070c0: 6cfb ldr r3, [r7, #76] ; 0x4c + 80070c2: 2b01 cmp r3, #1 + 80070c4: d105 bne.n 80070d2 + { + USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD; + 80070c6: 687b ldr r3, [r7, #4] + 80070c8: 68db ldr r3, [r3, #12] + 80070ca: f443 1280 orr.w r2, r3, #1048576 ; 0x100000 + 80070ce: 687b ldr r3, [r7, #4] + 80070d0: 60da str r2, [r3, #12] + } + /* Reset after a PHY select */ + ret = USB_CoreReset(USBx); + 80070d2: 6878 ldr r0, [r7, #4] + 80070d4: f000 f94a bl 800736c + 80070d8: 4603 mov r3, r0 + 80070da: 73fb strb r3, [r7, #15] + 80070dc: e01a b.n 8007114 + } + else /* FS interface (embedded Phy) */ + { + /* Select FS Embedded PHY */ + USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; + 80070de: 687b ldr r3, [r7, #4] + 80070e0: 68db ldr r3, [r3, #12] + 80070e2: f043 0240 orr.w r2, r3, #64 ; 0x40 + 80070e6: 687b ldr r3, [r7, #4] + 80070e8: 60da str r2, [r3, #12] + + /* Reset after a PHY select */ + ret = USB_CoreReset(USBx); + 80070ea: 6878 ldr r0, [r7, #4] + 80070ec: f000 f93e bl 800736c + 80070f0: 4603 mov r3, r0 + 80070f2: 73fb strb r3, [r7, #15] + + if (cfg.battery_charging_enable == 0U) + 80070f4: 6c3b ldr r3, [r7, #64] ; 0x40 + 80070f6: 2b00 cmp r3, #0 + 80070f8: d106 bne.n 8007108 + { + /* Activate the USB Transceiver */ + USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; + 80070fa: 687b ldr r3, [r7, #4] + 80070fc: 6b9b ldr r3, [r3, #56] ; 0x38 + 80070fe: f443 3280 orr.w r2, r3, #65536 ; 0x10000 + 8007102: 687b ldr r3, [r7, #4] + 8007104: 639a str r2, [r3, #56] ; 0x38 + 8007106: e005 b.n 8007114 + } + else + { + /* Deactivate the USB Transceiver */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); + 8007108: 687b ldr r3, [r7, #4] + 800710a: 6b9b ldr r3, [r3, #56] ; 0x38 + 800710c: f423 3280 bic.w r2, r3, #65536 ; 0x10000 + 8007110: 687b ldr r3, [r7, #4] + 8007112: 639a str r2, [r3, #56] ; 0x38 + } + } + + if (cfg.dma_enable == 1U) + 8007114: 6abb ldr r3, [r7, #40] ; 0x28 + 8007116: 2b01 cmp r3, #1 + 8007118: d10b bne.n 8007132 + { + USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2; + 800711a: 687b ldr r3, [r7, #4] + 800711c: 689b ldr r3, [r3, #8] + 800711e: f043 0206 orr.w r2, r3, #6 + 8007122: 687b ldr r3, [r7, #4] + 8007124: 609a str r2, [r3, #8] + USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN; + 8007126: 687b ldr r3, [r7, #4] + 8007128: 689b ldr r3, [r3, #8] + 800712a: f043 0220 orr.w r2, r3, #32 + 800712e: 687b ldr r3, [r7, #4] + 8007130: 609a str r2, [r3, #8] + } + + return ret; + 8007132: 7bfb ldrb r3, [r7, #15] +} + 8007134: 4618 mov r0, r3 + 8007136: 3710 adds r7, #16 + 8007138: 46bd mov sp, r7 + 800713a: e8bd 4080 ldmia.w sp!, {r7, lr} + 800713e: b004 add sp, #16 + 8007140: 4770 bx lr + +08007142 : + * Enables the controller's Global Int in the AHB Config reg + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx) +{ + 8007142: b480 push {r7} + 8007144: b083 sub sp, #12 + 8007146: af00 add r7, sp, #0 + 8007148: 6078 str r0, [r7, #4] + USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT; + 800714a: 687b ldr r3, [r7, #4] + 800714c: 689b ldr r3, [r3, #8] + 800714e: f043 0201 orr.w r2, r3, #1 + 8007152: 687b ldr r3, [r7, #4] + 8007154: 609a str r2, [r3, #8] + return HAL_OK; + 8007156: 2300 movs r3, #0 +} + 8007158: 4618 mov r0, r3 + 800715a: 370c adds r7, #12 + 800715c: 46bd mov sp, r7 + 800715e: f85d 7b04 ldr.w r7, [sp], #4 + 8007162: 4770 bx lr + +08007164 : + * Disable the controller's Global Int in the AHB Config reg + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) +{ + 8007164: b480 push {r7} + 8007166: b083 sub sp, #12 + 8007168: af00 add r7, sp, #0 + 800716a: 6078 str r0, [r7, #4] + USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; + 800716c: 687b ldr r3, [r7, #4] + 800716e: 689b ldr r3, [r3, #8] + 8007170: f023 0201 bic.w r2, r3, #1 + 8007174: 687b ldr r3, [r7, #4] + 8007176: 609a str r2, [r3, #8] + return HAL_OK; + 8007178: 2300 movs r3, #0 +} + 800717a: 4618 mov r0, r3 + 800717c: 370c adds r7, #12 + 800717e: 46bd mov sp, r7 + 8007180: f85d 7b04 ldr.w r7, [sp], #4 + 8007184: 4770 bx lr + +08007186 : + * @arg USB_DEVICE_MODE Peripheral mode + * @arg USB_HOST_MODE Host mode + * @retval HAL status + */ +HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode) +{ + 8007186: b580 push {r7, lr} + 8007188: b082 sub sp, #8 + 800718a: af00 add r7, sp, #0 + 800718c: 6078 str r0, [r7, #4] + 800718e: 460b mov r3, r1 + 8007190: 70fb strb r3, [r7, #3] + USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); + 8007192: 687b ldr r3, [r7, #4] + 8007194: 68db ldr r3, [r3, #12] + 8007196: f023 42c0 bic.w r2, r3, #1610612736 ; 0x60000000 + 800719a: 687b ldr r3, [r7, #4] + 800719c: 60da str r2, [r3, #12] + + if (mode == USB_HOST_MODE) + 800719e: 78fb ldrb r3, [r7, #3] + 80071a0: 2b01 cmp r3, #1 + 80071a2: d106 bne.n 80071b2 + { + USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; + 80071a4: 687b ldr r3, [r7, #4] + 80071a6: 68db ldr r3, [r3, #12] + 80071a8: f043 5200 orr.w r2, r3, #536870912 ; 0x20000000 + 80071ac: 687b ldr r3, [r7, #4] + 80071ae: 60da str r2, [r3, #12] + 80071b0: e00b b.n 80071ca + } + else if (mode == USB_DEVICE_MODE) + 80071b2: 78fb ldrb r3, [r7, #3] + 80071b4: 2b00 cmp r3, #0 + 80071b6: d106 bne.n 80071c6 + { + USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; + 80071b8: 687b ldr r3, [r7, #4] + 80071ba: 68db ldr r3, [r3, #12] + 80071bc: f043 4280 orr.w r2, r3, #1073741824 ; 0x40000000 + 80071c0: 687b ldr r3, [r7, #4] + 80071c2: 60da str r2, [r3, #12] + 80071c4: e001 b.n 80071ca + } + else + { + return HAL_ERROR; + 80071c6: 2301 movs r3, #1 + 80071c8: e003 b.n 80071d2 + } + HAL_Delay(50U); + 80071ca: 2032 movs r0, #50 ; 0x32 + 80071cc: f7fb f8b2 bl 8002334 + + return HAL_OK; + 80071d0: 2300 movs r3, #0 +} + 80071d2: 4618 mov r0, r3 + 80071d4: 3708 adds r7, #8 + 80071d6: 46bd mov sp, r7 + 80071d8: bd80 pop {r7, pc} + ... + +080071dc : + * This parameter can be a value from 1 to 15 + 15 means Flush all Tx FIFOs + * @retval HAL status + */ +HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) +{ + 80071dc: b480 push {r7} + 80071de: b085 sub sp, #20 + 80071e0: af00 add r7, sp, #0 + 80071e2: 6078 str r0, [r7, #4] + 80071e4: 6039 str r1, [r7, #0] + uint32_t count = 0U; + 80071e6: 2300 movs r3, #0 + 80071e8: 60fb str r3, [r7, #12] + + USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6)); + 80071ea: 683b ldr r3, [r7, #0] + 80071ec: 019b lsls r3, r3, #6 + 80071ee: f043 0220 orr.w r2, r3, #32 + 80071f2: 687b ldr r3, [r7, #4] + 80071f4: 611a str r2, [r3, #16] + + do + { + if (++count > 200000U) + 80071f6: 68fb ldr r3, [r7, #12] + 80071f8: 3301 adds r3, #1 + 80071fa: 60fb str r3, [r7, #12] + 80071fc: 68fb ldr r3, [r7, #12] + 80071fe: 4a09 ldr r2, [pc, #36] ; (8007224 ) + 8007200: 4293 cmp r3, r2 + 8007202: d901 bls.n 8007208 + { + return HAL_TIMEOUT; + 8007204: 2303 movs r3, #3 + 8007206: e006 b.n 8007216 + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH); + 8007208: 687b ldr r3, [r7, #4] + 800720a: 691b ldr r3, [r3, #16] + 800720c: f003 0320 and.w r3, r3, #32 + 8007210: 2b20 cmp r3, #32 + 8007212: d0f0 beq.n 80071f6 + + return HAL_OK; + 8007214: 2300 movs r3, #0 +} + 8007216: 4618 mov r0, r3 + 8007218: 3714 adds r7, #20 + 800721a: 46bd mov sp, r7 + 800721c: f85d 7b04 ldr.w r7, [sp], #4 + 8007220: 4770 bx lr + 8007222: bf00 nop + 8007224: 00030d40 .word 0x00030d40 + +08007228 : + * @brief USB_FlushRxFifo : Flush Rx FIFO + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) +{ + 8007228: b480 push {r7} + 800722a: b085 sub sp, #20 + 800722c: af00 add r7, sp, #0 + 800722e: 6078 str r0, [r7, #4] + uint32_t count = 0; + 8007230: 2300 movs r3, #0 + 8007232: 60fb str r3, [r7, #12] + + USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; + 8007234: 687b ldr r3, [r7, #4] + 8007236: 2210 movs r2, #16 + 8007238: 611a str r2, [r3, #16] + + do + { + if (++count > 200000U) + 800723a: 68fb ldr r3, [r7, #12] + 800723c: 3301 adds r3, #1 + 800723e: 60fb str r3, [r7, #12] + 8007240: 68fb ldr r3, [r7, #12] + 8007242: 4a09 ldr r2, [pc, #36] ; (8007268 ) + 8007244: 4293 cmp r3, r2 + 8007246: d901 bls.n 800724c + { + return HAL_TIMEOUT; + 8007248: 2303 movs r3, #3 + 800724a: e006 b.n 800725a + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH); + 800724c: 687b ldr r3, [r7, #4] + 800724e: 691b ldr r3, [r3, #16] + 8007250: f003 0310 and.w r3, r3, #16 + 8007254: 2b10 cmp r3, #16 + 8007256: d0f0 beq.n 800723a + + return HAL_OK; + 8007258: 2300 movs r3, #0 +} + 800725a: 4618 mov r0, r3 + 800725c: 3714 adds r7, #20 + 800725e: 46bd mov sp, r7 + 8007260: f85d 7b04 ldr.w r7, [sp], #4 + 8007264: 4770 bx lr + 8007266: bf00 nop + 8007268: 00030d40 .word 0x00030d40 + +0800726c : + * 1 : DMA feature used + * @retval HAL status + */ +HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, + uint8_t ch_ep_num, uint16_t len, uint8_t dma) +{ + 800726c: b480 push {r7} + 800726e: b089 sub sp, #36 ; 0x24 + 8007270: af00 add r7, sp, #0 + 8007272: 60f8 str r0, [r7, #12] + 8007274: 60b9 str r1, [r7, #8] + 8007276: 4611 mov r1, r2 + 8007278: 461a mov r2, r3 + 800727a: 460b mov r3, r1 + 800727c: 71fb strb r3, [r7, #7] + 800727e: 4613 mov r3, r2 + 8007280: 80bb strh r3, [r7, #4] + uint32_t USBx_BASE = (uint32_t)USBx; + 8007282: 68fb ldr r3, [r7, #12] + 8007284: 617b str r3, [r7, #20] + uint32_t *pSrc = (uint32_t *)src; + 8007286: 68bb ldr r3, [r7, #8] + 8007288: 61fb str r3, [r7, #28] + uint32_t count32b, i; + + if (dma == 0U) + 800728a: f897 3028 ldrb.w r3, [r7, #40] ; 0x28 + 800728e: 2b00 cmp r3, #0 + 8007290: d11a bne.n 80072c8 + { + count32b = ((uint32_t)len + 3U) / 4U; + 8007292: 88bb ldrh r3, [r7, #4] + 8007294: 3303 adds r3, #3 + 8007296: 089b lsrs r3, r3, #2 + 8007298: 613b str r3, [r7, #16] + for (i = 0U; i < count32b; i++) + 800729a: 2300 movs r3, #0 + 800729c: 61bb str r3, [r7, #24] + 800729e: e00f b.n 80072c0 + { + USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc); + 80072a0: 79fb ldrb r3, [r7, #7] + 80072a2: 031a lsls r2, r3, #12 + 80072a4: 697b ldr r3, [r7, #20] + 80072a6: 4413 add r3, r2 + 80072a8: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 80072ac: 461a mov r2, r3 + 80072ae: 69fb ldr r3, [r7, #28] + 80072b0: 681b ldr r3, [r3, #0] + 80072b2: 6013 str r3, [r2, #0] + pSrc++; + 80072b4: 69fb ldr r3, [r7, #28] + 80072b6: 3304 adds r3, #4 + 80072b8: 61fb str r3, [r7, #28] + for (i = 0U; i < count32b; i++) + 80072ba: 69bb ldr r3, [r7, #24] + 80072bc: 3301 adds r3, #1 + 80072be: 61bb str r3, [r7, #24] + 80072c0: 69ba ldr r2, [r7, #24] + 80072c2: 693b ldr r3, [r7, #16] + 80072c4: 429a cmp r2, r3 + 80072c6: d3eb bcc.n 80072a0 + } + } + + return HAL_OK; + 80072c8: 2300 movs r3, #0 +} + 80072ca: 4618 mov r0, r3 + 80072cc: 3724 adds r7, #36 ; 0x24 + 80072ce: 46bd mov sp, r7 + 80072d0: f85d 7b04 ldr.w r7, [sp], #4 + 80072d4: 4770 bx lr + +080072d6 : + * @param dest source pointer + * @param len Number of bytes to read + * @retval pointer to destination buffer + */ +void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) +{ + 80072d6: b480 push {r7} + 80072d8: b089 sub sp, #36 ; 0x24 + 80072da: af00 add r7, sp, #0 + 80072dc: 60f8 str r0, [r7, #12] + 80072de: 60b9 str r1, [r7, #8] + 80072e0: 4613 mov r3, r2 + 80072e2: 80fb strh r3, [r7, #6] + uint32_t USBx_BASE = (uint32_t)USBx; + 80072e4: 68fb ldr r3, [r7, #12] + 80072e6: 617b str r3, [r7, #20] + uint32_t *pDest = (uint32_t *)dest; + 80072e8: 68bb ldr r3, [r7, #8] + 80072ea: 61fb str r3, [r7, #28] + uint32_t i; + uint32_t count32b = ((uint32_t)len + 3U) / 4U; + 80072ec: 88fb ldrh r3, [r7, #6] + 80072ee: 3303 adds r3, #3 + 80072f0: 089b lsrs r3, r3, #2 + 80072f2: 613b str r3, [r7, #16] + + for (i = 0U; i < count32b; i++) + 80072f4: 2300 movs r3, #0 + 80072f6: 61bb str r3, [r7, #24] + 80072f8: e00b b.n 8007312 + { + __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U)); + 80072fa: 697b ldr r3, [r7, #20] + 80072fc: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 8007300: 681a ldr r2, [r3, #0] + 8007302: 69fb ldr r3, [r7, #28] + 8007304: 601a str r2, [r3, #0] + pDest++; + 8007306: 69fb ldr r3, [r7, #28] + 8007308: 3304 adds r3, #4 + 800730a: 61fb str r3, [r7, #28] + for (i = 0U; i < count32b; i++) + 800730c: 69bb ldr r3, [r7, #24] + 800730e: 3301 adds r3, #1 + 8007310: 61bb str r3, [r7, #24] + 8007312: 69ba ldr r2, [r7, #24] + 8007314: 693b ldr r3, [r7, #16] + 8007316: 429a cmp r2, r3 + 8007318: d3ef bcc.n 80072fa + } + + return ((void *)pDest); + 800731a: 69fb ldr r3, [r7, #28] +} + 800731c: 4618 mov r0, r3 + 800731e: 3724 adds r7, #36 ; 0x24 + 8007320: 46bd mov sp, r7 + 8007322: f85d 7b04 ldr.w r7, [sp], #4 + 8007326: 4770 bx lr + +08007328 : + * @brief USB_ReadInterrupts: return the global USB interrupt status + * @param USBx Selected device + * @retval HAL status + */ +uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx) +{ + 8007328: b480 push {r7} + 800732a: b085 sub sp, #20 + 800732c: af00 add r7, sp, #0 + 800732e: 6078 str r0, [r7, #4] + uint32_t tmpreg; + + tmpreg = USBx->GINTSTS; + 8007330: 687b ldr r3, [r7, #4] + 8007332: 695b ldr r3, [r3, #20] + 8007334: 60fb str r3, [r7, #12] + tmpreg &= USBx->GINTMSK; + 8007336: 687b ldr r3, [r7, #4] + 8007338: 699b ldr r3, [r3, #24] + 800733a: 68fa ldr r2, [r7, #12] + 800733c: 4013 ands r3, r2 + 800733e: 60fb str r3, [r7, #12] + + return tmpreg; + 8007340: 68fb ldr r3, [r7, #12] +} + 8007342: 4618 mov r0, r3 + 8007344: 3714 adds r7, #20 + 8007346: 46bd mov sp, r7 + 8007348: f85d 7b04 ldr.w r7, [sp], #4 + 800734c: 4770 bx lr + +0800734e : + * This parameter can be one of these values: + * 0 : Host + * 1 : Device + */ +uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx) +{ + 800734e: b480 push {r7} + 8007350: b083 sub sp, #12 + 8007352: af00 add r7, sp, #0 + 8007354: 6078 str r0, [r7, #4] + return ((USBx->GINTSTS) & 0x1U); + 8007356: 687b ldr r3, [r7, #4] + 8007358: 695b ldr r3, [r3, #20] + 800735a: f003 0301 and.w r3, r3, #1 +} + 800735e: 4618 mov r0, r3 + 8007360: 370c adds r7, #12 + 8007362: 46bd mov sp, r7 + 8007364: f85d 7b04 ldr.w r7, [sp], #4 + 8007368: 4770 bx lr + ... + +0800736c : + * @brief Reset the USB Core (needed after USB clock settings change) + * @param USBx Selected device + * @retval HAL status + */ +static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) +{ + 800736c: b480 push {r7} + 800736e: b085 sub sp, #20 + 8007370: af00 add r7, sp, #0 + 8007372: 6078 str r0, [r7, #4] + uint32_t count = 0U; + 8007374: 2300 movs r3, #0 + 8007376: 60fb str r3, [r7, #12] + + /* Wait for AHB master IDLE state. */ + do + { + if (++count > 200000U) + 8007378: 68fb ldr r3, [r7, #12] + 800737a: 3301 adds r3, #1 + 800737c: 60fb str r3, [r7, #12] + 800737e: 68fb ldr r3, [r7, #12] + 8007380: 4a13 ldr r2, [pc, #76] ; (80073d0 ) + 8007382: 4293 cmp r3, r2 + 8007384: d901 bls.n 800738a + { + return HAL_TIMEOUT; + 8007386: 2303 movs r3, #3 + 8007388: e01b b.n 80073c2 + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); + 800738a: 687b ldr r3, [r7, #4] + 800738c: 691b ldr r3, [r3, #16] + 800738e: 2b00 cmp r3, #0 + 8007390: daf2 bge.n 8007378 + + /* Core Soft Reset */ + count = 0U; + 8007392: 2300 movs r3, #0 + 8007394: 60fb str r3, [r7, #12] + USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; + 8007396: 687b ldr r3, [r7, #4] + 8007398: 691b ldr r3, [r3, #16] + 800739a: f043 0201 orr.w r2, r3, #1 + 800739e: 687b ldr r3, [r7, #4] + 80073a0: 611a str r2, [r3, #16] + + do + { + if (++count > 200000U) + 80073a2: 68fb ldr r3, [r7, #12] + 80073a4: 3301 adds r3, #1 + 80073a6: 60fb str r3, [r7, #12] + 80073a8: 68fb ldr r3, [r7, #12] + 80073aa: 4a09 ldr r2, [pc, #36] ; (80073d0 ) + 80073ac: 4293 cmp r3, r2 + 80073ae: d901 bls.n 80073b4 + { + return HAL_TIMEOUT; + 80073b0: 2303 movs r3, #3 + 80073b2: e006 b.n 80073c2 + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST); + 80073b4: 687b ldr r3, [r7, #4] + 80073b6: 691b ldr r3, [r3, #16] + 80073b8: f003 0301 and.w r3, r3, #1 + 80073bc: 2b01 cmp r3, #1 + 80073be: d0f0 beq.n 80073a2 + + return HAL_OK; + 80073c0: 2300 movs r3, #0 +} + 80073c2: 4618 mov r0, r3 + 80073c4: 3714 adds r7, #20 + 80073c6: 46bd mov sp, r7 + 80073c8: f85d 7b04 ldr.w r7, [sp], #4 + 80073cc: 4770 bx lr + 80073ce: bf00 nop + 80073d0: 00030d40 .word 0x00030d40 + +080073d4 : + * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains + * the configuration information for the specified USBx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) +{ + 80073d4: b084 sub sp, #16 + 80073d6: b580 push {r7, lr} + 80073d8: b084 sub sp, #16 + 80073da: af00 add r7, sp, #0 + 80073dc: 6078 str r0, [r7, #4] + 80073de: f107 001c add.w r0, r7, #28 + 80073e2: e880 000e stmia.w r0, {r1, r2, r3} + uint32_t USBx_BASE = (uint32_t)USBx; + 80073e6: 687b ldr r3, [r7, #4] + 80073e8: 60bb str r3, [r7, #8] + uint32_t i; + + /* Restart the Phy Clock */ + USBx_PCGCCTL = 0U; + 80073ea: 68bb ldr r3, [r7, #8] + 80073ec: f503 6360 add.w r3, r3, #3584 ; 0xe00 + 80073f0: 461a mov r2, r3 + 80073f2: 2300 movs r3, #0 + 80073f4: 6013 str r3, [r2, #0] +#else + /* + * Disable HW VBUS sensing. VBUS is internally considered to be always + * at VBUS-Valid level (5V). + */ + USBx->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS; + 80073f6: 687b ldr r3, [r7, #4] + 80073f8: 6b9b ldr r3, [r3, #56] ; 0x38 + 80073fa: f443 1200 orr.w r2, r3, #2097152 ; 0x200000 + 80073fe: 687b ldr r3, [r7, #4] + 8007400: 639a str r2, [r3, #56] ; 0x38 + USBx->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN; + 8007402: 687b ldr r3, [r7, #4] + 8007404: 6b9b ldr r3, [r3, #56] ; 0x38 + 8007406: f423 2200 bic.w r2, r3, #524288 ; 0x80000 + 800740a: 687b ldr r3, [r7, #4] + 800740c: 639a str r2, [r3, #56] ; 0x38 + USBx->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN; + 800740e: 687b ldr r3, [r7, #4] + 8007410: 6b9b ldr r3, [r3, #56] ; 0x38 + 8007412: f423 2280 bic.w r2, r3, #262144 ; 0x40000 + 8007416: 687b ldr r3, [r7, #4] + 8007418: 639a str r2, [r3, #56] ; 0x38 +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) + /* Disable Battery chargin detector */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN); +#endif /* defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ + + if ((USBx->CID & (0x1U << 8)) != 0U) + 800741a: 687b ldr r3, [r7, #4] + 800741c: 6bdb ldr r3, [r3, #60] ; 0x3c + 800741e: f403 7380 and.w r3, r3, #256 ; 0x100 + 8007422: 2b00 cmp r3, #0 + 8007424: d018 beq.n 8007458 + { + if (cfg.speed == USBH_FSLS_SPEED) + 8007426: 6a7b ldr r3, [r7, #36] ; 0x24 + 8007428: 2b01 cmp r3, #1 + 800742a: d10a bne.n 8007442 + { + /* Force Device Enumeration to FS/LS mode only */ + USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS; + 800742c: 68bb ldr r3, [r7, #8] + 800742e: f503 6380 add.w r3, r3, #1024 ; 0x400 + 8007432: 681b ldr r3, [r3, #0] + 8007434: 68ba ldr r2, [r7, #8] + 8007436: f502 6280 add.w r2, r2, #1024 ; 0x400 + 800743a: f043 0304 orr.w r3, r3, #4 + 800743e: 6013 str r3, [r2, #0] + 8007440: e014 b.n 800746c + } + else + { + /* Set default Max speed support */ + USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS); + 8007442: 68bb ldr r3, [r7, #8] + 8007444: f503 6380 add.w r3, r3, #1024 ; 0x400 + 8007448: 681b ldr r3, [r3, #0] + 800744a: 68ba ldr r2, [r7, #8] + 800744c: f502 6280 add.w r2, r2, #1024 ; 0x400 + 8007450: f023 0304 bic.w r3, r3, #4 + 8007454: 6013 str r3, [r2, #0] + 8007456: e009 b.n 800746c + } + } + else + { + /* Set default Max speed support */ + USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS); + 8007458: 68bb ldr r3, [r7, #8] + 800745a: f503 6380 add.w r3, r3, #1024 ; 0x400 + 800745e: 681b ldr r3, [r3, #0] + 8007460: 68ba ldr r2, [r7, #8] + 8007462: f502 6280 add.w r2, r2, #1024 ; 0x400 + 8007466: f023 0304 bic.w r3, r3, #4 + 800746a: 6013 str r3, [r2, #0] + } + + /* Make sure the FIFOs are flushed. */ + (void)USB_FlushTxFifo(USBx, 0x10U); /* all Tx FIFOs */ + 800746c: 2110 movs r1, #16 + 800746e: 6878 ldr r0, [r7, #4] + 8007470: f7ff feb4 bl 80071dc + (void)USB_FlushRxFifo(USBx); + 8007474: 6878 ldr r0, [r7, #4] + 8007476: f7ff fed7 bl 8007228 + + /* Clear all pending HC Interrupts */ + for (i = 0U; i < cfg.Host_channels; i++) + 800747a: 2300 movs r3, #0 + 800747c: 60fb str r3, [r7, #12] + 800747e: e015 b.n 80074ac + { + USBx_HC(i)->HCINT = 0xFFFFFFFFU; + 8007480: 68fb ldr r3, [r7, #12] + 8007482: 015a lsls r2, r3, #5 + 8007484: 68bb ldr r3, [r7, #8] + 8007486: 4413 add r3, r2 + 8007488: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 800748c: 461a mov r2, r3 + 800748e: f04f 33ff mov.w r3, #4294967295 + 8007492: 6093 str r3, [r2, #8] + USBx_HC(i)->HCINTMSK = 0U; + 8007494: 68fb ldr r3, [r7, #12] + 8007496: 015a lsls r2, r3, #5 + 8007498: 68bb ldr r3, [r7, #8] + 800749a: 4413 add r3, r2 + 800749c: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 80074a0: 461a mov r2, r3 + 80074a2: 2300 movs r3, #0 + 80074a4: 60d3 str r3, [r2, #12] + for (i = 0U; i < cfg.Host_channels; i++) + 80074a6: 68fb ldr r3, [r7, #12] + 80074a8: 3301 adds r3, #1 + 80074aa: 60fb str r3, [r7, #12] + 80074ac: 6a3b ldr r3, [r7, #32] + 80074ae: 68fa ldr r2, [r7, #12] + 80074b0: 429a cmp r2, r3 + 80074b2: d3e5 bcc.n 8007480 + } + + /* Enable VBUS driving */ + (void)USB_DriveVbus(USBx, 1U); + 80074b4: 2101 movs r1, #1 + 80074b6: 6878 ldr r0, [r7, #4] + 80074b8: f000 f8ac bl 8007614 + + HAL_Delay(200U); + 80074bc: 20c8 movs r0, #200 ; 0xc8 + 80074be: f7fa ff39 bl 8002334 + + /* Disable all interrupts. */ + USBx->GINTMSK = 0U; + 80074c2: 687b ldr r3, [r7, #4] + 80074c4: 2200 movs r2, #0 + 80074c6: 619a str r2, [r3, #24] + + /* Clear any pending interrupts */ + USBx->GINTSTS = 0xFFFFFFFFU; + 80074c8: 687b ldr r3, [r7, #4] + 80074ca: f04f 32ff mov.w r2, #4294967295 + 80074ce: 615a str r2, [r3, #20] + + if ((USBx->CID & (0x1U << 8)) != 0U) + 80074d0: 687b ldr r3, [r7, #4] + 80074d2: 6bdb ldr r3, [r3, #60] ; 0x3c + 80074d4: f403 7380 and.w r3, r3, #256 ; 0x100 + 80074d8: 2b00 cmp r3, #0 + 80074da: d00b beq.n 80074f4 + { + /* set Rx FIFO size */ + USBx->GRXFSIZ = 0x200U; + 80074dc: 687b ldr r3, [r7, #4] + 80074de: f44f 7200 mov.w r2, #512 ; 0x200 + 80074e2: 625a str r2, [r3, #36] ; 0x24 + USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x100U << 16) & USB_OTG_NPTXFD) | 0x200U); + 80074e4: 687b ldr r3, [r7, #4] + 80074e6: 4a14 ldr r2, [pc, #80] ; (8007538 ) + 80074e8: 629a str r2, [r3, #40] ; 0x28 + USBx->HPTXFSIZ = (uint32_t)(((0xE0U << 16) & USB_OTG_HPTXFSIZ_PTXFD) | 0x300U); + 80074ea: 687b ldr r3, [r7, #4] + 80074ec: 4a13 ldr r2, [pc, #76] ; (800753c ) + 80074ee: f8c3 2100 str.w r2, [r3, #256] ; 0x100 + 80074f2: e009 b.n 8007508 + } + else + { + /* set Rx FIFO size */ + USBx->GRXFSIZ = 0x80U; + 80074f4: 687b ldr r3, [r7, #4] + 80074f6: 2280 movs r2, #128 ; 0x80 + 80074f8: 625a str r2, [r3, #36] ; 0x24 + USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x60U << 16) & USB_OTG_NPTXFD) | 0x80U); + 80074fa: 687b ldr r3, [r7, #4] + 80074fc: 4a10 ldr r2, [pc, #64] ; (8007540 ) + 80074fe: 629a str r2, [r3, #40] ; 0x28 + USBx->HPTXFSIZ = (uint32_t)(((0x40U << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0U); + 8007500: 687b ldr r3, [r7, #4] + 8007502: 4a10 ldr r2, [pc, #64] ; (8007544 ) + 8007504: f8c3 2100 str.w r2, [r3, #256] ; 0x100 + } + + /* Enable the common interrupts */ + if (cfg.dma_enable == 0U) + 8007508: 6abb ldr r3, [r7, #40] ; 0x28 + 800750a: 2b00 cmp r3, #0 + 800750c: d105 bne.n 800751a + { + USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; + 800750e: 687b ldr r3, [r7, #4] + 8007510: 699b ldr r3, [r3, #24] + 8007512: f043 0210 orr.w r2, r3, #16 + 8007516: 687b ldr r3, [r7, #4] + 8007518: 619a str r2, [r3, #24] + } + + /* Enable interrupts matching to the Host mode ONLY */ + USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM | \ + 800751a: 687b ldr r3, [r7, #4] + 800751c: 699a ldr r2, [r3, #24] + 800751e: 4b0a ldr r3, [pc, #40] ; (8007548 ) + 8007520: 4313 orrs r3, r2 + 8007522: 687a ldr r2, [r7, #4] + 8007524: 6193 str r3, [r2, #24] + USB_OTG_GINTMSK_SOFM | USB_OTG_GINTSTS_DISCINT | \ + USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM); + + return HAL_OK; + 8007526: 2300 movs r3, #0 +} + 8007528: 4618 mov r0, r3 + 800752a: 3710 adds r7, #16 + 800752c: 46bd mov sp, r7 + 800752e: e8bd 4080 ldmia.w sp!, {r7, lr} + 8007532: b004 add sp, #16 + 8007534: 4770 bx lr + 8007536: bf00 nop + 8007538: 01000200 .word 0x01000200 + 800753c: 00e00300 .word 0x00e00300 + 8007540: 00600080 .word 0x00600080 + 8007544: 004000e0 .word 0x004000e0 + 8007548: a3200008 .word 0xa3200008 + +0800754c : + * HCFG_48_MHZ : Full Speed 48 MHz Clock + * HCFG_6_MHZ : Low Speed 6 MHz Clock + * @retval HAL status + */ +HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq) +{ + 800754c: b480 push {r7} + 800754e: b085 sub sp, #20 + 8007550: af00 add r7, sp, #0 + 8007552: 6078 str r0, [r7, #4] + 8007554: 460b mov r3, r1 + 8007556: 70fb strb r3, [r7, #3] + uint32_t USBx_BASE = (uint32_t)USBx; + 8007558: 687b ldr r3, [r7, #4] + 800755a: 60fb str r3, [r7, #12] + + USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS); + 800755c: 68fb ldr r3, [r7, #12] + 800755e: f503 6380 add.w r3, r3, #1024 ; 0x400 + 8007562: 681b ldr r3, [r3, #0] + 8007564: 68fa ldr r2, [r7, #12] + 8007566: f502 6280 add.w r2, r2, #1024 ; 0x400 + 800756a: f023 0303 bic.w r3, r3, #3 + 800756e: 6013 str r3, [r2, #0] + USBx_HOST->HCFG |= (uint32_t)freq & USB_OTG_HCFG_FSLSPCS; + 8007570: 68fb ldr r3, [r7, #12] + 8007572: f503 6380 add.w r3, r3, #1024 ; 0x400 + 8007576: 681a ldr r2, [r3, #0] + 8007578: 78fb ldrb r3, [r7, #3] + 800757a: f003 0303 and.w r3, r3, #3 + 800757e: 68f9 ldr r1, [r7, #12] + 8007580: f501 6180 add.w r1, r1, #1024 ; 0x400 + 8007584: 4313 orrs r3, r2 + 8007586: 600b str r3, [r1, #0] + + if (freq == HCFG_48_MHZ) + 8007588: 78fb ldrb r3, [r7, #3] + 800758a: 2b01 cmp r3, #1 + 800758c: d107 bne.n 800759e + { + USBx_HOST->HFIR = 48000U; + 800758e: 68fb ldr r3, [r7, #12] + 8007590: f503 6380 add.w r3, r3, #1024 ; 0x400 + 8007594: 461a mov r2, r3 + 8007596: f64b 3380 movw r3, #48000 ; 0xbb80 + 800759a: 6053 str r3, [r2, #4] + 800759c: e009 b.n 80075b2 + } + else if (freq == HCFG_6_MHZ) + 800759e: 78fb ldrb r3, [r7, #3] + 80075a0: 2b02 cmp r3, #2 + 80075a2: d106 bne.n 80075b2 + { + USBx_HOST->HFIR = 6000U; + 80075a4: 68fb ldr r3, [r7, #12] + 80075a6: f503 6380 add.w r3, r3, #1024 ; 0x400 + 80075aa: 461a mov r2, r3 + 80075ac: f241 7370 movw r3, #6000 ; 0x1770 + 80075b0: 6053 str r3, [r2, #4] + else + { + /* ... */ + } + + return HAL_OK; + 80075b2: 2300 movs r3, #0 +} + 80075b4: 4618 mov r0, r3 + 80075b6: 3714 adds r7, #20 + 80075b8: 46bd mov sp, r7 + 80075ba: f85d 7b04 ldr.w r7, [sp], #4 + 80075be: 4770 bx lr + +080075c0 : + * @retval HAL status + * @note (1)The application must wait at least 10 ms + * before clearing the reset bit. + */ +HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx) +{ + 80075c0: b580 push {r7, lr} + 80075c2: b084 sub sp, #16 + 80075c4: af00 add r7, sp, #0 + 80075c6: 6078 str r0, [r7, #4] + uint32_t USBx_BASE = (uint32_t)USBx; + 80075c8: 687b ldr r3, [r7, #4] + 80075ca: 60fb str r3, [r7, #12] + + __IO uint32_t hprt0 = 0U; + 80075cc: 2300 movs r3, #0 + 80075ce: 60bb str r3, [r7, #8] + + hprt0 = USBx_HPRT0; + 80075d0: 68fb ldr r3, [r7, #12] + 80075d2: f503 6388 add.w r3, r3, #1088 ; 0x440 + 80075d6: 681b ldr r3, [r3, #0] + 80075d8: 60bb str r3, [r7, #8] + + hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | + 80075da: 68bb ldr r3, [r7, #8] + 80075dc: f023 032e bic.w r3, r3, #46 ; 0x2e + 80075e0: 60bb str r3, [r7, #8] + USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); + + USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0); + 80075e2: 68bb ldr r3, [r7, #8] + 80075e4: 68fa ldr r2, [r7, #12] + 80075e6: f502 6288 add.w r2, r2, #1088 ; 0x440 + 80075ea: f443 7380 orr.w r3, r3, #256 ; 0x100 + 80075ee: 6013 str r3, [r2, #0] + HAL_Delay(100U); /* See Note #1 */ + 80075f0: 2064 movs r0, #100 ; 0x64 + 80075f2: f7fa fe9f bl 8002334 + USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0); + 80075f6: 68bb ldr r3, [r7, #8] + 80075f8: 68fa ldr r2, [r7, #12] + 80075fa: f502 6288 add.w r2, r2, #1088 ; 0x440 + 80075fe: f423 7380 bic.w r3, r3, #256 ; 0x100 + 8007602: 6013 str r3, [r2, #0] + HAL_Delay(10U); + 8007604: 200a movs r0, #10 + 8007606: f7fa fe95 bl 8002334 + + return HAL_OK; + 800760a: 2300 movs r3, #0 +} + 800760c: 4618 mov r0, r3 + 800760e: 3710 adds r7, #16 + 8007610: 46bd mov sp, r7 + 8007612: bd80 pop {r7, pc} + +08007614 : + * 0 : Deactivate VBUS + * 1 : Activate VBUS + * @retval HAL status + */ +HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state) +{ + 8007614: b480 push {r7} + 8007616: b085 sub sp, #20 + 8007618: af00 add r7, sp, #0 + 800761a: 6078 str r0, [r7, #4] + 800761c: 460b mov r3, r1 + 800761e: 70fb strb r3, [r7, #3] + uint32_t USBx_BASE = (uint32_t)USBx; + 8007620: 687b ldr r3, [r7, #4] + 8007622: 60fb str r3, [r7, #12] + __IO uint32_t hprt0 = 0U; + 8007624: 2300 movs r3, #0 + 8007626: 60bb str r3, [r7, #8] + + hprt0 = USBx_HPRT0; + 8007628: 68fb ldr r3, [r7, #12] + 800762a: f503 6388 add.w r3, r3, #1088 ; 0x440 + 800762e: 681b ldr r3, [r3, #0] + 8007630: 60bb str r3, [r7, #8] + + hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | + 8007632: 68bb ldr r3, [r7, #8] + 8007634: f023 032e bic.w r3, r3, #46 ; 0x2e + 8007638: 60bb str r3, [r7, #8] + USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); + + if (((hprt0 & USB_OTG_HPRT_PPWR) == 0U) && (state == 1U)) + 800763a: 68bb ldr r3, [r7, #8] + 800763c: f403 5380 and.w r3, r3, #4096 ; 0x1000 + 8007640: 2b00 cmp r3, #0 + 8007642: d109 bne.n 8007658 + 8007644: 78fb ldrb r3, [r7, #3] + 8007646: 2b01 cmp r3, #1 + 8007648: d106 bne.n 8007658 + { + USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0); + 800764a: 68bb ldr r3, [r7, #8] + 800764c: 68fa ldr r2, [r7, #12] + 800764e: f502 6288 add.w r2, r2, #1088 ; 0x440 + 8007652: f443 5380 orr.w r3, r3, #4096 ; 0x1000 + 8007656: 6013 str r3, [r2, #0] + } + if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0U)) + 8007658: 68bb ldr r3, [r7, #8] + 800765a: f403 5380 and.w r3, r3, #4096 ; 0x1000 + 800765e: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 + 8007662: d109 bne.n 8007678 + 8007664: 78fb ldrb r3, [r7, #3] + 8007666: 2b00 cmp r3, #0 + 8007668: d106 bne.n 8007678 + { + USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0); + 800766a: 68bb ldr r3, [r7, #8] + 800766c: 68fa ldr r2, [r7, #12] + 800766e: f502 6288 add.w r2, r2, #1088 ; 0x440 + 8007672: f423 5380 bic.w r3, r3, #4096 ; 0x1000 + 8007676: 6013 str r3, [r2, #0] + } + return HAL_OK; + 8007678: 2300 movs r3, #0 +} + 800767a: 4618 mov r0, r3 + 800767c: 3714 adds r7, #20 + 800767e: 46bd mov sp, r7 + 8007680: f85d 7b04 ldr.w r7, [sp], #4 + 8007684: 4770 bx lr + +08007686 : + * @arg HCD_SPEED_HIGH: High speed mode + * @arg HCD_SPEED_FULL: Full speed mode + * @arg HCD_SPEED_LOW: Low speed mode + */ +uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx) +{ + 8007686: b480 push {r7} + 8007688: b085 sub sp, #20 + 800768a: af00 add r7, sp, #0 + 800768c: 6078 str r0, [r7, #4] + uint32_t USBx_BASE = (uint32_t)USBx; + 800768e: 687b ldr r3, [r7, #4] + 8007690: 60fb str r3, [r7, #12] + __IO uint32_t hprt0 = 0U; + 8007692: 2300 movs r3, #0 + 8007694: 60bb str r3, [r7, #8] + + hprt0 = USBx_HPRT0; + 8007696: 68fb ldr r3, [r7, #12] + 8007698: f503 6388 add.w r3, r3, #1088 ; 0x440 + 800769c: 681b ldr r3, [r3, #0] + 800769e: 60bb str r3, [r7, #8] + return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17); + 80076a0: 68bb ldr r3, [r7, #8] + 80076a2: 0c5b lsrs r3, r3, #17 + 80076a4: f003 0303 and.w r3, r3, #3 +} + 80076a8: 4618 mov r0, r3 + 80076aa: 3714 adds r7, #20 + 80076ac: 46bd mov sp, r7 + 80076ae: f85d 7b04 ldr.w r7, [sp], #4 + 80076b2: 4770 bx lr + +080076b4 : + * @brief Return Host Current Frame number + * @param USBx Selected device + * @retval current frame number + */ +uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx) +{ + 80076b4: b480 push {r7} + 80076b6: b085 sub sp, #20 + 80076b8: af00 add r7, sp, #0 + 80076ba: 6078 str r0, [r7, #4] + uint32_t USBx_BASE = (uint32_t)USBx; + 80076bc: 687b ldr r3, [r7, #4] + 80076be: 60fb str r3, [r7, #12] + + return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM); + 80076c0: 68fb ldr r3, [r7, #12] + 80076c2: f503 6380 add.w r3, r3, #1024 ; 0x400 + 80076c6: 689b ldr r3, [r3, #8] + 80076c8: b29b uxth r3, r3 +} + 80076ca: 4618 mov r0, r3 + 80076cc: 3714 adds r7, #20 + 80076ce: 46bd mov sp, r7 + 80076d0: f85d 7b04 ldr.w r7, [sp], #4 + 80076d4: 4770 bx lr + ... + +080076d8 : + * @retval HAL state + */ +HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, + uint8_t epnum, uint8_t dev_address, uint8_t speed, + uint8_t ep_type, uint16_t mps) +{ + 80076d8: b480 push {r7} + 80076da: b087 sub sp, #28 + 80076dc: af00 add r7, sp, #0 + 80076de: 6078 str r0, [r7, #4] + 80076e0: 4608 mov r0, r1 + 80076e2: 4611 mov r1, r2 + 80076e4: 461a mov r2, r3 + 80076e6: 4603 mov r3, r0 + 80076e8: 70fb strb r3, [r7, #3] + 80076ea: 460b mov r3, r1 + 80076ec: 70bb strb r3, [r7, #2] + 80076ee: 4613 mov r3, r2 + 80076f0: 707b strb r3, [r7, #1] + HAL_StatusTypeDef ret = HAL_OK; + 80076f2: 2300 movs r3, #0 + 80076f4: 75fb strb r3, [r7, #23] + uint32_t USBx_BASE = (uint32_t)USBx; + 80076f6: 687b ldr r3, [r7, #4] + 80076f8: 60bb str r3, [r7, #8] + uint32_t HCcharEpDir, HCcharLowSpeed; + + /* Clear old interrupt conditions for this host channel. */ + USBx_HC((uint32_t)ch_num)->HCINT = 0xFFFFFFFFU; + 80076fa: 78fb ldrb r3, [r7, #3] + 80076fc: 015a lsls r2, r3, #5 + 80076fe: 68bb ldr r3, [r7, #8] + 8007700: 4413 add r3, r2 + 8007702: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8007706: 461a mov r2, r3 + 8007708: f04f 33ff mov.w r3, #4294967295 + 800770c: 6093 str r3, [r2, #8] + + /* Enable channel interrupts required for this transfer. */ + switch (ep_type) + 800770e: f897 3024 ldrb.w r3, [r7, #36] ; 0x24 + 8007712: 2b03 cmp r3, #3 + 8007714: d87e bhi.n 8007814 + 8007716: a201 add r2, pc, #4 ; (adr r2, 800771c ) + 8007718: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 800771c: 0800772d .word 0x0800772d + 8007720: 080077d7 .word 0x080077d7 + 8007724: 0800772d .word 0x0800772d + 8007728: 08007799 .word 0x08007799 + { + case EP_TYPE_CTRL: + case EP_TYPE_BULK: + USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | + 800772c: 78fb ldrb r3, [r7, #3] + 800772e: 015a lsls r2, r3, #5 + 8007730: 68bb ldr r3, [r7, #8] + 8007732: 4413 add r3, r2 + 8007734: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8007738: 461a mov r2, r3 + 800773a: f240 439d movw r3, #1181 ; 0x49d + 800773e: 60d3 str r3, [r2, #12] + USB_OTG_HCINTMSK_TXERRM | + USB_OTG_HCINTMSK_DTERRM | + USB_OTG_HCINTMSK_AHBERR | + USB_OTG_HCINTMSK_NAKM; + + if ((epnum & 0x80U) == 0x80U) + 8007740: f997 3002 ldrsb.w r3, [r7, #2] + 8007744: 2b00 cmp r3, #0 + 8007746: da10 bge.n 800776a + { + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; + 8007748: 78fb ldrb r3, [r7, #3] + 800774a: 015a lsls r2, r3, #5 + 800774c: 68bb ldr r3, [r7, #8] + 800774e: 4413 add r3, r2 + 8007750: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8007754: 68db ldr r3, [r3, #12] + 8007756: 78fa ldrb r2, [r7, #3] + 8007758: 0151 lsls r1, r2, #5 + 800775a: 68ba ldr r2, [r7, #8] + 800775c: 440a add r2, r1 + 800775e: f502 62a0 add.w r2, r2, #1280 ; 0x500 + 8007762: f443 7380 orr.w r3, r3, #256 ; 0x100 + 8007766: 60d3 str r3, [r2, #12] + if ((USBx->CID & (0x1U << 8)) != 0U) + { + USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM); + } + } + break; + 8007768: e057 b.n 800781a + if ((USBx->CID & (0x1U << 8)) != 0U) + 800776a: 687b ldr r3, [r7, #4] + 800776c: 6bdb ldr r3, [r3, #60] ; 0x3c + 800776e: f403 7380 and.w r3, r3, #256 ; 0x100 + 8007772: 2b00 cmp r3, #0 + 8007774: d051 beq.n 800781a + USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM); + 8007776: 78fb ldrb r3, [r7, #3] + 8007778: 015a lsls r2, r3, #5 + 800777a: 68bb ldr r3, [r7, #8] + 800777c: 4413 add r3, r2 + 800777e: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8007782: 68db ldr r3, [r3, #12] + 8007784: 78fa ldrb r2, [r7, #3] + 8007786: 0151 lsls r1, r2, #5 + 8007788: 68ba ldr r2, [r7, #8] + 800778a: 440a add r2, r1 + 800778c: f502 62a0 add.w r2, r2, #1280 ; 0x500 + 8007790: f043 0360 orr.w r3, r3, #96 ; 0x60 + 8007794: 60d3 str r3, [r2, #12] + break; + 8007796: e040 b.n 800781a + + case EP_TYPE_INTR: + USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | + 8007798: 78fb ldrb r3, [r7, #3] + 800779a: 015a lsls r2, r3, #5 + 800779c: 68bb ldr r3, [r7, #8] + 800779e: 4413 add r3, r2 + 80077a0: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 80077a4: 461a mov r2, r3 + 80077a6: f240 639d movw r3, #1693 ; 0x69d + 80077aa: 60d3 str r3, [r2, #12] + USB_OTG_HCINTMSK_DTERRM | + USB_OTG_HCINTMSK_NAKM | + USB_OTG_HCINTMSK_AHBERR | + USB_OTG_HCINTMSK_FRMORM; + + if ((epnum & 0x80U) == 0x80U) + 80077ac: f997 3002 ldrsb.w r3, [r7, #2] + 80077b0: 2b00 cmp r3, #0 + 80077b2: da34 bge.n 800781e + { + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; + 80077b4: 78fb ldrb r3, [r7, #3] + 80077b6: 015a lsls r2, r3, #5 + 80077b8: 68bb ldr r3, [r7, #8] + 80077ba: 4413 add r3, r2 + 80077bc: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 80077c0: 68db ldr r3, [r3, #12] + 80077c2: 78fa ldrb r2, [r7, #3] + 80077c4: 0151 lsls r1, r2, #5 + 80077c6: 68ba ldr r2, [r7, #8] + 80077c8: 440a add r2, r1 + 80077ca: f502 62a0 add.w r2, r2, #1280 ; 0x500 + 80077ce: f443 7380 orr.w r3, r3, #256 ; 0x100 + 80077d2: 60d3 str r3, [r2, #12] + } + + break; + 80077d4: e023 b.n 800781e + + case EP_TYPE_ISOC: + USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | + 80077d6: 78fb ldrb r3, [r7, #3] + 80077d8: 015a lsls r2, r3, #5 + 80077da: 68bb ldr r3, [r7, #8] + 80077dc: 4413 add r3, r2 + 80077de: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 80077e2: 461a mov r2, r3 + 80077e4: f240 2325 movw r3, #549 ; 0x225 + 80077e8: 60d3 str r3, [r2, #12] + USB_OTG_HCINTMSK_ACKM | + USB_OTG_HCINTMSK_AHBERR | + USB_OTG_HCINTMSK_FRMORM; + + if ((epnum & 0x80U) == 0x80U) + 80077ea: f997 3002 ldrsb.w r3, [r7, #2] + 80077ee: 2b00 cmp r3, #0 + 80077f0: da17 bge.n 8007822 + { + USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM); + 80077f2: 78fb ldrb r3, [r7, #3] + 80077f4: 015a lsls r2, r3, #5 + 80077f6: 68bb ldr r3, [r7, #8] + 80077f8: 4413 add r3, r2 + 80077fa: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 80077fe: 68db ldr r3, [r3, #12] + 8007800: 78fa ldrb r2, [r7, #3] + 8007802: 0151 lsls r1, r2, #5 + 8007804: 68ba ldr r2, [r7, #8] + 8007806: 440a add r2, r1 + 8007808: f502 62a0 add.w r2, r2, #1280 ; 0x500 + 800780c: f443 73c0 orr.w r3, r3, #384 ; 0x180 + 8007810: 60d3 str r3, [r2, #12] + } + break; + 8007812: e006 b.n 8007822 + + default: + ret = HAL_ERROR; + 8007814: 2301 movs r3, #1 + 8007816: 75fb strb r3, [r7, #23] + break; + 8007818: e004 b.n 8007824 + break; + 800781a: bf00 nop + 800781c: e002 b.n 8007824 + break; + 800781e: bf00 nop + 8007820: e000 b.n 8007824 + break; + 8007822: bf00 nop + } + + /* Enable the top level host channel interrupt. */ + USBx_HOST->HAINTMSK |= 1UL << (ch_num & 0xFU); + 8007824: 68bb ldr r3, [r7, #8] + 8007826: f503 6380 add.w r3, r3, #1024 ; 0x400 + 800782a: 699a ldr r2, [r3, #24] + 800782c: 78fb ldrb r3, [r7, #3] + 800782e: f003 030f and.w r3, r3, #15 + 8007832: 2101 movs r1, #1 + 8007834: fa01 f303 lsl.w r3, r1, r3 + 8007838: 68b9 ldr r1, [r7, #8] + 800783a: f501 6180 add.w r1, r1, #1024 ; 0x400 + 800783e: 4313 orrs r3, r2 + 8007840: 618b str r3, [r1, #24] + + /* Make sure host channel interrupts are enabled. */ + USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM; + 8007842: 687b ldr r3, [r7, #4] + 8007844: 699b ldr r3, [r3, #24] + 8007846: f043 7200 orr.w r2, r3, #33554432 ; 0x2000000 + 800784a: 687b ldr r3, [r7, #4] + 800784c: 619a str r2, [r3, #24] + + /* Program the HCCHAR register */ + if ((epnum & 0x80U) == 0x80U) + 800784e: f997 3002 ldrsb.w r3, [r7, #2] + 8007852: 2b00 cmp r3, #0 + 8007854: da03 bge.n 800785e + { + HCcharEpDir = (0x1U << 15) & USB_OTG_HCCHAR_EPDIR; + 8007856: f44f 4300 mov.w r3, #32768 ; 0x8000 + 800785a: 613b str r3, [r7, #16] + 800785c: e001 b.n 8007862 + } + else + { + HCcharEpDir = 0U; + 800785e: 2300 movs r3, #0 + 8007860: 613b str r3, [r7, #16] + } + + if (speed == HPRT0_PRTSPD_LOW_SPEED) + 8007862: f897 3020 ldrb.w r3, [r7, #32] + 8007866: 2b02 cmp r3, #2 + 8007868: d103 bne.n 8007872 + { + HCcharLowSpeed = (0x1U << 17) & USB_OTG_HCCHAR_LSDEV; + 800786a: f44f 3300 mov.w r3, #131072 ; 0x20000 + 800786e: 60fb str r3, [r7, #12] + 8007870: e001 b.n 8007876 + } + else + { + HCcharLowSpeed = 0U; + 8007872: 2300 movs r3, #0 + 8007874: 60fb str r3, [r7, #12] + } + + USBx_HC((uint32_t)ch_num)->HCCHAR = (((uint32_t)dev_address << 22) & USB_OTG_HCCHAR_DAD) | + 8007876: 787b ldrb r3, [r7, #1] + 8007878: 059b lsls r3, r3, #22 + 800787a: f003 52fe and.w r2, r3, #532676608 ; 0x1fc00000 + ((((uint32_t)epnum & 0x7FU) << 11) & USB_OTG_HCCHAR_EPNUM) | + 800787e: 78bb ldrb r3, [r7, #2] + 8007880: 02db lsls r3, r3, #11 + 8007882: f403 43f0 and.w r3, r3, #30720 ; 0x7800 + USBx_HC((uint32_t)ch_num)->HCCHAR = (((uint32_t)dev_address << 22) & USB_OTG_HCCHAR_DAD) | + 8007886: 431a orrs r2, r3 + (((uint32_t)ep_type << 18) & USB_OTG_HCCHAR_EPTYP) | + 8007888: f897 3024 ldrb.w r3, [r7, #36] ; 0x24 + 800788c: 049b lsls r3, r3, #18 + 800788e: f403 2340 and.w r3, r3, #786432 ; 0xc0000 + ((((uint32_t)epnum & 0x7FU) << 11) & USB_OTG_HCCHAR_EPNUM) | + 8007892: 431a orrs r2, r3 + ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | HCcharEpDir | HCcharLowSpeed; + 8007894: 8d3b ldrh r3, [r7, #40] ; 0x28 + 8007896: f3c3 030a ubfx r3, r3, #0, #11 + (((uint32_t)ep_type << 18) & USB_OTG_HCCHAR_EPTYP) | + 800789a: 431a orrs r2, r3 + ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | HCcharEpDir | HCcharLowSpeed; + 800789c: 693b ldr r3, [r7, #16] + 800789e: 431a orrs r2, r3 + USBx_HC((uint32_t)ch_num)->HCCHAR = (((uint32_t)dev_address << 22) & USB_OTG_HCCHAR_DAD) | + 80078a0: 78fb ldrb r3, [r7, #3] + 80078a2: 0159 lsls r1, r3, #5 + 80078a4: 68bb ldr r3, [r7, #8] + 80078a6: 440b add r3, r1 + 80078a8: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 80078ac: 4619 mov r1, r3 + ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | HCcharEpDir | HCcharLowSpeed; + 80078ae: 68fb ldr r3, [r7, #12] + 80078b0: 4313 orrs r3, r2 + USBx_HC((uint32_t)ch_num)->HCCHAR = (((uint32_t)dev_address << 22) & USB_OTG_HCCHAR_DAD) | + 80078b2: 600b str r3, [r1, #0] + + if (ep_type == EP_TYPE_INTR) + 80078b4: f897 3024 ldrb.w r3, [r7, #36] ; 0x24 + 80078b8: 2b03 cmp r3, #3 + 80078ba: d10f bne.n 80078dc + { + USBx_HC((uint32_t)ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ; + 80078bc: 78fb ldrb r3, [r7, #3] + 80078be: 015a lsls r2, r3, #5 + 80078c0: 68bb ldr r3, [r7, #8] + 80078c2: 4413 add r3, r2 + 80078c4: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 80078c8: 681b ldr r3, [r3, #0] + 80078ca: 78fa ldrb r2, [r7, #3] + 80078cc: 0151 lsls r1, r2, #5 + 80078ce: 68ba ldr r2, [r7, #8] + 80078d0: 440a add r2, r1 + 80078d2: f502 62a0 add.w r2, r2, #1280 ; 0x500 + 80078d6: f043 5300 orr.w r3, r3, #536870912 ; 0x20000000 + 80078da: 6013 str r3, [r2, #0] + } + + return ret; + 80078dc: 7dfb ldrb r3, [r7, #23] +} + 80078de: 4618 mov r0, r3 + 80078e0: 371c adds r7, #28 + 80078e2: 46bd mov sp, r7 + 80078e4: f85d 7b04 ldr.w r7, [sp], #4 + 80078e8: 4770 bx lr + 80078ea: bf00 nop + +080078ec : + * 0 : DMA feature not used + * 1 : DMA feature used + * @retval HAL state + */ +HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma) +{ + 80078ec: b580 push {r7, lr} + 80078ee: b08c sub sp, #48 ; 0x30 + 80078f0: af02 add r7, sp, #8 + 80078f2: 60f8 str r0, [r7, #12] + 80078f4: 60b9 str r1, [r7, #8] + 80078f6: 4613 mov r3, r2 + 80078f8: 71fb strb r3, [r7, #7] + uint32_t USBx_BASE = (uint32_t)USBx; + 80078fa: 68fb ldr r3, [r7, #12] + 80078fc: 623b str r3, [r7, #32] + uint32_t ch_num = (uint32_t)hc->ch_num; + 80078fe: 68bb ldr r3, [r7, #8] + 8007900: 785b ldrb r3, [r3, #1] + 8007902: 61fb str r3, [r7, #28] + static __IO uint32_t tmpreg = 0U; + uint8_t is_oddframe; + uint16_t len_words; + uint16_t num_packets; + uint16_t max_hc_pkt_count = 256U; + 8007904: f44f 7380 mov.w r3, #256 ; 0x100 + 8007908: 837b strh r3, [r7, #26] + + if (((USBx->CID & (0x1U << 8)) != 0U) && (hc->speed == USBH_HS_SPEED)) + 800790a: 68fb ldr r3, [r7, #12] + 800790c: 6bdb ldr r3, [r3, #60] ; 0x3c + 800790e: f403 7380 and.w r3, r3, #256 ; 0x100 + 8007912: 2b00 cmp r3, #0 + 8007914: d028 beq.n 8007968 + 8007916: 68bb ldr r3, [r7, #8] + 8007918: 791b ldrb r3, [r3, #4] + 800791a: 2b00 cmp r3, #0 + 800791c: d124 bne.n 8007968 + { + if ((dma == 0U) && (hc->do_ping == 1U)) + 800791e: 79fb ldrb r3, [r7, #7] + 8007920: 2b00 cmp r3, #0 + 8007922: d10b bne.n 800793c + 8007924: 68bb ldr r3, [r7, #8] + 8007926: 795b ldrb r3, [r3, #5] + 8007928: 2b01 cmp r3, #1 + 800792a: d107 bne.n 800793c + { + (void)USB_DoPing(USBx, hc->ch_num); + 800792c: 68bb ldr r3, [r7, #8] + 800792e: 785b ldrb r3, [r3, #1] + 8007930: 4619 mov r1, r3 + 8007932: 68f8 ldr r0, [r7, #12] + 8007934: f000 fa30 bl 8007d98 + return HAL_OK; + 8007938: 2300 movs r3, #0 + 800793a: e114 b.n 8007b66 + } + else if (dma == 1U) + 800793c: 79fb ldrb r3, [r7, #7] + 800793e: 2b01 cmp r3, #1 + 8007940: d112 bne.n 8007968 + { + USBx_HC(ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM); + 8007942: 69fb ldr r3, [r7, #28] + 8007944: 015a lsls r2, r3, #5 + 8007946: 6a3b ldr r3, [r7, #32] + 8007948: 4413 add r3, r2 + 800794a: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 800794e: 68db ldr r3, [r3, #12] + 8007950: 69fa ldr r2, [r7, #28] + 8007952: 0151 lsls r1, r2, #5 + 8007954: 6a3a ldr r2, [r7, #32] + 8007956: 440a add r2, r1 + 8007958: f502 62a0 add.w r2, r2, #1280 ; 0x500 + 800795c: f023 0360 bic.w r3, r3, #96 ; 0x60 + 8007960: 60d3 str r3, [r2, #12] + hc->do_ping = 0U; + 8007962: 68bb ldr r3, [r7, #8] + 8007964: 2200 movs r2, #0 + 8007966: 715a strb r2, [r3, #5] + /* ... */ + } + } + + /* Compute the expected number of packets associated to the transfer */ + if (hc->xfer_len > 0U) + 8007968: 68bb ldr r3, [r7, #8] + 800796a: 691b ldr r3, [r3, #16] + 800796c: 2b00 cmp r3, #0 + 800796e: d018 beq.n 80079a2 + { + num_packets = (uint16_t)((hc->xfer_len + hc->max_packet - 1U) / hc->max_packet); + 8007970: 68bb ldr r3, [r7, #8] + 8007972: 691b ldr r3, [r3, #16] + 8007974: 68ba ldr r2, [r7, #8] + 8007976: 8912 ldrh r2, [r2, #8] + 8007978: 4413 add r3, r2 + 800797a: 3b01 subs r3, #1 + 800797c: 68ba ldr r2, [r7, #8] + 800797e: 8912 ldrh r2, [r2, #8] + 8007980: fbb3 f3f2 udiv r3, r3, r2 + 8007984: 84fb strh r3, [r7, #38] ; 0x26 + + if (num_packets > max_hc_pkt_count) + 8007986: 8cfa ldrh r2, [r7, #38] ; 0x26 + 8007988: 8b7b ldrh r3, [r7, #26] + 800798a: 429a cmp r2, r3 + 800798c: d90b bls.n 80079a6 + { + num_packets = max_hc_pkt_count; + 800798e: 8b7b ldrh r3, [r7, #26] + 8007990: 84fb strh r3, [r7, #38] ; 0x26 + hc->xfer_len = (uint32_t)num_packets * hc->max_packet; + 8007992: 8cfb ldrh r3, [r7, #38] ; 0x26 + 8007994: 68ba ldr r2, [r7, #8] + 8007996: 8912 ldrh r2, [r2, #8] + 8007998: fb02 f203 mul.w r2, r2, r3 + 800799c: 68bb ldr r3, [r7, #8] + 800799e: 611a str r2, [r3, #16] + 80079a0: e001 b.n 80079a6 + } + } + else + { + num_packets = 1U; + 80079a2: 2301 movs r3, #1 + 80079a4: 84fb strh r3, [r7, #38] ; 0x26 + } + if (hc->ep_is_in != 0U) + 80079a6: 68bb ldr r3, [r7, #8] + 80079a8: 78db ldrb r3, [r3, #3] + 80079aa: 2b00 cmp r3, #0 + 80079ac: d006 beq.n 80079bc + { + hc->xfer_len = (uint32_t)num_packets * hc->max_packet; + 80079ae: 8cfb ldrh r3, [r7, #38] ; 0x26 + 80079b0: 68ba ldr r2, [r7, #8] + 80079b2: 8912 ldrh r2, [r2, #8] + 80079b4: fb02 f203 mul.w r2, r2, r3 + 80079b8: 68bb ldr r3, [r7, #8] + 80079ba: 611a str r2, [r3, #16] + } + + /* Initialize the HCTSIZn register */ + USBx_HC(ch_num)->HCTSIZ = (hc->xfer_len & USB_OTG_HCTSIZ_XFRSIZ) | + 80079bc: 68bb ldr r3, [r7, #8] + 80079be: 691b ldr r3, [r3, #16] + 80079c0: f3c3 0212 ubfx r2, r3, #0, #19 + (((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) | + 80079c4: 8cfb ldrh r3, [r7, #38] ; 0x26 + 80079c6: 04d9 lsls r1, r3, #19 + 80079c8: 4b69 ldr r3, [pc, #420] ; (8007b70 ) + 80079ca: 400b ands r3, r1 + USBx_HC(ch_num)->HCTSIZ = (hc->xfer_len & USB_OTG_HCTSIZ_XFRSIZ) | + 80079cc: 431a orrs r2, r3 + (((uint32_t)hc->data_pid << 29) & USB_OTG_HCTSIZ_DPID); + 80079ce: 68bb ldr r3, [r7, #8] + 80079d0: 7a9b ldrb r3, [r3, #10] + 80079d2: 075b lsls r3, r3, #29 + 80079d4: f003 43c0 and.w r3, r3, #1610612736 ; 0x60000000 + USBx_HC(ch_num)->HCTSIZ = (hc->xfer_len & USB_OTG_HCTSIZ_XFRSIZ) | + 80079d8: 69f9 ldr r1, [r7, #28] + 80079da: 0148 lsls r0, r1, #5 + 80079dc: 6a39 ldr r1, [r7, #32] + 80079de: 4401 add r1, r0 + 80079e0: f501 61a0 add.w r1, r1, #1280 ; 0x500 + (((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) | + 80079e4: 4313 orrs r3, r2 + USBx_HC(ch_num)->HCTSIZ = (hc->xfer_len & USB_OTG_HCTSIZ_XFRSIZ) | + 80079e6: 610b str r3, [r1, #16] + + if (dma != 0U) + 80079e8: 79fb ldrb r3, [r7, #7] + 80079ea: 2b00 cmp r3, #0 + 80079ec: d009 beq.n 8007a02 + { + /* xfer_buff MUST be 32-bits aligned */ + USBx_HC(ch_num)->HCDMA = (uint32_t)hc->xfer_buff; + 80079ee: 68bb ldr r3, [r7, #8] + 80079f0: 68d9 ldr r1, [r3, #12] + 80079f2: 69fb ldr r3, [r7, #28] + 80079f4: 015a lsls r2, r3, #5 + 80079f6: 6a3b ldr r3, [r7, #32] + 80079f8: 4413 add r3, r2 + 80079fa: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 80079fe: 460a mov r2, r1 + 8007a00: 615a str r2, [r3, #20] + } + + is_oddframe = (((uint32_t)USBx_HOST->HFNUM & 0x01U) != 0U) ? 0U : 1U; + 8007a02: 6a3b ldr r3, [r7, #32] + 8007a04: f503 6380 add.w r3, r3, #1024 ; 0x400 + 8007a08: 689b ldr r3, [r3, #8] + 8007a0a: f003 0301 and.w r3, r3, #1 + 8007a0e: 2b00 cmp r3, #0 + 8007a10: bf0c ite eq + 8007a12: 2301 moveq r3, #1 + 8007a14: 2300 movne r3, #0 + 8007a16: b2db uxtb r3, r3 + 8007a18: 767b strb r3, [r7, #25] + USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM; + 8007a1a: 69fb ldr r3, [r7, #28] + 8007a1c: 015a lsls r2, r3, #5 + 8007a1e: 6a3b ldr r3, [r7, #32] + 8007a20: 4413 add r3, r2 + 8007a22: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8007a26: 681b ldr r3, [r3, #0] + 8007a28: 69fa ldr r2, [r7, #28] + 8007a2a: 0151 lsls r1, r2, #5 + 8007a2c: 6a3a ldr r2, [r7, #32] + 8007a2e: 440a add r2, r1 + 8007a30: f502 62a0 add.w r2, r2, #1280 ; 0x500 + 8007a34: f023 5300 bic.w r3, r3, #536870912 ; 0x20000000 + 8007a38: 6013 str r3, [r2, #0] + USBx_HC(ch_num)->HCCHAR |= (uint32_t)is_oddframe << 29; + 8007a3a: 69fb ldr r3, [r7, #28] + 8007a3c: 015a lsls r2, r3, #5 + 8007a3e: 6a3b ldr r3, [r7, #32] + 8007a40: 4413 add r3, r2 + 8007a42: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8007a46: 681a ldr r2, [r3, #0] + 8007a48: 7e7b ldrb r3, [r7, #25] + 8007a4a: 075b lsls r3, r3, #29 + 8007a4c: 69f9 ldr r1, [r7, #28] + 8007a4e: 0148 lsls r0, r1, #5 + 8007a50: 6a39 ldr r1, [r7, #32] + 8007a52: 4401 add r1, r0 + 8007a54: f501 61a0 add.w r1, r1, #1280 ; 0x500 + 8007a58: 4313 orrs r3, r2 + 8007a5a: 600b str r3, [r1, #0] + + /* Set host channel enable */ + tmpreg = USBx_HC(ch_num)->HCCHAR; + 8007a5c: 69fb ldr r3, [r7, #28] + 8007a5e: 015a lsls r2, r3, #5 + 8007a60: 6a3b ldr r3, [r7, #32] + 8007a62: 4413 add r3, r2 + 8007a64: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8007a68: 681b ldr r3, [r3, #0] + 8007a6a: 4a42 ldr r2, [pc, #264] ; (8007b74 ) + 8007a6c: 6013 str r3, [r2, #0] + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + 8007a6e: 4b41 ldr r3, [pc, #260] ; (8007b74 ) + 8007a70: 681b ldr r3, [r3, #0] + 8007a72: f023 4380 bic.w r3, r3, #1073741824 ; 0x40000000 + 8007a76: 4a3f ldr r2, [pc, #252] ; (8007b74 ) + 8007a78: 6013 str r3, [r2, #0] + + /* make sure to set the correct ep direction */ + if (hc->ep_is_in != 0U) + 8007a7a: 68bb ldr r3, [r7, #8] + 8007a7c: 78db ldrb r3, [r3, #3] + 8007a7e: 2b00 cmp r3, #0 + 8007a80: d006 beq.n 8007a90 + { + tmpreg |= USB_OTG_HCCHAR_EPDIR; + 8007a82: 4b3c ldr r3, [pc, #240] ; (8007b74 ) + 8007a84: 681b ldr r3, [r3, #0] + 8007a86: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 8007a8a: 4a3a ldr r2, [pc, #232] ; (8007b74 ) + 8007a8c: 6013 str r3, [r2, #0] + 8007a8e: e005 b.n 8007a9c + } + else + { + tmpreg &= ~USB_OTG_HCCHAR_EPDIR; + 8007a90: 4b38 ldr r3, [pc, #224] ; (8007b74 ) + 8007a92: 681b ldr r3, [r3, #0] + 8007a94: f423 4300 bic.w r3, r3, #32768 ; 0x8000 + 8007a98: 4a36 ldr r2, [pc, #216] ; (8007b74 ) + 8007a9a: 6013 str r3, [r2, #0] + } + tmpreg |= USB_OTG_HCCHAR_CHENA; + 8007a9c: 4b35 ldr r3, [pc, #212] ; (8007b74 ) + 8007a9e: 681b ldr r3, [r3, #0] + 8007aa0: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 + 8007aa4: 4a33 ldr r2, [pc, #204] ; (8007b74 ) + 8007aa6: 6013 str r3, [r2, #0] + USBx_HC(ch_num)->HCCHAR = tmpreg; + 8007aa8: 69fb ldr r3, [r7, #28] + 8007aaa: 015a lsls r2, r3, #5 + 8007aac: 6a3b ldr r3, [r7, #32] + 8007aae: 4413 add r3, r2 + 8007ab0: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8007ab4: 461a mov r2, r3 + 8007ab6: 4b2f ldr r3, [pc, #188] ; (8007b74 ) + 8007ab8: 681b ldr r3, [r3, #0] + 8007aba: 6013 str r3, [r2, #0] + + if (dma != 0U) /* dma mode */ + 8007abc: 79fb ldrb r3, [r7, #7] + 8007abe: 2b00 cmp r3, #0 + 8007ac0: d001 beq.n 8007ac6 + { + return HAL_OK; + 8007ac2: 2300 movs r3, #0 + 8007ac4: e04f b.n 8007b66 + } + + if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U)) + 8007ac6: 68bb ldr r3, [r7, #8] + 8007ac8: 78db ldrb r3, [r3, #3] + 8007aca: 2b00 cmp r3, #0 + 8007acc: d14a bne.n 8007b64 + 8007ace: 68bb ldr r3, [r7, #8] + 8007ad0: 691b ldr r3, [r3, #16] + 8007ad2: 2b00 cmp r3, #0 + 8007ad4: d046 beq.n 8007b64 + { + switch (hc->ep_type) + 8007ad6: 68bb ldr r3, [r7, #8] + 8007ad8: 79db ldrb r3, [r3, #7] + 8007ada: 2b03 cmp r3, #3 + 8007adc: d830 bhi.n 8007b40 + 8007ade: a201 add r2, pc, #4 ; (adr r2, 8007ae4 ) + 8007ae0: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8007ae4: 08007af5 .word 0x08007af5 + 8007ae8: 08007b19 .word 0x08007b19 + 8007aec: 08007af5 .word 0x08007af5 + 8007af0: 08007b19 .word 0x08007b19 + { + /* Non periodic transfer */ + case EP_TYPE_CTRL: + case EP_TYPE_BULK: + + len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); + 8007af4: 68bb ldr r3, [r7, #8] + 8007af6: 691b ldr r3, [r3, #16] + 8007af8: 3303 adds r3, #3 + 8007afa: 089b lsrs r3, r3, #2 + 8007afc: 82fb strh r3, [r7, #22] + + /* check if there is enough space in FIFO space */ + if (len_words > (USBx->HNPTXSTS & 0xFFFFU)) + 8007afe: 8afa ldrh r2, [r7, #22] + 8007b00: 68fb ldr r3, [r7, #12] + 8007b02: 6adb ldr r3, [r3, #44] ; 0x2c + 8007b04: b29b uxth r3, r3 + 8007b06: 429a cmp r2, r3 + 8007b08: d91c bls.n 8007b44 + { + /* need to process data in nptxfempty interrupt */ + USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM; + 8007b0a: 68fb ldr r3, [r7, #12] + 8007b0c: 699b ldr r3, [r3, #24] + 8007b0e: f043 0220 orr.w r2, r3, #32 + 8007b12: 68fb ldr r3, [r7, #12] + 8007b14: 619a str r2, [r3, #24] + } + break; + 8007b16: e015 b.n 8007b44 + + /* Periodic transfer */ + case EP_TYPE_INTR: + case EP_TYPE_ISOC: + len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); + 8007b18: 68bb ldr r3, [r7, #8] + 8007b1a: 691b ldr r3, [r3, #16] + 8007b1c: 3303 adds r3, #3 + 8007b1e: 089b lsrs r3, r3, #2 + 8007b20: 82fb strh r3, [r7, #22] + /* check if there is enough space in FIFO space */ + if (len_words > (USBx_HOST->HPTXSTS & 0xFFFFU)) /* split the transfer */ + 8007b22: 8afa ldrh r2, [r7, #22] + 8007b24: 6a3b ldr r3, [r7, #32] + 8007b26: f503 6380 add.w r3, r3, #1024 ; 0x400 + 8007b2a: 691b ldr r3, [r3, #16] + 8007b2c: b29b uxth r3, r3 + 8007b2e: 429a cmp r2, r3 + 8007b30: d90a bls.n 8007b48 + { + /* need to process data in ptxfempty interrupt */ + USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM; + 8007b32: 68fb ldr r3, [r7, #12] + 8007b34: 699b ldr r3, [r3, #24] + 8007b36: f043 6280 orr.w r2, r3, #67108864 ; 0x4000000 + 8007b3a: 68fb ldr r3, [r7, #12] + 8007b3c: 619a str r2, [r3, #24] + } + break; + 8007b3e: e003 b.n 8007b48 + + default: + break; + 8007b40: bf00 nop + 8007b42: e002 b.n 8007b4a + break; + 8007b44: bf00 nop + 8007b46: e000 b.n 8007b4a + break; + 8007b48: bf00 nop + } + + /* Write packet into the Tx FIFO. */ + (void)USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, (uint16_t)hc->xfer_len, 0); + 8007b4a: 68bb ldr r3, [r7, #8] + 8007b4c: 68d9 ldr r1, [r3, #12] + 8007b4e: 68bb ldr r3, [r7, #8] + 8007b50: 785a ldrb r2, [r3, #1] + 8007b52: 68bb ldr r3, [r7, #8] + 8007b54: 691b ldr r3, [r3, #16] + 8007b56: b298 uxth r0, r3 + 8007b58: 2300 movs r3, #0 + 8007b5a: 9300 str r3, [sp, #0] + 8007b5c: 4603 mov r3, r0 + 8007b5e: 68f8 ldr r0, [r7, #12] + 8007b60: f7ff fb84 bl 800726c + } + + return HAL_OK; + 8007b64: 2300 movs r3, #0 +} + 8007b66: 4618 mov r0, r3 + 8007b68: 3728 adds r7, #40 ; 0x28 + 8007b6a: 46bd mov sp, r7 + 8007b6c: bd80 pop {r7, pc} + 8007b6e: bf00 nop + 8007b70: 1ff80000 .word 0x1ff80000 + 8007b74: 2000022c .word 0x2000022c + +08007b78 : + * @brief Read all host channel interrupts status + * @param USBx Selected device + * @retval HAL state + */ +uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx) +{ + 8007b78: b480 push {r7} + 8007b7a: b085 sub sp, #20 + 8007b7c: af00 add r7, sp, #0 + 8007b7e: 6078 str r0, [r7, #4] + uint32_t USBx_BASE = (uint32_t)USBx; + 8007b80: 687b ldr r3, [r7, #4] + 8007b82: 60fb str r3, [r7, #12] + + return ((USBx_HOST->HAINT) & 0xFFFFU); + 8007b84: 68fb ldr r3, [r7, #12] + 8007b86: f503 6380 add.w r3, r3, #1024 ; 0x400 + 8007b8a: 695b ldr r3, [r3, #20] + 8007b8c: b29b uxth r3, r3 +} + 8007b8e: 4618 mov r0, r3 + 8007b90: 3714 adds r7, #20 + 8007b92: 46bd mov sp, r7 + 8007b94: f85d 7b04 ldr.w r7, [sp], #4 + 8007b98: 4770 bx lr + +08007b9a : + * @param hc_num Host Channel number + * This parameter can be a value from 1 to 15 + * @retval HAL state + */ +HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) +{ + 8007b9a: b480 push {r7} + 8007b9c: b087 sub sp, #28 + 8007b9e: af00 add r7, sp, #0 + 8007ba0: 6078 str r0, [r7, #4] + 8007ba2: 460b mov r3, r1 + 8007ba4: 70fb strb r3, [r7, #3] + uint32_t USBx_BASE = (uint32_t)USBx; + 8007ba6: 687b ldr r3, [r7, #4] + 8007ba8: 613b str r3, [r7, #16] + uint32_t hcnum = (uint32_t)hc_num; + 8007baa: 78fb ldrb r3, [r7, #3] + 8007bac: 60fb str r3, [r7, #12] + uint32_t count = 0U; + 8007bae: 2300 movs r3, #0 + 8007bb0: 617b str r3, [r7, #20] + uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18; + 8007bb2: 68fb ldr r3, [r7, #12] + 8007bb4: 015a lsls r2, r3, #5 + 8007bb6: 693b ldr r3, [r7, #16] + 8007bb8: 4413 add r3, r2 + 8007bba: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8007bbe: 681b ldr r3, [r3, #0] + 8007bc0: 0c9b lsrs r3, r3, #18 + 8007bc2: f003 0303 and.w r3, r3, #3 + 8007bc6: 60bb str r3, [r7, #8] + + /* Check for space in the request queue to issue the halt. */ + if ((HcEpType == HCCHAR_CTRL) || (HcEpType == HCCHAR_BULK)) + 8007bc8: 68bb ldr r3, [r7, #8] + 8007bca: 2b00 cmp r3, #0 + 8007bcc: d002 beq.n 8007bd4 + 8007bce: 68bb ldr r3, [r7, #8] + 8007bd0: 2b02 cmp r3, #2 + 8007bd2: d16c bne.n 8007cae + { + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; + 8007bd4: 68fb ldr r3, [r7, #12] + 8007bd6: 015a lsls r2, r3, #5 + 8007bd8: 693b ldr r3, [r7, #16] + 8007bda: 4413 add r3, r2 + 8007bdc: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8007be0: 681b ldr r3, [r3, #0] + 8007be2: 68fa ldr r2, [r7, #12] + 8007be4: 0151 lsls r1, r2, #5 + 8007be6: 693a ldr r2, [r7, #16] + 8007be8: 440a add r2, r1 + 8007bea: f502 62a0 add.w r2, r2, #1280 ; 0x500 + 8007bee: f043 4380 orr.w r3, r3, #1073741824 ; 0x40000000 + 8007bf2: 6013 str r3, [r2, #0] + + if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U) + 8007bf4: 687b ldr r3, [r7, #4] + 8007bf6: 6adb ldr r3, [r3, #44] ; 0x2c + 8007bf8: f403 037f and.w r3, r3, #16711680 ; 0xff0000 + 8007bfc: 2b00 cmp r3, #0 + 8007bfe: d143 bne.n 8007c88 + { + USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; + 8007c00: 68fb ldr r3, [r7, #12] + 8007c02: 015a lsls r2, r3, #5 + 8007c04: 693b ldr r3, [r7, #16] + 8007c06: 4413 add r3, r2 + 8007c08: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8007c0c: 681b ldr r3, [r3, #0] + 8007c0e: 68fa ldr r2, [r7, #12] + 8007c10: 0151 lsls r1, r2, #5 + 8007c12: 693a ldr r2, [r7, #16] + 8007c14: 440a add r2, r1 + 8007c16: f502 62a0 add.w r2, r2, #1280 ; 0x500 + 8007c1a: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000 + 8007c1e: 6013 str r3, [r2, #0] + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + 8007c20: 68fb ldr r3, [r7, #12] + 8007c22: 015a lsls r2, r3, #5 + 8007c24: 693b ldr r3, [r7, #16] + 8007c26: 4413 add r3, r2 + 8007c28: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8007c2c: 681b ldr r3, [r3, #0] + 8007c2e: 68fa ldr r2, [r7, #12] + 8007c30: 0151 lsls r1, r2, #5 + 8007c32: 693a ldr r2, [r7, #16] + 8007c34: 440a add r2, r1 + 8007c36: f502 62a0 add.w r2, r2, #1280 ; 0x500 + 8007c3a: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 + 8007c3e: 6013 str r3, [r2, #0] + USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR; + 8007c40: 68fb ldr r3, [r7, #12] + 8007c42: 015a lsls r2, r3, #5 + 8007c44: 693b ldr r3, [r7, #16] + 8007c46: 4413 add r3, r2 + 8007c48: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8007c4c: 681b ldr r3, [r3, #0] + 8007c4e: 68fa ldr r2, [r7, #12] + 8007c50: 0151 lsls r1, r2, #5 + 8007c52: 693a ldr r2, [r7, #16] + 8007c54: 440a add r2, r1 + 8007c56: f502 62a0 add.w r2, r2, #1280 ; 0x500 + 8007c5a: f423 4300 bic.w r3, r3, #32768 ; 0x8000 + 8007c5e: 6013 str r3, [r2, #0] + do + { + if (++count > 1000U) + 8007c60: 697b ldr r3, [r7, #20] + 8007c62: 3301 adds r3, #1 + 8007c64: 617b str r3, [r7, #20] + 8007c66: 697b ldr r3, [r7, #20] + 8007c68: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 + 8007c6c: d81d bhi.n 8007caa + { + break; + } + } while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + 8007c6e: 68fb ldr r3, [r7, #12] + 8007c70: 015a lsls r2, r3, #5 + 8007c72: 693b ldr r3, [r7, #16] + 8007c74: 4413 add r3, r2 + 8007c76: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8007c7a: 681b ldr r3, [r3, #0] + 8007c7c: f003 4300 and.w r3, r3, #2147483648 ; 0x80000000 + 8007c80: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000 + 8007c84: d0ec beq.n 8007c60 + if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U) + 8007c86: e080 b.n 8007d8a + } + else + { + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + 8007c88: 68fb ldr r3, [r7, #12] + 8007c8a: 015a lsls r2, r3, #5 + 8007c8c: 693b ldr r3, [r7, #16] + 8007c8e: 4413 add r3, r2 + 8007c90: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8007c94: 681b ldr r3, [r3, #0] + 8007c96: 68fa ldr r2, [r7, #12] + 8007c98: 0151 lsls r1, r2, #5 + 8007c9a: 693a ldr r2, [r7, #16] + 8007c9c: 440a add r2, r1 + 8007c9e: f502 62a0 add.w r2, r2, #1280 ; 0x500 + 8007ca2: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 + 8007ca6: 6013 str r3, [r2, #0] + if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U) + 8007ca8: e06f b.n 8007d8a + break; + 8007caa: bf00 nop + if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U) + 8007cac: e06d b.n 8007d8a + } + } + else + { + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; + 8007cae: 68fb ldr r3, [r7, #12] + 8007cb0: 015a lsls r2, r3, #5 + 8007cb2: 693b ldr r3, [r7, #16] + 8007cb4: 4413 add r3, r2 + 8007cb6: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8007cba: 681b ldr r3, [r3, #0] + 8007cbc: 68fa ldr r2, [r7, #12] + 8007cbe: 0151 lsls r1, r2, #5 + 8007cc0: 693a ldr r2, [r7, #16] + 8007cc2: 440a add r2, r1 + 8007cc4: f502 62a0 add.w r2, r2, #1280 ; 0x500 + 8007cc8: f043 4380 orr.w r3, r3, #1073741824 ; 0x40000000 + 8007ccc: 6013 str r3, [r2, #0] + + if ((USBx_HOST->HPTXSTS & (0xFFU << 16)) == 0U) + 8007cce: 693b ldr r3, [r7, #16] + 8007cd0: f503 6380 add.w r3, r3, #1024 ; 0x400 + 8007cd4: 691b ldr r3, [r3, #16] + 8007cd6: f403 037f and.w r3, r3, #16711680 ; 0xff0000 + 8007cda: 2b00 cmp r3, #0 + 8007cdc: d143 bne.n 8007d66 + { + USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; + 8007cde: 68fb ldr r3, [r7, #12] + 8007ce0: 015a lsls r2, r3, #5 + 8007ce2: 693b ldr r3, [r7, #16] + 8007ce4: 4413 add r3, r2 + 8007ce6: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8007cea: 681b ldr r3, [r3, #0] + 8007cec: 68fa ldr r2, [r7, #12] + 8007cee: 0151 lsls r1, r2, #5 + 8007cf0: 693a ldr r2, [r7, #16] + 8007cf2: 440a add r2, r1 + 8007cf4: f502 62a0 add.w r2, r2, #1280 ; 0x500 + 8007cf8: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000 + 8007cfc: 6013 str r3, [r2, #0] + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + 8007cfe: 68fb ldr r3, [r7, #12] + 8007d00: 015a lsls r2, r3, #5 + 8007d02: 693b ldr r3, [r7, #16] + 8007d04: 4413 add r3, r2 + 8007d06: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8007d0a: 681b ldr r3, [r3, #0] + 8007d0c: 68fa ldr r2, [r7, #12] + 8007d0e: 0151 lsls r1, r2, #5 + 8007d10: 693a ldr r2, [r7, #16] + 8007d12: 440a add r2, r1 + 8007d14: f502 62a0 add.w r2, r2, #1280 ; 0x500 + 8007d18: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 + 8007d1c: 6013 str r3, [r2, #0] + USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR; + 8007d1e: 68fb ldr r3, [r7, #12] + 8007d20: 015a lsls r2, r3, #5 + 8007d22: 693b ldr r3, [r7, #16] + 8007d24: 4413 add r3, r2 + 8007d26: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8007d2a: 681b ldr r3, [r3, #0] + 8007d2c: 68fa ldr r2, [r7, #12] + 8007d2e: 0151 lsls r1, r2, #5 + 8007d30: 693a ldr r2, [r7, #16] + 8007d32: 440a add r2, r1 + 8007d34: f502 62a0 add.w r2, r2, #1280 ; 0x500 + 8007d38: f423 4300 bic.w r3, r3, #32768 ; 0x8000 + 8007d3c: 6013 str r3, [r2, #0] + do + { + if (++count > 1000U) + 8007d3e: 697b ldr r3, [r7, #20] + 8007d40: 3301 adds r3, #1 + 8007d42: 617b str r3, [r7, #20] + 8007d44: 697b ldr r3, [r7, #20] + 8007d46: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 + 8007d4a: d81d bhi.n 8007d88 + { + break; + } + } while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + 8007d4c: 68fb ldr r3, [r7, #12] + 8007d4e: 015a lsls r2, r3, #5 + 8007d50: 693b ldr r3, [r7, #16] + 8007d52: 4413 add r3, r2 + 8007d54: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8007d58: 681b ldr r3, [r3, #0] + 8007d5a: f003 4300 and.w r3, r3, #2147483648 ; 0x80000000 + 8007d5e: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000 + 8007d62: d0ec beq.n 8007d3e + 8007d64: e011 b.n 8007d8a + } + else + { + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + 8007d66: 68fb ldr r3, [r7, #12] + 8007d68: 015a lsls r2, r3, #5 + 8007d6a: 693b ldr r3, [r7, #16] + 8007d6c: 4413 add r3, r2 + 8007d6e: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8007d72: 681b ldr r3, [r3, #0] + 8007d74: 68fa ldr r2, [r7, #12] + 8007d76: 0151 lsls r1, r2, #5 + 8007d78: 693a ldr r2, [r7, #16] + 8007d7a: 440a add r2, r1 + 8007d7c: f502 62a0 add.w r2, r2, #1280 ; 0x500 + 8007d80: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 + 8007d84: 6013 str r3, [r2, #0] + 8007d86: e000 b.n 8007d8a + break; + 8007d88: bf00 nop + } + } + + return HAL_OK; + 8007d8a: 2300 movs r3, #0 +} + 8007d8c: 4618 mov r0, r3 + 8007d8e: 371c adds r7, #28 + 8007d90: 46bd mov sp, r7 + 8007d92: f85d 7b04 ldr.w r7, [sp], #4 + 8007d96: 4770 bx lr + +08007d98 : + * @param hc_num Host Channel number + * This parameter can be a value from 1 to 15 + * @retval HAL state + */ +HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num) +{ + 8007d98: b480 push {r7} + 8007d9a: b087 sub sp, #28 + 8007d9c: af00 add r7, sp, #0 + 8007d9e: 6078 str r0, [r7, #4] + 8007da0: 460b mov r3, r1 + 8007da2: 70fb strb r3, [r7, #3] + uint32_t USBx_BASE = (uint32_t)USBx; + 8007da4: 687b ldr r3, [r7, #4] + 8007da6: 617b str r3, [r7, #20] + uint32_t chnum = (uint32_t)ch_num; + 8007da8: 78fb ldrb r3, [r7, #3] + 8007daa: 613b str r3, [r7, #16] + uint32_t num_packets = 1U; + 8007dac: 2301 movs r3, #1 + 8007dae: 60fb str r3, [r7, #12] + uint32_t tmpreg; + + USBx_HC(chnum)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) | + 8007db0: 68fb ldr r3, [r7, #12] + 8007db2: 04da lsls r2, r3, #19 + 8007db4: 4b15 ldr r3, [pc, #84] ; (8007e0c ) + 8007db6: 4013 ands r3, r2 + 8007db8: 693a ldr r2, [r7, #16] + 8007dba: 0151 lsls r1, r2, #5 + 8007dbc: 697a ldr r2, [r7, #20] + 8007dbe: 440a add r2, r1 + 8007dc0: f502 62a0 add.w r2, r2, #1280 ; 0x500 + 8007dc4: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 + 8007dc8: 6113 str r3, [r2, #16] + USB_OTG_HCTSIZ_DOPING; + + /* Set host channel enable */ + tmpreg = USBx_HC(chnum)->HCCHAR; + 8007dca: 693b ldr r3, [r7, #16] + 8007dcc: 015a lsls r2, r3, #5 + 8007dce: 697b ldr r3, [r7, #20] + 8007dd0: 4413 add r3, r2 + 8007dd2: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8007dd6: 681b ldr r3, [r3, #0] + 8007dd8: 60bb str r3, [r7, #8] + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + 8007dda: 68bb ldr r3, [r7, #8] + 8007ddc: f023 4380 bic.w r3, r3, #1073741824 ; 0x40000000 + 8007de0: 60bb str r3, [r7, #8] + tmpreg |= USB_OTG_HCCHAR_CHENA; + 8007de2: 68bb ldr r3, [r7, #8] + 8007de4: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 + 8007de8: 60bb str r3, [r7, #8] + USBx_HC(chnum)->HCCHAR = tmpreg; + 8007dea: 693b ldr r3, [r7, #16] + 8007dec: 015a lsls r2, r3, #5 + 8007dee: 697b ldr r3, [r7, #20] + 8007df0: 4413 add r3, r2 + 8007df2: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8007df6: 461a mov r2, r3 + 8007df8: 68bb ldr r3, [r7, #8] + 8007dfa: 6013 str r3, [r2, #0] + + return HAL_OK; + 8007dfc: 2300 movs r3, #0 +} + 8007dfe: 4618 mov r0, r3 + 8007e00: 371c adds r7, #28 + 8007e02: 46bd mov sp, r7 + 8007e04: f85d 7b04 ldr.w r7, [sp], #4 + 8007e08: 4770 bx lr + 8007e0a: bf00 nop + 8007e0c: 1ff80000 .word 0x1ff80000 + +08007e10 : + * @brief Stop Host Core + * @param USBx Selected device + * @retval HAL state + */ +HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) +{ + 8007e10: b580 push {r7, lr} + 8007e12: b086 sub sp, #24 + 8007e14: af00 add r7, sp, #0 + 8007e16: 6078 str r0, [r7, #4] + uint32_t USBx_BASE = (uint32_t)USBx; + 8007e18: 687b ldr r3, [r7, #4] + 8007e1a: 60fb str r3, [r7, #12] + uint32_t count = 0U; + 8007e1c: 2300 movs r3, #0 + 8007e1e: 617b str r3, [r7, #20] + uint32_t value; + uint32_t i; + + (void)USB_DisableGlobalInt(USBx); + 8007e20: 6878 ldr r0, [r7, #4] + 8007e22: f7ff f99f bl 8007164 + + /* Flush FIFO */ + (void)USB_FlushTxFifo(USBx, 0x10U); + 8007e26: 2110 movs r1, #16 + 8007e28: 6878 ldr r0, [r7, #4] + 8007e2a: f7ff f9d7 bl 80071dc + (void)USB_FlushRxFifo(USBx); + 8007e2e: 6878 ldr r0, [r7, #4] + 8007e30: f7ff f9fa bl 8007228 + + /* Flush out any leftover queued requests. */ + for (i = 0U; i <= 15U; i++) + 8007e34: 2300 movs r3, #0 + 8007e36: 613b str r3, [r7, #16] + 8007e38: e01f b.n 8007e7a + { + value = USBx_HC(i)->HCCHAR; + 8007e3a: 693b ldr r3, [r7, #16] + 8007e3c: 015a lsls r2, r3, #5 + 8007e3e: 68fb ldr r3, [r7, #12] + 8007e40: 4413 add r3, r2 + 8007e42: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8007e46: 681b ldr r3, [r3, #0] + 8007e48: 60bb str r3, [r7, #8] + value |= USB_OTG_HCCHAR_CHDIS; + 8007e4a: 68bb ldr r3, [r7, #8] + 8007e4c: f043 4380 orr.w r3, r3, #1073741824 ; 0x40000000 + 8007e50: 60bb str r3, [r7, #8] + value &= ~USB_OTG_HCCHAR_CHENA; + 8007e52: 68bb ldr r3, [r7, #8] + 8007e54: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000 + 8007e58: 60bb str r3, [r7, #8] + value &= ~USB_OTG_HCCHAR_EPDIR; + 8007e5a: 68bb ldr r3, [r7, #8] + 8007e5c: f423 4300 bic.w r3, r3, #32768 ; 0x8000 + 8007e60: 60bb str r3, [r7, #8] + USBx_HC(i)->HCCHAR = value; + 8007e62: 693b ldr r3, [r7, #16] + 8007e64: 015a lsls r2, r3, #5 + 8007e66: 68fb ldr r3, [r7, #12] + 8007e68: 4413 add r3, r2 + 8007e6a: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8007e6e: 461a mov r2, r3 + 8007e70: 68bb ldr r3, [r7, #8] + 8007e72: 6013 str r3, [r2, #0] + for (i = 0U; i <= 15U; i++) + 8007e74: 693b ldr r3, [r7, #16] + 8007e76: 3301 adds r3, #1 + 8007e78: 613b str r3, [r7, #16] + 8007e7a: 693b ldr r3, [r7, #16] + 8007e7c: 2b0f cmp r3, #15 + 8007e7e: d9dc bls.n 8007e3a + } + + /* Halt all channels to put them into a known state. */ + for (i = 0U; i <= 15U; i++) + 8007e80: 2300 movs r3, #0 + 8007e82: 613b str r3, [r7, #16] + 8007e84: e034 b.n 8007ef0 + { + value = USBx_HC(i)->HCCHAR; + 8007e86: 693b ldr r3, [r7, #16] + 8007e88: 015a lsls r2, r3, #5 + 8007e8a: 68fb ldr r3, [r7, #12] + 8007e8c: 4413 add r3, r2 + 8007e8e: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8007e92: 681b ldr r3, [r3, #0] + 8007e94: 60bb str r3, [r7, #8] + value |= USB_OTG_HCCHAR_CHDIS; + 8007e96: 68bb ldr r3, [r7, #8] + 8007e98: f043 4380 orr.w r3, r3, #1073741824 ; 0x40000000 + 8007e9c: 60bb str r3, [r7, #8] + value |= USB_OTG_HCCHAR_CHENA; + 8007e9e: 68bb ldr r3, [r7, #8] + 8007ea0: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 + 8007ea4: 60bb str r3, [r7, #8] + value &= ~USB_OTG_HCCHAR_EPDIR; + 8007ea6: 68bb ldr r3, [r7, #8] + 8007ea8: f423 4300 bic.w r3, r3, #32768 ; 0x8000 + 8007eac: 60bb str r3, [r7, #8] + USBx_HC(i)->HCCHAR = value; + 8007eae: 693b ldr r3, [r7, #16] + 8007eb0: 015a lsls r2, r3, #5 + 8007eb2: 68fb ldr r3, [r7, #12] + 8007eb4: 4413 add r3, r2 + 8007eb6: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8007eba: 461a mov r2, r3 + 8007ebc: 68bb ldr r3, [r7, #8] + 8007ebe: 6013 str r3, [r2, #0] + + do + { + if (++count > 1000U) + 8007ec0: 697b ldr r3, [r7, #20] + 8007ec2: 3301 adds r3, #1 + 8007ec4: 617b str r3, [r7, #20] + 8007ec6: 697b ldr r3, [r7, #20] + 8007ec8: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 + 8007ecc: d80c bhi.n 8007ee8 + { + break; + } + } while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + 8007ece: 693b ldr r3, [r7, #16] + 8007ed0: 015a lsls r2, r3, #5 + 8007ed2: 68fb ldr r3, [r7, #12] + 8007ed4: 4413 add r3, r2 + 8007ed6: f503 63a0 add.w r3, r3, #1280 ; 0x500 + 8007eda: 681b ldr r3, [r3, #0] + 8007edc: f003 4300 and.w r3, r3, #2147483648 ; 0x80000000 + 8007ee0: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000 + 8007ee4: d0ec beq.n 8007ec0 + 8007ee6: e000 b.n 8007eea + break; + 8007ee8: bf00 nop + for (i = 0U; i <= 15U; i++) + 8007eea: 693b ldr r3, [r7, #16] + 8007eec: 3301 adds r3, #1 + 8007eee: 613b str r3, [r7, #16] + 8007ef0: 693b ldr r3, [r7, #16] + 8007ef2: 2b0f cmp r3, #15 + 8007ef4: d9c7 bls.n 8007e86 + } + + /* Clear any pending Host interrupts */ + USBx_HOST->HAINT = 0xFFFFFFFFU; + 8007ef6: 68fb ldr r3, [r7, #12] + 8007ef8: f503 6380 add.w r3, r3, #1024 ; 0x400 + 8007efc: 461a mov r2, r3 + 8007efe: f04f 33ff mov.w r3, #4294967295 + 8007f02: 6153 str r3, [r2, #20] + USBx->GINTSTS = 0xFFFFFFFFU; + 8007f04: 687b ldr r3, [r7, #4] + 8007f06: f04f 32ff mov.w r2, #4294967295 + 8007f0a: 615a str r2, [r3, #20] + + (void)USB_EnableGlobalInt(USBx); + 8007f0c: 6878 ldr r0, [r7, #4] + 8007f0e: f7ff f918 bl 8007142 + + return HAL_OK; + 8007f12: 2300 movs r3, #0 +} + 8007f14: 4618 mov r0, r3 + 8007f16: 3718 adds r7, #24 + 8007f18: 46bd mov sp, r7 + 8007f1a: bd80 pop {r7, pc} + +08007f1c : + * The function init the CDC class. + * @param phost: Host handle + * @retval USBH Status + */ +static USBH_StatusTypeDef USBH_CDC_InterfaceInit(USBH_HandleTypeDef *phost) +{ + 8007f1c: b590 push {r4, r7, lr} + 8007f1e: b089 sub sp, #36 ; 0x24 + 8007f20: af04 add r7, sp, #16 + 8007f22: 6078 str r0, [r7, #4] + + USBH_StatusTypeDef status; + uint8_t interface; + CDC_HandleTypeDef *CDC_Handle; + + interface = USBH_FindInterface(phost, COMMUNICATION_INTERFACE_CLASS_CODE, + 8007f24: 2301 movs r3, #1 + 8007f26: 2202 movs r2, #2 + 8007f28: 2102 movs r1, #2 + 8007f2a: 6878 ldr r0, [r7, #4] + 8007f2c: f000 fc68 bl 8008800 + 8007f30: 4603 mov r3, r0 + 8007f32: 73fb strb r3, [r7, #15] + ABSTRACT_CONTROL_MODEL, COMMON_AT_COMMAND); + + if ((interface == 0xFFU) || (interface >= USBH_MAX_NUM_INTERFACES)) /* No Valid Interface */ + 8007f34: 7bfb ldrb r3, [r7, #15] + 8007f36: 2bff cmp r3, #255 ; 0xff + 8007f38: d002 beq.n 8007f40 + 8007f3a: 7bfb ldrb r3, [r7, #15] + 8007f3c: 2b01 cmp r3, #1 + 8007f3e: d901 bls.n 8007f44 + { + USBH_DbgLog("Cannot Find the interface for Communication Interface Class.", phost->pActiveClass->Name); + return USBH_FAIL; + 8007f40: 2302 movs r3, #2 + 8007f42: e13d b.n 80081c0 + } + + status = USBH_SelectInterface(phost, interface); + 8007f44: 7bfb ldrb r3, [r7, #15] + 8007f46: 4619 mov r1, r3 + 8007f48: 6878 ldr r0, [r7, #4] + 8007f4a: f000 fc3d bl 80087c8 + 8007f4e: 4603 mov r3, r0 + 8007f50: 73bb strb r3, [r7, #14] + + if (status != USBH_OK) + 8007f52: 7bbb ldrb r3, [r7, #14] + 8007f54: 2b00 cmp r3, #0 + 8007f56: d001 beq.n 8007f5c + { + return USBH_FAIL; + 8007f58: 2302 movs r3, #2 + 8007f5a: e131 b.n 80081c0 + } + + phost->pActiveClass->pData = (CDC_HandleTypeDef *)USBH_malloc(sizeof(CDC_HandleTypeDef)); + 8007f5c: 687b ldr r3, [r7, #4] + 8007f5e: f8d3 437c ldr.w r4, [r3, #892] ; 0x37c + 8007f62: 2050 movs r0, #80 ; 0x50 + 8007f64: f002 fa04 bl 800a370 + 8007f68: 4603 mov r3, r0 + 8007f6a: 61e3 str r3, [r4, #28] + CDC_Handle = (CDC_HandleTypeDef *) phost->pActiveClass->pData; + 8007f6c: 687b ldr r3, [r7, #4] + 8007f6e: f8d3 337c ldr.w r3, [r3, #892] ; 0x37c + 8007f72: 69db ldr r3, [r3, #28] + 8007f74: 60bb str r3, [r7, #8] + + if (CDC_Handle == NULL) + 8007f76: 68bb ldr r3, [r7, #8] + 8007f78: 2b00 cmp r3, #0 + 8007f7a: d101 bne.n 8007f80 + { + USBH_DbgLog("Cannot allocate memory for CDC Handle"); + return USBH_FAIL; + 8007f7c: 2302 movs r3, #2 + 8007f7e: e11f b.n 80081c0 + } + + /* Initialize cdc handler */ + USBH_memset(CDC_Handle, 0, sizeof(CDC_HandleTypeDef)); + 8007f80: 2250 movs r2, #80 ; 0x50 + 8007f82: 2100 movs r1, #0 + 8007f84: 68b8 ldr r0, [r7, #8] + 8007f86: f002 fa03 bl 800a390 + + /*Collect the notification endpoint address and length*/ + if (phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[0].bEndpointAddress & 0x80U) + 8007f8a: 7bfb ldrb r3, [r7, #15] + 8007f8c: 687a ldr r2, [r7, #4] + 8007f8e: 211a movs r1, #26 + 8007f90: fb01 f303 mul.w r3, r1, r3 + 8007f94: 4413 add r3, r2 + 8007f96: f203 334e addw r3, r3, #846 ; 0x34e + 8007f9a: 781b ldrb r3, [r3, #0] + 8007f9c: b25b sxtb r3, r3 + 8007f9e: 2b00 cmp r3, #0 + 8007fa0: da15 bge.n 8007fce + { + CDC_Handle->CommItf.NotifEp = phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[0].bEndpointAddress; + 8007fa2: 7bfb ldrb r3, [r7, #15] + 8007fa4: 687a ldr r2, [r7, #4] + 8007fa6: 211a movs r1, #26 + 8007fa8: fb01 f303 mul.w r3, r1, r3 + 8007fac: 4413 add r3, r2 + 8007fae: f203 334e addw r3, r3, #846 ; 0x34e + 8007fb2: 781a ldrb r2, [r3, #0] + 8007fb4: 68bb ldr r3, [r7, #8] + 8007fb6: 705a strb r2, [r3, #1] + CDC_Handle->CommItf.NotifEpSize = phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[0].wMaxPacketSize; + 8007fb8: 7bfb ldrb r3, [r7, #15] + 8007fba: 687a ldr r2, [r7, #4] + 8007fbc: 211a movs r1, #26 + 8007fbe: fb01 f303 mul.w r3, r1, r3 + 8007fc2: 4413 add r3, r2 + 8007fc4: f503 7354 add.w r3, r3, #848 ; 0x350 + 8007fc8: 881a ldrh r2, [r3, #0] + 8007fca: 68bb ldr r3, [r7, #8] + 8007fcc: 815a strh r2, [r3, #10] + } + + /*Allocate the length for host channel number in*/ + CDC_Handle->CommItf.NotifPipe = USBH_AllocPipe(phost, CDC_Handle->CommItf.NotifEp); + 8007fce: 68bb ldr r3, [r7, #8] + 8007fd0: 785b ldrb r3, [r3, #1] + 8007fd2: 4619 mov r1, r3 + 8007fd4: 6878 ldr r0, [r7, #4] + 8007fd6: f001 fe36 bl 8009c46 + 8007fda: 4603 mov r3, r0 + 8007fdc: 461a mov r2, r3 + 8007fde: 68bb ldr r3, [r7, #8] + 8007fe0: 701a strb r2, [r3, #0] + + /* Open pipe for Notification endpoint */ + USBH_OpenPipe(phost, CDC_Handle->CommItf.NotifPipe, CDC_Handle->CommItf.NotifEp, + 8007fe2: 68bb ldr r3, [r7, #8] + 8007fe4: 7819 ldrb r1, [r3, #0] + 8007fe6: 68bb ldr r3, [r7, #8] + 8007fe8: 7858 ldrb r0, [r3, #1] + 8007fea: 687b ldr r3, [r7, #4] + 8007fec: f893 431c ldrb.w r4, [r3, #796] ; 0x31c + 8007ff0: 687b ldr r3, [r7, #4] + 8007ff2: f893 331d ldrb.w r3, [r3, #797] ; 0x31d + 8007ff6: 68ba ldr r2, [r7, #8] + 8007ff8: 8952 ldrh r2, [r2, #10] + 8007ffa: 9202 str r2, [sp, #8] + 8007ffc: 2203 movs r2, #3 + 8007ffe: 9201 str r2, [sp, #4] + 8008000: 9300 str r3, [sp, #0] + 8008002: 4623 mov r3, r4 + 8008004: 4602 mov r2, r0 + 8008006: 6878 ldr r0, [r7, #4] + 8008008: f001 fdee bl 8009be8 + phost->device.address, phost->device.speed, USB_EP_TYPE_INTR, + CDC_Handle->CommItf.NotifEpSize); + + USBH_LL_SetToggle(phost, CDC_Handle->CommItf.NotifPipe, 0U); + 800800c: 68bb ldr r3, [r7, #8] + 800800e: 781b ldrb r3, [r3, #0] + 8008010: 2200 movs r2, #0 + 8008012: 4619 mov r1, r3 + 8008014: 6878 ldr r0, [r7, #4] + 8008016: f002 f8fb bl 800a210 + + interface = USBH_FindInterface(phost, DATA_INTERFACE_CLASS_CODE, + 800801a: 2300 movs r3, #0 + 800801c: 2200 movs r2, #0 + 800801e: 210a movs r1, #10 + 8008020: 6878 ldr r0, [r7, #4] + 8008022: f000 fbed bl 8008800 + 8008026: 4603 mov r3, r0 + 8008028: 73fb strb r3, [r7, #15] + RESERVED, NO_CLASS_SPECIFIC_PROTOCOL_CODE); + + if ((interface == 0xFFU) || (interface >= USBH_MAX_NUM_INTERFACES)) /* No Valid Interface */ + 800802a: 7bfb ldrb r3, [r7, #15] + 800802c: 2bff cmp r3, #255 ; 0xff + 800802e: d002 beq.n 8008036 + 8008030: 7bfb ldrb r3, [r7, #15] + 8008032: 2b01 cmp r3, #1 + 8008034: d901 bls.n 800803a + { + USBH_DbgLog("Cannot Find the interface for Data Interface Class.", phost->pActiveClass->Name); + return USBH_FAIL; + 8008036: 2302 movs r3, #2 + 8008038: e0c2 b.n 80081c0 + } + + /*Collect the class specific endpoint address and length*/ + if (phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[0].bEndpointAddress & 0x80U) + 800803a: 7bfb ldrb r3, [r7, #15] + 800803c: 687a ldr r2, [r7, #4] + 800803e: 211a movs r1, #26 + 8008040: fb01 f303 mul.w r3, r1, r3 + 8008044: 4413 add r3, r2 + 8008046: f203 334e addw r3, r3, #846 ; 0x34e + 800804a: 781b ldrb r3, [r3, #0] + 800804c: b25b sxtb r3, r3 + 800804e: 2b00 cmp r3, #0 + 8008050: da16 bge.n 8008080 + { + CDC_Handle->DataItf.InEp = phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[0].bEndpointAddress; + 8008052: 7bfb ldrb r3, [r7, #15] + 8008054: 687a ldr r2, [r7, #4] + 8008056: 211a movs r1, #26 + 8008058: fb01 f303 mul.w r3, r1, r3 + 800805c: 4413 add r3, r2 + 800805e: f203 334e addw r3, r3, #846 ; 0x34e + 8008062: 781a ldrb r2, [r3, #0] + 8008064: 68bb ldr r3, [r7, #8] + 8008066: 73da strb r2, [r3, #15] + CDC_Handle->DataItf.InEpSize = phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[0].wMaxPacketSize; + 8008068: 7bfb ldrb r3, [r7, #15] + 800806a: 687a ldr r2, [r7, #4] + 800806c: 211a movs r1, #26 + 800806e: fb01 f303 mul.w r3, r1, r3 + 8008072: 4413 add r3, r2 + 8008074: f503 7354 add.w r3, r3, #848 ; 0x350 + 8008078: 881a ldrh r2, [r3, #0] + 800807a: 68bb ldr r3, [r7, #8] + 800807c: 835a strh r2, [r3, #26] + 800807e: e015 b.n 80080ac + } + else + { + CDC_Handle->DataItf.OutEp = phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[0].bEndpointAddress; + 8008080: 7bfb ldrb r3, [r7, #15] + 8008082: 687a ldr r2, [r7, #4] + 8008084: 211a movs r1, #26 + 8008086: fb01 f303 mul.w r3, r1, r3 + 800808a: 4413 add r3, r2 + 800808c: f203 334e addw r3, r3, #846 ; 0x34e + 8008090: 781a ldrb r2, [r3, #0] + 8008092: 68bb ldr r3, [r7, #8] + 8008094: 739a strb r2, [r3, #14] + CDC_Handle->DataItf.OutEpSize = phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[0].wMaxPacketSize; + 8008096: 7bfb ldrb r3, [r7, #15] + 8008098: 687a ldr r2, [r7, #4] + 800809a: 211a movs r1, #26 + 800809c: fb01 f303 mul.w r3, r1, r3 + 80080a0: 4413 add r3, r2 + 80080a2: f503 7354 add.w r3, r3, #848 ; 0x350 + 80080a6: 881a ldrh r2, [r3, #0] + 80080a8: 68bb ldr r3, [r7, #8] + 80080aa: 831a strh r2, [r3, #24] + } + + if (phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[1].bEndpointAddress & 0x80U) + 80080ac: 7bfb ldrb r3, [r7, #15] + 80080ae: 687a ldr r2, [r7, #4] + 80080b0: 211a movs r1, #26 + 80080b2: fb01 f303 mul.w r3, r1, r3 + 80080b6: 4413 add r3, r2 + 80080b8: f203 3356 addw r3, r3, #854 ; 0x356 + 80080bc: 781b ldrb r3, [r3, #0] + 80080be: b25b sxtb r3, r3 + 80080c0: 2b00 cmp r3, #0 + 80080c2: da16 bge.n 80080f2 + { + CDC_Handle->DataItf.InEp = phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[1].bEndpointAddress; + 80080c4: 7bfb ldrb r3, [r7, #15] + 80080c6: 687a ldr r2, [r7, #4] + 80080c8: 211a movs r1, #26 + 80080ca: fb01 f303 mul.w r3, r1, r3 + 80080ce: 4413 add r3, r2 + 80080d0: f203 3356 addw r3, r3, #854 ; 0x356 + 80080d4: 781a ldrb r2, [r3, #0] + 80080d6: 68bb ldr r3, [r7, #8] + 80080d8: 73da strb r2, [r3, #15] + CDC_Handle->DataItf.InEpSize = phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[1].wMaxPacketSize; + 80080da: 7bfb ldrb r3, [r7, #15] + 80080dc: 687a ldr r2, [r7, #4] + 80080de: 211a movs r1, #26 + 80080e0: fb01 f303 mul.w r3, r1, r3 + 80080e4: 4413 add r3, r2 + 80080e6: f503 7356 add.w r3, r3, #856 ; 0x358 + 80080ea: 881a ldrh r2, [r3, #0] + 80080ec: 68bb ldr r3, [r7, #8] + 80080ee: 835a strh r2, [r3, #26] + 80080f0: e015 b.n 800811e + } + else + { + CDC_Handle->DataItf.OutEp = phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[1].bEndpointAddress; + 80080f2: 7bfb ldrb r3, [r7, #15] + 80080f4: 687a ldr r2, [r7, #4] + 80080f6: 211a movs r1, #26 + 80080f8: fb01 f303 mul.w r3, r1, r3 + 80080fc: 4413 add r3, r2 + 80080fe: f203 3356 addw r3, r3, #854 ; 0x356 + 8008102: 781a ldrb r2, [r3, #0] + 8008104: 68bb ldr r3, [r7, #8] + 8008106: 739a strb r2, [r3, #14] + CDC_Handle->DataItf.OutEpSize = phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[1].wMaxPacketSize; + 8008108: 7bfb ldrb r3, [r7, #15] + 800810a: 687a ldr r2, [r7, #4] + 800810c: 211a movs r1, #26 + 800810e: fb01 f303 mul.w r3, r1, r3 + 8008112: 4413 add r3, r2 + 8008114: f503 7356 add.w r3, r3, #856 ; 0x358 + 8008118: 881a ldrh r2, [r3, #0] + 800811a: 68bb ldr r3, [r7, #8] + 800811c: 831a strh r2, [r3, #24] + } + + /*Allocate the length for host channel number out*/ + CDC_Handle->DataItf.OutPipe = USBH_AllocPipe(phost, CDC_Handle->DataItf.OutEp); + 800811e: 68bb ldr r3, [r7, #8] + 8008120: 7b9b ldrb r3, [r3, #14] + 8008122: 4619 mov r1, r3 + 8008124: 6878 ldr r0, [r7, #4] + 8008126: f001 fd8e bl 8009c46 + 800812a: 4603 mov r3, r0 + 800812c: 461a mov r2, r3 + 800812e: 68bb ldr r3, [r7, #8] + 8008130: 735a strb r2, [r3, #13] + + /*Allocate the length for host channel number in*/ + CDC_Handle->DataItf.InPipe = USBH_AllocPipe(phost, CDC_Handle->DataItf.InEp); + 8008132: 68bb ldr r3, [r7, #8] + 8008134: 7bdb ldrb r3, [r3, #15] + 8008136: 4619 mov r1, r3 + 8008138: 6878 ldr r0, [r7, #4] + 800813a: f001 fd84 bl 8009c46 + 800813e: 4603 mov r3, r0 + 8008140: 461a mov r2, r3 + 8008142: 68bb ldr r3, [r7, #8] + 8008144: 731a strb r2, [r3, #12] + + /* Open channel for OUT endpoint */ + USBH_OpenPipe(phost, CDC_Handle->DataItf.OutPipe, CDC_Handle->DataItf.OutEp, + 8008146: 68bb ldr r3, [r7, #8] + 8008148: 7b59 ldrb r1, [r3, #13] + 800814a: 68bb ldr r3, [r7, #8] + 800814c: 7b98 ldrb r0, [r3, #14] + 800814e: 687b ldr r3, [r7, #4] + 8008150: f893 431c ldrb.w r4, [r3, #796] ; 0x31c + 8008154: 687b ldr r3, [r7, #4] + 8008156: f893 331d ldrb.w r3, [r3, #797] ; 0x31d + 800815a: 68ba ldr r2, [r7, #8] + 800815c: 8b12 ldrh r2, [r2, #24] + 800815e: 9202 str r2, [sp, #8] + 8008160: 2202 movs r2, #2 + 8008162: 9201 str r2, [sp, #4] + 8008164: 9300 str r3, [sp, #0] + 8008166: 4623 mov r3, r4 + 8008168: 4602 mov r2, r0 + 800816a: 6878 ldr r0, [r7, #4] + 800816c: f001 fd3c bl 8009be8 + phost->device.address, phost->device.speed, USB_EP_TYPE_BULK, + CDC_Handle->DataItf.OutEpSize); + + /* Open channel for IN endpoint */ + USBH_OpenPipe(phost, CDC_Handle->DataItf.InPipe, CDC_Handle->DataItf.InEp, + 8008170: 68bb ldr r3, [r7, #8] + 8008172: 7b19 ldrb r1, [r3, #12] + 8008174: 68bb ldr r3, [r7, #8] + 8008176: 7bd8 ldrb r0, [r3, #15] + 8008178: 687b ldr r3, [r7, #4] + 800817a: f893 431c ldrb.w r4, [r3, #796] ; 0x31c + 800817e: 687b ldr r3, [r7, #4] + 8008180: f893 331d ldrb.w r3, [r3, #797] ; 0x31d + 8008184: 68ba ldr r2, [r7, #8] + 8008186: 8b52 ldrh r2, [r2, #26] + 8008188: 9202 str r2, [sp, #8] + 800818a: 2202 movs r2, #2 + 800818c: 9201 str r2, [sp, #4] + 800818e: 9300 str r3, [sp, #0] + 8008190: 4623 mov r3, r4 + 8008192: 4602 mov r2, r0 + 8008194: 6878 ldr r0, [r7, #4] + 8008196: f001 fd27 bl 8009be8 + phost->device.address, phost->device.speed, USB_EP_TYPE_BULK, + CDC_Handle->DataItf.InEpSize); + + CDC_Handle->state = CDC_IDLE_STATE; + 800819a: 68bb ldr r3, [r7, #8] + 800819c: 2200 movs r2, #0 + 800819e: f883 204c strb.w r2, [r3, #76] ; 0x4c + + USBH_LL_SetToggle(phost, CDC_Handle->DataItf.OutPipe, 0U); + 80081a2: 68bb ldr r3, [r7, #8] + 80081a4: 7b5b ldrb r3, [r3, #13] + 80081a6: 2200 movs r2, #0 + 80081a8: 4619 mov r1, r3 + 80081aa: 6878 ldr r0, [r7, #4] + 80081ac: f002 f830 bl 800a210 + USBH_LL_SetToggle(phost, CDC_Handle->DataItf.InPipe, 0U); + 80081b0: 68bb ldr r3, [r7, #8] + 80081b2: 7b1b ldrb r3, [r3, #12] + 80081b4: 2200 movs r2, #0 + 80081b6: 4619 mov r1, r3 + 80081b8: 6878 ldr r0, [r7, #4] + 80081ba: f002 f829 bl 800a210 + + return USBH_OK; + 80081be: 2300 movs r3, #0 +} + 80081c0: 4618 mov r0, r3 + 80081c2: 3714 adds r7, #20 + 80081c4: 46bd mov sp, r7 + 80081c6: bd90 pop {r4, r7, pc} + +080081c8 : + * The function DeInit the Pipes used for the CDC class. + * @param phost: Host handle + * @retval USBH Status + */ +static USBH_StatusTypeDef USBH_CDC_InterfaceDeInit(USBH_HandleTypeDef *phost) +{ + 80081c8: b580 push {r7, lr} + 80081ca: b084 sub sp, #16 + 80081cc: af00 add r7, sp, #0 + 80081ce: 6078 str r0, [r7, #4] + CDC_HandleTypeDef *CDC_Handle = (CDC_HandleTypeDef *) phost->pActiveClass->pData; + 80081d0: 687b ldr r3, [r7, #4] + 80081d2: f8d3 337c ldr.w r3, [r3, #892] ; 0x37c + 80081d6: 69db ldr r3, [r3, #28] + 80081d8: 60fb str r3, [r7, #12] + + if (CDC_Handle->CommItf.NotifPipe) + 80081da: 68fb ldr r3, [r7, #12] + 80081dc: 781b ldrb r3, [r3, #0] + 80081de: 2b00 cmp r3, #0 + 80081e0: d00e beq.n 8008200 + { + USBH_ClosePipe(phost, CDC_Handle->CommItf.NotifPipe); + 80081e2: 68fb ldr r3, [r7, #12] + 80081e4: 781b ldrb r3, [r3, #0] + 80081e6: 4619 mov r1, r3 + 80081e8: 6878 ldr r0, [r7, #4] + 80081ea: f001 fd1c bl 8009c26 + USBH_FreePipe(phost, CDC_Handle->CommItf.NotifPipe); + 80081ee: 68fb ldr r3, [r7, #12] + 80081f0: 781b ldrb r3, [r3, #0] + 80081f2: 4619 mov r1, r3 + 80081f4: 6878 ldr r0, [r7, #4] + 80081f6: f001 fd47 bl 8009c88 + CDC_Handle->CommItf.NotifPipe = 0U; /* Reset the Channel as Free */ + 80081fa: 68fb ldr r3, [r7, #12] + 80081fc: 2200 movs r2, #0 + 80081fe: 701a strb r2, [r3, #0] + } + + if (CDC_Handle->DataItf.InPipe) + 8008200: 68fb ldr r3, [r7, #12] + 8008202: 7b1b ldrb r3, [r3, #12] + 8008204: 2b00 cmp r3, #0 + 8008206: d00e beq.n 8008226 + { + USBH_ClosePipe(phost, CDC_Handle->DataItf.InPipe); + 8008208: 68fb ldr r3, [r7, #12] + 800820a: 7b1b ldrb r3, [r3, #12] + 800820c: 4619 mov r1, r3 + 800820e: 6878 ldr r0, [r7, #4] + 8008210: f001 fd09 bl 8009c26 + USBH_FreePipe(phost, CDC_Handle->DataItf.InPipe); + 8008214: 68fb ldr r3, [r7, #12] + 8008216: 7b1b ldrb r3, [r3, #12] + 8008218: 4619 mov r1, r3 + 800821a: 6878 ldr r0, [r7, #4] + 800821c: f001 fd34 bl 8009c88 + CDC_Handle->DataItf.InPipe = 0U; /* Reset the Channel as Free */ + 8008220: 68fb ldr r3, [r7, #12] + 8008222: 2200 movs r2, #0 + 8008224: 731a strb r2, [r3, #12] + } + + if (CDC_Handle->DataItf.OutPipe) + 8008226: 68fb ldr r3, [r7, #12] + 8008228: 7b5b ldrb r3, [r3, #13] + 800822a: 2b00 cmp r3, #0 + 800822c: d00e beq.n 800824c + { + USBH_ClosePipe(phost, CDC_Handle->DataItf.OutPipe); + 800822e: 68fb ldr r3, [r7, #12] + 8008230: 7b5b ldrb r3, [r3, #13] + 8008232: 4619 mov r1, r3 + 8008234: 6878 ldr r0, [r7, #4] + 8008236: f001 fcf6 bl 8009c26 + USBH_FreePipe(phost, CDC_Handle->DataItf.OutPipe); + 800823a: 68fb ldr r3, [r7, #12] + 800823c: 7b5b ldrb r3, [r3, #13] + 800823e: 4619 mov r1, r3 + 8008240: 6878 ldr r0, [r7, #4] + 8008242: f001 fd21 bl 8009c88 + CDC_Handle->DataItf.OutPipe = 0U; /* Reset the Channel as Free */ + 8008246: 68fb ldr r3, [r7, #12] + 8008248: 2200 movs r2, #0 + 800824a: 735a strb r2, [r3, #13] + } + + if (phost->pActiveClass->pData) + 800824c: 687b ldr r3, [r7, #4] + 800824e: f8d3 337c ldr.w r3, [r3, #892] ; 0x37c + 8008252: 69db ldr r3, [r3, #28] + 8008254: 2b00 cmp r3, #0 + 8008256: d00b beq.n 8008270 + { + USBH_free(phost->pActiveClass->pData); + 8008258: 687b ldr r3, [r7, #4] + 800825a: f8d3 337c ldr.w r3, [r3, #892] ; 0x37c + 800825e: 69db ldr r3, [r3, #28] + 8008260: 4618 mov r0, r3 + 8008262: f002 f88d bl 800a380 + phost->pActiveClass->pData = 0U; + 8008266: 687b ldr r3, [r7, #4] + 8008268: f8d3 337c ldr.w r3, [r3, #892] ; 0x37c + 800826c: 2200 movs r2, #0 + 800826e: 61da str r2, [r3, #28] + } + + return USBH_OK; + 8008270: 2300 movs r3, #0 +} + 8008272: 4618 mov r0, r3 + 8008274: 3710 adds r7, #16 + 8008276: 46bd mov sp, r7 + 8008278: bd80 pop {r7, pc} + +0800827a : + * for CDC class. + * @param phost: Host handle + * @retval USBH Status + */ +static USBH_StatusTypeDef USBH_CDC_ClassRequest(USBH_HandleTypeDef *phost) +{ + 800827a: b580 push {r7, lr} + 800827c: b084 sub sp, #16 + 800827e: af00 add r7, sp, #0 + 8008280: 6078 str r0, [r7, #4] + USBH_StatusTypeDef status; + CDC_HandleTypeDef *CDC_Handle = (CDC_HandleTypeDef *) phost->pActiveClass->pData; + 8008282: 687b ldr r3, [r7, #4] + 8008284: f8d3 337c ldr.w r3, [r3, #892] ; 0x37c + 8008288: 69db ldr r3, [r3, #28] + 800828a: 60fb str r3, [r7, #12] + + /* Issue the get line coding request */ + status = GetLineCoding(phost, &CDC_Handle->LineCoding); + 800828c: 68fb ldr r3, [r7, #12] + 800828e: 3340 adds r3, #64 ; 0x40 + 8008290: 4619 mov r1, r3 + 8008292: 6878 ldr r0, [r7, #4] + 8008294: f000 f8b1 bl 80083fa + 8008298: 4603 mov r3, r0 + 800829a: 72fb strb r3, [r7, #11] + if (status == USBH_OK) + 800829c: 7afb ldrb r3, [r7, #11] + 800829e: 2b00 cmp r3, #0 + 80082a0: d105 bne.n 80082ae + { + phost->pUser(phost, HOST_USER_CLASS_ACTIVE); + 80082a2: 687b ldr r3, [r7, #4] + 80082a4: f8d3 33d4 ldr.w r3, [r3, #980] ; 0x3d4 + 80082a8: 2102 movs r1, #2 + 80082aa: 6878 ldr r0, [r7, #4] + 80082ac: 4798 blx r3 + else + { + /* .. */ + } + + return status; + 80082ae: 7afb ldrb r3, [r7, #11] +} + 80082b0: 4618 mov r0, r3 + 80082b2: 3710 adds r7, #16 + 80082b4: 46bd mov sp, r7 + 80082b6: bd80 pop {r7, pc} + +080082b8 : + * The function is for managing state machine for CDC data transfers + * @param phost: Host handle + * @retval USBH Status + */ +static USBH_StatusTypeDef USBH_CDC_Process(USBH_HandleTypeDef *phost) +{ + 80082b8: b580 push {r7, lr} + 80082ba: b084 sub sp, #16 + 80082bc: af00 add r7, sp, #0 + 80082be: 6078 str r0, [r7, #4] + USBH_StatusTypeDef status = USBH_BUSY; + 80082c0: 2301 movs r3, #1 + 80082c2: 73fb strb r3, [r7, #15] + USBH_StatusTypeDef req_status = USBH_OK; + 80082c4: 2300 movs r3, #0 + 80082c6: 73bb strb r3, [r7, #14] + CDC_HandleTypeDef *CDC_Handle = (CDC_HandleTypeDef *) phost->pActiveClass->pData; + 80082c8: 687b ldr r3, [r7, #4] + 80082ca: f8d3 337c ldr.w r3, [r3, #892] ; 0x37c + 80082ce: 69db ldr r3, [r3, #28] + 80082d0: 60bb str r3, [r7, #8] + + switch (CDC_Handle->state) + 80082d2: 68bb ldr r3, [r7, #8] + 80082d4: f893 304c ldrb.w r3, [r3, #76] ; 0x4c + 80082d8: 2b04 cmp r3, #4 + 80082da: d877 bhi.n 80083cc + 80082dc: a201 add r2, pc, #4 ; (adr r2, 80082e4 ) + 80082de: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 80082e2: bf00 nop + 80082e4: 080082f9 .word 0x080082f9 + 80082e8: 080082ff .word 0x080082ff + 80082ec: 0800832f .word 0x0800832f + 80082f0: 080083a3 .word 0x080083a3 + 80082f4: 080083b1 .word 0x080083b1 + { + + case CDC_IDLE_STATE: + status = USBH_OK; + 80082f8: 2300 movs r3, #0 + 80082fa: 73fb strb r3, [r7, #15] + break; + 80082fc: e06d b.n 80083da + + case CDC_SET_LINE_CODING_STATE: + req_status = SetLineCoding(phost, CDC_Handle->pUserLineCoding); + 80082fe: 68bb ldr r3, [r7, #8] + 8008300: 6c9b ldr r3, [r3, #72] ; 0x48 + 8008302: 4619 mov r1, r3 + 8008304: 6878 ldr r0, [r7, #4] + 8008306: f000 f897 bl 8008438 + 800830a: 4603 mov r3, r0 + 800830c: 73bb strb r3, [r7, #14] + + if (req_status == USBH_OK) + 800830e: 7bbb ldrb r3, [r7, #14] + 8008310: 2b00 cmp r3, #0 + 8008312: d104 bne.n 800831e + { + CDC_Handle->state = CDC_GET_LAST_LINE_CODING_STATE; + 8008314: 68bb ldr r3, [r7, #8] + 8008316: 2202 movs r2, #2 + 8008318: f883 204c strb.w r2, [r3, #76] ; 0x4c + if (req_status != USBH_BUSY) + { + CDC_Handle->state = CDC_ERROR_STATE; + } + } + break; + 800831c: e058 b.n 80083d0 + if (req_status != USBH_BUSY) + 800831e: 7bbb ldrb r3, [r7, #14] + 8008320: 2b01 cmp r3, #1 + 8008322: d055 beq.n 80083d0 + CDC_Handle->state = CDC_ERROR_STATE; + 8008324: 68bb ldr r3, [r7, #8] + 8008326: 2204 movs r2, #4 + 8008328: f883 204c strb.w r2, [r3, #76] ; 0x4c + break; + 800832c: e050 b.n 80083d0 + + + case CDC_GET_LAST_LINE_CODING_STATE: + req_status = GetLineCoding(phost, &(CDC_Handle->LineCoding)); + 800832e: 68bb ldr r3, [r7, #8] + 8008330: 3340 adds r3, #64 ; 0x40 + 8008332: 4619 mov r1, r3 + 8008334: 6878 ldr r0, [r7, #4] + 8008336: f000 f860 bl 80083fa + 800833a: 4603 mov r3, r0 + 800833c: 73bb strb r3, [r7, #14] + + if (req_status == USBH_OK) + 800833e: 7bbb ldrb r3, [r7, #14] + 8008340: 2b00 cmp r3, #0 + 8008342: d126 bne.n 8008392 + { + CDC_Handle->state = CDC_IDLE_STATE; + 8008344: 68bb ldr r3, [r7, #8] + 8008346: 2200 movs r2, #0 + 8008348: f883 204c strb.w r2, [r3, #76] ; 0x4c + + if ((CDC_Handle->LineCoding.b.bCharFormat == CDC_Handle->pUserLineCoding->b.bCharFormat) && + 800834c: 68bb ldr r3, [r7, #8] + 800834e: f893 2044 ldrb.w r2, [r3, #68] ; 0x44 + 8008352: 68bb ldr r3, [r7, #8] + 8008354: 6c9b ldr r3, [r3, #72] ; 0x48 + 8008356: 791b ldrb r3, [r3, #4] + 8008358: 429a cmp r2, r3 + 800835a: d13b bne.n 80083d4 + (CDC_Handle->LineCoding.b.bDataBits == CDC_Handle->pUserLineCoding->b.bDataBits) && + 800835c: 68bb ldr r3, [r7, #8] + 800835e: f893 2046 ldrb.w r2, [r3, #70] ; 0x46 + 8008362: 68bb ldr r3, [r7, #8] + 8008364: 6c9b ldr r3, [r3, #72] ; 0x48 + 8008366: 799b ldrb r3, [r3, #6] + if ((CDC_Handle->LineCoding.b.bCharFormat == CDC_Handle->pUserLineCoding->b.bCharFormat) && + 8008368: 429a cmp r2, r3 + 800836a: d133 bne.n 80083d4 + (CDC_Handle->LineCoding.b.bParityType == CDC_Handle->pUserLineCoding->b.bParityType) && + 800836c: 68bb ldr r3, [r7, #8] + 800836e: f893 2045 ldrb.w r2, [r3, #69] ; 0x45 + 8008372: 68bb ldr r3, [r7, #8] + 8008374: 6c9b ldr r3, [r3, #72] ; 0x48 + 8008376: 795b ldrb r3, [r3, #5] + (CDC_Handle->LineCoding.b.bDataBits == CDC_Handle->pUserLineCoding->b.bDataBits) && + 8008378: 429a cmp r2, r3 + 800837a: d12b bne.n 80083d4 + (CDC_Handle->LineCoding.b.dwDTERate == CDC_Handle->pUserLineCoding->b.dwDTERate)) + 800837c: 68bb ldr r3, [r7, #8] + 800837e: 6c1a ldr r2, [r3, #64] ; 0x40 + 8008380: 68bb ldr r3, [r7, #8] + 8008382: 6c9b ldr r3, [r3, #72] ; 0x48 + 8008384: 681b ldr r3, [r3, #0] + (CDC_Handle->LineCoding.b.bParityType == CDC_Handle->pUserLineCoding->b.bParityType) && + 8008386: 429a cmp r2, r3 + 8008388: d124 bne.n 80083d4 + { + USBH_CDC_LineCodingChanged(phost); + 800838a: 6878 ldr r0, [r7, #4] + 800838c: f000 f95a bl 8008644 + if (req_status != USBH_BUSY) + { + CDC_Handle->state = CDC_ERROR_STATE; + } + } + break; + 8008390: e020 b.n 80083d4 + if (req_status != USBH_BUSY) + 8008392: 7bbb ldrb r3, [r7, #14] + 8008394: 2b01 cmp r3, #1 + 8008396: d01d beq.n 80083d4 + CDC_Handle->state = CDC_ERROR_STATE; + 8008398: 68bb ldr r3, [r7, #8] + 800839a: 2204 movs r2, #4 + 800839c: f883 204c strb.w r2, [r3, #76] ; 0x4c + break; + 80083a0: e018 b.n 80083d4 + + case CDC_TRANSFER_DATA: + CDC_ProcessTransmission(phost); + 80083a2: 6878 ldr r0, [r7, #4] + 80083a4: f000 f867 bl 8008476 + CDC_ProcessReception(phost); + 80083a8: 6878 ldr r0, [r7, #4] + 80083aa: f000 f8dc bl 8008566 + break; + 80083ae: e014 b.n 80083da + + case CDC_ERROR_STATE: + req_status = USBH_ClrFeature(phost, 0x00U); + 80083b0: 2100 movs r1, #0 + 80083b2: 6878 ldr r0, [r7, #4] + 80083b4: f000 ffe5 bl 8009382 + 80083b8: 4603 mov r3, r0 + 80083ba: 73bb strb r3, [r7, #14] + + if (req_status == USBH_OK) + 80083bc: 7bbb ldrb r3, [r7, #14] + 80083be: 2b00 cmp r3, #0 + 80083c0: d10a bne.n 80083d8 + { + /*Change the state to waiting*/ + CDC_Handle->state = CDC_IDLE_STATE; + 80083c2: 68bb ldr r3, [r7, #8] + 80083c4: 2200 movs r2, #0 + 80083c6: f883 204c strb.w r2, [r3, #76] ; 0x4c + } + break; + 80083ca: e005 b.n 80083d8 + + default: + break; + 80083cc: bf00 nop + 80083ce: e004 b.n 80083da + break; + 80083d0: bf00 nop + 80083d2: e002 b.n 80083da + break; + 80083d4: bf00 nop + 80083d6: e000 b.n 80083da + break; + 80083d8: bf00 nop + + } + + return status; + 80083da: 7bfb ldrb r3, [r7, #15] +} + 80083dc: 4618 mov r0, r3 + 80083de: 3710 adds r7, #16 + 80083e0: 46bd mov sp, r7 + 80083e2: bd80 pop {r7, pc} + +080083e4 : + * The function is for managing SOF callback + * @param phost: Host handle + * @retval USBH Status + */ +static USBH_StatusTypeDef USBH_CDC_SOFProcess(USBH_HandleTypeDef *phost) +{ + 80083e4: b480 push {r7} + 80083e6: b083 sub sp, #12 + 80083e8: af00 add r7, sp, #0 + 80083ea: 6078 str r0, [r7, #4] + /* Prevent unused argument(s) compilation warning */ + UNUSED(phost); + + return USBH_OK; + 80083ec: 2300 movs r3, #0 +} + 80083ee: 4618 mov r0, r3 + 80083f0: 370c adds r7, #12 + 80083f2: 46bd mov sp, r7 + 80083f4: f85d 7b04 ldr.w r7, [sp], #4 + 80083f8: 4770 bx lr + +080083fa : + * configured line coding. + * @param pdev: Selected device + * @retval USBH_StatusTypeDef : USB ctl xfer status + */ +static USBH_StatusTypeDef GetLineCoding(USBH_HandleTypeDef *phost, CDC_LineCodingTypeDef *linecoding) +{ + 80083fa: b580 push {r7, lr} + 80083fc: b082 sub sp, #8 + 80083fe: af00 add r7, sp, #0 + 8008400: 6078 str r0, [r7, #4] + 8008402: 6039 str r1, [r7, #0] + + phost->Control.setup.b.bmRequestType = USB_D2H | USB_REQ_TYPE_CLASS | \ + 8008404: 687b ldr r3, [r7, #4] + 8008406: 22a1 movs r2, #161 ; 0xa1 + 8008408: 741a strb r2, [r3, #16] + USB_REQ_RECIPIENT_INTERFACE; + + phost->Control.setup.b.bRequest = CDC_GET_LINE_CODING; + 800840a: 687b ldr r3, [r7, #4] + 800840c: 2221 movs r2, #33 ; 0x21 + 800840e: 745a strb r2, [r3, #17] + phost->Control.setup.b.wValue.w = 0U; + 8008410: 687b ldr r3, [r7, #4] + 8008412: 2200 movs r2, #0 + 8008414: 825a strh r2, [r3, #18] + phost->Control.setup.b.wIndex.w = 0U; + 8008416: 687b ldr r3, [r7, #4] + 8008418: 2200 movs r2, #0 + 800841a: 829a strh r2, [r3, #20] + phost->Control.setup.b.wLength.w = LINE_CODING_STRUCTURE_SIZE; + 800841c: 687b ldr r3, [r7, #4] + 800841e: 2207 movs r2, #7 + 8008420: 82da strh r2, [r3, #22] + + return USBH_CtlReq(phost, linecoding->Array, LINE_CODING_STRUCTURE_SIZE); + 8008422: 683b ldr r3, [r7, #0] + 8008424: 2207 movs r2, #7 + 8008426: 4619 mov r1, r3 + 8008428: 6878 ldr r0, [r7, #4] + 800842a: f001 f98a bl 8009742 + 800842e: 4603 mov r3, r0 +} + 8008430: 4618 mov r0, r3 + 8008432: 3708 adds r7, #8 + 8008434: 46bd mov sp, r7 + 8008436: bd80 pop {r7, pc} + +08008438 : + * @param pdev: Selected device + * @retval USBH_StatusTypeDef : USB ctl xfer status + */ +static USBH_StatusTypeDef SetLineCoding(USBH_HandleTypeDef *phost, + CDC_LineCodingTypeDef *linecoding) +{ + 8008438: b580 push {r7, lr} + 800843a: b082 sub sp, #8 + 800843c: af00 add r7, sp, #0 + 800843e: 6078 str r0, [r7, #4] + 8008440: 6039 str r1, [r7, #0] + phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_TYPE_CLASS | + 8008442: 687b ldr r3, [r7, #4] + 8008444: 2221 movs r2, #33 ; 0x21 + 8008446: 741a strb r2, [r3, #16] + USB_REQ_RECIPIENT_INTERFACE; + + phost->Control.setup.b.bRequest = CDC_SET_LINE_CODING; + 8008448: 687b ldr r3, [r7, #4] + 800844a: 2220 movs r2, #32 + 800844c: 745a strb r2, [r3, #17] + phost->Control.setup.b.wValue.w = 0U; + 800844e: 687b ldr r3, [r7, #4] + 8008450: 2200 movs r2, #0 + 8008452: 825a strh r2, [r3, #18] + + phost->Control.setup.b.wIndex.w = 0U; + 8008454: 687b ldr r3, [r7, #4] + 8008456: 2200 movs r2, #0 + 8008458: 829a strh r2, [r3, #20] + + phost->Control.setup.b.wLength.w = LINE_CODING_STRUCTURE_SIZE; + 800845a: 687b ldr r3, [r7, #4] + 800845c: 2207 movs r2, #7 + 800845e: 82da strh r2, [r3, #22] + + return USBH_CtlReq(phost, linecoding->Array, LINE_CODING_STRUCTURE_SIZE); + 8008460: 683b ldr r3, [r7, #0] + 8008462: 2207 movs r2, #7 + 8008464: 4619 mov r1, r3 + 8008466: 6878 ldr r0, [r7, #4] + 8008468: f001 f96b bl 8009742 + 800846c: 4603 mov r3, r0 +} + 800846e: 4618 mov r0, r3 + 8008470: 3708 adds r7, #8 + 8008472: 46bd mov sp, r7 + 8008474: bd80 pop {r7, pc} + +08008476 : +* @brief The function is responsible for sending data to the device +* @param pdev: Selected device +* @retval None +*/ +static void CDC_ProcessTransmission(USBH_HandleTypeDef *phost) +{ + 8008476: b580 push {r7, lr} + 8008478: b086 sub sp, #24 + 800847a: af02 add r7, sp, #8 + 800847c: 6078 str r0, [r7, #4] + CDC_HandleTypeDef *CDC_Handle = (CDC_HandleTypeDef *) phost->pActiveClass->pData; + 800847e: 687b ldr r3, [r7, #4] + 8008480: f8d3 337c ldr.w r3, [r3, #892] ; 0x37c + 8008484: 69db ldr r3, [r3, #28] + 8008486: 60fb str r3, [r7, #12] + USBH_URBStateTypeDef URB_Status = USBH_URB_IDLE; + 8008488: 2300 movs r3, #0 + 800848a: 72fb strb r3, [r7, #11] + + switch (CDC_Handle->data_tx_state) + 800848c: 68fb ldr r3, [r7, #12] + 800848e: f893 304d ldrb.w r3, [r3, #77] ; 0x4d + 8008492: 2b01 cmp r3, #1 + 8008494: d002 beq.n 800849c + 8008496: 2b02 cmp r3, #2 + 8008498: d025 beq.n 80084e6 + } + } + break; + + default: + break; + 800849a: e060 b.n 800855e + if (CDC_Handle->TxDataLength > CDC_Handle->DataItf.OutEpSize) + 800849c: 68fb ldr r3, [r7, #12] + 800849e: 6a5b ldr r3, [r3, #36] ; 0x24 + 80084a0: 68fa ldr r2, [r7, #12] + 80084a2: 8b12 ldrh r2, [r2, #24] + 80084a4: 4293 cmp r3, r2 + 80084a6: d90c bls.n 80084c2 + USBH_BulkSendData(phost, + 80084a8: 68fb ldr r3, [r7, #12] + 80084aa: 69d9 ldr r1, [r3, #28] + 80084ac: 68fb ldr r3, [r7, #12] + 80084ae: 8b1a ldrh r2, [r3, #24] + 80084b0: 68fb ldr r3, [r7, #12] + 80084b2: 7b58 ldrb r0, [r3, #13] + 80084b4: 2301 movs r3, #1 + 80084b6: 9300 str r3, [sp, #0] + 80084b8: 4603 mov r3, r0 + 80084ba: 6878 ldr r0, [r7, #4] + 80084bc: f001 fb51 bl 8009b62 + 80084c0: e00c b.n 80084dc + USBH_BulkSendData(phost, + 80084c2: 68fb ldr r3, [r7, #12] + 80084c4: 69d9 ldr r1, [r3, #28] + (uint16_t)CDC_Handle->TxDataLength, + 80084c6: 68fb ldr r3, [r7, #12] + 80084c8: 6a5b ldr r3, [r3, #36] ; 0x24 + USBH_BulkSendData(phost, + 80084ca: b29a uxth r2, r3 + 80084cc: 68fb ldr r3, [r7, #12] + 80084ce: 7b58 ldrb r0, [r3, #13] + 80084d0: 2301 movs r3, #1 + 80084d2: 9300 str r3, [sp, #0] + 80084d4: 4603 mov r3, r0 + 80084d6: 6878 ldr r0, [r7, #4] + 80084d8: f001 fb43 bl 8009b62 + CDC_Handle->data_tx_state = CDC_SEND_DATA_WAIT; + 80084dc: 68fb ldr r3, [r7, #12] + 80084de: 2202 movs r2, #2 + 80084e0: f883 204d strb.w r2, [r3, #77] ; 0x4d + break; + 80084e4: e03b b.n 800855e + URB_Status = USBH_LL_GetURBState(phost, CDC_Handle->DataItf.OutPipe); + 80084e6: 68fb ldr r3, [r7, #12] + 80084e8: 7b5b ldrb r3, [r3, #13] + 80084ea: 4619 mov r1, r3 + 80084ec: 6878 ldr r0, [r7, #4] + 80084ee: f001 fe65 bl 800a1bc + 80084f2: 4603 mov r3, r0 + 80084f4: 72fb strb r3, [r7, #11] + if (URB_Status == USBH_URB_DONE) + 80084f6: 7afb ldrb r3, [r7, #11] + 80084f8: 2b01 cmp r3, #1 + 80084fa: d128 bne.n 800854e + if (CDC_Handle->TxDataLength > CDC_Handle->DataItf.OutEpSize) + 80084fc: 68fb ldr r3, [r7, #12] + 80084fe: 6a5b ldr r3, [r3, #36] ; 0x24 + 8008500: 68fa ldr r2, [r7, #12] + 8008502: 8b12 ldrh r2, [r2, #24] + 8008504: 4293 cmp r3, r2 + 8008506: d90e bls.n 8008526 + CDC_Handle->TxDataLength -= CDC_Handle->DataItf.OutEpSize; + 8008508: 68fb ldr r3, [r7, #12] + 800850a: 6a5b ldr r3, [r3, #36] ; 0x24 + 800850c: 68fa ldr r2, [r7, #12] + 800850e: 8b12 ldrh r2, [r2, #24] + 8008510: 1a9a subs r2, r3, r2 + 8008512: 68fb ldr r3, [r7, #12] + 8008514: 625a str r2, [r3, #36] ; 0x24 + CDC_Handle->pTxData += CDC_Handle->DataItf.OutEpSize; + 8008516: 68fb ldr r3, [r7, #12] + 8008518: 69db ldr r3, [r3, #28] + 800851a: 68fa ldr r2, [r7, #12] + 800851c: 8b12 ldrh r2, [r2, #24] + 800851e: 441a add r2, r3 + 8008520: 68fb ldr r3, [r7, #12] + 8008522: 61da str r2, [r3, #28] + 8008524: e002 b.n 800852c + CDC_Handle->TxDataLength = 0U; + 8008526: 68fb ldr r3, [r7, #12] + 8008528: 2200 movs r2, #0 + 800852a: 625a str r2, [r3, #36] ; 0x24 + if (CDC_Handle->TxDataLength > 0U) + 800852c: 68fb ldr r3, [r7, #12] + 800852e: 6a5b ldr r3, [r3, #36] ; 0x24 + 8008530: 2b00 cmp r3, #0 + 8008532: d004 beq.n 800853e + CDC_Handle->data_tx_state = CDC_SEND_DATA; + 8008534: 68fb ldr r3, [r7, #12] + 8008536: 2201 movs r2, #1 + 8008538: f883 204d strb.w r2, [r3, #77] ; 0x4d + break; + 800853c: e00e b.n 800855c + CDC_Handle->data_tx_state = CDC_IDLE; + 800853e: 68fb ldr r3, [r7, #12] + 8008540: 2200 movs r2, #0 + 8008542: f883 204d strb.w r2, [r3, #77] ; 0x4d + USBH_CDC_TransmitCallback(phost); + 8008546: 6878 ldr r0, [r7, #4] + 8008548: f000 f868 bl 800861c + break; + 800854c: e006 b.n 800855c + if (URB_Status == USBH_URB_NOTREADY) + 800854e: 7afb ldrb r3, [r7, #11] + 8008550: 2b02 cmp r3, #2 + 8008552: d103 bne.n 800855c + CDC_Handle->data_tx_state = CDC_SEND_DATA; + 8008554: 68fb ldr r3, [r7, #12] + 8008556: 2201 movs r2, #1 + 8008558: f883 204d strb.w r2, [r3, #77] ; 0x4d + break; + 800855c: bf00 nop + } +} + 800855e: bf00 nop + 8008560: 3710 adds r7, #16 + 8008562: 46bd mov sp, r7 + 8008564: bd80 pop {r7, pc} + +08008566 : +* @param pdev: Selected device +* @retval None +*/ + +static void CDC_ProcessReception(USBH_HandleTypeDef *phost) +{ + 8008566: b580 push {r7, lr} + 8008568: b086 sub sp, #24 + 800856a: af00 add r7, sp, #0 + 800856c: 6078 str r0, [r7, #4] + CDC_HandleTypeDef *CDC_Handle = (CDC_HandleTypeDef *) phost->pActiveClass->pData; + 800856e: 687b ldr r3, [r7, #4] + 8008570: f8d3 337c ldr.w r3, [r3, #892] ; 0x37c + 8008574: 69db ldr r3, [r3, #28] + 8008576: 617b str r3, [r7, #20] + USBH_URBStateTypeDef URB_Status = USBH_URB_IDLE; + 8008578: 2300 movs r3, #0 + 800857a: 74fb strb r3, [r7, #19] + uint32_t length; + + switch (CDC_Handle->data_rx_state) + 800857c: 697b ldr r3, [r7, #20] + 800857e: f893 304e ldrb.w r3, [r3, #78] ; 0x4e + 8008582: 2b03 cmp r3, #3 + 8008584: d002 beq.n 800858c + 8008586: 2b04 cmp r3, #4 + 8008588: d00e beq.n 80085a8 +#endif + } + break; + + default: + break; + 800858a: e043 b.n 8008614 + USBH_BulkReceiveData(phost, + 800858c: 697b ldr r3, [r7, #20] + 800858e: 6a19 ldr r1, [r3, #32] + 8008590: 697b ldr r3, [r7, #20] + 8008592: 8b5a ldrh r2, [r3, #26] + 8008594: 697b ldr r3, [r7, #20] + 8008596: 7b1b ldrb r3, [r3, #12] + 8008598: 6878 ldr r0, [r7, #4] + 800859a: f001 fb07 bl 8009bac + CDC_Handle->data_rx_state = CDC_RECEIVE_DATA_WAIT; + 800859e: 697b ldr r3, [r7, #20] + 80085a0: 2204 movs r2, #4 + 80085a2: f883 204e strb.w r2, [r3, #78] ; 0x4e + break; + 80085a6: e035 b.n 8008614 + URB_Status = USBH_LL_GetURBState(phost, CDC_Handle->DataItf.InPipe); + 80085a8: 697b ldr r3, [r7, #20] + 80085aa: 7b1b ldrb r3, [r3, #12] + 80085ac: 4619 mov r1, r3 + 80085ae: 6878 ldr r0, [r7, #4] + 80085b0: f001 fe04 bl 800a1bc + 80085b4: 4603 mov r3, r0 + 80085b6: 74fb strb r3, [r7, #19] + if (URB_Status == USBH_URB_DONE) + 80085b8: 7cfb ldrb r3, [r7, #19] + 80085ba: 2b01 cmp r3, #1 + 80085bc: d129 bne.n 8008612 + length = USBH_LL_GetLastXferSize(phost, CDC_Handle->DataItf.InPipe); + 80085be: 697b ldr r3, [r7, #20] + 80085c0: 7b1b ldrb r3, [r3, #12] + 80085c2: 4619 mov r1, r3 + 80085c4: 6878 ldr r0, [r7, #4] + 80085c6: f001 fd67 bl 800a098 + 80085ca: 60f8 str r0, [r7, #12] + if (((CDC_Handle->RxDataLength - length) > 0U) && (length > CDC_Handle->DataItf.InEpSize)) + 80085cc: 697b ldr r3, [r7, #20] + 80085ce: 6a9b ldr r3, [r3, #40] ; 0x28 + 80085d0: 68fa ldr r2, [r7, #12] + 80085d2: 429a cmp r2, r3 + 80085d4: d016 beq.n 8008604 + 80085d6: 697b ldr r3, [r7, #20] + 80085d8: 8b5b ldrh r3, [r3, #26] + 80085da: 461a mov r2, r3 + 80085dc: 68fb ldr r3, [r7, #12] + 80085de: 4293 cmp r3, r2 + 80085e0: d910 bls.n 8008604 + CDC_Handle->RxDataLength -= length ; + 80085e2: 697b ldr r3, [r7, #20] + 80085e4: 6a9a ldr r2, [r3, #40] ; 0x28 + 80085e6: 68fb ldr r3, [r7, #12] + 80085e8: 1ad2 subs r2, r2, r3 + 80085ea: 697b ldr r3, [r7, #20] + 80085ec: 629a str r2, [r3, #40] ; 0x28 + CDC_Handle->pRxData += length; + 80085ee: 697b ldr r3, [r7, #20] + 80085f0: 6a1a ldr r2, [r3, #32] + 80085f2: 68fb ldr r3, [r7, #12] + 80085f4: 441a add r2, r3 + 80085f6: 697b ldr r3, [r7, #20] + 80085f8: 621a str r2, [r3, #32] + CDC_Handle->data_rx_state = CDC_RECEIVE_DATA; + 80085fa: 697b ldr r3, [r7, #20] + 80085fc: 2203 movs r2, #3 + 80085fe: f883 204e strb.w r2, [r3, #78] ; 0x4e + break; + 8008602: e006 b.n 8008612 + CDC_Handle->data_rx_state = CDC_IDLE; + 8008604: 697b ldr r3, [r7, #20] + 8008606: 2200 movs r2, #0 + 8008608: f883 204e strb.w r2, [r3, #78] ; 0x4e + USBH_CDC_ReceiveCallback(phost); + 800860c: 6878 ldr r0, [r7, #4] + 800860e: f000 f80f bl 8008630 + break; + 8008612: bf00 nop + } +} + 8008614: bf00 nop + 8008616: 3718 adds r7, #24 + 8008618: 46bd mov sp, r7 + 800861a: bd80 pop {r7, pc} + +0800861c : +* @brief The function informs user that data have been received +* @param pdev: Selected device +* @retval None +*/ +__weak void USBH_CDC_TransmitCallback(USBH_HandleTypeDef *phost) +{ + 800861c: b480 push {r7} + 800861e: b083 sub sp, #12 + 8008620: af00 add r7, sp, #0 + 8008622: 6078 str r0, [r7, #4] + /* Prevent unused argument(s) compilation warning */ + UNUSED(phost); +} + 8008624: bf00 nop + 8008626: 370c adds r7, #12 + 8008628: 46bd mov sp, r7 + 800862a: f85d 7b04 ldr.w r7, [sp], #4 + 800862e: 4770 bx lr + +08008630 : +* @brief The function informs user that data have been sent +* @param pdev: Selected device +* @retval None +*/ +__weak void USBH_CDC_ReceiveCallback(USBH_HandleTypeDef *phost) +{ + 8008630: b480 push {r7} + 8008632: b083 sub sp, #12 + 8008634: af00 add r7, sp, #0 + 8008636: 6078 str r0, [r7, #4] + /* Prevent unused argument(s) compilation warning */ + UNUSED(phost); +} + 8008638: bf00 nop + 800863a: 370c adds r7, #12 + 800863c: 46bd mov sp, r7 + 800863e: f85d 7b04 ldr.w r7, [sp], #4 + 8008642: 4770 bx lr + +08008644 : +* @brief The function informs user that Settings have been changed +* @param pdev: Selected device +* @retval None +*/ +__weak void USBH_CDC_LineCodingChanged(USBH_HandleTypeDef *phost) +{ + 8008644: b480 push {r7} + 8008646: b083 sub sp, #12 + 8008648: af00 add r7, sp, #0 + 800864a: 6078 str r0, [r7, #4] + /* Prevent unused argument(s) compilation warning */ + UNUSED(phost); +} + 800864c: bf00 nop + 800864e: 370c adds r7, #12 + 8008650: 46bd mov sp, r7 + 8008652: f85d 7b04 ldr.w r7, [sp], #4 + 8008656: 4770 bx lr + +08008658 : + * @retval USBH Status + */ +USBH_StatusTypeDef USBH_Init(USBH_HandleTypeDef *phost, + void (*pUsrFunc)(USBH_HandleTypeDef *phost, + uint8_t id), uint8_t id) +{ + 8008658: b580 push {r7, lr} + 800865a: b084 sub sp, #16 + 800865c: af00 add r7, sp, #0 + 800865e: 60f8 str r0, [r7, #12] + 8008660: 60b9 str r1, [r7, #8] + 8008662: 4613 mov r3, r2 + 8008664: 71fb strb r3, [r7, #7] + /* Check whether the USB Host handle is valid */ + if (phost == NULL) + 8008666: 68fb ldr r3, [r7, #12] + 8008668: 2b00 cmp r3, #0 + 800866a: d101 bne.n 8008670 + { + USBH_ErrLog("Invalid Host handle"); + return USBH_FAIL; + 800866c: 2302 movs r3, #2 + 800866e: e029 b.n 80086c4 + } + + /* Set DRiver ID */ + phost->id = id; + 8008670: 68fb ldr r3, [r7, #12] + 8008672: 79fa ldrb r2, [r7, #7] + 8008674: f883 23cc strb.w r2, [r3, #972] ; 0x3cc + + /* Unlink class*/ + phost->pActiveClass = NULL; + 8008678: 68fb ldr r3, [r7, #12] + 800867a: 2200 movs r2, #0 + 800867c: f8c3 237c str.w r2, [r3, #892] ; 0x37c + phost->ClassNumber = 0U; + 8008680: 68fb ldr r3, [r7, #12] + 8008682: 2200 movs r2, #0 + 8008684: f8c3 2380 str.w r2, [r3, #896] ; 0x380 + + /* Restore default states and prepare EP0 */ + DeInitStateMachine(phost); + 8008688: 68f8 ldr r0, [r7, #12] + 800868a: f000 f81f bl 80086cc + + /* Restore default Device connection states */ + phost->device.PortEnabled = 0U; + 800868e: 68fb ldr r3, [r7, #12] + 8008690: 2200 movs r2, #0 + 8008692: f883 2323 strb.w r2, [r3, #803] ; 0x323 + phost->device.is_connected = 0U; + 8008696: 68fb ldr r3, [r7, #12] + 8008698: 2200 movs r2, #0 + 800869a: f883 2320 strb.w r2, [r3, #800] ; 0x320 + phost->device.is_disconnected = 0U; + 800869e: 68fb ldr r3, [r7, #12] + 80086a0: 2200 movs r2, #0 + 80086a2: f883 2321 strb.w r2, [r3, #801] ; 0x321 + phost->device.is_ReEnumerated = 0U; + 80086a6: 68fb ldr r3, [r7, #12] + 80086a8: 2200 movs r2, #0 + 80086aa: f883 2322 strb.w r2, [r3, #802] ; 0x322 + + /* Assign User process */ + if (pUsrFunc != NULL) + 80086ae: 68bb ldr r3, [r7, #8] + 80086b0: 2b00 cmp r3, #0 + 80086b2: d003 beq.n 80086bc + { + phost->pUser = pUsrFunc; + 80086b4: 68fb ldr r3, [r7, #12] + 80086b6: 68ba ldr r2, [r7, #8] + 80086b8: f8c3 23d4 str.w r2, [r3, #980] ; 0x3d4 + +#endif /* (osCMSIS < 0x20000U) */ +#endif /* (USBH_USE_OS == 1U) */ + + /* Initialize low level driver */ + USBH_LL_Init(phost); + 80086bc: 68f8 ldr r0, [r7, #12] + 80086be: f001 fc39 bl 8009f34 + + return USBH_OK; + 80086c2: 2300 movs r3, #0 +} + 80086c4: 4618 mov r0, r3 + 80086c6: 3710 adds r7, #16 + 80086c8: 46bd mov sp, r7 + 80086ca: bd80 pop {r7, pc} + +080086cc : + * De-Initialize the Host state machine. + * @param phost: Host Handle + * @retval USBH Status + */ +static USBH_StatusTypeDef DeInitStateMachine(USBH_HandleTypeDef *phost) +{ + 80086cc: b480 push {r7} + 80086ce: b085 sub sp, #20 + 80086d0: af00 add r7, sp, #0 + 80086d2: 6078 str r0, [r7, #4] + uint32_t i = 0U; + 80086d4: 2300 movs r3, #0 + 80086d6: 60fb str r3, [r7, #12] + + /* Clear Pipes flags*/ + for (i = 0U; i < USBH_MAX_PIPES_NBR; i++) + 80086d8: 2300 movs r3, #0 + 80086da: 60fb str r3, [r7, #12] + 80086dc: e009 b.n 80086f2 + { + phost->Pipes[i] = 0U; + 80086de: 687a ldr r2, [r7, #4] + 80086e0: 68fb ldr r3, [r7, #12] + 80086e2: 33e0 adds r3, #224 ; 0xe0 + 80086e4: 009b lsls r3, r3, #2 + 80086e6: 4413 add r3, r2 + 80086e8: 2200 movs r2, #0 + 80086ea: 605a str r2, [r3, #4] + for (i = 0U; i < USBH_MAX_PIPES_NBR; i++) + 80086ec: 68fb ldr r3, [r7, #12] + 80086ee: 3301 adds r3, #1 + 80086f0: 60fb str r3, [r7, #12] + 80086f2: 68fb ldr r3, [r7, #12] + 80086f4: 2b0e cmp r3, #14 + 80086f6: d9f2 bls.n 80086de + } + + for (i = 0U; i < USBH_MAX_DATA_BUFFER; i++) + 80086f8: 2300 movs r3, #0 + 80086fa: 60fb str r3, [r7, #12] + 80086fc: e009 b.n 8008712 + { + phost->device.Data[i] = 0U; + 80086fe: 687a ldr r2, [r7, #4] + 8008700: 68fb ldr r3, [r7, #12] + 8008702: 4413 add r3, r2 + 8008704: f503 738e add.w r3, r3, #284 ; 0x11c + 8008708: 2200 movs r2, #0 + 800870a: 701a strb r2, [r3, #0] + for (i = 0U; i < USBH_MAX_DATA_BUFFER; i++) + 800870c: 68fb ldr r3, [r7, #12] + 800870e: 3301 adds r3, #1 + 8008710: 60fb str r3, [r7, #12] + 8008712: 68fb ldr r3, [r7, #12] + 8008714: f5b3 7f00 cmp.w r3, #512 ; 0x200 + 8008718: d3f1 bcc.n 80086fe + } + + phost->gState = HOST_IDLE; + 800871a: 687b ldr r3, [r7, #4] + 800871c: 2200 movs r2, #0 + 800871e: 701a strb r2, [r3, #0] + phost->EnumState = ENUM_IDLE; + 8008720: 687b ldr r3, [r7, #4] + 8008722: 2200 movs r2, #0 + 8008724: 705a strb r2, [r3, #1] + phost->RequestState = CMD_SEND; + 8008726: 687b ldr r3, [r7, #4] + 8008728: 2201 movs r2, #1 + 800872a: 709a strb r2, [r3, #2] + phost->Timer = 0U; + 800872c: 687b ldr r3, [r7, #4] + 800872e: 2200 movs r2, #0 + 8008730: f8c3 23c4 str.w r2, [r3, #964] ; 0x3c4 + + phost->Control.state = CTRL_SETUP; + 8008734: 687b ldr r3, [r7, #4] + 8008736: 2201 movs r2, #1 + 8008738: 761a strb r2, [r3, #24] + phost->Control.pipe_size = USBH_MPS_DEFAULT; + 800873a: 687b ldr r3, [r7, #4] + 800873c: 2240 movs r2, #64 ; 0x40 + 800873e: 719a strb r2, [r3, #6] + phost->Control.errorcount = 0U; + 8008740: 687b ldr r3, [r7, #4] + 8008742: 2200 movs r2, #0 + 8008744: 765a strb r2, [r3, #25] + + phost->device.address = USBH_ADDRESS_DEFAULT; + 8008746: 687b ldr r3, [r7, #4] + 8008748: 2200 movs r2, #0 + 800874a: f883 231c strb.w r2, [r3, #796] ; 0x31c + phost->device.speed = USBH_SPEED_FULL; + 800874e: 687b ldr r3, [r7, #4] + 8008750: 2201 movs r2, #1 + 8008752: f883 231d strb.w r2, [r3, #797] ; 0x31d + phost->device.RstCnt = 0U; + 8008756: 687b ldr r3, [r7, #4] + 8008758: 2200 movs r2, #0 + 800875a: f883 231f strb.w r2, [r3, #799] ; 0x31f + phost->device.EnumCnt = 0U; + 800875e: 687b ldr r3, [r7, #4] + 8008760: 2200 movs r2, #0 + 8008762: f883 231e strb.w r2, [r3, #798] ; 0x31e + + return USBH_OK; + 8008766: 2300 movs r3, #0 +} + 8008768: 4618 mov r0, r3 + 800876a: 3714 adds r7, #20 + 800876c: 46bd mov sp, r7 + 800876e: f85d 7b04 ldr.w r7, [sp], #4 + 8008772: 4770 bx lr + +08008774 : + * @param phost : Host Handle + * @param pclass: Class handle + * @retval USBH Status + */ +USBH_StatusTypeDef USBH_RegisterClass(USBH_HandleTypeDef *phost, USBH_ClassTypeDef *pclass) +{ + 8008774: b480 push {r7} + 8008776: b085 sub sp, #20 + 8008778: af00 add r7, sp, #0 + 800877a: 6078 str r0, [r7, #4] + 800877c: 6039 str r1, [r7, #0] + USBH_StatusTypeDef status = USBH_OK; + 800877e: 2300 movs r3, #0 + 8008780: 73fb strb r3, [r7, #15] + + if (pclass != NULL) + 8008782: 683b ldr r3, [r7, #0] + 8008784: 2b00 cmp r3, #0 + 8008786: d016 beq.n 80087b6 + { + if (phost->ClassNumber < USBH_MAX_NUM_SUPPORTED_CLASS) + 8008788: 687b ldr r3, [r7, #4] + 800878a: f8d3 3380 ldr.w r3, [r3, #896] ; 0x380 + 800878e: 2b00 cmp r3, #0 + 8008790: d10e bne.n 80087b0 + { + /* link the class to the USB Host handle */ + phost->pClass[phost->ClassNumber++] = pclass; + 8008792: 687b ldr r3, [r7, #4] + 8008794: f8d3 3380 ldr.w r3, [r3, #896] ; 0x380 + 8008798: 1c59 adds r1, r3, #1 + 800879a: 687a ldr r2, [r7, #4] + 800879c: f8c2 1380 str.w r1, [r2, #896] ; 0x380 + 80087a0: 687a ldr r2, [r7, #4] + 80087a2: 33de adds r3, #222 ; 0xde + 80087a4: 6839 ldr r1, [r7, #0] + 80087a6: f842 1023 str.w r1, [r2, r3, lsl #2] + status = USBH_OK; + 80087aa: 2300 movs r3, #0 + 80087ac: 73fb strb r3, [r7, #15] + 80087ae: e004 b.n 80087ba + } + else + { + USBH_ErrLog("Max Class Number reached"); + status = USBH_FAIL; + 80087b0: 2302 movs r3, #2 + 80087b2: 73fb strb r3, [r7, #15] + 80087b4: e001 b.n 80087ba + } + } + else + { + USBH_ErrLog("Invalid Class handle"); + status = USBH_FAIL; + 80087b6: 2302 movs r3, #2 + 80087b8: 73fb strb r3, [r7, #15] + } + + return status; + 80087ba: 7bfb ldrb r3, [r7, #15] +} + 80087bc: 4618 mov r0, r3 + 80087be: 3714 adds r7, #20 + 80087c0: 46bd mov sp, r7 + 80087c2: f85d 7b04 ldr.w r7, [sp], #4 + 80087c6: 4770 bx lr + +080087c8 : + * @param phost: Host Handle + * @param interface: Interface number + * @retval USBH Status + */ +USBH_StatusTypeDef USBH_SelectInterface(USBH_HandleTypeDef *phost, uint8_t interface) +{ + 80087c8: b480 push {r7} + 80087ca: b085 sub sp, #20 + 80087cc: af00 add r7, sp, #0 + 80087ce: 6078 str r0, [r7, #4] + 80087d0: 460b mov r3, r1 + 80087d2: 70fb strb r3, [r7, #3] + USBH_StatusTypeDef status = USBH_OK; + 80087d4: 2300 movs r3, #0 + 80087d6: 73fb strb r3, [r7, #15] + + if (interface < phost->device.CfgDesc.bNumInterfaces) + 80087d8: 687b ldr r3, [r7, #4] + 80087da: f893 333c ldrb.w r3, [r3, #828] ; 0x33c + 80087de: 78fa ldrb r2, [r7, #3] + 80087e0: 429a cmp r2, r3 + 80087e2: d204 bcs.n 80087ee + { + phost->device.current_interface = interface; + 80087e4: 687b ldr r3, [r7, #4] + 80087e6: 78fa ldrb r2, [r7, #3] + 80087e8: f883 2324 strb.w r2, [r3, #804] ; 0x324 + 80087ec: e001 b.n 80087f2 + USBH_UsrLog("Protocol : %xh", phost->device.CfgDesc.Itf_Desc[interface].bInterfaceProtocol); + } + else + { + USBH_ErrLog("Cannot Select This Interface."); + status = USBH_FAIL; + 80087ee: 2302 movs r3, #2 + 80087f0: 73fb strb r3, [r7, #15] + } + + return status; + 80087f2: 7bfb ldrb r3, [r7, #15] +} + 80087f4: 4618 mov r0, r3 + 80087f6: 3714 adds r7, #20 + 80087f8: 46bd mov sp, r7 + 80087fa: f85d 7b04 ldr.w r7, [sp], #4 + 80087fe: 4770 bx lr + +08008800 : + * @param Protocol: Protocol code + * @retval interface index in the configuration structure + * @note : (1)interface index 0xFF means interface index not found + */ +uint8_t USBH_FindInterface(USBH_HandleTypeDef *phost, uint8_t Class, uint8_t SubClass, uint8_t Protocol) +{ + 8008800: b480 push {r7} + 8008802: b087 sub sp, #28 + 8008804: af00 add r7, sp, #0 + 8008806: 6078 str r0, [r7, #4] + 8008808: 4608 mov r0, r1 + 800880a: 4611 mov r1, r2 + 800880c: 461a mov r2, r3 + 800880e: 4603 mov r3, r0 + 8008810: 70fb strb r3, [r7, #3] + 8008812: 460b mov r3, r1 + 8008814: 70bb strb r3, [r7, #2] + 8008816: 4613 mov r3, r2 + 8008818: 707b strb r3, [r7, #1] + USBH_InterfaceDescTypeDef *pif; + USBH_CfgDescTypeDef *pcfg; + uint8_t if_ix = 0U; + 800881a: 2300 movs r3, #0 + 800881c: 75fb strb r3, [r7, #23] + + pif = (USBH_InterfaceDescTypeDef *)0; + 800881e: 2300 movs r3, #0 + 8008820: 613b str r3, [r7, #16] + pcfg = &phost->device.CfgDesc; + 8008822: 687b ldr r3, [r7, #4] + 8008824: f503 734e add.w r3, r3, #824 ; 0x338 + 8008828: 60fb str r3, [r7, #12] + + while (if_ix < USBH_MAX_NUM_INTERFACES) + 800882a: e025 b.n 8008878 + { + pif = &pcfg->Itf_Desc[if_ix]; + 800882c: 7dfb ldrb r3, [r7, #23] + 800882e: 221a movs r2, #26 + 8008830: fb02 f303 mul.w r3, r2, r3 + 8008834: 3308 adds r3, #8 + 8008836: 68fa ldr r2, [r7, #12] + 8008838: 4413 add r3, r2 + 800883a: 3302 adds r3, #2 + 800883c: 613b str r3, [r7, #16] + if (((pif->bInterfaceClass == Class) || (Class == 0xFFU)) && + 800883e: 693b ldr r3, [r7, #16] + 8008840: 795b ldrb r3, [r3, #5] + 8008842: 78fa ldrb r2, [r7, #3] + 8008844: 429a cmp r2, r3 + 8008846: d002 beq.n 800884e + 8008848: 78fb ldrb r3, [r7, #3] + 800884a: 2bff cmp r3, #255 ; 0xff + 800884c: d111 bne.n 8008872 + ((pif->bInterfaceSubClass == SubClass) || (SubClass == 0xFFU)) && + 800884e: 693b ldr r3, [r7, #16] + 8008850: 799b ldrb r3, [r3, #6] + if (((pif->bInterfaceClass == Class) || (Class == 0xFFU)) && + 8008852: 78ba ldrb r2, [r7, #2] + 8008854: 429a cmp r2, r3 + 8008856: d002 beq.n 800885e + ((pif->bInterfaceSubClass == SubClass) || (SubClass == 0xFFU)) && + 8008858: 78bb ldrb r3, [r7, #2] + 800885a: 2bff cmp r3, #255 ; 0xff + 800885c: d109 bne.n 8008872 + ((pif->bInterfaceProtocol == Protocol) || (Protocol == 0xFFU))) + 800885e: 693b ldr r3, [r7, #16] + 8008860: 79db ldrb r3, [r3, #7] + ((pif->bInterfaceSubClass == SubClass) || (SubClass == 0xFFU)) && + 8008862: 787a ldrb r2, [r7, #1] + 8008864: 429a cmp r2, r3 + 8008866: d002 beq.n 800886e + ((pif->bInterfaceProtocol == Protocol) || (Protocol == 0xFFU))) + 8008868: 787b ldrb r3, [r7, #1] + 800886a: 2bff cmp r3, #255 ; 0xff + 800886c: d101 bne.n 8008872 + { + return if_ix; + 800886e: 7dfb ldrb r3, [r7, #23] + 8008870: e006 b.n 8008880 + } + if_ix++; + 8008872: 7dfb ldrb r3, [r7, #23] + 8008874: 3301 adds r3, #1 + 8008876: 75fb strb r3, [r7, #23] + while (if_ix < USBH_MAX_NUM_INTERFACES) + 8008878: 7dfb ldrb r3, [r7, #23] + 800887a: 2b01 cmp r3, #1 + 800887c: d9d6 bls.n 800882c + } + return 0xFFU; + 800887e: 23ff movs r3, #255 ; 0xff +} + 8008880: 4618 mov r0, r3 + 8008882: 371c adds r7, #28 + 8008884: 46bd mov sp, r7 + 8008886: f85d 7b04 ldr.w r7, [sp], #4 + 800888a: 4770 bx lr + +0800888c : + * Start the USB Host Core. + * @param phost: Host Handle + * @retval USBH Status + */ +USBH_StatusTypeDef USBH_Start(USBH_HandleTypeDef *phost) +{ + 800888c: b580 push {r7, lr} + 800888e: b082 sub sp, #8 + 8008890: af00 add r7, sp, #0 + 8008892: 6078 str r0, [r7, #4] + /* Start the low level driver */ + USBH_LL_Start(phost); + 8008894: 6878 ldr r0, [r7, #4] + 8008896: f001 fb89 bl 8009fac + + /* Activate VBUS on the port */ + USBH_LL_DriverVBUS(phost, TRUE); + 800889a: 2101 movs r1, #1 + 800889c: 6878 ldr r0, [r7, #4] + 800889e: f001 fca0 bl 800a1e2 + + return USBH_OK; + 80088a2: 2300 movs r3, #0 +} + 80088a4: 4618 mov r0, r3 + 80088a6: 3708 adds r7, #8 + 80088a8: 46bd mov sp, r7 + 80088aa: bd80 pop {r7, pc} + +080088ac : + * Background process of the USB Core. + * @param phost: Host Handle + * @retval USBH Status + */ +USBH_StatusTypeDef USBH_Process(USBH_HandleTypeDef *phost) +{ + 80088ac: b580 push {r7, lr} + 80088ae: b088 sub sp, #32 + 80088b0: af04 add r7, sp, #16 + 80088b2: 6078 str r0, [r7, #4] + __IO USBH_StatusTypeDef status = USBH_FAIL; + 80088b4: 2302 movs r3, #2 + 80088b6: 73bb strb r3, [r7, #14] + uint8_t idx = 0U; + 80088b8: 2300 movs r3, #0 + 80088ba: 73fb strb r3, [r7, #15] + + /* check for Host pending port disconnect event */ + if (phost->device.is_disconnected == 1U) + 80088bc: 687b ldr r3, [r7, #4] + 80088be: f893 3321 ldrb.w r3, [r3, #801] ; 0x321 + 80088c2: b2db uxtb r3, r3 + 80088c4: 2b01 cmp r3, #1 + 80088c6: d102 bne.n 80088ce + { + phost->gState = HOST_DEV_DISCONNECTED; + 80088c8: 687b ldr r3, [r7, #4] + 80088ca: 2203 movs r2, #3 + 80088cc: 701a strb r2, [r3, #0] + } + + switch (phost->gState) + 80088ce: 687b ldr r3, [r7, #4] + 80088d0: 781b ldrb r3, [r3, #0] + 80088d2: b2db uxtb r3, r3 + 80088d4: 2b0b cmp r3, #11 + 80088d6: f200 81b3 bhi.w 8008c40 + 80088da: a201 add r2, pc, #4 ; (adr r2, 80088e0 ) + 80088dc: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 80088e0: 08008911 .word 0x08008911 + 80088e4: 08008943 .word 0x08008943 + 80088e8: 080089ab .word 0x080089ab + 80088ec: 08008bdb .word 0x08008bdb + 80088f0: 08008c41 .word 0x08008c41 + 80088f4: 08008a4f .word 0x08008a4f + 80088f8: 08008b81 .word 0x08008b81 + 80088fc: 08008a85 .word 0x08008a85 + 8008900: 08008aa5 .word 0x08008aa5 + 8008904: 08008ac5 .word 0x08008ac5 + 8008908: 08008af3 .word 0x08008af3 + 800890c: 08008bc3 .word 0x08008bc3 + { + case HOST_IDLE : + + if (phost->device.is_connected) + 8008910: 687b ldr r3, [r7, #4] + 8008912: f893 3320 ldrb.w r3, [r3, #800] ; 0x320 + 8008916: b2db uxtb r3, r3 + 8008918: 2b00 cmp r3, #0 + 800891a: f000 8193 beq.w 8008c44 + { + USBH_UsrLog("USB Device Connected"); + + /* Wait for 200 ms after connection */ + phost->gState = HOST_DEV_WAIT_FOR_ATTACHMENT; + 800891e: 687b ldr r3, [r7, #4] + 8008920: 2201 movs r2, #1 + 8008922: 701a strb r2, [r3, #0] + USBH_Delay(200U); + 8008924: 20c8 movs r0, #200 ; 0xc8 + 8008926: f001 fca6 bl 800a276 + USBH_LL_ResetPort(phost); + 800892a: 6878 ldr r0, [r7, #4] + 800892c: f001 fb99 bl 800a062 + + /* Make sure to start with Default address */ + phost->device.address = USBH_ADDRESS_DEFAULT; + 8008930: 687b ldr r3, [r7, #4] + 8008932: 2200 movs r2, #0 + 8008934: f883 231c strb.w r2, [r3, #796] ; 0x31c + phost->Timeout = 0U; + 8008938: 687b ldr r3, [r7, #4] + 800893a: 2200 movs r2, #0 + 800893c: f8c3 23c8 str.w r2, [r3, #968] ; 0x3c8 +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + } + break; + 8008940: e180 b.n 8008c44 + + case HOST_DEV_WAIT_FOR_ATTACHMENT: /* Wait for Port Enabled */ + + if (phost->device.PortEnabled == 1U) + 8008942: 687b ldr r3, [r7, #4] + 8008944: f893 3323 ldrb.w r3, [r3, #803] ; 0x323 + 8008948: 2b01 cmp r3, #1 + 800894a: d107 bne.n 800895c + { + USBH_UsrLog("USB Device Reset Completed"); + phost->device.RstCnt = 0U; + 800894c: 687b ldr r3, [r7, #4] + 800894e: 2200 movs r2, #0 + 8008950: f883 231f strb.w r2, [r3, #799] ; 0x31f + phost->gState = HOST_DEV_ATTACHED; + 8008954: 687b ldr r3, [r7, #4] + 8008956: 2202 movs r2, #2 + 8008958: 701a strb r2, [r3, #0] + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + break; + 800895a: e182 b.n 8008c62 + if (phost->Timeout > USBH_DEV_RESET_TIMEOUT) + 800895c: 687b ldr r3, [r7, #4] + 800895e: f8d3 33c8 ldr.w r3, [r3, #968] ; 0x3c8 + 8008962: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 + 8008966: d914 bls.n 8008992 + phost->device.RstCnt++; + 8008968: 687b ldr r3, [r7, #4] + 800896a: f893 331f ldrb.w r3, [r3, #799] ; 0x31f + 800896e: 3301 adds r3, #1 + 8008970: b2da uxtb r2, r3 + 8008972: 687b ldr r3, [r7, #4] + 8008974: f883 231f strb.w r2, [r3, #799] ; 0x31f + if (phost->device.RstCnt > 3U) + 8008978: 687b ldr r3, [r7, #4] + 800897a: f893 331f ldrb.w r3, [r3, #799] ; 0x31f + 800897e: 2b03 cmp r3, #3 + 8008980: d903 bls.n 800898a + phost->gState = HOST_ABORT_STATE; + 8008982: 687b ldr r3, [r7, #4] + 8008984: 220d movs r2, #13 + 8008986: 701a strb r2, [r3, #0] + break; + 8008988: e16b b.n 8008c62 + phost->gState = HOST_IDLE; + 800898a: 687b ldr r3, [r7, #4] + 800898c: 2200 movs r2, #0 + 800898e: 701a strb r2, [r3, #0] + break; + 8008990: e167 b.n 8008c62 + phost->Timeout += 10U; + 8008992: 687b ldr r3, [r7, #4] + 8008994: f8d3 33c8 ldr.w r3, [r3, #968] ; 0x3c8 + 8008998: f103 020a add.w r2, r3, #10 + 800899c: 687b ldr r3, [r7, #4] + 800899e: f8c3 23c8 str.w r2, [r3, #968] ; 0x3c8 + USBH_Delay(10U); + 80089a2: 200a movs r0, #10 + 80089a4: f001 fc67 bl 800a276 + break; + 80089a8: e15b b.n 8008c62 + + case HOST_DEV_ATTACHED : + + if (phost->pUser != NULL) + 80089aa: 687b ldr r3, [r7, #4] + 80089ac: f8d3 33d4 ldr.w r3, [r3, #980] ; 0x3d4 + 80089b0: 2b00 cmp r3, #0 + 80089b2: d005 beq.n 80089c0 + { + phost->pUser(phost, HOST_USER_CONNECTION); + 80089b4: 687b ldr r3, [r7, #4] + 80089b6: f8d3 33d4 ldr.w r3, [r3, #980] ; 0x3d4 + 80089ba: 2104 movs r1, #4 + 80089bc: 6878 ldr r0, [r7, #4] + 80089be: 4798 blx r3 + } + + /* Wait for 100 ms after Reset */ + USBH_Delay(100U); + 80089c0: 2064 movs r0, #100 ; 0x64 + 80089c2: f001 fc58 bl 800a276 + + phost->device.speed = USBH_LL_GetSpeed(phost); + 80089c6: 6878 ldr r0, [r7, #4] + 80089c8: f001 fb26 bl 800a018 + 80089cc: 4603 mov r3, r0 + 80089ce: 461a mov r2, r3 + 80089d0: 687b ldr r3, [r7, #4] + 80089d2: f883 231d strb.w r2, [r3, #797] ; 0x31d + + phost->gState = HOST_ENUMERATION; + 80089d6: 687b ldr r3, [r7, #4] + 80089d8: 2205 movs r2, #5 + 80089da: 701a strb r2, [r3, #0] + + phost->Control.pipe_out = USBH_AllocPipe(phost, 0x00U); + 80089dc: 2100 movs r1, #0 + 80089de: 6878 ldr r0, [r7, #4] + 80089e0: f001 f931 bl 8009c46 + 80089e4: 4603 mov r3, r0 + 80089e6: 461a mov r2, r3 + 80089e8: 687b ldr r3, [r7, #4] + 80089ea: 715a strb r2, [r3, #5] + phost->Control.pipe_in = USBH_AllocPipe(phost, 0x80U); + 80089ec: 2180 movs r1, #128 ; 0x80 + 80089ee: 6878 ldr r0, [r7, #4] + 80089f0: f001 f929 bl 8009c46 + 80089f4: 4603 mov r3, r0 + 80089f6: 461a mov r2, r3 + 80089f8: 687b ldr r3, [r7, #4] + 80089fa: 711a strb r2, [r3, #4] + + /* Open Control pipes */ + USBH_OpenPipe(phost, phost->Control.pipe_in, 0x80U, + 80089fc: 687b ldr r3, [r7, #4] + 80089fe: 7919 ldrb r1, [r3, #4] + 8008a00: 687b ldr r3, [r7, #4] + 8008a02: f893 031c ldrb.w r0, [r3, #796] ; 0x31c + 8008a06: 687b ldr r3, [r7, #4] + 8008a08: f893 331d ldrb.w r3, [r3, #797] ; 0x31d + phost->device.address, phost->device.speed, + USBH_EP_CONTROL, (uint16_t)phost->Control.pipe_size); + 8008a0c: 687a ldr r2, [r7, #4] + 8008a0e: 7992 ldrb r2, [r2, #6] + USBH_OpenPipe(phost, phost->Control.pipe_in, 0x80U, + 8008a10: b292 uxth r2, r2 + 8008a12: 9202 str r2, [sp, #8] + 8008a14: 2200 movs r2, #0 + 8008a16: 9201 str r2, [sp, #4] + 8008a18: 9300 str r3, [sp, #0] + 8008a1a: 4603 mov r3, r0 + 8008a1c: 2280 movs r2, #128 ; 0x80 + 8008a1e: 6878 ldr r0, [r7, #4] + 8008a20: f001 f8e2 bl 8009be8 + + /* Open Control pipes */ + USBH_OpenPipe(phost, phost->Control.pipe_out, 0x00U, + 8008a24: 687b ldr r3, [r7, #4] + 8008a26: 7959 ldrb r1, [r3, #5] + 8008a28: 687b ldr r3, [r7, #4] + 8008a2a: f893 031c ldrb.w r0, [r3, #796] ; 0x31c + 8008a2e: 687b ldr r3, [r7, #4] + 8008a30: f893 331d ldrb.w r3, [r3, #797] ; 0x31d + phost->device.address, phost->device.speed, + USBH_EP_CONTROL, (uint16_t)phost->Control.pipe_size); + 8008a34: 687a ldr r2, [r7, #4] + 8008a36: 7992 ldrb r2, [r2, #6] + USBH_OpenPipe(phost, phost->Control.pipe_out, 0x00U, + 8008a38: b292 uxth r2, r2 + 8008a3a: 9202 str r2, [sp, #8] + 8008a3c: 2200 movs r2, #0 + 8008a3e: 9201 str r2, [sp, #4] + 8008a40: 9300 str r3, [sp, #0] + 8008a42: 4603 mov r3, r0 + 8008a44: 2200 movs r2, #0 + 8008a46: 6878 ldr r0, [r7, #4] + 8008a48: f001 f8ce bl 8009be8 + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + break; + 8008a4c: e109 b.n 8008c62 + + case HOST_ENUMERATION: + /* Check for enumeration status */ + status = USBH_HandleEnum(phost); + 8008a4e: 6878 ldr r0, [r7, #4] + 8008a50: f000 f90c bl 8008c6c + 8008a54: 4603 mov r3, r0 + 8008a56: 73bb strb r3, [r7, #14] + if (status == USBH_OK) + 8008a58: 7bbb ldrb r3, [r7, #14] + 8008a5a: b2db uxtb r3, r3 + 8008a5c: 2b00 cmp r3, #0 + 8008a5e: f040 80f3 bne.w 8008c48 + { + /* The function shall return USBH_OK when full enumeration is complete */ + USBH_UsrLog("Enumeration done."); + + phost->device.current_interface = 0U; + 8008a62: 687b ldr r3, [r7, #4] + 8008a64: 2200 movs r2, #0 + 8008a66: f883 2324 strb.w r2, [r3, #804] ; 0x324 + + if (phost->device.DevDesc.bNumConfigurations == 1U) + 8008a6a: 687b ldr r3, [r7, #4] + 8008a6c: f893 3337 ldrb.w r3, [r3, #823] ; 0x337 + 8008a70: 2b01 cmp r3, #1 + 8008a72: d103 bne.n 8008a7c + { + USBH_UsrLog("This device has only 1 configuration."); + phost->gState = HOST_SET_CONFIGURATION; + 8008a74: 687b ldr r3, [r7, #4] + 8008a76: 2208 movs r2, #8 + 8008a78: 701a strb r2, [r3, #0] +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + } + break; + 8008a7a: e0e5 b.n 8008c48 + phost->gState = HOST_INPUT; + 8008a7c: 687b ldr r3, [r7, #4] + 8008a7e: 2207 movs r2, #7 + 8008a80: 701a strb r2, [r3, #0] + break; + 8008a82: e0e1 b.n 8008c48 + + case HOST_INPUT: + { + /* user callback for end of device basic enumeration */ + if (phost->pUser != NULL) + 8008a84: 687b ldr r3, [r7, #4] + 8008a86: f8d3 33d4 ldr.w r3, [r3, #980] ; 0x3d4 + 8008a8a: 2b00 cmp r3, #0 + 8008a8c: f000 80de beq.w 8008c4c + { + phost->pUser(phost, HOST_USER_SELECT_CONFIGURATION); + 8008a90: 687b ldr r3, [r7, #4] + 8008a92: f8d3 33d4 ldr.w r3, [r3, #980] ; 0x3d4 + 8008a96: 2101 movs r1, #1 + 8008a98: 6878 ldr r0, [r7, #4] + 8008a9a: 4798 blx r3 + phost->gState = HOST_SET_CONFIGURATION; + 8008a9c: 687b ldr r3, [r7, #4] + 8008a9e: 2208 movs r2, #8 + 8008aa0: 701a strb r2, [r3, #0] + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + } + } + break; + 8008aa2: e0d3 b.n 8008c4c + + case HOST_SET_CONFIGURATION: + /* set configuration */ + if (USBH_SetCfg(phost, (uint16_t)phost->device.CfgDesc.bConfigurationValue) == USBH_OK) + 8008aa4: 687b ldr r3, [r7, #4] + 8008aa6: f893 333d ldrb.w r3, [r3, #829] ; 0x33d + 8008aaa: b29b uxth r3, r3 + 8008aac: 4619 mov r1, r3 + 8008aae: 6878 ldr r0, [r7, #4] + 8008ab0: f000 fc20 bl 80092f4 + 8008ab4: 4603 mov r3, r0 + 8008ab6: 2b00 cmp r3, #0 + 8008ab8: f040 80ca bne.w 8008c50 + { + phost->gState = HOST_SET_WAKEUP_FEATURE; + 8008abc: 687b ldr r3, [r7, #4] + 8008abe: 2209 movs r2, #9 + 8008ac0: 701a strb r2, [r3, #0] + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + break; + 8008ac2: e0c5 b.n 8008c50 + + case HOST_SET_WAKEUP_FEATURE: + + if ((phost->device.CfgDesc.bmAttributes) & (1U << 5)) + 8008ac4: 687b ldr r3, [r7, #4] + 8008ac6: f893 333f ldrb.w r3, [r3, #831] ; 0x33f + 8008aca: f003 0320 and.w r3, r3, #32 + 8008ace: 2b00 cmp r3, #0 + 8008ad0: d00b beq.n 8008aea + { + if (USBH_SetFeature(phost, FEATURE_SELECTOR_REMOTEWAKEUP) == USBH_OK) + 8008ad2: 2101 movs r1, #1 + 8008ad4: 6878 ldr r0, [r7, #4] + 8008ad6: f000 fc30 bl 800933a + 8008ada: 4603 mov r3, r0 + 8008adc: 2b00 cmp r3, #0 + 8008ade: f040 80b9 bne.w 8008c54 + { + USBH_UsrLog("Device remote wakeup enabled"); + phost->gState = HOST_CHECK_CLASS; + 8008ae2: 687b ldr r3, [r7, #4] + 8008ae4: 220a movs r2, #10 + 8008ae6: 701a strb r2, [r3, #0] + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + break; + 8008ae8: e0b4 b.n 8008c54 + phost->gState = HOST_CHECK_CLASS; + 8008aea: 687b ldr r3, [r7, #4] + 8008aec: 220a movs r2, #10 + 8008aee: 701a strb r2, [r3, #0] + break; + 8008af0: e0b0 b.n 8008c54 + + case HOST_CHECK_CLASS: + + if (phost->ClassNumber == 0U) + 8008af2: 687b ldr r3, [r7, #4] + 8008af4: f8d3 3380 ldr.w r3, [r3, #896] ; 0x380 + 8008af8: 2b00 cmp r3, #0 + 8008afa: f000 80ad beq.w 8008c58 + { + USBH_UsrLog("No Class has been registered."); + } + else + { + phost->pActiveClass = NULL; + 8008afe: 687b ldr r3, [r7, #4] + 8008b00: 2200 movs r2, #0 + 8008b02: f8c3 237c str.w r2, [r3, #892] ; 0x37c + + for (idx = 0U; idx < USBH_MAX_NUM_SUPPORTED_CLASS; idx++) + 8008b06: 2300 movs r3, #0 + 8008b08: 73fb strb r3, [r7, #15] + 8008b0a: e016 b.n 8008b3a + { + if (phost->pClass[idx]->ClassCode == phost->device.CfgDesc.Itf_Desc[0].bInterfaceClass) + 8008b0c: 7bfa ldrb r2, [r7, #15] + 8008b0e: 687b ldr r3, [r7, #4] + 8008b10: 32de adds r2, #222 ; 0xde + 8008b12: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8008b16: 791a ldrb r2, [r3, #4] + 8008b18: 687b ldr r3, [r7, #4] + 8008b1a: f893 3347 ldrb.w r3, [r3, #839] ; 0x347 + 8008b1e: 429a cmp r2, r3 + 8008b20: d108 bne.n 8008b34 + { + phost->pActiveClass = phost->pClass[idx]; + 8008b22: 7bfa ldrb r2, [r7, #15] + 8008b24: 687b ldr r3, [r7, #4] + 8008b26: 32de adds r2, #222 ; 0xde + 8008b28: f853 2022 ldr.w r2, [r3, r2, lsl #2] + 8008b2c: 687b ldr r3, [r7, #4] + 8008b2e: f8c3 237c str.w r2, [r3, #892] ; 0x37c + break; + 8008b32: e005 b.n 8008b40 + for (idx = 0U; idx < USBH_MAX_NUM_SUPPORTED_CLASS; idx++) + 8008b34: 7bfb ldrb r3, [r7, #15] + 8008b36: 3301 adds r3, #1 + 8008b38: 73fb strb r3, [r7, #15] + 8008b3a: 7bfb ldrb r3, [r7, #15] + 8008b3c: 2b00 cmp r3, #0 + 8008b3e: d0e5 beq.n 8008b0c + } + } + + if (phost->pActiveClass != NULL) + 8008b40: 687b ldr r3, [r7, #4] + 8008b42: f8d3 337c ldr.w r3, [r3, #892] ; 0x37c + 8008b46: 2b00 cmp r3, #0 + 8008b48: d016 beq.n 8008b78 + { + if (phost->pActiveClass->Init(phost) == USBH_OK) + 8008b4a: 687b ldr r3, [r7, #4] + 8008b4c: f8d3 337c ldr.w r3, [r3, #892] ; 0x37c + 8008b50: 689b ldr r3, [r3, #8] + 8008b52: 6878 ldr r0, [r7, #4] + 8008b54: 4798 blx r3 + 8008b56: 4603 mov r3, r0 + 8008b58: 2b00 cmp r3, #0 + 8008b5a: d109 bne.n 8008b70 + { + phost->gState = HOST_CLASS_REQUEST; + 8008b5c: 687b ldr r3, [r7, #4] + 8008b5e: 2206 movs r2, #6 + 8008b60: 701a strb r2, [r3, #0] + USBH_UsrLog("%s class started.", phost->pActiveClass->Name); + + /* Inform user that a class has been activated */ + phost->pUser(phost, HOST_USER_CLASS_SELECTED); + 8008b62: 687b ldr r3, [r7, #4] + 8008b64: f8d3 33d4 ldr.w r3, [r3, #980] ; 0x3d4 + 8008b68: 2103 movs r1, #3 + 8008b6a: 6878 ldr r0, [r7, #4] + 8008b6c: 4798 blx r3 + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + break; + 8008b6e: e073 b.n 8008c58 + phost->gState = HOST_ABORT_STATE; + 8008b70: 687b ldr r3, [r7, #4] + 8008b72: 220d movs r2, #13 + 8008b74: 701a strb r2, [r3, #0] + break; + 8008b76: e06f b.n 8008c58 + phost->gState = HOST_ABORT_STATE; + 8008b78: 687b ldr r3, [r7, #4] + 8008b7a: 220d movs r2, #13 + 8008b7c: 701a strb r2, [r3, #0] + break; + 8008b7e: e06b b.n 8008c58 + + case HOST_CLASS_REQUEST: + /* process class standard control requests state machine */ + if (phost->pActiveClass != NULL) + 8008b80: 687b ldr r3, [r7, #4] + 8008b82: f8d3 337c ldr.w r3, [r3, #892] ; 0x37c + 8008b86: 2b00 cmp r3, #0 + 8008b88: d017 beq.n 8008bba + { + status = phost->pActiveClass->Requests(phost); + 8008b8a: 687b ldr r3, [r7, #4] + 8008b8c: f8d3 337c ldr.w r3, [r3, #892] ; 0x37c + 8008b90: 691b ldr r3, [r3, #16] + 8008b92: 6878 ldr r0, [r7, #4] + 8008b94: 4798 blx r3 + 8008b96: 4603 mov r3, r0 + 8008b98: 73bb strb r3, [r7, #14] + + if (status == USBH_OK) + 8008b9a: 7bbb ldrb r3, [r7, #14] + 8008b9c: b2db uxtb r3, r3 + 8008b9e: 2b00 cmp r3, #0 + 8008ba0: d103 bne.n 8008baa + { + phost->gState = HOST_CLASS; + 8008ba2: 687b ldr r3, [r7, #4] + 8008ba4: 220b movs r2, #11 + 8008ba6: 701a strb r2, [r3, #0] + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + break; + 8008ba8: e058 b.n 8008c5c + else if (status == USBH_FAIL) + 8008baa: 7bbb ldrb r3, [r7, #14] + 8008bac: b2db uxtb r3, r3 + 8008bae: 2b02 cmp r3, #2 + 8008bb0: d154 bne.n 8008c5c + phost->gState = HOST_ABORT_STATE; + 8008bb2: 687b ldr r3, [r7, #4] + 8008bb4: 220d movs r2, #13 + 8008bb6: 701a strb r2, [r3, #0] + break; + 8008bb8: e050 b.n 8008c5c + phost->gState = HOST_ABORT_STATE; + 8008bba: 687b ldr r3, [r7, #4] + 8008bbc: 220d movs r2, #13 + 8008bbe: 701a strb r2, [r3, #0] + break; + 8008bc0: e04c b.n 8008c5c + + case HOST_CLASS: + /* process class state machine */ + if (phost->pActiveClass != NULL) + 8008bc2: 687b ldr r3, [r7, #4] + 8008bc4: f8d3 337c ldr.w r3, [r3, #892] ; 0x37c + 8008bc8: 2b00 cmp r3, #0 + 8008bca: d049 beq.n 8008c60 + { + phost->pActiveClass->BgndProcess(phost); + 8008bcc: 687b ldr r3, [r7, #4] + 8008bce: f8d3 337c ldr.w r3, [r3, #892] ; 0x37c + 8008bd2: 695b ldr r3, [r3, #20] + 8008bd4: 6878 ldr r0, [r7, #4] + 8008bd6: 4798 blx r3 + } + break; + 8008bd8: e042 b.n 8008c60 + + case HOST_DEV_DISCONNECTED : + phost->device.is_disconnected = 0U; + 8008bda: 687b ldr r3, [r7, #4] + 8008bdc: 2200 movs r2, #0 + 8008bde: f883 2321 strb.w r2, [r3, #801] ; 0x321 + + DeInitStateMachine(phost); + 8008be2: 6878 ldr r0, [r7, #4] + 8008be4: f7ff fd72 bl 80086cc + + /* Re-Initilaize Host for new Enumeration */ + if (phost->pActiveClass != NULL) + 8008be8: 687b ldr r3, [r7, #4] + 8008bea: f8d3 337c ldr.w r3, [r3, #892] ; 0x37c + 8008bee: 2b00 cmp r3, #0 + 8008bf0: d009 beq.n 8008c06 + { + phost->pActiveClass->DeInit(phost); + 8008bf2: 687b ldr r3, [r7, #4] + 8008bf4: f8d3 337c ldr.w r3, [r3, #892] ; 0x37c + 8008bf8: 68db ldr r3, [r3, #12] + 8008bfa: 6878 ldr r0, [r7, #4] + 8008bfc: 4798 blx r3 + phost->pActiveClass = NULL; + 8008bfe: 687b ldr r3, [r7, #4] + 8008c00: 2200 movs r2, #0 + 8008c02: f8c3 237c str.w r2, [r3, #892] ; 0x37c + } + + if (phost->pUser != NULL) + 8008c06: 687b ldr r3, [r7, #4] + 8008c08: f8d3 33d4 ldr.w r3, [r3, #980] ; 0x3d4 + 8008c0c: 2b00 cmp r3, #0 + 8008c0e: d005 beq.n 8008c1c + { + phost->pUser(phost, HOST_USER_DISCONNECTION); + 8008c10: 687b ldr r3, [r7, #4] + 8008c12: f8d3 33d4 ldr.w r3, [r3, #980] ; 0x3d4 + 8008c16: 2105 movs r1, #5 + 8008c18: 6878 ldr r0, [r7, #4] + 8008c1a: 4798 blx r3 + } + USBH_UsrLog("USB Device disconnected"); + + if (phost->device.is_ReEnumerated == 1U) + 8008c1c: 687b ldr r3, [r7, #4] + 8008c1e: f893 3322 ldrb.w r3, [r3, #802] ; 0x322 + 8008c22: b2db uxtb r3, r3 + 8008c24: 2b01 cmp r3, #1 + 8008c26: d107 bne.n 8008c38 + { + phost->device.is_ReEnumerated = 0U; + 8008c28: 687b ldr r3, [r7, #4] + 8008c2a: 2200 movs r2, #0 + 8008c2c: f883 2322 strb.w r2, [r3, #802] ; 0x322 + + /* Start the host and re-enable Vbus */ + USBH_Start(phost); + 8008c30: 6878 ldr r0, [r7, #4] + 8008c32: f7ff fe2b bl 800888c + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + break; + 8008c36: e014 b.n 8008c62 + USBH_LL_Start(phost); + 8008c38: 6878 ldr r0, [r7, #4] + 8008c3a: f001 f9b7 bl 8009fac + break; + 8008c3e: e010 b.n 8008c62 + + case HOST_ABORT_STATE: + default : + break; + 8008c40: bf00 nop + 8008c42: e00e b.n 8008c62 + break; + 8008c44: bf00 nop + 8008c46: e00c b.n 8008c62 + break; + 8008c48: bf00 nop + 8008c4a: e00a b.n 8008c62 + break; + 8008c4c: bf00 nop + 8008c4e: e008 b.n 8008c62 + break; + 8008c50: bf00 nop + 8008c52: e006 b.n 8008c62 + break; + 8008c54: bf00 nop + 8008c56: e004 b.n 8008c62 + break; + 8008c58: bf00 nop + 8008c5a: e002 b.n 8008c62 + break; + 8008c5c: bf00 nop + 8008c5e: e000 b.n 8008c62 + break; + 8008c60: bf00 nop + } + return USBH_OK; + 8008c62: 2300 movs r3, #0 +} + 8008c64: 4618 mov r0, r3 + 8008c66: 3710 adds r7, #16 + 8008c68: 46bd mov sp, r7 + 8008c6a: bd80 pop {r7, pc} + +08008c6c : + * This function includes the complete enumeration process + * @param phost: Host Handle + * @retval USBH_Status + */ +static USBH_StatusTypeDef USBH_HandleEnum(USBH_HandleTypeDef *phost) +{ + 8008c6c: b580 push {r7, lr} + 8008c6e: b088 sub sp, #32 + 8008c70: af04 add r7, sp, #16 + 8008c72: 6078 str r0, [r7, #4] + USBH_StatusTypeDef Status = USBH_BUSY; + 8008c74: 2301 movs r3, #1 + 8008c76: 73fb strb r3, [r7, #15] + USBH_StatusTypeDef ReqStatus = USBH_BUSY; + 8008c78: 2301 movs r3, #1 + 8008c7a: 73bb strb r3, [r7, #14] + + switch (phost->EnumState) + 8008c7c: 687b ldr r3, [r7, #4] + 8008c7e: 785b ldrb r3, [r3, #1] + 8008c80: 2b07 cmp r3, #7 + 8008c82: f200 81c1 bhi.w 8009008 + 8008c86: a201 add r2, pc, #4 ; (adr r2, 8008c8c ) + 8008c88: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8008c8c: 08008cad .word 0x08008cad + 8008c90: 08008d6b .word 0x08008d6b + 8008c94: 08008dd5 .word 0x08008dd5 + 8008c98: 08008e63 .word 0x08008e63 + 8008c9c: 08008ecd .word 0x08008ecd + 8008ca0: 08008f3d .word 0x08008f3d + 8008ca4: 08008f83 .word 0x08008f83 + 8008ca8: 08008fc9 .word 0x08008fc9 + { + case ENUM_IDLE: + /* Get Device Desc for only 1st 8 bytes : To get EP0 MaxPacketSize */ + ReqStatus = USBH_Get_DevDesc(phost, 8U); + 8008cac: 2108 movs r1, #8 + 8008cae: 6878 ldr r0, [r7, #4] + 8008cb0: f000 fa50 bl 8009154 + 8008cb4: 4603 mov r3, r0 + 8008cb6: 73bb strb r3, [r7, #14] + if (ReqStatus == USBH_OK) + 8008cb8: 7bbb ldrb r3, [r7, #14] + 8008cba: 2b00 cmp r3, #0 + 8008cbc: d130 bne.n 8008d20 + { + phost->Control.pipe_size = phost->device.DevDesc.bMaxPacketSize; + 8008cbe: 687b ldr r3, [r7, #4] + 8008cc0: f893 232d ldrb.w r2, [r3, #813] ; 0x32d + 8008cc4: 687b ldr r3, [r7, #4] + 8008cc6: 719a strb r2, [r3, #6] + + phost->EnumState = ENUM_GET_FULL_DEV_DESC; + 8008cc8: 687b ldr r3, [r7, #4] + 8008cca: 2201 movs r2, #1 + 8008ccc: 705a strb r2, [r3, #1] + + /* modify control channels configuration for MaxPacket size */ + USBH_OpenPipe(phost, phost->Control.pipe_in, 0x80U, phost->device.address, + 8008cce: 687b ldr r3, [r7, #4] + 8008cd0: 7919 ldrb r1, [r3, #4] + 8008cd2: 687b ldr r3, [r7, #4] + 8008cd4: f893 031c ldrb.w r0, [r3, #796] ; 0x31c + 8008cd8: 687b ldr r3, [r7, #4] + 8008cda: f893 331d ldrb.w r3, [r3, #797] ; 0x31d + phost->device.speed, USBH_EP_CONTROL, + (uint16_t)phost->Control.pipe_size); + 8008cde: 687a ldr r2, [r7, #4] + 8008ce0: 7992 ldrb r2, [r2, #6] + USBH_OpenPipe(phost, phost->Control.pipe_in, 0x80U, phost->device.address, + 8008ce2: b292 uxth r2, r2 + 8008ce4: 9202 str r2, [sp, #8] + 8008ce6: 2200 movs r2, #0 + 8008ce8: 9201 str r2, [sp, #4] + 8008cea: 9300 str r3, [sp, #0] + 8008cec: 4603 mov r3, r0 + 8008cee: 2280 movs r2, #128 ; 0x80 + 8008cf0: 6878 ldr r0, [r7, #4] + 8008cf2: f000 ff79 bl 8009be8 + + /* Open Control pipes */ + USBH_OpenPipe(phost, phost->Control.pipe_out, 0x00U, phost->device.address, + 8008cf6: 687b ldr r3, [r7, #4] + 8008cf8: 7959 ldrb r1, [r3, #5] + 8008cfa: 687b ldr r3, [r7, #4] + 8008cfc: f893 031c ldrb.w r0, [r3, #796] ; 0x31c + 8008d00: 687b ldr r3, [r7, #4] + 8008d02: f893 331d ldrb.w r3, [r3, #797] ; 0x31d + phost->device.speed, USBH_EP_CONTROL, + (uint16_t)phost->Control.pipe_size); + 8008d06: 687a ldr r2, [r7, #4] + 8008d08: 7992 ldrb r2, [r2, #6] + USBH_OpenPipe(phost, phost->Control.pipe_out, 0x00U, phost->device.address, + 8008d0a: b292 uxth r2, r2 + 8008d0c: 9202 str r2, [sp, #8] + 8008d0e: 2200 movs r2, #0 + 8008d10: 9201 str r2, [sp, #4] + 8008d12: 9300 str r3, [sp, #0] + 8008d14: 4603 mov r3, r0 + 8008d16: 2200 movs r2, #0 + 8008d18: 6878 ldr r0, [r7, #4] + 8008d1a: f000 ff65 bl 8009be8 + } + else + { + /* .. */ + } + break; + 8008d1e: e175 b.n 800900c + else if (ReqStatus == USBH_NOT_SUPPORTED) + 8008d20: 7bbb ldrb r3, [r7, #14] + 8008d22: 2b03 cmp r3, #3 + 8008d24: f040 8172 bne.w 800900c + phost->device.EnumCnt++; + 8008d28: 687b ldr r3, [r7, #4] + 8008d2a: f893 331e ldrb.w r3, [r3, #798] ; 0x31e + 8008d2e: 3301 adds r3, #1 + 8008d30: b2da uxtb r2, r3 + 8008d32: 687b ldr r3, [r7, #4] + 8008d34: f883 231e strb.w r2, [r3, #798] ; 0x31e + if (phost->device.EnumCnt > 3U) + 8008d38: 687b ldr r3, [r7, #4] + 8008d3a: f893 331e ldrb.w r3, [r3, #798] ; 0x31e + 8008d3e: 2b03 cmp r3, #3 + 8008d40: d903 bls.n 8008d4a + phost->gState = HOST_ABORT_STATE; + 8008d42: 687b ldr r3, [r7, #4] + 8008d44: 220d movs r2, #13 + 8008d46: 701a strb r2, [r3, #0] + break; + 8008d48: e160 b.n 800900c + USBH_FreePipe(phost, phost->Control.pipe_out); + 8008d4a: 687b ldr r3, [r7, #4] + 8008d4c: 795b ldrb r3, [r3, #5] + 8008d4e: 4619 mov r1, r3 + 8008d50: 6878 ldr r0, [r7, #4] + 8008d52: f000 ff99 bl 8009c88 + USBH_FreePipe(phost, phost->Control.pipe_in); + 8008d56: 687b ldr r3, [r7, #4] + 8008d58: 791b ldrb r3, [r3, #4] + 8008d5a: 4619 mov r1, r3 + 8008d5c: 6878 ldr r0, [r7, #4] + 8008d5e: f000 ff93 bl 8009c88 + phost->gState = HOST_IDLE; + 8008d62: 687b ldr r3, [r7, #4] + 8008d64: 2200 movs r2, #0 + 8008d66: 701a strb r2, [r3, #0] + break; + 8008d68: e150 b.n 800900c + + case ENUM_GET_FULL_DEV_DESC: + /* Get FULL Device Desc */ + ReqStatus = USBH_Get_DevDesc(phost, USB_DEVICE_DESC_SIZE); + 8008d6a: 2112 movs r1, #18 + 8008d6c: 6878 ldr r0, [r7, #4] + 8008d6e: f000 f9f1 bl 8009154 + 8008d72: 4603 mov r3, r0 + 8008d74: 73bb strb r3, [r7, #14] + if (ReqStatus == USBH_OK) + 8008d76: 7bbb ldrb r3, [r7, #14] + 8008d78: 2b00 cmp r3, #0 + 8008d7a: d103 bne.n 8008d84 + { + USBH_UsrLog("PID: %xh", phost->device.DevDesc.idProduct); + USBH_UsrLog("VID: %xh", phost->device.DevDesc.idVendor); + + phost->EnumState = ENUM_SET_ADDR; + 8008d7c: 687b ldr r3, [r7, #4] + 8008d7e: 2202 movs r2, #2 + 8008d80: 705a strb r2, [r3, #1] + } + else + { + /* .. */ + } + break; + 8008d82: e145 b.n 8009010 + else if (ReqStatus == USBH_NOT_SUPPORTED) + 8008d84: 7bbb ldrb r3, [r7, #14] + 8008d86: 2b03 cmp r3, #3 + 8008d88: f040 8142 bne.w 8009010 + phost->device.EnumCnt++; + 8008d8c: 687b ldr r3, [r7, #4] + 8008d8e: f893 331e ldrb.w r3, [r3, #798] ; 0x31e + 8008d92: 3301 adds r3, #1 + 8008d94: b2da uxtb r2, r3 + 8008d96: 687b ldr r3, [r7, #4] + 8008d98: f883 231e strb.w r2, [r3, #798] ; 0x31e + if (phost->device.EnumCnt > 3U) + 8008d9c: 687b ldr r3, [r7, #4] + 8008d9e: f893 331e ldrb.w r3, [r3, #798] ; 0x31e + 8008da2: 2b03 cmp r3, #3 + 8008da4: d903 bls.n 8008dae + phost->gState = HOST_ABORT_STATE; + 8008da6: 687b ldr r3, [r7, #4] + 8008da8: 220d movs r2, #13 + 8008daa: 701a strb r2, [r3, #0] + break; + 8008dac: e130 b.n 8009010 + USBH_FreePipe(phost, phost->Control.pipe_out); + 8008dae: 687b ldr r3, [r7, #4] + 8008db0: 795b ldrb r3, [r3, #5] + 8008db2: 4619 mov r1, r3 + 8008db4: 6878 ldr r0, [r7, #4] + 8008db6: f000 ff67 bl 8009c88 + USBH_FreePipe(phost, phost->Control.pipe_in); + 8008dba: 687b ldr r3, [r7, #4] + 8008dbc: 791b ldrb r3, [r3, #4] + 8008dbe: 4619 mov r1, r3 + 8008dc0: 6878 ldr r0, [r7, #4] + 8008dc2: f000 ff61 bl 8009c88 + phost->EnumState = ENUM_IDLE; + 8008dc6: 687b ldr r3, [r7, #4] + 8008dc8: 2200 movs r2, #0 + 8008dca: 705a strb r2, [r3, #1] + phost->gState = HOST_IDLE; + 8008dcc: 687b ldr r3, [r7, #4] + 8008dce: 2200 movs r2, #0 + 8008dd0: 701a strb r2, [r3, #0] + break; + 8008dd2: e11d b.n 8009010 + + case ENUM_SET_ADDR: + /* set address */ + ReqStatus = USBH_SetAddress(phost, USBH_DEVICE_ADDRESS); + 8008dd4: 2101 movs r1, #1 + 8008dd6: 6878 ldr r0, [r7, #4] + 8008dd8: f000 fa68 bl 80092ac + 8008ddc: 4603 mov r3, r0 + 8008dde: 73bb strb r3, [r7, #14] + if (ReqStatus == USBH_OK) + 8008de0: 7bbb ldrb r3, [r7, #14] + 8008de2: 2b00 cmp r3, #0 + 8008de4: d132 bne.n 8008e4c + { + USBH_Delay(2U); + 8008de6: 2002 movs r0, #2 + 8008de8: f001 fa45 bl 800a276 + phost->device.address = USBH_DEVICE_ADDRESS; + 8008dec: 687b ldr r3, [r7, #4] + 8008dee: 2201 movs r2, #1 + 8008df0: f883 231c strb.w r2, [r3, #796] ; 0x31c + + /* user callback for device address assigned */ + USBH_UsrLog("Address (#%d) assigned.", phost->device.address); + phost->EnumState = ENUM_GET_CFG_DESC; + 8008df4: 687b ldr r3, [r7, #4] + 8008df6: 2203 movs r2, #3 + 8008df8: 705a strb r2, [r3, #1] + + /* modify control channels to update device address */ + USBH_OpenPipe(phost, phost->Control.pipe_in, 0x80U, phost->device.address, + 8008dfa: 687b ldr r3, [r7, #4] + 8008dfc: 7919 ldrb r1, [r3, #4] + 8008dfe: 687b ldr r3, [r7, #4] + 8008e00: f893 031c ldrb.w r0, [r3, #796] ; 0x31c + 8008e04: 687b ldr r3, [r7, #4] + 8008e06: f893 331d ldrb.w r3, [r3, #797] ; 0x31d + phost->device.speed, USBH_EP_CONTROL, + (uint16_t)phost->Control.pipe_size); + 8008e0a: 687a ldr r2, [r7, #4] + 8008e0c: 7992 ldrb r2, [r2, #6] + USBH_OpenPipe(phost, phost->Control.pipe_in, 0x80U, phost->device.address, + 8008e0e: b292 uxth r2, r2 + 8008e10: 9202 str r2, [sp, #8] + 8008e12: 2200 movs r2, #0 + 8008e14: 9201 str r2, [sp, #4] + 8008e16: 9300 str r3, [sp, #0] + 8008e18: 4603 mov r3, r0 + 8008e1a: 2280 movs r2, #128 ; 0x80 + 8008e1c: 6878 ldr r0, [r7, #4] + 8008e1e: f000 fee3 bl 8009be8 + + /* Open Control pipes */ + USBH_OpenPipe(phost, phost->Control.pipe_out, 0x00U, phost->device.address, + 8008e22: 687b ldr r3, [r7, #4] + 8008e24: 7959 ldrb r1, [r3, #5] + 8008e26: 687b ldr r3, [r7, #4] + 8008e28: f893 031c ldrb.w r0, [r3, #796] ; 0x31c + 8008e2c: 687b ldr r3, [r7, #4] + 8008e2e: f893 331d ldrb.w r3, [r3, #797] ; 0x31d + phost->device.speed, USBH_EP_CONTROL, + (uint16_t)phost->Control.pipe_size); + 8008e32: 687a ldr r2, [r7, #4] + 8008e34: 7992 ldrb r2, [r2, #6] + USBH_OpenPipe(phost, phost->Control.pipe_out, 0x00U, phost->device.address, + 8008e36: b292 uxth r2, r2 + 8008e38: 9202 str r2, [sp, #8] + 8008e3a: 2200 movs r2, #0 + 8008e3c: 9201 str r2, [sp, #4] + 8008e3e: 9300 str r3, [sp, #0] + 8008e40: 4603 mov r3, r0 + 8008e42: 2200 movs r2, #0 + 8008e44: 6878 ldr r0, [r7, #4] + 8008e46: f000 fecf bl 8009be8 + } + else + { + /* .. */ + } + break; + 8008e4a: e0e3 b.n 8009014 + else if (ReqStatus == USBH_NOT_SUPPORTED) + 8008e4c: 7bbb ldrb r3, [r7, #14] + 8008e4e: 2b03 cmp r3, #3 + 8008e50: f040 80e0 bne.w 8009014 + phost->gState = HOST_ABORT_STATE; + 8008e54: 687b ldr r3, [r7, #4] + 8008e56: 220d movs r2, #13 + 8008e58: 701a strb r2, [r3, #0] + phost->EnumState = ENUM_IDLE; + 8008e5a: 687b ldr r3, [r7, #4] + 8008e5c: 2200 movs r2, #0 + 8008e5e: 705a strb r2, [r3, #1] + break; + 8008e60: e0d8 b.n 8009014 + + case ENUM_GET_CFG_DESC: + /* get standard configuration descriptor */ + ReqStatus = USBH_Get_CfgDesc(phost, USB_CONFIGURATION_DESC_SIZE); + 8008e62: 2109 movs r1, #9 + 8008e64: 6878 ldr r0, [r7, #4] + 8008e66: f000 f99d bl 80091a4 + 8008e6a: 4603 mov r3, r0 + 8008e6c: 73bb strb r3, [r7, #14] + if (ReqStatus == USBH_OK) + 8008e6e: 7bbb ldrb r3, [r7, #14] + 8008e70: 2b00 cmp r3, #0 + 8008e72: d103 bne.n 8008e7c + { + phost->EnumState = ENUM_GET_FULL_CFG_DESC; + 8008e74: 687b ldr r3, [r7, #4] + 8008e76: 2204 movs r2, #4 + 8008e78: 705a strb r2, [r3, #1] + } + else + { + /* .. */ + } + break; + 8008e7a: e0cd b.n 8009018 + else if (ReqStatus == USBH_NOT_SUPPORTED) + 8008e7c: 7bbb ldrb r3, [r7, #14] + 8008e7e: 2b03 cmp r3, #3 + 8008e80: f040 80ca bne.w 8009018 + phost->device.EnumCnt++; + 8008e84: 687b ldr r3, [r7, #4] + 8008e86: f893 331e ldrb.w r3, [r3, #798] ; 0x31e + 8008e8a: 3301 adds r3, #1 + 8008e8c: b2da uxtb r2, r3 + 8008e8e: 687b ldr r3, [r7, #4] + 8008e90: f883 231e strb.w r2, [r3, #798] ; 0x31e + if (phost->device.EnumCnt > 3U) + 8008e94: 687b ldr r3, [r7, #4] + 8008e96: f893 331e ldrb.w r3, [r3, #798] ; 0x31e + 8008e9a: 2b03 cmp r3, #3 + 8008e9c: d903 bls.n 8008ea6 + phost->gState = HOST_ABORT_STATE; + 8008e9e: 687b ldr r3, [r7, #4] + 8008ea0: 220d movs r2, #13 + 8008ea2: 701a strb r2, [r3, #0] + break; + 8008ea4: e0b8 b.n 8009018 + USBH_FreePipe(phost, phost->Control.pipe_out); + 8008ea6: 687b ldr r3, [r7, #4] + 8008ea8: 795b ldrb r3, [r3, #5] + 8008eaa: 4619 mov r1, r3 + 8008eac: 6878 ldr r0, [r7, #4] + 8008eae: f000 feeb bl 8009c88 + USBH_FreePipe(phost, phost->Control.pipe_in); + 8008eb2: 687b ldr r3, [r7, #4] + 8008eb4: 791b ldrb r3, [r3, #4] + 8008eb6: 4619 mov r1, r3 + 8008eb8: 6878 ldr r0, [r7, #4] + 8008eba: f000 fee5 bl 8009c88 + phost->EnumState = ENUM_IDLE; + 8008ebe: 687b ldr r3, [r7, #4] + 8008ec0: 2200 movs r2, #0 + 8008ec2: 705a strb r2, [r3, #1] + phost->gState = HOST_IDLE; + 8008ec4: 687b ldr r3, [r7, #4] + 8008ec6: 2200 movs r2, #0 + 8008ec8: 701a strb r2, [r3, #0] + break; + 8008eca: e0a5 b.n 8009018 + + case ENUM_GET_FULL_CFG_DESC: + /* get FULL config descriptor (config, interface, endpoints) */ + ReqStatus = USBH_Get_CfgDesc(phost, phost->device.CfgDesc.wTotalLength); + 8008ecc: 687b ldr r3, [r7, #4] + 8008ece: f8b3 333a ldrh.w r3, [r3, #826] ; 0x33a + 8008ed2: 4619 mov r1, r3 + 8008ed4: 6878 ldr r0, [r7, #4] + 8008ed6: f000 f965 bl 80091a4 + 8008eda: 4603 mov r3, r0 + 8008edc: 73bb strb r3, [r7, #14] + if (ReqStatus == USBH_OK) + 8008ede: 7bbb ldrb r3, [r7, #14] + 8008ee0: 2b00 cmp r3, #0 + 8008ee2: d103 bne.n 8008eec + { + phost->EnumState = ENUM_GET_MFC_STRING_DESC; + 8008ee4: 687b ldr r3, [r7, #4] + 8008ee6: 2205 movs r2, #5 + 8008ee8: 705a strb r2, [r3, #1] + } + else + { + /* .. */ + } + break; + 8008eea: e097 b.n 800901c + else if (ReqStatus == USBH_NOT_SUPPORTED) + 8008eec: 7bbb ldrb r3, [r7, #14] + 8008eee: 2b03 cmp r3, #3 + 8008ef0: f040 8094 bne.w 800901c + phost->device.EnumCnt++; + 8008ef4: 687b ldr r3, [r7, #4] + 8008ef6: f893 331e ldrb.w r3, [r3, #798] ; 0x31e + 8008efa: 3301 adds r3, #1 + 8008efc: b2da uxtb r2, r3 + 8008efe: 687b ldr r3, [r7, #4] + 8008f00: f883 231e strb.w r2, [r3, #798] ; 0x31e + if (phost->device.EnumCnt > 3U) + 8008f04: 687b ldr r3, [r7, #4] + 8008f06: f893 331e ldrb.w r3, [r3, #798] ; 0x31e + 8008f0a: 2b03 cmp r3, #3 + 8008f0c: d903 bls.n 8008f16 + phost->gState = HOST_ABORT_STATE; + 8008f0e: 687b ldr r3, [r7, #4] + 8008f10: 220d movs r2, #13 + 8008f12: 701a strb r2, [r3, #0] + break; + 8008f14: e082 b.n 800901c + USBH_FreePipe(phost, phost->Control.pipe_out); + 8008f16: 687b ldr r3, [r7, #4] + 8008f18: 795b ldrb r3, [r3, #5] + 8008f1a: 4619 mov r1, r3 + 8008f1c: 6878 ldr r0, [r7, #4] + 8008f1e: f000 feb3 bl 8009c88 + USBH_FreePipe(phost, phost->Control.pipe_in); + 8008f22: 687b ldr r3, [r7, #4] + 8008f24: 791b ldrb r3, [r3, #4] + 8008f26: 4619 mov r1, r3 + 8008f28: 6878 ldr r0, [r7, #4] + 8008f2a: f000 fead bl 8009c88 + phost->EnumState = ENUM_IDLE; + 8008f2e: 687b ldr r3, [r7, #4] + 8008f30: 2200 movs r2, #0 + 8008f32: 705a strb r2, [r3, #1] + phost->gState = HOST_IDLE; + 8008f34: 687b ldr r3, [r7, #4] + 8008f36: 2200 movs r2, #0 + 8008f38: 701a strb r2, [r3, #0] + break; + 8008f3a: e06f b.n 800901c + + case ENUM_GET_MFC_STRING_DESC: + if (phost->device.DevDesc.iManufacturer != 0U) + 8008f3c: 687b ldr r3, [r7, #4] + 8008f3e: f893 3334 ldrb.w r3, [r3, #820] ; 0x334 + 8008f42: 2b00 cmp r3, #0 + 8008f44: d019 beq.n 8008f7a + { + /* Check that Manufacturer String is available */ + ReqStatus = USBH_Get_StringDesc(phost, phost->device.DevDesc.iManufacturer, + 8008f46: 687b ldr r3, [r7, #4] + 8008f48: f893 1334 ldrb.w r1, [r3, #820] ; 0x334 + phost->device.Data, 0xFFU); + 8008f4c: 687b ldr r3, [r7, #4] + 8008f4e: f503 728e add.w r2, r3, #284 ; 0x11c + ReqStatus = USBH_Get_StringDesc(phost, phost->device.DevDesc.iManufacturer, + 8008f52: 23ff movs r3, #255 ; 0xff + 8008f54: 6878 ldr r0, [r7, #4] + 8008f56: f000 f949 bl 80091ec + 8008f5a: 4603 mov r3, r0 + 8008f5c: 73bb strb r3, [r7, #14] + if (ReqStatus == USBH_OK) + 8008f5e: 7bbb ldrb r3, [r7, #14] + 8008f60: 2b00 cmp r3, #0 + 8008f62: d103 bne.n 8008f6c + { + /* User callback for Manufacturing string */ + USBH_UsrLog("Manufacturer : %s", (char *)(void *)phost->device.Data); + phost->EnumState = ENUM_GET_PRODUCT_STRING_DESC; + 8008f64: 687b ldr r3, [r7, #4] + 8008f66: 2206 movs r2, #6 + 8008f68: 705a strb r2, [r3, #1] +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + } + break; + 8008f6a: e059 b.n 8009020 + else if (ReqStatus == USBH_NOT_SUPPORTED) + 8008f6c: 7bbb ldrb r3, [r7, #14] + 8008f6e: 2b03 cmp r3, #3 + 8008f70: d156 bne.n 8009020 + phost->EnumState = ENUM_GET_PRODUCT_STRING_DESC; + 8008f72: 687b ldr r3, [r7, #4] + 8008f74: 2206 movs r2, #6 + 8008f76: 705a strb r2, [r3, #1] + break; + 8008f78: e052 b.n 8009020 + phost->EnumState = ENUM_GET_PRODUCT_STRING_DESC; + 8008f7a: 687b ldr r3, [r7, #4] + 8008f7c: 2206 movs r2, #6 + 8008f7e: 705a strb r2, [r3, #1] + break; + 8008f80: e04e b.n 8009020 + + case ENUM_GET_PRODUCT_STRING_DESC: + if (phost->device.DevDesc.iProduct != 0U) + 8008f82: 687b ldr r3, [r7, #4] + 8008f84: f893 3335 ldrb.w r3, [r3, #821] ; 0x335 + 8008f88: 2b00 cmp r3, #0 + 8008f8a: d019 beq.n 8008fc0 + { + /* Check that Product string is available */ + ReqStatus = USBH_Get_StringDesc(phost, phost->device.DevDesc.iProduct, + 8008f8c: 687b ldr r3, [r7, #4] + 8008f8e: f893 1335 ldrb.w r1, [r3, #821] ; 0x335 + phost->device.Data, 0xFFU); + 8008f92: 687b ldr r3, [r7, #4] + 8008f94: f503 728e add.w r2, r3, #284 ; 0x11c + ReqStatus = USBH_Get_StringDesc(phost, phost->device.DevDesc.iProduct, + 8008f98: 23ff movs r3, #255 ; 0xff + 8008f9a: 6878 ldr r0, [r7, #4] + 8008f9c: f000 f926 bl 80091ec + 8008fa0: 4603 mov r3, r0 + 8008fa2: 73bb strb r3, [r7, #14] + if (ReqStatus == USBH_OK) + 8008fa4: 7bbb ldrb r3, [r7, #14] + 8008fa6: 2b00 cmp r3, #0 + 8008fa8: d103 bne.n 8008fb2 + { + /* User callback for Product string */ + USBH_UsrLog("Product : %s", (char *)(void *)phost->device.Data); + phost->EnumState = ENUM_GET_SERIALNUM_STRING_DESC; + 8008faa: 687b ldr r3, [r7, #4] + 8008fac: 2207 movs r2, #7 + 8008fae: 705a strb r2, [r3, #1] +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + } + break; + 8008fb0: e038 b.n 8009024 + else if (ReqStatus == USBH_NOT_SUPPORTED) + 8008fb2: 7bbb ldrb r3, [r7, #14] + 8008fb4: 2b03 cmp r3, #3 + 8008fb6: d135 bne.n 8009024 + phost->EnumState = ENUM_GET_SERIALNUM_STRING_DESC; + 8008fb8: 687b ldr r3, [r7, #4] + 8008fba: 2207 movs r2, #7 + 8008fbc: 705a strb r2, [r3, #1] + break; + 8008fbe: e031 b.n 8009024 + phost->EnumState = ENUM_GET_SERIALNUM_STRING_DESC; + 8008fc0: 687b ldr r3, [r7, #4] + 8008fc2: 2207 movs r2, #7 + 8008fc4: 705a strb r2, [r3, #1] + break; + 8008fc6: e02d b.n 8009024 + + case ENUM_GET_SERIALNUM_STRING_DESC: + if (phost->device.DevDesc.iSerialNumber != 0U) + 8008fc8: 687b ldr r3, [r7, #4] + 8008fca: f893 3336 ldrb.w r3, [r3, #822] ; 0x336 + 8008fce: 2b00 cmp r3, #0 + 8008fd0: d017 beq.n 8009002 + { + /* Check that Serial number string is available */ + ReqStatus = USBH_Get_StringDesc(phost, phost->device.DevDesc.iSerialNumber, + 8008fd2: 687b ldr r3, [r7, #4] + 8008fd4: f893 1336 ldrb.w r1, [r3, #822] ; 0x336 + phost->device.Data, 0xFFU); + 8008fd8: 687b ldr r3, [r7, #4] + 8008fda: f503 728e add.w r2, r3, #284 ; 0x11c + ReqStatus = USBH_Get_StringDesc(phost, phost->device.DevDesc.iSerialNumber, + 8008fde: 23ff movs r3, #255 ; 0xff + 8008fe0: 6878 ldr r0, [r7, #4] + 8008fe2: f000 f903 bl 80091ec + 8008fe6: 4603 mov r3, r0 + 8008fe8: 73bb strb r3, [r7, #14] + if (ReqStatus == USBH_OK) + 8008fea: 7bbb ldrb r3, [r7, #14] + 8008fec: 2b00 cmp r3, #0 + 8008fee: d102 bne.n 8008ff6 + { + /* User callback for Serial number string */ + USBH_UsrLog("Serial Number : %s", (char *)(void *)phost->device.Data); + Status = USBH_OK; + 8008ff0: 2300 movs r3, #0 + 8008ff2: 73fb strb r3, [r7, #15] + else + { + USBH_UsrLog("Serial Number : N/A"); + Status = USBH_OK; + } + break; + 8008ff4: e018 b.n 8009028 + else if (ReqStatus == USBH_NOT_SUPPORTED) + 8008ff6: 7bbb ldrb r3, [r7, #14] + 8008ff8: 2b03 cmp r3, #3 + 8008ffa: d115 bne.n 8009028 + Status = USBH_OK; + 8008ffc: 2300 movs r3, #0 + 8008ffe: 73fb strb r3, [r7, #15] + break; + 8009000: e012 b.n 8009028 + Status = USBH_OK; + 8009002: 2300 movs r3, #0 + 8009004: 73fb strb r3, [r7, #15] + break; + 8009006: e00f b.n 8009028 + + default: + break; + 8009008: bf00 nop + 800900a: e00e b.n 800902a + break; + 800900c: bf00 nop + 800900e: e00c b.n 800902a + break; + 8009010: bf00 nop + 8009012: e00a b.n 800902a + break; + 8009014: bf00 nop + 8009016: e008 b.n 800902a + break; + 8009018: bf00 nop + 800901a: e006 b.n 800902a + break; + 800901c: bf00 nop + 800901e: e004 b.n 800902a + break; + 8009020: bf00 nop + 8009022: e002 b.n 800902a + break; + 8009024: bf00 nop + 8009026: e000 b.n 800902a + break; + 8009028: bf00 nop + } + return Status; + 800902a: 7bfb ldrb r3, [r7, #15] +} + 800902c: 4618 mov r0, r3 + 800902e: 3710 adds r7, #16 + 8009030: 46bd mov sp, r7 + 8009032: bd80 pop {r7, pc} + +08009034 : + * Set the initial Host Timer tick + * @param phost: Host Handle + * @retval None + */ +void USBH_LL_SetTimer(USBH_HandleTypeDef *phost, uint32_t time) +{ + 8009034: b480 push {r7} + 8009036: b083 sub sp, #12 + 8009038: af00 add r7, sp, #0 + 800903a: 6078 str r0, [r7, #4] + 800903c: 6039 str r1, [r7, #0] + phost->Timer = time; + 800903e: 687b ldr r3, [r7, #4] + 8009040: 683a ldr r2, [r7, #0] + 8009042: f8c3 23c4 str.w r2, [r3, #964] ; 0x3c4 +} + 8009046: bf00 nop + 8009048: 370c adds r7, #12 + 800904a: 46bd mov sp, r7 + 800904c: f85d 7b04 ldr.w r7, [sp], #4 + 8009050: 4770 bx lr + +08009052 : + * Increment Host Timer tick + * @param phost: Host Handle + * @retval None + */ +void USBH_LL_IncTimer(USBH_HandleTypeDef *phost) +{ + 8009052: b580 push {r7, lr} + 8009054: b082 sub sp, #8 + 8009056: af00 add r7, sp, #0 + 8009058: 6078 str r0, [r7, #4] + phost->Timer++; + 800905a: 687b ldr r3, [r7, #4] + 800905c: f8d3 33c4 ldr.w r3, [r3, #964] ; 0x3c4 + 8009060: 1c5a adds r2, r3, #1 + 8009062: 687b ldr r3, [r7, #4] + 8009064: f8c3 23c4 str.w r2, [r3, #964] ; 0x3c4 + USBH_HandleSof(phost); + 8009068: 6878 ldr r0, [r7, #4] + 800906a: f000 f804 bl 8009076 +} + 800906e: bf00 nop + 8009070: 3708 adds r7, #8 + 8009072: 46bd mov sp, r7 + 8009074: bd80 pop {r7, pc} + +08009076 : + * Call SOF process + * @param phost: Host Handle + * @retval None + */ +static void USBH_HandleSof(USBH_HandleTypeDef *phost) +{ + 8009076: b580 push {r7, lr} + 8009078: b082 sub sp, #8 + 800907a: af00 add r7, sp, #0 + 800907c: 6078 str r0, [r7, #4] + if ((phost->gState == HOST_CLASS) && (phost->pActiveClass != NULL)) + 800907e: 687b ldr r3, [r7, #4] + 8009080: 781b ldrb r3, [r3, #0] + 8009082: b2db uxtb r3, r3 + 8009084: 2b0b cmp r3, #11 + 8009086: d10a bne.n 800909e + 8009088: 687b ldr r3, [r7, #4] + 800908a: f8d3 337c ldr.w r3, [r3, #892] ; 0x37c + 800908e: 2b00 cmp r3, #0 + 8009090: d005 beq.n 800909e + { + phost->pActiveClass->SOFProcess(phost); + 8009092: 687b ldr r3, [r7, #4] + 8009094: f8d3 337c ldr.w r3, [r3, #892] ; 0x37c + 8009098: 699b ldr r3, [r3, #24] + 800909a: 6878 ldr r0, [r7, #4] + 800909c: 4798 blx r3 + } +} + 800909e: bf00 nop + 80090a0: 3708 adds r7, #8 + 80090a2: 46bd mov sp, r7 + 80090a4: bd80 pop {r7, pc} + +080090a6 : + * Port Enabled + * @param phost: Host Handle + * @retval None + */ +void USBH_LL_PortEnabled(USBH_HandleTypeDef *phost) +{ + 80090a6: b480 push {r7} + 80090a8: b083 sub sp, #12 + 80090aa: af00 add r7, sp, #0 + 80090ac: 6078 str r0, [r7, #4] + phost->device.PortEnabled = 1U; + 80090ae: 687b ldr r3, [r7, #4] + 80090b0: 2201 movs r2, #1 + 80090b2: f883 2323 strb.w r2, [r3, #803] ; 0x323 +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + + return; + 80090b6: bf00 nop +} + 80090b8: 370c adds r7, #12 + 80090ba: 46bd mov sp, r7 + 80090bc: f85d 7b04 ldr.w r7, [sp], #4 + 80090c0: 4770 bx lr + +080090c2 : + * Port Disabled + * @param phost: Host Handle + * @retval None + */ +void USBH_LL_PortDisabled(USBH_HandleTypeDef *phost) +{ + 80090c2: b480 push {r7} + 80090c4: b083 sub sp, #12 + 80090c6: af00 add r7, sp, #0 + 80090c8: 6078 str r0, [r7, #4] + phost->device.PortEnabled = 0U; + 80090ca: 687b ldr r3, [r7, #4] + 80090cc: 2200 movs r2, #0 + 80090ce: f883 2323 strb.w r2, [r3, #803] ; 0x323 + + return; + 80090d2: bf00 nop +} + 80090d4: 370c adds r7, #12 + 80090d6: 46bd mov sp, r7 + 80090d8: f85d 7b04 ldr.w r7, [sp], #4 + 80090dc: 4770 bx lr + +080090de : + * Handle USB Host connexion event + * @param phost: Host Handle + * @retval USBH_Status + */ +USBH_StatusTypeDef USBH_LL_Connect(USBH_HandleTypeDef *phost) +{ + 80090de: b480 push {r7} + 80090e0: b083 sub sp, #12 + 80090e2: af00 add r7, sp, #0 + 80090e4: 6078 str r0, [r7, #4] + phost->device.is_connected = 1U; + 80090e6: 687b ldr r3, [r7, #4] + 80090e8: 2201 movs r2, #1 + 80090ea: f883 2320 strb.w r2, [r3, #800] ; 0x320 + phost->device.is_disconnected = 0U; + 80090ee: 687b ldr r3, [r7, #4] + 80090f0: 2200 movs r2, #0 + 80090f2: f883 2321 strb.w r2, [r3, #801] ; 0x321 + phost->device.is_ReEnumerated = 0U; + 80090f6: 687b ldr r3, [r7, #4] + 80090f8: 2200 movs r2, #0 + 80090fa: f883 2322 strb.w r2, [r3, #802] ; 0x322 +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + + return USBH_OK; + 80090fe: 2300 movs r3, #0 +} + 8009100: 4618 mov r0, r3 + 8009102: 370c adds r7, #12 + 8009104: 46bd mov sp, r7 + 8009106: f85d 7b04 ldr.w r7, [sp], #4 + 800910a: 4770 bx lr + +0800910c : + * Handle USB Host disconnection event + * @param phost: Host Handle + * @retval USBH_Status + */ +USBH_StatusTypeDef USBH_LL_Disconnect(USBH_HandleTypeDef *phost) +{ + 800910c: b580 push {r7, lr} + 800910e: b082 sub sp, #8 + 8009110: af00 add r7, sp, #0 + 8009112: 6078 str r0, [r7, #4] + /* update device connection states */ + phost->device.is_disconnected = 1U; + 8009114: 687b ldr r3, [r7, #4] + 8009116: 2201 movs r2, #1 + 8009118: f883 2321 strb.w r2, [r3, #801] ; 0x321 + phost->device.is_connected = 0U; + 800911c: 687b ldr r3, [r7, #4] + 800911e: 2200 movs r2, #0 + 8009120: f883 2320 strb.w r2, [r3, #800] ; 0x320 + phost->device.PortEnabled = 0U; + 8009124: 687b ldr r3, [r7, #4] + 8009126: 2200 movs r2, #0 + 8009128: f883 2323 strb.w r2, [r3, #803] ; 0x323 + + /* Stop Host */ + USBH_LL_Stop(phost); + 800912c: 6878 ldr r0, [r7, #4] + 800912e: f000 ff58 bl 8009fe2 + + /* FRee Control Pipes */ + USBH_FreePipe(phost, phost->Control.pipe_in); + 8009132: 687b ldr r3, [r7, #4] + 8009134: 791b ldrb r3, [r3, #4] + 8009136: 4619 mov r1, r3 + 8009138: 6878 ldr r0, [r7, #4] + 800913a: f000 fda5 bl 8009c88 + USBH_FreePipe(phost, phost->Control.pipe_out); + 800913e: 687b ldr r3, [r7, #4] + 8009140: 795b ldrb r3, [r3, #5] + 8009142: 4619 mov r1, r3 + 8009144: 6878 ldr r0, [r7, #4] + 8009146: f000 fd9f bl 8009c88 +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + + return USBH_OK; + 800914a: 2300 movs r3, #0 +} + 800914c: 4618 mov r0, r3 + 800914e: 3708 adds r7, #8 + 8009150: 46bd mov sp, r7 + 8009152: bd80 pop {r7, pc} + +08009154 : + * @param phost: Host Handle + * @param length: Length of the descriptor + * @retval USBH Status + */ +USBH_StatusTypeDef USBH_Get_DevDesc(USBH_HandleTypeDef *phost, uint8_t length) +{ + 8009154: b580 push {r7, lr} + 8009156: b086 sub sp, #24 + 8009158: af02 add r7, sp, #8 + 800915a: 6078 str r0, [r7, #4] + 800915c: 460b mov r3, r1 + 800915e: 70fb strb r3, [r7, #3] + USBH_StatusTypeDef status; + + if ((status = USBH_GetDescriptor(phost, + USB_REQ_RECIPIENT_DEVICE | USB_REQ_TYPE_STANDARD, + USB_DESC_DEVICE, phost->device.Data, + 8009160: 687b ldr r3, [r7, #4] + 8009162: f503 728e add.w r2, r3, #284 ; 0x11c + if ((status = USBH_GetDescriptor(phost, + 8009166: 78fb ldrb r3, [r7, #3] + 8009168: b29b uxth r3, r3 + 800916a: 9300 str r3, [sp, #0] + 800916c: 4613 mov r3, r2 + 800916e: f44f 7280 mov.w r2, #256 ; 0x100 + 8009172: 2100 movs r1, #0 + 8009174: 6878 ldr r0, [r7, #4] + 8009176: f000 f864 bl 8009242 + 800917a: 4603 mov r3, r0 + 800917c: 73fb strb r3, [r7, #15] + 800917e: 7bfb ldrb r3, [r7, #15] + 8009180: 2b00 cmp r3, #0 + 8009182: d10a bne.n 800919a + (uint16_t)length)) == USBH_OK) + { + /* Commands successfully sent and Response Received */ + USBH_ParseDevDesc(&phost->device.DevDesc, phost->device.Data, + 8009184: 687b ldr r3, [r7, #4] + 8009186: f203 3026 addw r0, r3, #806 ; 0x326 + 800918a: 687b ldr r3, [r7, #4] + 800918c: f503 738e add.w r3, r3, #284 ; 0x11c + 8009190: 78fa ldrb r2, [r7, #3] + 8009192: b292 uxth r2, r2 + 8009194: 4619 mov r1, r3 + 8009196: f000 f918 bl 80093ca + (uint16_t)length); + } + + return status; + 800919a: 7bfb ldrb r3, [r7, #15] +} + 800919c: 4618 mov r0, r3 + 800919e: 3710 adds r7, #16 + 80091a0: 46bd mov sp, r7 + 80091a2: bd80 pop {r7, pc} + +080091a4 : + * @retval USBH Status + */ +USBH_StatusTypeDef USBH_Get_CfgDesc(USBH_HandleTypeDef *phost, + uint16_t length) + +{ + 80091a4: b580 push {r7, lr} + 80091a6: b086 sub sp, #24 + 80091a8: af02 add r7, sp, #8 + 80091aa: 6078 str r0, [r7, #4] + 80091ac: 460b mov r3, r1 + 80091ae: 807b strh r3, [r7, #2] + USBH_StatusTypeDef status; + uint8_t *pData = phost->device.CfgDesc_Raw;; + 80091b0: 687b ldr r3, [r7, #4] + 80091b2: 331c adds r3, #28 + 80091b4: 60fb str r3, [r7, #12] + + if ((status = USBH_GetDescriptor(phost, (USB_REQ_RECIPIENT_DEVICE | USB_REQ_TYPE_STANDARD), + 80091b6: 887b ldrh r3, [r7, #2] + 80091b8: 9300 str r3, [sp, #0] + 80091ba: 68fb ldr r3, [r7, #12] + 80091bc: f44f 7200 mov.w r2, #512 ; 0x200 + 80091c0: 2100 movs r1, #0 + 80091c2: 6878 ldr r0, [r7, #4] + 80091c4: f000 f83d bl 8009242 + 80091c8: 4603 mov r3, r0 + 80091ca: 72fb strb r3, [r7, #11] + 80091cc: 7afb ldrb r3, [r7, #11] + 80091ce: 2b00 cmp r3, #0 + 80091d0: d107 bne.n 80091e2 + USB_DESC_CONFIGURATION, pData, length)) == USBH_OK) + { + /* Commands successfully sent and Response Received */ + USBH_ParseCfgDesc(&phost->device.CfgDesc, pData, length); + 80091d2: 687b ldr r3, [r7, #4] + 80091d4: f503 734e add.w r3, r3, #824 ; 0x338 + 80091d8: 887a ldrh r2, [r7, #2] + 80091da: 68f9 ldr r1, [r7, #12] + 80091dc: 4618 mov r0, r3 + 80091de: f000 f964 bl 80094aa + } + + return status; + 80091e2: 7afb ldrb r3, [r7, #11] +} + 80091e4: 4618 mov r0, r3 + 80091e6: 3710 adds r7, #16 + 80091e8: 46bd mov sp, r7 + 80091ea: bd80 pop {r7, pc} + +080091ec : + * @retval USBH Status + */ +USBH_StatusTypeDef USBH_Get_StringDesc(USBH_HandleTypeDef *phost, + uint8_t string_index, uint8_t *buff, + uint16_t length) +{ + 80091ec: b580 push {r7, lr} + 80091ee: b088 sub sp, #32 + 80091f0: af02 add r7, sp, #8 + 80091f2: 60f8 str r0, [r7, #12] + 80091f4: 607a str r2, [r7, #4] + 80091f6: 461a mov r2, r3 + 80091f8: 460b mov r3, r1 + 80091fa: 72fb strb r3, [r7, #11] + 80091fc: 4613 mov r3, r2 + 80091fe: 813b strh r3, [r7, #8] + USBH_StatusTypeDef status; + + if ((status = USBH_GetDescriptor(phost, + 8009200: 7afb ldrb r3, [r7, #11] + 8009202: b29b uxth r3, r3 + 8009204: f443 7340 orr.w r3, r3, #768 ; 0x300 + 8009208: b29a uxth r2, r3 + USB_REQ_RECIPIENT_DEVICE | USB_REQ_TYPE_STANDARD, + USB_DESC_STRING | string_index, + phost->device.Data, length)) == USBH_OK) + 800920a: 68fb ldr r3, [r7, #12] + 800920c: f503 718e add.w r1, r3, #284 ; 0x11c + if ((status = USBH_GetDescriptor(phost, + 8009210: 893b ldrh r3, [r7, #8] + 8009212: 9300 str r3, [sp, #0] + 8009214: 460b mov r3, r1 + 8009216: 2100 movs r1, #0 + 8009218: 68f8 ldr r0, [r7, #12] + 800921a: f000 f812 bl 8009242 + 800921e: 4603 mov r3, r0 + 8009220: 75fb strb r3, [r7, #23] + 8009222: 7dfb ldrb r3, [r7, #23] + 8009224: 2b00 cmp r3, #0 + 8009226: d107 bne.n 8009238 + { + /* Commands successfully sent and Response Received */ + USBH_ParseStringDesc(phost->device.Data, buff, length); + 8009228: 68fb ldr r3, [r7, #12] + 800922a: f503 738e add.w r3, r3, #284 ; 0x11c + 800922e: 893a ldrh r2, [r7, #8] + 8009230: 6879 ldr r1, [r7, #4] + 8009232: 4618 mov r0, r3 + 8009234: f000 fa37 bl 80096a6 + } + + return status; + 8009238: 7dfb ldrb r3, [r7, #23] +} + 800923a: 4618 mov r0, r3 + 800923c: 3718 adds r7, #24 + 800923e: 46bd mov sp, r7 + 8009240: bd80 pop {r7, pc} + +08009242 : +USBH_StatusTypeDef USBH_GetDescriptor(USBH_HandleTypeDef *phost, + uint8_t req_type, + uint16_t value_idx, + uint8_t *buff, + uint16_t length) +{ + 8009242: b580 push {r7, lr} + 8009244: b084 sub sp, #16 + 8009246: af00 add r7, sp, #0 + 8009248: 60f8 str r0, [r7, #12] + 800924a: 607b str r3, [r7, #4] + 800924c: 460b mov r3, r1 + 800924e: 72fb strb r3, [r7, #11] + 8009250: 4613 mov r3, r2 + 8009252: 813b strh r3, [r7, #8] + if (phost->RequestState == CMD_SEND) + 8009254: 68fb ldr r3, [r7, #12] + 8009256: 789b ldrb r3, [r3, #2] + 8009258: 2b01 cmp r3, #1 + 800925a: d11c bne.n 8009296 + { + phost->Control.setup.b.bmRequestType = USB_D2H | req_type; + 800925c: 7afb ldrb r3, [r7, #11] + 800925e: f063 037f orn r3, r3, #127 ; 0x7f + 8009262: b2da uxtb r2, r3 + 8009264: 68fb ldr r3, [r7, #12] + 8009266: 741a strb r2, [r3, #16] + phost->Control.setup.b.bRequest = USB_REQ_GET_DESCRIPTOR; + 8009268: 68fb ldr r3, [r7, #12] + 800926a: 2206 movs r2, #6 + 800926c: 745a strb r2, [r3, #17] + phost->Control.setup.b.wValue.w = value_idx; + 800926e: 68fb ldr r3, [r7, #12] + 8009270: 893a ldrh r2, [r7, #8] + 8009272: 825a strh r2, [r3, #18] + + if ((value_idx & 0xff00U) == USB_DESC_STRING) + 8009274: 893b ldrh r3, [r7, #8] + 8009276: f403 437f and.w r3, r3, #65280 ; 0xff00 + 800927a: f5b3 7f40 cmp.w r3, #768 ; 0x300 + 800927e: d104 bne.n 800928a + { + phost->Control.setup.b.wIndex.w = 0x0409U; + 8009280: 68fb ldr r3, [r7, #12] + 8009282: f240 4209 movw r2, #1033 ; 0x409 + 8009286: 829a strh r2, [r3, #20] + 8009288: e002 b.n 8009290 + } + else + { + phost->Control.setup.b.wIndex.w = 0U; + 800928a: 68fb ldr r3, [r7, #12] + 800928c: 2200 movs r2, #0 + 800928e: 829a strh r2, [r3, #20] + } + phost->Control.setup.b.wLength.w = length; + 8009290: 68fb ldr r3, [r7, #12] + 8009292: 8b3a ldrh r2, [r7, #24] + 8009294: 82da strh r2, [r3, #22] + } + + return USBH_CtlReq(phost, buff, length); + 8009296: 8b3b ldrh r3, [r7, #24] + 8009298: 461a mov r2, r3 + 800929a: 6879 ldr r1, [r7, #4] + 800929c: 68f8 ldr r0, [r7, #12] + 800929e: f000 fa50 bl 8009742 + 80092a2: 4603 mov r3, r0 +} + 80092a4: 4618 mov r0, r3 + 80092a6: 3710 adds r7, #16 + 80092a8: 46bd mov sp, r7 + 80092aa: bd80 pop {r7, pc} + +080092ac : + * @param DeviceAddress: Device address to assign + * @retval USBH Status + */ +USBH_StatusTypeDef USBH_SetAddress(USBH_HandleTypeDef *phost, + uint8_t DeviceAddress) +{ + 80092ac: b580 push {r7, lr} + 80092ae: b082 sub sp, #8 + 80092b0: af00 add r7, sp, #0 + 80092b2: 6078 str r0, [r7, #4] + 80092b4: 460b mov r3, r1 + 80092b6: 70fb strb r3, [r7, #3] + if (phost->RequestState == CMD_SEND) + 80092b8: 687b ldr r3, [r7, #4] + 80092ba: 789b ldrb r3, [r3, #2] + 80092bc: 2b01 cmp r3, #1 + 80092be: d10f bne.n 80092e0 + { + phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_DEVICE | \ + 80092c0: 687b ldr r3, [r7, #4] + 80092c2: 2200 movs r2, #0 + 80092c4: 741a strb r2, [r3, #16] + USB_REQ_TYPE_STANDARD; + + phost->Control.setup.b.bRequest = USB_REQ_SET_ADDRESS; + 80092c6: 687b ldr r3, [r7, #4] + 80092c8: 2205 movs r2, #5 + 80092ca: 745a strb r2, [r3, #17] + + phost->Control.setup.b.wValue.w = (uint16_t)DeviceAddress; + 80092cc: 78fb ldrb r3, [r7, #3] + 80092ce: b29a uxth r2, r3 + 80092d0: 687b ldr r3, [r7, #4] + 80092d2: 825a strh r2, [r3, #18] + phost->Control.setup.b.wIndex.w = 0U; + 80092d4: 687b ldr r3, [r7, #4] + 80092d6: 2200 movs r2, #0 + 80092d8: 829a strh r2, [r3, #20] + phost->Control.setup.b.wLength.w = 0U; + 80092da: 687b ldr r3, [r7, #4] + 80092dc: 2200 movs r2, #0 + 80092de: 82da strh r2, [r3, #22] + } + + return USBH_CtlReq(phost, 0U, 0U); + 80092e0: 2200 movs r2, #0 + 80092e2: 2100 movs r1, #0 + 80092e4: 6878 ldr r0, [r7, #4] + 80092e6: f000 fa2c bl 8009742 + 80092ea: 4603 mov r3, r0 +} + 80092ec: 4618 mov r0, r3 + 80092ee: 3708 adds r7, #8 + 80092f0: 46bd mov sp, r7 + 80092f2: bd80 pop {r7, pc} + +080092f4 : + * @param phost: Host Handle + * @param cfg_idx: Configuration value + * @retval USBH Status + */ +USBH_StatusTypeDef USBH_SetCfg(USBH_HandleTypeDef *phost, uint16_t cfg_idx) +{ + 80092f4: b580 push {r7, lr} + 80092f6: b082 sub sp, #8 + 80092f8: af00 add r7, sp, #0 + 80092fa: 6078 str r0, [r7, #4] + 80092fc: 460b mov r3, r1 + 80092fe: 807b strh r3, [r7, #2] + if (phost->RequestState == CMD_SEND) + 8009300: 687b ldr r3, [r7, #4] + 8009302: 789b ldrb r3, [r3, #2] + 8009304: 2b01 cmp r3, #1 + 8009306: d10e bne.n 8009326 + { + phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_DEVICE + 8009308: 687b ldr r3, [r7, #4] + 800930a: 2200 movs r2, #0 + 800930c: 741a strb r2, [r3, #16] + | USB_REQ_TYPE_STANDARD; + + phost->Control.setup.b.bRequest = USB_REQ_SET_CONFIGURATION; + 800930e: 687b ldr r3, [r7, #4] + 8009310: 2209 movs r2, #9 + 8009312: 745a strb r2, [r3, #17] + phost->Control.setup.b.wValue.w = cfg_idx; + 8009314: 687b ldr r3, [r7, #4] + 8009316: 887a ldrh r2, [r7, #2] + 8009318: 825a strh r2, [r3, #18] + phost->Control.setup.b.wIndex.w = 0U; + 800931a: 687b ldr r3, [r7, #4] + 800931c: 2200 movs r2, #0 + 800931e: 829a strh r2, [r3, #20] + phost->Control.setup.b.wLength.w = 0U; + 8009320: 687b ldr r3, [r7, #4] + 8009322: 2200 movs r2, #0 + 8009324: 82da strh r2, [r3, #22] + } + + return USBH_CtlReq(phost, 0U, 0U); + 8009326: 2200 movs r2, #0 + 8009328: 2100 movs r1, #0 + 800932a: 6878 ldr r0, [r7, #4] + 800932c: f000 fa09 bl 8009742 + 8009330: 4603 mov r3, r0 +} + 8009332: 4618 mov r0, r3 + 8009334: 3708 adds r7, #8 + 8009336: 46bd mov sp, r7 + 8009338: bd80 pop {r7, pc} + +0800933a : + * @param pdev: Selected device + * @param itf_idx + * @retval Status +*/ +USBH_StatusTypeDef USBH_SetFeature(USBH_HandleTypeDef *phost, uint8_t wValue) +{ + 800933a: b580 push {r7, lr} + 800933c: b082 sub sp, #8 + 800933e: af00 add r7, sp, #0 + 8009340: 6078 str r0, [r7, #4] + 8009342: 460b mov r3, r1 + 8009344: 70fb strb r3, [r7, #3] + if (phost->RequestState == CMD_SEND) + 8009346: 687b ldr r3, [r7, #4] + 8009348: 789b ldrb r3, [r3, #2] + 800934a: 2b01 cmp r3, #1 + 800934c: d10f bne.n 800936e + { + phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_DEVICE + 800934e: 687b ldr r3, [r7, #4] + 8009350: 2200 movs r2, #0 + 8009352: 741a strb r2, [r3, #16] + | USB_REQ_TYPE_STANDARD; + + phost->Control.setup.b.bRequest = USB_REQ_SET_FEATURE; + 8009354: 687b ldr r3, [r7, #4] + 8009356: 2203 movs r2, #3 + 8009358: 745a strb r2, [r3, #17] + phost->Control.setup.b.wValue.w = wValue; + 800935a: 78fb ldrb r3, [r7, #3] + 800935c: b29a uxth r2, r3 + 800935e: 687b ldr r3, [r7, #4] + 8009360: 825a strh r2, [r3, #18] + phost->Control.setup.b.wIndex.w = 0U; + 8009362: 687b ldr r3, [r7, #4] + 8009364: 2200 movs r2, #0 + 8009366: 829a strh r2, [r3, #20] + phost->Control.setup.b.wLength.w = 0U; + 8009368: 687b ldr r3, [r7, #4] + 800936a: 2200 movs r2, #0 + 800936c: 82da strh r2, [r3, #22] + } + + return USBH_CtlReq(phost, 0U, 0U); + 800936e: 2200 movs r2, #0 + 8009370: 2100 movs r1, #0 + 8009372: 6878 ldr r0, [r7, #4] + 8009374: f000 f9e5 bl 8009742 + 8009378: 4603 mov r3, r0 +} + 800937a: 4618 mov r0, r3 + 800937c: 3708 adds r7, #8 + 800937e: 46bd mov sp, r7 + 8009380: bd80 pop {r7, pc} + +08009382 : + * @param ep_num: endpoint number + * @param hc_num: Host channel number + * @retval USBH Status + */ +USBH_StatusTypeDef USBH_ClrFeature(USBH_HandleTypeDef *phost, uint8_t ep_num) +{ + 8009382: b580 push {r7, lr} + 8009384: b082 sub sp, #8 + 8009386: af00 add r7, sp, #0 + 8009388: 6078 str r0, [r7, #4] + 800938a: 460b mov r3, r1 + 800938c: 70fb strb r3, [r7, #3] + if (phost->RequestState == CMD_SEND) + 800938e: 687b ldr r3, [r7, #4] + 8009390: 789b ldrb r3, [r3, #2] + 8009392: 2b01 cmp r3, #1 + 8009394: d10f bne.n 80093b6 + { + phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_ENDPOINT + 8009396: 687b ldr r3, [r7, #4] + 8009398: 2202 movs r2, #2 + 800939a: 741a strb r2, [r3, #16] + | USB_REQ_TYPE_STANDARD; + + phost->Control.setup.b.bRequest = USB_REQ_CLEAR_FEATURE; + 800939c: 687b ldr r3, [r7, #4] + 800939e: 2201 movs r2, #1 + 80093a0: 745a strb r2, [r3, #17] + phost->Control.setup.b.wValue.w = FEATURE_SELECTOR_ENDPOINT; + 80093a2: 687b ldr r3, [r7, #4] + 80093a4: 2200 movs r2, #0 + 80093a6: 825a strh r2, [r3, #18] + phost->Control.setup.b.wIndex.w = ep_num; + 80093a8: 78fb ldrb r3, [r7, #3] + 80093aa: b29a uxth r2, r3 + 80093ac: 687b ldr r3, [r7, #4] + 80093ae: 829a strh r2, [r3, #20] + phost->Control.setup.b.wLength.w = 0U; + 80093b0: 687b ldr r3, [r7, #4] + 80093b2: 2200 movs r2, #0 + 80093b4: 82da strh r2, [r3, #22] + } + return USBH_CtlReq(phost, 0U, 0U); + 80093b6: 2200 movs r2, #0 + 80093b8: 2100 movs r1, #0 + 80093ba: 6878 ldr r0, [r7, #4] + 80093bc: f000 f9c1 bl 8009742 + 80093c0: 4603 mov r3, r0 +} + 80093c2: 4618 mov r0, r3 + 80093c4: 3708 adds r7, #8 + 80093c6: 46bd mov sp, r7 + 80093c8: bd80 pop {r7, pc} + +080093ca : + * @param length: Length of the descriptor + * @retval None + */ +static void USBH_ParseDevDesc(USBH_DevDescTypeDef *dev_desc, uint8_t *buf, + uint16_t length) +{ + 80093ca: b480 push {r7} + 80093cc: b085 sub sp, #20 + 80093ce: af00 add r7, sp, #0 + 80093d0: 60f8 str r0, [r7, #12] + 80093d2: 60b9 str r1, [r7, #8] + 80093d4: 4613 mov r3, r2 + 80093d6: 80fb strh r3, [r7, #6] + dev_desc->bLength = *(uint8_t *)(buf + 0); + 80093d8: 68bb ldr r3, [r7, #8] + 80093da: 781a ldrb r2, [r3, #0] + 80093dc: 68fb ldr r3, [r7, #12] + 80093de: 701a strb r2, [r3, #0] + dev_desc->bDescriptorType = *(uint8_t *)(buf + 1); + 80093e0: 68bb ldr r3, [r7, #8] + 80093e2: 785a ldrb r2, [r3, #1] + 80093e4: 68fb ldr r3, [r7, #12] + 80093e6: 705a strb r2, [r3, #1] + dev_desc->bcdUSB = LE16(buf + 2); + 80093e8: 68bb ldr r3, [r7, #8] + 80093ea: 3302 adds r3, #2 + 80093ec: 781b ldrb r3, [r3, #0] + 80093ee: b29a uxth r2, r3 + 80093f0: 68bb ldr r3, [r7, #8] + 80093f2: 3303 adds r3, #3 + 80093f4: 781b ldrb r3, [r3, #0] + 80093f6: b29b uxth r3, r3 + 80093f8: 021b lsls r3, r3, #8 + 80093fa: b29b uxth r3, r3 + 80093fc: 4313 orrs r3, r2 + 80093fe: b29a uxth r2, r3 + 8009400: 68fb ldr r3, [r7, #12] + 8009402: 805a strh r2, [r3, #2] + dev_desc->bDeviceClass = *(uint8_t *)(buf + 4); + 8009404: 68bb ldr r3, [r7, #8] + 8009406: 791a ldrb r2, [r3, #4] + 8009408: 68fb ldr r3, [r7, #12] + 800940a: 711a strb r2, [r3, #4] + dev_desc->bDeviceSubClass = *(uint8_t *)(buf + 5); + 800940c: 68bb ldr r3, [r7, #8] + 800940e: 795a ldrb r2, [r3, #5] + 8009410: 68fb ldr r3, [r7, #12] + 8009412: 715a strb r2, [r3, #5] + dev_desc->bDeviceProtocol = *(uint8_t *)(buf + 6); + 8009414: 68bb ldr r3, [r7, #8] + 8009416: 799a ldrb r2, [r3, #6] + 8009418: 68fb ldr r3, [r7, #12] + 800941a: 719a strb r2, [r3, #6] + dev_desc->bMaxPacketSize = *(uint8_t *)(buf + 7); + 800941c: 68bb ldr r3, [r7, #8] + 800941e: 79da ldrb r2, [r3, #7] + 8009420: 68fb ldr r3, [r7, #12] + 8009422: 71da strb r2, [r3, #7] + + if (length > 8U) + 8009424: 88fb ldrh r3, [r7, #6] + 8009426: 2b08 cmp r3, #8 + 8009428: d939 bls.n 800949e + { + /* For 1st time after device connection, Host may issue only 8 bytes for + Device Descriptor Length */ + dev_desc->idVendor = LE16(buf + 8); + 800942a: 68bb ldr r3, [r7, #8] + 800942c: 3308 adds r3, #8 + 800942e: 781b ldrb r3, [r3, #0] + 8009430: b29a uxth r2, r3 + 8009432: 68bb ldr r3, [r7, #8] + 8009434: 3309 adds r3, #9 + 8009436: 781b ldrb r3, [r3, #0] + 8009438: b29b uxth r3, r3 + 800943a: 021b lsls r3, r3, #8 + 800943c: b29b uxth r3, r3 + 800943e: 4313 orrs r3, r2 + 8009440: b29a uxth r2, r3 + 8009442: 68fb ldr r3, [r7, #12] + 8009444: 811a strh r2, [r3, #8] + dev_desc->idProduct = LE16(buf + 10); + 8009446: 68bb ldr r3, [r7, #8] + 8009448: 330a adds r3, #10 + 800944a: 781b ldrb r3, [r3, #0] + 800944c: b29a uxth r2, r3 + 800944e: 68bb ldr r3, [r7, #8] + 8009450: 330b adds r3, #11 + 8009452: 781b ldrb r3, [r3, #0] + 8009454: b29b uxth r3, r3 + 8009456: 021b lsls r3, r3, #8 + 8009458: b29b uxth r3, r3 + 800945a: 4313 orrs r3, r2 + 800945c: b29a uxth r2, r3 + 800945e: 68fb ldr r3, [r7, #12] + 8009460: 815a strh r2, [r3, #10] + dev_desc->bcdDevice = LE16(buf + 12); + 8009462: 68bb ldr r3, [r7, #8] + 8009464: 330c adds r3, #12 + 8009466: 781b ldrb r3, [r3, #0] + 8009468: b29a uxth r2, r3 + 800946a: 68bb ldr r3, [r7, #8] + 800946c: 330d adds r3, #13 + 800946e: 781b ldrb r3, [r3, #0] + 8009470: b29b uxth r3, r3 + 8009472: 021b lsls r3, r3, #8 + 8009474: b29b uxth r3, r3 + 8009476: 4313 orrs r3, r2 + 8009478: b29a uxth r2, r3 + 800947a: 68fb ldr r3, [r7, #12] + 800947c: 819a strh r2, [r3, #12] + dev_desc->iManufacturer = *(uint8_t *)(buf + 14); + 800947e: 68bb ldr r3, [r7, #8] + 8009480: 7b9a ldrb r2, [r3, #14] + 8009482: 68fb ldr r3, [r7, #12] + 8009484: 739a strb r2, [r3, #14] + dev_desc->iProduct = *(uint8_t *)(buf + 15); + 8009486: 68bb ldr r3, [r7, #8] + 8009488: 7bda ldrb r2, [r3, #15] + 800948a: 68fb ldr r3, [r7, #12] + 800948c: 73da strb r2, [r3, #15] + dev_desc->iSerialNumber = *(uint8_t *)(buf + 16); + 800948e: 68bb ldr r3, [r7, #8] + 8009490: 7c1a ldrb r2, [r3, #16] + 8009492: 68fb ldr r3, [r7, #12] + 8009494: 741a strb r2, [r3, #16] + dev_desc->bNumConfigurations = *(uint8_t *)(buf + 17); + 8009496: 68bb ldr r3, [r7, #8] + 8009498: 7c5a ldrb r2, [r3, #17] + 800949a: 68fb ldr r3, [r7, #12] + 800949c: 745a strb r2, [r3, #17] + } +} + 800949e: bf00 nop + 80094a0: 3714 adds r7, #20 + 80094a2: 46bd mov sp, r7 + 80094a4: f85d 7b04 ldr.w r7, [sp], #4 + 80094a8: 4770 bx lr + +080094aa : + * @param length: Length of the descriptor + * @retval None + */ +static void USBH_ParseCfgDesc(USBH_CfgDescTypeDef *cfg_desc, uint8_t *buf, + uint16_t length) +{ + 80094aa: b580 push {r7, lr} + 80094ac: b08a sub sp, #40 ; 0x28 + 80094ae: af00 add r7, sp, #0 + 80094b0: 60f8 str r0, [r7, #12] + 80094b2: 60b9 str r1, [r7, #8] + 80094b4: 4613 mov r3, r2 + 80094b6: 80fb strh r3, [r7, #6] + USBH_InterfaceDescTypeDef *pif ; + USBH_EpDescTypeDef *pep; + USBH_DescHeader_t *pdesc = (USBH_DescHeader_t *)(void *)buf; + 80094b8: 68bb ldr r3, [r7, #8] + 80094ba: 627b str r3, [r7, #36] ; 0x24 + uint16_t ptr; + uint8_t if_ix = 0U; + 80094bc: 2300 movs r3, #0 + 80094be: f887 3023 strb.w r3, [r7, #35] ; 0x23 + uint8_t ep_ix = 0U; + 80094c2: 2300 movs r3, #0 + 80094c4: f887 3022 strb.w r3, [r7, #34] ; 0x22 + + pdesc = (USBH_DescHeader_t *)(void *)buf; + 80094c8: 68bb ldr r3, [r7, #8] + 80094ca: 627b str r3, [r7, #36] ; 0x24 + + /* Parse configuration descriptor */ + cfg_desc->bLength = *(uint8_t *)(buf + 0); + 80094cc: 68bb ldr r3, [r7, #8] + 80094ce: 781a ldrb r2, [r3, #0] + 80094d0: 68fb ldr r3, [r7, #12] + 80094d2: 701a strb r2, [r3, #0] + cfg_desc->bDescriptorType = *(uint8_t *)(buf + 1); + 80094d4: 68bb ldr r3, [r7, #8] + 80094d6: 785a ldrb r2, [r3, #1] + 80094d8: 68fb ldr r3, [r7, #12] + 80094da: 705a strb r2, [r3, #1] + cfg_desc->wTotalLength = LE16(buf + 2); + 80094dc: 68bb ldr r3, [r7, #8] + 80094de: 3302 adds r3, #2 + 80094e0: 781b ldrb r3, [r3, #0] + 80094e2: b29a uxth r2, r3 + 80094e4: 68bb ldr r3, [r7, #8] + 80094e6: 3303 adds r3, #3 + 80094e8: 781b ldrb r3, [r3, #0] + 80094ea: b29b uxth r3, r3 + 80094ec: 021b lsls r3, r3, #8 + 80094ee: b29b uxth r3, r3 + 80094f0: 4313 orrs r3, r2 + 80094f2: b29a uxth r2, r3 + 80094f4: 68fb ldr r3, [r7, #12] + 80094f6: 805a strh r2, [r3, #2] + cfg_desc->bNumInterfaces = *(uint8_t *)(buf + 4); + 80094f8: 68bb ldr r3, [r7, #8] + 80094fa: 791a ldrb r2, [r3, #4] + 80094fc: 68fb ldr r3, [r7, #12] + 80094fe: 711a strb r2, [r3, #4] + cfg_desc->bConfigurationValue = *(uint8_t *)(buf + 5); + 8009500: 68bb ldr r3, [r7, #8] + 8009502: 795a ldrb r2, [r3, #5] + 8009504: 68fb ldr r3, [r7, #12] + 8009506: 715a strb r2, [r3, #5] + cfg_desc->iConfiguration = *(uint8_t *)(buf + 6); + 8009508: 68bb ldr r3, [r7, #8] + 800950a: 799a ldrb r2, [r3, #6] + 800950c: 68fb ldr r3, [r7, #12] + 800950e: 719a strb r2, [r3, #6] + cfg_desc->bmAttributes = *(uint8_t *)(buf + 7); + 8009510: 68bb ldr r3, [r7, #8] + 8009512: 79da ldrb r2, [r3, #7] + 8009514: 68fb ldr r3, [r7, #12] + 8009516: 71da strb r2, [r3, #7] + cfg_desc->bMaxPower = *(uint8_t *)(buf + 8); + 8009518: 68bb ldr r3, [r7, #8] + 800951a: 7a1a ldrb r2, [r3, #8] + 800951c: 68fb ldr r3, [r7, #12] + 800951e: 721a strb r2, [r3, #8] + + if (length > USB_CONFIGURATION_DESC_SIZE) + 8009520: 88fb ldrh r3, [r7, #6] + 8009522: 2b09 cmp r3, #9 + 8009524: d95f bls.n 80095e6 + { + ptr = USB_LEN_CFG_DESC; + 8009526: 2309 movs r3, #9 + 8009528: 82fb strh r3, [r7, #22] + pif = (USBH_InterfaceDescTypeDef *)0; + 800952a: 2300 movs r3, #0 + 800952c: 61fb str r3, [r7, #28] + + while ((if_ix < USBH_MAX_NUM_INTERFACES) && (ptr < cfg_desc->wTotalLength)) + 800952e: e051 b.n 80095d4 + { + pdesc = USBH_GetNextDesc((uint8_t *)(void *)pdesc, &ptr); + 8009530: f107 0316 add.w r3, r7, #22 + 8009534: 4619 mov r1, r3 + 8009536: 6a78 ldr r0, [r7, #36] ; 0x24 + 8009538: f000 f8e8 bl 800970c + 800953c: 6278 str r0, [r7, #36] ; 0x24 + if (pdesc->bDescriptorType == USB_DESC_TYPE_INTERFACE) + 800953e: 6a7b ldr r3, [r7, #36] ; 0x24 + 8009540: 785b ldrb r3, [r3, #1] + 8009542: 2b04 cmp r3, #4 + 8009544: d146 bne.n 80095d4 + { + pif = &cfg_desc->Itf_Desc[if_ix]; + 8009546: f897 3023 ldrb.w r3, [r7, #35] ; 0x23 + 800954a: 221a movs r2, #26 + 800954c: fb02 f303 mul.w r3, r2, r3 + 8009550: 3308 adds r3, #8 + 8009552: 68fa ldr r2, [r7, #12] + 8009554: 4413 add r3, r2 + 8009556: 3302 adds r3, #2 + 8009558: 61fb str r3, [r7, #28] + USBH_ParseInterfaceDesc(pif, (uint8_t *)(void *)pdesc); + 800955a: 6a79 ldr r1, [r7, #36] ; 0x24 + 800955c: 69f8 ldr r0, [r7, #28] + 800955e: f000 f846 bl 80095ee + + ep_ix = 0U; + 8009562: 2300 movs r3, #0 + 8009564: f887 3022 strb.w r3, [r7, #34] ; 0x22 + pep = (USBH_EpDescTypeDef *)0; + 8009568: 2300 movs r3, #0 + 800956a: 61bb str r3, [r7, #24] + while ((ep_ix < pif->bNumEndpoints) && (ptr < cfg_desc->wTotalLength)) + 800956c: e022 b.n 80095b4 + { + pdesc = USBH_GetNextDesc((uint8_t *)(void *)pdesc, &ptr); + 800956e: f107 0316 add.w r3, r7, #22 + 8009572: 4619 mov r1, r3 + 8009574: 6a78 ldr r0, [r7, #36] ; 0x24 + 8009576: f000 f8c9 bl 800970c + 800957a: 6278 str r0, [r7, #36] ; 0x24 + if (pdesc->bDescriptorType == USB_DESC_TYPE_ENDPOINT) + 800957c: 6a7b ldr r3, [r7, #36] ; 0x24 + 800957e: 785b ldrb r3, [r3, #1] + 8009580: 2b05 cmp r3, #5 + 8009582: d117 bne.n 80095b4 + { + pep = &cfg_desc->Itf_Desc[if_ix].Ep_Desc[ep_ix]; + 8009584: f897 3023 ldrb.w r3, [r7, #35] ; 0x23 + 8009588: f897 2022 ldrb.w r2, [r7, #34] ; 0x22 + 800958c: 3201 adds r2, #1 + 800958e: 00d2 lsls r2, r2, #3 + 8009590: 211a movs r1, #26 + 8009592: fb01 f303 mul.w r3, r1, r3 + 8009596: 4413 add r3, r2 + 8009598: 3308 adds r3, #8 + 800959a: 68fa ldr r2, [r7, #12] + 800959c: 4413 add r3, r2 + 800959e: 3304 adds r3, #4 + 80095a0: 61bb str r3, [r7, #24] + USBH_ParseEPDesc(pep, (uint8_t *)(void *)pdesc); + 80095a2: 6a79 ldr r1, [r7, #36] ; 0x24 + 80095a4: 69b8 ldr r0, [r7, #24] + 80095a6: f000 f851 bl 800964c + ep_ix++; + 80095aa: f897 3022 ldrb.w r3, [r7, #34] ; 0x22 + 80095ae: 3301 adds r3, #1 + 80095b0: f887 3022 strb.w r3, [r7, #34] ; 0x22 + while ((ep_ix < pif->bNumEndpoints) && (ptr < cfg_desc->wTotalLength)) + 80095b4: 69fb ldr r3, [r7, #28] + 80095b6: 791b ldrb r3, [r3, #4] + 80095b8: f897 2022 ldrb.w r2, [r7, #34] ; 0x22 + 80095bc: 429a cmp r2, r3 + 80095be: d204 bcs.n 80095ca + 80095c0: 68fb ldr r3, [r7, #12] + 80095c2: 885a ldrh r2, [r3, #2] + 80095c4: 8afb ldrh r3, [r7, #22] + 80095c6: 429a cmp r2, r3 + 80095c8: d8d1 bhi.n 800956e + } + } + if_ix++; + 80095ca: f897 3023 ldrb.w r3, [r7, #35] ; 0x23 + 80095ce: 3301 adds r3, #1 + 80095d0: f887 3023 strb.w r3, [r7, #35] ; 0x23 + while ((if_ix < USBH_MAX_NUM_INTERFACES) && (ptr < cfg_desc->wTotalLength)) + 80095d4: f897 3023 ldrb.w r3, [r7, #35] ; 0x23 + 80095d8: 2b01 cmp r3, #1 + 80095da: d804 bhi.n 80095e6 + 80095dc: 68fb ldr r3, [r7, #12] + 80095de: 885a ldrh r2, [r3, #2] + 80095e0: 8afb ldrh r3, [r7, #22] + 80095e2: 429a cmp r2, r3 + 80095e4: d8a4 bhi.n 8009530 + } + } + } +} + 80095e6: bf00 nop + 80095e8: 3728 adds r7, #40 ; 0x28 + 80095ea: 46bd mov sp, r7 + 80095ec: bd80 pop {r7, pc} + +080095ee : + * @param buf: Buffer where the descriptor data is available + * @retval None + */ +static void USBH_ParseInterfaceDesc(USBH_InterfaceDescTypeDef *if_descriptor, + uint8_t *buf) +{ + 80095ee: b480 push {r7} + 80095f0: b083 sub sp, #12 + 80095f2: af00 add r7, sp, #0 + 80095f4: 6078 str r0, [r7, #4] + 80095f6: 6039 str r1, [r7, #0] + if_descriptor->bLength = *(uint8_t *)(buf + 0); + 80095f8: 683b ldr r3, [r7, #0] + 80095fa: 781a ldrb r2, [r3, #0] + 80095fc: 687b ldr r3, [r7, #4] + 80095fe: 701a strb r2, [r3, #0] + if_descriptor->bDescriptorType = *(uint8_t *)(buf + 1); + 8009600: 683b ldr r3, [r7, #0] + 8009602: 785a ldrb r2, [r3, #1] + 8009604: 687b ldr r3, [r7, #4] + 8009606: 705a strb r2, [r3, #1] + if_descriptor->bInterfaceNumber = *(uint8_t *)(buf + 2); + 8009608: 683b ldr r3, [r7, #0] + 800960a: 789a ldrb r2, [r3, #2] + 800960c: 687b ldr r3, [r7, #4] + 800960e: 709a strb r2, [r3, #2] + if_descriptor->bAlternateSetting = *(uint8_t *)(buf + 3); + 8009610: 683b ldr r3, [r7, #0] + 8009612: 78da ldrb r2, [r3, #3] + 8009614: 687b ldr r3, [r7, #4] + 8009616: 70da strb r2, [r3, #3] + if_descriptor->bNumEndpoints = *(uint8_t *)(buf + 4); + 8009618: 683b ldr r3, [r7, #0] + 800961a: 791a ldrb r2, [r3, #4] + 800961c: 687b ldr r3, [r7, #4] + 800961e: 711a strb r2, [r3, #4] + if_descriptor->bInterfaceClass = *(uint8_t *)(buf + 5); + 8009620: 683b ldr r3, [r7, #0] + 8009622: 795a ldrb r2, [r3, #5] + 8009624: 687b ldr r3, [r7, #4] + 8009626: 715a strb r2, [r3, #5] + if_descriptor->bInterfaceSubClass = *(uint8_t *)(buf + 6); + 8009628: 683b ldr r3, [r7, #0] + 800962a: 799a ldrb r2, [r3, #6] + 800962c: 687b ldr r3, [r7, #4] + 800962e: 719a strb r2, [r3, #6] + if_descriptor->bInterfaceProtocol = *(uint8_t *)(buf + 7); + 8009630: 683b ldr r3, [r7, #0] + 8009632: 79da ldrb r2, [r3, #7] + 8009634: 687b ldr r3, [r7, #4] + 8009636: 71da strb r2, [r3, #7] + if_descriptor->iInterface = *(uint8_t *)(buf + 8); + 8009638: 683b ldr r3, [r7, #0] + 800963a: 7a1a ldrb r2, [r3, #8] + 800963c: 687b ldr r3, [r7, #4] + 800963e: 721a strb r2, [r3, #8] +} + 8009640: bf00 nop + 8009642: 370c adds r7, #12 + 8009644: 46bd mov sp, r7 + 8009646: f85d 7b04 ldr.w r7, [sp], #4 + 800964a: 4770 bx lr + +0800964c : + * @param buf: Buffer where the parsed descriptor stored + * @retval None + */ +static void USBH_ParseEPDesc(USBH_EpDescTypeDef *ep_descriptor, + uint8_t *buf) +{ + 800964c: b480 push {r7} + 800964e: b083 sub sp, #12 + 8009650: af00 add r7, sp, #0 + 8009652: 6078 str r0, [r7, #4] + 8009654: 6039 str r1, [r7, #0] + ep_descriptor->bLength = *(uint8_t *)(buf + 0); + 8009656: 683b ldr r3, [r7, #0] + 8009658: 781a ldrb r2, [r3, #0] + 800965a: 687b ldr r3, [r7, #4] + 800965c: 701a strb r2, [r3, #0] + ep_descriptor->bDescriptorType = *(uint8_t *)(buf + 1); + 800965e: 683b ldr r3, [r7, #0] + 8009660: 785a ldrb r2, [r3, #1] + 8009662: 687b ldr r3, [r7, #4] + 8009664: 705a strb r2, [r3, #1] + ep_descriptor->bEndpointAddress = *(uint8_t *)(buf + 2); + 8009666: 683b ldr r3, [r7, #0] + 8009668: 789a ldrb r2, [r3, #2] + 800966a: 687b ldr r3, [r7, #4] + 800966c: 709a strb r2, [r3, #2] + ep_descriptor->bmAttributes = *(uint8_t *)(buf + 3); + 800966e: 683b ldr r3, [r7, #0] + 8009670: 78da ldrb r2, [r3, #3] + 8009672: 687b ldr r3, [r7, #4] + 8009674: 70da strb r2, [r3, #3] + ep_descriptor->wMaxPacketSize = LE16(buf + 4); + 8009676: 683b ldr r3, [r7, #0] + 8009678: 3304 adds r3, #4 + 800967a: 781b ldrb r3, [r3, #0] + 800967c: b29a uxth r2, r3 + 800967e: 683b ldr r3, [r7, #0] + 8009680: 3305 adds r3, #5 + 8009682: 781b ldrb r3, [r3, #0] + 8009684: b29b uxth r3, r3 + 8009686: 021b lsls r3, r3, #8 + 8009688: b29b uxth r3, r3 + 800968a: 4313 orrs r3, r2 + 800968c: b29a uxth r2, r3 + 800968e: 687b ldr r3, [r7, #4] + 8009690: 809a strh r2, [r3, #4] + ep_descriptor->bInterval = *(uint8_t *)(buf + 6); + 8009692: 683b ldr r3, [r7, #0] + 8009694: 799a ldrb r2, [r3, #6] + 8009696: 687b ldr r3, [r7, #4] + 8009698: 719a strb r2, [r3, #6] +} + 800969a: bf00 nop + 800969c: 370c adds r7, #12 + 800969e: 46bd mov sp, r7 + 80096a0: f85d 7b04 ldr.w r7, [sp], #4 + 80096a4: 4770 bx lr + +080096a6 : + * @param pdest: Destination address pointer + * @param length: Length of the descriptor + * @retval None + */ +static void USBH_ParseStringDesc(uint8_t *psrc, uint8_t *pdest, uint16_t length) +{ + 80096a6: b480 push {r7} + 80096a8: b087 sub sp, #28 + 80096aa: af00 add r7, sp, #0 + 80096ac: 60f8 str r0, [r7, #12] + 80096ae: 60b9 str r1, [r7, #8] + 80096b0: 4613 mov r3, r2 + 80096b2: 80fb strh r3, [r7, #6] + */ + + /* Check which is lower size, the Size of string or the length of bytes read + from the device */ + + if (psrc[1] == USB_DESC_TYPE_STRING) + 80096b4: 68fb ldr r3, [r7, #12] + 80096b6: 3301 adds r3, #1 + 80096b8: 781b ldrb r3, [r3, #0] + 80096ba: 2b03 cmp r3, #3 + 80096bc: d120 bne.n 8009700 + { + /* Make sure the Descriptor is String Type */ + + /* psrc[0] contains Size of Descriptor, subtract 2 to get the length of string */ + strlength = ((((uint16_t)psrc[0] - 2U) <= length) ? ((uint16_t)psrc[0] - 2U) : length); + 80096be: 68fb ldr r3, [r7, #12] + 80096c0: 781b ldrb r3, [r3, #0] + 80096c2: 1e9a subs r2, r3, #2 + 80096c4: 88fb ldrh r3, [r7, #6] + 80096c6: 4293 cmp r3, r2 + 80096c8: bf28 it cs + 80096ca: 4613 movcs r3, r2 + 80096cc: 82bb strh r3, [r7, #20] + + /* Adjust the offset ignoring the String Len and Descriptor type */ + psrc += 2U; + 80096ce: 68fb ldr r3, [r7, #12] + 80096d0: 3302 adds r3, #2 + 80096d2: 60fb str r3, [r7, #12] + + for (idx = 0U; idx < strlength; idx += 2U) + 80096d4: 2300 movs r3, #0 + 80096d6: 82fb strh r3, [r7, #22] + 80096d8: e00b b.n 80096f2 + { + /* Copy Only the string and ignore the UNICODE ID, hence add the src */ + *pdest = psrc[idx]; + 80096da: 8afb ldrh r3, [r7, #22] + 80096dc: 68fa ldr r2, [r7, #12] + 80096de: 4413 add r3, r2 + 80096e0: 781a ldrb r2, [r3, #0] + 80096e2: 68bb ldr r3, [r7, #8] + 80096e4: 701a strb r2, [r3, #0] + pdest++; + 80096e6: 68bb ldr r3, [r7, #8] + 80096e8: 3301 adds r3, #1 + 80096ea: 60bb str r3, [r7, #8] + for (idx = 0U; idx < strlength; idx += 2U) + 80096ec: 8afb ldrh r3, [r7, #22] + 80096ee: 3302 adds r3, #2 + 80096f0: 82fb strh r3, [r7, #22] + 80096f2: 8afa ldrh r2, [r7, #22] + 80096f4: 8abb ldrh r3, [r7, #20] + 80096f6: 429a cmp r2, r3 + 80096f8: d3ef bcc.n 80096da + } + *pdest = 0U; /* mark end of string */ + 80096fa: 68bb ldr r3, [r7, #8] + 80096fc: 2200 movs r2, #0 + 80096fe: 701a strb r2, [r3, #0] + } +} + 8009700: bf00 nop + 8009702: 371c adds r7, #28 + 8009704: 46bd mov sp, r7 + 8009706: f85d 7b04 ldr.w r7, [sp], #4 + 800970a: 4770 bx lr + +0800970c : + * @param buf: Buffer where the cfg descriptor is available + * @param ptr: data pointer inside the cfg descriptor + * @retval next header + */ +USBH_DescHeader_t *USBH_GetNextDesc(uint8_t *pbuf, uint16_t *ptr) +{ + 800970c: b480 push {r7} + 800970e: b085 sub sp, #20 + 8009710: af00 add r7, sp, #0 + 8009712: 6078 str r0, [r7, #4] + 8009714: 6039 str r1, [r7, #0] + USBH_DescHeader_t *pnext; + + *ptr += ((USBH_DescHeader_t *)(void *)pbuf)->bLength; + 8009716: 683b ldr r3, [r7, #0] + 8009718: 881a ldrh r2, [r3, #0] + 800971a: 687b ldr r3, [r7, #4] + 800971c: 781b ldrb r3, [r3, #0] + 800971e: b29b uxth r3, r3 + 8009720: 4413 add r3, r2 + 8009722: b29a uxth r2, r3 + 8009724: 683b ldr r3, [r7, #0] + 8009726: 801a strh r2, [r3, #0] + pnext = (USBH_DescHeader_t *)(void *)((uint8_t *)(void *)pbuf + \ + ((USBH_DescHeader_t *)(void *)pbuf)->bLength); + 8009728: 687b ldr r3, [r7, #4] + 800972a: 781b ldrb r3, [r3, #0] + 800972c: 461a mov r2, r3 + pnext = (USBH_DescHeader_t *)(void *)((uint8_t *)(void *)pbuf + \ + 800972e: 687b ldr r3, [r7, #4] + 8009730: 4413 add r3, r2 + 8009732: 60fb str r3, [r7, #12] + + return (pnext); + 8009734: 68fb ldr r3, [r7, #12] +} + 8009736: 4618 mov r0, r3 + 8009738: 3714 adds r7, #20 + 800973a: 46bd mov sp, r7 + 800973c: f85d 7b04 ldr.w r7, [sp], #4 + 8009740: 4770 bx lr + +08009742 : + * @param length: length of the response + * @retval USBH Status + */ +USBH_StatusTypeDef USBH_CtlReq(USBH_HandleTypeDef *phost, uint8_t *buff, + uint16_t length) +{ + 8009742: b580 push {r7, lr} + 8009744: b086 sub sp, #24 + 8009746: af00 add r7, sp, #0 + 8009748: 60f8 str r0, [r7, #12] + 800974a: 60b9 str r1, [r7, #8] + 800974c: 4613 mov r3, r2 + 800974e: 80fb strh r3, [r7, #6] + USBH_StatusTypeDef status; + status = USBH_BUSY; + 8009750: 2301 movs r3, #1 + 8009752: 75fb strb r3, [r7, #23] + + switch (phost->RequestState) + 8009754: 68fb ldr r3, [r7, #12] + 8009756: 789b ldrb r3, [r3, #2] + 8009758: 2b01 cmp r3, #1 + 800975a: d002 beq.n 8009762 + 800975c: 2b02 cmp r3, #2 + 800975e: d00f beq.n 8009780 +#endif +#endif + break; + + default: + break; + 8009760: e027 b.n 80097b2 + phost->Control.buff = buff; + 8009762: 68fb ldr r3, [r7, #12] + 8009764: 68ba ldr r2, [r7, #8] + 8009766: 609a str r2, [r3, #8] + phost->Control.length = length; + 8009768: 68fb ldr r3, [r7, #12] + 800976a: 88fa ldrh r2, [r7, #6] + 800976c: 819a strh r2, [r3, #12] + phost->Control.state = CTRL_SETUP; + 800976e: 68fb ldr r3, [r7, #12] + 8009770: 2201 movs r2, #1 + 8009772: 761a strb r2, [r3, #24] + phost->RequestState = CMD_WAIT; + 8009774: 68fb ldr r3, [r7, #12] + 8009776: 2202 movs r2, #2 + 8009778: 709a strb r2, [r3, #2] + status = USBH_BUSY; + 800977a: 2301 movs r3, #1 + 800977c: 75fb strb r3, [r7, #23] + break; + 800977e: e018 b.n 80097b2 + status = USBH_HandleControl(phost); + 8009780: 68f8 ldr r0, [r7, #12] + 8009782: f000 f81b bl 80097bc + 8009786: 4603 mov r3, r0 + 8009788: 75fb strb r3, [r7, #23] + if ((status == USBH_OK) || (status == USBH_NOT_SUPPORTED)) + 800978a: 7dfb ldrb r3, [r7, #23] + 800978c: 2b00 cmp r3, #0 + 800978e: d002 beq.n 8009796 + 8009790: 7dfb ldrb r3, [r7, #23] + 8009792: 2b03 cmp r3, #3 + 8009794: d106 bne.n 80097a4 + phost->RequestState = CMD_SEND; + 8009796: 68fb ldr r3, [r7, #12] + 8009798: 2201 movs r2, #1 + 800979a: 709a strb r2, [r3, #2] + phost->Control.state = CTRL_IDLE; + 800979c: 68fb ldr r3, [r7, #12] + 800979e: 2200 movs r2, #0 + 80097a0: 761a strb r2, [r3, #24] + break; + 80097a2: e005 b.n 80097b0 + else if (status == USBH_FAIL) + 80097a4: 7dfb ldrb r3, [r7, #23] + 80097a6: 2b02 cmp r3, #2 + 80097a8: d102 bne.n 80097b0 + phost->RequestState = CMD_SEND; + 80097aa: 68fb ldr r3, [r7, #12] + 80097ac: 2201 movs r2, #1 + 80097ae: 709a strb r2, [r3, #2] + break; + 80097b0: bf00 nop + } + return status; + 80097b2: 7dfb ldrb r3, [r7, #23] +} + 80097b4: 4618 mov r0, r3 + 80097b6: 3718 adds r7, #24 + 80097b8: 46bd mov sp, r7 + 80097ba: bd80 pop {r7, pc} + +080097bc : + * Handles the USB control transfer state machine + * @param phost: Host Handle + * @retval USBH Status + */ +static USBH_StatusTypeDef USBH_HandleControl(USBH_HandleTypeDef *phost) +{ + 80097bc: b580 push {r7, lr} + 80097be: b086 sub sp, #24 + 80097c0: af02 add r7, sp, #8 + 80097c2: 6078 str r0, [r7, #4] + uint8_t direction; + USBH_StatusTypeDef status = USBH_BUSY; + 80097c4: 2301 movs r3, #1 + 80097c6: 73fb strb r3, [r7, #15] + USBH_URBStateTypeDef URB_Status = USBH_URB_IDLE; + 80097c8: 2300 movs r3, #0 + 80097ca: 73bb strb r3, [r7, #14] + + switch (phost->Control.state) + 80097cc: 687b ldr r3, [r7, #4] + 80097ce: 7e1b ldrb r3, [r3, #24] + 80097d0: 3b01 subs r3, #1 + 80097d2: 2b0a cmp r3, #10 + 80097d4: f200 8158 bhi.w 8009a88 + 80097d8: a201 add r2, pc, #4 ; (adr r2, 80097e0 ) + 80097da: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 80097de: bf00 nop + 80097e0: 0800980d .word 0x0800980d + 80097e4: 08009827 .word 0x08009827 + 80097e8: 08009891 .word 0x08009891 + 80097ec: 080098b7 .word 0x080098b7 + 80097f0: 080098ef .word 0x080098ef + 80097f4: 0800991b .word 0x0800991b + 80097f8: 0800996d .word 0x0800996d + 80097fc: 0800998f .word 0x0800998f + 8009800: 080099cb .word 0x080099cb + 8009804: 080099f3 .word 0x080099f3 + 8009808: 08009a31 .word 0x08009a31 + { + case CTRL_SETUP: + /* send a SETUP packet */ + USBH_CtlSendSetup(phost, (uint8_t *)(void *)phost->Control.setup.d8, + 800980c: 687b ldr r3, [r7, #4] + 800980e: f103 0110 add.w r1, r3, #16 + 8009812: 687b ldr r3, [r7, #4] + 8009814: 795b ldrb r3, [r3, #5] + 8009816: 461a mov r2, r3 + 8009818: 6878 ldr r0, [r7, #4] + 800981a: f000 f945 bl 8009aa8 + phost->Control.pipe_out); + + phost->Control.state = CTRL_SETUP_WAIT; + 800981e: 687b ldr r3, [r7, #4] + 8009820: 2202 movs r2, #2 + 8009822: 761a strb r2, [r3, #24] + break; + 8009824: e13b b.n 8009a9e + + case CTRL_SETUP_WAIT: + + URB_Status = USBH_LL_GetURBState(phost, phost->Control.pipe_out); + 8009826: 687b ldr r3, [r7, #4] + 8009828: 795b ldrb r3, [r3, #5] + 800982a: 4619 mov r1, r3 + 800982c: 6878 ldr r0, [r7, #4] + 800982e: f000 fcc5 bl 800a1bc + 8009832: 4603 mov r3, r0 + 8009834: 73bb strb r3, [r7, #14] + /* case SETUP packet sent successfully */ + if (URB_Status == USBH_URB_DONE) + 8009836: 7bbb ldrb r3, [r7, #14] + 8009838: 2b01 cmp r3, #1 + 800983a: d11e bne.n 800987a + { + direction = (phost->Control.setup.b.bmRequestType & USB_REQ_DIR_MASK); + 800983c: 687b ldr r3, [r7, #4] + 800983e: 7c1b ldrb r3, [r3, #16] + 8009840: f023 037f bic.w r3, r3, #127 ; 0x7f + 8009844: 737b strb r3, [r7, #13] + + /* check if there is a data stage */ + if (phost->Control.setup.b.wLength.w != 0U) + 8009846: 687b ldr r3, [r7, #4] + 8009848: 8adb ldrh r3, [r3, #22] + 800984a: 2b00 cmp r3, #0 + 800984c: d00a beq.n 8009864 + { + if (direction == USB_D2H) + 800984e: 7b7b ldrb r3, [r7, #13] + 8009850: 2b80 cmp r3, #128 ; 0x80 + 8009852: d103 bne.n 800985c + { + /* Data Direction is IN */ + phost->Control.state = CTRL_DATA_IN; + 8009854: 687b ldr r3, [r7, #4] + 8009856: 2203 movs r2, #3 + 8009858: 761a strb r2, [r3, #24] + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + } + } + break; + 800985a: e117 b.n 8009a8c + phost->Control.state = CTRL_DATA_OUT; + 800985c: 687b ldr r3, [r7, #4] + 800985e: 2205 movs r2, #5 + 8009860: 761a strb r2, [r3, #24] + break; + 8009862: e113 b.n 8009a8c + if (direction == USB_D2H) + 8009864: 7b7b ldrb r3, [r7, #13] + 8009866: 2b80 cmp r3, #128 ; 0x80 + 8009868: d103 bne.n 8009872 + phost->Control.state = CTRL_STATUS_OUT; + 800986a: 687b ldr r3, [r7, #4] + 800986c: 2209 movs r2, #9 + 800986e: 761a strb r2, [r3, #24] + break; + 8009870: e10c b.n 8009a8c + phost->Control.state = CTRL_STATUS_IN; + 8009872: 687b ldr r3, [r7, #4] + 8009874: 2207 movs r2, #7 + 8009876: 761a strb r2, [r3, #24] + break; + 8009878: e108 b.n 8009a8c + if ((URB_Status == USBH_URB_ERROR) || (URB_Status == USBH_URB_NOTREADY)) + 800987a: 7bbb ldrb r3, [r7, #14] + 800987c: 2b04 cmp r3, #4 + 800987e: d003 beq.n 8009888 + 8009880: 7bbb ldrb r3, [r7, #14] + 8009882: 2b02 cmp r3, #2 + 8009884: f040 8102 bne.w 8009a8c + phost->Control.state = CTRL_ERROR; + 8009888: 687b ldr r3, [r7, #4] + 800988a: 220b movs r2, #11 + 800988c: 761a strb r2, [r3, #24] + break; + 800988e: e0fd b.n 8009a8c + + case CTRL_DATA_IN: + /* Issue an IN token */ + phost->Control.timer = (uint16_t)phost->Timer; + 8009890: 687b ldr r3, [r7, #4] + 8009892: f8d3 33c4 ldr.w r3, [r3, #964] ; 0x3c4 + 8009896: b29a uxth r2, r3 + 8009898: 687b ldr r3, [r7, #4] + 800989a: 81da strh r2, [r3, #14] + USBH_CtlReceiveData(phost, phost->Control.buff, phost->Control.length, + 800989c: 687b ldr r3, [r7, #4] + 800989e: 6899 ldr r1, [r3, #8] + 80098a0: 687b ldr r3, [r7, #4] + 80098a2: 899a ldrh r2, [r3, #12] + 80098a4: 687b ldr r3, [r7, #4] + 80098a6: 791b ldrb r3, [r3, #4] + 80098a8: 6878 ldr r0, [r7, #4] + 80098aa: f000 f93c bl 8009b26 + phost->Control.pipe_in); + + phost->Control.state = CTRL_DATA_IN_WAIT; + 80098ae: 687b ldr r3, [r7, #4] + 80098b0: 2204 movs r2, #4 + 80098b2: 761a strb r2, [r3, #24] + break; + 80098b4: e0f3 b.n 8009a9e + + case CTRL_DATA_IN_WAIT: + + URB_Status = USBH_LL_GetURBState(phost, phost->Control.pipe_in); + 80098b6: 687b ldr r3, [r7, #4] + 80098b8: 791b ldrb r3, [r3, #4] + 80098ba: 4619 mov r1, r3 + 80098bc: 6878 ldr r0, [r7, #4] + 80098be: f000 fc7d bl 800a1bc + 80098c2: 4603 mov r3, r0 + 80098c4: 73bb strb r3, [r7, #14] + + /* check is DATA packet transferred successfully */ + if (URB_Status == USBH_URB_DONE) + 80098c6: 7bbb ldrb r3, [r7, #14] + 80098c8: 2b01 cmp r3, #1 + 80098ca: d102 bne.n 80098d2 + { + phost->Control.state = CTRL_STATUS_OUT; + 80098cc: 687b ldr r3, [r7, #4] + 80098ce: 2209 movs r2, #9 + 80098d0: 761a strb r2, [r3, #24] +#endif +#endif + } + + /* manage error cases*/ + if (URB_Status == USBH_URB_STALL) + 80098d2: 7bbb ldrb r3, [r7, #14] + 80098d4: 2b05 cmp r3, #5 + 80098d6: d102 bne.n 80098de + { + /* In stall case, return to previous machine state*/ + status = USBH_NOT_SUPPORTED; + 80098d8: 2303 movs r3, #3 + 80098da: 73fb strb r3, [r7, #15] + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + } + } + break; + 80098dc: e0d8 b.n 8009a90 + if (URB_Status == USBH_URB_ERROR) + 80098de: 7bbb ldrb r3, [r7, #14] + 80098e0: 2b04 cmp r3, #4 + 80098e2: f040 80d5 bne.w 8009a90 + phost->Control.state = CTRL_ERROR; + 80098e6: 687b ldr r3, [r7, #4] + 80098e8: 220b movs r2, #11 + 80098ea: 761a strb r2, [r3, #24] + break; + 80098ec: e0d0 b.n 8009a90 + + case CTRL_DATA_OUT: + + USBH_CtlSendData(phost, phost->Control.buff, phost->Control.length, + 80098ee: 687b ldr r3, [r7, #4] + 80098f0: 6899 ldr r1, [r3, #8] + 80098f2: 687b ldr r3, [r7, #4] + 80098f4: 899a ldrh r2, [r3, #12] + 80098f6: 687b ldr r3, [r7, #4] + 80098f8: 7958 ldrb r0, [r3, #5] + 80098fa: 2301 movs r3, #1 + 80098fc: 9300 str r3, [sp, #0] + 80098fe: 4603 mov r3, r0 + 8009900: 6878 ldr r0, [r7, #4] + 8009902: f000 f8eb bl 8009adc + phost->Control.pipe_out, 1U); + + phost->Control.timer = (uint16_t)phost->Timer; + 8009906: 687b ldr r3, [r7, #4] + 8009908: f8d3 33c4 ldr.w r3, [r3, #964] ; 0x3c4 + 800990c: b29a uxth r2, r3 + 800990e: 687b ldr r3, [r7, #4] + 8009910: 81da strh r2, [r3, #14] + phost->Control.state = CTRL_DATA_OUT_WAIT; + 8009912: 687b ldr r3, [r7, #4] + 8009914: 2206 movs r2, #6 + 8009916: 761a strb r2, [r3, #24] + break; + 8009918: e0c1 b.n 8009a9e + + case CTRL_DATA_OUT_WAIT: + + URB_Status = USBH_LL_GetURBState(phost, phost->Control.pipe_out); + 800991a: 687b ldr r3, [r7, #4] + 800991c: 795b ldrb r3, [r3, #5] + 800991e: 4619 mov r1, r3 + 8009920: 6878 ldr r0, [r7, #4] + 8009922: f000 fc4b bl 800a1bc + 8009926: 4603 mov r3, r0 + 8009928: 73bb strb r3, [r7, #14] + + if (URB_Status == USBH_URB_DONE) + 800992a: 7bbb ldrb r3, [r7, #14] + 800992c: 2b01 cmp r3, #1 + 800992e: d103 bne.n 8009938 + { + /* If the Setup Pkt is sent successful, then change the state */ + phost->Control.state = CTRL_STATUS_IN; + 8009930: 687b ldr r3, [r7, #4] + 8009932: 2207 movs r2, #7 + 8009934: 761a strb r2, [r3, #24] + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + } + } + break; + 8009936: e0ad b.n 8009a94 + else if (URB_Status == USBH_URB_STALL) + 8009938: 7bbb ldrb r3, [r7, #14] + 800993a: 2b05 cmp r3, #5 + 800993c: d105 bne.n 800994a + phost->Control.state = CTRL_STALLED; + 800993e: 687b ldr r3, [r7, #4] + 8009940: 220c movs r2, #12 + 8009942: 761a strb r2, [r3, #24] + status = USBH_NOT_SUPPORTED; + 8009944: 2303 movs r3, #3 + 8009946: 73fb strb r3, [r7, #15] + break; + 8009948: e0a4 b.n 8009a94 + else if (URB_Status == USBH_URB_NOTREADY) + 800994a: 7bbb ldrb r3, [r7, #14] + 800994c: 2b02 cmp r3, #2 + 800994e: d103 bne.n 8009958 + phost->Control.state = CTRL_DATA_OUT; + 8009950: 687b ldr r3, [r7, #4] + 8009952: 2205 movs r2, #5 + 8009954: 761a strb r2, [r3, #24] + break; + 8009956: e09d b.n 8009a94 + if (URB_Status == USBH_URB_ERROR) + 8009958: 7bbb ldrb r3, [r7, #14] + 800995a: 2b04 cmp r3, #4 + 800995c: f040 809a bne.w 8009a94 + phost->Control.state = CTRL_ERROR; + 8009960: 687b ldr r3, [r7, #4] + 8009962: 220b movs r2, #11 + 8009964: 761a strb r2, [r3, #24] + status = USBH_FAIL; + 8009966: 2302 movs r3, #2 + 8009968: 73fb strb r3, [r7, #15] + break; + 800996a: e093 b.n 8009a94 + + case CTRL_STATUS_IN: + /* Send 0 bytes out packet */ + USBH_CtlReceiveData(phost, 0U, 0U, phost->Control.pipe_in); + 800996c: 687b ldr r3, [r7, #4] + 800996e: 791b ldrb r3, [r3, #4] + 8009970: 2200 movs r2, #0 + 8009972: 2100 movs r1, #0 + 8009974: 6878 ldr r0, [r7, #4] + 8009976: f000 f8d6 bl 8009b26 + + phost->Control.timer = (uint16_t)phost->Timer; + 800997a: 687b ldr r3, [r7, #4] + 800997c: f8d3 33c4 ldr.w r3, [r3, #964] ; 0x3c4 + 8009980: b29a uxth r2, r3 + 8009982: 687b ldr r3, [r7, #4] + 8009984: 81da strh r2, [r3, #14] + phost->Control.state = CTRL_STATUS_IN_WAIT; + 8009986: 687b ldr r3, [r7, #4] + 8009988: 2208 movs r2, #8 + 800998a: 761a strb r2, [r3, #24] + + break; + 800998c: e087 b.n 8009a9e + + case CTRL_STATUS_IN_WAIT: + + URB_Status = USBH_LL_GetURBState(phost, phost->Control.pipe_in); + 800998e: 687b ldr r3, [r7, #4] + 8009990: 791b ldrb r3, [r3, #4] + 8009992: 4619 mov r1, r3 + 8009994: 6878 ldr r0, [r7, #4] + 8009996: f000 fc11 bl 800a1bc + 800999a: 4603 mov r3, r0 + 800999c: 73bb strb r3, [r7, #14] + + if (URB_Status == USBH_URB_DONE) + 800999e: 7bbb ldrb r3, [r7, #14] + 80099a0: 2b01 cmp r3, #1 + 80099a2: d105 bne.n 80099b0 + { + /* Control transfers completed, Exit the State Machine */ + phost->Control.state = CTRL_COMPLETE; + 80099a4: 687b ldr r3, [r7, #4] + 80099a6: 220d movs r2, #13 + 80099a8: 761a strb r2, [r3, #24] + status = USBH_OK; + 80099aa: 2300 movs r3, #0 + 80099ac: 73fb strb r3, [r7, #15] + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + } + } + break; + 80099ae: e073 b.n 8009a98 + else if (URB_Status == USBH_URB_ERROR) + 80099b0: 7bbb ldrb r3, [r7, #14] + 80099b2: 2b04 cmp r3, #4 + 80099b4: d103 bne.n 80099be + phost->Control.state = CTRL_ERROR; + 80099b6: 687b ldr r3, [r7, #4] + 80099b8: 220b movs r2, #11 + 80099ba: 761a strb r2, [r3, #24] + break; + 80099bc: e06c b.n 8009a98 + if (URB_Status == USBH_URB_STALL) + 80099be: 7bbb ldrb r3, [r7, #14] + 80099c0: 2b05 cmp r3, #5 + 80099c2: d169 bne.n 8009a98 + status = USBH_NOT_SUPPORTED; + 80099c4: 2303 movs r3, #3 + 80099c6: 73fb strb r3, [r7, #15] + break; + 80099c8: e066 b.n 8009a98 + + case CTRL_STATUS_OUT: + USBH_CtlSendData(phost, 0U, 0U, phost->Control.pipe_out, 1U); + 80099ca: 687b ldr r3, [r7, #4] + 80099cc: 795a ldrb r2, [r3, #5] + 80099ce: 2301 movs r3, #1 + 80099d0: 9300 str r3, [sp, #0] + 80099d2: 4613 mov r3, r2 + 80099d4: 2200 movs r2, #0 + 80099d6: 2100 movs r1, #0 + 80099d8: 6878 ldr r0, [r7, #4] + 80099da: f000 f87f bl 8009adc + + phost->Control.timer = (uint16_t)phost->Timer; + 80099de: 687b ldr r3, [r7, #4] + 80099e0: f8d3 33c4 ldr.w r3, [r3, #964] ; 0x3c4 + 80099e4: b29a uxth r2, r3 + 80099e6: 687b ldr r3, [r7, #4] + 80099e8: 81da strh r2, [r3, #14] + phost->Control.state = CTRL_STATUS_OUT_WAIT; + 80099ea: 687b ldr r3, [r7, #4] + 80099ec: 220a movs r2, #10 + 80099ee: 761a strb r2, [r3, #24] + break; + 80099f0: e055 b.n 8009a9e + + case CTRL_STATUS_OUT_WAIT: + URB_Status = USBH_LL_GetURBState(phost, phost->Control.pipe_out); + 80099f2: 687b ldr r3, [r7, #4] + 80099f4: 795b ldrb r3, [r3, #5] + 80099f6: 4619 mov r1, r3 + 80099f8: 6878 ldr r0, [r7, #4] + 80099fa: f000 fbdf bl 800a1bc + 80099fe: 4603 mov r3, r0 + 8009a00: 73bb strb r3, [r7, #14] + if (URB_Status == USBH_URB_DONE) + 8009a02: 7bbb ldrb r3, [r7, #14] + 8009a04: 2b01 cmp r3, #1 + 8009a06: d105 bne.n 8009a14 + { + status = USBH_OK; + 8009a08: 2300 movs r3, #0 + 8009a0a: 73fb strb r3, [r7, #15] + phost->Control.state = CTRL_COMPLETE; + 8009a0c: 687b ldr r3, [r7, #4] + 8009a0e: 220d movs r2, #13 + 8009a10: 761a strb r2, [r3, #24] + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + } + } + break; + 8009a12: e043 b.n 8009a9c + else if (URB_Status == USBH_URB_NOTREADY) + 8009a14: 7bbb ldrb r3, [r7, #14] + 8009a16: 2b02 cmp r3, #2 + 8009a18: d103 bne.n 8009a22 + phost->Control.state = CTRL_STATUS_OUT; + 8009a1a: 687b ldr r3, [r7, #4] + 8009a1c: 2209 movs r2, #9 + 8009a1e: 761a strb r2, [r3, #24] + break; + 8009a20: e03c b.n 8009a9c + if (URB_Status == USBH_URB_ERROR) + 8009a22: 7bbb ldrb r3, [r7, #14] + 8009a24: 2b04 cmp r3, #4 + 8009a26: d139 bne.n 8009a9c + phost->Control.state = CTRL_ERROR; + 8009a28: 687b ldr r3, [r7, #4] + 8009a2a: 220b movs r2, #11 + 8009a2c: 761a strb r2, [r3, #24] + break; + 8009a2e: e035 b.n 8009a9c + PID; i.e., recovery actions via some other pipe are not required for control + endpoints. For the Default Control Pipe, a device reset will ultimately be + required to clear the halt or error condition if the next Setup PID is not + accepted. + */ + if (++phost->Control.errorcount <= USBH_MAX_ERROR_COUNT) + 8009a30: 687b ldr r3, [r7, #4] + 8009a32: 7e5b ldrb r3, [r3, #25] + 8009a34: 3301 adds r3, #1 + 8009a36: b2da uxtb r2, r3 + 8009a38: 687b ldr r3, [r7, #4] + 8009a3a: 765a strb r2, [r3, #25] + 8009a3c: 687b ldr r3, [r7, #4] + 8009a3e: 7e5b ldrb r3, [r3, #25] + 8009a40: 2b02 cmp r3, #2 + 8009a42: d806 bhi.n 8009a52 + { + /* Do the transmission again, starting from SETUP Packet */ + phost->Control.state = CTRL_SETUP; + 8009a44: 687b ldr r3, [r7, #4] + 8009a46: 2201 movs r2, #1 + 8009a48: 761a strb r2, [r3, #24] + phost->RequestState = CMD_SEND; + 8009a4a: 687b ldr r3, [r7, #4] + 8009a4c: 2201 movs r2, #1 + 8009a4e: 709a strb r2, [r3, #2] + USBH_FreePipe(phost, phost->Control.pipe_in); + + phost->gState = HOST_IDLE; + status = USBH_FAIL; + } + break; + 8009a50: e025 b.n 8009a9e + phost->pUser(phost, HOST_USER_UNRECOVERED_ERROR); + 8009a52: 687b ldr r3, [r7, #4] + 8009a54: f8d3 33d4 ldr.w r3, [r3, #980] ; 0x3d4 + 8009a58: 2106 movs r1, #6 + 8009a5a: 6878 ldr r0, [r7, #4] + 8009a5c: 4798 blx r3 + phost->Control.errorcount = 0U; + 8009a5e: 687b ldr r3, [r7, #4] + 8009a60: 2200 movs r2, #0 + 8009a62: 765a strb r2, [r3, #25] + USBH_FreePipe(phost, phost->Control.pipe_out); + 8009a64: 687b ldr r3, [r7, #4] + 8009a66: 795b ldrb r3, [r3, #5] + 8009a68: 4619 mov r1, r3 + 8009a6a: 6878 ldr r0, [r7, #4] + 8009a6c: f000 f90c bl 8009c88 + USBH_FreePipe(phost, phost->Control.pipe_in); + 8009a70: 687b ldr r3, [r7, #4] + 8009a72: 791b ldrb r3, [r3, #4] + 8009a74: 4619 mov r1, r3 + 8009a76: 6878 ldr r0, [r7, #4] + 8009a78: f000 f906 bl 8009c88 + phost->gState = HOST_IDLE; + 8009a7c: 687b ldr r3, [r7, #4] + 8009a7e: 2200 movs r2, #0 + 8009a80: 701a strb r2, [r3, #0] + status = USBH_FAIL; + 8009a82: 2302 movs r3, #2 + 8009a84: 73fb strb r3, [r7, #15] + break; + 8009a86: e00a b.n 8009a9e + + default: + break; + 8009a88: bf00 nop + 8009a8a: e008 b.n 8009a9e + break; + 8009a8c: bf00 nop + 8009a8e: e006 b.n 8009a9e + break; + 8009a90: bf00 nop + 8009a92: e004 b.n 8009a9e + break; + 8009a94: bf00 nop + 8009a96: e002 b.n 8009a9e + break; + 8009a98: bf00 nop + 8009a9a: e000 b.n 8009a9e + break; + 8009a9c: bf00 nop + } + + return status; + 8009a9e: 7bfb ldrb r3, [r7, #15] +} + 8009aa0: 4618 mov r0, r3 + 8009aa2: 3710 adds r7, #16 + 8009aa4: 46bd mov sp, r7 + 8009aa6: bd80 pop {r7, pc} + +08009aa8 : + * @retval USBH Status + */ +USBH_StatusTypeDef USBH_CtlSendSetup(USBH_HandleTypeDef *phost, + uint8_t *buff, + uint8_t pipe_num) +{ + 8009aa8: b580 push {r7, lr} + 8009aaa: b088 sub sp, #32 + 8009aac: af04 add r7, sp, #16 + 8009aae: 60f8 str r0, [r7, #12] + 8009ab0: 60b9 str r1, [r7, #8] + 8009ab2: 4613 mov r3, r2 + 8009ab4: 71fb strb r3, [r7, #7] + + USBH_LL_SubmitURB(phost, /* Driver handle */ + 8009ab6: 79f9 ldrb r1, [r7, #7] + 8009ab8: 2300 movs r3, #0 + 8009aba: 9303 str r3, [sp, #12] + 8009abc: 2308 movs r3, #8 + 8009abe: 9302 str r3, [sp, #8] + 8009ac0: 68bb ldr r3, [r7, #8] + 8009ac2: 9301 str r3, [sp, #4] + 8009ac4: 2300 movs r3, #0 + 8009ac6: 9300 str r3, [sp, #0] + 8009ac8: 2300 movs r3, #0 + 8009aca: 2200 movs r2, #0 + 8009acc: 68f8 ldr r0, [r7, #12] + 8009ace: f000 fb44 bl 800a15a + USBH_EP_CONTROL, /* EP type */ + USBH_PID_SETUP, /* Type setup */ + buff, /* data buffer */ + USBH_SETUP_PKT_SIZE, /* data length */ + 0U); + return USBH_OK; + 8009ad2: 2300 movs r3, #0 +} + 8009ad4: 4618 mov r0, r3 + 8009ad6: 3710 adds r7, #16 + 8009ad8: 46bd mov sp, r7 + 8009ada: bd80 pop {r7, pc} + +08009adc : +USBH_StatusTypeDef USBH_CtlSendData(USBH_HandleTypeDef *phost, + uint8_t *buff, + uint16_t length, + uint8_t pipe_num, + uint8_t do_ping) +{ + 8009adc: b580 push {r7, lr} + 8009ade: b088 sub sp, #32 + 8009ae0: af04 add r7, sp, #16 + 8009ae2: 60f8 str r0, [r7, #12] + 8009ae4: 60b9 str r1, [r7, #8] + 8009ae6: 4611 mov r1, r2 + 8009ae8: 461a mov r2, r3 + 8009aea: 460b mov r3, r1 + 8009aec: 80fb strh r3, [r7, #6] + 8009aee: 4613 mov r3, r2 + 8009af0: 717b strb r3, [r7, #5] + if (phost->device.speed != USBH_SPEED_HIGH) + 8009af2: 68fb ldr r3, [r7, #12] + 8009af4: f893 331d ldrb.w r3, [r3, #797] ; 0x31d + 8009af8: 2b00 cmp r3, #0 + 8009afa: d001 beq.n 8009b00 + { + do_ping = 0U; + 8009afc: 2300 movs r3, #0 + 8009afe: 763b strb r3, [r7, #24] + } + + USBH_LL_SubmitURB(phost, /* Driver handle */ + 8009b00: 7979 ldrb r1, [r7, #5] + 8009b02: 7e3b ldrb r3, [r7, #24] + 8009b04: 9303 str r3, [sp, #12] + 8009b06: 88fb ldrh r3, [r7, #6] + 8009b08: 9302 str r3, [sp, #8] + 8009b0a: 68bb ldr r3, [r7, #8] + 8009b0c: 9301 str r3, [sp, #4] + 8009b0e: 2301 movs r3, #1 + 8009b10: 9300 str r3, [sp, #0] + 8009b12: 2300 movs r3, #0 + 8009b14: 2200 movs r2, #0 + 8009b16: 68f8 ldr r0, [r7, #12] + 8009b18: f000 fb1f bl 800a15a + USBH_PID_DATA, /* Type Data */ + buff, /* data buffer */ + length, /* data length */ + do_ping); /* do ping (HS Only)*/ + + return USBH_OK; + 8009b1c: 2300 movs r3, #0 +} + 8009b1e: 4618 mov r0, r3 + 8009b20: 3710 adds r7, #16 + 8009b22: 46bd mov sp, r7 + 8009b24: bd80 pop {r7, pc} + +08009b26 : + */ +USBH_StatusTypeDef USBH_CtlReceiveData(USBH_HandleTypeDef *phost, + uint8_t *buff, + uint16_t length, + uint8_t pipe_num) +{ + 8009b26: b580 push {r7, lr} + 8009b28: b088 sub sp, #32 + 8009b2a: af04 add r7, sp, #16 + 8009b2c: 60f8 str r0, [r7, #12] + 8009b2e: 60b9 str r1, [r7, #8] + 8009b30: 4611 mov r1, r2 + 8009b32: 461a mov r2, r3 + 8009b34: 460b mov r3, r1 + 8009b36: 80fb strh r3, [r7, #6] + 8009b38: 4613 mov r3, r2 + 8009b3a: 717b strb r3, [r7, #5] + USBH_LL_SubmitURB(phost, /* Driver handle */ + 8009b3c: 7979 ldrb r1, [r7, #5] + 8009b3e: 2300 movs r3, #0 + 8009b40: 9303 str r3, [sp, #12] + 8009b42: 88fb ldrh r3, [r7, #6] + 8009b44: 9302 str r3, [sp, #8] + 8009b46: 68bb ldr r3, [r7, #8] + 8009b48: 9301 str r3, [sp, #4] + 8009b4a: 2301 movs r3, #1 + 8009b4c: 9300 str r3, [sp, #0] + 8009b4e: 2300 movs r3, #0 + 8009b50: 2201 movs r2, #1 + 8009b52: 68f8 ldr r0, [r7, #12] + 8009b54: f000 fb01 bl 800a15a + USBH_EP_CONTROL, /* EP type */ + USBH_PID_DATA, /* Type Data */ + buff, /* data buffer */ + length, /* data length */ + 0U); + return USBH_OK; + 8009b58: 2300 movs r3, #0 + +} + 8009b5a: 4618 mov r0, r3 + 8009b5c: 3710 adds r7, #16 + 8009b5e: 46bd mov sp, r7 + 8009b60: bd80 pop {r7, pc} + +08009b62 : +USBH_StatusTypeDef USBH_BulkSendData(USBH_HandleTypeDef *phost, + uint8_t *buff, + uint16_t length, + uint8_t pipe_num, + uint8_t do_ping) +{ + 8009b62: b580 push {r7, lr} + 8009b64: b088 sub sp, #32 + 8009b66: af04 add r7, sp, #16 + 8009b68: 60f8 str r0, [r7, #12] + 8009b6a: 60b9 str r1, [r7, #8] + 8009b6c: 4611 mov r1, r2 + 8009b6e: 461a mov r2, r3 + 8009b70: 460b mov r3, r1 + 8009b72: 80fb strh r3, [r7, #6] + 8009b74: 4613 mov r3, r2 + 8009b76: 717b strb r3, [r7, #5] + if (phost->device.speed != USBH_SPEED_HIGH) + 8009b78: 68fb ldr r3, [r7, #12] + 8009b7a: f893 331d ldrb.w r3, [r3, #797] ; 0x31d + 8009b7e: 2b00 cmp r3, #0 + 8009b80: d001 beq.n 8009b86 + { + do_ping = 0U; + 8009b82: 2300 movs r3, #0 + 8009b84: 763b strb r3, [r7, #24] + } + + USBH_LL_SubmitURB(phost, /* Driver handle */ + 8009b86: 7979 ldrb r1, [r7, #5] + 8009b88: 7e3b ldrb r3, [r7, #24] + 8009b8a: 9303 str r3, [sp, #12] + 8009b8c: 88fb ldrh r3, [r7, #6] + 8009b8e: 9302 str r3, [sp, #8] + 8009b90: 68bb ldr r3, [r7, #8] + 8009b92: 9301 str r3, [sp, #4] + 8009b94: 2301 movs r3, #1 + 8009b96: 9300 str r3, [sp, #0] + 8009b98: 2302 movs r3, #2 + 8009b9a: 2200 movs r2, #0 + 8009b9c: 68f8 ldr r0, [r7, #12] + 8009b9e: f000 fadc bl 800a15a + USBH_EP_BULK, /* EP type */ + USBH_PID_DATA, /* Type Data */ + buff, /* data buffer */ + length, /* data length */ + do_ping); /* do ping (HS Only)*/ + return USBH_OK; + 8009ba2: 2300 movs r3, #0 +} + 8009ba4: 4618 mov r0, r3 + 8009ba6: 3710 adds r7, #16 + 8009ba8: 46bd mov sp, r7 + 8009baa: bd80 pop {r7, pc} + +08009bac : + */ +USBH_StatusTypeDef USBH_BulkReceiveData(USBH_HandleTypeDef *phost, + uint8_t *buff, + uint16_t length, + uint8_t pipe_num) +{ + 8009bac: b580 push {r7, lr} + 8009bae: b088 sub sp, #32 + 8009bb0: af04 add r7, sp, #16 + 8009bb2: 60f8 str r0, [r7, #12] + 8009bb4: 60b9 str r1, [r7, #8] + 8009bb6: 4611 mov r1, r2 + 8009bb8: 461a mov r2, r3 + 8009bba: 460b mov r3, r1 + 8009bbc: 80fb strh r3, [r7, #6] + 8009bbe: 4613 mov r3, r2 + 8009bc0: 717b strb r3, [r7, #5] + USBH_LL_SubmitURB(phost, /* Driver handle */ + 8009bc2: 7979 ldrb r1, [r7, #5] + 8009bc4: 2300 movs r3, #0 + 8009bc6: 9303 str r3, [sp, #12] + 8009bc8: 88fb ldrh r3, [r7, #6] + 8009bca: 9302 str r3, [sp, #8] + 8009bcc: 68bb ldr r3, [r7, #8] + 8009bce: 9301 str r3, [sp, #4] + 8009bd0: 2301 movs r3, #1 + 8009bd2: 9300 str r3, [sp, #0] + 8009bd4: 2302 movs r3, #2 + 8009bd6: 2201 movs r2, #1 + 8009bd8: 68f8 ldr r0, [r7, #12] + 8009bda: f000 fabe bl 800a15a + USBH_EP_BULK, /* EP type */ + USBH_PID_DATA, /* Type Data */ + buff, /* data buffer */ + length, /* data length */ + 0U); + return USBH_OK; + 8009bde: 2300 movs r3, #0 +} + 8009be0: 4618 mov r0, r3 + 8009be2: 3710 adds r7, #16 + 8009be4: 46bd mov sp, r7 + 8009be6: bd80 pop {r7, pc} + +08009be8 : + * @retval USBH Status + */ +USBH_StatusTypeDef USBH_OpenPipe(USBH_HandleTypeDef *phost, uint8_t pipe_num, + uint8_t epnum, uint8_t dev_address, + uint8_t speed, uint8_t ep_type, uint16_t mps) +{ + 8009be8: b580 push {r7, lr} + 8009bea: b086 sub sp, #24 + 8009bec: af04 add r7, sp, #16 + 8009bee: 6078 str r0, [r7, #4] + 8009bf0: 4608 mov r0, r1 + 8009bf2: 4611 mov r1, r2 + 8009bf4: 461a mov r2, r3 + 8009bf6: 4603 mov r3, r0 + 8009bf8: 70fb strb r3, [r7, #3] + 8009bfa: 460b mov r3, r1 + 8009bfc: 70bb strb r3, [r7, #2] + 8009bfe: 4613 mov r3, r2 + 8009c00: 707b strb r3, [r7, #1] + USBH_LL_OpenPipe(phost, pipe_num, epnum, dev_address, speed, ep_type, mps); + 8009c02: 7878 ldrb r0, [r7, #1] + 8009c04: 78ba ldrb r2, [r7, #2] + 8009c06: 78f9 ldrb r1, [r7, #3] + 8009c08: 8b3b ldrh r3, [r7, #24] + 8009c0a: 9302 str r3, [sp, #8] + 8009c0c: 7d3b ldrb r3, [r7, #20] + 8009c0e: 9301 str r3, [sp, #4] + 8009c10: 7c3b ldrb r3, [r7, #16] + 8009c12: 9300 str r3, [sp, #0] + 8009c14: 4603 mov r3, r0 + 8009c16: 6878 ldr r0, [r7, #4] + 8009c18: f000 fa51 bl 800a0be + + return USBH_OK; + 8009c1c: 2300 movs r3, #0 +} + 8009c1e: 4618 mov r0, r3 + 8009c20: 3708 adds r7, #8 + 8009c22: 46bd mov sp, r7 + 8009c24: bd80 pop {r7, pc} + +08009c26 : + * @param phost: Host Handle + * @param pipe_num: Pipe Number + * @retval USBH Status + */ +USBH_StatusTypeDef USBH_ClosePipe(USBH_HandleTypeDef *phost, uint8_t pipe_num) +{ + 8009c26: b580 push {r7, lr} + 8009c28: b082 sub sp, #8 + 8009c2a: af00 add r7, sp, #0 + 8009c2c: 6078 str r0, [r7, #4] + 8009c2e: 460b mov r3, r1 + 8009c30: 70fb strb r3, [r7, #3] + USBH_LL_ClosePipe(phost, pipe_num); + 8009c32: 78fb ldrb r3, [r7, #3] + 8009c34: 4619 mov r1, r3 + 8009c36: 6878 ldr r0, [r7, #4] + 8009c38: f000 fa70 bl 800a11c + + return USBH_OK; + 8009c3c: 2300 movs r3, #0 +} + 8009c3e: 4618 mov r0, r3 + 8009c40: 3708 adds r7, #8 + 8009c42: 46bd mov sp, r7 + 8009c44: bd80 pop {r7, pc} + +08009c46 : + * @param phost: Host Handle + * @param ep_addr: End point for which the Pipe to be allocated + * @retval Pipe number + */ +uint8_t USBH_AllocPipe(USBH_HandleTypeDef *phost, uint8_t ep_addr) +{ + 8009c46: b580 push {r7, lr} + 8009c48: b084 sub sp, #16 + 8009c4a: af00 add r7, sp, #0 + 8009c4c: 6078 str r0, [r7, #4] + 8009c4e: 460b mov r3, r1 + 8009c50: 70fb strb r3, [r7, #3] + uint16_t pipe; + + pipe = USBH_GetFreePipe(phost); + 8009c52: 6878 ldr r0, [r7, #4] + 8009c54: f000 f836 bl 8009cc4 + 8009c58: 4603 mov r3, r0 + 8009c5a: 81fb strh r3, [r7, #14] + + if (pipe != 0xFFFFU) + 8009c5c: 89fb ldrh r3, [r7, #14] + 8009c5e: f64f 72ff movw r2, #65535 ; 0xffff + 8009c62: 4293 cmp r3, r2 + 8009c64: d00a beq.n 8009c7c + { + phost->Pipes[pipe & 0xFU] = 0x8000U | ep_addr; + 8009c66: 78fa ldrb r2, [r7, #3] + 8009c68: 89fb ldrh r3, [r7, #14] + 8009c6a: f003 030f and.w r3, r3, #15 + 8009c6e: f442 4200 orr.w r2, r2, #32768 ; 0x8000 + 8009c72: 6879 ldr r1, [r7, #4] + 8009c74: 33e0 adds r3, #224 ; 0xe0 + 8009c76: 009b lsls r3, r3, #2 + 8009c78: 440b add r3, r1 + 8009c7a: 605a str r2, [r3, #4] + } + + return (uint8_t)pipe; + 8009c7c: 89fb ldrh r3, [r7, #14] + 8009c7e: b2db uxtb r3, r3 +} + 8009c80: 4618 mov r0, r3 + 8009c82: 3710 adds r7, #16 + 8009c84: 46bd mov sp, r7 + 8009c86: bd80 pop {r7, pc} + +08009c88 : + * @param phost: Host Handle + * @param idx: Pipe number to be freed + * @retval USBH Status + */ +USBH_StatusTypeDef USBH_FreePipe(USBH_HandleTypeDef *phost, uint8_t idx) +{ + 8009c88: b480 push {r7} + 8009c8a: b083 sub sp, #12 + 8009c8c: af00 add r7, sp, #0 + 8009c8e: 6078 str r0, [r7, #4] + 8009c90: 460b mov r3, r1 + 8009c92: 70fb strb r3, [r7, #3] + if (idx < 11U) + 8009c94: 78fb ldrb r3, [r7, #3] + 8009c96: 2b0a cmp r3, #10 + 8009c98: d80d bhi.n 8009cb6 + { + phost->Pipes[idx] &= 0x7FFFU; + 8009c9a: 78fb ldrb r3, [r7, #3] + 8009c9c: 687a ldr r2, [r7, #4] + 8009c9e: 33e0 adds r3, #224 ; 0xe0 + 8009ca0: 009b lsls r3, r3, #2 + 8009ca2: 4413 add r3, r2 + 8009ca4: 685a ldr r2, [r3, #4] + 8009ca6: 78fb ldrb r3, [r7, #3] + 8009ca8: f3c2 020e ubfx r2, r2, #0, #15 + 8009cac: 6879 ldr r1, [r7, #4] + 8009cae: 33e0 adds r3, #224 ; 0xe0 + 8009cb0: 009b lsls r3, r3, #2 + 8009cb2: 440b add r3, r1 + 8009cb4: 605a str r2, [r3, #4] + } + + return USBH_OK; + 8009cb6: 2300 movs r3, #0 +} + 8009cb8: 4618 mov r0, r3 + 8009cba: 370c adds r7, #12 + 8009cbc: 46bd mov sp, r7 + 8009cbe: f85d 7b04 ldr.w r7, [sp], #4 + 8009cc2: 4770 bx lr + +08009cc4 : + * @param phost: Host Handle + * Get a free Pipe number for allocation to a device endpoint + * @retval idx: Free Pipe number + */ +static uint16_t USBH_GetFreePipe(USBH_HandleTypeDef *phost) +{ + 8009cc4: b480 push {r7} + 8009cc6: b085 sub sp, #20 + 8009cc8: af00 add r7, sp, #0 + 8009cca: 6078 str r0, [r7, #4] + uint8_t idx = 0U; + 8009ccc: 2300 movs r3, #0 + 8009cce: 73fb strb r3, [r7, #15] + + for (idx = 0U ; idx < 11U ; idx++) + 8009cd0: 2300 movs r3, #0 + 8009cd2: 73fb strb r3, [r7, #15] + 8009cd4: e00f b.n 8009cf6 + { + if ((phost->Pipes[idx] & 0x8000U) == 0U) + 8009cd6: 7bfb ldrb r3, [r7, #15] + 8009cd8: 687a ldr r2, [r7, #4] + 8009cda: 33e0 adds r3, #224 ; 0xe0 + 8009cdc: 009b lsls r3, r3, #2 + 8009cde: 4413 add r3, r2 + 8009ce0: 685b ldr r3, [r3, #4] + 8009ce2: f403 4300 and.w r3, r3, #32768 ; 0x8000 + 8009ce6: 2b00 cmp r3, #0 + 8009ce8: d102 bne.n 8009cf0 + { + return (uint16_t)idx; + 8009cea: 7bfb ldrb r3, [r7, #15] + 8009cec: b29b uxth r3, r3 + 8009cee: e007 b.n 8009d00 + for (idx = 0U ; idx < 11U ; idx++) + 8009cf0: 7bfb ldrb r3, [r7, #15] + 8009cf2: 3301 adds r3, #1 + 8009cf4: 73fb strb r3, [r7, #15] + 8009cf6: 7bfb ldrb r3, [r7, #15] + 8009cf8: 2b0a cmp r3, #10 + 8009cfa: d9ec bls.n 8009cd6 + } + } + + return 0xFFFFU; + 8009cfc: f64f 73ff movw r3, #65535 ; 0xffff +} + 8009d00: 4618 mov r0, r3 + 8009d02: 3714 adds r7, #20 + 8009d04: 46bd mov sp, r7 + 8009d06: f85d 7b04 ldr.w r7, [sp], #4 + 8009d0a: 4770 bx lr + +08009d0c : +/** + * Init USB host library, add supported class and start the library + * @retval None + */ +void MX_USB_HOST_Init(void) +{ + 8009d0c: b580 push {r7, lr} + 8009d0e: af00 add r7, sp, #0 + /* USER CODE BEGIN USB_HOST_Init_PreTreatment */ + + /* USER CODE END USB_HOST_Init_PreTreatment */ + + /* Init host Library, add supported class and start the library. */ + if (USBH_Init(&hUsbHostFS, USBH_UserProcess, HOST_FS) != USBH_OK) + 8009d10: 2201 movs r2, #1 + 8009d12: 490e ldr r1, [pc, #56] ; (8009d4c ) + 8009d14: 480e ldr r0, [pc, #56] ; (8009d50 ) + 8009d16: f7fe fc9f bl 8008658 + 8009d1a: 4603 mov r3, r0 + 8009d1c: 2b00 cmp r3, #0 + 8009d1e: d001 beq.n 8009d24 + { + Error_Handler(); + 8009d20: f7f7 fcba bl 8001698 + } + if (USBH_RegisterClass(&hUsbHostFS, USBH_CDC_CLASS) != USBH_OK) + 8009d24: 490b ldr r1, [pc, #44] ; (8009d54 ) + 8009d26: 480a ldr r0, [pc, #40] ; (8009d50 ) + 8009d28: f7fe fd24 bl 8008774 + 8009d2c: 4603 mov r3, r0 + 8009d2e: 2b00 cmp r3, #0 + 8009d30: d001 beq.n 8009d36 + { + Error_Handler(); + 8009d32: f7f7 fcb1 bl 8001698 + } + if (USBH_Start(&hUsbHostFS) != USBH_OK) + 8009d36: 4806 ldr r0, [pc, #24] ; (8009d50 ) + 8009d38: f7fe fda8 bl 800888c + 8009d3c: 4603 mov r3, r0 + 8009d3e: 2b00 cmp r3, #0 + 8009d40: d001 beq.n 8009d46 + { + Error_Handler(); + 8009d42: f7f7 fca9 bl 8001698 + } + /* USER CODE BEGIN USB_HOST_Init_PostTreatment */ + + /* USER CODE END USB_HOST_Init_PostTreatment */ +} + 8009d46: bf00 nop + 8009d48: bd80 pop {r7, pc} + 8009d4a: bf00 nop + 8009d4c: 08009d6d .word 0x08009d6d + 8009d50: 20000414 .word 0x20000414 + 8009d54: 2000000c .word 0x2000000c + +08009d58 : + +/* + * Background task + */ +void MX_USB_HOST_Process(void) +{ + 8009d58: b580 push {r7, lr} + 8009d5a: af00 add r7, sp, #0 + /* USB Host Background task */ + USBH_Process(&hUsbHostFS); + 8009d5c: 4802 ldr r0, [pc, #8] ; (8009d68 ) + 8009d5e: f7fe fda5 bl 80088ac +} + 8009d62: bf00 nop + 8009d64: bd80 pop {r7, pc} + 8009d66: bf00 nop + 8009d68: 20000414 .word 0x20000414 + +08009d6c : +/* + * user callback definition + */ +static void USBH_UserProcess (USBH_HandleTypeDef *phost, uint8_t id) +{ + 8009d6c: b480 push {r7} + 8009d6e: b083 sub sp, #12 + 8009d70: af00 add r7, sp, #0 + 8009d72: 6078 str r0, [r7, #4] + 8009d74: 460b mov r3, r1 + 8009d76: 70fb strb r3, [r7, #3] + /* USER CODE BEGIN CALL_BACK_1 */ + switch(id) + 8009d78: 78fb ldrb r3, [r7, #3] + 8009d7a: 3b01 subs r3, #1 + 8009d7c: 2b04 cmp r3, #4 + 8009d7e: d819 bhi.n 8009db4 + 8009d80: a201 add r2, pc, #4 ; (adr r2, 8009d88 ) + 8009d82: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8009d86: bf00 nop + 8009d88: 08009db5 .word 0x08009db5 + 8009d8c: 08009da5 .word 0x08009da5 + 8009d90: 08009db5 .word 0x08009db5 + 8009d94: 08009dad .word 0x08009dad + 8009d98: 08009d9d .word 0x08009d9d + { + case HOST_USER_SELECT_CONFIGURATION: + break; + + case HOST_USER_DISCONNECTION: + Appli_state = APPLICATION_DISCONNECT; + 8009d9c: 4b09 ldr r3, [pc, #36] ; (8009dc4 ) + 8009d9e: 2203 movs r2, #3 + 8009da0: 701a strb r2, [r3, #0] + break; + 8009da2: e008 b.n 8009db6 + + case HOST_USER_CLASS_ACTIVE: + Appli_state = APPLICATION_READY; + 8009da4: 4b07 ldr r3, [pc, #28] ; (8009dc4 ) + 8009da6: 2202 movs r2, #2 + 8009da8: 701a strb r2, [r3, #0] + break; + 8009daa: e004 b.n 8009db6 + + case HOST_USER_CONNECTION: + Appli_state = APPLICATION_START; + 8009dac: 4b05 ldr r3, [pc, #20] ; (8009dc4 ) + 8009dae: 2201 movs r2, #1 + 8009db0: 701a strb r2, [r3, #0] + break; + 8009db2: e000 b.n 8009db6 + + default: + break; + 8009db4: bf00 nop + } + /* USER CODE END CALL_BACK_1 */ +} + 8009db6: bf00 nop + 8009db8: 370c adds r7, #12 + 8009dba: 46bd mov sp, r7 + 8009dbc: f85d 7b04 ldr.w r7, [sp], #4 + 8009dc0: 4770 bx lr + 8009dc2: bf00 nop + 8009dc4: 20000230 .word 0x20000230 + +08009dc8 : + LL Driver Callbacks (HCD -> USB Host Library) +*******************************************************************************/ +/* MSP Init */ + +void HAL_HCD_MspInit(HCD_HandleTypeDef* hcdHandle) +{ + 8009dc8: b580 push {r7, lr} + 8009dca: b08a sub sp, #40 ; 0x28 + 8009dcc: af00 add r7, sp, #0 + 8009dce: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8009dd0: f107 0314 add.w r3, r7, #20 + 8009dd4: 2200 movs r2, #0 + 8009dd6: 601a str r2, [r3, #0] + 8009dd8: 605a str r2, [r3, #4] + 8009dda: 609a str r2, [r3, #8] + 8009ddc: 60da str r2, [r3, #12] + 8009dde: 611a str r2, [r3, #16] + if(hcdHandle->Instance==USB_OTG_FS) + 8009de0: 687b ldr r3, [r7, #4] + 8009de2: 681b ldr r3, [r3, #0] + 8009de4: f1b3 4fa0 cmp.w r3, #1342177280 ; 0x50000000 + 8009de8: d147 bne.n 8009e7a + { + /* USER CODE BEGIN USB_OTG_FS_MspInit 0 */ + + /* USER CODE END USB_OTG_FS_MspInit 0 */ + + __HAL_RCC_GPIOA_CLK_ENABLE(); + 8009dea: 2300 movs r3, #0 + 8009dec: 613b str r3, [r7, #16] + 8009dee: 4b25 ldr r3, [pc, #148] ; (8009e84 ) + 8009df0: 6b1b ldr r3, [r3, #48] ; 0x30 + 8009df2: 4a24 ldr r2, [pc, #144] ; (8009e84 ) + 8009df4: f043 0301 orr.w r3, r3, #1 + 8009df8: 6313 str r3, [r2, #48] ; 0x30 + 8009dfa: 4b22 ldr r3, [pc, #136] ; (8009e84 ) + 8009dfc: 6b1b ldr r3, [r3, #48] ; 0x30 + 8009dfe: f003 0301 and.w r3, r3, #1 + 8009e02: 613b str r3, [r7, #16] + 8009e04: 693b ldr r3, [r7, #16] + PA9 ------> USB_OTG_FS_VBUS + PA10 ------> USB_OTG_FS_ID + PA11 ------> USB_OTG_FS_DM + PA12 ------> USB_OTG_FS_DP + */ + GPIO_InitStruct.Pin = VBUS_FS_Pin; + 8009e06: f44f 7300 mov.w r3, #512 ; 0x200 + 8009e0a: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + 8009e0c: 2300 movs r3, #0 + 8009e0e: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8009e10: 2300 movs r3, #0 + 8009e12: 61fb str r3, [r7, #28] + HAL_GPIO_Init(VBUS_FS_GPIO_Port, &GPIO_InitStruct); + 8009e14: f107 0314 add.w r3, r7, #20 + 8009e18: 4619 mov r1, r3 + 8009e1a: 481b ldr r0, [pc, #108] ; (8009e88 ) + 8009e1c: f7f8 fbbe bl 800259c + + GPIO_InitStruct.Pin = OTG_FS_ID_Pin|OTG_FS_DM_Pin|OTG_FS_DP_Pin; + 8009e20: f44f 53e0 mov.w r3, #7168 ; 0x1c00 + 8009e24: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8009e26: 2302 movs r3, #2 + 8009e28: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8009e2a: 2300 movs r3, #0 + 8009e2c: 61fb str r3, [r7, #28] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 8009e2e: 2303 movs r3, #3 + 8009e30: 623b str r3, [r7, #32] + GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; + 8009e32: 230a movs r3, #10 + 8009e34: 627b str r3, [r7, #36] ; 0x24 + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 8009e36: f107 0314 add.w r3, r7, #20 + 8009e3a: 4619 mov r1, r3 + 8009e3c: 4812 ldr r0, [pc, #72] ; (8009e88 ) + 8009e3e: f7f8 fbad bl 800259c + + /* Peripheral clock enable */ + __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); + 8009e42: 4b10 ldr r3, [pc, #64] ; (8009e84 ) + 8009e44: 6b5b ldr r3, [r3, #52] ; 0x34 + 8009e46: 4a0f ldr r2, [pc, #60] ; (8009e84 ) + 8009e48: f043 0380 orr.w r3, r3, #128 ; 0x80 + 8009e4c: 6353 str r3, [r2, #52] ; 0x34 + 8009e4e: 2300 movs r3, #0 + 8009e50: 60fb str r3, [r7, #12] + 8009e52: 4b0c ldr r3, [pc, #48] ; (8009e84 ) + 8009e54: 6c5b ldr r3, [r3, #68] ; 0x44 + 8009e56: 4a0b ldr r2, [pc, #44] ; (8009e84 ) + 8009e58: f443 4380 orr.w r3, r3, #16384 ; 0x4000 + 8009e5c: 6453 str r3, [r2, #68] ; 0x44 + 8009e5e: 4b09 ldr r3, [pc, #36] ; (8009e84 ) + 8009e60: 6c5b ldr r3, [r3, #68] ; 0x44 + 8009e62: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 8009e66: 60fb str r3, [r7, #12] + 8009e68: 68fb ldr r3, [r7, #12] + + /* Peripheral interrupt init */ + HAL_NVIC_SetPriority(OTG_FS_IRQn, 0, 0); + 8009e6a: 2200 movs r2, #0 + 8009e6c: 2100 movs r1, #0 + 8009e6e: 2043 movs r0, #67 ; 0x43 + 8009e70: f7f8 fb5d bl 800252e + HAL_NVIC_EnableIRQ(OTG_FS_IRQn); + 8009e74: 2043 movs r0, #67 ; 0x43 + 8009e76: f7f8 fb76 bl 8002566 + /* USER CODE BEGIN USB_OTG_FS_MspInit 1 */ + + /* USER CODE END USB_OTG_FS_MspInit 1 */ + } +} + 8009e7a: bf00 nop + 8009e7c: 3728 adds r7, #40 ; 0x28 + 8009e7e: 46bd mov sp, r7 + 8009e80: bd80 pop {r7, pc} + 8009e82: bf00 nop + 8009e84: 40023800 .word 0x40023800 + 8009e88: 40020000 .word 0x40020000 + +08009e8c : + * @brief SOF callback. + * @param hhcd: HCD handle + * @retval None + */ +void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd) +{ + 8009e8c: b580 push {r7, lr} + 8009e8e: b082 sub sp, #8 + 8009e90: af00 add r7, sp, #0 + 8009e92: 6078 str r0, [r7, #4] + USBH_LL_IncTimer(hhcd->pData); + 8009e94: 687b ldr r3, [r7, #4] + 8009e96: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0 + 8009e9a: 4618 mov r0, r3 + 8009e9c: f7ff f8d9 bl 8009052 +} + 8009ea0: bf00 nop + 8009ea2: 3708 adds r7, #8 + 8009ea4: 46bd mov sp, r7 + 8009ea6: bd80 pop {r7, pc} + +08009ea8 : + * @brief SOF callback. + * @param hhcd: HCD handle + * @retval None + */ +void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd) +{ + 8009ea8: b580 push {r7, lr} + 8009eaa: b082 sub sp, #8 + 8009eac: af00 add r7, sp, #0 + 8009eae: 6078 str r0, [r7, #4] + USBH_LL_Connect(hhcd->pData); + 8009eb0: 687b ldr r3, [r7, #4] + 8009eb2: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0 + 8009eb6: 4618 mov r0, r3 + 8009eb8: f7ff f911 bl 80090de +} + 8009ebc: bf00 nop + 8009ebe: 3708 adds r7, #8 + 8009ec0: 46bd mov sp, r7 + 8009ec2: bd80 pop {r7, pc} + +08009ec4 : + * @brief SOF callback. + * @param hhcd: HCD handle + * @retval None + */ +void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd) +{ + 8009ec4: b580 push {r7, lr} + 8009ec6: b082 sub sp, #8 + 8009ec8: af00 add r7, sp, #0 + 8009eca: 6078 str r0, [r7, #4] + USBH_LL_Disconnect(hhcd->pData); + 8009ecc: 687b ldr r3, [r7, #4] + 8009ece: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0 + 8009ed2: 4618 mov r0, r3 + 8009ed4: f7ff f91a bl 800910c +} + 8009ed8: bf00 nop + 8009eda: 3708 adds r7, #8 + 8009edc: 46bd mov sp, r7 + 8009ede: bd80 pop {r7, pc} + +08009ee0 : + * @param chnum: channel number + * @param urb_state: state + * @retval None + */ +void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state) +{ + 8009ee0: b480 push {r7} + 8009ee2: b083 sub sp, #12 + 8009ee4: af00 add r7, sp, #0 + 8009ee6: 6078 str r0, [r7, #4] + 8009ee8: 460b mov r3, r1 + 8009eea: 70fb strb r3, [r7, #3] + 8009eec: 4613 mov r3, r2 + 8009eee: 70bb strb r3, [r7, #2] + /* To be used with OS to sync URB state with the global state machine */ +#if (USBH_USE_OS == 1) + USBH_LL_NotifyURBChange(hhcd->pData); +#endif +} + 8009ef0: bf00 nop + 8009ef2: 370c adds r7, #12 + 8009ef4: 46bd mov sp, r7 + 8009ef6: f85d 7b04 ldr.w r7, [sp], #4 + 8009efa: 4770 bx lr + +08009efc : +* @brief Port Port Enabled callback. + * @param hhcd: HCD handle + * @retval None + */ +void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd) +{ + 8009efc: b580 push {r7, lr} + 8009efe: b082 sub sp, #8 + 8009f00: af00 add r7, sp, #0 + 8009f02: 6078 str r0, [r7, #4] + USBH_LL_PortEnabled(hhcd->pData); + 8009f04: 687b ldr r3, [r7, #4] + 8009f06: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0 + 8009f0a: 4618 mov r0, r3 + 8009f0c: f7ff f8cb bl 80090a6 +} + 8009f10: bf00 nop + 8009f12: 3708 adds r7, #8 + 8009f14: 46bd mov sp, r7 + 8009f16: bd80 pop {r7, pc} + +08009f18 : + * @brief Port Port Disabled callback. + * @param hhcd: HCD handle + * @retval None + */ +void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd) +{ + 8009f18: b580 push {r7, lr} + 8009f1a: b082 sub sp, #8 + 8009f1c: af00 add r7, sp, #0 + 8009f1e: 6078 str r0, [r7, #4] + USBH_LL_PortDisabled(hhcd->pData); + 8009f20: 687b ldr r3, [r7, #4] + 8009f22: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0 + 8009f26: 4618 mov r0, r3 + 8009f28: f7ff f8cb bl 80090c2 +} + 8009f2c: bf00 nop + 8009f2e: 3708 adds r7, #8 + 8009f30: 46bd mov sp, r7 + 8009f32: bd80 pop {r7, pc} + +08009f34 : + * @brief Initialize the low level portion of the host driver. + * @param phost: Host handle + * @retval USBH status + */ +USBH_StatusTypeDef USBH_LL_Init(USBH_HandleTypeDef *phost) +{ + 8009f34: b580 push {r7, lr} + 8009f36: b082 sub sp, #8 + 8009f38: af00 add r7, sp, #0 + 8009f3a: 6078 str r0, [r7, #4] + /* Init USB_IP */ + if (phost->id == HOST_FS) { + 8009f3c: 687b ldr r3, [r7, #4] + 8009f3e: f893 33cc ldrb.w r3, [r3, #972] ; 0x3cc + 8009f42: 2b01 cmp r3, #1 + 8009f44: d12a bne.n 8009f9c + /* Link the driver to the stack. */ + hhcd_USB_OTG_FS.pData = phost; + 8009f46: 4a18 ldr r2, [pc, #96] ; (8009fa8 ) + 8009f48: 687b ldr r3, [r7, #4] + 8009f4a: f8c2 32c0 str.w r3, [r2, #704] ; 0x2c0 + phost->pData = &hhcd_USB_OTG_FS; + 8009f4e: 687b ldr r3, [r7, #4] + 8009f50: 4a15 ldr r2, [pc, #84] ; (8009fa8 ) + 8009f52: f8c3 23d0 str.w r2, [r3, #976] ; 0x3d0 + + hhcd_USB_OTG_FS.Instance = USB_OTG_FS; + 8009f56: 4b14 ldr r3, [pc, #80] ; (8009fa8 ) + 8009f58: f04f 42a0 mov.w r2, #1342177280 ; 0x50000000 + 8009f5c: 601a str r2, [r3, #0] + hhcd_USB_OTG_FS.Init.Host_channels = 8; + 8009f5e: 4b12 ldr r3, [pc, #72] ; (8009fa8 ) + 8009f60: 2208 movs r2, #8 + 8009f62: 609a str r2, [r3, #8] + hhcd_USB_OTG_FS.Init.speed = HCD_SPEED_FULL; + 8009f64: 4b10 ldr r3, [pc, #64] ; (8009fa8 ) + 8009f66: 2201 movs r2, #1 + 8009f68: 60da str r2, [r3, #12] + hhcd_USB_OTG_FS.Init.dma_enable = DISABLE; + 8009f6a: 4b0f ldr r3, [pc, #60] ; (8009fa8 ) + 8009f6c: 2200 movs r2, #0 + 8009f6e: 611a str r2, [r3, #16] + hhcd_USB_OTG_FS.Init.phy_itface = HCD_PHY_EMBEDDED; + 8009f70: 4b0d ldr r3, [pc, #52] ; (8009fa8 ) + 8009f72: 2202 movs r2, #2 + 8009f74: 619a str r2, [r3, #24] + hhcd_USB_OTG_FS.Init.Sof_enable = DISABLE; + 8009f76: 4b0c ldr r3, [pc, #48] ; (8009fa8 ) + 8009f78: 2200 movs r2, #0 + 8009f7a: 61da str r2, [r3, #28] + if (HAL_HCD_Init(&hhcd_USB_OTG_FS) != HAL_OK) + 8009f7c: 480a ldr r0, [pc, #40] ; (8009fa8 ) + 8009f7e: f7f8 fca8 bl 80028d2 + 8009f82: 4603 mov r3, r0 + 8009f84: 2b00 cmp r3, #0 + 8009f86: d001 beq.n 8009f8c + { + Error_Handler( ); + 8009f88: f7f7 fb86 bl 8001698 + } + + USBH_LL_SetTimer(phost, HAL_HCD_GetCurrentFrame(&hhcd_USB_OTG_FS)); + 8009f8c: 4806 ldr r0, [pc, #24] ; (8009fa8 ) + 8009f8e: f7f9 f8ab bl 80030e8 + 8009f92: 4603 mov r3, r0 + 8009f94: 4619 mov r1, r3 + 8009f96: 6878 ldr r0, [r7, #4] + 8009f98: f7ff f84c bl 8009034 + } + return USBH_OK; + 8009f9c: 2300 movs r3, #0 +} + 8009f9e: 4618 mov r0, r3 + 8009fa0: 3708 adds r7, #8 + 8009fa2: 46bd mov sp, r7 + 8009fa4: bd80 pop {r7, pc} + 8009fa6: bf00 nop + 8009fa8: 200007ec .word 0x200007ec + +08009fac : + * @brief Start the low level portion of the host driver. + * @param phost: Host handle + * @retval USBH status + */ +USBH_StatusTypeDef USBH_LL_Start(USBH_HandleTypeDef *phost) +{ + 8009fac: b580 push {r7, lr} + 8009fae: b084 sub sp, #16 + 8009fb0: af00 add r7, sp, #0 + 8009fb2: 6078 str r0, [r7, #4] + HAL_StatusTypeDef hal_status = HAL_OK; + 8009fb4: 2300 movs r3, #0 + 8009fb6: 73fb strb r3, [r7, #15] + USBH_StatusTypeDef usb_status = USBH_OK; + 8009fb8: 2300 movs r3, #0 + 8009fba: 73bb strb r3, [r7, #14] + + hal_status = HAL_HCD_Start(phost->pData); + 8009fbc: 687b ldr r3, [r7, #4] + 8009fbe: f8d3 33d0 ldr.w r3, [r3, #976] ; 0x3d0 + 8009fc2: 4618 mov r0, r3 + 8009fc4: f7f9 f818 bl 8002ff8 + 8009fc8: 4603 mov r3, r0 + 8009fca: 73fb strb r3, [r7, #15] + + usb_status = USBH_Get_USB_Status(hal_status); + 8009fcc: 7bfb ldrb r3, [r7, #15] + 8009fce: 4618 mov r0, r3 + 8009fd0: f000 f95c bl 800a28c + 8009fd4: 4603 mov r3, r0 + 8009fd6: 73bb strb r3, [r7, #14] + + return usb_status; + 8009fd8: 7bbb ldrb r3, [r7, #14] +} + 8009fda: 4618 mov r0, r3 + 8009fdc: 3710 adds r7, #16 + 8009fde: 46bd mov sp, r7 + 8009fe0: bd80 pop {r7, pc} + +08009fe2 : + * @brief Stop the low level portion of the host driver. + * @param phost: Host handle + * @retval USBH status + */ +USBH_StatusTypeDef USBH_LL_Stop(USBH_HandleTypeDef *phost) +{ + 8009fe2: b580 push {r7, lr} + 8009fe4: b084 sub sp, #16 + 8009fe6: af00 add r7, sp, #0 + 8009fe8: 6078 str r0, [r7, #4] + HAL_StatusTypeDef hal_status = HAL_OK; + 8009fea: 2300 movs r3, #0 + 8009fec: 73fb strb r3, [r7, #15] + USBH_StatusTypeDef usb_status = USBH_OK; + 8009fee: 2300 movs r3, #0 + 8009ff0: 73bb strb r3, [r7, #14] + + hal_status = HAL_HCD_Stop(phost->pData); + 8009ff2: 687b ldr r3, [r7, #4] + 8009ff4: f8d3 33d0 ldr.w r3, [r3, #976] ; 0x3d0 + 8009ff8: 4618 mov r0, r3 + 8009ffa: f7f9 f820 bl 800303e + 8009ffe: 4603 mov r3, r0 + 800a000: 73fb strb r3, [r7, #15] + + usb_status = USBH_Get_USB_Status(hal_status); + 800a002: 7bfb ldrb r3, [r7, #15] + 800a004: 4618 mov r0, r3 + 800a006: f000 f941 bl 800a28c + 800a00a: 4603 mov r3, r0 + 800a00c: 73bb strb r3, [r7, #14] + + return usb_status; + 800a00e: 7bbb ldrb r3, [r7, #14] +} + 800a010: 4618 mov r0, r3 + 800a012: 3710 adds r7, #16 + 800a014: 46bd mov sp, r7 + 800a016: bd80 pop {r7, pc} + +0800a018 : + * @brief Return the USB host speed from the low level driver. + * @param phost: Host handle + * @retval USBH speeds + */ +USBH_SpeedTypeDef USBH_LL_GetSpeed(USBH_HandleTypeDef *phost) +{ + 800a018: b580 push {r7, lr} + 800a01a: b084 sub sp, #16 + 800a01c: af00 add r7, sp, #0 + 800a01e: 6078 str r0, [r7, #4] + USBH_SpeedTypeDef speed = USBH_SPEED_FULL; + 800a020: 2301 movs r3, #1 + 800a022: 73fb strb r3, [r7, #15] + + switch (HAL_HCD_GetCurrentSpeed(phost->pData)) + 800a024: 687b ldr r3, [r7, #4] + 800a026: f8d3 33d0 ldr.w r3, [r3, #976] ; 0x3d0 + 800a02a: 4618 mov r0, r3 + 800a02c: f7f9 f86a bl 8003104 + 800a030: 4603 mov r3, r0 + 800a032: 2b01 cmp r3, #1 + 800a034: d007 beq.n 800a046 + 800a036: 2b01 cmp r3, #1 + 800a038: d302 bcc.n 800a040 + 800a03a: 2b02 cmp r3, #2 + 800a03c: d006 beq.n 800a04c + 800a03e: e008 b.n 800a052 + { + case 0 : + speed = USBH_SPEED_HIGH; + 800a040: 2300 movs r3, #0 + 800a042: 73fb strb r3, [r7, #15] + break; + 800a044: e008 b.n 800a058 + + case 1 : + speed = USBH_SPEED_FULL; + 800a046: 2301 movs r3, #1 + 800a048: 73fb strb r3, [r7, #15] + break; + 800a04a: e005 b.n 800a058 + + case 2 : + speed = USBH_SPEED_LOW; + 800a04c: 2302 movs r3, #2 + 800a04e: 73fb strb r3, [r7, #15] + break; + 800a050: e002 b.n 800a058 + + default: + speed = USBH_SPEED_FULL; + 800a052: 2301 movs r3, #1 + 800a054: 73fb strb r3, [r7, #15] + break; + 800a056: bf00 nop + } + return speed; + 800a058: 7bfb ldrb r3, [r7, #15] +} + 800a05a: 4618 mov r0, r3 + 800a05c: 3710 adds r7, #16 + 800a05e: 46bd mov sp, r7 + 800a060: bd80 pop {r7, pc} + +0800a062 : + * @brief Reset the Host port of the low level driver. + * @param phost: Host handle + * @retval USBH status + */ +USBH_StatusTypeDef USBH_LL_ResetPort(USBH_HandleTypeDef *phost) +{ + 800a062: b580 push {r7, lr} + 800a064: b084 sub sp, #16 + 800a066: af00 add r7, sp, #0 + 800a068: 6078 str r0, [r7, #4] + HAL_StatusTypeDef hal_status = HAL_OK; + 800a06a: 2300 movs r3, #0 + 800a06c: 73fb strb r3, [r7, #15] + USBH_StatusTypeDef usb_status = USBH_OK; + 800a06e: 2300 movs r3, #0 + 800a070: 73bb strb r3, [r7, #14] + + hal_status = HAL_HCD_ResetPort(phost->pData); + 800a072: 687b ldr r3, [r7, #4] + 800a074: f8d3 33d0 ldr.w r3, [r3, #976] ; 0x3d0 + 800a078: 4618 mov r0, r3 + 800a07a: f7f8 fffd bl 8003078 + 800a07e: 4603 mov r3, r0 + 800a080: 73fb strb r3, [r7, #15] + + usb_status = USBH_Get_USB_Status(hal_status); + 800a082: 7bfb ldrb r3, [r7, #15] + 800a084: 4618 mov r0, r3 + 800a086: f000 f901 bl 800a28c + 800a08a: 4603 mov r3, r0 + 800a08c: 73bb strb r3, [r7, #14] + + return usb_status; + 800a08e: 7bbb ldrb r3, [r7, #14] +} + 800a090: 4618 mov r0, r3 + 800a092: 3710 adds r7, #16 + 800a094: 46bd mov sp, r7 + 800a096: bd80 pop {r7, pc} + +0800a098 : + * @param phost: Host handle + * @param pipe: Pipe index + * @retval Packet size + */ +uint32_t USBH_LL_GetLastXferSize(USBH_HandleTypeDef *phost, uint8_t pipe) +{ + 800a098: b580 push {r7, lr} + 800a09a: b082 sub sp, #8 + 800a09c: af00 add r7, sp, #0 + 800a09e: 6078 str r0, [r7, #4] + 800a0a0: 460b mov r3, r1 + 800a0a2: 70fb strb r3, [r7, #3] + return HAL_HCD_HC_GetXferCount(phost->pData, pipe); + 800a0a4: 687b ldr r3, [r7, #4] + 800a0a6: f8d3 33d0 ldr.w r3, [r3, #976] ; 0x3d0 + 800a0aa: 78fa ldrb r2, [r7, #3] + 800a0ac: 4611 mov r1, r2 + 800a0ae: 4618 mov r0, r3 + 800a0b0: f7f9 f805 bl 80030be + 800a0b4: 4603 mov r3, r0 +} + 800a0b6: 4618 mov r0, r3 + 800a0b8: 3708 adds r7, #8 + 800a0ba: 46bd mov sp, r7 + 800a0bc: bd80 pop {r7, pc} + +0800a0be : + * @param mps: Endpoint max packet size + * @retval USBH status + */ +USBH_StatusTypeDef USBH_LL_OpenPipe(USBH_HandleTypeDef *phost, uint8_t pipe_num, uint8_t epnum, + uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps) +{ + 800a0be: b590 push {r4, r7, lr} + 800a0c0: b089 sub sp, #36 ; 0x24 + 800a0c2: af04 add r7, sp, #16 + 800a0c4: 6078 str r0, [r7, #4] + 800a0c6: 4608 mov r0, r1 + 800a0c8: 4611 mov r1, r2 + 800a0ca: 461a mov r2, r3 + 800a0cc: 4603 mov r3, r0 + 800a0ce: 70fb strb r3, [r7, #3] + 800a0d0: 460b mov r3, r1 + 800a0d2: 70bb strb r3, [r7, #2] + 800a0d4: 4613 mov r3, r2 + 800a0d6: 707b strb r3, [r7, #1] + HAL_StatusTypeDef hal_status = HAL_OK; + 800a0d8: 2300 movs r3, #0 + 800a0da: 73fb strb r3, [r7, #15] + USBH_StatusTypeDef usb_status = USBH_OK; + 800a0dc: 2300 movs r3, #0 + 800a0de: 73bb strb r3, [r7, #14] + + hal_status = HAL_HCD_HC_Init(phost->pData, pipe_num, epnum, + 800a0e0: 687b ldr r3, [r7, #4] + 800a0e2: f8d3 03d0 ldr.w r0, [r3, #976] ; 0x3d0 + 800a0e6: 787c ldrb r4, [r7, #1] + 800a0e8: 78ba ldrb r2, [r7, #2] + 800a0ea: 78f9 ldrb r1, [r7, #3] + 800a0ec: 8d3b ldrh r3, [r7, #40] ; 0x28 + 800a0ee: 9302 str r3, [sp, #8] + 800a0f0: f897 3024 ldrb.w r3, [r7, #36] ; 0x24 + 800a0f4: 9301 str r3, [sp, #4] + 800a0f6: f897 3020 ldrb.w r3, [r7, #32] + 800a0fa: 9300 str r3, [sp, #0] + 800a0fc: 4623 mov r3, r4 + 800a0fe: f7f8 fc4a bl 8002996 + 800a102: 4603 mov r3, r0 + 800a104: 73fb strb r3, [r7, #15] + dev_address, speed, ep_type, mps); + + usb_status = USBH_Get_USB_Status(hal_status); + 800a106: 7bfb ldrb r3, [r7, #15] + 800a108: 4618 mov r0, r3 + 800a10a: f000 f8bf bl 800a28c + 800a10e: 4603 mov r3, r0 + 800a110: 73bb strb r3, [r7, #14] + + return usb_status; + 800a112: 7bbb ldrb r3, [r7, #14] +} + 800a114: 4618 mov r0, r3 + 800a116: 3714 adds r7, #20 + 800a118: 46bd mov sp, r7 + 800a11a: bd90 pop {r4, r7, pc} + +0800a11c : + * @param phost: Host handle + * @param pipe: Pipe index + * @retval USBH status + */ +USBH_StatusTypeDef USBH_LL_ClosePipe(USBH_HandleTypeDef *phost, uint8_t pipe) +{ + 800a11c: b580 push {r7, lr} + 800a11e: b084 sub sp, #16 + 800a120: af00 add r7, sp, #0 + 800a122: 6078 str r0, [r7, #4] + 800a124: 460b mov r3, r1 + 800a126: 70fb strb r3, [r7, #3] + HAL_StatusTypeDef hal_status = HAL_OK; + 800a128: 2300 movs r3, #0 + 800a12a: 73fb strb r3, [r7, #15] + USBH_StatusTypeDef usb_status = USBH_OK; + 800a12c: 2300 movs r3, #0 + 800a12e: 73bb strb r3, [r7, #14] + + hal_status = HAL_HCD_HC_Halt(phost->pData, pipe); + 800a130: 687b ldr r3, [r7, #4] + 800a132: f8d3 33d0 ldr.w r3, [r3, #976] ; 0x3d0 + 800a136: 78fa ldrb r2, [r7, #3] + 800a138: 4611 mov r1, r2 + 800a13a: 4618 mov r0, r3 + 800a13c: f7f8 fcc3 bl 8002ac6 + 800a140: 4603 mov r3, r0 + 800a142: 73fb strb r3, [r7, #15] + + usb_status = USBH_Get_USB_Status(hal_status); + 800a144: 7bfb ldrb r3, [r7, #15] + 800a146: 4618 mov r0, r3 + 800a148: f000 f8a0 bl 800a28c + 800a14c: 4603 mov r3, r0 + 800a14e: 73bb strb r3, [r7, #14] + + return usb_status; + 800a150: 7bbb ldrb r3, [r7, #14] +} + 800a152: 4618 mov r0, r3 + 800a154: 3710 adds r7, #16 + 800a156: 46bd mov sp, r7 + 800a158: bd80 pop {r7, pc} + +0800a15a : + * @retval Status + */ +USBH_StatusTypeDef USBH_LL_SubmitURB(USBH_HandleTypeDef *phost, uint8_t pipe, uint8_t direction, + uint8_t ep_type, uint8_t token, uint8_t *pbuff, uint16_t length, + uint8_t do_ping) +{ + 800a15a: b590 push {r4, r7, lr} + 800a15c: b089 sub sp, #36 ; 0x24 + 800a15e: af04 add r7, sp, #16 + 800a160: 6078 str r0, [r7, #4] + 800a162: 4608 mov r0, r1 + 800a164: 4611 mov r1, r2 + 800a166: 461a mov r2, r3 + 800a168: 4603 mov r3, r0 + 800a16a: 70fb strb r3, [r7, #3] + 800a16c: 460b mov r3, r1 + 800a16e: 70bb strb r3, [r7, #2] + 800a170: 4613 mov r3, r2 + 800a172: 707b strb r3, [r7, #1] + HAL_StatusTypeDef hal_status = HAL_OK; + 800a174: 2300 movs r3, #0 + 800a176: 73fb strb r3, [r7, #15] + USBH_StatusTypeDef usb_status = USBH_OK; + 800a178: 2300 movs r3, #0 + 800a17a: 73bb strb r3, [r7, #14] + + hal_status = HAL_HCD_HC_SubmitRequest(phost->pData, pipe, direction , + 800a17c: 687b ldr r3, [r7, #4] + 800a17e: f8d3 03d0 ldr.w r0, [r3, #976] ; 0x3d0 + 800a182: 787c ldrb r4, [r7, #1] + 800a184: 78ba ldrb r2, [r7, #2] + 800a186: 78f9 ldrb r1, [r7, #3] + 800a188: f897 302c ldrb.w r3, [r7, #44] ; 0x2c + 800a18c: 9303 str r3, [sp, #12] + 800a18e: 8d3b ldrh r3, [r7, #40] ; 0x28 + 800a190: 9302 str r3, [sp, #8] + 800a192: 6a7b ldr r3, [r7, #36] ; 0x24 + 800a194: 9301 str r3, [sp, #4] + 800a196: f897 3020 ldrb.w r3, [r7, #32] + 800a19a: 9300 str r3, [sp, #0] + 800a19c: 4623 mov r3, r4 + 800a19e: f7f8 fcb5 bl 8002b0c + 800a1a2: 4603 mov r3, r0 + 800a1a4: 73fb strb r3, [r7, #15] + ep_type, token, pbuff, length, + do_ping); + usb_status = USBH_Get_USB_Status(hal_status); + 800a1a6: 7bfb ldrb r3, [r7, #15] + 800a1a8: 4618 mov r0, r3 + 800a1aa: f000 f86f bl 800a28c + 800a1ae: 4603 mov r3, r0 + 800a1b0: 73bb strb r3, [r7, #14] + + return usb_status; + 800a1b2: 7bbb ldrb r3, [r7, #14] +} + 800a1b4: 4618 mov r0, r3 + 800a1b6: 3714 adds r7, #20 + 800a1b8: 46bd mov sp, r7 + 800a1ba: bd90 pop {r4, r7, pc} + +0800a1bc : + * @arg URB_NYET + * @arg URB_ERROR + * @arg URB_STALL + */ +USBH_URBStateTypeDef USBH_LL_GetURBState(USBH_HandleTypeDef *phost, uint8_t pipe) +{ + 800a1bc: b580 push {r7, lr} + 800a1be: b082 sub sp, #8 + 800a1c0: af00 add r7, sp, #0 + 800a1c2: 6078 str r0, [r7, #4] + 800a1c4: 460b mov r3, r1 + 800a1c6: 70fb strb r3, [r7, #3] + return (USBH_URBStateTypeDef)HAL_HCD_HC_GetURBState (phost->pData, pipe); + 800a1c8: 687b ldr r3, [r7, #4] + 800a1ca: f8d3 33d0 ldr.w r3, [r3, #976] ; 0x3d0 + 800a1ce: 78fa ldrb r2, [r7, #3] + 800a1d0: 4611 mov r1, r2 + 800a1d2: 4618 mov r0, r3 + 800a1d4: f7f8 ff5e bl 8003094 + 800a1d8: 4603 mov r3, r0 +} + 800a1da: 4618 mov r0, r3 + 800a1dc: 3708 adds r7, #8 + 800a1de: 46bd mov sp, r7 + 800a1e0: bd80 pop {r7, pc} + +0800a1e2 : + * 0 : VBUS Inactive + * 1 : VBUS Active + * @retval Status + */ +USBH_StatusTypeDef USBH_LL_DriverVBUS(USBH_HandleTypeDef *phost, uint8_t state) +{ + 800a1e2: b580 push {r7, lr} + 800a1e4: b082 sub sp, #8 + 800a1e6: af00 add r7, sp, #0 + 800a1e8: 6078 str r0, [r7, #4] + 800a1ea: 460b mov r3, r1 + 800a1ec: 70fb strb r3, [r7, #3] + if (phost->id == HOST_FS) { + 800a1ee: 687b ldr r3, [r7, #4] + 800a1f0: f893 33cc ldrb.w r3, [r3, #972] ; 0x3cc + 800a1f4: 2b01 cmp r3, #1 + 800a1f6: d103 bne.n 800a200 + MX_DriverVbusFS(state); + 800a1f8: 78fb ldrb r3, [r7, #3] + 800a1fa: 4618 mov r0, r3 + 800a1fc: f000 f872 bl 800a2e4 + + /* USER CODE BEGIN 0 */ + + /* USER CODE END 0*/ + + HAL_Delay(200); + 800a200: 20c8 movs r0, #200 ; 0xc8 + 800a202: f7f8 f897 bl 8002334 + return USBH_OK; + 800a206: 2300 movs r3, #0 +} + 800a208: 4618 mov r0, r3 + 800a20a: 3708 adds r7, #8 + 800a20c: 46bd mov sp, r7 + 800a20e: bd80 pop {r7, pc} + +0800a210 : + * @param pipe: Pipe index + * @param toggle: toggle (0/1) + * @retval Status + */ +USBH_StatusTypeDef USBH_LL_SetToggle(USBH_HandleTypeDef *phost, uint8_t pipe, uint8_t toggle) +{ + 800a210: b480 push {r7} + 800a212: b085 sub sp, #20 + 800a214: af00 add r7, sp, #0 + 800a216: 6078 str r0, [r7, #4] + 800a218: 460b mov r3, r1 + 800a21a: 70fb strb r3, [r7, #3] + 800a21c: 4613 mov r3, r2 + 800a21e: 70bb strb r3, [r7, #2] + HCD_HandleTypeDef *pHandle; + pHandle = phost->pData; + 800a220: 687b ldr r3, [r7, #4] + 800a222: f8d3 33d0 ldr.w r3, [r3, #976] ; 0x3d0 + 800a226: 60fb str r3, [r7, #12] + + if(pHandle->hc[pipe].ep_is_in) + 800a228: 78fa ldrb r2, [r7, #3] + 800a22a: 68f9 ldr r1, [r7, #12] + 800a22c: 4613 mov r3, r2 + 800a22e: 009b lsls r3, r3, #2 + 800a230: 4413 add r3, r2 + 800a232: 00db lsls r3, r3, #3 + 800a234: 440b add r3, r1 + 800a236: 333b adds r3, #59 ; 0x3b + 800a238: 781b ldrb r3, [r3, #0] + 800a23a: 2b00 cmp r3, #0 + 800a23c: d00a beq.n 800a254 + { + pHandle->hc[pipe].toggle_in = toggle; + 800a23e: 78fa ldrb r2, [r7, #3] + 800a240: 68f9 ldr r1, [r7, #12] + 800a242: 4613 mov r3, r2 + 800a244: 009b lsls r3, r3, #2 + 800a246: 4413 add r3, r2 + 800a248: 00db lsls r3, r3, #3 + 800a24a: 440b add r3, r1 + 800a24c: 3350 adds r3, #80 ; 0x50 + 800a24e: 78ba ldrb r2, [r7, #2] + 800a250: 701a strb r2, [r3, #0] + 800a252: e009 b.n 800a268 + } + else + { + pHandle->hc[pipe].toggle_out = toggle; + 800a254: 78fa ldrb r2, [r7, #3] + 800a256: 68f9 ldr r1, [r7, #12] + 800a258: 4613 mov r3, r2 + 800a25a: 009b lsls r3, r3, #2 + 800a25c: 4413 add r3, r2 + 800a25e: 00db lsls r3, r3, #3 + 800a260: 440b add r3, r1 + 800a262: 3351 adds r3, #81 ; 0x51 + 800a264: 78ba ldrb r2, [r7, #2] + 800a266: 701a strb r2, [r3, #0] + } + + return USBH_OK; + 800a268: 2300 movs r3, #0 +} + 800a26a: 4618 mov r0, r3 + 800a26c: 3714 adds r7, #20 + 800a26e: 46bd mov sp, r7 + 800a270: f85d 7b04 ldr.w r7, [sp], #4 + 800a274: 4770 bx lr + +0800a276 : + * @brief Delay routine for the USB Host Library + * @param Delay: Delay in ms + * @retval None + */ +void USBH_Delay(uint32_t Delay) +{ + 800a276: b580 push {r7, lr} + 800a278: b082 sub sp, #8 + 800a27a: af00 add r7, sp, #0 + 800a27c: 6078 str r0, [r7, #4] + HAL_Delay(Delay); + 800a27e: 6878 ldr r0, [r7, #4] + 800a280: f7f8 f858 bl 8002334 +} + 800a284: bf00 nop + 800a286: 3708 adds r7, #8 + 800a288: 46bd mov sp, r7 + 800a28a: bd80 pop {r7, pc} + +0800a28c : + * @brief Retuns the USB status depending on the HAL status: + * @param hal_status: HAL status + * @retval USB status + */ +USBH_StatusTypeDef USBH_Get_USB_Status(HAL_StatusTypeDef hal_status) +{ + 800a28c: b480 push {r7} + 800a28e: b085 sub sp, #20 + 800a290: af00 add r7, sp, #0 + 800a292: 4603 mov r3, r0 + 800a294: 71fb strb r3, [r7, #7] + USBH_StatusTypeDef usb_status = USBH_OK; + 800a296: 2300 movs r3, #0 + 800a298: 73fb strb r3, [r7, #15] + + switch (hal_status) + 800a29a: 79fb ldrb r3, [r7, #7] + 800a29c: 2b03 cmp r3, #3 + 800a29e: d817 bhi.n 800a2d0 + 800a2a0: a201 add r2, pc, #4 ; (adr r2, 800a2a8 ) + 800a2a2: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 800a2a6: bf00 nop + 800a2a8: 0800a2b9 .word 0x0800a2b9 + 800a2ac: 0800a2bf .word 0x0800a2bf + 800a2b0: 0800a2c5 .word 0x0800a2c5 + 800a2b4: 0800a2cb .word 0x0800a2cb + { + case HAL_OK : + usb_status = USBH_OK; + 800a2b8: 2300 movs r3, #0 + 800a2ba: 73fb strb r3, [r7, #15] + break; + 800a2bc: e00b b.n 800a2d6 + case HAL_ERROR : + usb_status = USBH_FAIL; + 800a2be: 2302 movs r3, #2 + 800a2c0: 73fb strb r3, [r7, #15] + break; + 800a2c2: e008 b.n 800a2d6 + case HAL_BUSY : + usb_status = USBH_BUSY; + 800a2c4: 2301 movs r3, #1 + 800a2c6: 73fb strb r3, [r7, #15] + break; + 800a2c8: e005 b.n 800a2d6 + case HAL_TIMEOUT : + usb_status = USBH_FAIL; + 800a2ca: 2302 movs r3, #2 + 800a2cc: 73fb strb r3, [r7, #15] + break; + 800a2ce: e002 b.n 800a2d6 + default : + usb_status = USBH_FAIL; + 800a2d0: 2302 movs r3, #2 + 800a2d2: 73fb strb r3, [r7, #15] + break; + 800a2d4: bf00 nop + } + return usb_status; + 800a2d6: 7bfb ldrb r3, [r7, #15] +} + 800a2d8: 4618 mov r0, r3 + 800a2da: 3714 adds r7, #20 + 800a2dc: 46bd mov sp, r7 + 800a2de: f85d 7b04 ldr.w r7, [sp], #4 + 800a2e2: 4770 bx lr + +0800a2e4 : + * This parameter can be one of the these values: + * - 1 : VBUS Active + * - 0 : VBUS Inactive + */ +void MX_DriverVbusFS(uint8_t state) +{ + 800a2e4: b580 push {r7, lr} + 800a2e6: b084 sub sp, #16 + 800a2e8: af00 add r7, sp, #0 + 800a2ea: 4603 mov r3, r0 + 800a2ec: 71fb strb r3, [r7, #7] + uint8_t data = state; + 800a2ee: 79fb ldrb r3, [r7, #7] + 800a2f0: 73fb strb r3, [r7, #15] + /* USER CODE BEGIN PREPARE_GPIO_DATA_VBUS_FS */ + if(state == 0) + 800a2f2: 79fb ldrb r3, [r7, #7] + 800a2f4: 2b00 cmp r3, #0 + 800a2f6: d102 bne.n 800a2fe + { + /* Drive high Charge pump */ + data = GPIO_PIN_SET; + 800a2f8: 2301 movs r3, #1 + 800a2fa: 73fb strb r3, [r7, #15] + 800a2fc: e001 b.n 800a302 + } + else + { + /* Drive low Charge pump */ + data = GPIO_PIN_RESET; + 800a2fe: 2300 movs r3, #0 + 800a300: 73fb strb r3, [r7, #15] + } + /* USER CODE END PREPARE_GPIO_DATA_VBUS_FS */ + HAL_GPIO_WritePin(GPIOC,GPIO_PIN_0,(GPIO_PinState)data); + 800a302: 7bfb ldrb r3, [r7, #15] + 800a304: 461a mov r2, r3 + 800a306: 2101 movs r1, #1 + 800a308: 4803 ldr r0, [pc, #12] ; (800a318 ) + 800a30a: f7f8 fac9 bl 80028a0 +} + 800a30e: bf00 nop + 800a310: 3710 adds r7, #16 + 800a312: 46bd mov sp, r7 + 800a314: bd80 pop {r7, pc} + 800a316: bf00 nop + 800a318: 40020800 .word 0x40020800 + +0800a31c <__errno>: + 800a31c: 4b01 ldr r3, [pc, #4] ; (800a324 <__errno+0x8>) + 800a31e: 6818 ldr r0, [r3, #0] + 800a320: 4770 bx lr + 800a322: bf00 nop + 800a324: 2000002c .word 0x2000002c + +0800a328 <__libc_init_array>: + 800a328: b570 push {r4, r5, r6, lr} + 800a32a: 4e0d ldr r6, [pc, #52] ; (800a360 <__libc_init_array+0x38>) + 800a32c: 4c0d ldr r4, [pc, #52] ; (800a364 <__libc_init_array+0x3c>) + 800a32e: 1ba4 subs r4, r4, r6 + 800a330: 10a4 asrs r4, r4, #2 + 800a332: 2500 movs r5, #0 + 800a334: 42a5 cmp r5, r4 + 800a336: d109 bne.n 800a34c <__libc_init_array+0x24> + 800a338: 4e0b ldr r6, [pc, #44] ; (800a368 <__libc_init_array+0x40>) + 800a33a: 4c0c ldr r4, [pc, #48] ; (800a36c <__libc_init_array+0x44>) + 800a33c: f004 fa64 bl 800e808 <_init> + 800a340: 1ba4 subs r4, r4, r6 + 800a342: 10a4 asrs r4, r4, #2 + 800a344: 2500 movs r5, #0 + 800a346: 42a5 cmp r5, r4 + 800a348: d105 bne.n 800a356 <__libc_init_array+0x2e> + 800a34a: bd70 pop {r4, r5, r6, pc} + 800a34c: f856 3025 ldr.w r3, [r6, r5, lsl #2] + 800a350: 4798 blx r3 + 800a352: 3501 adds r5, #1 + 800a354: e7ee b.n 800a334 <__libc_init_array+0xc> + 800a356: f856 3025 ldr.w r3, [r6, r5, lsl #2] + 800a35a: 4798 blx r3 + 800a35c: 3501 adds r5, #1 + 800a35e: e7f2 b.n 800a346 <__libc_init_array+0x1e> + 800a360: 0800ec60 .word 0x0800ec60 + 800a364: 0800ec60 .word 0x0800ec60 + 800a368: 0800ec60 .word 0x0800ec60 + 800a36c: 0800ec64 .word 0x0800ec64 + +0800a370 : + 800a370: 4b02 ldr r3, [pc, #8] ; (800a37c ) + 800a372: 4601 mov r1, r0 + 800a374: 6818 ldr r0, [r3, #0] + 800a376: f000 b861 b.w 800a43c <_malloc_r> + 800a37a: bf00 nop + 800a37c: 2000002c .word 0x2000002c + +0800a380 : + 800a380: 4b02 ldr r3, [pc, #8] ; (800a38c ) + 800a382: 4601 mov r1, r0 + 800a384: 6818 ldr r0, [r3, #0] + 800a386: f000 b80b b.w 800a3a0 <_free_r> + 800a38a: bf00 nop + 800a38c: 2000002c .word 0x2000002c + +0800a390 : + 800a390: 4402 add r2, r0 + 800a392: 4603 mov r3, r0 + 800a394: 4293 cmp r3, r2 + 800a396: d100 bne.n 800a39a + 800a398: 4770 bx lr + 800a39a: f803 1b01 strb.w r1, [r3], #1 + 800a39e: e7f9 b.n 800a394 + +0800a3a0 <_free_r>: + 800a3a0: b538 push {r3, r4, r5, lr} + 800a3a2: 4605 mov r5, r0 + 800a3a4: 2900 cmp r1, #0 + 800a3a6: d045 beq.n 800a434 <_free_r+0x94> + 800a3a8: f851 3c04 ldr.w r3, [r1, #-4] + 800a3ac: 1f0c subs r4, r1, #4 + 800a3ae: 2b00 cmp r3, #0 + 800a3b0: bfb8 it lt + 800a3b2: 18e4 addlt r4, r4, r3 + 800a3b4: f003 fa75 bl 800d8a2 <__malloc_lock> + 800a3b8: 4a1f ldr r2, [pc, #124] ; (800a438 <_free_r+0x98>) + 800a3ba: 6813 ldr r3, [r2, #0] + 800a3bc: 4610 mov r0, r2 + 800a3be: b933 cbnz r3, 800a3ce <_free_r+0x2e> + 800a3c0: 6063 str r3, [r4, #4] + 800a3c2: 6014 str r4, [r2, #0] + 800a3c4: 4628 mov r0, r5 + 800a3c6: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} + 800a3ca: f003 ba6b b.w 800d8a4 <__malloc_unlock> + 800a3ce: 42a3 cmp r3, r4 + 800a3d0: d90c bls.n 800a3ec <_free_r+0x4c> + 800a3d2: 6821 ldr r1, [r4, #0] + 800a3d4: 1862 adds r2, r4, r1 + 800a3d6: 4293 cmp r3, r2 + 800a3d8: bf04 itt eq + 800a3da: 681a ldreq r2, [r3, #0] + 800a3dc: 685b ldreq r3, [r3, #4] + 800a3de: 6063 str r3, [r4, #4] + 800a3e0: bf04 itt eq + 800a3e2: 1852 addeq r2, r2, r1 + 800a3e4: 6022 streq r2, [r4, #0] + 800a3e6: 6004 str r4, [r0, #0] + 800a3e8: e7ec b.n 800a3c4 <_free_r+0x24> + 800a3ea: 4613 mov r3, r2 + 800a3ec: 685a ldr r2, [r3, #4] + 800a3ee: b10a cbz r2, 800a3f4 <_free_r+0x54> + 800a3f0: 42a2 cmp r2, r4 + 800a3f2: d9fa bls.n 800a3ea <_free_r+0x4a> + 800a3f4: 6819 ldr r1, [r3, #0] + 800a3f6: 1858 adds r0, r3, r1 + 800a3f8: 42a0 cmp r0, r4 + 800a3fa: d10b bne.n 800a414 <_free_r+0x74> + 800a3fc: 6820 ldr r0, [r4, #0] + 800a3fe: 4401 add r1, r0 + 800a400: 1858 adds r0, r3, r1 + 800a402: 4282 cmp r2, r0 + 800a404: 6019 str r1, [r3, #0] + 800a406: d1dd bne.n 800a3c4 <_free_r+0x24> + 800a408: 6810 ldr r0, [r2, #0] + 800a40a: 6852 ldr r2, [r2, #4] + 800a40c: 605a str r2, [r3, #4] + 800a40e: 4401 add r1, r0 + 800a410: 6019 str r1, [r3, #0] + 800a412: e7d7 b.n 800a3c4 <_free_r+0x24> + 800a414: d902 bls.n 800a41c <_free_r+0x7c> + 800a416: 230c movs r3, #12 + 800a418: 602b str r3, [r5, #0] + 800a41a: e7d3 b.n 800a3c4 <_free_r+0x24> + 800a41c: 6820 ldr r0, [r4, #0] + 800a41e: 1821 adds r1, r4, r0 + 800a420: 428a cmp r2, r1 + 800a422: bf04 itt eq + 800a424: 6811 ldreq r1, [r2, #0] + 800a426: 6852 ldreq r2, [r2, #4] + 800a428: 6062 str r2, [r4, #4] + 800a42a: bf04 itt eq + 800a42c: 1809 addeq r1, r1, r0 + 800a42e: 6021 streq r1, [r4, #0] + 800a430: 605c str r4, [r3, #4] + 800a432: e7c7 b.n 800a3c4 <_free_r+0x24> + 800a434: bd38 pop {r3, r4, r5, pc} + 800a436: bf00 nop + 800a438: 20000234 .word 0x20000234 + +0800a43c <_malloc_r>: + 800a43c: b570 push {r4, r5, r6, lr} + 800a43e: 1ccd adds r5, r1, #3 + 800a440: f025 0503 bic.w r5, r5, #3 + 800a444: 3508 adds r5, #8 + 800a446: 2d0c cmp r5, #12 + 800a448: bf38 it cc + 800a44a: 250c movcc r5, #12 + 800a44c: 2d00 cmp r5, #0 + 800a44e: 4606 mov r6, r0 + 800a450: db01 blt.n 800a456 <_malloc_r+0x1a> + 800a452: 42a9 cmp r1, r5 + 800a454: d903 bls.n 800a45e <_malloc_r+0x22> + 800a456: 230c movs r3, #12 + 800a458: 6033 str r3, [r6, #0] + 800a45a: 2000 movs r0, #0 + 800a45c: bd70 pop {r4, r5, r6, pc} + 800a45e: f003 fa20 bl 800d8a2 <__malloc_lock> + 800a462: 4a21 ldr r2, [pc, #132] ; (800a4e8 <_malloc_r+0xac>) + 800a464: 6814 ldr r4, [r2, #0] + 800a466: 4621 mov r1, r4 + 800a468: b991 cbnz r1, 800a490 <_malloc_r+0x54> + 800a46a: 4c20 ldr r4, [pc, #128] ; (800a4ec <_malloc_r+0xb0>) + 800a46c: 6823 ldr r3, [r4, #0] + 800a46e: b91b cbnz r3, 800a478 <_malloc_r+0x3c> + 800a470: 4630 mov r0, r6 + 800a472: f000 fef7 bl 800b264 <_sbrk_r> + 800a476: 6020 str r0, [r4, #0] + 800a478: 4629 mov r1, r5 + 800a47a: 4630 mov r0, r6 + 800a47c: f000 fef2 bl 800b264 <_sbrk_r> + 800a480: 1c43 adds r3, r0, #1 + 800a482: d124 bne.n 800a4ce <_malloc_r+0x92> + 800a484: 230c movs r3, #12 + 800a486: 6033 str r3, [r6, #0] + 800a488: 4630 mov r0, r6 + 800a48a: f003 fa0b bl 800d8a4 <__malloc_unlock> + 800a48e: e7e4 b.n 800a45a <_malloc_r+0x1e> + 800a490: 680b ldr r3, [r1, #0] + 800a492: 1b5b subs r3, r3, r5 + 800a494: d418 bmi.n 800a4c8 <_malloc_r+0x8c> + 800a496: 2b0b cmp r3, #11 + 800a498: d90f bls.n 800a4ba <_malloc_r+0x7e> + 800a49a: 600b str r3, [r1, #0] + 800a49c: 50cd str r5, [r1, r3] + 800a49e: 18cc adds r4, r1, r3 + 800a4a0: 4630 mov r0, r6 + 800a4a2: f003 f9ff bl 800d8a4 <__malloc_unlock> + 800a4a6: f104 000b add.w r0, r4, #11 + 800a4aa: 1d23 adds r3, r4, #4 + 800a4ac: f020 0007 bic.w r0, r0, #7 + 800a4b0: 1ac3 subs r3, r0, r3 + 800a4b2: d0d3 beq.n 800a45c <_malloc_r+0x20> + 800a4b4: 425a negs r2, r3 + 800a4b6: 50e2 str r2, [r4, r3] + 800a4b8: e7d0 b.n 800a45c <_malloc_r+0x20> + 800a4ba: 428c cmp r4, r1 + 800a4bc: 684b ldr r3, [r1, #4] + 800a4be: bf16 itet ne + 800a4c0: 6063 strne r3, [r4, #4] + 800a4c2: 6013 streq r3, [r2, #0] + 800a4c4: 460c movne r4, r1 + 800a4c6: e7eb b.n 800a4a0 <_malloc_r+0x64> + 800a4c8: 460c mov r4, r1 + 800a4ca: 6849 ldr r1, [r1, #4] + 800a4cc: e7cc b.n 800a468 <_malloc_r+0x2c> + 800a4ce: 1cc4 adds r4, r0, #3 + 800a4d0: f024 0403 bic.w r4, r4, #3 + 800a4d4: 42a0 cmp r0, r4 + 800a4d6: d005 beq.n 800a4e4 <_malloc_r+0xa8> + 800a4d8: 1a21 subs r1, r4, r0 + 800a4da: 4630 mov r0, r6 + 800a4dc: f000 fec2 bl 800b264 <_sbrk_r> + 800a4e0: 3001 adds r0, #1 + 800a4e2: d0cf beq.n 800a484 <_malloc_r+0x48> + 800a4e4: 6025 str r5, [r4, #0] + 800a4e6: e7db b.n 800a4a0 <_malloc_r+0x64> + 800a4e8: 20000234 .word 0x20000234 + 800a4ec: 20000238 .word 0x20000238 + +0800a4f0 <__cvt>: + 800a4f0: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} + 800a4f4: ec55 4b10 vmov r4, r5, d0 + 800a4f8: 9f0d ldr r7, [sp, #52] ; 0x34 + 800a4fa: f8dd a030 ldr.w sl, [sp, #48] ; 0x30 + 800a4fe: 2d00 cmp r5, #0 + 800a500: 460e mov r6, r1 + 800a502: 4691 mov r9, r2 + 800a504: 4619 mov r1, r3 + 800a506: bfb8 it lt + 800a508: 4622 movlt r2, r4 + 800a50a: 462b mov r3, r5 + 800a50c: f027 0720 bic.w r7, r7, #32 + 800a510: bfbb ittet lt + 800a512: f105 4300 addlt.w r3, r5, #2147483648 ; 0x80000000 + 800a516: 461d movlt r5, r3 + 800a518: 2300 movge r3, #0 + 800a51a: 232d movlt r3, #45 ; 0x2d + 800a51c: bfb8 it lt + 800a51e: 4614 movlt r4, r2 + 800a520: 2f46 cmp r7, #70 ; 0x46 + 800a522: 700b strb r3, [r1, #0] + 800a524: d004 beq.n 800a530 <__cvt+0x40> + 800a526: 2f45 cmp r7, #69 ; 0x45 + 800a528: d100 bne.n 800a52c <__cvt+0x3c> + 800a52a: 3601 adds r6, #1 + 800a52c: 2102 movs r1, #2 + 800a52e: e000 b.n 800a532 <__cvt+0x42> + 800a530: 2103 movs r1, #3 + 800a532: ab03 add r3, sp, #12 + 800a534: 9301 str r3, [sp, #4] + 800a536: ab02 add r3, sp, #8 + 800a538: 9300 str r3, [sp, #0] + 800a53a: 4632 mov r2, r6 + 800a53c: 4653 mov r3, sl + 800a53e: ec45 4b10 vmov d0, r4, r5 + 800a542: f001 fec1 bl 800c2c8 <_dtoa_r> + 800a546: 2f47 cmp r7, #71 ; 0x47 + 800a548: 4680 mov r8, r0 + 800a54a: d102 bne.n 800a552 <__cvt+0x62> + 800a54c: f019 0f01 tst.w r9, #1 + 800a550: d026 beq.n 800a5a0 <__cvt+0xb0> + 800a552: 2f46 cmp r7, #70 ; 0x46 + 800a554: eb08 0906 add.w r9, r8, r6 + 800a558: d111 bne.n 800a57e <__cvt+0x8e> + 800a55a: f898 3000 ldrb.w r3, [r8] + 800a55e: 2b30 cmp r3, #48 ; 0x30 + 800a560: d10a bne.n 800a578 <__cvt+0x88> + 800a562: 2200 movs r2, #0 + 800a564: 2300 movs r3, #0 + 800a566: 4620 mov r0, r4 + 800a568: 4629 mov r1, r5 + 800a56a: f7f6 fab5 bl 8000ad8 <__aeabi_dcmpeq> + 800a56e: b918 cbnz r0, 800a578 <__cvt+0x88> + 800a570: f1c6 0601 rsb r6, r6, #1 + 800a574: f8ca 6000 str.w r6, [sl] + 800a578: f8da 3000 ldr.w r3, [sl] + 800a57c: 4499 add r9, r3 + 800a57e: 2200 movs r2, #0 + 800a580: 2300 movs r3, #0 + 800a582: 4620 mov r0, r4 + 800a584: 4629 mov r1, r5 + 800a586: f7f6 faa7 bl 8000ad8 <__aeabi_dcmpeq> + 800a58a: b938 cbnz r0, 800a59c <__cvt+0xac> + 800a58c: 2230 movs r2, #48 ; 0x30 + 800a58e: 9b03 ldr r3, [sp, #12] + 800a590: 454b cmp r3, r9 + 800a592: d205 bcs.n 800a5a0 <__cvt+0xb0> + 800a594: 1c59 adds r1, r3, #1 + 800a596: 9103 str r1, [sp, #12] + 800a598: 701a strb r2, [r3, #0] + 800a59a: e7f8 b.n 800a58e <__cvt+0x9e> + 800a59c: f8cd 900c str.w r9, [sp, #12] + 800a5a0: 9b03 ldr r3, [sp, #12] + 800a5a2: 9a0e ldr r2, [sp, #56] ; 0x38 + 800a5a4: eba3 0308 sub.w r3, r3, r8 + 800a5a8: 4640 mov r0, r8 + 800a5aa: 6013 str r3, [r2, #0] + 800a5ac: b004 add sp, #16 + 800a5ae: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + +0800a5b2 <__exponent>: + 800a5b2: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} + 800a5b4: 2900 cmp r1, #0 + 800a5b6: 4604 mov r4, r0 + 800a5b8: bfba itte lt + 800a5ba: 4249 neglt r1, r1 + 800a5bc: 232d movlt r3, #45 ; 0x2d + 800a5be: 232b movge r3, #43 ; 0x2b + 800a5c0: 2909 cmp r1, #9 + 800a5c2: f804 2b02 strb.w r2, [r4], #2 + 800a5c6: 7043 strb r3, [r0, #1] + 800a5c8: dd20 ble.n 800a60c <__exponent+0x5a> + 800a5ca: f10d 0307 add.w r3, sp, #7 + 800a5ce: 461f mov r7, r3 + 800a5d0: 260a movs r6, #10 + 800a5d2: fb91 f5f6 sdiv r5, r1, r6 + 800a5d6: fb06 1115 mls r1, r6, r5, r1 + 800a5da: 3130 adds r1, #48 ; 0x30 + 800a5dc: 2d09 cmp r5, #9 + 800a5de: f803 1c01 strb.w r1, [r3, #-1] + 800a5e2: f103 32ff add.w r2, r3, #4294967295 + 800a5e6: 4629 mov r1, r5 + 800a5e8: dc09 bgt.n 800a5fe <__exponent+0x4c> + 800a5ea: 3130 adds r1, #48 ; 0x30 + 800a5ec: 3b02 subs r3, #2 + 800a5ee: f802 1c01 strb.w r1, [r2, #-1] + 800a5f2: 42bb cmp r3, r7 + 800a5f4: 4622 mov r2, r4 + 800a5f6: d304 bcc.n 800a602 <__exponent+0x50> + 800a5f8: 1a10 subs r0, r2, r0 + 800a5fa: b003 add sp, #12 + 800a5fc: bdf0 pop {r4, r5, r6, r7, pc} + 800a5fe: 4613 mov r3, r2 + 800a600: e7e7 b.n 800a5d2 <__exponent+0x20> + 800a602: f813 2b01 ldrb.w r2, [r3], #1 + 800a606: f804 2b01 strb.w r2, [r4], #1 + 800a60a: e7f2 b.n 800a5f2 <__exponent+0x40> + 800a60c: 2330 movs r3, #48 ; 0x30 + 800a60e: 4419 add r1, r3 + 800a610: 7083 strb r3, [r0, #2] + 800a612: 1d02 adds r2, r0, #4 + 800a614: 70c1 strb r1, [r0, #3] + 800a616: e7ef b.n 800a5f8 <__exponent+0x46> + +0800a618 <_printf_float>: + 800a618: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 800a61c: b08d sub sp, #52 ; 0x34 + 800a61e: 460c mov r4, r1 + 800a620: f8dd 8058 ldr.w r8, [sp, #88] ; 0x58 + 800a624: 4616 mov r6, r2 + 800a626: 461f mov r7, r3 + 800a628: 4605 mov r5, r0 + 800a62a: f003 f8ab bl 800d784 <_localeconv_r> + 800a62e: 6803 ldr r3, [r0, #0] + 800a630: 9304 str r3, [sp, #16] + 800a632: 4618 mov r0, r3 + 800a634: f7f5 fdd4 bl 80001e0 + 800a638: 2300 movs r3, #0 + 800a63a: 930a str r3, [sp, #40] ; 0x28 + 800a63c: f8d8 3000 ldr.w r3, [r8] + 800a640: 9005 str r0, [sp, #20] + 800a642: 3307 adds r3, #7 + 800a644: f023 0307 bic.w r3, r3, #7 + 800a648: f103 0208 add.w r2, r3, #8 + 800a64c: f894 a018 ldrb.w sl, [r4, #24] + 800a650: f8d4 b000 ldr.w fp, [r4] + 800a654: f8c8 2000 str.w r2, [r8] + 800a658: e9d3 2300 ldrd r2, r3, [r3] + 800a65c: e9c4 2312 strd r2, r3, [r4, #72] ; 0x48 + 800a660: e9d4 8912 ldrd r8, r9, [r4, #72] ; 0x48 + 800a664: f029 4300 bic.w r3, r9, #2147483648 ; 0x80000000 + 800a668: 9307 str r3, [sp, #28] + 800a66a: f8cd 8018 str.w r8, [sp, #24] + 800a66e: f04f 32ff mov.w r2, #4294967295 + 800a672: 4ba7 ldr r3, [pc, #668] ; (800a910 <_printf_float+0x2f8>) + 800a674: e9dd 0106 ldrd r0, r1, [sp, #24] + 800a678: f7f6 fa60 bl 8000b3c <__aeabi_dcmpun> + 800a67c: bb70 cbnz r0, 800a6dc <_printf_float+0xc4> + 800a67e: f04f 32ff mov.w r2, #4294967295 + 800a682: 4ba3 ldr r3, [pc, #652] ; (800a910 <_printf_float+0x2f8>) + 800a684: e9dd 0106 ldrd r0, r1, [sp, #24] + 800a688: f7f6 fa3a bl 8000b00 <__aeabi_dcmple> + 800a68c: bb30 cbnz r0, 800a6dc <_printf_float+0xc4> + 800a68e: 2200 movs r2, #0 + 800a690: 2300 movs r3, #0 + 800a692: 4640 mov r0, r8 + 800a694: 4649 mov r1, r9 + 800a696: f7f6 fa29 bl 8000aec <__aeabi_dcmplt> + 800a69a: b110 cbz r0, 800a6a2 <_printf_float+0x8a> + 800a69c: 232d movs r3, #45 ; 0x2d + 800a69e: f884 3043 strb.w r3, [r4, #67] ; 0x43 + 800a6a2: 4a9c ldr r2, [pc, #624] ; (800a914 <_printf_float+0x2fc>) + 800a6a4: 4b9c ldr r3, [pc, #624] ; (800a918 <_printf_float+0x300>) + 800a6a6: f1ba 0f47 cmp.w sl, #71 ; 0x47 + 800a6aa: bf8c ite hi + 800a6ac: 4690 movhi r8, r2 + 800a6ae: 4698 movls r8, r3 + 800a6b0: 2303 movs r3, #3 + 800a6b2: f02b 0204 bic.w r2, fp, #4 + 800a6b6: 6123 str r3, [r4, #16] + 800a6b8: 6022 str r2, [r4, #0] + 800a6ba: f04f 0900 mov.w r9, #0 + 800a6be: 9700 str r7, [sp, #0] + 800a6c0: 4633 mov r3, r6 + 800a6c2: aa0b add r2, sp, #44 ; 0x2c + 800a6c4: 4621 mov r1, r4 + 800a6c6: 4628 mov r0, r5 + 800a6c8: f000 f9e6 bl 800aa98 <_printf_common> + 800a6cc: 3001 adds r0, #1 + 800a6ce: f040 808d bne.w 800a7ec <_printf_float+0x1d4> + 800a6d2: f04f 30ff mov.w r0, #4294967295 + 800a6d6: b00d add sp, #52 ; 0x34 + 800a6d8: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 800a6dc: 4642 mov r2, r8 + 800a6de: 464b mov r3, r9 + 800a6e0: 4640 mov r0, r8 + 800a6e2: 4649 mov r1, r9 + 800a6e4: f7f6 fa2a bl 8000b3c <__aeabi_dcmpun> + 800a6e8: b110 cbz r0, 800a6f0 <_printf_float+0xd8> + 800a6ea: 4a8c ldr r2, [pc, #560] ; (800a91c <_printf_float+0x304>) + 800a6ec: 4b8c ldr r3, [pc, #560] ; (800a920 <_printf_float+0x308>) + 800a6ee: e7da b.n 800a6a6 <_printf_float+0x8e> + 800a6f0: 6861 ldr r1, [r4, #4] + 800a6f2: 1c4b adds r3, r1, #1 + 800a6f4: f44b 6280 orr.w r2, fp, #1024 ; 0x400 + 800a6f8: a80a add r0, sp, #40 ; 0x28 + 800a6fa: d13e bne.n 800a77a <_printf_float+0x162> + 800a6fc: 2306 movs r3, #6 + 800a6fe: 6063 str r3, [r4, #4] + 800a700: 2300 movs r3, #0 + 800a702: e9cd 0302 strd r0, r3, [sp, #8] + 800a706: ab09 add r3, sp, #36 ; 0x24 + 800a708: 9300 str r3, [sp, #0] + 800a70a: ec49 8b10 vmov d0, r8, r9 + 800a70e: f10d 0323 add.w r3, sp, #35 ; 0x23 + 800a712: 6022 str r2, [r4, #0] + 800a714: f8cd a004 str.w sl, [sp, #4] + 800a718: 6861 ldr r1, [r4, #4] + 800a71a: 4628 mov r0, r5 + 800a71c: f7ff fee8 bl 800a4f0 <__cvt> + 800a720: f00a 03df and.w r3, sl, #223 ; 0xdf + 800a724: 2b47 cmp r3, #71 ; 0x47 + 800a726: 4680 mov r8, r0 + 800a728: d109 bne.n 800a73e <_printf_float+0x126> + 800a72a: 9b09 ldr r3, [sp, #36] ; 0x24 + 800a72c: 1cd8 adds r0, r3, #3 + 800a72e: db02 blt.n 800a736 <_printf_float+0x11e> + 800a730: 6862 ldr r2, [r4, #4] + 800a732: 4293 cmp r3, r2 + 800a734: dd47 ble.n 800a7c6 <_printf_float+0x1ae> + 800a736: f1aa 0a02 sub.w sl, sl, #2 + 800a73a: fa5f fa8a uxtb.w sl, sl + 800a73e: f1ba 0f65 cmp.w sl, #101 ; 0x65 + 800a742: 9909 ldr r1, [sp, #36] ; 0x24 + 800a744: d824 bhi.n 800a790 <_printf_float+0x178> + 800a746: 3901 subs r1, #1 + 800a748: 4652 mov r2, sl + 800a74a: f104 0050 add.w r0, r4, #80 ; 0x50 + 800a74e: 9109 str r1, [sp, #36] ; 0x24 + 800a750: f7ff ff2f bl 800a5b2 <__exponent> + 800a754: 9a0a ldr r2, [sp, #40] ; 0x28 + 800a756: 1813 adds r3, r2, r0 + 800a758: 2a01 cmp r2, #1 + 800a75a: 4681 mov r9, r0 + 800a75c: 6123 str r3, [r4, #16] + 800a75e: dc02 bgt.n 800a766 <_printf_float+0x14e> + 800a760: 6822 ldr r2, [r4, #0] + 800a762: 07d1 lsls r1, r2, #31 + 800a764: d501 bpl.n 800a76a <_printf_float+0x152> + 800a766: 3301 adds r3, #1 + 800a768: 6123 str r3, [r4, #16] + 800a76a: f89d 3023 ldrb.w r3, [sp, #35] ; 0x23 + 800a76e: 2b00 cmp r3, #0 + 800a770: d0a5 beq.n 800a6be <_printf_float+0xa6> + 800a772: 232d movs r3, #45 ; 0x2d + 800a774: f884 3043 strb.w r3, [r4, #67] ; 0x43 + 800a778: e7a1 b.n 800a6be <_printf_float+0xa6> + 800a77a: f1ba 0f67 cmp.w sl, #103 ; 0x67 + 800a77e: f000 8177 beq.w 800aa70 <_printf_float+0x458> + 800a782: f1ba 0f47 cmp.w sl, #71 ; 0x47 + 800a786: d1bb bne.n 800a700 <_printf_float+0xe8> + 800a788: 2900 cmp r1, #0 + 800a78a: d1b9 bne.n 800a700 <_printf_float+0xe8> + 800a78c: 2301 movs r3, #1 + 800a78e: e7b6 b.n 800a6fe <_printf_float+0xe6> + 800a790: f1ba 0f66 cmp.w sl, #102 ; 0x66 + 800a794: d119 bne.n 800a7ca <_printf_float+0x1b2> + 800a796: 2900 cmp r1, #0 + 800a798: 6863 ldr r3, [r4, #4] + 800a79a: dd0c ble.n 800a7b6 <_printf_float+0x19e> + 800a79c: 6121 str r1, [r4, #16] + 800a79e: b913 cbnz r3, 800a7a6 <_printf_float+0x18e> + 800a7a0: 6822 ldr r2, [r4, #0] + 800a7a2: 07d2 lsls r2, r2, #31 + 800a7a4: d502 bpl.n 800a7ac <_printf_float+0x194> + 800a7a6: 3301 adds r3, #1 + 800a7a8: 440b add r3, r1 + 800a7aa: 6123 str r3, [r4, #16] + 800a7ac: 9b09 ldr r3, [sp, #36] ; 0x24 + 800a7ae: 65a3 str r3, [r4, #88] ; 0x58 + 800a7b0: f04f 0900 mov.w r9, #0 + 800a7b4: e7d9 b.n 800a76a <_printf_float+0x152> + 800a7b6: b913 cbnz r3, 800a7be <_printf_float+0x1a6> + 800a7b8: 6822 ldr r2, [r4, #0] + 800a7ba: 07d0 lsls r0, r2, #31 + 800a7bc: d501 bpl.n 800a7c2 <_printf_float+0x1aa> + 800a7be: 3302 adds r3, #2 + 800a7c0: e7f3 b.n 800a7aa <_printf_float+0x192> + 800a7c2: 2301 movs r3, #1 + 800a7c4: e7f1 b.n 800a7aa <_printf_float+0x192> + 800a7c6: f04f 0a67 mov.w sl, #103 ; 0x67 + 800a7ca: e9dd 3209 ldrd r3, r2, [sp, #36] ; 0x24 + 800a7ce: 4293 cmp r3, r2 + 800a7d0: db05 blt.n 800a7de <_printf_float+0x1c6> + 800a7d2: 6822 ldr r2, [r4, #0] + 800a7d4: 6123 str r3, [r4, #16] + 800a7d6: 07d1 lsls r1, r2, #31 + 800a7d8: d5e8 bpl.n 800a7ac <_printf_float+0x194> + 800a7da: 3301 adds r3, #1 + 800a7dc: e7e5 b.n 800a7aa <_printf_float+0x192> + 800a7de: 2b00 cmp r3, #0 + 800a7e0: bfd4 ite le + 800a7e2: f1c3 0302 rsble r3, r3, #2 + 800a7e6: 2301 movgt r3, #1 + 800a7e8: 4413 add r3, r2 + 800a7ea: e7de b.n 800a7aa <_printf_float+0x192> + 800a7ec: 6823 ldr r3, [r4, #0] + 800a7ee: 055a lsls r2, r3, #21 + 800a7f0: d407 bmi.n 800a802 <_printf_float+0x1ea> + 800a7f2: 6923 ldr r3, [r4, #16] + 800a7f4: 4642 mov r2, r8 + 800a7f6: 4631 mov r1, r6 + 800a7f8: 4628 mov r0, r5 + 800a7fa: 47b8 blx r7 + 800a7fc: 3001 adds r0, #1 + 800a7fe: d12b bne.n 800a858 <_printf_float+0x240> + 800a800: e767 b.n 800a6d2 <_printf_float+0xba> + 800a802: f1ba 0f65 cmp.w sl, #101 ; 0x65 + 800a806: f240 80dc bls.w 800a9c2 <_printf_float+0x3aa> + 800a80a: 2200 movs r2, #0 + 800a80c: 2300 movs r3, #0 + 800a80e: e9d4 0112 ldrd r0, r1, [r4, #72] ; 0x48 + 800a812: f7f6 f961 bl 8000ad8 <__aeabi_dcmpeq> + 800a816: 2800 cmp r0, #0 + 800a818: d033 beq.n 800a882 <_printf_float+0x26a> + 800a81a: 2301 movs r3, #1 + 800a81c: 4a41 ldr r2, [pc, #260] ; (800a924 <_printf_float+0x30c>) + 800a81e: 4631 mov r1, r6 + 800a820: 4628 mov r0, r5 + 800a822: 47b8 blx r7 + 800a824: 3001 adds r0, #1 + 800a826: f43f af54 beq.w 800a6d2 <_printf_float+0xba> + 800a82a: e9dd 2309 ldrd r2, r3, [sp, #36] ; 0x24 + 800a82e: 429a cmp r2, r3 + 800a830: db02 blt.n 800a838 <_printf_float+0x220> + 800a832: 6823 ldr r3, [r4, #0] + 800a834: 07d8 lsls r0, r3, #31 + 800a836: d50f bpl.n 800a858 <_printf_float+0x240> + 800a838: e9dd 2304 ldrd r2, r3, [sp, #16] + 800a83c: 4631 mov r1, r6 + 800a83e: 4628 mov r0, r5 + 800a840: 47b8 blx r7 + 800a842: 3001 adds r0, #1 + 800a844: f43f af45 beq.w 800a6d2 <_printf_float+0xba> + 800a848: f04f 0800 mov.w r8, #0 + 800a84c: f104 091a add.w r9, r4, #26 + 800a850: 9b0a ldr r3, [sp, #40] ; 0x28 + 800a852: 3b01 subs r3, #1 + 800a854: 4543 cmp r3, r8 + 800a856: dc09 bgt.n 800a86c <_printf_float+0x254> + 800a858: 6823 ldr r3, [r4, #0] + 800a85a: 079b lsls r3, r3, #30 + 800a85c: f100 8103 bmi.w 800aa66 <_printf_float+0x44e> + 800a860: 68e0 ldr r0, [r4, #12] + 800a862: 9b0b ldr r3, [sp, #44] ; 0x2c + 800a864: 4298 cmp r0, r3 + 800a866: bfb8 it lt + 800a868: 4618 movlt r0, r3 + 800a86a: e734 b.n 800a6d6 <_printf_float+0xbe> + 800a86c: 2301 movs r3, #1 + 800a86e: 464a mov r2, r9 + 800a870: 4631 mov r1, r6 + 800a872: 4628 mov r0, r5 + 800a874: 47b8 blx r7 + 800a876: 3001 adds r0, #1 + 800a878: f43f af2b beq.w 800a6d2 <_printf_float+0xba> + 800a87c: f108 0801 add.w r8, r8, #1 + 800a880: e7e6 b.n 800a850 <_printf_float+0x238> + 800a882: 9b09 ldr r3, [sp, #36] ; 0x24 + 800a884: 2b00 cmp r3, #0 + 800a886: dc2b bgt.n 800a8e0 <_printf_float+0x2c8> + 800a888: 2301 movs r3, #1 + 800a88a: 4a26 ldr r2, [pc, #152] ; (800a924 <_printf_float+0x30c>) + 800a88c: 4631 mov r1, r6 + 800a88e: 4628 mov r0, r5 + 800a890: 47b8 blx r7 + 800a892: 3001 adds r0, #1 + 800a894: f43f af1d beq.w 800a6d2 <_printf_float+0xba> + 800a898: 9b09 ldr r3, [sp, #36] ; 0x24 + 800a89a: b923 cbnz r3, 800a8a6 <_printf_float+0x28e> + 800a89c: 9b0a ldr r3, [sp, #40] ; 0x28 + 800a89e: b913 cbnz r3, 800a8a6 <_printf_float+0x28e> + 800a8a0: 6823 ldr r3, [r4, #0] + 800a8a2: 07d9 lsls r1, r3, #31 + 800a8a4: d5d8 bpl.n 800a858 <_printf_float+0x240> + 800a8a6: e9dd 2304 ldrd r2, r3, [sp, #16] + 800a8aa: 4631 mov r1, r6 + 800a8ac: 4628 mov r0, r5 + 800a8ae: 47b8 blx r7 + 800a8b0: 3001 adds r0, #1 + 800a8b2: f43f af0e beq.w 800a6d2 <_printf_float+0xba> + 800a8b6: f04f 0900 mov.w r9, #0 + 800a8ba: f104 0a1a add.w sl, r4, #26 + 800a8be: 9b09 ldr r3, [sp, #36] ; 0x24 + 800a8c0: 425b negs r3, r3 + 800a8c2: 454b cmp r3, r9 + 800a8c4: dc01 bgt.n 800a8ca <_printf_float+0x2b2> + 800a8c6: 9b0a ldr r3, [sp, #40] ; 0x28 + 800a8c8: e794 b.n 800a7f4 <_printf_float+0x1dc> + 800a8ca: 2301 movs r3, #1 + 800a8cc: 4652 mov r2, sl + 800a8ce: 4631 mov r1, r6 + 800a8d0: 4628 mov r0, r5 + 800a8d2: 47b8 blx r7 + 800a8d4: 3001 adds r0, #1 + 800a8d6: f43f aefc beq.w 800a6d2 <_printf_float+0xba> + 800a8da: f109 0901 add.w r9, r9, #1 + 800a8de: e7ee b.n 800a8be <_printf_float+0x2a6> + 800a8e0: 9a0a ldr r2, [sp, #40] ; 0x28 + 800a8e2: 6da3 ldr r3, [r4, #88] ; 0x58 + 800a8e4: 429a cmp r2, r3 + 800a8e6: bfa8 it ge + 800a8e8: 461a movge r2, r3 + 800a8ea: 2a00 cmp r2, #0 + 800a8ec: 4691 mov r9, r2 + 800a8ee: dd07 ble.n 800a900 <_printf_float+0x2e8> + 800a8f0: 4613 mov r3, r2 + 800a8f2: 4631 mov r1, r6 + 800a8f4: 4642 mov r2, r8 + 800a8f6: 4628 mov r0, r5 + 800a8f8: 47b8 blx r7 + 800a8fa: 3001 adds r0, #1 + 800a8fc: f43f aee9 beq.w 800a6d2 <_printf_float+0xba> + 800a900: f104 031a add.w r3, r4, #26 + 800a904: f04f 0b00 mov.w fp, #0 + 800a908: ea29 79e9 bic.w r9, r9, r9, asr #31 + 800a90c: 9306 str r3, [sp, #24] + 800a90e: e015 b.n 800a93c <_printf_float+0x324> + 800a910: 7fefffff .word 0x7fefffff + 800a914: 0800e93c .word 0x0800e93c + 800a918: 0800e938 .word 0x0800e938 + 800a91c: 0800e944 .word 0x0800e944 + 800a920: 0800e940 .word 0x0800e940 + 800a924: 0800e948 .word 0x0800e948 + 800a928: 2301 movs r3, #1 + 800a92a: 9a06 ldr r2, [sp, #24] + 800a92c: 4631 mov r1, r6 + 800a92e: 4628 mov r0, r5 + 800a930: 47b8 blx r7 + 800a932: 3001 adds r0, #1 + 800a934: f43f aecd beq.w 800a6d2 <_printf_float+0xba> + 800a938: f10b 0b01 add.w fp, fp, #1 + 800a93c: f8d4 a058 ldr.w sl, [r4, #88] ; 0x58 + 800a940: ebaa 0309 sub.w r3, sl, r9 + 800a944: 455b cmp r3, fp + 800a946: dcef bgt.n 800a928 <_printf_float+0x310> + 800a948: e9dd 2309 ldrd r2, r3, [sp, #36] ; 0x24 + 800a94c: 429a cmp r2, r3 + 800a94e: 44d0 add r8, sl + 800a950: db15 blt.n 800a97e <_printf_float+0x366> + 800a952: 6823 ldr r3, [r4, #0] + 800a954: 07da lsls r2, r3, #31 + 800a956: d412 bmi.n 800a97e <_printf_float+0x366> + 800a958: 9b0a ldr r3, [sp, #40] ; 0x28 + 800a95a: 9909 ldr r1, [sp, #36] ; 0x24 + 800a95c: eba3 020a sub.w r2, r3, sl + 800a960: eba3 0a01 sub.w sl, r3, r1 + 800a964: 4592 cmp sl, r2 + 800a966: bfa8 it ge + 800a968: 4692 movge sl, r2 + 800a96a: f1ba 0f00 cmp.w sl, #0 + 800a96e: dc0e bgt.n 800a98e <_printf_float+0x376> + 800a970: f04f 0800 mov.w r8, #0 + 800a974: ea2a 7aea bic.w sl, sl, sl, asr #31 + 800a978: f104 091a add.w r9, r4, #26 + 800a97c: e019 b.n 800a9b2 <_printf_float+0x39a> + 800a97e: e9dd 2304 ldrd r2, r3, [sp, #16] + 800a982: 4631 mov r1, r6 + 800a984: 4628 mov r0, r5 + 800a986: 47b8 blx r7 + 800a988: 3001 adds r0, #1 + 800a98a: d1e5 bne.n 800a958 <_printf_float+0x340> + 800a98c: e6a1 b.n 800a6d2 <_printf_float+0xba> + 800a98e: 4653 mov r3, sl + 800a990: 4642 mov r2, r8 + 800a992: 4631 mov r1, r6 + 800a994: 4628 mov r0, r5 + 800a996: 47b8 blx r7 + 800a998: 3001 adds r0, #1 + 800a99a: d1e9 bne.n 800a970 <_printf_float+0x358> + 800a99c: e699 b.n 800a6d2 <_printf_float+0xba> + 800a99e: 2301 movs r3, #1 + 800a9a0: 464a mov r2, r9 + 800a9a2: 4631 mov r1, r6 + 800a9a4: 4628 mov r0, r5 + 800a9a6: 47b8 blx r7 + 800a9a8: 3001 adds r0, #1 + 800a9aa: f43f ae92 beq.w 800a6d2 <_printf_float+0xba> + 800a9ae: f108 0801 add.w r8, r8, #1 + 800a9b2: e9dd 2309 ldrd r2, r3, [sp, #36] ; 0x24 + 800a9b6: 1a9b subs r3, r3, r2 + 800a9b8: eba3 030a sub.w r3, r3, sl + 800a9bc: 4543 cmp r3, r8 + 800a9be: dcee bgt.n 800a99e <_printf_float+0x386> + 800a9c0: e74a b.n 800a858 <_printf_float+0x240> + 800a9c2: 9a0a ldr r2, [sp, #40] ; 0x28 + 800a9c4: 2a01 cmp r2, #1 + 800a9c6: dc01 bgt.n 800a9cc <_printf_float+0x3b4> + 800a9c8: 07db lsls r3, r3, #31 + 800a9ca: d53a bpl.n 800aa42 <_printf_float+0x42a> + 800a9cc: 2301 movs r3, #1 + 800a9ce: 4642 mov r2, r8 + 800a9d0: 4631 mov r1, r6 + 800a9d2: 4628 mov r0, r5 + 800a9d4: 47b8 blx r7 + 800a9d6: 3001 adds r0, #1 + 800a9d8: f43f ae7b beq.w 800a6d2 <_printf_float+0xba> + 800a9dc: e9dd 2304 ldrd r2, r3, [sp, #16] + 800a9e0: 4631 mov r1, r6 + 800a9e2: 4628 mov r0, r5 + 800a9e4: 47b8 blx r7 + 800a9e6: 3001 adds r0, #1 + 800a9e8: f108 0801 add.w r8, r8, #1 + 800a9ec: f43f ae71 beq.w 800a6d2 <_printf_float+0xba> + 800a9f0: 9b0a ldr r3, [sp, #40] ; 0x28 + 800a9f2: 2200 movs r2, #0 + 800a9f4: f103 3aff add.w sl, r3, #4294967295 + 800a9f8: e9d4 0112 ldrd r0, r1, [r4, #72] ; 0x48 + 800a9fc: 2300 movs r3, #0 + 800a9fe: f7f6 f86b bl 8000ad8 <__aeabi_dcmpeq> + 800aa02: b9c8 cbnz r0, 800aa38 <_printf_float+0x420> + 800aa04: 4653 mov r3, sl + 800aa06: 4642 mov r2, r8 + 800aa08: 4631 mov r1, r6 + 800aa0a: 4628 mov r0, r5 + 800aa0c: 47b8 blx r7 + 800aa0e: 3001 adds r0, #1 + 800aa10: d10e bne.n 800aa30 <_printf_float+0x418> + 800aa12: e65e b.n 800a6d2 <_printf_float+0xba> + 800aa14: 2301 movs r3, #1 + 800aa16: 4652 mov r2, sl + 800aa18: 4631 mov r1, r6 + 800aa1a: 4628 mov r0, r5 + 800aa1c: 47b8 blx r7 + 800aa1e: 3001 adds r0, #1 + 800aa20: f43f ae57 beq.w 800a6d2 <_printf_float+0xba> + 800aa24: f108 0801 add.w r8, r8, #1 + 800aa28: 9b0a ldr r3, [sp, #40] ; 0x28 + 800aa2a: 3b01 subs r3, #1 + 800aa2c: 4543 cmp r3, r8 + 800aa2e: dcf1 bgt.n 800aa14 <_printf_float+0x3fc> + 800aa30: 464b mov r3, r9 + 800aa32: f104 0250 add.w r2, r4, #80 ; 0x50 + 800aa36: e6de b.n 800a7f6 <_printf_float+0x1de> + 800aa38: f04f 0800 mov.w r8, #0 + 800aa3c: f104 0a1a add.w sl, r4, #26 + 800aa40: e7f2 b.n 800aa28 <_printf_float+0x410> + 800aa42: 2301 movs r3, #1 + 800aa44: e7df b.n 800aa06 <_printf_float+0x3ee> + 800aa46: 2301 movs r3, #1 + 800aa48: 464a mov r2, r9 + 800aa4a: 4631 mov r1, r6 + 800aa4c: 4628 mov r0, r5 + 800aa4e: 47b8 blx r7 + 800aa50: 3001 adds r0, #1 + 800aa52: f43f ae3e beq.w 800a6d2 <_printf_float+0xba> + 800aa56: f108 0801 add.w r8, r8, #1 + 800aa5a: 68e3 ldr r3, [r4, #12] + 800aa5c: 9a0b ldr r2, [sp, #44] ; 0x2c + 800aa5e: 1a9b subs r3, r3, r2 + 800aa60: 4543 cmp r3, r8 + 800aa62: dcf0 bgt.n 800aa46 <_printf_float+0x42e> + 800aa64: e6fc b.n 800a860 <_printf_float+0x248> + 800aa66: f04f 0800 mov.w r8, #0 + 800aa6a: f104 0919 add.w r9, r4, #25 + 800aa6e: e7f4 b.n 800aa5a <_printf_float+0x442> + 800aa70: 2900 cmp r1, #0 + 800aa72: f43f ae8b beq.w 800a78c <_printf_float+0x174> + 800aa76: 2300 movs r3, #0 + 800aa78: e9cd 0302 strd r0, r3, [sp, #8] + 800aa7c: ab09 add r3, sp, #36 ; 0x24 + 800aa7e: 9300 str r3, [sp, #0] + 800aa80: ec49 8b10 vmov d0, r8, r9 + 800aa84: 6022 str r2, [r4, #0] + 800aa86: f8cd a004 str.w sl, [sp, #4] + 800aa8a: f10d 0323 add.w r3, sp, #35 ; 0x23 + 800aa8e: 4628 mov r0, r5 + 800aa90: f7ff fd2e bl 800a4f0 <__cvt> + 800aa94: 4680 mov r8, r0 + 800aa96: e648 b.n 800a72a <_printf_float+0x112> + +0800aa98 <_printf_common>: + 800aa98: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 800aa9c: 4691 mov r9, r2 + 800aa9e: 461f mov r7, r3 + 800aaa0: 688a ldr r2, [r1, #8] + 800aaa2: 690b ldr r3, [r1, #16] + 800aaa4: f8dd 8020 ldr.w r8, [sp, #32] + 800aaa8: 4293 cmp r3, r2 + 800aaaa: bfb8 it lt + 800aaac: 4613 movlt r3, r2 + 800aaae: f8c9 3000 str.w r3, [r9] + 800aab2: f891 2043 ldrb.w r2, [r1, #67] ; 0x43 + 800aab6: 4606 mov r6, r0 + 800aab8: 460c mov r4, r1 + 800aaba: b112 cbz r2, 800aac2 <_printf_common+0x2a> + 800aabc: 3301 adds r3, #1 + 800aabe: f8c9 3000 str.w r3, [r9] + 800aac2: 6823 ldr r3, [r4, #0] + 800aac4: 0699 lsls r1, r3, #26 + 800aac6: bf42 ittt mi + 800aac8: f8d9 3000 ldrmi.w r3, [r9] + 800aacc: 3302 addmi r3, #2 + 800aace: f8c9 3000 strmi.w r3, [r9] + 800aad2: 6825 ldr r5, [r4, #0] + 800aad4: f015 0506 ands.w r5, r5, #6 + 800aad8: d107 bne.n 800aaea <_printf_common+0x52> + 800aada: f104 0a19 add.w sl, r4, #25 + 800aade: 68e3 ldr r3, [r4, #12] + 800aae0: f8d9 2000 ldr.w r2, [r9] + 800aae4: 1a9b subs r3, r3, r2 + 800aae6: 42ab cmp r3, r5 + 800aae8: dc28 bgt.n 800ab3c <_printf_common+0xa4> + 800aaea: f894 3043 ldrb.w r3, [r4, #67] ; 0x43 + 800aaee: 6822 ldr r2, [r4, #0] + 800aaf0: 3300 adds r3, #0 + 800aaf2: bf18 it ne + 800aaf4: 2301 movne r3, #1 + 800aaf6: 0692 lsls r2, r2, #26 + 800aaf8: d42d bmi.n 800ab56 <_printf_common+0xbe> + 800aafa: f104 0243 add.w r2, r4, #67 ; 0x43 + 800aafe: 4639 mov r1, r7 + 800ab00: 4630 mov r0, r6 + 800ab02: 47c0 blx r8 + 800ab04: 3001 adds r0, #1 + 800ab06: d020 beq.n 800ab4a <_printf_common+0xb2> + 800ab08: 6823 ldr r3, [r4, #0] + 800ab0a: 68e5 ldr r5, [r4, #12] + 800ab0c: f8d9 2000 ldr.w r2, [r9] + 800ab10: f003 0306 and.w r3, r3, #6 + 800ab14: 2b04 cmp r3, #4 + 800ab16: bf08 it eq + 800ab18: 1aad subeq r5, r5, r2 + 800ab1a: 68a3 ldr r3, [r4, #8] + 800ab1c: 6922 ldr r2, [r4, #16] + 800ab1e: bf0c ite eq + 800ab20: ea25 75e5 biceq.w r5, r5, r5, asr #31 + 800ab24: 2500 movne r5, #0 + 800ab26: 4293 cmp r3, r2 + 800ab28: bfc4 itt gt + 800ab2a: 1a9b subgt r3, r3, r2 + 800ab2c: 18ed addgt r5, r5, r3 + 800ab2e: f04f 0900 mov.w r9, #0 + 800ab32: 341a adds r4, #26 + 800ab34: 454d cmp r5, r9 + 800ab36: d11a bne.n 800ab6e <_printf_common+0xd6> + 800ab38: 2000 movs r0, #0 + 800ab3a: e008 b.n 800ab4e <_printf_common+0xb6> + 800ab3c: 2301 movs r3, #1 + 800ab3e: 4652 mov r2, sl + 800ab40: 4639 mov r1, r7 + 800ab42: 4630 mov r0, r6 + 800ab44: 47c0 blx r8 + 800ab46: 3001 adds r0, #1 + 800ab48: d103 bne.n 800ab52 <_printf_common+0xba> + 800ab4a: f04f 30ff mov.w r0, #4294967295 + 800ab4e: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 800ab52: 3501 adds r5, #1 + 800ab54: e7c3 b.n 800aade <_printf_common+0x46> + 800ab56: 18e1 adds r1, r4, r3 + 800ab58: 1c5a adds r2, r3, #1 + 800ab5a: 2030 movs r0, #48 ; 0x30 + 800ab5c: f881 0043 strb.w r0, [r1, #67] ; 0x43 + 800ab60: 4422 add r2, r4 + 800ab62: f894 1045 ldrb.w r1, [r4, #69] ; 0x45 + 800ab66: f882 1043 strb.w r1, [r2, #67] ; 0x43 + 800ab6a: 3302 adds r3, #2 + 800ab6c: e7c5 b.n 800aafa <_printf_common+0x62> + 800ab6e: 2301 movs r3, #1 + 800ab70: 4622 mov r2, r4 + 800ab72: 4639 mov r1, r7 + 800ab74: 4630 mov r0, r6 + 800ab76: 47c0 blx r8 + 800ab78: 3001 adds r0, #1 + 800ab7a: d0e6 beq.n 800ab4a <_printf_common+0xb2> + 800ab7c: f109 0901 add.w r9, r9, #1 + 800ab80: e7d8 b.n 800ab34 <_printf_common+0x9c> + ... + +0800ab84 <_printf_i>: + 800ab84: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} + 800ab88: f101 0c43 add.w ip, r1, #67 ; 0x43 + 800ab8c: 460c mov r4, r1 + 800ab8e: 7e09 ldrb r1, [r1, #24] + 800ab90: b085 sub sp, #20 + 800ab92: 296e cmp r1, #110 ; 0x6e + 800ab94: 4617 mov r7, r2 + 800ab96: 4606 mov r6, r0 + 800ab98: 4698 mov r8, r3 + 800ab9a: 9a0c ldr r2, [sp, #48] ; 0x30 + 800ab9c: f000 80b3 beq.w 800ad06 <_printf_i+0x182> + 800aba0: d822 bhi.n 800abe8 <_printf_i+0x64> + 800aba2: 2963 cmp r1, #99 ; 0x63 + 800aba4: d036 beq.n 800ac14 <_printf_i+0x90> + 800aba6: d80a bhi.n 800abbe <_printf_i+0x3a> + 800aba8: 2900 cmp r1, #0 + 800abaa: f000 80b9 beq.w 800ad20 <_printf_i+0x19c> + 800abae: 2958 cmp r1, #88 ; 0x58 + 800abb0: f000 8083 beq.w 800acba <_printf_i+0x136> + 800abb4: f104 0542 add.w r5, r4, #66 ; 0x42 + 800abb8: f884 1042 strb.w r1, [r4, #66] ; 0x42 + 800abbc: e032 b.n 800ac24 <_printf_i+0xa0> + 800abbe: 2964 cmp r1, #100 ; 0x64 + 800abc0: d001 beq.n 800abc6 <_printf_i+0x42> + 800abc2: 2969 cmp r1, #105 ; 0x69 + 800abc4: d1f6 bne.n 800abb4 <_printf_i+0x30> + 800abc6: 6820 ldr r0, [r4, #0] + 800abc8: 6813 ldr r3, [r2, #0] + 800abca: 0605 lsls r5, r0, #24 + 800abcc: f103 0104 add.w r1, r3, #4 + 800abd0: d52a bpl.n 800ac28 <_printf_i+0xa4> + 800abd2: 681b ldr r3, [r3, #0] + 800abd4: 6011 str r1, [r2, #0] + 800abd6: 2b00 cmp r3, #0 + 800abd8: da03 bge.n 800abe2 <_printf_i+0x5e> + 800abda: 222d movs r2, #45 ; 0x2d + 800abdc: 425b negs r3, r3 + 800abde: f884 2043 strb.w r2, [r4, #67] ; 0x43 + 800abe2: 486f ldr r0, [pc, #444] ; (800ada0 <_printf_i+0x21c>) + 800abe4: 220a movs r2, #10 + 800abe6: e039 b.n 800ac5c <_printf_i+0xd8> + 800abe8: 2973 cmp r1, #115 ; 0x73 + 800abea: f000 809d beq.w 800ad28 <_printf_i+0x1a4> + 800abee: d808 bhi.n 800ac02 <_printf_i+0x7e> + 800abf0: 296f cmp r1, #111 ; 0x6f + 800abf2: d020 beq.n 800ac36 <_printf_i+0xb2> + 800abf4: 2970 cmp r1, #112 ; 0x70 + 800abf6: d1dd bne.n 800abb4 <_printf_i+0x30> + 800abf8: 6823 ldr r3, [r4, #0] + 800abfa: f043 0320 orr.w r3, r3, #32 + 800abfe: 6023 str r3, [r4, #0] + 800ac00: e003 b.n 800ac0a <_printf_i+0x86> + 800ac02: 2975 cmp r1, #117 ; 0x75 + 800ac04: d017 beq.n 800ac36 <_printf_i+0xb2> + 800ac06: 2978 cmp r1, #120 ; 0x78 + 800ac08: d1d4 bne.n 800abb4 <_printf_i+0x30> + 800ac0a: 2378 movs r3, #120 ; 0x78 + 800ac0c: f884 3045 strb.w r3, [r4, #69] ; 0x45 + 800ac10: 4864 ldr r0, [pc, #400] ; (800ada4 <_printf_i+0x220>) + 800ac12: e055 b.n 800acc0 <_printf_i+0x13c> + 800ac14: 6813 ldr r3, [r2, #0] + 800ac16: 1d19 adds r1, r3, #4 + 800ac18: 681b ldr r3, [r3, #0] + 800ac1a: 6011 str r1, [r2, #0] + 800ac1c: f104 0542 add.w r5, r4, #66 ; 0x42 + 800ac20: f884 3042 strb.w r3, [r4, #66] ; 0x42 + 800ac24: 2301 movs r3, #1 + 800ac26: e08c b.n 800ad42 <_printf_i+0x1be> + 800ac28: 681b ldr r3, [r3, #0] + 800ac2a: 6011 str r1, [r2, #0] + 800ac2c: f010 0f40 tst.w r0, #64 ; 0x40 + 800ac30: bf18 it ne + 800ac32: b21b sxthne r3, r3 + 800ac34: e7cf b.n 800abd6 <_printf_i+0x52> + 800ac36: 6813 ldr r3, [r2, #0] + 800ac38: 6825 ldr r5, [r4, #0] + 800ac3a: 1d18 adds r0, r3, #4 + 800ac3c: 6010 str r0, [r2, #0] + 800ac3e: 0628 lsls r0, r5, #24 + 800ac40: d501 bpl.n 800ac46 <_printf_i+0xc2> + 800ac42: 681b ldr r3, [r3, #0] + 800ac44: e002 b.n 800ac4c <_printf_i+0xc8> + 800ac46: 0668 lsls r0, r5, #25 + 800ac48: d5fb bpl.n 800ac42 <_printf_i+0xbe> + 800ac4a: 881b ldrh r3, [r3, #0] + 800ac4c: 4854 ldr r0, [pc, #336] ; (800ada0 <_printf_i+0x21c>) + 800ac4e: 296f cmp r1, #111 ; 0x6f + 800ac50: bf14 ite ne + 800ac52: 220a movne r2, #10 + 800ac54: 2208 moveq r2, #8 + 800ac56: 2100 movs r1, #0 + 800ac58: f884 1043 strb.w r1, [r4, #67] ; 0x43 + 800ac5c: 6865 ldr r5, [r4, #4] + 800ac5e: 60a5 str r5, [r4, #8] + 800ac60: 2d00 cmp r5, #0 + 800ac62: f2c0 8095 blt.w 800ad90 <_printf_i+0x20c> + 800ac66: 6821 ldr r1, [r4, #0] + 800ac68: f021 0104 bic.w r1, r1, #4 + 800ac6c: 6021 str r1, [r4, #0] + 800ac6e: 2b00 cmp r3, #0 + 800ac70: d13d bne.n 800acee <_printf_i+0x16a> + 800ac72: 2d00 cmp r5, #0 + 800ac74: f040 808e bne.w 800ad94 <_printf_i+0x210> + 800ac78: 4665 mov r5, ip + 800ac7a: 2a08 cmp r2, #8 + 800ac7c: d10b bne.n 800ac96 <_printf_i+0x112> + 800ac7e: 6823 ldr r3, [r4, #0] + 800ac80: 07db lsls r3, r3, #31 + 800ac82: d508 bpl.n 800ac96 <_printf_i+0x112> + 800ac84: 6923 ldr r3, [r4, #16] + 800ac86: 6862 ldr r2, [r4, #4] + 800ac88: 429a cmp r2, r3 + 800ac8a: bfde ittt le + 800ac8c: 2330 movle r3, #48 ; 0x30 + 800ac8e: f805 3c01 strble.w r3, [r5, #-1] + 800ac92: f105 35ff addle.w r5, r5, #4294967295 + 800ac96: ebac 0305 sub.w r3, ip, r5 + 800ac9a: 6123 str r3, [r4, #16] + 800ac9c: f8cd 8000 str.w r8, [sp] + 800aca0: 463b mov r3, r7 + 800aca2: aa03 add r2, sp, #12 + 800aca4: 4621 mov r1, r4 + 800aca6: 4630 mov r0, r6 + 800aca8: f7ff fef6 bl 800aa98 <_printf_common> + 800acac: 3001 adds r0, #1 + 800acae: d14d bne.n 800ad4c <_printf_i+0x1c8> + 800acb0: f04f 30ff mov.w r0, #4294967295 + 800acb4: b005 add sp, #20 + 800acb6: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} + 800acba: 4839 ldr r0, [pc, #228] ; (800ada0 <_printf_i+0x21c>) + 800acbc: f884 1045 strb.w r1, [r4, #69] ; 0x45 + 800acc0: 6813 ldr r3, [r2, #0] + 800acc2: 6821 ldr r1, [r4, #0] + 800acc4: 1d1d adds r5, r3, #4 + 800acc6: 681b ldr r3, [r3, #0] + 800acc8: 6015 str r5, [r2, #0] + 800acca: 060a lsls r2, r1, #24 + 800accc: d50b bpl.n 800ace6 <_printf_i+0x162> + 800acce: 07ca lsls r2, r1, #31 + 800acd0: bf44 itt mi + 800acd2: f041 0120 orrmi.w r1, r1, #32 + 800acd6: 6021 strmi r1, [r4, #0] + 800acd8: b91b cbnz r3, 800ace2 <_printf_i+0x15e> + 800acda: 6822 ldr r2, [r4, #0] + 800acdc: f022 0220 bic.w r2, r2, #32 + 800ace0: 6022 str r2, [r4, #0] + 800ace2: 2210 movs r2, #16 + 800ace4: e7b7 b.n 800ac56 <_printf_i+0xd2> + 800ace6: 064d lsls r5, r1, #25 + 800ace8: bf48 it mi + 800acea: b29b uxthmi r3, r3 + 800acec: e7ef b.n 800acce <_printf_i+0x14a> + 800acee: 4665 mov r5, ip + 800acf0: fbb3 f1f2 udiv r1, r3, r2 + 800acf4: fb02 3311 mls r3, r2, r1, r3 + 800acf8: 5cc3 ldrb r3, [r0, r3] + 800acfa: f805 3d01 strb.w r3, [r5, #-1]! + 800acfe: 460b mov r3, r1 + 800ad00: 2900 cmp r1, #0 + 800ad02: d1f5 bne.n 800acf0 <_printf_i+0x16c> + 800ad04: e7b9 b.n 800ac7a <_printf_i+0xf6> + 800ad06: 6813 ldr r3, [r2, #0] + 800ad08: 6825 ldr r5, [r4, #0] + 800ad0a: 6961 ldr r1, [r4, #20] + 800ad0c: 1d18 adds r0, r3, #4 + 800ad0e: 6010 str r0, [r2, #0] + 800ad10: 0628 lsls r0, r5, #24 + 800ad12: 681b ldr r3, [r3, #0] + 800ad14: d501 bpl.n 800ad1a <_printf_i+0x196> + 800ad16: 6019 str r1, [r3, #0] + 800ad18: e002 b.n 800ad20 <_printf_i+0x19c> + 800ad1a: 066a lsls r2, r5, #25 + 800ad1c: d5fb bpl.n 800ad16 <_printf_i+0x192> + 800ad1e: 8019 strh r1, [r3, #0] + 800ad20: 2300 movs r3, #0 + 800ad22: 6123 str r3, [r4, #16] + 800ad24: 4665 mov r5, ip + 800ad26: e7b9 b.n 800ac9c <_printf_i+0x118> + 800ad28: 6813 ldr r3, [r2, #0] + 800ad2a: 1d19 adds r1, r3, #4 + 800ad2c: 6011 str r1, [r2, #0] + 800ad2e: 681d ldr r5, [r3, #0] + 800ad30: 6862 ldr r2, [r4, #4] + 800ad32: 2100 movs r1, #0 + 800ad34: 4628 mov r0, r5 + 800ad36: f7f5 fa5b bl 80001f0 + 800ad3a: b108 cbz r0, 800ad40 <_printf_i+0x1bc> + 800ad3c: 1b40 subs r0, r0, r5 + 800ad3e: 6060 str r0, [r4, #4] + 800ad40: 6863 ldr r3, [r4, #4] + 800ad42: 6123 str r3, [r4, #16] + 800ad44: 2300 movs r3, #0 + 800ad46: f884 3043 strb.w r3, [r4, #67] ; 0x43 + 800ad4a: e7a7 b.n 800ac9c <_printf_i+0x118> + 800ad4c: 6923 ldr r3, [r4, #16] + 800ad4e: 462a mov r2, r5 + 800ad50: 4639 mov r1, r7 + 800ad52: 4630 mov r0, r6 + 800ad54: 47c0 blx r8 + 800ad56: 3001 adds r0, #1 + 800ad58: d0aa beq.n 800acb0 <_printf_i+0x12c> + 800ad5a: 6823 ldr r3, [r4, #0] + 800ad5c: 079b lsls r3, r3, #30 + 800ad5e: d413 bmi.n 800ad88 <_printf_i+0x204> + 800ad60: 68e0 ldr r0, [r4, #12] + 800ad62: 9b03 ldr r3, [sp, #12] + 800ad64: 4298 cmp r0, r3 + 800ad66: bfb8 it lt + 800ad68: 4618 movlt r0, r3 + 800ad6a: e7a3 b.n 800acb4 <_printf_i+0x130> + 800ad6c: 2301 movs r3, #1 + 800ad6e: 464a mov r2, r9 + 800ad70: 4639 mov r1, r7 + 800ad72: 4630 mov r0, r6 + 800ad74: 47c0 blx r8 + 800ad76: 3001 adds r0, #1 + 800ad78: d09a beq.n 800acb0 <_printf_i+0x12c> + 800ad7a: 3501 adds r5, #1 + 800ad7c: 68e3 ldr r3, [r4, #12] + 800ad7e: 9a03 ldr r2, [sp, #12] + 800ad80: 1a9b subs r3, r3, r2 + 800ad82: 42ab cmp r3, r5 + 800ad84: dcf2 bgt.n 800ad6c <_printf_i+0x1e8> + 800ad86: e7eb b.n 800ad60 <_printf_i+0x1dc> + 800ad88: 2500 movs r5, #0 + 800ad8a: f104 0919 add.w r9, r4, #25 + 800ad8e: e7f5 b.n 800ad7c <_printf_i+0x1f8> + 800ad90: 2b00 cmp r3, #0 + 800ad92: d1ac bne.n 800acee <_printf_i+0x16a> + 800ad94: 7803 ldrb r3, [r0, #0] + 800ad96: f884 3042 strb.w r3, [r4, #66] ; 0x42 + 800ad9a: f104 0542 add.w r5, r4, #66 ; 0x42 + 800ad9e: e76c b.n 800ac7a <_printf_i+0xf6> + 800ada0: 0800e94a .word 0x0800e94a + 800ada4: 0800e95b .word 0x0800e95b + +0800ada8 <_scanf_float>: + 800ada8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 800adac: 469a mov sl, r3 + 800adae: 688b ldr r3, [r1, #8] + 800adb0: 4616 mov r6, r2 + 800adb2: 1e5a subs r2, r3, #1 + 800adb4: f5b2 7fae cmp.w r2, #348 ; 0x15c + 800adb8: b087 sub sp, #28 + 800adba: bf83 ittte hi + 800adbc: f46f 72ae mvnhi.w r2, #348 ; 0x15c + 800adc0: 189b addhi r3, r3, r2 + 800adc2: 9301 strhi r3, [sp, #4] + 800adc4: 2300 movls r3, #0 + 800adc6: bf86 itte hi + 800adc8: f240 135d movwhi r3, #349 ; 0x15d + 800adcc: 608b strhi r3, [r1, #8] + 800adce: 9301 strls r3, [sp, #4] + 800add0: 680b ldr r3, [r1, #0] + 800add2: 4688 mov r8, r1 + 800add4: f04f 0b00 mov.w fp, #0 + 800add8: f443 63f0 orr.w r3, r3, #1920 ; 0x780 + 800addc: f848 3b1c str.w r3, [r8], #28 + 800ade0: e9cd bb03 strd fp, fp, [sp, #12] + 800ade4: 4607 mov r7, r0 + 800ade6: 460c mov r4, r1 + 800ade8: 4645 mov r5, r8 + 800adea: 465a mov r2, fp + 800adec: 46d9 mov r9, fp + 800adee: f8cd b008 str.w fp, [sp, #8] + 800adf2: 68a1 ldr r1, [r4, #8] + 800adf4: b181 cbz r1, 800ae18 <_scanf_float+0x70> + 800adf6: 6833 ldr r3, [r6, #0] + 800adf8: 781b ldrb r3, [r3, #0] + 800adfa: 2b49 cmp r3, #73 ; 0x49 + 800adfc: d071 beq.n 800aee2 <_scanf_float+0x13a> + 800adfe: d84d bhi.n 800ae9c <_scanf_float+0xf4> + 800ae00: 2b39 cmp r3, #57 ; 0x39 + 800ae02: d840 bhi.n 800ae86 <_scanf_float+0xde> + 800ae04: 2b31 cmp r3, #49 ; 0x31 + 800ae06: f080 8088 bcs.w 800af1a <_scanf_float+0x172> + 800ae0a: 2b2d cmp r3, #45 ; 0x2d + 800ae0c: f000 8090 beq.w 800af30 <_scanf_float+0x188> + 800ae10: d815 bhi.n 800ae3e <_scanf_float+0x96> + 800ae12: 2b2b cmp r3, #43 ; 0x2b + 800ae14: f000 808c beq.w 800af30 <_scanf_float+0x188> + 800ae18: f1b9 0f00 cmp.w r9, #0 + 800ae1c: d003 beq.n 800ae26 <_scanf_float+0x7e> + 800ae1e: 6823 ldr r3, [r4, #0] + 800ae20: f423 7380 bic.w r3, r3, #256 ; 0x100 + 800ae24: 6023 str r3, [r4, #0] + 800ae26: 3a01 subs r2, #1 + 800ae28: 2a01 cmp r2, #1 + 800ae2a: f200 80ea bhi.w 800b002 <_scanf_float+0x25a> + 800ae2e: 4545 cmp r5, r8 + 800ae30: f200 80dc bhi.w 800afec <_scanf_float+0x244> + 800ae34: 2601 movs r6, #1 + 800ae36: 4630 mov r0, r6 + 800ae38: b007 add sp, #28 + 800ae3a: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 800ae3e: 2b2e cmp r3, #46 ; 0x2e + 800ae40: f000 809f beq.w 800af82 <_scanf_float+0x1da> + 800ae44: 2b30 cmp r3, #48 ; 0x30 + 800ae46: d1e7 bne.n 800ae18 <_scanf_float+0x70> + 800ae48: 6820 ldr r0, [r4, #0] + 800ae4a: f410 7f80 tst.w r0, #256 ; 0x100 + 800ae4e: d064 beq.n 800af1a <_scanf_float+0x172> + 800ae50: 9b01 ldr r3, [sp, #4] + 800ae52: f020 0080 bic.w r0, r0, #128 ; 0x80 + 800ae56: 6020 str r0, [r4, #0] + 800ae58: f109 0901 add.w r9, r9, #1 + 800ae5c: b11b cbz r3, 800ae66 <_scanf_float+0xbe> + 800ae5e: 3b01 subs r3, #1 + 800ae60: 3101 adds r1, #1 + 800ae62: 9301 str r3, [sp, #4] + 800ae64: 60a1 str r1, [r4, #8] + 800ae66: 68a3 ldr r3, [r4, #8] + 800ae68: 3b01 subs r3, #1 + 800ae6a: 60a3 str r3, [r4, #8] + 800ae6c: 6923 ldr r3, [r4, #16] + 800ae6e: 3301 adds r3, #1 + 800ae70: 6123 str r3, [r4, #16] + 800ae72: 6873 ldr r3, [r6, #4] + 800ae74: 3b01 subs r3, #1 + 800ae76: 2b00 cmp r3, #0 + 800ae78: 6073 str r3, [r6, #4] + 800ae7a: f340 80ac ble.w 800afd6 <_scanf_float+0x22e> + 800ae7e: 6833 ldr r3, [r6, #0] + 800ae80: 3301 adds r3, #1 + 800ae82: 6033 str r3, [r6, #0] + 800ae84: e7b5 b.n 800adf2 <_scanf_float+0x4a> + 800ae86: 2b45 cmp r3, #69 ; 0x45 + 800ae88: f000 8085 beq.w 800af96 <_scanf_float+0x1ee> + 800ae8c: 2b46 cmp r3, #70 ; 0x46 + 800ae8e: d06a beq.n 800af66 <_scanf_float+0x1be> + 800ae90: 2b41 cmp r3, #65 ; 0x41 + 800ae92: d1c1 bne.n 800ae18 <_scanf_float+0x70> + 800ae94: 2a01 cmp r2, #1 + 800ae96: d1bf bne.n 800ae18 <_scanf_float+0x70> + 800ae98: 2202 movs r2, #2 + 800ae9a: e046 b.n 800af2a <_scanf_float+0x182> + 800ae9c: 2b65 cmp r3, #101 ; 0x65 + 800ae9e: d07a beq.n 800af96 <_scanf_float+0x1ee> + 800aea0: d818 bhi.n 800aed4 <_scanf_float+0x12c> + 800aea2: 2b54 cmp r3, #84 ; 0x54 + 800aea4: d066 beq.n 800af74 <_scanf_float+0x1cc> + 800aea6: d811 bhi.n 800aecc <_scanf_float+0x124> + 800aea8: 2b4e cmp r3, #78 ; 0x4e + 800aeaa: d1b5 bne.n 800ae18 <_scanf_float+0x70> + 800aeac: 2a00 cmp r2, #0 + 800aeae: d146 bne.n 800af3e <_scanf_float+0x196> + 800aeb0: f1b9 0f00 cmp.w r9, #0 + 800aeb4: d145 bne.n 800af42 <_scanf_float+0x19a> + 800aeb6: 6821 ldr r1, [r4, #0] + 800aeb8: f401 60e0 and.w r0, r1, #1792 ; 0x700 + 800aebc: f5b0 6fe0 cmp.w r0, #1792 ; 0x700 + 800aec0: d13f bne.n 800af42 <_scanf_float+0x19a> + 800aec2: f421 61f0 bic.w r1, r1, #1920 ; 0x780 + 800aec6: 6021 str r1, [r4, #0] + 800aec8: 2201 movs r2, #1 + 800aeca: e02e b.n 800af2a <_scanf_float+0x182> + 800aecc: 2b59 cmp r3, #89 ; 0x59 + 800aece: d01e beq.n 800af0e <_scanf_float+0x166> + 800aed0: 2b61 cmp r3, #97 ; 0x61 + 800aed2: e7de b.n 800ae92 <_scanf_float+0xea> + 800aed4: 2b6e cmp r3, #110 ; 0x6e + 800aed6: d0e9 beq.n 800aeac <_scanf_float+0x104> + 800aed8: d815 bhi.n 800af06 <_scanf_float+0x15e> + 800aeda: 2b66 cmp r3, #102 ; 0x66 + 800aedc: d043 beq.n 800af66 <_scanf_float+0x1be> + 800aede: 2b69 cmp r3, #105 ; 0x69 + 800aee0: d19a bne.n 800ae18 <_scanf_float+0x70> + 800aee2: f1bb 0f00 cmp.w fp, #0 + 800aee6: d138 bne.n 800af5a <_scanf_float+0x1b2> + 800aee8: f1b9 0f00 cmp.w r9, #0 + 800aeec: d197 bne.n 800ae1e <_scanf_float+0x76> + 800aeee: 6821 ldr r1, [r4, #0] + 800aef0: f401 60e0 and.w r0, r1, #1792 ; 0x700 + 800aef4: f5b0 6fe0 cmp.w r0, #1792 ; 0x700 + 800aef8: d195 bne.n 800ae26 <_scanf_float+0x7e> + 800aefa: f421 61f0 bic.w r1, r1, #1920 ; 0x780 + 800aefe: 6021 str r1, [r4, #0] + 800af00: f04f 0b01 mov.w fp, #1 + 800af04: e011 b.n 800af2a <_scanf_float+0x182> + 800af06: 2b74 cmp r3, #116 ; 0x74 + 800af08: d034 beq.n 800af74 <_scanf_float+0x1cc> + 800af0a: 2b79 cmp r3, #121 ; 0x79 + 800af0c: d184 bne.n 800ae18 <_scanf_float+0x70> + 800af0e: f1bb 0f07 cmp.w fp, #7 + 800af12: d181 bne.n 800ae18 <_scanf_float+0x70> + 800af14: f04f 0b08 mov.w fp, #8 + 800af18: e007 b.n 800af2a <_scanf_float+0x182> + 800af1a: eb12 0f0b cmn.w r2, fp + 800af1e: f47f af7b bne.w 800ae18 <_scanf_float+0x70> + 800af22: 6821 ldr r1, [r4, #0] + 800af24: f421 71c0 bic.w r1, r1, #384 ; 0x180 + 800af28: 6021 str r1, [r4, #0] + 800af2a: 702b strb r3, [r5, #0] + 800af2c: 3501 adds r5, #1 + 800af2e: e79a b.n 800ae66 <_scanf_float+0xbe> + 800af30: 6821 ldr r1, [r4, #0] + 800af32: 0608 lsls r0, r1, #24 + 800af34: f57f af70 bpl.w 800ae18 <_scanf_float+0x70> + 800af38: f021 0180 bic.w r1, r1, #128 ; 0x80 + 800af3c: e7f4 b.n 800af28 <_scanf_float+0x180> + 800af3e: 2a02 cmp r2, #2 + 800af40: d047 beq.n 800afd2 <_scanf_float+0x22a> + 800af42: f1bb 0f01 cmp.w fp, #1 + 800af46: d003 beq.n 800af50 <_scanf_float+0x1a8> + 800af48: f1bb 0f04 cmp.w fp, #4 + 800af4c: f47f af64 bne.w 800ae18 <_scanf_float+0x70> + 800af50: f10b 0b01 add.w fp, fp, #1 + 800af54: fa5f fb8b uxtb.w fp, fp + 800af58: e7e7 b.n 800af2a <_scanf_float+0x182> + 800af5a: f1bb 0f03 cmp.w fp, #3 + 800af5e: d0f7 beq.n 800af50 <_scanf_float+0x1a8> + 800af60: f1bb 0f05 cmp.w fp, #5 + 800af64: e7f2 b.n 800af4c <_scanf_float+0x1a4> + 800af66: f1bb 0f02 cmp.w fp, #2 + 800af6a: f47f af55 bne.w 800ae18 <_scanf_float+0x70> + 800af6e: f04f 0b03 mov.w fp, #3 + 800af72: e7da b.n 800af2a <_scanf_float+0x182> + 800af74: f1bb 0f06 cmp.w fp, #6 + 800af78: f47f af4e bne.w 800ae18 <_scanf_float+0x70> + 800af7c: f04f 0b07 mov.w fp, #7 + 800af80: e7d3 b.n 800af2a <_scanf_float+0x182> + 800af82: 6821 ldr r1, [r4, #0] + 800af84: 0588 lsls r0, r1, #22 + 800af86: f57f af47 bpl.w 800ae18 <_scanf_float+0x70> + 800af8a: f421 7120 bic.w r1, r1, #640 ; 0x280 + 800af8e: 6021 str r1, [r4, #0] + 800af90: f8cd 9008 str.w r9, [sp, #8] + 800af94: e7c9 b.n 800af2a <_scanf_float+0x182> + 800af96: 6821 ldr r1, [r4, #0] + 800af98: f401 60a0 and.w r0, r1, #1280 ; 0x500 + 800af9c: f5b0 6f80 cmp.w r0, #1024 ; 0x400 + 800afa0: d006 beq.n 800afb0 <_scanf_float+0x208> + 800afa2: 0548 lsls r0, r1, #21 + 800afa4: f57f af38 bpl.w 800ae18 <_scanf_float+0x70> + 800afa8: f1b9 0f00 cmp.w r9, #0 + 800afac: f43f af3b beq.w 800ae26 <_scanf_float+0x7e> + 800afb0: 0588 lsls r0, r1, #22 + 800afb2: bf58 it pl + 800afb4: 9802 ldrpl r0, [sp, #8] + 800afb6: f421 61f0 bic.w r1, r1, #1920 ; 0x780 + 800afba: bf58 it pl + 800afbc: eba9 0000 subpl.w r0, r9, r0 + 800afc0: f441 71c0 orr.w r1, r1, #384 ; 0x180 + 800afc4: bf58 it pl + 800afc6: e9cd 0503 strdpl r0, r5, [sp, #12] + 800afca: 6021 str r1, [r4, #0] + 800afcc: f04f 0900 mov.w r9, #0 + 800afd0: e7ab b.n 800af2a <_scanf_float+0x182> + 800afd2: 2203 movs r2, #3 + 800afd4: e7a9 b.n 800af2a <_scanf_float+0x182> + 800afd6: f8d4 3180 ldr.w r3, [r4, #384] ; 0x180 + 800afda: 9205 str r2, [sp, #20] + 800afdc: 4631 mov r1, r6 + 800afde: 4638 mov r0, r7 + 800afe0: 4798 blx r3 + 800afe2: 9a05 ldr r2, [sp, #20] + 800afe4: 2800 cmp r0, #0 + 800afe6: f43f af04 beq.w 800adf2 <_scanf_float+0x4a> + 800afea: e715 b.n 800ae18 <_scanf_float+0x70> + 800afec: f8d4 317c ldr.w r3, [r4, #380] ; 0x17c + 800aff0: f815 1d01 ldrb.w r1, [r5, #-1]! + 800aff4: 4632 mov r2, r6 + 800aff6: 4638 mov r0, r7 + 800aff8: 4798 blx r3 + 800affa: 6923 ldr r3, [r4, #16] + 800affc: 3b01 subs r3, #1 + 800affe: 6123 str r3, [r4, #16] + 800b000: e715 b.n 800ae2e <_scanf_float+0x86> + 800b002: f10b 33ff add.w r3, fp, #4294967295 + 800b006: 2b06 cmp r3, #6 + 800b008: d80a bhi.n 800b020 <_scanf_float+0x278> + 800b00a: f1bb 0f02 cmp.w fp, #2 + 800b00e: d968 bls.n 800b0e2 <_scanf_float+0x33a> + 800b010: f1ab 0b03 sub.w fp, fp, #3 + 800b014: fa5f fb8b uxtb.w fp, fp + 800b018: eba5 0b0b sub.w fp, r5, fp + 800b01c: 455d cmp r5, fp + 800b01e: d14b bne.n 800b0b8 <_scanf_float+0x310> + 800b020: 6823 ldr r3, [r4, #0] + 800b022: 05da lsls r2, r3, #23 + 800b024: d51f bpl.n 800b066 <_scanf_float+0x2be> + 800b026: 055b lsls r3, r3, #21 + 800b028: d468 bmi.n 800b0fc <_scanf_float+0x354> + 800b02a: f815 1c01 ldrb.w r1, [r5, #-1] + 800b02e: 6923 ldr r3, [r4, #16] + 800b030: 2965 cmp r1, #101 ; 0x65 + 800b032: f103 33ff add.w r3, r3, #4294967295 + 800b036: f105 3bff add.w fp, r5, #4294967295 + 800b03a: 6123 str r3, [r4, #16] + 800b03c: d00d beq.n 800b05a <_scanf_float+0x2b2> + 800b03e: 2945 cmp r1, #69 ; 0x45 + 800b040: d00b beq.n 800b05a <_scanf_float+0x2b2> + 800b042: f8d4 317c ldr.w r3, [r4, #380] ; 0x17c + 800b046: 4632 mov r2, r6 + 800b048: 4638 mov r0, r7 + 800b04a: 4798 blx r3 + 800b04c: 6923 ldr r3, [r4, #16] + 800b04e: f815 1c02 ldrb.w r1, [r5, #-2] + 800b052: 3b01 subs r3, #1 + 800b054: f1a5 0b02 sub.w fp, r5, #2 + 800b058: 6123 str r3, [r4, #16] + 800b05a: f8d4 317c ldr.w r3, [r4, #380] ; 0x17c + 800b05e: 4632 mov r2, r6 + 800b060: 4638 mov r0, r7 + 800b062: 4798 blx r3 + 800b064: 465d mov r5, fp + 800b066: 6826 ldr r6, [r4, #0] + 800b068: f016 0610 ands.w r6, r6, #16 + 800b06c: d17a bne.n 800b164 <_scanf_float+0x3bc> + 800b06e: 702e strb r6, [r5, #0] + 800b070: 6823 ldr r3, [r4, #0] + 800b072: f403 63c0 and.w r3, r3, #1536 ; 0x600 + 800b076: f5b3 6f80 cmp.w r3, #1024 ; 0x400 + 800b07a: d142 bne.n 800b102 <_scanf_float+0x35a> + 800b07c: 9b02 ldr r3, [sp, #8] + 800b07e: eba9 0303 sub.w r3, r9, r3 + 800b082: 425a negs r2, r3 + 800b084: 2b00 cmp r3, #0 + 800b086: d149 bne.n 800b11c <_scanf_float+0x374> + 800b088: 2200 movs r2, #0 + 800b08a: 4641 mov r1, r8 + 800b08c: 4638 mov r0, r7 + 800b08e: f000 ff2f bl 800bef0 <_strtod_r> + 800b092: 6825 ldr r5, [r4, #0] + 800b094: f8da 3000 ldr.w r3, [sl] + 800b098: f015 0f02 tst.w r5, #2 + 800b09c: f103 0204 add.w r2, r3, #4 + 800b0a0: ec59 8b10 vmov r8, r9, d0 + 800b0a4: f8ca 2000 str.w r2, [sl] + 800b0a8: d043 beq.n 800b132 <_scanf_float+0x38a> + 800b0aa: 681b ldr r3, [r3, #0] + 800b0ac: e9c3 8900 strd r8, r9, [r3] + 800b0b0: 68e3 ldr r3, [r4, #12] + 800b0b2: 3301 adds r3, #1 + 800b0b4: 60e3 str r3, [r4, #12] + 800b0b6: e6be b.n 800ae36 <_scanf_float+0x8e> + 800b0b8: f8d4 317c ldr.w r3, [r4, #380] ; 0x17c + 800b0bc: f815 1d01 ldrb.w r1, [r5, #-1]! + 800b0c0: 4632 mov r2, r6 + 800b0c2: 4638 mov r0, r7 + 800b0c4: 4798 blx r3 + 800b0c6: 6923 ldr r3, [r4, #16] + 800b0c8: 3b01 subs r3, #1 + 800b0ca: 6123 str r3, [r4, #16] + 800b0cc: e7a6 b.n 800b01c <_scanf_float+0x274> + 800b0ce: f8d4 317c ldr.w r3, [r4, #380] ; 0x17c + 800b0d2: f815 1d01 ldrb.w r1, [r5, #-1]! + 800b0d6: 4632 mov r2, r6 + 800b0d8: 4638 mov r0, r7 + 800b0da: 4798 blx r3 + 800b0dc: 6923 ldr r3, [r4, #16] + 800b0de: 3b01 subs r3, #1 + 800b0e0: 6123 str r3, [r4, #16] + 800b0e2: 4545 cmp r5, r8 + 800b0e4: d8f3 bhi.n 800b0ce <_scanf_float+0x326> + 800b0e6: e6a5 b.n 800ae34 <_scanf_float+0x8c> + 800b0e8: f8d4 317c ldr.w r3, [r4, #380] ; 0x17c + 800b0ec: f815 1d01 ldrb.w r1, [r5, #-1]! + 800b0f0: 4632 mov r2, r6 + 800b0f2: 4638 mov r0, r7 + 800b0f4: 4798 blx r3 + 800b0f6: 6923 ldr r3, [r4, #16] + 800b0f8: 3b01 subs r3, #1 + 800b0fa: 6123 str r3, [r4, #16] + 800b0fc: 4545 cmp r5, r8 + 800b0fe: d8f3 bhi.n 800b0e8 <_scanf_float+0x340> + 800b100: e698 b.n 800ae34 <_scanf_float+0x8c> + 800b102: 9b03 ldr r3, [sp, #12] + 800b104: 2b00 cmp r3, #0 + 800b106: d0bf beq.n 800b088 <_scanf_float+0x2e0> + 800b108: 9904 ldr r1, [sp, #16] + 800b10a: 230a movs r3, #10 + 800b10c: 4632 mov r2, r6 + 800b10e: 3101 adds r1, #1 + 800b110: 4638 mov r0, r7 + 800b112: f000 ff79 bl 800c008 <_strtol_r> + 800b116: 9b03 ldr r3, [sp, #12] + 800b118: 9d04 ldr r5, [sp, #16] + 800b11a: 1ac2 subs r2, r0, r3 + 800b11c: f204 136f addw r3, r4, #367 ; 0x16f + 800b120: 429d cmp r5, r3 + 800b122: bf28 it cs + 800b124: f504 75b7 addcs.w r5, r4, #366 ; 0x16e + 800b128: 490f ldr r1, [pc, #60] ; (800b168 <_scanf_float+0x3c0>) + 800b12a: 4628 mov r0, r5 + 800b12c: f000 f8b0 bl 800b290 + 800b130: e7aa b.n 800b088 <_scanf_float+0x2e0> + 800b132: f015 0504 ands.w r5, r5, #4 + 800b136: d1b8 bne.n 800b0aa <_scanf_float+0x302> + 800b138: 681f ldr r7, [r3, #0] + 800b13a: ee10 2a10 vmov r2, s0 + 800b13e: 464b mov r3, r9 + 800b140: ee10 0a10 vmov r0, s0 + 800b144: 4649 mov r1, r9 + 800b146: f7f5 fcf9 bl 8000b3c <__aeabi_dcmpun> + 800b14a: b128 cbz r0, 800b158 <_scanf_float+0x3b0> + 800b14c: 4628 mov r0, r5 + 800b14e: f000 f899 bl 800b284 + 800b152: ed87 0a00 vstr s0, [r7] + 800b156: e7ab b.n 800b0b0 <_scanf_float+0x308> + 800b158: 4640 mov r0, r8 + 800b15a: 4649 mov r1, r9 + 800b15c: f7f5 fd4c bl 8000bf8 <__aeabi_d2f> + 800b160: 6038 str r0, [r7, #0] + 800b162: e7a5 b.n 800b0b0 <_scanf_float+0x308> + 800b164: 2600 movs r6, #0 + 800b166: e666 b.n 800ae36 <_scanf_float+0x8e> + 800b168: 0800e96c .word 0x0800e96c + +0800b16c : + 800b16c: b40f push {r0, r1, r2, r3} + 800b16e: 4b0a ldr r3, [pc, #40] ; (800b198 ) + 800b170: b513 push {r0, r1, r4, lr} + 800b172: 681c ldr r4, [r3, #0] + 800b174: b124 cbz r4, 800b180 + 800b176: 69a3 ldr r3, [r4, #24] + 800b178: b913 cbnz r3, 800b180 + 800b17a: 4620 mov r0, r4 + 800b17c: f001 ff4c bl 800d018 <__sinit> + 800b180: ab05 add r3, sp, #20 + 800b182: 9a04 ldr r2, [sp, #16] + 800b184: 68a1 ldr r1, [r4, #8] + 800b186: 9301 str r3, [sp, #4] + 800b188: 4620 mov r0, r4 + 800b18a: f003 f915 bl 800e3b8 <_vfiprintf_r> + 800b18e: b002 add sp, #8 + 800b190: e8bd 4010 ldmia.w sp!, {r4, lr} + 800b194: b004 add sp, #16 + 800b196: 4770 bx lr + 800b198: 2000002c .word 0x2000002c + +0800b19c <_puts_r>: + 800b19c: b570 push {r4, r5, r6, lr} + 800b19e: 460e mov r6, r1 + 800b1a0: 4605 mov r5, r0 + 800b1a2: b118 cbz r0, 800b1ac <_puts_r+0x10> + 800b1a4: 6983 ldr r3, [r0, #24] + 800b1a6: b90b cbnz r3, 800b1ac <_puts_r+0x10> + 800b1a8: f001 ff36 bl 800d018 <__sinit> + 800b1ac: 69ab ldr r3, [r5, #24] + 800b1ae: 68ac ldr r4, [r5, #8] + 800b1b0: b913 cbnz r3, 800b1b8 <_puts_r+0x1c> + 800b1b2: 4628 mov r0, r5 + 800b1b4: f001 ff30 bl 800d018 <__sinit> + 800b1b8: 4b23 ldr r3, [pc, #140] ; (800b248 <_puts_r+0xac>) + 800b1ba: 429c cmp r4, r3 + 800b1bc: d117 bne.n 800b1ee <_puts_r+0x52> + 800b1be: 686c ldr r4, [r5, #4] + 800b1c0: 89a3 ldrh r3, [r4, #12] + 800b1c2: 071b lsls r3, r3, #28 + 800b1c4: d51d bpl.n 800b202 <_puts_r+0x66> + 800b1c6: 6923 ldr r3, [r4, #16] + 800b1c8: b1db cbz r3, 800b202 <_puts_r+0x66> + 800b1ca: 3e01 subs r6, #1 + 800b1cc: 68a3 ldr r3, [r4, #8] + 800b1ce: f816 1f01 ldrb.w r1, [r6, #1]! + 800b1d2: 3b01 subs r3, #1 + 800b1d4: 60a3 str r3, [r4, #8] + 800b1d6: b9e9 cbnz r1, 800b214 <_puts_r+0x78> + 800b1d8: 2b00 cmp r3, #0 + 800b1da: da2e bge.n 800b23a <_puts_r+0x9e> + 800b1dc: 4622 mov r2, r4 + 800b1de: 210a movs r1, #10 + 800b1e0: 4628 mov r0, r5 + 800b1e2: f000 ff23 bl 800c02c <__swbuf_r> + 800b1e6: 3001 adds r0, #1 + 800b1e8: d011 beq.n 800b20e <_puts_r+0x72> + 800b1ea: 200a movs r0, #10 + 800b1ec: e011 b.n 800b212 <_puts_r+0x76> + 800b1ee: 4b17 ldr r3, [pc, #92] ; (800b24c <_puts_r+0xb0>) + 800b1f0: 429c cmp r4, r3 + 800b1f2: d101 bne.n 800b1f8 <_puts_r+0x5c> + 800b1f4: 68ac ldr r4, [r5, #8] + 800b1f6: e7e3 b.n 800b1c0 <_puts_r+0x24> + 800b1f8: 4b15 ldr r3, [pc, #84] ; (800b250 <_puts_r+0xb4>) + 800b1fa: 429c cmp r4, r3 + 800b1fc: bf08 it eq + 800b1fe: 68ec ldreq r4, [r5, #12] + 800b200: e7de b.n 800b1c0 <_puts_r+0x24> + 800b202: 4621 mov r1, r4 + 800b204: 4628 mov r0, r5 + 800b206: f000 ff63 bl 800c0d0 <__swsetup_r> + 800b20a: 2800 cmp r0, #0 + 800b20c: d0dd beq.n 800b1ca <_puts_r+0x2e> + 800b20e: f04f 30ff mov.w r0, #4294967295 + 800b212: bd70 pop {r4, r5, r6, pc} + 800b214: 2b00 cmp r3, #0 + 800b216: da04 bge.n 800b222 <_puts_r+0x86> + 800b218: 69a2 ldr r2, [r4, #24] + 800b21a: 429a cmp r2, r3 + 800b21c: dc06 bgt.n 800b22c <_puts_r+0x90> + 800b21e: 290a cmp r1, #10 + 800b220: d004 beq.n 800b22c <_puts_r+0x90> + 800b222: 6823 ldr r3, [r4, #0] + 800b224: 1c5a adds r2, r3, #1 + 800b226: 6022 str r2, [r4, #0] + 800b228: 7019 strb r1, [r3, #0] + 800b22a: e7cf b.n 800b1cc <_puts_r+0x30> + 800b22c: 4622 mov r2, r4 + 800b22e: 4628 mov r0, r5 + 800b230: f000 fefc bl 800c02c <__swbuf_r> + 800b234: 3001 adds r0, #1 + 800b236: d1c9 bne.n 800b1cc <_puts_r+0x30> + 800b238: e7e9 b.n 800b20e <_puts_r+0x72> + 800b23a: 6823 ldr r3, [r4, #0] + 800b23c: 200a movs r0, #10 + 800b23e: 1c5a adds r2, r3, #1 + 800b240: 6022 str r2, [r4, #0] + 800b242: 7018 strb r0, [r3, #0] + 800b244: e7e5 b.n 800b212 <_puts_r+0x76> + 800b246: bf00 nop + 800b248: 0800e9f8 .word 0x0800e9f8 + 800b24c: 0800ea18 .word 0x0800ea18 + 800b250: 0800e9d8 .word 0x0800e9d8 + +0800b254 : + 800b254: 4b02 ldr r3, [pc, #8] ; (800b260 ) + 800b256: 4601 mov r1, r0 + 800b258: 6818 ldr r0, [r3, #0] + 800b25a: f7ff bf9f b.w 800b19c <_puts_r> + 800b25e: bf00 nop + 800b260: 2000002c .word 0x2000002c + +0800b264 <_sbrk_r>: + 800b264: b538 push {r3, r4, r5, lr} + 800b266: 4c06 ldr r4, [pc, #24] ; (800b280 <_sbrk_r+0x1c>) + 800b268: 2300 movs r3, #0 + 800b26a: 4605 mov r5, r0 + 800b26c: 4608 mov r0, r1 + 800b26e: 6023 str r3, [r4, #0] + 800b270: f7f6 fc76 bl 8001b60 <_sbrk> + 800b274: 1c43 adds r3, r0, #1 + 800b276: d102 bne.n 800b27e <_sbrk_r+0x1a> + 800b278: 6823 ldr r3, [r4, #0] + 800b27a: b103 cbz r3, 800b27e <_sbrk_r+0x1a> + 800b27c: 602b str r3, [r5, #0] + 800b27e: bd38 pop {r3, r4, r5, pc} + 800b280: 20000ab0 .word 0x20000ab0 + +0800b284 : + 800b284: ed9f 0a01 vldr s0, [pc, #4] ; 800b28c + 800b288: 4770 bx lr + 800b28a: bf00 nop + 800b28c: 7fc00000 .word 0x7fc00000 + +0800b290 : + 800b290: b40e push {r1, r2, r3} + 800b292: b500 push {lr} + 800b294: b09c sub sp, #112 ; 0x70 + 800b296: ab1d add r3, sp, #116 ; 0x74 + 800b298: 9002 str r0, [sp, #8] + 800b29a: 9006 str r0, [sp, #24] + 800b29c: f06f 4100 mvn.w r1, #2147483648 ; 0x80000000 + 800b2a0: 4809 ldr r0, [pc, #36] ; (800b2c8 ) + 800b2a2: 9107 str r1, [sp, #28] + 800b2a4: 9104 str r1, [sp, #16] + 800b2a6: 4909 ldr r1, [pc, #36] ; (800b2cc ) + 800b2a8: f853 2b04 ldr.w r2, [r3], #4 + 800b2ac: 9105 str r1, [sp, #20] + 800b2ae: 6800 ldr r0, [r0, #0] + 800b2b0: 9301 str r3, [sp, #4] + 800b2b2: a902 add r1, sp, #8 + 800b2b4: f002 ff5e bl 800e174 <_svfiprintf_r> + 800b2b8: 9b02 ldr r3, [sp, #8] + 800b2ba: 2200 movs r2, #0 + 800b2bc: 701a strb r2, [r3, #0] + 800b2be: b01c add sp, #112 ; 0x70 + 800b2c0: f85d eb04 ldr.w lr, [sp], #4 + 800b2c4: b003 add sp, #12 + 800b2c6: 4770 bx lr + 800b2c8: 2000002c .word 0x2000002c + 800b2cc: ffff0208 .word 0xffff0208 + +0800b2d0 : + 800b2d0: b570 push {r4, r5, r6, lr} + 800b2d2: 4604 mov r4, r0 + 800b2d4: 460d mov r5, r1 + 800b2d6: ec45 4b10 vmov d0, r4, r5 + 800b2da: 4616 mov r6, r2 + 800b2dc: f002 fdae bl 800de3c <__ulp> + 800b2e0: ec51 0b10 vmov r0, r1, d0 + 800b2e4: b17e cbz r6, 800b306 + 800b2e6: f3c5 530a ubfx r3, r5, #20, #11 + 800b2ea: f1c3 036b rsb r3, r3, #107 ; 0x6b + 800b2ee: 2b00 cmp r3, #0 + 800b2f0: dd09 ble.n 800b306 + 800b2f2: 051b lsls r3, r3, #20 + 800b2f4: f103 557f add.w r5, r3, #1069547520 ; 0x3fc00000 + 800b2f8: 2400 movs r4, #0 + 800b2fa: f505 1540 add.w r5, r5, #3145728 ; 0x300000 + 800b2fe: 4622 mov r2, r4 + 800b300: 462b mov r3, r5 + 800b302: f7f5 f981 bl 8000608 <__aeabi_dmul> + 800b306: bd70 pop {r4, r5, r6, pc} + +0800b308 <_strtod_l>: + 800b308: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 800b30c: 461f mov r7, r3 + 800b30e: b0a1 sub sp, #132 ; 0x84 + 800b310: 2300 movs r3, #0 + 800b312: 4681 mov r9, r0 + 800b314: 4638 mov r0, r7 + 800b316: 460e mov r6, r1 + 800b318: 9217 str r2, [sp, #92] ; 0x5c + 800b31a: 931c str r3, [sp, #112] ; 0x70 + 800b31c: f002 fa2f bl 800d77e <__localeconv_l> + 800b320: 4680 mov r8, r0 + 800b322: 6800 ldr r0, [r0, #0] + 800b324: f7f4 ff5c bl 80001e0 + 800b328: f04f 0a00 mov.w sl, #0 + 800b32c: 4604 mov r4, r0 + 800b32e: f04f 0b00 mov.w fp, #0 + 800b332: 961b str r6, [sp, #108] ; 0x6c + 800b334: 9b1b ldr r3, [sp, #108] ; 0x6c + 800b336: 781a ldrb r2, [r3, #0] + 800b338: 2a0d cmp r2, #13 + 800b33a: d832 bhi.n 800b3a2 <_strtod_l+0x9a> + 800b33c: 2a09 cmp r2, #9 + 800b33e: d236 bcs.n 800b3ae <_strtod_l+0xa6> + 800b340: 2a00 cmp r2, #0 + 800b342: d03e beq.n 800b3c2 <_strtod_l+0xba> + 800b344: 2300 movs r3, #0 + 800b346: 930d str r3, [sp, #52] ; 0x34 + 800b348: 9d1b ldr r5, [sp, #108] ; 0x6c + 800b34a: 782b ldrb r3, [r5, #0] + 800b34c: 2b30 cmp r3, #48 ; 0x30 + 800b34e: f040 80ac bne.w 800b4aa <_strtod_l+0x1a2> + 800b352: 786b ldrb r3, [r5, #1] + 800b354: 2b58 cmp r3, #88 ; 0x58 + 800b356: d001 beq.n 800b35c <_strtod_l+0x54> + 800b358: 2b78 cmp r3, #120 ; 0x78 + 800b35a: d167 bne.n 800b42c <_strtod_l+0x124> + 800b35c: 9b0d ldr r3, [sp, #52] ; 0x34 + 800b35e: 9301 str r3, [sp, #4] + 800b360: ab1c add r3, sp, #112 ; 0x70 + 800b362: 9300 str r3, [sp, #0] + 800b364: 9702 str r7, [sp, #8] + 800b366: ab1d add r3, sp, #116 ; 0x74 + 800b368: 4a88 ldr r2, [pc, #544] ; (800b58c <_strtod_l+0x284>) + 800b36a: a91b add r1, sp, #108 ; 0x6c + 800b36c: 4648 mov r0, r9 + 800b36e: f001 ff2c bl 800d1ca <__gethex> + 800b372: f010 0407 ands.w r4, r0, #7 + 800b376: 4606 mov r6, r0 + 800b378: d005 beq.n 800b386 <_strtod_l+0x7e> + 800b37a: 2c06 cmp r4, #6 + 800b37c: d12b bne.n 800b3d6 <_strtod_l+0xce> + 800b37e: 3501 adds r5, #1 + 800b380: 2300 movs r3, #0 + 800b382: 951b str r5, [sp, #108] ; 0x6c + 800b384: 930d str r3, [sp, #52] ; 0x34 + 800b386: 9b17 ldr r3, [sp, #92] ; 0x5c + 800b388: 2b00 cmp r3, #0 + 800b38a: f040 859a bne.w 800bec2 <_strtod_l+0xbba> + 800b38e: 9b0d ldr r3, [sp, #52] ; 0x34 + 800b390: b1e3 cbz r3, 800b3cc <_strtod_l+0xc4> + 800b392: 4652 mov r2, sl + 800b394: f10b 4300 add.w r3, fp, #2147483648 ; 0x80000000 + 800b398: ec43 2b10 vmov d0, r2, r3 + 800b39c: b021 add sp, #132 ; 0x84 + 800b39e: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 800b3a2: 2a2b cmp r2, #43 ; 0x2b + 800b3a4: d015 beq.n 800b3d2 <_strtod_l+0xca> + 800b3a6: 2a2d cmp r2, #45 ; 0x2d + 800b3a8: d004 beq.n 800b3b4 <_strtod_l+0xac> + 800b3aa: 2a20 cmp r2, #32 + 800b3ac: d1ca bne.n 800b344 <_strtod_l+0x3c> + 800b3ae: 3301 adds r3, #1 + 800b3b0: 931b str r3, [sp, #108] ; 0x6c + 800b3b2: e7bf b.n 800b334 <_strtod_l+0x2c> + 800b3b4: 2201 movs r2, #1 + 800b3b6: 920d str r2, [sp, #52] ; 0x34 + 800b3b8: 1c5a adds r2, r3, #1 + 800b3ba: 921b str r2, [sp, #108] ; 0x6c + 800b3bc: 785b ldrb r3, [r3, #1] + 800b3be: 2b00 cmp r3, #0 + 800b3c0: d1c2 bne.n 800b348 <_strtod_l+0x40> + 800b3c2: 9b17 ldr r3, [sp, #92] ; 0x5c + 800b3c4: 961b str r6, [sp, #108] ; 0x6c + 800b3c6: 2b00 cmp r3, #0 + 800b3c8: f040 8579 bne.w 800bebe <_strtod_l+0xbb6> + 800b3cc: 4652 mov r2, sl + 800b3ce: 465b mov r3, fp + 800b3d0: e7e2 b.n 800b398 <_strtod_l+0x90> + 800b3d2: 2200 movs r2, #0 + 800b3d4: e7ef b.n 800b3b6 <_strtod_l+0xae> + 800b3d6: 9a1c ldr r2, [sp, #112] ; 0x70 + 800b3d8: b13a cbz r2, 800b3ea <_strtod_l+0xe2> + 800b3da: 2135 movs r1, #53 ; 0x35 + 800b3dc: a81e add r0, sp, #120 ; 0x78 + 800b3de: f002 fe25 bl 800e02c <__copybits> + 800b3e2: 991c ldr r1, [sp, #112] ; 0x70 + 800b3e4: 4648 mov r0, r9 + 800b3e6: f002 fa92 bl 800d90e <_Bfree> + 800b3ea: 3c01 subs r4, #1 + 800b3ec: 2c04 cmp r4, #4 + 800b3ee: d806 bhi.n 800b3fe <_strtod_l+0xf6> + 800b3f0: e8df f004 tbb [pc, r4] + 800b3f4: 1714030a .word 0x1714030a + 800b3f8: 0a .byte 0x0a + 800b3f9: 00 .byte 0x00 + 800b3fa: e9dd ab1e ldrd sl, fp, [sp, #120] ; 0x78 + 800b3fe: 0730 lsls r0, r6, #28 + 800b400: d5c1 bpl.n 800b386 <_strtod_l+0x7e> + 800b402: f04b 4b00 orr.w fp, fp, #2147483648 ; 0x80000000 + 800b406: e7be b.n 800b386 <_strtod_l+0x7e> + 800b408: e9dd a31e ldrd sl, r3, [sp, #120] ; 0x78 + 800b40c: 9a1d ldr r2, [sp, #116] ; 0x74 + 800b40e: f423 1380 bic.w r3, r3, #1048576 ; 0x100000 + 800b412: f202 4233 addw r2, r2, #1075 ; 0x433 + 800b416: ea43 5b02 orr.w fp, r3, r2, lsl #20 + 800b41a: e7f0 b.n 800b3fe <_strtod_l+0xf6> + 800b41c: f8df b170 ldr.w fp, [pc, #368] ; 800b590 <_strtod_l+0x288> + 800b420: e7ed b.n 800b3fe <_strtod_l+0xf6> + 800b422: f06f 4b00 mvn.w fp, #2147483648 ; 0x80000000 + 800b426: f04f 3aff mov.w sl, #4294967295 + 800b42a: e7e8 b.n 800b3fe <_strtod_l+0xf6> + 800b42c: 9b1b ldr r3, [sp, #108] ; 0x6c + 800b42e: 1c5a adds r2, r3, #1 + 800b430: 921b str r2, [sp, #108] ; 0x6c + 800b432: 785b ldrb r3, [r3, #1] + 800b434: 2b30 cmp r3, #48 ; 0x30 + 800b436: d0f9 beq.n 800b42c <_strtod_l+0x124> + 800b438: 2b00 cmp r3, #0 + 800b43a: d0a4 beq.n 800b386 <_strtod_l+0x7e> + 800b43c: 2301 movs r3, #1 + 800b43e: 2500 movs r5, #0 + 800b440: 9306 str r3, [sp, #24] + 800b442: 9b1b ldr r3, [sp, #108] ; 0x6c + 800b444: 9308 str r3, [sp, #32] + 800b446: 9507 str r5, [sp, #28] + 800b448: 9505 str r5, [sp, #20] + 800b44a: 220a movs r2, #10 + 800b44c: 981b ldr r0, [sp, #108] ; 0x6c + 800b44e: 7807 ldrb r7, [r0, #0] + 800b450: f1a7 0330 sub.w r3, r7, #48 ; 0x30 + 800b454: b2d9 uxtb r1, r3 + 800b456: 2909 cmp r1, #9 + 800b458: d929 bls.n 800b4ae <_strtod_l+0x1a6> + 800b45a: 4622 mov r2, r4 + 800b45c: f8d8 1000 ldr.w r1, [r8] + 800b460: f003 f903 bl 800e66a + 800b464: 2800 cmp r0, #0 + 800b466: d031 beq.n 800b4cc <_strtod_l+0x1c4> + 800b468: 2000 movs r0, #0 + 800b46a: 9c05 ldr r4, [sp, #20] + 800b46c: 9004 str r0, [sp, #16] + 800b46e: 463b mov r3, r7 + 800b470: 4602 mov r2, r0 + 800b472: 2b65 cmp r3, #101 ; 0x65 + 800b474: d001 beq.n 800b47a <_strtod_l+0x172> + 800b476: 2b45 cmp r3, #69 ; 0x45 + 800b478: d114 bne.n 800b4a4 <_strtod_l+0x19c> + 800b47a: b924 cbnz r4, 800b486 <_strtod_l+0x17e> + 800b47c: b910 cbnz r0, 800b484 <_strtod_l+0x17c> + 800b47e: 9b06 ldr r3, [sp, #24] + 800b480: 2b00 cmp r3, #0 + 800b482: d09e beq.n 800b3c2 <_strtod_l+0xba> + 800b484: 2400 movs r4, #0 + 800b486: 9e1b ldr r6, [sp, #108] ; 0x6c + 800b488: 1c73 adds r3, r6, #1 + 800b48a: 931b str r3, [sp, #108] ; 0x6c + 800b48c: 7873 ldrb r3, [r6, #1] + 800b48e: 2b2b cmp r3, #43 ; 0x2b + 800b490: d078 beq.n 800b584 <_strtod_l+0x27c> + 800b492: 2b2d cmp r3, #45 ; 0x2d + 800b494: d070 beq.n 800b578 <_strtod_l+0x270> + 800b496: f04f 0c00 mov.w ip, #0 + 800b49a: f1a3 0730 sub.w r7, r3, #48 ; 0x30 + 800b49e: 2f09 cmp r7, #9 + 800b4a0: d97c bls.n 800b59c <_strtod_l+0x294> + 800b4a2: 961b str r6, [sp, #108] ; 0x6c + 800b4a4: f04f 0e00 mov.w lr, #0 + 800b4a8: e09a b.n 800b5e0 <_strtod_l+0x2d8> + 800b4aa: 2300 movs r3, #0 + 800b4ac: e7c7 b.n 800b43e <_strtod_l+0x136> + 800b4ae: 9905 ldr r1, [sp, #20] + 800b4b0: 2908 cmp r1, #8 + 800b4b2: bfdd ittte le + 800b4b4: 9907 ldrle r1, [sp, #28] + 800b4b6: fb02 3301 mlale r3, r2, r1, r3 + 800b4ba: 9307 strle r3, [sp, #28] + 800b4bc: fb02 3505 mlagt r5, r2, r5, r3 + 800b4c0: 9b05 ldr r3, [sp, #20] + 800b4c2: 3001 adds r0, #1 + 800b4c4: 3301 adds r3, #1 + 800b4c6: 9305 str r3, [sp, #20] + 800b4c8: 901b str r0, [sp, #108] ; 0x6c + 800b4ca: e7bf b.n 800b44c <_strtod_l+0x144> + 800b4cc: 9b1b ldr r3, [sp, #108] ; 0x6c + 800b4ce: 191a adds r2, r3, r4 + 800b4d0: 921b str r2, [sp, #108] ; 0x6c + 800b4d2: 9a05 ldr r2, [sp, #20] + 800b4d4: 5d1b ldrb r3, [r3, r4] + 800b4d6: 2a00 cmp r2, #0 + 800b4d8: d037 beq.n 800b54a <_strtod_l+0x242> + 800b4da: 9c05 ldr r4, [sp, #20] + 800b4dc: 4602 mov r2, r0 + 800b4de: f1a3 0130 sub.w r1, r3, #48 ; 0x30 + 800b4e2: 2909 cmp r1, #9 + 800b4e4: d913 bls.n 800b50e <_strtod_l+0x206> + 800b4e6: 2101 movs r1, #1 + 800b4e8: 9104 str r1, [sp, #16] + 800b4ea: e7c2 b.n 800b472 <_strtod_l+0x16a> + 800b4ec: 9b1b ldr r3, [sp, #108] ; 0x6c + 800b4ee: 1c5a adds r2, r3, #1 + 800b4f0: 921b str r2, [sp, #108] ; 0x6c + 800b4f2: 785b ldrb r3, [r3, #1] + 800b4f4: 3001 adds r0, #1 + 800b4f6: 2b30 cmp r3, #48 ; 0x30 + 800b4f8: d0f8 beq.n 800b4ec <_strtod_l+0x1e4> + 800b4fa: f1a3 0231 sub.w r2, r3, #49 ; 0x31 + 800b4fe: 2a08 cmp r2, #8 + 800b500: f200 84e4 bhi.w 800becc <_strtod_l+0xbc4> + 800b504: 9a1b ldr r2, [sp, #108] ; 0x6c + 800b506: 9208 str r2, [sp, #32] + 800b508: 4602 mov r2, r0 + 800b50a: 2000 movs r0, #0 + 800b50c: 4604 mov r4, r0 + 800b50e: f1b3 0e30 subs.w lr, r3, #48 ; 0x30 + 800b512: f100 0101 add.w r1, r0, #1 + 800b516: d012 beq.n 800b53e <_strtod_l+0x236> + 800b518: 440a add r2, r1 + 800b51a: eb00 0c04 add.w ip, r0, r4 + 800b51e: 4621 mov r1, r4 + 800b520: 270a movs r7, #10 + 800b522: 458c cmp ip, r1 + 800b524: d113 bne.n 800b54e <_strtod_l+0x246> + 800b526: 1821 adds r1, r4, r0 + 800b528: 2908 cmp r1, #8 + 800b52a: f104 0401 add.w r4, r4, #1 + 800b52e: 4404 add r4, r0 + 800b530: dc19 bgt.n 800b566 <_strtod_l+0x25e> + 800b532: 9b07 ldr r3, [sp, #28] + 800b534: 210a movs r1, #10 + 800b536: fb01 e303 mla r3, r1, r3, lr + 800b53a: 9307 str r3, [sp, #28] + 800b53c: 2100 movs r1, #0 + 800b53e: 9b1b ldr r3, [sp, #108] ; 0x6c + 800b540: 1c58 adds r0, r3, #1 + 800b542: 901b str r0, [sp, #108] ; 0x6c + 800b544: 785b ldrb r3, [r3, #1] + 800b546: 4608 mov r0, r1 + 800b548: e7c9 b.n 800b4de <_strtod_l+0x1d6> + 800b54a: 9805 ldr r0, [sp, #20] + 800b54c: e7d3 b.n 800b4f6 <_strtod_l+0x1ee> + 800b54e: 2908 cmp r1, #8 + 800b550: f101 0101 add.w r1, r1, #1 + 800b554: dc03 bgt.n 800b55e <_strtod_l+0x256> + 800b556: 9b07 ldr r3, [sp, #28] + 800b558: 437b muls r3, r7 + 800b55a: 9307 str r3, [sp, #28] + 800b55c: e7e1 b.n 800b522 <_strtod_l+0x21a> + 800b55e: 2910 cmp r1, #16 + 800b560: bfd8 it le + 800b562: 437d mulle r5, r7 + 800b564: e7dd b.n 800b522 <_strtod_l+0x21a> + 800b566: 2c10 cmp r4, #16 + 800b568: bfdc itt le + 800b56a: 210a movle r1, #10 + 800b56c: fb01 e505 mlale r5, r1, r5, lr + 800b570: e7e4 b.n 800b53c <_strtod_l+0x234> + 800b572: 2301 movs r3, #1 + 800b574: 9304 str r3, [sp, #16] + 800b576: e781 b.n 800b47c <_strtod_l+0x174> + 800b578: f04f 0c01 mov.w ip, #1 + 800b57c: 1cb3 adds r3, r6, #2 + 800b57e: 931b str r3, [sp, #108] ; 0x6c + 800b580: 78b3 ldrb r3, [r6, #2] + 800b582: e78a b.n 800b49a <_strtod_l+0x192> + 800b584: f04f 0c00 mov.w ip, #0 + 800b588: e7f8 b.n 800b57c <_strtod_l+0x274> + 800b58a: bf00 nop + 800b58c: 0800e974 .word 0x0800e974 + 800b590: 7ff00000 .word 0x7ff00000 + 800b594: 9b1b ldr r3, [sp, #108] ; 0x6c + 800b596: 1c5f adds r7, r3, #1 + 800b598: 971b str r7, [sp, #108] ; 0x6c + 800b59a: 785b ldrb r3, [r3, #1] + 800b59c: 2b30 cmp r3, #48 ; 0x30 + 800b59e: d0f9 beq.n 800b594 <_strtod_l+0x28c> + 800b5a0: f1a3 0731 sub.w r7, r3, #49 ; 0x31 + 800b5a4: 2f08 cmp r7, #8 + 800b5a6: f63f af7d bhi.w 800b4a4 <_strtod_l+0x19c> + 800b5aa: f1a3 0e30 sub.w lr, r3, #48 ; 0x30 + 800b5ae: 9b1b ldr r3, [sp, #108] ; 0x6c + 800b5b0: 930a str r3, [sp, #40] ; 0x28 + 800b5b2: 9b1b ldr r3, [sp, #108] ; 0x6c + 800b5b4: 1c5f adds r7, r3, #1 + 800b5b6: 971b str r7, [sp, #108] ; 0x6c + 800b5b8: 785b ldrb r3, [r3, #1] + 800b5ba: f1a3 0830 sub.w r8, r3, #48 ; 0x30 + 800b5be: f1b8 0f09 cmp.w r8, #9 + 800b5c2: d937 bls.n 800b634 <_strtod_l+0x32c> + 800b5c4: 990a ldr r1, [sp, #40] ; 0x28 + 800b5c6: 1a7f subs r7, r7, r1 + 800b5c8: 2f08 cmp r7, #8 + 800b5ca: f644 671f movw r7, #19999 ; 0x4e1f + 800b5ce: dc37 bgt.n 800b640 <_strtod_l+0x338> + 800b5d0: 45be cmp lr, r7 + 800b5d2: bfa8 it ge + 800b5d4: 46be movge lr, r7 + 800b5d6: f1bc 0f00 cmp.w ip, #0 + 800b5da: d001 beq.n 800b5e0 <_strtod_l+0x2d8> + 800b5dc: f1ce 0e00 rsb lr, lr, #0 + 800b5e0: 2c00 cmp r4, #0 + 800b5e2: d151 bne.n 800b688 <_strtod_l+0x380> + 800b5e4: 2800 cmp r0, #0 + 800b5e6: f47f aece bne.w 800b386 <_strtod_l+0x7e> + 800b5ea: 9a06 ldr r2, [sp, #24] + 800b5ec: 2a00 cmp r2, #0 + 800b5ee: f47f aeca bne.w 800b386 <_strtod_l+0x7e> + 800b5f2: 9a04 ldr r2, [sp, #16] + 800b5f4: 2a00 cmp r2, #0 + 800b5f6: f47f aee4 bne.w 800b3c2 <_strtod_l+0xba> + 800b5fa: 2b4e cmp r3, #78 ; 0x4e + 800b5fc: d027 beq.n 800b64e <_strtod_l+0x346> + 800b5fe: dc21 bgt.n 800b644 <_strtod_l+0x33c> + 800b600: 2b49 cmp r3, #73 ; 0x49 + 800b602: f47f aede bne.w 800b3c2 <_strtod_l+0xba> + 800b606: 49a0 ldr r1, [pc, #640] ; (800b888 <_strtod_l+0x580>) + 800b608: a81b add r0, sp, #108 ; 0x6c + 800b60a: f002 f811 bl 800d630 <__match> + 800b60e: 2800 cmp r0, #0 + 800b610: f43f aed7 beq.w 800b3c2 <_strtod_l+0xba> + 800b614: 9b1b ldr r3, [sp, #108] ; 0x6c + 800b616: 499d ldr r1, [pc, #628] ; (800b88c <_strtod_l+0x584>) + 800b618: 3b01 subs r3, #1 + 800b61a: a81b add r0, sp, #108 ; 0x6c + 800b61c: 931b str r3, [sp, #108] ; 0x6c + 800b61e: f002 f807 bl 800d630 <__match> + 800b622: b910 cbnz r0, 800b62a <_strtod_l+0x322> + 800b624: 9b1b ldr r3, [sp, #108] ; 0x6c + 800b626: 3301 adds r3, #1 + 800b628: 931b str r3, [sp, #108] ; 0x6c + 800b62a: f8df b274 ldr.w fp, [pc, #628] ; 800b8a0 <_strtod_l+0x598> + 800b62e: f04f 0a00 mov.w sl, #0 + 800b632: e6a8 b.n 800b386 <_strtod_l+0x7e> + 800b634: 210a movs r1, #10 + 800b636: fb01 3e0e mla lr, r1, lr, r3 + 800b63a: f1ae 0e30 sub.w lr, lr, #48 ; 0x30 + 800b63e: e7b8 b.n 800b5b2 <_strtod_l+0x2aa> + 800b640: 46be mov lr, r7 + 800b642: e7c8 b.n 800b5d6 <_strtod_l+0x2ce> + 800b644: 2b69 cmp r3, #105 ; 0x69 + 800b646: d0de beq.n 800b606 <_strtod_l+0x2fe> + 800b648: 2b6e cmp r3, #110 ; 0x6e + 800b64a: f47f aeba bne.w 800b3c2 <_strtod_l+0xba> + 800b64e: 4990 ldr r1, [pc, #576] ; (800b890 <_strtod_l+0x588>) + 800b650: a81b add r0, sp, #108 ; 0x6c + 800b652: f001 ffed bl 800d630 <__match> + 800b656: 2800 cmp r0, #0 + 800b658: f43f aeb3 beq.w 800b3c2 <_strtod_l+0xba> + 800b65c: 9b1b ldr r3, [sp, #108] ; 0x6c + 800b65e: 781b ldrb r3, [r3, #0] + 800b660: 2b28 cmp r3, #40 ; 0x28 + 800b662: d10e bne.n 800b682 <_strtod_l+0x37a> + 800b664: aa1e add r2, sp, #120 ; 0x78 + 800b666: 498b ldr r1, [pc, #556] ; (800b894 <_strtod_l+0x58c>) + 800b668: a81b add r0, sp, #108 ; 0x6c + 800b66a: f001 fff5 bl 800d658 <__hexnan> + 800b66e: 2805 cmp r0, #5 + 800b670: d107 bne.n 800b682 <_strtod_l+0x37a> + 800b672: 9b1f ldr r3, [sp, #124] ; 0x7c + 800b674: f8dd a078 ldr.w sl, [sp, #120] ; 0x78 + 800b678: f043 4bff orr.w fp, r3, #2139095040 ; 0x7f800000 + 800b67c: f44b 0be0 orr.w fp, fp, #7340032 ; 0x700000 + 800b680: e681 b.n 800b386 <_strtod_l+0x7e> + 800b682: f8df b224 ldr.w fp, [pc, #548] ; 800b8a8 <_strtod_l+0x5a0> + 800b686: e7d2 b.n 800b62e <_strtod_l+0x326> + 800b688: ebae 0302 sub.w r3, lr, r2 + 800b68c: 9306 str r3, [sp, #24] + 800b68e: 9b05 ldr r3, [sp, #20] + 800b690: 9807 ldr r0, [sp, #28] + 800b692: 2b00 cmp r3, #0 + 800b694: bf08 it eq + 800b696: 4623 moveq r3, r4 + 800b698: 2c10 cmp r4, #16 + 800b69a: 9305 str r3, [sp, #20] + 800b69c: 46a0 mov r8, r4 + 800b69e: bfa8 it ge + 800b6a0: f04f 0810 movge.w r8, #16 + 800b6a4: f7f4 ff36 bl 8000514 <__aeabi_ui2d> + 800b6a8: 2c09 cmp r4, #9 + 800b6aa: 4682 mov sl, r0 + 800b6ac: 468b mov fp, r1 + 800b6ae: dc13 bgt.n 800b6d8 <_strtod_l+0x3d0> + 800b6b0: 9b06 ldr r3, [sp, #24] + 800b6b2: 2b00 cmp r3, #0 + 800b6b4: f43f ae67 beq.w 800b386 <_strtod_l+0x7e> + 800b6b8: 9b06 ldr r3, [sp, #24] + 800b6ba: dd7a ble.n 800b7b2 <_strtod_l+0x4aa> + 800b6bc: 2b16 cmp r3, #22 + 800b6be: dc61 bgt.n 800b784 <_strtod_l+0x47c> + 800b6c0: 4a75 ldr r2, [pc, #468] ; (800b898 <_strtod_l+0x590>) + 800b6c2: eb02 0ec3 add.w lr, r2, r3, lsl #3 + 800b6c6: e9de 0100 ldrd r0, r1, [lr] + 800b6ca: 4652 mov r2, sl + 800b6cc: 465b mov r3, fp + 800b6ce: f7f4 ff9b bl 8000608 <__aeabi_dmul> + 800b6d2: 4682 mov sl, r0 + 800b6d4: 468b mov fp, r1 + 800b6d6: e656 b.n 800b386 <_strtod_l+0x7e> + 800b6d8: 4b6f ldr r3, [pc, #444] ; (800b898 <_strtod_l+0x590>) + 800b6da: eb03 03c8 add.w r3, r3, r8, lsl #3 + 800b6de: e953 2312 ldrd r2, r3, [r3, #-72] ; 0x48 + 800b6e2: f7f4 ff91 bl 8000608 <__aeabi_dmul> + 800b6e6: 4606 mov r6, r0 + 800b6e8: 4628 mov r0, r5 + 800b6ea: 460f mov r7, r1 + 800b6ec: f7f4 ff12 bl 8000514 <__aeabi_ui2d> + 800b6f0: 4602 mov r2, r0 + 800b6f2: 460b mov r3, r1 + 800b6f4: 4630 mov r0, r6 + 800b6f6: 4639 mov r1, r7 + 800b6f8: f7f4 fdd0 bl 800029c <__adddf3> + 800b6fc: 2c0f cmp r4, #15 + 800b6fe: 4682 mov sl, r0 + 800b700: 468b mov fp, r1 + 800b702: ddd5 ble.n 800b6b0 <_strtod_l+0x3a8> + 800b704: 9b06 ldr r3, [sp, #24] + 800b706: eba4 0808 sub.w r8, r4, r8 + 800b70a: 4498 add r8, r3 + 800b70c: f1b8 0f00 cmp.w r8, #0 + 800b710: f340 8096 ble.w 800b840 <_strtod_l+0x538> + 800b714: f018 030f ands.w r3, r8, #15 + 800b718: d00a beq.n 800b730 <_strtod_l+0x428> + 800b71a: 495f ldr r1, [pc, #380] ; (800b898 <_strtod_l+0x590>) + 800b71c: eb01 01c3 add.w r1, r1, r3, lsl #3 + 800b720: 4652 mov r2, sl + 800b722: 465b mov r3, fp + 800b724: e9d1 0100 ldrd r0, r1, [r1] + 800b728: f7f4 ff6e bl 8000608 <__aeabi_dmul> + 800b72c: 4682 mov sl, r0 + 800b72e: 468b mov fp, r1 + 800b730: f038 080f bics.w r8, r8, #15 + 800b734: d073 beq.n 800b81e <_strtod_l+0x516> + 800b736: f5b8 7f9a cmp.w r8, #308 ; 0x134 + 800b73a: dd47 ble.n 800b7cc <_strtod_l+0x4c4> + 800b73c: 2400 movs r4, #0 + 800b73e: 46a0 mov r8, r4 + 800b740: 9407 str r4, [sp, #28] + 800b742: 9405 str r4, [sp, #20] + 800b744: 2322 movs r3, #34 ; 0x22 + 800b746: f8df b158 ldr.w fp, [pc, #344] ; 800b8a0 <_strtod_l+0x598> + 800b74a: f8c9 3000 str.w r3, [r9] + 800b74e: f04f 0a00 mov.w sl, #0 + 800b752: 9b07 ldr r3, [sp, #28] + 800b754: 2b00 cmp r3, #0 + 800b756: f43f ae16 beq.w 800b386 <_strtod_l+0x7e> + 800b75a: 991c ldr r1, [sp, #112] ; 0x70 + 800b75c: 4648 mov r0, r9 + 800b75e: f002 f8d6 bl 800d90e <_Bfree> + 800b762: 9905 ldr r1, [sp, #20] + 800b764: 4648 mov r0, r9 + 800b766: f002 f8d2 bl 800d90e <_Bfree> + 800b76a: 4641 mov r1, r8 + 800b76c: 4648 mov r0, r9 + 800b76e: f002 f8ce bl 800d90e <_Bfree> + 800b772: 9907 ldr r1, [sp, #28] + 800b774: 4648 mov r0, r9 + 800b776: f002 f8ca bl 800d90e <_Bfree> + 800b77a: 4621 mov r1, r4 + 800b77c: 4648 mov r0, r9 + 800b77e: f002 f8c6 bl 800d90e <_Bfree> + 800b782: e600 b.n 800b386 <_strtod_l+0x7e> + 800b784: 9a06 ldr r2, [sp, #24] + 800b786: f1c4 0325 rsb r3, r4, #37 ; 0x25 + 800b78a: 4293 cmp r3, r2 + 800b78c: dbba blt.n 800b704 <_strtod_l+0x3fc> + 800b78e: 4d42 ldr r5, [pc, #264] ; (800b898 <_strtod_l+0x590>) + 800b790: f1c4 040f rsb r4, r4, #15 + 800b794: eb05 01c4 add.w r1, r5, r4, lsl #3 + 800b798: 4652 mov r2, sl + 800b79a: 465b mov r3, fp + 800b79c: e9d1 0100 ldrd r0, r1, [r1] + 800b7a0: f7f4 ff32 bl 8000608 <__aeabi_dmul> + 800b7a4: 9b06 ldr r3, [sp, #24] + 800b7a6: 1b1c subs r4, r3, r4 + 800b7a8: eb05 05c4 add.w r5, r5, r4, lsl #3 + 800b7ac: e9d5 2300 ldrd r2, r3, [r5] + 800b7b0: e78d b.n 800b6ce <_strtod_l+0x3c6> + 800b7b2: f113 0f16 cmn.w r3, #22 + 800b7b6: dba5 blt.n 800b704 <_strtod_l+0x3fc> + 800b7b8: 4a37 ldr r2, [pc, #220] ; (800b898 <_strtod_l+0x590>) + 800b7ba: eba2 02c3 sub.w r2, r2, r3, lsl #3 + 800b7be: e9d2 2300 ldrd r2, r3, [r2] + 800b7c2: 4650 mov r0, sl + 800b7c4: 4659 mov r1, fp + 800b7c6: f7f5 f849 bl 800085c <__aeabi_ddiv> + 800b7ca: e782 b.n 800b6d2 <_strtod_l+0x3ca> + 800b7cc: 2300 movs r3, #0 + 800b7ce: 4e33 ldr r6, [pc, #204] ; (800b89c <_strtod_l+0x594>) + 800b7d0: ea4f 1828 mov.w r8, r8, asr #4 + 800b7d4: 4650 mov r0, sl + 800b7d6: 4659 mov r1, fp + 800b7d8: 461d mov r5, r3 + 800b7da: f1b8 0f01 cmp.w r8, #1 + 800b7de: dc21 bgt.n 800b824 <_strtod_l+0x51c> + 800b7e0: b10b cbz r3, 800b7e6 <_strtod_l+0x4de> + 800b7e2: 4682 mov sl, r0 + 800b7e4: 468b mov fp, r1 + 800b7e6: 4b2d ldr r3, [pc, #180] ; (800b89c <_strtod_l+0x594>) + 800b7e8: f1ab 7b54 sub.w fp, fp, #55574528 ; 0x3500000 + 800b7ec: eb03 05c5 add.w r5, r3, r5, lsl #3 + 800b7f0: 4652 mov r2, sl + 800b7f2: 465b mov r3, fp + 800b7f4: e9d5 0100 ldrd r0, r1, [r5] + 800b7f8: f7f4 ff06 bl 8000608 <__aeabi_dmul> + 800b7fc: 4b28 ldr r3, [pc, #160] ; (800b8a0 <_strtod_l+0x598>) + 800b7fe: 460a mov r2, r1 + 800b800: 400b ands r3, r1 + 800b802: 4928 ldr r1, [pc, #160] ; (800b8a4 <_strtod_l+0x59c>) + 800b804: 428b cmp r3, r1 + 800b806: 4682 mov sl, r0 + 800b808: d898 bhi.n 800b73c <_strtod_l+0x434> + 800b80a: f5a1 1180 sub.w r1, r1, #1048576 ; 0x100000 + 800b80e: 428b cmp r3, r1 + 800b810: bf86 itte hi + 800b812: f8df b098 ldrhi.w fp, [pc, #152] ; 800b8ac <_strtod_l+0x5a4> + 800b816: f04f 3aff movhi.w sl, #4294967295 + 800b81a: f102 7b54 addls.w fp, r2, #55574528 ; 0x3500000 + 800b81e: 2300 movs r3, #0 + 800b820: 9304 str r3, [sp, #16] + 800b822: e077 b.n 800b914 <_strtod_l+0x60c> + 800b824: f018 0f01 tst.w r8, #1 + 800b828: d006 beq.n 800b838 <_strtod_l+0x530> + 800b82a: eb06 03c5 add.w r3, r6, r5, lsl #3 + 800b82e: e9d3 2300 ldrd r2, r3, [r3] + 800b832: f7f4 fee9 bl 8000608 <__aeabi_dmul> + 800b836: 2301 movs r3, #1 + 800b838: 3501 adds r5, #1 + 800b83a: ea4f 0868 mov.w r8, r8, asr #1 + 800b83e: e7cc b.n 800b7da <_strtod_l+0x4d2> + 800b840: d0ed beq.n 800b81e <_strtod_l+0x516> + 800b842: f1c8 0800 rsb r8, r8, #0 + 800b846: f018 020f ands.w r2, r8, #15 + 800b84a: d00a beq.n 800b862 <_strtod_l+0x55a> + 800b84c: 4b12 ldr r3, [pc, #72] ; (800b898 <_strtod_l+0x590>) + 800b84e: eb03 03c2 add.w r3, r3, r2, lsl #3 + 800b852: 4650 mov r0, sl + 800b854: 4659 mov r1, fp + 800b856: e9d3 2300 ldrd r2, r3, [r3] + 800b85a: f7f4 ffff bl 800085c <__aeabi_ddiv> + 800b85e: 4682 mov sl, r0 + 800b860: 468b mov fp, r1 + 800b862: ea5f 1828 movs.w r8, r8, asr #4 + 800b866: d0da beq.n 800b81e <_strtod_l+0x516> + 800b868: f1b8 0f1f cmp.w r8, #31 + 800b86c: dd20 ble.n 800b8b0 <_strtod_l+0x5a8> + 800b86e: 2400 movs r4, #0 + 800b870: 46a0 mov r8, r4 + 800b872: 9407 str r4, [sp, #28] + 800b874: 9405 str r4, [sp, #20] + 800b876: 2322 movs r3, #34 ; 0x22 + 800b878: f04f 0a00 mov.w sl, #0 + 800b87c: f04f 0b00 mov.w fp, #0 + 800b880: f8c9 3000 str.w r3, [r9] + 800b884: e765 b.n 800b752 <_strtod_l+0x44a> + 800b886: bf00 nop + 800b888: 0800e93d .word 0x0800e93d + 800b88c: 0800e9cb .word 0x0800e9cb + 800b890: 0800e945 .word 0x0800e945 + 800b894: 0800e988 .word 0x0800e988 + 800b898: 0800ea70 .word 0x0800ea70 + 800b89c: 0800ea48 .word 0x0800ea48 + 800b8a0: 7ff00000 .word 0x7ff00000 + 800b8a4: 7ca00000 .word 0x7ca00000 + 800b8a8: fff80000 .word 0xfff80000 + 800b8ac: 7fefffff .word 0x7fefffff + 800b8b0: f018 0310 ands.w r3, r8, #16 + 800b8b4: bf18 it ne + 800b8b6: 236a movne r3, #106 ; 0x6a + 800b8b8: 4da0 ldr r5, [pc, #640] ; (800bb3c <_strtod_l+0x834>) + 800b8ba: 9304 str r3, [sp, #16] + 800b8bc: 4650 mov r0, sl + 800b8be: 4659 mov r1, fp + 800b8c0: 2300 movs r3, #0 + 800b8c2: f1b8 0f00 cmp.w r8, #0 + 800b8c6: f300 810a bgt.w 800bade <_strtod_l+0x7d6> + 800b8ca: b10b cbz r3, 800b8d0 <_strtod_l+0x5c8> + 800b8cc: 4682 mov sl, r0 + 800b8ce: 468b mov fp, r1 + 800b8d0: 9b04 ldr r3, [sp, #16] + 800b8d2: b1bb cbz r3, 800b904 <_strtod_l+0x5fc> + 800b8d4: f3cb 530a ubfx r3, fp, #20, #11 + 800b8d8: f1c3 036b rsb r3, r3, #107 ; 0x6b + 800b8dc: 2b00 cmp r3, #0 + 800b8de: 4659 mov r1, fp + 800b8e0: dd10 ble.n 800b904 <_strtod_l+0x5fc> + 800b8e2: 2b1f cmp r3, #31 + 800b8e4: f340 8107 ble.w 800baf6 <_strtod_l+0x7ee> + 800b8e8: 2b34 cmp r3, #52 ; 0x34 + 800b8ea: bfde ittt le + 800b8ec: 3b20 suble r3, #32 + 800b8ee: f04f 32ff movle.w r2, #4294967295 + 800b8f2: fa02 f303 lslle.w r3, r2, r3 + 800b8f6: f04f 0a00 mov.w sl, #0 + 800b8fa: bfcc ite gt + 800b8fc: f04f 7b5c movgt.w fp, #57671680 ; 0x3700000 + 800b900: ea03 0b01 andle.w fp, r3, r1 + 800b904: 2200 movs r2, #0 + 800b906: 2300 movs r3, #0 + 800b908: 4650 mov r0, sl + 800b90a: 4659 mov r1, fp + 800b90c: f7f5 f8e4 bl 8000ad8 <__aeabi_dcmpeq> + 800b910: 2800 cmp r0, #0 + 800b912: d1ac bne.n 800b86e <_strtod_l+0x566> + 800b914: 9b07 ldr r3, [sp, #28] + 800b916: 9300 str r3, [sp, #0] + 800b918: 9a05 ldr r2, [sp, #20] + 800b91a: 9908 ldr r1, [sp, #32] + 800b91c: 4623 mov r3, r4 + 800b91e: 4648 mov r0, r9 + 800b920: f002 f847 bl 800d9b2 <__s2b> + 800b924: 9007 str r0, [sp, #28] + 800b926: 2800 cmp r0, #0 + 800b928: f43f af08 beq.w 800b73c <_strtod_l+0x434> + 800b92c: 9a06 ldr r2, [sp, #24] + 800b92e: 9b06 ldr r3, [sp, #24] + 800b930: 2a00 cmp r2, #0 + 800b932: f1c3 0300 rsb r3, r3, #0 + 800b936: bfa8 it ge + 800b938: 2300 movge r3, #0 + 800b93a: 930e str r3, [sp, #56] ; 0x38 + 800b93c: 2400 movs r4, #0 + 800b93e: ea22 73e2 bic.w r3, r2, r2, asr #31 + 800b942: 9316 str r3, [sp, #88] ; 0x58 + 800b944: 46a0 mov r8, r4 + 800b946: 9b07 ldr r3, [sp, #28] + 800b948: 4648 mov r0, r9 + 800b94a: 6859 ldr r1, [r3, #4] + 800b94c: f001 ffab bl 800d8a6 <_Balloc> + 800b950: 9005 str r0, [sp, #20] + 800b952: 2800 cmp r0, #0 + 800b954: f43f aef6 beq.w 800b744 <_strtod_l+0x43c> + 800b958: 9b07 ldr r3, [sp, #28] + 800b95a: 691a ldr r2, [r3, #16] + 800b95c: 3202 adds r2, #2 + 800b95e: f103 010c add.w r1, r3, #12 + 800b962: 0092 lsls r2, r2, #2 + 800b964: 300c adds r0, #12 + 800b966: f001 ff91 bl 800d88c + 800b96a: aa1e add r2, sp, #120 ; 0x78 + 800b96c: a91d add r1, sp, #116 ; 0x74 + 800b96e: ec4b ab10 vmov d0, sl, fp + 800b972: 4648 mov r0, r9 + 800b974: e9cd ab08 strd sl, fp, [sp, #32] + 800b978: f002 fad6 bl 800df28 <__d2b> + 800b97c: 901c str r0, [sp, #112] ; 0x70 + 800b97e: 2800 cmp r0, #0 + 800b980: f43f aee0 beq.w 800b744 <_strtod_l+0x43c> + 800b984: 2101 movs r1, #1 + 800b986: 4648 mov r0, r9 + 800b988: f002 f89f bl 800daca <__i2b> + 800b98c: 4680 mov r8, r0 + 800b98e: 2800 cmp r0, #0 + 800b990: f43f aed8 beq.w 800b744 <_strtod_l+0x43c> + 800b994: 9e1d ldr r6, [sp, #116] ; 0x74 + 800b996: 9a1e ldr r2, [sp, #120] ; 0x78 + 800b998: 2e00 cmp r6, #0 + 800b99a: bfab itete ge + 800b99c: 9b0e ldrge r3, [sp, #56] ; 0x38 + 800b99e: 9b16 ldrlt r3, [sp, #88] ; 0x58 + 800b9a0: 9d16 ldrge r5, [sp, #88] ; 0x58 + 800b9a2: 9f0e ldrlt r7, [sp, #56] ; 0x38 + 800b9a4: bfac ite ge + 800b9a6: 18f7 addge r7, r6, r3 + 800b9a8: 1b9d sublt r5, r3, r6 + 800b9aa: 9b04 ldr r3, [sp, #16] + 800b9ac: 1af6 subs r6, r6, r3 + 800b9ae: 4416 add r6, r2 + 800b9b0: 4b63 ldr r3, [pc, #396] ; (800bb40 <_strtod_l+0x838>) + 800b9b2: 3e01 subs r6, #1 + 800b9b4: 429e cmp r6, r3 + 800b9b6: f1c2 0236 rsb r2, r2, #54 ; 0x36 + 800b9ba: f280 80af bge.w 800bb1c <_strtod_l+0x814> + 800b9be: 1b9b subs r3, r3, r6 + 800b9c0: 2b1f cmp r3, #31 + 800b9c2: eba2 0203 sub.w r2, r2, r3 + 800b9c6: f04f 0101 mov.w r1, #1 + 800b9ca: f300 809b bgt.w 800bb04 <_strtod_l+0x7fc> + 800b9ce: fa01 f303 lsl.w r3, r1, r3 + 800b9d2: 930f str r3, [sp, #60] ; 0x3c + 800b9d4: 2300 movs r3, #0 + 800b9d6: 930a str r3, [sp, #40] ; 0x28 + 800b9d8: 18be adds r6, r7, r2 + 800b9da: 9b04 ldr r3, [sp, #16] + 800b9dc: 42b7 cmp r7, r6 + 800b9de: 4415 add r5, r2 + 800b9e0: 441d add r5, r3 + 800b9e2: 463b mov r3, r7 + 800b9e4: bfa8 it ge + 800b9e6: 4633 movge r3, r6 + 800b9e8: 42ab cmp r3, r5 + 800b9ea: bfa8 it ge + 800b9ec: 462b movge r3, r5 + 800b9ee: 2b00 cmp r3, #0 + 800b9f0: bfc2 ittt gt + 800b9f2: 1af6 subgt r6, r6, r3 + 800b9f4: 1aed subgt r5, r5, r3 + 800b9f6: 1aff subgt r7, r7, r3 + 800b9f8: 9b0e ldr r3, [sp, #56] ; 0x38 + 800b9fa: b1bb cbz r3, 800ba2c <_strtod_l+0x724> + 800b9fc: 4641 mov r1, r8 + 800b9fe: 461a mov r2, r3 + 800ba00: 4648 mov r0, r9 + 800ba02: f002 f901 bl 800dc08 <__pow5mult> + 800ba06: 4680 mov r8, r0 + 800ba08: 2800 cmp r0, #0 + 800ba0a: f43f ae9b beq.w 800b744 <_strtod_l+0x43c> + 800ba0e: 4601 mov r1, r0 + 800ba10: 9a1c ldr r2, [sp, #112] ; 0x70 + 800ba12: 4648 mov r0, r9 + 800ba14: f002 f862 bl 800dadc <__multiply> + 800ba18: 900c str r0, [sp, #48] ; 0x30 + 800ba1a: 2800 cmp r0, #0 + 800ba1c: f43f ae92 beq.w 800b744 <_strtod_l+0x43c> + 800ba20: 991c ldr r1, [sp, #112] ; 0x70 + 800ba22: 4648 mov r0, r9 + 800ba24: f001 ff73 bl 800d90e <_Bfree> + 800ba28: 9b0c ldr r3, [sp, #48] ; 0x30 + 800ba2a: 931c str r3, [sp, #112] ; 0x70 + 800ba2c: 2e00 cmp r6, #0 + 800ba2e: dc7a bgt.n 800bb26 <_strtod_l+0x81e> + 800ba30: 9b06 ldr r3, [sp, #24] + 800ba32: 2b00 cmp r3, #0 + 800ba34: dd08 ble.n 800ba48 <_strtod_l+0x740> + 800ba36: 9a16 ldr r2, [sp, #88] ; 0x58 + 800ba38: 9905 ldr r1, [sp, #20] + 800ba3a: 4648 mov r0, r9 + 800ba3c: f002 f8e4 bl 800dc08 <__pow5mult> + 800ba40: 9005 str r0, [sp, #20] + 800ba42: 2800 cmp r0, #0 + 800ba44: f43f ae7e beq.w 800b744 <_strtod_l+0x43c> + 800ba48: 2d00 cmp r5, #0 + 800ba4a: dd08 ble.n 800ba5e <_strtod_l+0x756> + 800ba4c: 462a mov r2, r5 + 800ba4e: 9905 ldr r1, [sp, #20] + 800ba50: 4648 mov r0, r9 + 800ba52: f002 f927 bl 800dca4 <__lshift> + 800ba56: 9005 str r0, [sp, #20] + 800ba58: 2800 cmp r0, #0 + 800ba5a: f43f ae73 beq.w 800b744 <_strtod_l+0x43c> + 800ba5e: 2f00 cmp r7, #0 + 800ba60: dd08 ble.n 800ba74 <_strtod_l+0x76c> + 800ba62: 4641 mov r1, r8 + 800ba64: 463a mov r2, r7 + 800ba66: 4648 mov r0, r9 + 800ba68: f002 f91c bl 800dca4 <__lshift> + 800ba6c: 4680 mov r8, r0 + 800ba6e: 2800 cmp r0, #0 + 800ba70: f43f ae68 beq.w 800b744 <_strtod_l+0x43c> + 800ba74: 9a05 ldr r2, [sp, #20] + 800ba76: 991c ldr r1, [sp, #112] ; 0x70 + 800ba78: 4648 mov r0, r9 + 800ba7a: f002 f981 bl 800dd80 <__mdiff> + 800ba7e: 4604 mov r4, r0 + 800ba80: 2800 cmp r0, #0 + 800ba82: f43f ae5f beq.w 800b744 <_strtod_l+0x43c> + 800ba86: 68c3 ldr r3, [r0, #12] + 800ba88: 930c str r3, [sp, #48] ; 0x30 + 800ba8a: 2300 movs r3, #0 + 800ba8c: 60c3 str r3, [r0, #12] + 800ba8e: 4641 mov r1, r8 + 800ba90: f002 f95c bl 800dd4c <__mcmp> + 800ba94: 2800 cmp r0, #0 + 800ba96: da55 bge.n 800bb44 <_strtod_l+0x83c> + 800ba98: 9b0c ldr r3, [sp, #48] ; 0x30 + 800ba9a: b9e3 cbnz r3, 800bad6 <_strtod_l+0x7ce> + 800ba9c: f1ba 0f00 cmp.w sl, #0 + 800baa0: d119 bne.n 800bad6 <_strtod_l+0x7ce> + 800baa2: f3cb 0313 ubfx r3, fp, #0, #20 + 800baa6: b9b3 cbnz r3, 800bad6 <_strtod_l+0x7ce> + 800baa8: f02b 4300 bic.w r3, fp, #2147483648 ; 0x80000000 + 800baac: 0d1b lsrs r3, r3, #20 + 800baae: 051b lsls r3, r3, #20 + 800bab0: f1b3 6fd6 cmp.w r3, #112197632 ; 0x6b00000 + 800bab4: d90f bls.n 800bad6 <_strtod_l+0x7ce> + 800bab6: 6963 ldr r3, [r4, #20] + 800bab8: b913 cbnz r3, 800bac0 <_strtod_l+0x7b8> + 800baba: 6923 ldr r3, [r4, #16] + 800babc: 2b01 cmp r3, #1 + 800babe: dd0a ble.n 800bad6 <_strtod_l+0x7ce> + 800bac0: 4621 mov r1, r4 + 800bac2: 2201 movs r2, #1 + 800bac4: 4648 mov r0, r9 + 800bac6: f002 f8ed bl 800dca4 <__lshift> + 800baca: 4641 mov r1, r8 + 800bacc: 4604 mov r4, r0 + 800bace: f002 f93d bl 800dd4c <__mcmp> + 800bad2: 2800 cmp r0, #0 + 800bad4: dc67 bgt.n 800bba6 <_strtod_l+0x89e> + 800bad6: 9b04 ldr r3, [sp, #16] + 800bad8: 2b00 cmp r3, #0 + 800bada: d171 bne.n 800bbc0 <_strtod_l+0x8b8> + 800badc: e63d b.n 800b75a <_strtod_l+0x452> + 800bade: f018 0f01 tst.w r8, #1 + 800bae2: d004 beq.n 800baee <_strtod_l+0x7e6> + 800bae4: e9d5 2300 ldrd r2, r3, [r5] + 800bae8: f7f4 fd8e bl 8000608 <__aeabi_dmul> + 800baec: 2301 movs r3, #1 + 800baee: ea4f 0868 mov.w r8, r8, asr #1 + 800baf2: 3508 adds r5, #8 + 800baf4: e6e5 b.n 800b8c2 <_strtod_l+0x5ba> + 800baf6: f04f 32ff mov.w r2, #4294967295 + 800bafa: fa02 f303 lsl.w r3, r2, r3 + 800bafe: ea03 0a0a and.w sl, r3, sl + 800bb02: e6ff b.n 800b904 <_strtod_l+0x5fc> + 800bb04: f1c6 467f rsb r6, r6, #4278190080 ; 0xff000000 + 800bb08: f506 067f add.w r6, r6, #16711680 ; 0xff0000 + 800bb0c: f506 467b add.w r6, r6, #64256 ; 0xfb00 + 800bb10: 36e2 adds r6, #226 ; 0xe2 + 800bb12: fa01 f306 lsl.w r3, r1, r6 + 800bb16: 930a str r3, [sp, #40] ; 0x28 + 800bb18: 910f str r1, [sp, #60] ; 0x3c + 800bb1a: e75d b.n 800b9d8 <_strtod_l+0x6d0> + 800bb1c: 2300 movs r3, #0 + 800bb1e: 930a str r3, [sp, #40] ; 0x28 + 800bb20: 2301 movs r3, #1 + 800bb22: 930f str r3, [sp, #60] ; 0x3c + 800bb24: e758 b.n 800b9d8 <_strtod_l+0x6d0> + 800bb26: 4632 mov r2, r6 + 800bb28: 991c ldr r1, [sp, #112] ; 0x70 + 800bb2a: 4648 mov r0, r9 + 800bb2c: f002 f8ba bl 800dca4 <__lshift> + 800bb30: 901c str r0, [sp, #112] ; 0x70 + 800bb32: 2800 cmp r0, #0 + 800bb34: f47f af7c bne.w 800ba30 <_strtod_l+0x728> + 800bb38: e604 b.n 800b744 <_strtod_l+0x43c> + 800bb3a: bf00 nop + 800bb3c: 0800e9a0 .word 0x0800e9a0 + 800bb40: fffffc02 .word 0xfffffc02 + 800bb44: 465d mov r5, fp + 800bb46: f040 8086 bne.w 800bc56 <_strtod_l+0x94e> + 800bb4a: 9a0c ldr r2, [sp, #48] ; 0x30 + 800bb4c: f3cb 0313 ubfx r3, fp, #0, #20 + 800bb50: b32a cbz r2, 800bb9e <_strtod_l+0x896> + 800bb52: 4aaf ldr r2, [pc, #700] ; (800be10 <_strtod_l+0xb08>) + 800bb54: 4293 cmp r3, r2 + 800bb56: d153 bne.n 800bc00 <_strtod_l+0x8f8> + 800bb58: 9b04 ldr r3, [sp, #16] + 800bb5a: 4650 mov r0, sl + 800bb5c: b1d3 cbz r3, 800bb94 <_strtod_l+0x88c> + 800bb5e: 4aad ldr r2, [pc, #692] ; (800be14 <_strtod_l+0xb0c>) + 800bb60: 402a ands r2, r5 + 800bb62: f1b2 6fd4 cmp.w r2, #111149056 ; 0x6a00000 + 800bb66: f04f 31ff mov.w r1, #4294967295 + 800bb6a: d816 bhi.n 800bb9a <_strtod_l+0x892> + 800bb6c: 0d12 lsrs r2, r2, #20 + 800bb6e: f1c2 036b rsb r3, r2, #107 ; 0x6b + 800bb72: fa01 f303 lsl.w r3, r1, r3 + 800bb76: 4298 cmp r0, r3 + 800bb78: d142 bne.n 800bc00 <_strtod_l+0x8f8> + 800bb7a: 4ba7 ldr r3, [pc, #668] ; (800be18 <_strtod_l+0xb10>) + 800bb7c: 429d cmp r5, r3 + 800bb7e: d102 bne.n 800bb86 <_strtod_l+0x87e> + 800bb80: 3001 adds r0, #1 + 800bb82: f43f addf beq.w 800b744 <_strtod_l+0x43c> + 800bb86: 4ba3 ldr r3, [pc, #652] ; (800be14 <_strtod_l+0xb0c>) + 800bb88: 402b ands r3, r5 + 800bb8a: f503 1b80 add.w fp, r3, #1048576 ; 0x100000 + 800bb8e: f04f 0a00 mov.w sl, #0 + 800bb92: e7a0 b.n 800bad6 <_strtod_l+0x7ce> + 800bb94: f04f 33ff mov.w r3, #4294967295 + 800bb98: e7ed b.n 800bb76 <_strtod_l+0x86e> + 800bb9a: 460b mov r3, r1 + 800bb9c: e7eb b.n 800bb76 <_strtod_l+0x86e> + 800bb9e: bb7b cbnz r3, 800bc00 <_strtod_l+0x8f8> + 800bba0: f1ba 0f00 cmp.w sl, #0 + 800bba4: d12c bne.n 800bc00 <_strtod_l+0x8f8> + 800bba6: 9904 ldr r1, [sp, #16] + 800bba8: 4a9a ldr r2, [pc, #616] ; (800be14 <_strtod_l+0xb0c>) + 800bbaa: 465b mov r3, fp + 800bbac: b1f1 cbz r1, 800bbec <_strtod_l+0x8e4> + 800bbae: ea02 010b and.w r1, r2, fp + 800bbb2: f1b1 6fd6 cmp.w r1, #112197632 ; 0x6b00000 + 800bbb6: dc19 bgt.n 800bbec <_strtod_l+0x8e4> + 800bbb8: f1b1 7f5c cmp.w r1, #57671680 ; 0x3700000 + 800bbbc: f77f ae5b ble.w 800b876 <_strtod_l+0x56e> + 800bbc0: 4a96 ldr r2, [pc, #600] ; (800be1c <_strtod_l+0xb14>) + 800bbc2: 2300 movs r3, #0 + 800bbc4: e9cd 3214 strd r3, r2, [sp, #80] ; 0x50 + 800bbc8: 4650 mov r0, sl + 800bbca: 4659 mov r1, fp + 800bbcc: e9dd 2314 ldrd r2, r3, [sp, #80] ; 0x50 + 800bbd0: f7f4 fd1a bl 8000608 <__aeabi_dmul> + 800bbd4: 4682 mov sl, r0 + 800bbd6: 468b mov fp, r1 + 800bbd8: 2900 cmp r1, #0 + 800bbda: f47f adbe bne.w 800b75a <_strtod_l+0x452> + 800bbde: 2800 cmp r0, #0 + 800bbe0: f47f adbb bne.w 800b75a <_strtod_l+0x452> + 800bbe4: 2322 movs r3, #34 ; 0x22 + 800bbe6: f8c9 3000 str.w r3, [r9] + 800bbea: e5b6 b.n 800b75a <_strtod_l+0x452> + 800bbec: 4013 ands r3, r2 + 800bbee: f5a3 1380 sub.w r3, r3, #1048576 ; 0x100000 + 800bbf2: ea6f 5b13 mvn.w fp, r3, lsr #20 + 800bbf6: ea6f 5b0b mvn.w fp, fp, lsl #20 + 800bbfa: f04f 3aff mov.w sl, #4294967295 + 800bbfe: e76a b.n 800bad6 <_strtod_l+0x7ce> + 800bc00: 9b0a ldr r3, [sp, #40] ; 0x28 + 800bc02: b193 cbz r3, 800bc2a <_strtod_l+0x922> + 800bc04: 422b tst r3, r5 + 800bc06: f43f af66 beq.w 800bad6 <_strtod_l+0x7ce> + 800bc0a: 9b0c ldr r3, [sp, #48] ; 0x30 + 800bc0c: 9a04 ldr r2, [sp, #16] + 800bc0e: 4650 mov r0, sl + 800bc10: 4659 mov r1, fp + 800bc12: b173 cbz r3, 800bc32 <_strtod_l+0x92a> + 800bc14: f7ff fb5c bl 800b2d0 + 800bc18: 4602 mov r2, r0 + 800bc1a: 460b mov r3, r1 + 800bc1c: e9dd 0108 ldrd r0, r1, [sp, #32] + 800bc20: f7f4 fb3c bl 800029c <__adddf3> + 800bc24: 4682 mov sl, r0 + 800bc26: 468b mov fp, r1 + 800bc28: e755 b.n 800bad6 <_strtod_l+0x7ce> + 800bc2a: 9b0f ldr r3, [sp, #60] ; 0x3c + 800bc2c: ea13 0f0a tst.w r3, sl + 800bc30: e7e9 b.n 800bc06 <_strtod_l+0x8fe> + 800bc32: f7ff fb4d bl 800b2d0 + 800bc36: 4602 mov r2, r0 + 800bc38: 460b mov r3, r1 + 800bc3a: e9dd 0108 ldrd r0, r1, [sp, #32] + 800bc3e: f7f4 fb2b bl 8000298 <__aeabi_dsub> + 800bc42: 2200 movs r2, #0 + 800bc44: 2300 movs r3, #0 + 800bc46: 4682 mov sl, r0 + 800bc48: 468b mov fp, r1 + 800bc4a: f7f4 ff45 bl 8000ad8 <__aeabi_dcmpeq> + 800bc4e: 2800 cmp r0, #0 + 800bc50: f47f ae11 bne.w 800b876 <_strtod_l+0x56e> + 800bc54: e73f b.n 800bad6 <_strtod_l+0x7ce> + 800bc56: 4641 mov r1, r8 + 800bc58: 4620 mov r0, r4 + 800bc5a: f002 f9b4 bl 800dfc6 <__ratio> + 800bc5e: ec57 6b10 vmov r6, r7, d0 + 800bc62: 2200 movs r2, #0 + 800bc64: f04f 4380 mov.w r3, #1073741824 ; 0x40000000 + 800bc68: ee10 0a10 vmov r0, s0 + 800bc6c: 4639 mov r1, r7 + 800bc6e: f7f4 ff47 bl 8000b00 <__aeabi_dcmple> + 800bc72: 2800 cmp r0, #0 + 800bc74: d077 beq.n 800bd66 <_strtod_l+0xa5e> + 800bc76: 9b0c ldr r3, [sp, #48] ; 0x30 + 800bc78: 2b00 cmp r3, #0 + 800bc7a: d04a beq.n 800bd12 <_strtod_l+0xa0a> + 800bc7c: 4b68 ldr r3, [pc, #416] ; (800be20 <_strtod_l+0xb18>) + 800bc7e: 2200 movs r2, #0 + 800bc80: e9cd 230a strd r2, r3, [sp, #40] ; 0x28 + 800bc84: 4f66 ldr r7, [pc, #408] ; (800be20 <_strtod_l+0xb18>) + 800bc86: 2600 movs r6, #0 + 800bc88: 4b62 ldr r3, [pc, #392] ; (800be14 <_strtod_l+0xb0c>) + 800bc8a: 402b ands r3, r5 + 800bc8c: 930f str r3, [sp, #60] ; 0x3c + 800bc8e: 9a0f ldr r2, [sp, #60] ; 0x3c + 800bc90: 4b64 ldr r3, [pc, #400] ; (800be24 <_strtod_l+0xb1c>) + 800bc92: 429a cmp r2, r3 + 800bc94: f040 80ce bne.w 800be34 <_strtod_l+0xb2c> + 800bc98: e9dd 2308 ldrd r2, r3, [sp, #32] + 800bc9c: e9dd 010a ldrd r0, r1, [sp, #40] ; 0x28 + 800bca0: f1a5 7b54 sub.w fp, r5, #55574528 ; 0x3500000 + 800bca4: ec4b ab10 vmov d0, sl, fp + 800bca8: e9cd 2314 strd r2, r3, [sp, #80] ; 0x50 + 800bcac: e9cd 010a strd r0, r1, [sp, #40] ; 0x28 + 800bcb0: f002 f8c4 bl 800de3c <__ulp> + 800bcb4: e9dd 010a ldrd r0, r1, [sp, #40] ; 0x28 + 800bcb8: ec53 2b10 vmov r2, r3, d0 + 800bcbc: f7f4 fca4 bl 8000608 <__aeabi_dmul> + 800bcc0: 4652 mov r2, sl + 800bcc2: 465b mov r3, fp + 800bcc4: f7f4 faea bl 800029c <__adddf3> + 800bcc8: 460b mov r3, r1 + 800bcca: 4952 ldr r1, [pc, #328] ; (800be14 <_strtod_l+0xb0c>) + 800bccc: 4a56 ldr r2, [pc, #344] ; (800be28 <_strtod_l+0xb20>) + 800bcce: 4019 ands r1, r3 + 800bcd0: 4291 cmp r1, r2 + 800bcd2: 4682 mov sl, r0 + 800bcd4: d95b bls.n 800bd8e <_strtod_l+0xa86> + 800bcd6: 9b09 ldr r3, [sp, #36] ; 0x24 + 800bcd8: f102 7254 add.w r2, r2, #55574528 ; 0x3500000 + 800bcdc: 4293 cmp r3, r2 + 800bcde: d103 bne.n 800bce8 <_strtod_l+0x9e0> + 800bce0: 9b08 ldr r3, [sp, #32] + 800bce2: 3301 adds r3, #1 + 800bce4: f43f ad2e beq.w 800b744 <_strtod_l+0x43c> + 800bce8: f8df b12c ldr.w fp, [pc, #300] ; 800be18 <_strtod_l+0xb10> + 800bcec: f04f 3aff mov.w sl, #4294967295 + 800bcf0: 991c ldr r1, [sp, #112] ; 0x70 + 800bcf2: 4648 mov r0, r9 + 800bcf4: f001 fe0b bl 800d90e <_Bfree> + 800bcf8: 9905 ldr r1, [sp, #20] + 800bcfa: 4648 mov r0, r9 + 800bcfc: f001 fe07 bl 800d90e <_Bfree> + 800bd00: 4641 mov r1, r8 + 800bd02: 4648 mov r0, r9 + 800bd04: f001 fe03 bl 800d90e <_Bfree> + 800bd08: 4621 mov r1, r4 + 800bd0a: 4648 mov r0, r9 + 800bd0c: f001 fdff bl 800d90e <_Bfree> + 800bd10: e619 b.n 800b946 <_strtod_l+0x63e> + 800bd12: f1ba 0f00 cmp.w sl, #0 + 800bd16: d11a bne.n 800bd4e <_strtod_l+0xa46> + 800bd18: f3cb 0313 ubfx r3, fp, #0, #20 + 800bd1c: b9eb cbnz r3, 800bd5a <_strtod_l+0xa52> + 800bd1e: 2200 movs r2, #0 + 800bd20: 4b3f ldr r3, [pc, #252] ; (800be20 <_strtod_l+0xb18>) + 800bd22: 4630 mov r0, r6 + 800bd24: 4639 mov r1, r7 + 800bd26: f7f4 fee1 bl 8000aec <__aeabi_dcmplt> + 800bd2a: b9c8 cbnz r0, 800bd60 <_strtod_l+0xa58> + 800bd2c: 4630 mov r0, r6 + 800bd2e: 4639 mov r1, r7 + 800bd30: 2200 movs r2, #0 + 800bd32: 4b3e ldr r3, [pc, #248] ; (800be2c <_strtod_l+0xb24>) + 800bd34: f7f4 fc68 bl 8000608 <__aeabi_dmul> + 800bd38: 4606 mov r6, r0 + 800bd3a: 460f mov r7, r1 + 800bd3c: f107 4300 add.w r3, r7, #2147483648 ; 0x80000000 + 800bd40: 9618 str r6, [sp, #96] ; 0x60 + 800bd42: 9319 str r3, [sp, #100] ; 0x64 + 800bd44: e9dd 2318 ldrd r2, r3, [sp, #96] ; 0x60 + 800bd48: e9cd 230a strd r2, r3, [sp, #40] ; 0x28 + 800bd4c: e79c b.n 800bc88 <_strtod_l+0x980> + 800bd4e: f1ba 0f01 cmp.w sl, #1 + 800bd52: d102 bne.n 800bd5a <_strtod_l+0xa52> + 800bd54: 2d00 cmp r5, #0 + 800bd56: f43f ad8e beq.w 800b876 <_strtod_l+0x56e> + 800bd5a: 2200 movs r2, #0 + 800bd5c: 4b34 ldr r3, [pc, #208] ; (800be30 <_strtod_l+0xb28>) + 800bd5e: e78f b.n 800bc80 <_strtod_l+0x978> + 800bd60: 2600 movs r6, #0 + 800bd62: 4f32 ldr r7, [pc, #200] ; (800be2c <_strtod_l+0xb24>) + 800bd64: e7ea b.n 800bd3c <_strtod_l+0xa34> + 800bd66: 4b31 ldr r3, [pc, #196] ; (800be2c <_strtod_l+0xb24>) + 800bd68: 4630 mov r0, r6 + 800bd6a: 4639 mov r1, r7 + 800bd6c: 2200 movs r2, #0 + 800bd6e: f7f4 fc4b bl 8000608 <__aeabi_dmul> + 800bd72: 9b0c ldr r3, [sp, #48] ; 0x30 + 800bd74: 4606 mov r6, r0 + 800bd76: 460f mov r7, r1 + 800bd78: b933 cbnz r3, 800bd88 <_strtod_l+0xa80> + 800bd7a: f101 4300 add.w r3, r1, #2147483648 ; 0x80000000 + 800bd7e: 9010 str r0, [sp, #64] ; 0x40 + 800bd80: 9311 str r3, [sp, #68] ; 0x44 + 800bd82: e9dd 2310 ldrd r2, r3, [sp, #64] ; 0x40 + 800bd86: e7df b.n 800bd48 <_strtod_l+0xa40> + 800bd88: e9cd 6710 strd r6, r7, [sp, #64] ; 0x40 + 800bd8c: e7f9 b.n 800bd82 <_strtod_l+0xa7a> + 800bd8e: f103 7b54 add.w fp, r3, #55574528 ; 0x3500000 + 800bd92: 9b04 ldr r3, [sp, #16] + 800bd94: 2b00 cmp r3, #0 + 800bd96: d1ab bne.n 800bcf0 <_strtod_l+0x9e8> + 800bd98: f02b 4300 bic.w r3, fp, #2147483648 ; 0x80000000 + 800bd9c: 0d1b lsrs r3, r3, #20 + 800bd9e: 9a0f ldr r2, [sp, #60] ; 0x3c + 800bda0: 051b lsls r3, r3, #20 + 800bda2: 429a cmp r2, r3 + 800bda4: 465d mov r5, fp + 800bda6: d1a3 bne.n 800bcf0 <_strtod_l+0x9e8> + 800bda8: 4639 mov r1, r7 + 800bdaa: 4630 mov r0, r6 + 800bdac: f7f4 fedc bl 8000b68 <__aeabi_d2iz> + 800bdb0: f7f4 fbc0 bl 8000534 <__aeabi_i2d> + 800bdb4: 460b mov r3, r1 + 800bdb6: 4602 mov r2, r0 + 800bdb8: 4639 mov r1, r7 + 800bdba: 4630 mov r0, r6 + 800bdbc: f7f4 fa6c bl 8000298 <__aeabi_dsub> + 800bdc0: 9b0c ldr r3, [sp, #48] ; 0x30 + 800bdc2: 4606 mov r6, r0 + 800bdc4: 460f mov r7, r1 + 800bdc6: b933 cbnz r3, 800bdd6 <_strtod_l+0xace> + 800bdc8: f1ba 0f00 cmp.w sl, #0 + 800bdcc: d103 bne.n 800bdd6 <_strtod_l+0xace> + 800bdce: f3cb 0513 ubfx r5, fp, #0, #20 + 800bdd2: 2d00 cmp r5, #0 + 800bdd4: d06d beq.n 800beb2 <_strtod_l+0xbaa> + 800bdd6: a30a add r3, pc, #40 ; (adr r3, 800be00 <_strtod_l+0xaf8>) + 800bdd8: e9d3 2300 ldrd r2, r3, [r3] + 800bddc: 4630 mov r0, r6 + 800bdde: 4639 mov r1, r7 + 800bde0: f7f4 fe84 bl 8000aec <__aeabi_dcmplt> + 800bde4: 2800 cmp r0, #0 + 800bde6: f47f acb8 bne.w 800b75a <_strtod_l+0x452> + 800bdea: a307 add r3, pc, #28 ; (adr r3, 800be08 <_strtod_l+0xb00>) + 800bdec: e9d3 2300 ldrd r2, r3, [r3] + 800bdf0: 4630 mov r0, r6 + 800bdf2: 4639 mov r1, r7 + 800bdf4: f7f4 fe98 bl 8000b28 <__aeabi_dcmpgt> + 800bdf8: 2800 cmp r0, #0 + 800bdfa: f43f af79 beq.w 800bcf0 <_strtod_l+0x9e8> + 800bdfe: e4ac b.n 800b75a <_strtod_l+0x452> + 800be00: 94a03595 .word 0x94a03595 + 800be04: 3fdfffff .word 0x3fdfffff + 800be08: 35afe535 .word 0x35afe535 + 800be0c: 3fe00000 .word 0x3fe00000 + 800be10: 000fffff .word 0x000fffff + 800be14: 7ff00000 .word 0x7ff00000 + 800be18: 7fefffff .word 0x7fefffff + 800be1c: 39500000 .word 0x39500000 + 800be20: 3ff00000 .word 0x3ff00000 + 800be24: 7fe00000 .word 0x7fe00000 + 800be28: 7c9fffff .word 0x7c9fffff + 800be2c: 3fe00000 .word 0x3fe00000 + 800be30: bff00000 .word 0xbff00000 + 800be34: 9b04 ldr r3, [sp, #16] + 800be36: b333 cbz r3, 800be86 <_strtod_l+0xb7e> + 800be38: 9b0f ldr r3, [sp, #60] ; 0x3c + 800be3a: f1b3 6fd4 cmp.w r3, #111149056 ; 0x6a00000 + 800be3e: d822 bhi.n 800be86 <_strtod_l+0xb7e> + 800be40: a327 add r3, pc, #156 ; (adr r3, 800bee0 <_strtod_l+0xbd8>) + 800be42: e9d3 2300 ldrd r2, r3, [r3] + 800be46: 4630 mov r0, r6 + 800be48: 4639 mov r1, r7 + 800be4a: f7f4 fe59 bl 8000b00 <__aeabi_dcmple> + 800be4e: b1a0 cbz r0, 800be7a <_strtod_l+0xb72> + 800be50: 4639 mov r1, r7 + 800be52: 4630 mov r0, r6 + 800be54: f7f4 feb0 bl 8000bb8 <__aeabi_d2uiz> + 800be58: 2800 cmp r0, #0 + 800be5a: bf08 it eq + 800be5c: 2001 moveq r0, #1 + 800be5e: f7f4 fb59 bl 8000514 <__aeabi_ui2d> + 800be62: 9b0c ldr r3, [sp, #48] ; 0x30 + 800be64: 4606 mov r6, r0 + 800be66: 460f mov r7, r1 + 800be68: bb03 cbnz r3, 800beac <_strtod_l+0xba4> + 800be6a: f101 4300 add.w r3, r1, #2147483648 ; 0x80000000 + 800be6e: 9012 str r0, [sp, #72] ; 0x48 + 800be70: 9313 str r3, [sp, #76] ; 0x4c + 800be72: e9dd 2312 ldrd r2, r3, [sp, #72] ; 0x48 + 800be76: e9cd 230a strd r2, r3, [sp, #40] ; 0x28 + 800be7a: 9b0b ldr r3, [sp, #44] ; 0x2c + 800be7c: 9a0f ldr r2, [sp, #60] ; 0x3c + 800be7e: f103 63d6 add.w r3, r3, #112197632 ; 0x6b00000 + 800be82: 1a9b subs r3, r3, r2 + 800be84: 930b str r3, [sp, #44] ; 0x2c + 800be86: ed9d 0b08 vldr d0, [sp, #32] + 800be8a: e9dd ab0a ldrd sl, fp, [sp, #40] ; 0x28 + 800be8e: f001 ffd5 bl 800de3c <__ulp> + 800be92: 4650 mov r0, sl + 800be94: ec53 2b10 vmov r2, r3, d0 + 800be98: 4659 mov r1, fp + 800be9a: f7f4 fbb5 bl 8000608 <__aeabi_dmul> + 800be9e: e9dd 2308 ldrd r2, r3, [sp, #32] + 800bea2: f7f4 f9fb bl 800029c <__adddf3> + 800bea6: 4682 mov sl, r0 + 800bea8: 468b mov fp, r1 + 800beaa: e772 b.n 800bd92 <_strtod_l+0xa8a> + 800beac: e9cd 6712 strd r6, r7, [sp, #72] ; 0x48 + 800beb0: e7df b.n 800be72 <_strtod_l+0xb6a> + 800beb2: a30d add r3, pc, #52 ; (adr r3, 800bee8 <_strtod_l+0xbe0>) + 800beb4: e9d3 2300 ldrd r2, r3, [r3] + 800beb8: f7f4 fe18 bl 8000aec <__aeabi_dcmplt> + 800bebc: e79c b.n 800bdf8 <_strtod_l+0xaf0> + 800bebe: 2300 movs r3, #0 + 800bec0: 930d str r3, [sp, #52] ; 0x34 + 800bec2: 9a17 ldr r2, [sp, #92] ; 0x5c + 800bec4: 9b1b ldr r3, [sp, #108] ; 0x6c + 800bec6: 6013 str r3, [r2, #0] + 800bec8: f7ff ba61 b.w 800b38e <_strtod_l+0x86> + 800becc: 2b65 cmp r3, #101 ; 0x65 + 800bece: f04f 0200 mov.w r2, #0 + 800bed2: f43f ab4e beq.w 800b572 <_strtod_l+0x26a> + 800bed6: 2101 movs r1, #1 + 800bed8: 4614 mov r4, r2 + 800beda: 9104 str r1, [sp, #16] + 800bedc: f7ff bacb b.w 800b476 <_strtod_l+0x16e> + 800bee0: ffc00000 .word 0xffc00000 + 800bee4: 41dfffff .word 0x41dfffff + 800bee8: 94a03595 .word 0x94a03595 + 800beec: 3fcfffff .word 0x3fcfffff + +0800bef0 <_strtod_r>: + 800bef0: 4b05 ldr r3, [pc, #20] ; (800bf08 <_strtod_r+0x18>) + 800bef2: 681b ldr r3, [r3, #0] + 800bef4: b410 push {r4} + 800bef6: 6a1b ldr r3, [r3, #32] + 800bef8: 4c04 ldr r4, [pc, #16] ; (800bf0c <_strtod_r+0x1c>) + 800befa: 2b00 cmp r3, #0 + 800befc: bf08 it eq + 800befe: 4623 moveq r3, r4 + 800bf00: f85d 4b04 ldr.w r4, [sp], #4 + 800bf04: f7ff ba00 b.w 800b308 <_strtod_l> + 800bf08: 2000002c .word 0x2000002c + 800bf0c: 20000090 .word 0x20000090 + +0800bf10 <_strtol_l.isra.0>: + 800bf10: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 800bf14: 4680 mov r8, r0 + 800bf16: 4689 mov r9, r1 + 800bf18: 4692 mov sl, r2 + 800bf1a: 461e mov r6, r3 + 800bf1c: 460f mov r7, r1 + 800bf1e: 463d mov r5, r7 + 800bf20: 9808 ldr r0, [sp, #32] + 800bf22: f815 4b01 ldrb.w r4, [r5], #1 + 800bf26: f001 fc27 bl 800d778 <__locale_ctype_ptr_l> + 800bf2a: 4420 add r0, r4 + 800bf2c: 7843 ldrb r3, [r0, #1] + 800bf2e: f013 0308 ands.w r3, r3, #8 + 800bf32: d132 bne.n 800bf9a <_strtol_l.isra.0+0x8a> + 800bf34: 2c2d cmp r4, #45 ; 0x2d + 800bf36: d132 bne.n 800bf9e <_strtol_l.isra.0+0x8e> + 800bf38: 787c ldrb r4, [r7, #1] + 800bf3a: 1cbd adds r5, r7, #2 + 800bf3c: 2201 movs r2, #1 + 800bf3e: 2e00 cmp r6, #0 + 800bf40: d05d beq.n 800bffe <_strtol_l.isra.0+0xee> + 800bf42: 2e10 cmp r6, #16 + 800bf44: d109 bne.n 800bf5a <_strtol_l.isra.0+0x4a> + 800bf46: 2c30 cmp r4, #48 ; 0x30 + 800bf48: d107 bne.n 800bf5a <_strtol_l.isra.0+0x4a> + 800bf4a: 782b ldrb r3, [r5, #0] + 800bf4c: f003 03df and.w r3, r3, #223 ; 0xdf + 800bf50: 2b58 cmp r3, #88 ; 0x58 + 800bf52: d14f bne.n 800bff4 <_strtol_l.isra.0+0xe4> + 800bf54: 786c ldrb r4, [r5, #1] + 800bf56: 2610 movs r6, #16 + 800bf58: 3502 adds r5, #2 + 800bf5a: 2a00 cmp r2, #0 + 800bf5c: bf14 ite ne + 800bf5e: f04f 4100 movne.w r1, #2147483648 ; 0x80000000 + 800bf62: f06f 4100 mvneq.w r1, #2147483648 ; 0x80000000 + 800bf66: 2700 movs r7, #0 + 800bf68: fbb1 fcf6 udiv ip, r1, r6 + 800bf6c: 4638 mov r0, r7 + 800bf6e: fb06 1e1c mls lr, r6, ip, r1 + 800bf72: f1a4 0330 sub.w r3, r4, #48 ; 0x30 + 800bf76: 2b09 cmp r3, #9 + 800bf78: d817 bhi.n 800bfaa <_strtol_l.isra.0+0x9a> + 800bf7a: 461c mov r4, r3 + 800bf7c: 42a6 cmp r6, r4 + 800bf7e: dd23 ble.n 800bfc8 <_strtol_l.isra.0+0xb8> + 800bf80: 1c7b adds r3, r7, #1 + 800bf82: d007 beq.n 800bf94 <_strtol_l.isra.0+0x84> + 800bf84: 4584 cmp ip, r0 + 800bf86: d31c bcc.n 800bfc2 <_strtol_l.isra.0+0xb2> + 800bf88: d101 bne.n 800bf8e <_strtol_l.isra.0+0x7e> + 800bf8a: 45a6 cmp lr, r4 + 800bf8c: db19 blt.n 800bfc2 <_strtol_l.isra.0+0xb2> + 800bf8e: fb00 4006 mla r0, r0, r6, r4 + 800bf92: 2701 movs r7, #1 + 800bf94: f815 4b01 ldrb.w r4, [r5], #1 + 800bf98: e7eb b.n 800bf72 <_strtol_l.isra.0+0x62> + 800bf9a: 462f mov r7, r5 + 800bf9c: e7bf b.n 800bf1e <_strtol_l.isra.0+0xe> + 800bf9e: 2c2b cmp r4, #43 ; 0x2b + 800bfa0: bf04 itt eq + 800bfa2: 1cbd addeq r5, r7, #2 + 800bfa4: 787c ldrbeq r4, [r7, #1] + 800bfa6: 461a mov r2, r3 + 800bfa8: e7c9 b.n 800bf3e <_strtol_l.isra.0+0x2e> + 800bfaa: f1a4 0341 sub.w r3, r4, #65 ; 0x41 + 800bfae: 2b19 cmp r3, #25 + 800bfb0: d801 bhi.n 800bfb6 <_strtol_l.isra.0+0xa6> + 800bfb2: 3c37 subs r4, #55 ; 0x37 + 800bfb4: e7e2 b.n 800bf7c <_strtol_l.isra.0+0x6c> + 800bfb6: f1a4 0361 sub.w r3, r4, #97 ; 0x61 + 800bfba: 2b19 cmp r3, #25 + 800bfbc: d804 bhi.n 800bfc8 <_strtol_l.isra.0+0xb8> + 800bfbe: 3c57 subs r4, #87 ; 0x57 + 800bfc0: e7dc b.n 800bf7c <_strtol_l.isra.0+0x6c> + 800bfc2: f04f 37ff mov.w r7, #4294967295 + 800bfc6: e7e5 b.n 800bf94 <_strtol_l.isra.0+0x84> + 800bfc8: 1c7b adds r3, r7, #1 + 800bfca: d108 bne.n 800bfde <_strtol_l.isra.0+0xce> + 800bfcc: 2322 movs r3, #34 ; 0x22 + 800bfce: f8c8 3000 str.w r3, [r8] + 800bfd2: 4608 mov r0, r1 + 800bfd4: f1ba 0f00 cmp.w sl, #0 + 800bfd8: d107 bne.n 800bfea <_strtol_l.isra.0+0xda> + 800bfda: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 800bfde: b102 cbz r2, 800bfe2 <_strtol_l.isra.0+0xd2> + 800bfe0: 4240 negs r0, r0 + 800bfe2: f1ba 0f00 cmp.w sl, #0 + 800bfe6: d0f8 beq.n 800bfda <_strtol_l.isra.0+0xca> + 800bfe8: b10f cbz r7, 800bfee <_strtol_l.isra.0+0xde> + 800bfea: f105 39ff add.w r9, r5, #4294967295 + 800bfee: f8ca 9000 str.w r9, [sl] + 800bff2: e7f2 b.n 800bfda <_strtol_l.isra.0+0xca> + 800bff4: 2430 movs r4, #48 ; 0x30 + 800bff6: 2e00 cmp r6, #0 + 800bff8: d1af bne.n 800bf5a <_strtol_l.isra.0+0x4a> + 800bffa: 2608 movs r6, #8 + 800bffc: e7ad b.n 800bf5a <_strtol_l.isra.0+0x4a> + 800bffe: 2c30 cmp r4, #48 ; 0x30 + 800c000: d0a3 beq.n 800bf4a <_strtol_l.isra.0+0x3a> + 800c002: 260a movs r6, #10 + 800c004: e7a9 b.n 800bf5a <_strtol_l.isra.0+0x4a> + ... + +0800c008 <_strtol_r>: + 800c008: b537 push {r0, r1, r2, r4, r5, lr} + 800c00a: 4c06 ldr r4, [pc, #24] ; (800c024 <_strtol_r+0x1c>) + 800c00c: 4d06 ldr r5, [pc, #24] ; (800c028 <_strtol_r+0x20>) + 800c00e: 6824 ldr r4, [r4, #0] + 800c010: 6a24 ldr r4, [r4, #32] + 800c012: 2c00 cmp r4, #0 + 800c014: bf08 it eq + 800c016: 462c moveq r4, r5 + 800c018: 9400 str r4, [sp, #0] + 800c01a: f7ff ff79 bl 800bf10 <_strtol_l.isra.0> + 800c01e: b003 add sp, #12 + 800c020: bd30 pop {r4, r5, pc} + 800c022: bf00 nop + 800c024: 2000002c .word 0x2000002c + 800c028: 20000090 .word 0x20000090 + +0800c02c <__swbuf_r>: + 800c02c: b5f8 push {r3, r4, r5, r6, r7, lr} + 800c02e: 460e mov r6, r1 + 800c030: 4614 mov r4, r2 + 800c032: 4605 mov r5, r0 + 800c034: b118 cbz r0, 800c03e <__swbuf_r+0x12> + 800c036: 6983 ldr r3, [r0, #24] + 800c038: b90b cbnz r3, 800c03e <__swbuf_r+0x12> + 800c03a: f000 ffed bl 800d018 <__sinit> + 800c03e: 4b21 ldr r3, [pc, #132] ; (800c0c4 <__swbuf_r+0x98>) + 800c040: 429c cmp r4, r3 + 800c042: d12a bne.n 800c09a <__swbuf_r+0x6e> + 800c044: 686c ldr r4, [r5, #4] + 800c046: 69a3 ldr r3, [r4, #24] + 800c048: 60a3 str r3, [r4, #8] + 800c04a: 89a3 ldrh r3, [r4, #12] + 800c04c: 071a lsls r2, r3, #28 + 800c04e: d52e bpl.n 800c0ae <__swbuf_r+0x82> + 800c050: 6923 ldr r3, [r4, #16] + 800c052: b363 cbz r3, 800c0ae <__swbuf_r+0x82> + 800c054: 6923 ldr r3, [r4, #16] + 800c056: 6820 ldr r0, [r4, #0] + 800c058: 1ac0 subs r0, r0, r3 + 800c05a: 6963 ldr r3, [r4, #20] + 800c05c: b2f6 uxtb r6, r6 + 800c05e: 4283 cmp r3, r0 + 800c060: 4637 mov r7, r6 + 800c062: dc04 bgt.n 800c06e <__swbuf_r+0x42> + 800c064: 4621 mov r1, r4 + 800c066: 4628 mov r0, r5 + 800c068: f000 ff6c bl 800cf44 <_fflush_r> + 800c06c: bb28 cbnz r0, 800c0ba <__swbuf_r+0x8e> + 800c06e: 68a3 ldr r3, [r4, #8] + 800c070: 3b01 subs r3, #1 + 800c072: 60a3 str r3, [r4, #8] + 800c074: 6823 ldr r3, [r4, #0] + 800c076: 1c5a adds r2, r3, #1 + 800c078: 6022 str r2, [r4, #0] + 800c07a: 701e strb r6, [r3, #0] + 800c07c: 6963 ldr r3, [r4, #20] + 800c07e: 3001 adds r0, #1 + 800c080: 4283 cmp r3, r0 + 800c082: d004 beq.n 800c08e <__swbuf_r+0x62> + 800c084: 89a3 ldrh r3, [r4, #12] + 800c086: 07db lsls r3, r3, #31 + 800c088: d519 bpl.n 800c0be <__swbuf_r+0x92> + 800c08a: 2e0a cmp r6, #10 + 800c08c: d117 bne.n 800c0be <__swbuf_r+0x92> + 800c08e: 4621 mov r1, r4 + 800c090: 4628 mov r0, r5 + 800c092: f000 ff57 bl 800cf44 <_fflush_r> + 800c096: b190 cbz r0, 800c0be <__swbuf_r+0x92> + 800c098: e00f b.n 800c0ba <__swbuf_r+0x8e> + 800c09a: 4b0b ldr r3, [pc, #44] ; (800c0c8 <__swbuf_r+0x9c>) + 800c09c: 429c cmp r4, r3 + 800c09e: d101 bne.n 800c0a4 <__swbuf_r+0x78> + 800c0a0: 68ac ldr r4, [r5, #8] + 800c0a2: e7d0 b.n 800c046 <__swbuf_r+0x1a> + 800c0a4: 4b09 ldr r3, [pc, #36] ; (800c0cc <__swbuf_r+0xa0>) + 800c0a6: 429c cmp r4, r3 + 800c0a8: bf08 it eq + 800c0aa: 68ec ldreq r4, [r5, #12] + 800c0ac: e7cb b.n 800c046 <__swbuf_r+0x1a> + 800c0ae: 4621 mov r1, r4 + 800c0b0: 4628 mov r0, r5 + 800c0b2: f000 f80d bl 800c0d0 <__swsetup_r> + 800c0b6: 2800 cmp r0, #0 + 800c0b8: d0cc beq.n 800c054 <__swbuf_r+0x28> + 800c0ba: f04f 37ff mov.w r7, #4294967295 + 800c0be: 4638 mov r0, r7 + 800c0c0: bdf8 pop {r3, r4, r5, r6, r7, pc} + 800c0c2: bf00 nop + 800c0c4: 0800e9f8 .word 0x0800e9f8 + 800c0c8: 0800ea18 .word 0x0800ea18 + 800c0cc: 0800e9d8 .word 0x0800e9d8 + +0800c0d0 <__swsetup_r>: + 800c0d0: 4b32 ldr r3, [pc, #200] ; (800c19c <__swsetup_r+0xcc>) + 800c0d2: b570 push {r4, r5, r6, lr} + 800c0d4: 681d ldr r5, [r3, #0] + 800c0d6: 4606 mov r6, r0 + 800c0d8: 460c mov r4, r1 + 800c0da: b125 cbz r5, 800c0e6 <__swsetup_r+0x16> + 800c0dc: 69ab ldr r3, [r5, #24] + 800c0de: b913 cbnz r3, 800c0e6 <__swsetup_r+0x16> + 800c0e0: 4628 mov r0, r5 + 800c0e2: f000 ff99 bl 800d018 <__sinit> + 800c0e6: 4b2e ldr r3, [pc, #184] ; (800c1a0 <__swsetup_r+0xd0>) + 800c0e8: 429c cmp r4, r3 + 800c0ea: d10f bne.n 800c10c <__swsetup_r+0x3c> + 800c0ec: 686c ldr r4, [r5, #4] + 800c0ee: f9b4 300c ldrsh.w r3, [r4, #12] + 800c0f2: b29a uxth r2, r3 + 800c0f4: 0715 lsls r5, r2, #28 + 800c0f6: d42c bmi.n 800c152 <__swsetup_r+0x82> + 800c0f8: 06d0 lsls r0, r2, #27 + 800c0fa: d411 bmi.n 800c120 <__swsetup_r+0x50> + 800c0fc: 2209 movs r2, #9 + 800c0fe: 6032 str r2, [r6, #0] + 800c100: f043 0340 orr.w r3, r3, #64 ; 0x40 + 800c104: 81a3 strh r3, [r4, #12] + 800c106: f04f 30ff mov.w r0, #4294967295 + 800c10a: e03e b.n 800c18a <__swsetup_r+0xba> + 800c10c: 4b25 ldr r3, [pc, #148] ; (800c1a4 <__swsetup_r+0xd4>) + 800c10e: 429c cmp r4, r3 + 800c110: d101 bne.n 800c116 <__swsetup_r+0x46> + 800c112: 68ac ldr r4, [r5, #8] + 800c114: e7eb b.n 800c0ee <__swsetup_r+0x1e> + 800c116: 4b24 ldr r3, [pc, #144] ; (800c1a8 <__swsetup_r+0xd8>) + 800c118: 429c cmp r4, r3 + 800c11a: bf08 it eq + 800c11c: 68ec ldreq r4, [r5, #12] + 800c11e: e7e6 b.n 800c0ee <__swsetup_r+0x1e> + 800c120: 0751 lsls r1, r2, #29 + 800c122: d512 bpl.n 800c14a <__swsetup_r+0x7a> + 800c124: 6b61 ldr r1, [r4, #52] ; 0x34 + 800c126: b141 cbz r1, 800c13a <__swsetup_r+0x6a> + 800c128: f104 0344 add.w r3, r4, #68 ; 0x44 + 800c12c: 4299 cmp r1, r3 + 800c12e: d002 beq.n 800c136 <__swsetup_r+0x66> + 800c130: 4630 mov r0, r6 + 800c132: f7fe f935 bl 800a3a0 <_free_r> + 800c136: 2300 movs r3, #0 + 800c138: 6363 str r3, [r4, #52] ; 0x34 + 800c13a: 89a3 ldrh r3, [r4, #12] + 800c13c: f023 0324 bic.w r3, r3, #36 ; 0x24 + 800c140: 81a3 strh r3, [r4, #12] + 800c142: 2300 movs r3, #0 + 800c144: 6063 str r3, [r4, #4] + 800c146: 6923 ldr r3, [r4, #16] + 800c148: 6023 str r3, [r4, #0] + 800c14a: 89a3 ldrh r3, [r4, #12] + 800c14c: f043 0308 orr.w r3, r3, #8 + 800c150: 81a3 strh r3, [r4, #12] + 800c152: 6923 ldr r3, [r4, #16] + 800c154: b94b cbnz r3, 800c16a <__swsetup_r+0x9a> + 800c156: 89a3 ldrh r3, [r4, #12] + 800c158: f403 7320 and.w r3, r3, #640 ; 0x280 + 800c15c: f5b3 7f00 cmp.w r3, #512 ; 0x200 + 800c160: d003 beq.n 800c16a <__swsetup_r+0x9a> + 800c162: 4621 mov r1, r4 + 800c164: 4630 mov r0, r6 + 800c166: f001 fb3f bl 800d7e8 <__smakebuf_r> + 800c16a: 89a2 ldrh r2, [r4, #12] + 800c16c: f012 0301 ands.w r3, r2, #1 + 800c170: d00c beq.n 800c18c <__swsetup_r+0xbc> + 800c172: 2300 movs r3, #0 + 800c174: 60a3 str r3, [r4, #8] + 800c176: 6963 ldr r3, [r4, #20] + 800c178: 425b negs r3, r3 + 800c17a: 61a3 str r3, [r4, #24] + 800c17c: 6923 ldr r3, [r4, #16] + 800c17e: b953 cbnz r3, 800c196 <__swsetup_r+0xc6> + 800c180: f9b4 300c ldrsh.w r3, [r4, #12] + 800c184: f013 0080 ands.w r0, r3, #128 ; 0x80 + 800c188: d1ba bne.n 800c100 <__swsetup_r+0x30> + 800c18a: bd70 pop {r4, r5, r6, pc} + 800c18c: 0792 lsls r2, r2, #30 + 800c18e: bf58 it pl + 800c190: 6963 ldrpl r3, [r4, #20] + 800c192: 60a3 str r3, [r4, #8] + 800c194: e7f2 b.n 800c17c <__swsetup_r+0xac> + 800c196: 2000 movs r0, #0 + 800c198: e7f7 b.n 800c18a <__swsetup_r+0xba> + 800c19a: bf00 nop + 800c19c: 2000002c .word 0x2000002c + 800c1a0: 0800e9f8 .word 0x0800e9f8 + 800c1a4: 0800ea18 .word 0x0800ea18 + 800c1a8: 0800e9d8 .word 0x0800e9d8 + +0800c1ac : + 800c1ac: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} + 800c1b0: 6903 ldr r3, [r0, #16] + 800c1b2: 690c ldr r4, [r1, #16] + 800c1b4: 42a3 cmp r3, r4 + 800c1b6: 4680 mov r8, r0 + 800c1b8: f2c0 8082 blt.w 800c2c0 + 800c1bc: 3c01 subs r4, #1 + 800c1be: f101 0714 add.w r7, r1, #20 + 800c1c2: ea4f 0c84 mov.w ip, r4, lsl #2 + 800c1c6: f100 0614 add.w r6, r0, #20 + 800c1ca: f857 5024 ldr.w r5, [r7, r4, lsl #2] + 800c1ce: f856 0024 ldr.w r0, [r6, r4, lsl #2] + 800c1d2: eb06 030c add.w r3, r6, ip + 800c1d6: 3501 adds r5, #1 + 800c1d8: eb07 090c add.w r9, r7, ip + 800c1dc: 9301 str r3, [sp, #4] + 800c1de: fbb0 f5f5 udiv r5, r0, r5 + 800c1e2: b395 cbz r5, 800c24a + 800c1e4: f04f 0a00 mov.w sl, #0 + 800c1e8: 4638 mov r0, r7 + 800c1ea: 46b6 mov lr, r6 + 800c1ec: 46d3 mov fp, sl + 800c1ee: f850 2b04 ldr.w r2, [r0], #4 + 800c1f2: b293 uxth r3, r2 + 800c1f4: fb05 a303 mla r3, r5, r3, sl + 800c1f8: ea4f 4a13 mov.w sl, r3, lsr #16 + 800c1fc: b29b uxth r3, r3 + 800c1fe: ebab 0303 sub.w r3, fp, r3 + 800c202: 0c12 lsrs r2, r2, #16 + 800c204: f8de b000 ldr.w fp, [lr] + 800c208: fb05 a202 mla r2, r5, r2, sl + 800c20c: fa13 f38b uxtah r3, r3, fp + 800c210: ea4f 4a12 mov.w sl, r2, lsr #16 + 800c214: fa1f fb82 uxth.w fp, r2 + 800c218: f8de 2000 ldr.w r2, [lr] + 800c21c: ebcb 4212 rsb r2, fp, r2, lsr #16 + 800c220: eb02 4223 add.w r2, r2, r3, asr #16 + 800c224: b29b uxth r3, r3 + 800c226: ea43 4302 orr.w r3, r3, r2, lsl #16 + 800c22a: 4581 cmp r9, r0 + 800c22c: ea4f 4b22 mov.w fp, r2, asr #16 + 800c230: f84e 3b04 str.w r3, [lr], #4 + 800c234: d2db bcs.n 800c1ee + 800c236: f856 300c ldr.w r3, [r6, ip] + 800c23a: b933 cbnz r3, 800c24a + 800c23c: 9b01 ldr r3, [sp, #4] + 800c23e: 3b04 subs r3, #4 + 800c240: 429e cmp r6, r3 + 800c242: 461a mov r2, r3 + 800c244: d330 bcc.n 800c2a8 + 800c246: f8c8 4010 str.w r4, [r8, #16] + 800c24a: 4640 mov r0, r8 + 800c24c: f001 fd7e bl 800dd4c <__mcmp> + 800c250: 2800 cmp r0, #0 + 800c252: db25 blt.n 800c2a0 + 800c254: 3501 adds r5, #1 + 800c256: 4630 mov r0, r6 + 800c258: f04f 0c00 mov.w ip, #0 + 800c25c: f857 2b04 ldr.w r2, [r7], #4 + 800c260: f8d0 e000 ldr.w lr, [r0] + 800c264: b293 uxth r3, r2 + 800c266: ebac 0303 sub.w r3, ip, r3 + 800c26a: 0c12 lsrs r2, r2, #16 + 800c26c: fa13 f38e uxtah r3, r3, lr + 800c270: ebc2 421e rsb r2, r2, lr, lsr #16 + 800c274: eb02 4223 add.w r2, r2, r3, asr #16 + 800c278: b29b uxth r3, r3 + 800c27a: ea43 4302 orr.w r3, r3, r2, lsl #16 + 800c27e: 45b9 cmp r9, r7 + 800c280: ea4f 4c22 mov.w ip, r2, asr #16 + 800c284: f840 3b04 str.w r3, [r0], #4 + 800c288: d2e8 bcs.n 800c25c + 800c28a: f856 2024 ldr.w r2, [r6, r4, lsl #2] + 800c28e: eb06 0384 add.w r3, r6, r4, lsl #2 + 800c292: b92a cbnz r2, 800c2a0 + 800c294: 3b04 subs r3, #4 + 800c296: 429e cmp r6, r3 + 800c298: 461a mov r2, r3 + 800c29a: d30b bcc.n 800c2b4 + 800c29c: f8c8 4010 str.w r4, [r8, #16] + 800c2a0: 4628 mov r0, r5 + 800c2a2: b003 add sp, #12 + 800c2a4: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 800c2a8: 6812 ldr r2, [r2, #0] + 800c2aa: 3b04 subs r3, #4 + 800c2ac: 2a00 cmp r2, #0 + 800c2ae: d1ca bne.n 800c246 + 800c2b0: 3c01 subs r4, #1 + 800c2b2: e7c5 b.n 800c240 + 800c2b4: 6812 ldr r2, [r2, #0] + 800c2b6: 3b04 subs r3, #4 + 800c2b8: 2a00 cmp r2, #0 + 800c2ba: d1ef bne.n 800c29c + 800c2bc: 3c01 subs r4, #1 + 800c2be: e7ea b.n 800c296 + 800c2c0: 2000 movs r0, #0 + 800c2c2: e7ee b.n 800c2a2 + 800c2c4: 0000 movs r0, r0 + ... + +0800c2c8 <_dtoa_r>: + 800c2c8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 800c2cc: ec57 6b10 vmov r6, r7, d0 + 800c2d0: b097 sub sp, #92 ; 0x5c + 800c2d2: 6a45 ldr r5, [r0, #36] ; 0x24 + 800c2d4: 9106 str r1, [sp, #24] + 800c2d6: 4604 mov r4, r0 + 800c2d8: 920b str r2, [sp, #44] ; 0x2c + 800c2da: 9312 str r3, [sp, #72] ; 0x48 + 800c2dc: f8dd 8080 ldr.w r8, [sp, #128] ; 0x80 + 800c2e0: e9cd 6700 strd r6, r7, [sp] + 800c2e4: b93d cbnz r5, 800c2f6 <_dtoa_r+0x2e> + 800c2e6: 2010 movs r0, #16 + 800c2e8: f7fe f842 bl 800a370 + 800c2ec: 6260 str r0, [r4, #36] ; 0x24 + 800c2ee: e9c0 5501 strd r5, r5, [r0, #4] + 800c2f2: 6005 str r5, [r0, #0] + 800c2f4: 60c5 str r5, [r0, #12] + 800c2f6: 6a63 ldr r3, [r4, #36] ; 0x24 + 800c2f8: 6819 ldr r1, [r3, #0] + 800c2fa: b151 cbz r1, 800c312 <_dtoa_r+0x4a> + 800c2fc: 685a ldr r2, [r3, #4] + 800c2fe: 604a str r2, [r1, #4] + 800c300: 2301 movs r3, #1 + 800c302: 4093 lsls r3, r2 + 800c304: 608b str r3, [r1, #8] + 800c306: 4620 mov r0, r4 + 800c308: f001 fb01 bl 800d90e <_Bfree> + 800c30c: 6a63 ldr r3, [r4, #36] ; 0x24 + 800c30e: 2200 movs r2, #0 + 800c310: 601a str r2, [r3, #0] + 800c312: 1e3b subs r3, r7, #0 + 800c314: bfbb ittet lt + 800c316: f023 4300 biclt.w r3, r3, #2147483648 ; 0x80000000 + 800c31a: 9301 strlt r3, [sp, #4] + 800c31c: 2300 movge r3, #0 + 800c31e: 2201 movlt r2, #1 + 800c320: bfac ite ge + 800c322: f8c8 3000 strge.w r3, [r8] + 800c326: f8c8 2000 strlt.w r2, [r8] + 800c32a: 4baf ldr r3, [pc, #700] ; (800c5e8 <_dtoa_r+0x320>) + 800c32c: f8dd 8004 ldr.w r8, [sp, #4] + 800c330: ea33 0308 bics.w r3, r3, r8 + 800c334: d114 bne.n 800c360 <_dtoa_r+0x98> + 800c336: 9a12 ldr r2, [sp, #72] ; 0x48 + 800c338: f242 730f movw r3, #9999 ; 0x270f + 800c33c: 6013 str r3, [r2, #0] + 800c33e: 9b00 ldr r3, [sp, #0] + 800c340: b923 cbnz r3, 800c34c <_dtoa_r+0x84> + 800c342: f3c8 0013 ubfx r0, r8, #0, #20 + 800c346: 2800 cmp r0, #0 + 800c348: f000 8542 beq.w 800cdd0 <_dtoa_r+0xb08> + 800c34c: 9b21 ldr r3, [sp, #132] ; 0x84 + 800c34e: f8df b2ac ldr.w fp, [pc, #684] ; 800c5fc <_dtoa_r+0x334> + 800c352: 2b00 cmp r3, #0 + 800c354: f000 8544 beq.w 800cde0 <_dtoa_r+0xb18> + 800c358: f10b 0303 add.w r3, fp, #3 + 800c35c: f000 bd3e b.w 800cddc <_dtoa_r+0xb14> + 800c360: e9dd 6700 ldrd r6, r7, [sp] + 800c364: 2200 movs r2, #0 + 800c366: 2300 movs r3, #0 + 800c368: 4630 mov r0, r6 + 800c36a: 4639 mov r1, r7 + 800c36c: f7f4 fbb4 bl 8000ad8 <__aeabi_dcmpeq> + 800c370: 4681 mov r9, r0 + 800c372: b168 cbz r0, 800c390 <_dtoa_r+0xc8> + 800c374: 9a12 ldr r2, [sp, #72] ; 0x48 + 800c376: 2301 movs r3, #1 + 800c378: 6013 str r3, [r2, #0] + 800c37a: 9b21 ldr r3, [sp, #132] ; 0x84 + 800c37c: 2b00 cmp r3, #0 + 800c37e: f000 8524 beq.w 800cdca <_dtoa_r+0xb02> + 800c382: 4b9a ldr r3, [pc, #616] ; (800c5ec <_dtoa_r+0x324>) + 800c384: 9a21 ldr r2, [sp, #132] ; 0x84 + 800c386: f103 3bff add.w fp, r3, #4294967295 + 800c38a: 6013 str r3, [r2, #0] + 800c38c: f000 bd28 b.w 800cde0 <_dtoa_r+0xb18> + 800c390: aa14 add r2, sp, #80 ; 0x50 + 800c392: a915 add r1, sp, #84 ; 0x54 + 800c394: ec47 6b10 vmov d0, r6, r7 + 800c398: 4620 mov r0, r4 + 800c39a: f001 fdc5 bl 800df28 <__d2b> + 800c39e: f3c8 550a ubfx r5, r8, #20, #11 + 800c3a2: 9004 str r0, [sp, #16] + 800c3a4: 2d00 cmp r5, #0 + 800c3a6: d07c beq.n 800c4a2 <_dtoa_r+0x1da> + 800c3a8: f3c7 0313 ubfx r3, r7, #0, #20 + 800c3ac: f043 5b7f orr.w fp, r3, #1069547520 ; 0x3fc00000 + 800c3b0: 46b2 mov sl, r6 + 800c3b2: f44b 1b40 orr.w fp, fp, #3145728 ; 0x300000 + 800c3b6: f2a5 35ff subw r5, r5, #1023 ; 0x3ff + 800c3ba: f8cd 904c str.w r9, [sp, #76] ; 0x4c + 800c3be: 2200 movs r2, #0 + 800c3c0: 4b8b ldr r3, [pc, #556] ; (800c5f0 <_dtoa_r+0x328>) + 800c3c2: 4650 mov r0, sl + 800c3c4: 4659 mov r1, fp + 800c3c6: f7f3 ff67 bl 8000298 <__aeabi_dsub> + 800c3ca: a381 add r3, pc, #516 ; (adr r3, 800c5d0 <_dtoa_r+0x308>) + 800c3cc: e9d3 2300 ldrd r2, r3, [r3] + 800c3d0: f7f4 f91a bl 8000608 <__aeabi_dmul> + 800c3d4: a380 add r3, pc, #512 ; (adr r3, 800c5d8 <_dtoa_r+0x310>) + 800c3d6: e9d3 2300 ldrd r2, r3, [r3] + 800c3da: f7f3 ff5f bl 800029c <__adddf3> + 800c3de: 4606 mov r6, r0 + 800c3e0: 4628 mov r0, r5 + 800c3e2: 460f mov r7, r1 + 800c3e4: f7f4 f8a6 bl 8000534 <__aeabi_i2d> + 800c3e8: a37d add r3, pc, #500 ; (adr r3, 800c5e0 <_dtoa_r+0x318>) + 800c3ea: e9d3 2300 ldrd r2, r3, [r3] + 800c3ee: f7f4 f90b bl 8000608 <__aeabi_dmul> + 800c3f2: 4602 mov r2, r0 + 800c3f4: 460b mov r3, r1 + 800c3f6: 4630 mov r0, r6 + 800c3f8: 4639 mov r1, r7 + 800c3fa: f7f3 ff4f bl 800029c <__adddf3> + 800c3fe: 4606 mov r6, r0 + 800c400: 460f mov r7, r1 + 800c402: f7f4 fbb1 bl 8000b68 <__aeabi_d2iz> + 800c406: 2200 movs r2, #0 + 800c408: 4682 mov sl, r0 + 800c40a: 2300 movs r3, #0 + 800c40c: 4630 mov r0, r6 + 800c40e: 4639 mov r1, r7 + 800c410: f7f4 fb6c bl 8000aec <__aeabi_dcmplt> + 800c414: b148 cbz r0, 800c42a <_dtoa_r+0x162> + 800c416: 4650 mov r0, sl + 800c418: f7f4 f88c bl 8000534 <__aeabi_i2d> + 800c41c: 4632 mov r2, r6 + 800c41e: 463b mov r3, r7 + 800c420: f7f4 fb5a bl 8000ad8 <__aeabi_dcmpeq> + 800c424: b908 cbnz r0, 800c42a <_dtoa_r+0x162> + 800c426: f10a 3aff add.w sl, sl, #4294967295 + 800c42a: f1ba 0f16 cmp.w sl, #22 + 800c42e: d859 bhi.n 800c4e4 <_dtoa_r+0x21c> + 800c430: 4970 ldr r1, [pc, #448] ; (800c5f4 <_dtoa_r+0x32c>) + 800c432: eb01 01ca add.w r1, r1, sl, lsl #3 + 800c436: e9dd 2300 ldrd r2, r3, [sp] + 800c43a: e9d1 0100 ldrd r0, r1, [r1] + 800c43e: f7f4 fb73 bl 8000b28 <__aeabi_dcmpgt> + 800c442: 2800 cmp r0, #0 + 800c444: d050 beq.n 800c4e8 <_dtoa_r+0x220> + 800c446: f10a 3aff add.w sl, sl, #4294967295 + 800c44a: 2300 movs r3, #0 + 800c44c: 930f str r3, [sp, #60] ; 0x3c + 800c44e: 9b14 ldr r3, [sp, #80] ; 0x50 + 800c450: 1b5d subs r5, r3, r5 + 800c452: f1b5 0801 subs.w r8, r5, #1 + 800c456: bf49 itett mi + 800c458: f1c5 0301 rsbmi r3, r5, #1 + 800c45c: 2300 movpl r3, #0 + 800c45e: 9305 strmi r3, [sp, #20] + 800c460: f04f 0800 movmi.w r8, #0 + 800c464: bf58 it pl + 800c466: 9305 strpl r3, [sp, #20] + 800c468: f1ba 0f00 cmp.w sl, #0 + 800c46c: db3e blt.n 800c4ec <_dtoa_r+0x224> + 800c46e: 2300 movs r3, #0 + 800c470: 44d0 add r8, sl + 800c472: f8cd a038 str.w sl, [sp, #56] ; 0x38 + 800c476: 9307 str r3, [sp, #28] + 800c478: 9b06 ldr r3, [sp, #24] + 800c47a: 2b09 cmp r3, #9 + 800c47c: f200 8090 bhi.w 800c5a0 <_dtoa_r+0x2d8> + 800c480: 2b05 cmp r3, #5 + 800c482: bfc4 itt gt + 800c484: 3b04 subgt r3, #4 + 800c486: 9306 strgt r3, [sp, #24] + 800c488: 9b06 ldr r3, [sp, #24] + 800c48a: f1a3 0302 sub.w r3, r3, #2 + 800c48e: bfcc ite gt + 800c490: 2500 movgt r5, #0 + 800c492: 2501 movle r5, #1 + 800c494: 2b03 cmp r3, #3 + 800c496: f200 808f bhi.w 800c5b8 <_dtoa_r+0x2f0> + 800c49a: e8df f003 tbb [pc, r3] + 800c49e: 7f7d .short 0x7f7d + 800c4a0: 7131 .short 0x7131 + 800c4a2: e9dd 5314 ldrd r5, r3, [sp, #80] ; 0x50 + 800c4a6: 441d add r5, r3 + 800c4a8: f205 4032 addw r0, r5, #1074 ; 0x432 + 800c4ac: 2820 cmp r0, #32 + 800c4ae: dd13 ble.n 800c4d8 <_dtoa_r+0x210> + 800c4b0: f1c0 0040 rsb r0, r0, #64 ; 0x40 + 800c4b4: 9b00 ldr r3, [sp, #0] + 800c4b6: fa08 f800 lsl.w r8, r8, r0 + 800c4ba: f205 4012 addw r0, r5, #1042 ; 0x412 + 800c4be: fa23 f000 lsr.w r0, r3, r0 + 800c4c2: ea48 0000 orr.w r0, r8, r0 + 800c4c6: f7f4 f825 bl 8000514 <__aeabi_ui2d> + 800c4ca: 2301 movs r3, #1 + 800c4cc: 4682 mov sl, r0 + 800c4ce: f1a1 7bf8 sub.w fp, r1, #32505856 ; 0x1f00000 + 800c4d2: 3d01 subs r5, #1 + 800c4d4: 9313 str r3, [sp, #76] ; 0x4c + 800c4d6: e772 b.n 800c3be <_dtoa_r+0xf6> + 800c4d8: 9b00 ldr r3, [sp, #0] + 800c4da: f1c0 0020 rsb r0, r0, #32 + 800c4de: fa03 f000 lsl.w r0, r3, r0 + 800c4e2: e7f0 b.n 800c4c6 <_dtoa_r+0x1fe> + 800c4e4: 2301 movs r3, #1 + 800c4e6: e7b1 b.n 800c44c <_dtoa_r+0x184> + 800c4e8: 900f str r0, [sp, #60] ; 0x3c + 800c4ea: e7b0 b.n 800c44e <_dtoa_r+0x186> + 800c4ec: 9b05 ldr r3, [sp, #20] + 800c4ee: eba3 030a sub.w r3, r3, sl + 800c4f2: 9305 str r3, [sp, #20] + 800c4f4: f1ca 0300 rsb r3, sl, #0 + 800c4f8: 9307 str r3, [sp, #28] + 800c4fa: 2300 movs r3, #0 + 800c4fc: 930e str r3, [sp, #56] ; 0x38 + 800c4fe: e7bb b.n 800c478 <_dtoa_r+0x1b0> + 800c500: 2301 movs r3, #1 + 800c502: 930a str r3, [sp, #40] ; 0x28 + 800c504: 9b0b ldr r3, [sp, #44] ; 0x2c + 800c506: 2b00 cmp r3, #0 + 800c508: dd59 ble.n 800c5be <_dtoa_r+0x2f6> + 800c50a: 9302 str r3, [sp, #8] + 800c50c: 4699 mov r9, r3 + 800c50e: 6a66 ldr r6, [r4, #36] ; 0x24 + 800c510: 2200 movs r2, #0 + 800c512: 6072 str r2, [r6, #4] + 800c514: 2204 movs r2, #4 + 800c516: f102 0014 add.w r0, r2, #20 + 800c51a: 4298 cmp r0, r3 + 800c51c: 6871 ldr r1, [r6, #4] + 800c51e: d953 bls.n 800c5c8 <_dtoa_r+0x300> + 800c520: 4620 mov r0, r4 + 800c522: f001 f9c0 bl 800d8a6 <_Balloc> + 800c526: 6a63 ldr r3, [r4, #36] ; 0x24 + 800c528: 6030 str r0, [r6, #0] + 800c52a: f1b9 0f0e cmp.w r9, #14 + 800c52e: f8d3 b000 ldr.w fp, [r3] + 800c532: f200 80e6 bhi.w 800c702 <_dtoa_r+0x43a> + 800c536: 2d00 cmp r5, #0 + 800c538: f000 80e3 beq.w 800c702 <_dtoa_r+0x43a> + 800c53c: ed9d 7b00 vldr d7, [sp] + 800c540: f1ba 0f00 cmp.w sl, #0 + 800c544: ed8d 7b10 vstr d7, [sp, #64] ; 0x40 + 800c548: dd74 ble.n 800c634 <_dtoa_r+0x36c> + 800c54a: 4a2a ldr r2, [pc, #168] ; (800c5f4 <_dtoa_r+0x32c>) + 800c54c: f00a 030f and.w r3, sl, #15 + 800c550: eb02 03c3 add.w r3, r2, r3, lsl #3 + 800c554: ed93 7b00 vldr d7, [r3] + 800c558: ea4f 162a mov.w r6, sl, asr #4 + 800c55c: 06f0 lsls r0, r6, #27 + 800c55e: ed8d 7b08 vstr d7, [sp, #32] + 800c562: d565 bpl.n 800c630 <_dtoa_r+0x368> + 800c564: 4b24 ldr r3, [pc, #144] ; (800c5f8 <_dtoa_r+0x330>) + 800c566: e9dd 0110 ldrd r0, r1, [sp, #64] ; 0x40 + 800c56a: e9d3 2308 ldrd r2, r3, [r3, #32] + 800c56e: f7f4 f975 bl 800085c <__aeabi_ddiv> + 800c572: e9cd 0100 strd r0, r1, [sp] + 800c576: f006 060f and.w r6, r6, #15 + 800c57a: 2503 movs r5, #3 + 800c57c: 4f1e ldr r7, [pc, #120] ; (800c5f8 <_dtoa_r+0x330>) + 800c57e: e04c b.n 800c61a <_dtoa_r+0x352> + 800c580: 2301 movs r3, #1 + 800c582: 930a str r3, [sp, #40] ; 0x28 + 800c584: 9b0b ldr r3, [sp, #44] ; 0x2c + 800c586: 4453 add r3, sl + 800c588: f103 0901 add.w r9, r3, #1 + 800c58c: 9302 str r3, [sp, #8] + 800c58e: 464b mov r3, r9 + 800c590: 2b01 cmp r3, #1 + 800c592: bfb8 it lt + 800c594: 2301 movlt r3, #1 + 800c596: e7ba b.n 800c50e <_dtoa_r+0x246> + 800c598: 2300 movs r3, #0 + 800c59a: e7b2 b.n 800c502 <_dtoa_r+0x23a> + 800c59c: 2300 movs r3, #0 + 800c59e: e7f0 b.n 800c582 <_dtoa_r+0x2ba> + 800c5a0: 2501 movs r5, #1 + 800c5a2: 2300 movs r3, #0 + 800c5a4: 9306 str r3, [sp, #24] + 800c5a6: 950a str r5, [sp, #40] ; 0x28 + 800c5a8: f04f 33ff mov.w r3, #4294967295 + 800c5ac: 9302 str r3, [sp, #8] + 800c5ae: 4699 mov r9, r3 + 800c5b0: 2200 movs r2, #0 + 800c5b2: 2312 movs r3, #18 + 800c5b4: 920b str r2, [sp, #44] ; 0x2c + 800c5b6: e7aa b.n 800c50e <_dtoa_r+0x246> + 800c5b8: 2301 movs r3, #1 + 800c5ba: 930a str r3, [sp, #40] ; 0x28 + 800c5bc: e7f4 b.n 800c5a8 <_dtoa_r+0x2e0> + 800c5be: 2301 movs r3, #1 + 800c5c0: 9302 str r3, [sp, #8] + 800c5c2: 4699 mov r9, r3 + 800c5c4: 461a mov r2, r3 + 800c5c6: e7f5 b.n 800c5b4 <_dtoa_r+0x2ec> + 800c5c8: 3101 adds r1, #1 + 800c5ca: 6071 str r1, [r6, #4] + 800c5cc: 0052 lsls r2, r2, #1 + 800c5ce: e7a2 b.n 800c516 <_dtoa_r+0x24e> + 800c5d0: 636f4361 .word 0x636f4361 + 800c5d4: 3fd287a7 .word 0x3fd287a7 + 800c5d8: 8b60c8b3 .word 0x8b60c8b3 + 800c5dc: 3fc68a28 .word 0x3fc68a28 + 800c5e0: 509f79fb .word 0x509f79fb + 800c5e4: 3fd34413 .word 0x3fd34413 + 800c5e8: 7ff00000 .word 0x7ff00000 + 800c5ec: 0800e949 .word 0x0800e949 + 800c5f0: 3ff80000 .word 0x3ff80000 + 800c5f4: 0800ea70 .word 0x0800ea70 + 800c5f8: 0800ea48 .word 0x0800ea48 + 800c5fc: 0800e9d1 .word 0x0800e9d1 + 800c600: 07f1 lsls r1, r6, #31 + 800c602: d508 bpl.n 800c616 <_dtoa_r+0x34e> + 800c604: e9dd 0108 ldrd r0, r1, [sp, #32] + 800c608: e9d7 2300 ldrd r2, r3, [r7] + 800c60c: f7f3 fffc bl 8000608 <__aeabi_dmul> + 800c610: e9cd 0108 strd r0, r1, [sp, #32] + 800c614: 3501 adds r5, #1 + 800c616: 1076 asrs r6, r6, #1 + 800c618: 3708 adds r7, #8 + 800c61a: 2e00 cmp r6, #0 + 800c61c: d1f0 bne.n 800c600 <_dtoa_r+0x338> + 800c61e: e9dd 2308 ldrd r2, r3, [sp, #32] + 800c622: e9dd 0100 ldrd r0, r1, [sp] + 800c626: f7f4 f919 bl 800085c <__aeabi_ddiv> + 800c62a: e9cd 0100 strd r0, r1, [sp] + 800c62e: e01a b.n 800c666 <_dtoa_r+0x39e> + 800c630: 2502 movs r5, #2 + 800c632: e7a3 b.n 800c57c <_dtoa_r+0x2b4> + 800c634: f000 80a0 beq.w 800c778 <_dtoa_r+0x4b0> + 800c638: f1ca 0600 rsb r6, sl, #0 + 800c63c: 4b9f ldr r3, [pc, #636] ; (800c8bc <_dtoa_r+0x5f4>) + 800c63e: 4fa0 ldr r7, [pc, #640] ; (800c8c0 <_dtoa_r+0x5f8>) + 800c640: f006 020f and.w r2, r6, #15 + 800c644: eb03 03c2 add.w r3, r3, r2, lsl #3 + 800c648: e9d3 2300 ldrd r2, r3, [r3] + 800c64c: e9dd 0110 ldrd r0, r1, [sp, #64] ; 0x40 + 800c650: f7f3 ffda bl 8000608 <__aeabi_dmul> + 800c654: e9cd 0100 strd r0, r1, [sp] + 800c658: 1136 asrs r6, r6, #4 + 800c65a: 2300 movs r3, #0 + 800c65c: 2502 movs r5, #2 + 800c65e: 2e00 cmp r6, #0 + 800c660: d17f bne.n 800c762 <_dtoa_r+0x49a> + 800c662: 2b00 cmp r3, #0 + 800c664: d1e1 bne.n 800c62a <_dtoa_r+0x362> + 800c666: 9b0f ldr r3, [sp, #60] ; 0x3c + 800c668: 2b00 cmp r3, #0 + 800c66a: f000 8087 beq.w 800c77c <_dtoa_r+0x4b4> + 800c66e: e9dd 6700 ldrd r6, r7, [sp] + 800c672: 2200 movs r2, #0 + 800c674: 4b93 ldr r3, [pc, #588] ; (800c8c4 <_dtoa_r+0x5fc>) + 800c676: 4630 mov r0, r6 + 800c678: 4639 mov r1, r7 + 800c67a: f7f4 fa37 bl 8000aec <__aeabi_dcmplt> + 800c67e: 2800 cmp r0, #0 + 800c680: d07c beq.n 800c77c <_dtoa_r+0x4b4> + 800c682: f1b9 0f00 cmp.w r9, #0 + 800c686: d079 beq.n 800c77c <_dtoa_r+0x4b4> + 800c688: 9b02 ldr r3, [sp, #8] + 800c68a: 2b00 cmp r3, #0 + 800c68c: dd35 ble.n 800c6fa <_dtoa_r+0x432> + 800c68e: f10a 33ff add.w r3, sl, #4294967295 + 800c692: 9308 str r3, [sp, #32] + 800c694: 4639 mov r1, r7 + 800c696: 2200 movs r2, #0 + 800c698: 4b8b ldr r3, [pc, #556] ; (800c8c8 <_dtoa_r+0x600>) + 800c69a: 4630 mov r0, r6 + 800c69c: f7f3 ffb4 bl 8000608 <__aeabi_dmul> + 800c6a0: e9cd 0100 strd r0, r1, [sp] + 800c6a4: 9f02 ldr r7, [sp, #8] + 800c6a6: 3501 adds r5, #1 + 800c6a8: 4628 mov r0, r5 + 800c6aa: f7f3 ff43 bl 8000534 <__aeabi_i2d> + 800c6ae: e9dd 2300 ldrd r2, r3, [sp] + 800c6b2: f7f3 ffa9 bl 8000608 <__aeabi_dmul> + 800c6b6: 2200 movs r2, #0 + 800c6b8: 4b84 ldr r3, [pc, #528] ; (800c8cc <_dtoa_r+0x604>) + 800c6ba: f7f3 fdef bl 800029c <__adddf3> + 800c6be: 4605 mov r5, r0 + 800c6c0: f1a1 7650 sub.w r6, r1, #54525952 ; 0x3400000 + 800c6c4: 2f00 cmp r7, #0 + 800c6c6: d15d bne.n 800c784 <_dtoa_r+0x4bc> + 800c6c8: 2200 movs r2, #0 + 800c6ca: 4b81 ldr r3, [pc, #516] ; (800c8d0 <_dtoa_r+0x608>) + 800c6cc: e9dd 0100 ldrd r0, r1, [sp] + 800c6d0: f7f3 fde2 bl 8000298 <__aeabi_dsub> + 800c6d4: 462a mov r2, r5 + 800c6d6: 4633 mov r3, r6 + 800c6d8: e9cd 0100 strd r0, r1, [sp] + 800c6dc: f7f4 fa24 bl 8000b28 <__aeabi_dcmpgt> + 800c6e0: 2800 cmp r0, #0 + 800c6e2: f040 8288 bne.w 800cbf6 <_dtoa_r+0x92e> + 800c6e6: 462a mov r2, r5 + 800c6e8: f106 4300 add.w r3, r6, #2147483648 ; 0x80000000 + 800c6ec: e9dd 0100 ldrd r0, r1, [sp] + 800c6f0: f7f4 f9fc bl 8000aec <__aeabi_dcmplt> + 800c6f4: 2800 cmp r0, #0 + 800c6f6: f040 827c bne.w 800cbf2 <_dtoa_r+0x92a> + 800c6fa: e9dd 2310 ldrd r2, r3, [sp, #64] ; 0x40 + 800c6fe: e9cd 2300 strd r2, r3, [sp] + 800c702: 9b15 ldr r3, [sp, #84] ; 0x54 + 800c704: 2b00 cmp r3, #0 + 800c706: f2c0 8150 blt.w 800c9aa <_dtoa_r+0x6e2> + 800c70a: f1ba 0f0e cmp.w sl, #14 + 800c70e: f300 814c bgt.w 800c9aa <_dtoa_r+0x6e2> + 800c712: 4b6a ldr r3, [pc, #424] ; (800c8bc <_dtoa_r+0x5f4>) + 800c714: eb03 03ca add.w r3, r3, sl, lsl #3 + 800c718: ed93 7b00 vldr d7, [r3] + 800c71c: 9b0b ldr r3, [sp, #44] ; 0x2c + 800c71e: 2b00 cmp r3, #0 + 800c720: ed8d 7b02 vstr d7, [sp, #8] + 800c724: f280 80d8 bge.w 800c8d8 <_dtoa_r+0x610> + 800c728: f1b9 0f00 cmp.w r9, #0 + 800c72c: f300 80d4 bgt.w 800c8d8 <_dtoa_r+0x610> + 800c730: f040 825e bne.w 800cbf0 <_dtoa_r+0x928> + 800c734: 2200 movs r2, #0 + 800c736: 4b66 ldr r3, [pc, #408] ; (800c8d0 <_dtoa_r+0x608>) + 800c738: ec51 0b17 vmov r0, r1, d7 + 800c73c: f7f3 ff64 bl 8000608 <__aeabi_dmul> + 800c740: e9dd 2300 ldrd r2, r3, [sp] + 800c744: f7f4 f9e6 bl 8000b14 <__aeabi_dcmpge> + 800c748: 464f mov r7, r9 + 800c74a: 464e mov r6, r9 + 800c74c: 2800 cmp r0, #0 + 800c74e: f040 8234 bne.w 800cbba <_dtoa_r+0x8f2> + 800c752: 2331 movs r3, #49 ; 0x31 + 800c754: f10b 0501 add.w r5, fp, #1 + 800c758: f88b 3000 strb.w r3, [fp] + 800c75c: f10a 0a01 add.w sl, sl, #1 + 800c760: e22f b.n 800cbc2 <_dtoa_r+0x8fa> + 800c762: 07f2 lsls r2, r6, #31 + 800c764: d505 bpl.n 800c772 <_dtoa_r+0x4aa> + 800c766: e9d7 2300 ldrd r2, r3, [r7] + 800c76a: f7f3 ff4d bl 8000608 <__aeabi_dmul> + 800c76e: 3501 adds r5, #1 + 800c770: 2301 movs r3, #1 + 800c772: 1076 asrs r6, r6, #1 + 800c774: 3708 adds r7, #8 + 800c776: e772 b.n 800c65e <_dtoa_r+0x396> + 800c778: 2502 movs r5, #2 + 800c77a: e774 b.n 800c666 <_dtoa_r+0x39e> + 800c77c: f8cd a020 str.w sl, [sp, #32] + 800c780: 464f mov r7, r9 + 800c782: e791 b.n 800c6a8 <_dtoa_r+0x3e0> + 800c784: 4b4d ldr r3, [pc, #308] ; (800c8bc <_dtoa_r+0x5f4>) + 800c786: eb03 03c7 add.w r3, r3, r7, lsl #3 + 800c78a: e953 0102 ldrd r0, r1, [r3, #-8] + 800c78e: 9b0a ldr r3, [sp, #40] ; 0x28 + 800c790: 2b00 cmp r3, #0 + 800c792: d047 beq.n 800c824 <_dtoa_r+0x55c> + 800c794: 4602 mov r2, r0 + 800c796: 460b mov r3, r1 + 800c798: 2000 movs r0, #0 + 800c79a: 494e ldr r1, [pc, #312] ; (800c8d4 <_dtoa_r+0x60c>) + 800c79c: f7f4 f85e bl 800085c <__aeabi_ddiv> + 800c7a0: 462a mov r2, r5 + 800c7a2: 4633 mov r3, r6 + 800c7a4: f7f3 fd78 bl 8000298 <__aeabi_dsub> + 800c7a8: e9cd 010c strd r0, r1, [sp, #48] ; 0x30 + 800c7ac: 465d mov r5, fp + 800c7ae: e9dd 0100 ldrd r0, r1, [sp] + 800c7b2: f7f4 f9d9 bl 8000b68 <__aeabi_d2iz> + 800c7b6: 4606 mov r6, r0 + 800c7b8: f7f3 febc bl 8000534 <__aeabi_i2d> + 800c7bc: 4602 mov r2, r0 + 800c7be: 460b mov r3, r1 + 800c7c0: e9dd 0100 ldrd r0, r1, [sp] + 800c7c4: f7f3 fd68 bl 8000298 <__aeabi_dsub> + 800c7c8: 3630 adds r6, #48 ; 0x30 + 800c7ca: f805 6b01 strb.w r6, [r5], #1 + 800c7ce: e9dd 230c ldrd r2, r3, [sp, #48] ; 0x30 + 800c7d2: e9cd 0100 strd r0, r1, [sp] + 800c7d6: f7f4 f989 bl 8000aec <__aeabi_dcmplt> + 800c7da: 2800 cmp r0, #0 + 800c7dc: d163 bne.n 800c8a6 <_dtoa_r+0x5de> + 800c7de: e9dd 2300 ldrd r2, r3, [sp] + 800c7e2: 2000 movs r0, #0 + 800c7e4: 4937 ldr r1, [pc, #220] ; (800c8c4 <_dtoa_r+0x5fc>) + 800c7e6: f7f3 fd57 bl 8000298 <__aeabi_dsub> + 800c7ea: e9dd 230c ldrd r2, r3, [sp, #48] ; 0x30 + 800c7ee: f7f4 f97d bl 8000aec <__aeabi_dcmplt> + 800c7f2: 2800 cmp r0, #0 + 800c7f4: f040 80b7 bne.w 800c966 <_dtoa_r+0x69e> + 800c7f8: eba5 030b sub.w r3, r5, fp + 800c7fc: 429f cmp r7, r3 + 800c7fe: f77f af7c ble.w 800c6fa <_dtoa_r+0x432> + 800c802: 2200 movs r2, #0 + 800c804: 4b30 ldr r3, [pc, #192] ; (800c8c8 <_dtoa_r+0x600>) + 800c806: e9dd 010c ldrd r0, r1, [sp, #48] ; 0x30 + 800c80a: f7f3 fefd bl 8000608 <__aeabi_dmul> + 800c80e: 2200 movs r2, #0 + 800c810: e9cd 010c strd r0, r1, [sp, #48] ; 0x30 + 800c814: 4b2c ldr r3, [pc, #176] ; (800c8c8 <_dtoa_r+0x600>) + 800c816: e9dd 0100 ldrd r0, r1, [sp] + 800c81a: f7f3 fef5 bl 8000608 <__aeabi_dmul> + 800c81e: e9cd 0100 strd r0, r1, [sp] + 800c822: e7c4 b.n 800c7ae <_dtoa_r+0x4e6> + 800c824: 462a mov r2, r5 + 800c826: 4633 mov r3, r6 + 800c828: f7f3 feee bl 8000608 <__aeabi_dmul> + 800c82c: e9cd 010c strd r0, r1, [sp, #48] ; 0x30 + 800c830: eb0b 0507 add.w r5, fp, r7 + 800c834: 465e mov r6, fp + 800c836: e9dd 0100 ldrd r0, r1, [sp] + 800c83a: f7f4 f995 bl 8000b68 <__aeabi_d2iz> + 800c83e: 4607 mov r7, r0 + 800c840: f7f3 fe78 bl 8000534 <__aeabi_i2d> + 800c844: 3730 adds r7, #48 ; 0x30 + 800c846: 4602 mov r2, r0 + 800c848: 460b mov r3, r1 + 800c84a: e9dd 0100 ldrd r0, r1, [sp] + 800c84e: f7f3 fd23 bl 8000298 <__aeabi_dsub> + 800c852: f806 7b01 strb.w r7, [r6], #1 + 800c856: 42ae cmp r6, r5 + 800c858: e9cd 0100 strd r0, r1, [sp] + 800c85c: f04f 0200 mov.w r2, #0 + 800c860: d126 bne.n 800c8b0 <_dtoa_r+0x5e8> + 800c862: 4b1c ldr r3, [pc, #112] ; (800c8d4 <_dtoa_r+0x60c>) + 800c864: e9dd 010c ldrd r0, r1, [sp, #48] ; 0x30 + 800c868: f7f3 fd18 bl 800029c <__adddf3> + 800c86c: 4602 mov r2, r0 + 800c86e: 460b mov r3, r1 + 800c870: e9dd 0100 ldrd r0, r1, [sp] + 800c874: f7f4 f958 bl 8000b28 <__aeabi_dcmpgt> + 800c878: 2800 cmp r0, #0 + 800c87a: d174 bne.n 800c966 <_dtoa_r+0x69e> + 800c87c: e9dd 230c ldrd r2, r3, [sp, #48] ; 0x30 + 800c880: 2000 movs r0, #0 + 800c882: 4914 ldr r1, [pc, #80] ; (800c8d4 <_dtoa_r+0x60c>) + 800c884: f7f3 fd08 bl 8000298 <__aeabi_dsub> + 800c888: 4602 mov r2, r0 + 800c88a: 460b mov r3, r1 + 800c88c: e9dd 0100 ldrd r0, r1, [sp] + 800c890: f7f4 f92c bl 8000aec <__aeabi_dcmplt> + 800c894: 2800 cmp r0, #0 + 800c896: f43f af30 beq.w 800c6fa <_dtoa_r+0x432> + 800c89a: f815 3c01 ldrb.w r3, [r5, #-1] + 800c89e: 2b30 cmp r3, #48 ; 0x30 + 800c8a0: f105 32ff add.w r2, r5, #4294967295 + 800c8a4: d002 beq.n 800c8ac <_dtoa_r+0x5e4> + 800c8a6: f8dd a020 ldr.w sl, [sp, #32] + 800c8aa: e04a b.n 800c942 <_dtoa_r+0x67a> + 800c8ac: 4615 mov r5, r2 + 800c8ae: e7f4 b.n 800c89a <_dtoa_r+0x5d2> + 800c8b0: 4b05 ldr r3, [pc, #20] ; (800c8c8 <_dtoa_r+0x600>) + 800c8b2: f7f3 fea9 bl 8000608 <__aeabi_dmul> + 800c8b6: e9cd 0100 strd r0, r1, [sp] + 800c8ba: e7bc b.n 800c836 <_dtoa_r+0x56e> + 800c8bc: 0800ea70 .word 0x0800ea70 + 800c8c0: 0800ea48 .word 0x0800ea48 + 800c8c4: 3ff00000 .word 0x3ff00000 + 800c8c8: 40240000 .word 0x40240000 + 800c8cc: 401c0000 .word 0x401c0000 + 800c8d0: 40140000 .word 0x40140000 + 800c8d4: 3fe00000 .word 0x3fe00000 + 800c8d8: e9dd 6700 ldrd r6, r7, [sp] + 800c8dc: 465d mov r5, fp + 800c8de: e9dd 2302 ldrd r2, r3, [sp, #8] + 800c8e2: 4630 mov r0, r6 + 800c8e4: 4639 mov r1, r7 + 800c8e6: f7f3 ffb9 bl 800085c <__aeabi_ddiv> + 800c8ea: f7f4 f93d bl 8000b68 <__aeabi_d2iz> + 800c8ee: 4680 mov r8, r0 + 800c8f0: f7f3 fe20 bl 8000534 <__aeabi_i2d> + 800c8f4: e9dd 2302 ldrd r2, r3, [sp, #8] + 800c8f8: f7f3 fe86 bl 8000608 <__aeabi_dmul> + 800c8fc: 4602 mov r2, r0 + 800c8fe: 460b mov r3, r1 + 800c900: 4630 mov r0, r6 + 800c902: 4639 mov r1, r7 + 800c904: f108 0630 add.w r6, r8, #48 ; 0x30 + 800c908: f7f3 fcc6 bl 8000298 <__aeabi_dsub> + 800c90c: f805 6b01 strb.w r6, [r5], #1 + 800c910: eba5 060b sub.w r6, r5, fp + 800c914: 45b1 cmp r9, r6 + 800c916: 4602 mov r2, r0 + 800c918: 460b mov r3, r1 + 800c91a: d139 bne.n 800c990 <_dtoa_r+0x6c8> + 800c91c: f7f3 fcbe bl 800029c <__adddf3> + 800c920: e9dd 2302 ldrd r2, r3, [sp, #8] + 800c924: 4606 mov r6, r0 + 800c926: 460f mov r7, r1 + 800c928: f7f4 f8fe bl 8000b28 <__aeabi_dcmpgt> + 800c92c: b9c8 cbnz r0, 800c962 <_dtoa_r+0x69a> + 800c92e: e9dd 2302 ldrd r2, r3, [sp, #8] + 800c932: 4630 mov r0, r6 + 800c934: 4639 mov r1, r7 + 800c936: f7f4 f8cf bl 8000ad8 <__aeabi_dcmpeq> + 800c93a: b110 cbz r0, 800c942 <_dtoa_r+0x67a> + 800c93c: f018 0f01 tst.w r8, #1 + 800c940: d10f bne.n 800c962 <_dtoa_r+0x69a> + 800c942: 9904 ldr r1, [sp, #16] + 800c944: 4620 mov r0, r4 + 800c946: f000 ffe2 bl 800d90e <_Bfree> + 800c94a: 2300 movs r3, #0 + 800c94c: 9a12 ldr r2, [sp, #72] ; 0x48 + 800c94e: 702b strb r3, [r5, #0] + 800c950: f10a 0301 add.w r3, sl, #1 + 800c954: 6013 str r3, [r2, #0] + 800c956: 9b21 ldr r3, [sp, #132] ; 0x84 + 800c958: 2b00 cmp r3, #0 + 800c95a: f000 8241 beq.w 800cde0 <_dtoa_r+0xb18> + 800c95e: 601d str r5, [r3, #0] + 800c960: e23e b.n 800cde0 <_dtoa_r+0xb18> + 800c962: f8cd a020 str.w sl, [sp, #32] + 800c966: f815 2c01 ldrb.w r2, [r5, #-1] + 800c96a: 2a39 cmp r2, #57 ; 0x39 + 800c96c: f105 33ff add.w r3, r5, #4294967295 + 800c970: d108 bne.n 800c984 <_dtoa_r+0x6bc> + 800c972: 459b cmp fp, r3 + 800c974: d10a bne.n 800c98c <_dtoa_r+0x6c4> + 800c976: 9b08 ldr r3, [sp, #32] + 800c978: 3301 adds r3, #1 + 800c97a: 9308 str r3, [sp, #32] + 800c97c: 2330 movs r3, #48 ; 0x30 + 800c97e: f88b 3000 strb.w r3, [fp] + 800c982: 465b mov r3, fp + 800c984: 781a ldrb r2, [r3, #0] + 800c986: 3201 adds r2, #1 + 800c988: 701a strb r2, [r3, #0] + 800c98a: e78c b.n 800c8a6 <_dtoa_r+0x5de> + 800c98c: 461d mov r5, r3 + 800c98e: e7ea b.n 800c966 <_dtoa_r+0x69e> + 800c990: 2200 movs r2, #0 + 800c992: 4b9b ldr r3, [pc, #620] ; (800cc00 <_dtoa_r+0x938>) + 800c994: f7f3 fe38 bl 8000608 <__aeabi_dmul> + 800c998: 2200 movs r2, #0 + 800c99a: 2300 movs r3, #0 + 800c99c: 4606 mov r6, r0 + 800c99e: 460f mov r7, r1 + 800c9a0: f7f4 f89a bl 8000ad8 <__aeabi_dcmpeq> + 800c9a4: 2800 cmp r0, #0 + 800c9a6: d09a beq.n 800c8de <_dtoa_r+0x616> + 800c9a8: e7cb b.n 800c942 <_dtoa_r+0x67a> + 800c9aa: 9a0a ldr r2, [sp, #40] ; 0x28 + 800c9ac: 2a00 cmp r2, #0 + 800c9ae: f000 808b beq.w 800cac8 <_dtoa_r+0x800> + 800c9b2: 9a06 ldr r2, [sp, #24] + 800c9b4: 2a01 cmp r2, #1 + 800c9b6: dc6e bgt.n 800ca96 <_dtoa_r+0x7ce> + 800c9b8: 9a13 ldr r2, [sp, #76] ; 0x4c + 800c9ba: 2a00 cmp r2, #0 + 800c9bc: d067 beq.n 800ca8e <_dtoa_r+0x7c6> + 800c9be: f203 4333 addw r3, r3, #1075 ; 0x433 + 800c9c2: 9f07 ldr r7, [sp, #28] + 800c9c4: 9d05 ldr r5, [sp, #20] + 800c9c6: 9a05 ldr r2, [sp, #20] + 800c9c8: 2101 movs r1, #1 + 800c9ca: 441a add r2, r3 + 800c9cc: 4620 mov r0, r4 + 800c9ce: 9205 str r2, [sp, #20] + 800c9d0: 4498 add r8, r3 + 800c9d2: f001 f87a bl 800daca <__i2b> + 800c9d6: 4606 mov r6, r0 + 800c9d8: 2d00 cmp r5, #0 + 800c9da: dd0c ble.n 800c9f6 <_dtoa_r+0x72e> + 800c9dc: f1b8 0f00 cmp.w r8, #0 + 800c9e0: dd09 ble.n 800c9f6 <_dtoa_r+0x72e> + 800c9e2: 4545 cmp r5, r8 + 800c9e4: 9a05 ldr r2, [sp, #20] + 800c9e6: 462b mov r3, r5 + 800c9e8: bfa8 it ge + 800c9ea: 4643 movge r3, r8 + 800c9ec: 1ad2 subs r2, r2, r3 + 800c9ee: 9205 str r2, [sp, #20] + 800c9f0: 1aed subs r5, r5, r3 + 800c9f2: eba8 0803 sub.w r8, r8, r3 + 800c9f6: 9b07 ldr r3, [sp, #28] + 800c9f8: b1eb cbz r3, 800ca36 <_dtoa_r+0x76e> + 800c9fa: 9b0a ldr r3, [sp, #40] ; 0x28 + 800c9fc: 2b00 cmp r3, #0 + 800c9fe: d067 beq.n 800cad0 <_dtoa_r+0x808> + 800ca00: b18f cbz r7, 800ca26 <_dtoa_r+0x75e> + 800ca02: 4631 mov r1, r6 + 800ca04: 463a mov r2, r7 + 800ca06: 4620 mov r0, r4 + 800ca08: f001 f8fe bl 800dc08 <__pow5mult> + 800ca0c: 9a04 ldr r2, [sp, #16] + 800ca0e: 4601 mov r1, r0 + 800ca10: 4606 mov r6, r0 + 800ca12: 4620 mov r0, r4 + 800ca14: f001 f862 bl 800dadc <__multiply> + 800ca18: 9904 ldr r1, [sp, #16] + 800ca1a: 9008 str r0, [sp, #32] + 800ca1c: 4620 mov r0, r4 + 800ca1e: f000 ff76 bl 800d90e <_Bfree> + 800ca22: 9b08 ldr r3, [sp, #32] + 800ca24: 9304 str r3, [sp, #16] + 800ca26: 9b07 ldr r3, [sp, #28] + 800ca28: 1bda subs r2, r3, r7 + 800ca2a: d004 beq.n 800ca36 <_dtoa_r+0x76e> + 800ca2c: 9904 ldr r1, [sp, #16] + 800ca2e: 4620 mov r0, r4 + 800ca30: f001 f8ea bl 800dc08 <__pow5mult> + 800ca34: 9004 str r0, [sp, #16] + 800ca36: 2101 movs r1, #1 + 800ca38: 4620 mov r0, r4 + 800ca3a: f001 f846 bl 800daca <__i2b> + 800ca3e: 9b0e ldr r3, [sp, #56] ; 0x38 + 800ca40: 4607 mov r7, r0 + 800ca42: 2b00 cmp r3, #0 + 800ca44: f000 81d0 beq.w 800cde8 <_dtoa_r+0xb20> + 800ca48: 461a mov r2, r3 + 800ca4a: 4601 mov r1, r0 + 800ca4c: 4620 mov r0, r4 + 800ca4e: f001 f8db bl 800dc08 <__pow5mult> + 800ca52: 9b06 ldr r3, [sp, #24] + 800ca54: 2b01 cmp r3, #1 + 800ca56: 4607 mov r7, r0 + 800ca58: dc40 bgt.n 800cadc <_dtoa_r+0x814> + 800ca5a: 9b00 ldr r3, [sp, #0] + 800ca5c: 2b00 cmp r3, #0 + 800ca5e: d139 bne.n 800cad4 <_dtoa_r+0x80c> + 800ca60: 9b01 ldr r3, [sp, #4] + 800ca62: f3c3 0313 ubfx r3, r3, #0, #20 + 800ca66: 2b00 cmp r3, #0 + 800ca68: d136 bne.n 800cad8 <_dtoa_r+0x810> + 800ca6a: 9b01 ldr r3, [sp, #4] + 800ca6c: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000 + 800ca70: 0d1b lsrs r3, r3, #20 + 800ca72: 051b lsls r3, r3, #20 + 800ca74: b12b cbz r3, 800ca82 <_dtoa_r+0x7ba> + 800ca76: 9b05 ldr r3, [sp, #20] + 800ca78: 3301 adds r3, #1 + 800ca7a: 9305 str r3, [sp, #20] + 800ca7c: f108 0801 add.w r8, r8, #1 + 800ca80: 2301 movs r3, #1 + 800ca82: 9307 str r3, [sp, #28] + 800ca84: 9b0e ldr r3, [sp, #56] ; 0x38 + 800ca86: 2b00 cmp r3, #0 + 800ca88: d12a bne.n 800cae0 <_dtoa_r+0x818> + 800ca8a: 2001 movs r0, #1 + 800ca8c: e030 b.n 800caf0 <_dtoa_r+0x828> + 800ca8e: 9b14 ldr r3, [sp, #80] ; 0x50 + 800ca90: f1c3 0336 rsb r3, r3, #54 ; 0x36 + 800ca94: e795 b.n 800c9c2 <_dtoa_r+0x6fa> + 800ca96: 9b07 ldr r3, [sp, #28] + 800ca98: f109 37ff add.w r7, r9, #4294967295 + 800ca9c: 42bb cmp r3, r7 + 800ca9e: bfbf itttt lt + 800caa0: 9b07 ldrlt r3, [sp, #28] + 800caa2: 9707 strlt r7, [sp, #28] + 800caa4: 1afa sublt r2, r7, r3 + 800caa6: 9b0e ldrlt r3, [sp, #56] ; 0x38 + 800caa8: bfbb ittet lt + 800caaa: 189b addlt r3, r3, r2 + 800caac: 930e strlt r3, [sp, #56] ; 0x38 + 800caae: 1bdf subge r7, r3, r7 + 800cab0: 2700 movlt r7, #0 + 800cab2: f1b9 0f00 cmp.w r9, #0 + 800cab6: bfb5 itete lt + 800cab8: 9b05 ldrlt r3, [sp, #20] + 800caba: 9d05 ldrge r5, [sp, #20] + 800cabc: eba3 0509 sublt.w r5, r3, r9 + 800cac0: 464b movge r3, r9 + 800cac2: bfb8 it lt + 800cac4: 2300 movlt r3, #0 + 800cac6: e77e b.n 800c9c6 <_dtoa_r+0x6fe> + 800cac8: 9f07 ldr r7, [sp, #28] + 800caca: 9d05 ldr r5, [sp, #20] + 800cacc: 9e0a ldr r6, [sp, #40] ; 0x28 + 800cace: e783 b.n 800c9d8 <_dtoa_r+0x710> + 800cad0: 9a07 ldr r2, [sp, #28] + 800cad2: e7ab b.n 800ca2c <_dtoa_r+0x764> + 800cad4: 2300 movs r3, #0 + 800cad6: e7d4 b.n 800ca82 <_dtoa_r+0x7ba> + 800cad8: 9b00 ldr r3, [sp, #0] + 800cada: e7d2 b.n 800ca82 <_dtoa_r+0x7ba> + 800cadc: 2300 movs r3, #0 + 800cade: 9307 str r3, [sp, #28] + 800cae0: 693b ldr r3, [r7, #16] + 800cae2: eb07 0383 add.w r3, r7, r3, lsl #2 + 800cae6: 6918 ldr r0, [r3, #16] + 800cae8: f000 ffa1 bl 800da2e <__hi0bits> + 800caec: f1c0 0020 rsb r0, r0, #32 + 800caf0: 4440 add r0, r8 + 800caf2: f010 001f ands.w r0, r0, #31 + 800caf6: d047 beq.n 800cb88 <_dtoa_r+0x8c0> + 800caf8: f1c0 0320 rsb r3, r0, #32 + 800cafc: 2b04 cmp r3, #4 + 800cafe: dd3b ble.n 800cb78 <_dtoa_r+0x8b0> + 800cb00: 9b05 ldr r3, [sp, #20] + 800cb02: f1c0 001c rsb r0, r0, #28 + 800cb06: 4403 add r3, r0 + 800cb08: 9305 str r3, [sp, #20] + 800cb0a: 4405 add r5, r0 + 800cb0c: 4480 add r8, r0 + 800cb0e: 9b05 ldr r3, [sp, #20] + 800cb10: 2b00 cmp r3, #0 + 800cb12: dd05 ble.n 800cb20 <_dtoa_r+0x858> + 800cb14: 461a mov r2, r3 + 800cb16: 9904 ldr r1, [sp, #16] + 800cb18: 4620 mov r0, r4 + 800cb1a: f001 f8c3 bl 800dca4 <__lshift> + 800cb1e: 9004 str r0, [sp, #16] + 800cb20: f1b8 0f00 cmp.w r8, #0 + 800cb24: dd05 ble.n 800cb32 <_dtoa_r+0x86a> + 800cb26: 4639 mov r1, r7 + 800cb28: 4642 mov r2, r8 + 800cb2a: 4620 mov r0, r4 + 800cb2c: f001 f8ba bl 800dca4 <__lshift> + 800cb30: 4607 mov r7, r0 + 800cb32: 9b0f ldr r3, [sp, #60] ; 0x3c + 800cb34: b353 cbz r3, 800cb8c <_dtoa_r+0x8c4> + 800cb36: 4639 mov r1, r7 + 800cb38: 9804 ldr r0, [sp, #16] + 800cb3a: f001 f907 bl 800dd4c <__mcmp> + 800cb3e: 2800 cmp r0, #0 + 800cb40: da24 bge.n 800cb8c <_dtoa_r+0x8c4> + 800cb42: 2300 movs r3, #0 + 800cb44: 220a movs r2, #10 + 800cb46: 9904 ldr r1, [sp, #16] + 800cb48: 4620 mov r0, r4 + 800cb4a: f000 fef7 bl 800d93c <__multadd> + 800cb4e: 9b0a ldr r3, [sp, #40] ; 0x28 + 800cb50: 9004 str r0, [sp, #16] + 800cb52: f10a 3aff add.w sl, sl, #4294967295 + 800cb56: 2b00 cmp r3, #0 + 800cb58: f000 814d beq.w 800cdf6 <_dtoa_r+0xb2e> + 800cb5c: 2300 movs r3, #0 + 800cb5e: 4631 mov r1, r6 + 800cb60: 220a movs r2, #10 + 800cb62: 4620 mov r0, r4 + 800cb64: f000 feea bl 800d93c <__multadd> + 800cb68: 9b02 ldr r3, [sp, #8] + 800cb6a: 2b00 cmp r3, #0 + 800cb6c: 4606 mov r6, r0 + 800cb6e: dc4f bgt.n 800cc10 <_dtoa_r+0x948> + 800cb70: 9b06 ldr r3, [sp, #24] + 800cb72: 2b02 cmp r3, #2 + 800cb74: dd4c ble.n 800cc10 <_dtoa_r+0x948> + 800cb76: e011 b.n 800cb9c <_dtoa_r+0x8d4> + 800cb78: d0c9 beq.n 800cb0e <_dtoa_r+0x846> + 800cb7a: 9a05 ldr r2, [sp, #20] + 800cb7c: 331c adds r3, #28 + 800cb7e: 441a add r2, r3 + 800cb80: 9205 str r2, [sp, #20] + 800cb82: 441d add r5, r3 + 800cb84: 4498 add r8, r3 + 800cb86: e7c2 b.n 800cb0e <_dtoa_r+0x846> + 800cb88: 4603 mov r3, r0 + 800cb8a: e7f6 b.n 800cb7a <_dtoa_r+0x8b2> + 800cb8c: f1b9 0f00 cmp.w r9, #0 + 800cb90: dc38 bgt.n 800cc04 <_dtoa_r+0x93c> + 800cb92: 9b06 ldr r3, [sp, #24] + 800cb94: 2b02 cmp r3, #2 + 800cb96: dd35 ble.n 800cc04 <_dtoa_r+0x93c> + 800cb98: f8cd 9008 str.w r9, [sp, #8] + 800cb9c: 9b02 ldr r3, [sp, #8] + 800cb9e: b963 cbnz r3, 800cbba <_dtoa_r+0x8f2> + 800cba0: 4639 mov r1, r7 + 800cba2: 2205 movs r2, #5 + 800cba4: 4620 mov r0, r4 + 800cba6: f000 fec9 bl 800d93c <__multadd> + 800cbaa: 4601 mov r1, r0 + 800cbac: 4607 mov r7, r0 + 800cbae: 9804 ldr r0, [sp, #16] + 800cbb0: f001 f8cc bl 800dd4c <__mcmp> + 800cbb4: 2800 cmp r0, #0 + 800cbb6: f73f adcc bgt.w 800c752 <_dtoa_r+0x48a> + 800cbba: 9b0b ldr r3, [sp, #44] ; 0x2c + 800cbbc: 465d mov r5, fp + 800cbbe: ea6f 0a03 mvn.w sl, r3 + 800cbc2: f04f 0900 mov.w r9, #0 + 800cbc6: 4639 mov r1, r7 + 800cbc8: 4620 mov r0, r4 + 800cbca: f000 fea0 bl 800d90e <_Bfree> + 800cbce: 2e00 cmp r6, #0 + 800cbd0: f43f aeb7 beq.w 800c942 <_dtoa_r+0x67a> + 800cbd4: f1b9 0f00 cmp.w r9, #0 + 800cbd8: d005 beq.n 800cbe6 <_dtoa_r+0x91e> + 800cbda: 45b1 cmp r9, r6 + 800cbdc: d003 beq.n 800cbe6 <_dtoa_r+0x91e> + 800cbde: 4649 mov r1, r9 + 800cbe0: 4620 mov r0, r4 + 800cbe2: f000 fe94 bl 800d90e <_Bfree> + 800cbe6: 4631 mov r1, r6 + 800cbe8: 4620 mov r0, r4 + 800cbea: f000 fe90 bl 800d90e <_Bfree> + 800cbee: e6a8 b.n 800c942 <_dtoa_r+0x67a> + 800cbf0: 2700 movs r7, #0 + 800cbf2: 463e mov r6, r7 + 800cbf4: e7e1 b.n 800cbba <_dtoa_r+0x8f2> + 800cbf6: f8dd a020 ldr.w sl, [sp, #32] + 800cbfa: 463e mov r6, r7 + 800cbfc: e5a9 b.n 800c752 <_dtoa_r+0x48a> + 800cbfe: bf00 nop + 800cc00: 40240000 .word 0x40240000 + 800cc04: 9b0a ldr r3, [sp, #40] ; 0x28 + 800cc06: f8cd 9008 str.w r9, [sp, #8] + 800cc0a: 2b00 cmp r3, #0 + 800cc0c: f000 80fa beq.w 800ce04 <_dtoa_r+0xb3c> + 800cc10: 2d00 cmp r5, #0 + 800cc12: dd05 ble.n 800cc20 <_dtoa_r+0x958> + 800cc14: 4631 mov r1, r6 + 800cc16: 462a mov r2, r5 + 800cc18: 4620 mov r0, r4 + 800cc1a: f001 f843 bl 800dca4 <__lshift> + 800cc1e: 4606 mov r6, r0 + 800cc20: 9b07 ldr r3, [sp, #28] + 800cc22: 2b00 cmp r3, #0 + 800cc24: d04c beq.n 800ccc0 <_dtoa_r+0x9f8> + 800cc26: 6871 ldr r1, [r6, #4] + 800cc28: 4620 mov r0, r4 + 800cc2a: f000 fe3c bl 800d8a6 <_Balloc> + 800cc2e: 6932 ldr r2, [r6, #16] + 800cc30: 3202 adds r2, #2 + 800cc32: 4605 mov r5, r0 + 800cc34: 0092 lsls r2, r2, #2 + 800cc36: f106 010c add.w r1, r6, #12 + 800cc3a: 300c adds r0, #12 + 800cc3c: f000 fe26 bl 800d88c + 800cc40: 2201 movs r2, #1 + 800cc42: 4629 mov r1, r5 + 800cc44: 4620 mov r0, r4 + 800cc46: f001 f82d bl 800dca4 <__lshift> + 800cc4a: 9b00 ldr r3, [sp, #0] + 800cc4c: f8cd b014 str.w fp, [sp, #20] + 800cc50: f003 0301 and.w r3, r3, #1 + 800cc54: 46b1 mov r9, r6 + 800cc56: 9307 str r3, [sp, #28] + 800cc58: 4606 mov r6, r0 + 800cc5a: 4639 mov r1, r7 + 800cc5c: 9804 ldr r0, [sp, #16] + 800cc5e: f7ff faa5 bl 800c1ac + 800cc62: 4649 mov r1, r9 + 800cc64: 4605 mov r5, r0 + 800cc66: f100 0830 add.w r8, r0, #48 ; 0x30 + 800cc6a: 9804 ldr r0, [sp, #16] + 800cc6c: f001 f86e bl 800dd4c <__mcmp> + 800cc70: 4632 mov r2, r6 + 800cc72: 9000 str r0, [sp, #0] + 800cc74: 4639 mov r1, r7 + 800cc76: 4620 mov r0, r4 + 800cc78: f001 f882 bl 800dd80 <__mdiff> + 800cc7c: 68c3 ldr r3, [r0, #12] + 800cc7e: 4602 mov r2, r0 + 800cc80: bb03 cbnz r3, 800ccc4 <_dtoa_r+0x9fc> + 800cc82: 4601 mov r1, r0 + 800cc84: 9008 str r0, [sp, #32] + 800cc86: 9804 ldr r0, [sp, #16] + 800cc88: f001 f860 bl 800dd4c <__mcmp> + 800cc8c: 9a08 ldr r2, [sp, #32] + 800cc8e: 4603 mov r3, r0 + 800cc90: 4611 mov r1, r2 + 800cc92: 4620 mov r0, r4 + 800cc94: 9308 str r3, [sp, #32] + 800cc96: f000 fe3a bl 800d90e <_Bfree> + 800cc9a: 9b08 ldr r3, [sp, #32] + 800cc9c: b9a3 cbnz r3, 800ccc8 <_dtoa_r+0xa00> + 800cc9e: 9a06 ldr r2, [sp, #24] + 800cca0: b992 cbnz r2, 800ccc8 <_dtoa_r+0xa00> + 800cca2: 9a07 ldr r2, [sp, #28] + 800cca4: b982 cbnz r2, 800ccc8 <_dtoa_r+0xa00> + 800cca6: f1b8 0f39 cmp.w r8, #57 ; 0x39 + 800ccaa: d029 beq.n 800cd00 <_dtoa_r+0xa38> + 800ccac: 9b00 ldr r3, [sp, #0] + 800ccae: 2b00 cmp r3, #0 + 800ccb0: dd01 ble.n 800ccb6 <_dtoa_r+0x9ee> + 800ccb2: f105 0831 add.w r8, r5, #49 ; 0x31 + 800ccb6: 9b05 ldr r3, [sp, #20] + 800ccb8: 1c5d adds r5, r3, #1 + 800ccba: f883 8000 strb.w r8, [r3] + 800ccbe: e782 b.n 800cbc6 <_dtoa_r+0x8fe> + 800ccc0: 4630 mov r0, r6 + 800ccc2: e7c2 b.n 800cc4a <_dtoa_r+0x982> + 800ccc4: 2301 movs r3, #1 + 800ccc6: e7e3 b.n 800cc90 <_dtoa_r+0x9c8> + 800ccc8: 9a00 ldr r2, [sp, #0] + 800ccca: 2a00 cmp r2, #0 + 800cccc: db04 blt.n 800ccd8 <_dtoa_r+0xa10> + 800ccce: d125 bne.n 800cd1c <_dtoa_r+0xa54> + 800ccd0: 9a06 ldr r2, [sp, #24] + 800ccd2: bb1a cbnz r2, 800cd1c <_dtoa_r+0xa54> + 800ccd4: 9a07 ldr r2, [sp, #28] + 800ccd6: bb0a cbnz r2, 800cd1c <_dtoa_r+0xa54> + 800ccd8: 2b00 cmp r3, #0 + 800ccda: ddec ble.n 800ccb6 <_dtoa_r+0x9ee> + 800ccdc: 2201 movs r2, #1 + 800ccde: 9904 ldr r1, [sp, #16] + 800cce0: 4620 mov r0, r4 + 800cce2: f000 ffdf bl 800dca4 <__lshift> + 800cce6: 4639 mov r1, r7 + 800cce8: 9004 str r0, [sp, #16] + 800ccea: f001 f82f bl 800dd4c <__mcmp> + 800ccee: 2800 cmp r0, #0 + 800ccf0: dc03 bgt.n 800ccfa <_dtoa_r+0xa32> + 800ccf2: d1e0 bne.n 800ccb6 <_dtoa_r+0x9ee> + 800ccf4: f018 0f01 tst.w r8, #1 + 800ccf8: d0dd beq.n 800ccb6 <_dtoa_r+0x9ee> + 800ccfa: f1b8 0f39 cmp.w r8, #57 ; 0x39 + 800ccfe: d1d8 bne.n 800ccb2 <_dtoa_r+0x9ea> + 800cd00: 9b05 ldr r3, [sp, #20] + 800cd02: 9a05 ldr r2, [sp, #20] + 800cd04: 1c5d adds r5, r3, #1 + 800cd06: 2339 movs r3, #57 ; 0x39 + 800cd08: 7013 strb r3, [r2, #0] + 800cd0a: f815 3c01 ldrb.w r3, [r5, #-1] + 800cd0e: 2b39 cmp r3, #57 ; 0x39 + 800cd10: f105 32ff add.w r2, r5, #4294967295 + 800cd14: d04f beq.n 800cdb6 <_dtoa_r+0xaee> + 800cd16: 3301 adds r3, #1 + 800cd18: 7013 strb r3, [r2, #0] + 800cd1a: e754 b.n 800cbc6 <_dtoa_r+0x8fe> + 800cd1c: 9a05 ldr r2, [sp, #20] + 800cd1e: 2b00 cmp r3, #0 + 800cd20: f102 0501 add.w r5, r2, #1 + 800cd24: dd06 ble.n 800cd34 <_dtoa_r+0xa6c> + 800cd26: f1b8 0f39 cmp.w r8, #57 ; 0x39 + 800cd2a: d0e9 beq.n 800cd00 <_dtoa_r+0xa38> + 800cd2c: f108 0801 add.w r8, r8, #1 + 800cd30: 9b05 ldr r3, [sp, #20] + 800cd32: e7c2 b.n 800ccba <_dtoa_r+0x9f2> + 800cd34: 9a02 ldr r2, [sp, #8] + 800cd36: f805 8c01 strb.w r8, [r5, #-1] + 800cd3a: eba5 030b sub.w r3, r5, fp + 800cd3e: 4293 cmp r3, r2 + 800cd40: d021 beq.n 800cd86 <_dtoa_r+0xabe> + 800cd42: 2300 movs r3, #0 + 800cd44: 220a movs r2, #10 + 800cd46: 9904 ldr r1, [sp, #16] + 800cd48: 4620 mov r0, r4 + 800cd4a: f000 fdf7 bl 800d93c <__multadd> + 800cd4e: 45b1 cmp r9, r6 + 800cd50: 9004 str r0, [sp, #16] + 800cd52: f04f 0300 mov.w r3, #0 + 800cd56: f04f 020a mov.w r2, #10 + 800cd5a: 4649 mov r1, r9 + 800cd5c: 4620 mov r0, r4 + 800cd5e: d105 bne.n 800cd6c <_dtoa_r+0xaa4> + 800cd60: f000 fdec bl 800d93c <__multadd> + 800cd64: 4681 mov r9, r0 + 800cd66: 4606 mov r6, r0 + 800cd68: 9505 str r5, [sp, #20] + 800cd6a: e776 b.n 800cc5a <_dtoa_r+0x992> + 800cd6c: f000 fde6 bl 800d93c <__multadd> + 800cd70: 4631 mov r1, r6 + 800cd72: 4681 mov r9, r0 + 800cd74: 2300 movs r3, #0 + 800cd76: 220a movs r2, #10 + 800cd78: 4620 mov r0, r4 + 800cd7a: f000 fddf bl 800d93c <__multadd> + 800cd7e: 4606 mov r6, r0 + 800cd80: e7f2 b.n 800cd68 <_dtoa_r+0xaa0> + 800cd82: f04f 0900 mov.w r9, #0 + 800cd86: 2201 movs r2, #1 + 800cd88: 9904 ldr r1, [sp, #16] + 800cd8a: 4620 mov r0, r4 + 800cd8c: f000 ff8a bl 800dca4 <__lshift> + 800cd90: 4639 mov r1, r7 + 800cd92: 9004 str r0, [sp, #16] + 800cd94: f000 ffda bl 800dd4c <__mcmp> + 800cd98: 2800 cmp r0, #0 + 800cd9a: dcb6 bgt.n 800cd0a <_dtoa_r+0xa42> + 800cd9c: d102 bne.n 800cda4 <_dtoa_r+0xadc> + 800cd9e: f018 0f01 tst.w r8, #1 + 800cda2: d1b2 bne.n 800cd0a <_dtoa_r+0xa42> + 800cda4: f815 3c01 ldrb.w r3, [r5, #-1] + 800cda8: 2b30 cmp r3, #48 ; 0x30 + 800cdaa: f105 32ff add.w r2, r5, #4294967295 + 800cdae: f47f af0a bne.w 800cbc6 <_dtoa_r+0x8fe> + 800cdb2: 4615 mov r5, r2 + 800cdb4: e7f6 b.n 800cda4 <_dtoa_r+0xadc> + 800cdb6: 4593 cmp fp, r2 + 800cdb8: d105 bne.n 800cdc6 <_dtoa_r+0xafe> + 800cdba: 2331 movs r3, #49 ; 0x31 + 800cdbc: f10a 0a01 add.w sl, sl, #1 + 800cdc0: f88b 3000 strb.w r3, [fp] + 800cdc4: e6ff b.n 800cbc6 <_dtoa_r+0x8fe> + 800cdc6: 4615 mov r5, r2 + 800cdc8: e79f b.n 800cd0a <_dtoa_r+0xa42> + 800cdca: f8df b064 ldr.w fp, [pc, #100] ; 800ce30 <_dtoa_r+0xb68> + 800cdce: e007 b.n 800cde0 <_dtoa_r+0xb18> + 800cdd0: 9b21 ldr r3, [sp, #132] ; 0x84 + 800cdd2: f8df b060 ldr.w fp, [pc, #96] ; 800ce34 <_dtoa_r+0xb6c> + 800cdd6: b11b cbz r3, 800cde0 <_dtoa_r+0xb18> + 800cdd8: f10b 0308 add.w r3, fp, #8 + 800cddc: 9a21 ldr r2, [sp, #132] ; 0x84 + 800cdde: 6013 str r3, [r2, #0] + 800cde0: 4658 mov r0, fp + 800cde2: b017 add sp, #92 ; 0x5c + 800cde4: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 800cde8: 9b06 ldr r3, [sp, #24] + 800cdea: 2b01 cmp r3, #1 + 800cdec: f77f ae35 ble.w 800ca5a <_dtoa_r+0x792> + 800cdf0: 9b0e ldr r3, [sp, #56] ; 0x38 + 800cdf2: 9307 str r3, [sp, #28] + 800cdf4: e649 b.n 800ca8a <_dtoa_r+0x7c2> + 800cdf6: 9b02 ldr r3, [sp, #8] + 800cdf8: 2b00 cmp r3, #0 + 800cdfa: dc03 bgt.n 800ce04 <_dtoa_r+0xb3c> + 800cdfc: 9b06 ldr r3, [sp, #24] + 800cdfe: 2b02 cmp r3, #2 + 800ce00: f73f aecc bgt.w 800cb9c <_dtoa_r+0x8d4> + 800ce04: 465d mov r5, fp + 800ce06: 4639 mov r1, r7 + 800ce08: 9804 ldr r0, [sp, #16] + 800ce0a: f7ff f9cf bl 800c1ac + 800ce0e: f100 0830 add.w r8, r0, #48 ; 0x30 + 800ce12: f805 8b01 strb.w r8, [r5], #1 + 800ce16: 9a02 ldr r2, [sp, #8] + 800ce18: eba5 030b sub.w r3, r5, fp + 800ce1c: 429a cmp r2, r3 + 800ce1e: ddb0 ble.n 800cd82 <_dtoa_r+0xaba> + 800ce20: 2300 movs r3, #0 + 800ce22: 220a movs r2, #10 + 800ce24: 9904 ldr r1, [sp, #16] + 800ce26: 4620 mov r0, r4 + 800ce28: f000 fd88 bl 800d93c <__multadd> + 800ce2c: 9004 str r0, [sp, #16] + 800ce2e: e7ea b.n 800ce06 <_dtoa_r+0xb3e> + 800ce30: 0800e948 .word 0x0800e948 + 800ce34: 0800e9c8 .word 0x0800e9c8 + +0800ce38 <__sflush_r>: + 800ce38: 898a ldrh r2, [r1, #12] + 800ce3a: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 800ce3e: 4605 mov r5, r0 + 800ce40: 0710 lsls r0, r2, #28 + 800ce42: 460c mov r4, r1 + 800ce44: d458 bmi.n 800cef8 <__sflush_r+0xc0> + 800ce46: 684b ldr r3, [r1, #4] + 800ce48: 2b00 cmp r3, #0 + 800ce4a: dc05 bgt.n 800ce58 <__sflush_r+0x20> + 800ce4c: 6c0b ldr r3, [r1, #64] ; 0x40 + 800ce4e: 2b00 cmp r3, #0 + 800ce50: dc02 bgt.n 800ce58 <__sflush_r+0x20> + 800ce52: 2000 movs r0, #0 + 800ce54: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 800ce58: 6ae6 ldr r6, [r4, #44] ; 0x2c + 800ce5a: 2e00 cmp r6, #0 + 800ce5c: d0f9 beq.n 800ce52 <__sflush_r+0x1a> + 800ce5e: 2300 movs r3, #0 + 800ce60: f412 5280 ands.w r2, r2, #4096 ; 0x1000 + 800ce64: 682f ldr r7, [r5, #0] + 800ce66: 6a21 ldr r1, [r4, #32] + 800ce68: 602b str r3, [r5, #0] + 800ce6a: d032 beq.n 800ced2 <__sflush_r+0x9a> + 800ce6c: 6d60 ldr r0, [r4, #84] ; 0x54 + 800ce6e: 89a3 ldrh r3, [r4, #12] + 800ce70: 075a lsls r2, r3, #29 + 800ce72: d505 bpl.n 800ce80 <__sflush_r+0x48> + 800ce74: 6863 ldr r3, [r4, #4] + 800ce76: 1ac0 subs r0, r0, r3 + 800ce78: 6b63 ldr r3, [r4, #52] ; 0x34 + 800ce7a: b10b cbz r3, 800ce80 <__sflush_r+0x48> + 800ce7c: 6c23 ldr r3, [r4, #64] ; 0x40 + 800ce7e: 1ac0 subs r0, r0, r3 + 800ce80: 2300 movs r3, #0 + 800ce82: 4602 mov r2, r0 + 800ce84: 6ae6 ldr r6, [r4, #44] ; 0x2c + 800ce86: 6a21 ldr r1, [r4, #32] + 800ce88: 4628 mov r0, r5 + 800ce8a: 47b0 blx r6 + 800ce8c: 1c43 adds r3, r0, #1 + 800ce8e: 89a3 ldrh r3, [r4, #12] + 800ce90: d106 bne.n 800cea0 <__sflush_r+0x68> + 800ce92: 6829 ldr r1, [r5, #0] + 800ce94: 291d cmp r1, #29 + 800ce96: d848 bhi.n 800cf2a <__sflush_r+0xf2> + 800ce98: 4a29 ldr r2, [pc, #164] ; (800cf40 <__sflush_r+0x108>) + 800ce9a: 40ca lsrs r2, r1 + 800ce9c: 07d6 lsls r6, r2, #31 + 800ce9e: d544 bpl.n 800cf2a <__sflush_r+0xf2> + 800cea0: 2200 movs r2, #0 + 800cea2: 6062 str r2, [r4, #4] + 800cea4: 04d9 lsls r1, r3, #19 + 800cea6: 6922 ldr r2, [r4, #16] + 800cea8: 6022 str r2, [r4, #0] + 800ceaa: d504 bpl.n 800ceb6 <__sflush_r+0x7e> + 800ceac: 1c42 adds r2, r0, #1 + 800ceae: d101 bne.n 800ceb4 <__sflush_r+0x7c> + 800ceb0: 682b ldr r3, [r5, #0] + 800ceb2: b903 cbnz r3, 800ceb6 <__sflush_r+0x7e> + 800ceb4: 6560 str r0, [r4, #84] ; 0x54 + 800ceb6: 6b61 ldr r1, [r4, #52] ; 0x34 + 800ceb8: 602f str r7, [r5, #0] + 800ceba: 2900 cmp r1, #0 + 800cebc: d0c9 beq.n 800ce52 <__sflush_r+0x1a> + 800cebe: f104 0344 add.w r3, r4, #68 ; 0x44 + 800cec2: 4299 cmp r1, r3 + 800cec4: d002 beq.n 800cecc <__sflush_r+0x94> + 800cec6: 4628 mov r0, r5 + 800cec8: f7fd fa6a bl 800a3a0 <_free_r> + 800cecc: 2000 movs r0, #0 + 800cece: 6360 str r0, [r4, #52] ; 0x34 + 800ced0: e7c0 b.n 800ce54 <__sflush_r+0x1c> + 800ced2: 2301 movs r3, #1 + 800ced4: 4628 mov r0, r5 + 800ced6: 47b0 blx r6 + 800ced8: 1c41 adds r1, r0, #1 + 800ceda: d1c8 bne.n 800ce6e <__sflush_r+0x36> + 800cedc: 682b ldr r3, [r5, #0] + 800cede: 2b00 cmp r3, #0 + 800cee0: d0c5 beq.n 800ce6e <__sflush_r+0x36> + 800cee2: 2b1d cmp r3, #29 + 800cee4: d001 beq.n 800ceea <__sflush_r+0xb2> + 800cee6: 2b16 cmp r3, #22 + 800cee8: d101 bne.n 800ceee <__sflush_r+0xb6> + 800ceea: 602f str r7, [r5, #0] + 800ceec: e7b1 b.n 800ce52 <__sflush_r+0x1a> + 800ceee: 89a3 ldrh r3, [r4, #12] + 800cef0: f043 0340 orr.w r3, r3, #64 ; 0x40 + 800cef4: 81a3 strh r3, [r4, #12] + 800cef6: e7ad b.n 800ce54 <__sflush_r+0x1c> + 800cef8: 690f ldr r7, [r1, #16] + 800cefa: 2f00 cmp r7, #0 + 800cefc: d0a9 beq.n 800ce52 <__sflush_r+0x1a> + 800cefe: 0793 lsls r3, r2, #30 + 800cf00: 680e ldr r6, [r1, #0] + 800cf02: bf08 it eq + 800cf04: 694b ldreq r3, [r1, #20] + 800cf06: 600f str r7, [r1, #0] + 800cf08: bf18 it ne + 800cf0a: 2300 movne r3, #0 + 800cf0c: eba6 0807 sub.w r8, r6, r7 + 800cf10: 608b str r3, [r1, #8] + 800cf12: f1b8 0f00 cmp.w r8, #0 + 800cf16: dd9c ble.n 800ce52 <__sflush_r+0x1a> + 800cf18: 4643 mov r3, r8 + 800cf1a: 463a mov r2, r7 + 800cf1c: 6a21 ldr r1, [r4, #32] + 800cf1e: 6aa6 ldr r6, [r4, #40] ; 0x28 + 800cf20: 4628 mov r0, r5 + 800cf22: 47b0 blx r6 + 800cf24: 2800 cmp r0, #0 + 800cf26: dc06 bgt.n 800cf36 <__sflush_r+0xfe> + 800cf28: 89a3 ldrh r3, [r4, #12] + 800cf2a: f043 0340 orr.w r3, r3, #64 ; 0x40 + 800cf2e: 81a3 strh r3, [r4, #12] + 800cf30: f04f 30ff mov.w r0, #4294967295 + 800cf34: e78e b.n 800ce54 <__sflush_r+0x1c> + 800cf36: 4407 add r7, r0 + 800cf38: eba8 0800 sub.w r8, r8, r0 + 800cf3c: e7e9 b.n 800cf12 <__sflush_r+0xda> + 800cf3e: bf00 nop + 800cf40: 20400001 .word 0x20400001 + +0800cf44 <_fflush_r>: + 800cf44: b538 push {r3, r4, r5, lr} + 800cf46: 690b ldr r3, [r1, #16] + 800cf48: 4605 mov r5, r0 + 800cf4a: 460c mov r4, r1 + 800cf4c: b1db cbz r3, 800cf86 <_fflush_r+0x42> + 800cf4e: b118 cbz r0, 800cf58 <_fflush_r+0x14> + 800cf50: 6983 ldr r3, [r0, #24] + 800cf52: b90b cbnz r3, 800cf58 <_fflush_r+0x14> + 800cf54: f000 f860 bl 800d018 <__sinit> + 800cf58: 4b0c ldr r3, [pc, #48] ; (800cf8c <_fflush_r+0x48>) + 800cf5a: 429c cmp r4, r3 + 800cf5c: d109 bne.n 800cf72 <_fflush_r+0x2e> + 800cf5e: 686c ldr r4, [r5, #4] + 800cf60: f9b4 300c ldrsh.w r3, [r4, #12] + 800cf64: b17b cbz r3, 800cf86 <_fflush_r+0x42> + 800cf66: 4621 mov r1, r4 + 800cf68: 4628 mov r0, r5 + 800cf6a: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} + 800cf6e: f7ff bf63 b.w 800ce38 <__sflush_r> + 800cf72: 4b07 ldr r3, [pc, #28] ; (800cf90 <_fflush_r+0x4c>) + 800cf74: 429c cmp r4, r3 + 800cf76: d101 bne.n 800cf7c <_fflush_r+0x38> + 800cf78: 68ac ldr r4, [r5, #8] + 800cf7a: e7f1 b.n 800cf60 <_fflush_r+0x1c> + 800cf7c: 4b05 ldr r3, [pc, #20] ; (800cf94 <_fflush_r+0x50>) + 800cf7e: 429c cmp r4, r3 + 800cf80: bf08 it eq + 800cf82: 68ec ldreq r4, [r5, #12] + 800cf84: e7ec b.n 800cf60 <_fflush_r+0x1c> + 800cf86: 2000 movs r0, #0 + 800cf88: bd38 pop {r3, r4, r5, pc} + 800cf8a: bf00 nop + 800cf8c: 0800e9f8 .word 0x0800e9f8 + 800cf90: 0800ea18 .word 0x0800ea18 + 800cf94: 0800e9d8 .word 0x0800e9d8 + +0800cf98 : + 800cf98: 2300 movs r3, #0 + 800cf9a: b510 push {r4, lr} + 800cf9c: 4604 mov r4, r0 + 800cf9e: e9c0 3300 strd r3, r3, [r0] + 800cfa2: 6083 str r3, [r0, #8] + 800cfa4: 8181 strh r1, [r0, #12] + 800cfa6: 6643 str r3, [r0, #100] ; 0x64 + 800cfa8: 81c2 strh r2, [r0, #14] + 800cfaa: e9c0 3304 strd r3, r3, [r0, #16] + 800cfae: 6183 str r3, [r0, #24] + 800cfb0: 4619 mov r1, r3 + 800cfb2: 2208 movs r2, #8 + 800cfb4: 305c adds r0, #92 ; 0x5c + 800cfb6: f7fd f9eb bl 800a390 + 800cfba: 4b05 ldr r3, [pc, #20] ; (800cfd0 ) + 800cfbc: 6263 str r3, [r4, #36] ; 0x24 + 800cfbe: 4b05 ldr r3, [pc, #20] ; (800cfd4 ) + 800cfc0: 62a3 str r3, [r4, #40] ; 0x28 + 800cfc2: 4b05 ldr r3, [pc, #20] ; (800cfd8 ) + 800cfc4: 62e3 str r3, [r4, #44] ; 0x2c + 800cfc6: 4b05 ldr r3, [pc, #20] ; (800cfdc ) + 800cfc8: 6224 str r4, [r4, #32] + 800cfca: 6323 str r3, [r4, #48] ; 0x30 + 800cfcc: bd10 pop {r4, pc} + 800cfce: bf00 nop + 800cfd0: 0800e5e5 .word 0x0800e5e5 + 800cfd4: 0800e607 .word 0x0800e607 + 800cfd8: 0800e63f .word 0x0800e63f + 800cfdc: 0800e663 .word 0x0800e663 + +0800cfe0 <_cleanup_r>: + 800cfe0: 4901 ldr r1, [pc, #4] ; (800cfe8 <_cleanup_r+0x8>) + 800cfe2: f000 b885 b.w 800d0f0 <_fwalk_reent> + 800cfe6: bf00 nop + 800cfe8: 0800cf45 .word 0x0800cf45 + +0800cfec <__sfmoreglue>: + 800cfec: b570 push {r4, r5, r6, lr} + 800cfee: 1e4a subs r2, r1, #1 + 800cff0: 2568 movs r5, #104 ; 0x68 + 800cff2: 4355 muls r5, r2 + 800cff4: 460e mov r6, r1 + 800cff6: f105 0174 add.w r1, r5, #116 ; 0x74 + 800cffa: f7fd fa1f bl 800a43c <_malloc_r> + 800cffe: 4604 mov r4, r0 + 800d000: b140 cbz r0, 800d014 <__sfmoreglue+0x28> + 800d002: 2100 movs r1, #0 + 800d004: e9c0 1600 strd r1, r6, [r0] + 800d008: 300c adds r0, #12 + 800d00a: 60a0 str r0, [r4, #8] + 800d00c: f105 0268 add.w r2, r5, #104 ; 0x68 + 800d010: f7fd f9be bl 800a390 + 800d014: 4620 mov r0, r4 + 800d016: bd70 pop {r4, r5, r6, pc} + +0800d018 <__sinit>: + 800d018: 6983 ldr r3, [r0, #24] + 800d01a: b510 push {r4, lr} + 800d01c: 4604 mov r4, r0 + 800d01e: bb33 cbnz r3, 800d06e <__sinit+0x56> + 800d020: e9c0 3312 strd r3, r3, [r0, #72] ; 0x48 + 800d024: 6503 str r3, [r0, #80] ; 0x50 + 800d026: 4b12 ldr r3, [pc, #72] ; (800d070 <__sinit+0x58>) + 800d028: 4a12 ldr r2, [pc, #72] ; (800d074 <__sinit+0x5c>) + 800d02a: 681b ldr r3, [r3, #0] + 800d02c: 6282 str r2, [r0, #40] ; 0x28 + 800d02e: 4298 cmp r0, r3 + 800d030: bf04 itt eq + 800d032: 2301 moveq r3, #1 + 800d034: 6183 streq r3, [r0, #24] + 800d036: f000 f81f bl 800d078 <__sfp> + 800d03a: 6060 str r0, [r4, #4] + 800d03c: 4620 mov r0, r4 + 800d03e: f000 f81b bl 800d078 <__sfp> + 800d042: 60a0 str r0, [r4, #8] + 800d044: 4620 mov r0, r4 + 800d046: f000 f817 bl 800d078 <__sfp> + 800d04a: 2200 movs r2, #0 + 800d04c: 60e0 str r0, [r4, #12] + 800d04e: 2104 movs r1, #4 + 800d050: 6860 ldr r0, [r4, #4] + 800d052: f7ff ffa1 bl 800cf98 + 800d056: 2201 movs r2, #1 + 800d058: 2109 movs r1, #9 + 800d05a: 68a0 ldr r0, [r4, #8] + 800d05c: f7ff ff9c bl 800cf98 + 800d060: 2202 movs r2, #2 + 800d062: 2112 movs r1, #18 + 800d064: 68e0 ldr r0, [r4, #12] + 800d066: f7ff ff97 bl 800cf98 + 800d06a: 2301 movs r3, #1 + 800d06c: 61a3 str r3, [r4, #24] + 800d06e: bd10 pop {r4, pc} + 800d070: 0800e934 .word 0x0800e934 + 800d074: 0800cfe1 .word 0x0800cfe1 + +0800d078 <__sfp>: + 800d078: b5f8 push {r3, r4, r5, r6, r7, lr} + 800d07a: 4b1b ldr r3, [pc, #108] ; (800d0e8 <__sfp+0x70>) + 800d07c: 681e ldr r6, [r3, #0] + 800d07e: 69b3 ldr r3, [r6, #24] + 800d080: 4607 mov r7, r0 + 800d082: b913 cbnz r3, 800d08a <__sfp+0x12> + 800d084: 4630 mov r0, r6 + 800d086: f7ff ffc7 bl 800d018 <__sinit> + 800d08a: 3648 adds r6, #72 ; 0x48 + 800d08c: e9d6 3401 ldrd r3, r4, [r6, #4] + 800d090: 3b01 subs r3, #1 + 800d092: d503 bpl.n 800d09c <__sfp+0x24> + 800d094: 6833 ldr r3, [r6, #0] + 800d096: b133 cbz r3, 800d0a6 <__sfp+0x2e> + 800d098: 6836 ldr r6, [r6, #0] + 800d09a: e7f7 b.n 800d08c <__sfp+0x14> + 800d09c: f9b4 500c ldrsh.w r5, [r4, #12] + 800d0a0: b16d cbz r5, 800d0be <__sfp+0x46> + 800d0a2: 3468 adds r4, #104 ; 0x68 + 800d0a4: e7f4 b.n 800d090 <__sfp+0x18> + 800d0a6: 2104 movs r1, #4 + 800d0a8: 4638 mov r0, r7 + 800d0aa: f7ff ff9f bl 800cfec <__sfmoreglue> + 800d0ae: 6030 str r0, [r6, #0] + 800d0b0: 2800 cmp r0, #0 + 800d0b2: d1f1 bne.n 800d098 <__sfp+0x20> + 800d0b4: 230c movs r3, #12 + 800d0b6: 603b str r3, [r7, #0] + 800d0b8: 4604 mov r4, r0 + 800d0ba: 4620 mov r0, r4 + 800d0bc: bdf8 pop {r3, r4, r5, r6, r7, pc} + 800d0be: 4b0b ldr r3, [pc, #44] ; (800d0ec <__sfp+0x74>) + 800d0c0: 6665 str r5, [r4, #100] ; 0x64 + 800d0c2: e9c4 5500 strd r5, r5, [r4] + 800d0c6: 60a5 str r5, [r4, #8] + 800d0c8: e9c4 3503 strd r3, r5, [r4, #12] + 800d0cc: e9c4 5505 strd r5, r5, [r4, #20] + 800d0d0: 2208 movs r2, #8 + 800d0d2: 4629 mov r1, r5 + 800d0d4: f104 005c add.w r0, r4, #92 ; 0x5c + 800d0d8: f7fd f95a bl 800a390 + 800d0dc: e9c4 550d strd r5, r5, [r4, #52] ; 0x34 + 800d0e0: e9c4 5512 strd r5, r5, [r4, #72] ; 0x48 + 800d0e4: e7e9 b.n 800d0ba <__sfp+0x42> + 800d0e6: bf00 nop + 800d0e8: 0800e934 .word 0x0800e934 + 800d0ec: ffff0001 .word 0xffff0001 + +0800d0f0 <_fwalk_reent>: + 800d0f0: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} + 800d0f4: 4680 mov r8, r0 + 800d0f6: 4689 mov r9, r1 + 800d0f8: f100 0448 add.w r4, r0, #72 ; 0x48 + 800d0fc: 2600 movs r6, #0 + 800d0fe: b914 cbnz r4, 800d106 <_fwalk_reent+0x16> + 800d100: 4630 mov r0, r6 + 800d102: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} + 800d106: e9d4 7501 ldrd r7, r5, [r4, #4] + 800d10a: 3f01 subs r7, #1 + 800d10c: d501 bpl.n 800d112 <_fwalk_reent+0x22> + 800d10e: 6824 ldr r4, [r4, #0] + 800d110: e7f5 b.n 800d0fe <_fwalk_reent+0xe> + 800d112: 89ab ldrh r3, [r5, #12] + 800d114: 2b01 cmp r3, #1 + 800d116: d907 bls.n 800d128 <_fwalk_reent+0x38> + 800d118: f9b5 300e ldrsh.w r3, [r5, #14] + 800d11c: 3301 adds r3, #1 + 800d11e: d003 beq.n 800d128 <_fwalk_reent+0x38> + 800d120: 4629 mov r1, r5 + 800d122: 4640 mov r0, r8 + 800d124: 47c8 blx r9 + 800d126: 4306 orrs r6, r0 + 800d128: 3568 adds r5, #104 ; 0x68 + 800d12a: e7ee b.n 800d10a <_fwalk_reent+0x1a> + +0800d12c : + 800d12c: b5f0 push {r4, r5, r6, r7, lr} + 800d12e: 6906 ldr r6, [r0, #16] + 800d130: 114b asrs r3, r1, #5 + 800d132: 429e cmp r6, r3 + 800d134: f100 0414 add.w r4, r0, #20 + 800d138: dd30 ble.n 800d19c + 800d13a: f011 011f ands.w r1, r1, #31 + 800d13e: eb04 0686 add.w r6, r4, r6, lsl #2 + 800d142: eb04 0283 add.w r2, r4, r3, lsl #2 + 800d146: d108 bne.n 800d15a + 800d148: 4621 mov r1, r4 + 800d14a: 42b2 cmp r2, r6 + 800d14c: 460b mov r3, r1 + 800d14e: d211 bcs.n 800d174 + 800d150: f852 3b04 ldr.w r3, [r2], #4 + 800d154: f841 3b04 str.w r3, [r1], #4 + 800d158: e7f7 b.n 800d14a + 800d15a: f854 5023 ldr.w r5, [r4, r3, lsl #2] + 800d15e: f1c1 0c20 rsb ip, r1, #32 + 800d162: 40cd lsrs r5, r1 + 800d164: 3204 adds r2, #4 + 800d166: 4623 mov r3, r4 + 800d168: 42b2 cmp r2, r6 + 800d16a: 4617 mov r7, r2 + 800d16c: d30c bcc.n 800d188 + 800d16e: 601d str r5, [r3, #0] + 800d170: b105 cbz r5, 800d174 + 800d172: 3304 adds r3, #4 + 800d174: 1b1a subs r2, r3, r4 + 800d176: 42a3 cmp r3, r4 + 800d178: ea4f 02a2 mov.w r2, r2, asr #2 + 800d17c: bf08 it eq + 800d17e: 2300 moveq r3, #0 + 800d180: 6102 str r2, [r0, #16] + 800d182: bf08 it eq + 800d184: 6143 streq r3, [r0, #20] + 800d186: bdf0 pop {r4, r5, r6, r7, pc} + 800d188: 683f ldr r7, [r7, #0] + 800d18a: fa07 f70c lsl.w r7, r7, ip + 800d18e: 433d orrs r5, r7 + 800d190: f843 5b04 str.w r5, [r3], #4 + 800d194: f852 5b04 ldr.w r5, [r2], #4 + 800d198: 40cd lsrs r5, r1 + 800d19a: e7e5 b.n 800d168 + 800d19c: 4623 mov r3, r4 + 800d19e: e7e9 b.n 800d174 + +0800d1a0 <__hexdig_fun>: + 800d1a0: f1a0 0330 sub.w r3, r0, #48 ; 0x30 + 800d1a4: 2b09 cmp r3, #9 + 800d1a6: d802 bhi.n 800d1ae <__hexdig_fun+0xe> + 800d1a8: 3820 subs r0, #32 + 800d1aa: b2c0 uxtb r0, r0 + 800d1ac: 4770 bx lr + 800d1ae: f1a0 0361 sub.w r3, r0, #97 ; 0x61 + 800d1b2: 2b05 cmp r3, #5 + 800d1b4: d801 bhi.n 800d1ba <__hexdig_fun+0x1a> + 800d1b6: 3847 subs r0, #71 ; 0x47 + 800d1b8: e7f7 b.n 800d1aa <__hexdig_fun+0xa> + 800d1ba: f1a0 0341 sub.w r3, r0, #65 ; 0x41 + 800d1be: 2b05 cmp r3, #5 + 800d1c0: d801 bhi.n 800d1c6 <__hexdig_fun+0x26> + 800d1c2: 3827 subs r0, #39 ; 0x27 + 800d1c4: e7f1 b.n 800d1aa <__hexdig_fun+0xa> + 800d1c6: 2000 movs r0, #0 + 800d1c8: 4770 bx lr + +0800d1ca <__gethex>: + 800d1ca: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 800d1ce: b08b sub sp, #44 ; 0x2c + 800d1d0: 468a mov sl, r1 + 800d1d2: 9002 str r0, [sp, #8] + 800d1d4: 9816 ldr r0, [sp, #88] ; 0x58 + 800d1d6: 9306 str r3, [sp, #24] + 800d1d8: 4690 mov r8, r2 + 800d1da: f000 fad0 bl 800d77e <__localeconv_l> + 800d1de: 6803 ldr r3, [r0, #0] + 800d1e0: 9303 str r3, [sp, #12] + 800d1e2: 4618 mov r0, r3 + 800d1e4: f7f2 fffc bl 80001e0 + 800d1e8: 9b03 ldr r3, [sp, #12] + 800d1ea: 9001 str r0, [sp, #4] + 800d1ec: 4403 add r3, r0 + 800d1ee: f04f 0b00 mov.w fp, #0 + 800d1f2: f813 3c01 ldrb.w r3, [r3, #-1] + 800d1f6: 9307 str r3, [sp, #28] + 800d1f8: f8da 3000 ldr.w r3, [sl] + 800d1fc: 3302 adds r3, #2 + 800d1fe: 461f mov r7, r3 + 800d200: f813 0b01 ldrb.w r0, [r3], #1 + 800d204: 2830 cmp r0, #48 ; 0x30 + 800d206: d06c beq.n 800d2e2 <__gethex+0x118> + 800d208: f7ff ffca bl 800d1a0 <__hexdig_fun> + 800d20c: 4604 mov r4, r0 + 800d20e: 2800 cmp r0, #0 + 800d210: d16a bne.n 800d2e8 <__gethex+0x11e> + 800d212: 9a01 ldr r2, [sp, #4] + 800d214: 9903 ldr r1, [sp, #12] + 800d216: 4638 mov r0, r7 + 800d218: f001 fa27 bl 800e66a + 800d21c: 2800 cmp r0, #0 + 800d21e: d166 bne.n 800d2ee <__gethex+0x124> + 800d220: 9b01 ldr r3, [sp, #4] + 800d222: 5cf8 ldrb r0, [r7, r3] + 800d224: 18fe adds r6, r7, r3 + 800d226: f7ff ffbb bl 800d1a0 <__hexdig_fun> + 800d22a: 2800 cmp r0, #0 + 800d22c: d062 beq.n 800d2f4 <__gethex+0x12a> + 800d22e: 4633 mov r3, r6 + 800d230: 7818 ldrb r0, [r3, #0] + 800d232: 2830 cmp r0, #48 ; 0x30 + 800d234: 461f mov r7, r3 + 800d236: f103 0301 add.w r3, r3, #1 + 800d23a: d0f9 beq.n 800d230 <__gethex+0x66> + 800d23c: f7ff ffb0 bl 800d1a0 <__hexdig_fun> + 800d240: fab0 f580 clz r5, r0 + 800d244: 096d lsrs r5, r5, #5 + 800d246: 4634 mov r4, r6 + 800d248: f04f 0b01 mov.w fp, #1 + 800d24c: 463a mov r2, r7 + 800d24e: 4616 mov r6, r2 + 800d250: 3201 adds r2, #1 + 800d252: 7830 ldrb r0, [r6, #0] + 800d254: f7ff ffa4 bl 800d1a0 <__hexdig_fun> + 800d258: 2800 cmp r0, #0 + 800d25a: d1f8 bne.n 800d24e <__gethex+0x84> + 800d25c: 9a01 ldr r2, [sp, #4] + 800d25e: 9903 ldr r1, [sp, #12] + 800d260: 4630 mov r0, r6 + 800d262: f001 fa02 bl 800e66a + 800d266: b950 cbnz r0, 800d27e <__gethex+0xb4> + 800d268: b954 cbnz r4, 800d280 <__gethex+0xb6> + 800d26a: 9b01 ldr r3, [sp, #4] + 800d26c: 18f4 adds r4, r6, r3 + 800d26e: 4622 mov r2, r4 + 800d270: 4616 mov r6, r2 + 800d272: 3201 adds r2, #1 + 800d274: 7830 ldrb r0, [r6, #0] + 800d276: f7ff ff93 bl 800d1a0 <__hexdig_fun> + 800d27a: 2800 cmp r0, #0 + 800d27c: d1f8 bne.n 800d270 <__gethex+0xa6> + 800d27e: b10c cbz r4, 800d284 <__gethex+0xba> + 800d280: 1ba4 subs r4, r4, r6 + 800d282: 00a4 lsls r4, r4, #2 + 800d284: 7833 ldrb r3, [r6, #0] + 800d286: 2b50 cmp r3, #80 ; 0x50 + 800d288: d001 beq.n 800d28e <__gethex+0xc4> + 800d28a: 2b70 cmp r3, #112 ; 0x70 + 800d28c: d140 bne.n 800d310 <__gethex+0x146> + 800d28e: 7873 ldrb r3, [r6, #1] + 800d290: 2b2b cmp r3, #43 ; 0x2b + 800d292: d031 beq.n 800d2f8 <__gethex+0x12e> + 800d294: 2b2d cmp r3, #45 ; 0x2d + 800d296: d033 beq.n 800d300 <__gethex+0x136> + 800d298: 1c71 adds r1, r6, #1 + 800d29a: f04f 0900 mov.w r9, #0 + 800d29e: 7808 ldrb r0, [r1, #0] + 800d2a0: f7ff ff7e bl 800d1a0 <__hexdig_fun> + 800d2a4: 1e43 subs r3, r0, #1 + 800d2a6: b2db uxtb r3, r3 + 800d2a8: 2b18 cmp r3, #24 + 800d2aa: d831 bhi.n 800d310 <__gethex+0x146> + 800d2ac: f1a0 0210 sub.w r2, r0, #16 + 800d2b0: f811 0f01 ldrb.w r0, [r1, #1]! + 800d2b4: f7ff ff74 bl 800d1a0 <__hexdig_fun> + 800d2b8: 1e43 subs r3, r0, #1 + 800d2ba: b2db uxtb r3, r3 + 800d2bc: 2b18 cmp r3, #24 + 800d2be: d922 bls.n 800d306 <__gethex+0x13c> + 800d2c0: f1b9 0f00 cmp.w r9, #0 + 800d2c4: d000 beq.n 800d2c8 <__gethex+0xfe> + 800d2c6: 4252 negs r2, r2 + 800d2c8: 4414 add r4, r2 + 800d2ca: f8ca 1000 str.w r1, [sl] + 800d2ce: b30d cbz r5, 800d314 <__gethex+0x14a> + 800d2d0: f1bb 0f00 cmp.w fp, #0 + 800d2d4: bf0c ite eq + 800d2d6: 2706 moveq r7, #6 + 800d2d8: 2700 movne r7, #0 + 800d2da: 4638 mov r0, r7 + 800d2dc: b00b add sp, #44 ; 0x2c + 800d2de: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 800d2e2: f10b 0b01 add.w fp, fp, #1 + 800d2e6: e78a b.n 800d1fe <__gethex+0x34> + 800d2e8: 2500 movs r5, #0 + 800d2ea: 462c mov r4, r5 + 800d2ec: e7ae b.n 800d24c <__gethex+0x82> + 800d2ee: 463e mov r6, r7 + 800d2f0: 2501 movs r5, #1 + 800d2f2: e7c7 b.n 800d284 <__gethex+0xba> + 800d2f4: 4604 mov r4, r0 + 800d2f6: e7fb b.n 800d2f0 <__gethex+0x126> + 800d2f8: f04f 0900 mov.w r9, #0 + 800d2fc: 1cb1 adds r1, r6, #2 + 800d2fe: e7ce b.n 800d29e <__gethex+0xd4> + 800d300: f04f 0901 mov.w r9, #1 + 800d304: e7fa b.n 800d2fc <__gethex+0x132> + 800d306: 230a movs r3, #10 + 800d308: fb03 0202 mla r2, r3, r2, r0 + 800d30c: 3a10 subs r2, #16 + 800d30e: e7cf b.n 800d2b0 <__gethex+0xe6> + 800d310: 4631 mov r1, r6 + 800d312: e7da b.n 800d2ca <__gethex+0x100> + 800d314: 1bf3 subs r3, r6, r7 + 800d316: 3b01 subs r3, #1 + 800d318: 4629 mov r1, r5 + 800d31a: 2b07 cmp r3, #7 + 800d31c: dc49 bgt.n 800d3b2 <__gethex+0x1e8> + 800d31e: 9802 ldr r0, [sp, #8] + 800d320: f000 fac1 bl 800d8a6 <_Balloc> + 800d324: 9b01 ldr r3, [sp, #4] + 800d326: f100 0914 add.w r9, r0, #20 + 800d32a: f04f 0b00 mov.w fp, #0 + 800d32e: f1c3 0301 rsb r3, r3, #1 + 800d332: 4605 mov r5, r0 + 800d334: f8cd 9010 str.w r9, [sp, #16] + 800d338: 46da mov sl, fp + 800d33a: 9308 str r3, [sp, #32] + 800d33c: 42b7 cmp r7, r6 + 800d33e: d33b bcc.n 800d3b8 <__gethex+0x1ee> + 800d340: 9804 ldr r0, [sp, #16] + 800d342: f840 ab04 str.w sl, [r0], #4 + 800d346: eba0 0009 sub.w r0, r0, r9 + 800d34a: 1080 asrs r0, r0, #2 + 800d34c: 6128 str r0, [r5, #16] + 800d34e: 0147 lsls r7, r0, #5 + 800d350: 4650 mov r0, sl + 800d352: f000 fb6c bl 800da2e <__hi0bits> + 800d356: f8d8 6000 ldr.w r6, [r8] + 800d35a: 1a3f subs r7, r7, r0 + 800d35c: 42b7 cmp r7, r6 + 800d35e: dd64 ble.n 800d42a <__gethex+0x260> + 800d360: 1bbf subs r7, r7, r6 + 800d362: 4639 mov r1, r7 + 800d364: 4628 mov r0, r5 + 800d366: f000 fe7b bl 800e060 <__any_on> + 800d36a: 4682 mov sl, r0 + 800d36c: b178 cbz r0, 800d38e <__gethex+0x1c4> + 800d36e: 1e7b subs r3, r7, #1 + 800d370: 1159 asrs r1, r3, #5 + 800d372: f003 021f and.w r2, r3, #31 + 800d376: f04f 0a01 mov.w sl, #1 + 800d37a: f859 1021 ldr.w r1, [r9, r1, lsl #2] + 800d37e: fa0a f202 lsl.w r2, sl, r2 + 800d382: 420a tst r2, r1 + 800d384: d003 beq.n 800d38e <__gethex+0x1c4> + 800d386: 4553 cmp r3, sl + 800d388: dc46 bgt.n 800d418 <__gethex+0x24e> + 800d38a: f04f 0a02 mov.w sl, #2 + 800d38e: 4639 mov r1, r7 + 800d390: 4628 mov r0, r5 + 800d392: f7ff fecb bl 800d12c + 800d396: 443c add r4, r7 + 800d398: f8d8 3008 ldr.w r3, [r8, #8] + 800d39c: 42a3 cmp r3, r4 + 800d39e: da52 bge.n 800d446 <__gethex+0x27c> + 800d3a0: 4629 mov r1, r5 + 800d3a2: 9802 ldr r0, [sp, #8] + 800d3a4: f000 fab3 bl 800d90e <_Bfree> + 800d3a8: 9a14 ldr r2, [sp, #80] ; 0x50 + 800d3aa: 2300 movs r3, #0 + 800d3ac: 6013 str r3, [r2, #0] + 800d3ae: 27a3 movs r7, #163 ; 0xa3 + 800d3b0: e793 b.n 800d2da <__gethex+0x110> + 800d3b2: 3101 adds r1, #1 + 800d3b4: 105b asrs r3, r3, #1 + 800d3b6: e7b0 b.n 800d31a <__gethex+0x150> + 800d3b8: 1e73 subs r3, r6, #1 + 800d3ba: 9305 str r3, [sp, #20] + 800d3bc: 9a07 ldr r2, [sp, #28] + 800d3be: f816 3c01 ldrb.w r3, [r6, #-1] + 800d3c2: 4293 cmp r3, r2 + 800d3c4: d018 beq.n 800d3f8 <__gethex+0x22e> + 800d3c6: f1bb 0f20 cmp.w fp, #32 + 800d3ca: d107 bne.n 800d3dc <__gethex+0x212> + 800d3cc: 9b04 ldr r3, [sp, #16] + 800d3ce: f8c3 a000 str.w sl, [r3] + 800d3d2: 3304 adds r3, #4 + 800d3d4: f04f 0a00 mov.w sl, #0 + 800d3d8: 9304 str r3, [sp, #16] + 800d3da: 46d3 mov fp, sl + 800d3dc: f816 0c01 ldrb.w r0, [r6, #-1] + 800d3e0: f7ff fede bl 800d1a0 <__hexdig_fun> + 800d3e4: f000 000f and.w r0, r0, #15 + 800d3e8: fa00 f00b lsl.w r0, r0, fp + 800d3ec: ea4a 0a00 orr.w sl, sl, r0 + 800d3f0: f10b 0b04 add.w fp, fp, #4 + 800d3f4: 9b05 ldr r3, [sp, #20] + 800d3f6: e00d b.n 800d414 <__gethex+0x24a> + 800d3f8: 9b05 ldr r3, [sp, #20] + 800d3fa: 9a08 ldr r2, [sp, #32] + 800d3fc: 4413 add r3, r2 + 800d3fe: 42bb cmp r3, r7 + 800d400: d3e1 bcc.n 800d3c6 <__gethex+0x1fc> + 800d402: 4618 mov r0, r3 + 800d404: 9a01 ldr r2, [sp, #4] + 800d406: 9903 ldr r1, [sp, #12] + 800d408: 9309 str r3, [sp, #36] ; 0x24 + 800d40a: f001 f92e bl 800e66a + 800d40e: 9b09 ldr r3, [sp, #36] ; 0x24 + 800d410: 2800 cmp r0, #0 + 800d412: d1d8 bne.n 800d3c6 <__gethex+0x1fc> + 800d414: 461e mov r6, r3 + 800d416: e791 b.n 800d33c <__gethex+0x172> + 800d418: 1eb9 subs r1, r7, #2 + 800d41a: 4628 mov r0, r5 + 800d41c: f000 fe20 bl 800e060 <__any_on> + 800d420: 2800 cmp r0, #0 + 800d422: d0b2 beq.n 800d38a <__gethex+0x1c0> + 800d424: f04f 0a03 mov.w sl, #3 + 800d428: e7b1 b.n 800d38e <__gethex+0x1c4> + 800d42a: da09 bge.n 800d440 <__gethex+0x276> + 800d42c: 1bf7 subs r7, r6, r7 + 800d42e: 4629 mov r1, r5 + 800d430: 463a mov r2, r7 + 800d432: 9802 ldr r0, [sp, #8] + 800d434: f000 fc36 bl 800dca4 <__lshift> + 800d438: 1be4 subs r4, r4, r7 + 800d43a: 4605 mov r5, r0 + 800d43c: f100 0914 add.w r9, r0, #20 + 800d440: f04f 0a00 mov.w sl, #0 + 800d444: e7a8 b.n 800d398 <__gethex+0x1ce> + 800d446: f8d8 0004 ldr.w r0, [r8, #4] + 800d44a: 42a0 cmp r0, r4 + 800d44c: dd6a ble.n 800d524 <__gethex+0x35a> + 800d44e: 1b04 subs r4, r0, r4 + 800d450: 42a6 cmp r6, r4 + 800d452: dc2e bgt.n 800d4b2 <__gethex+0x2e8> + 800d454: f8d8 300c ldr.w r3, [r8, #12] + 800d458: 2b02 cmp r3, #2 + 800d45a: d022 beq.n 800d4a2 <__gethex+0x2d8> + 800d45c: 2b03 cmp r3, #3 + 800d45e: d024 beq.n 800d4aa <__gethex+0x2e0> + 800d460: 2b01 cmp r3, #1 + 800d462: d115 bne.n 800d490 <__gethex+0x2c6> + 800d464: 42a6 cmp r6, r4 + 800d466: d113 bne.n 800d490 <__gethex+0x2c6> + 800d468: 2e01 cmp r6, #1 + 800d46a: dc0b bgt.n 800d484 <__gethex+0x2ba> + 800d46c: 9a06 ldr r2, [sp, #24] + 800d46e: f8d8 3004 ldr.w r3, [r8, #4] + 800d472: 6013 str r3, [r2, #0] + 800d474: 2301 movs r3, #1 + 800d476: 612b str r3, [r5, #16] + 800d478: f8c9 3000 str.w r3, [r9] + 800d47c: 9b14 ldr r3, [sp, #80] ; 0x50 + 800d47e: 2762 movs r7, #98 ; 0x62 + 800d480: 601d str r5, [r3, #0] + 800d482: e72a b.n 800d2da <__gethex+0x110> + 800d484: 1e71 subs r1, r6, #1 + 800d486: 4628 mov r0, r5 + 800d488: f000 fdea bl 800e060 <__any_on> + 800d48c: 2800 cmp r0, #0 + 800d48e: d1ed bne.n 800d46c <__gethex+0x2a2> + 800d490: 4629 mov r1, r5 + 800d492: 9802 ldr r0, [sp, #8] + 800d494: f000 fa3b bl 800d90e <_Bfree> + 800d498: 9a14 ldr r2, [sp, #80] ; 0x50 + 800d49a: 2300 movs r3, #0 + 800d49c: 6013 str r3, [r2, #0] + 800d49e: 2750 movs r7, #80 ; 0x50 + 800d4a0: e71b b.n 800d2da <__gethex+0x110> + 800d4a2: 9b15 ldr r3, [sp, #84] ; 0x54 + 800d4a4: 2b00 cmp r3, #0 + 800d4a6: d0e1 beq.n 800d46c <__gethex+0x2a2> + 800d4a8: e7f2 b.n 800d490 <__gethex+0x2c6> + 800d4aa: 9b15 ldr r3, [sp, #84] ; 0x54 + 800d4ac: 2b00 cmp r3, #0 + 800d4ae: d1dd bne.n 800d46c <__gethex+0x2a2> + 800d4b0: e7ee b.n 800d490 <__gethex+0x2c6> + 800d4b2: 1e67 subs r7, r4, #1 + 800d4b4: f1ba 0f00 cmp.w sl, #0 + 800d4b8: d131 bne.n 800d51e <__gethex+0x354> + 800d4ba: b127 cbz r7, 800d4c6 <__gethex+0x2fc> + 800d4bc: 4639 mov r1, r7 + 800d4be: 4628 mov r0, r5 + 800d4c0: f000 fdce bl 800e060 <__any_on> + 800d4c4: 4682 mov sl, r0 + 800d4c6: 117a asrs r2, r7, #5 + 800d4c8: 2301 movs r3, #1 + 800d4ca: f007 071f and.w r7, r7, #31 + 800d4ce: fa03 f707 lsl.w r7, r3, r7 + 800d4d2: f859 3022 ldr.w r3, [r9, r2, lsl #2] + 800d4d6: 4621 mov r1, r4 + 800d4d8: 421f tst r7, r3 + 800d4da: 4628 mov r0, r5 + 800d4dc: bf18 it ne + 800d4de: f04a 0a02 orrne.w sl, sl, #2 + 800d4e2: 1b36 subs r6, r6, r4 + 800d4e4: f7ff fe22 bl 800d12c + 800d4e8: f8d8 4004 ldr.w r4, [r8, #4] + 800d4ec: 2702 movs r7, #2 + 800d4ee: f1ba 0f00 cmp.w sl, #0 + 800d4f2: d048 beq.n 800d586 <__gethex+0x3bc> + 800d4f4: f8d8 300c ldr.w r3, [r8, #12] + 800d4f8: 2b02 cmp r3, #2 + 800d4fa: d015 beq.n 800d528 <__gethex+0x35e> + 800d4fc: 2b03 cmp r3, #3 + 800d4fe: d017 beq.n 800d530 <__gethex+0x366> + 800d500: 2b01 cmp r3, #1 + 800d502: d109 bne.n 800d518 <__gethex+0x34e> + 800d504: f01a 0f02 tst.w sl, #2 + 800d508: d006 beq.n 800d518 <__gethex+0x34e> + 800d50a: f8d9 3000 ldr.w r3, [r9] + 800d50e: ea4a 0a03 orr.w sl, sl, r3 + 800d512: f01a 0f01 tst.w sl, #1 + 800d516: d10e bne.n 800d536 <__gethex+0x36c> + 800d518: f047 0710 orr.w r7, r7, #16 + 800d51c: e033 b.n 800d586 <__gethex+0x3bc> + 800d51e: f04f 0a01 mov.w sl, #1 + 800d522: e7d0 b.n 800d4c6 <__gethex+0x2fc> + 800d524: 2701 movs r7, #1 + 800d526: e7e2 b.n 800d4ee <__gethex+0x324> + 800d528: 9b15 ldr r3, [sp, #84] ; 0x54 + 800d52a: f1c3 0301 rsb r3, r3, #1 + 800d52e: 9315 str r3, [sp, #84] ; 0x54 + 800d530: 9b15 ldr r3, [sp, #84] ; 0x54 + 800d532: 2b00 cmp r3, #0 + 800d534: d0f0 beq.n 800d518 <__gethex+0x34e> + 800d536: f8d5 9010 ldr.w r9, [r5, #16] + 800d53a: f105 0314 add.w r3, r5, #20 + 800d53e: ea4f 0a89 mov.w sl, r9, lsl #2 + 800d542: eb03 010a add.w r1, r3, sl + 800d546: f04f 0c00 mov.w ip, #0 + 800d54a: 4618 mov r0, r3 + 800d54c: f853 2b04 ldr.w r2, [r3], #4 + 800d550: f1b2 3fff cmp.w r2, #4294967295 + 800d554: d01c beq.n 800d590 <__gethex+0x3c6> + 800d556: 3201 adds r2, #1 + 800d558: 6002 str r2, [r0, #0] + 800d55a: 2f02 cmp r7, #2 + 800d55c: f105 0314 add.w r3, r5, #20 + 800d560: d138 bne.n 800d5d4 <__gethex+0x40a> + 800d562: f8d8 2000 ldr.w r2, [r8] + 800d566: 3a01 subs r2, #1 + 800d568: 42b2 cmp r2, r6 + 800d56a: d10a bne.n 800d582 <__gethex+0x3b8> + 800d56c: 1171 asrs r1, r6, #5 + 800d56e: 2201 movs r2, #1 + 800d570: f006 061f and.w r6, r6, #31 + 800d574: f853 3021 ldr.w r3, [r3, r1, lsl #2] + 800d578: fa02 f606 lsl.w r6, r2, r6 + 800d57c: 421e tst r6, r3 + 800d57e: bf18 it ne + 800d580: 4617 movne r7, r2 + 800d582: f047 0720 orr.w r7, r7, #32 + 800d586: 9b14 ldr r3, [sp, #80] ; 0x50 + 800d588: 601d str r5, [r3, #0] + 800d58a: 9b06 ldr r3, [sp, #24] + 800d58c: 601c str r4, [r3, #0] + 800d58e: e6a4 b.n 800d2da <__gethex+0x110> + 800d590: 4299 cmp r1, r3 + 800d592: f843 cc04 str.w ip, [r3, #-4] + 800d596: d8d8 bhi.n 800d54a <__gethex+0x380> + 800d598: 68ab ldr r3, [r5, #8] + 800d59a: 4599 cmp r9, r3 + 800d59c: db12 blt.n 800d5c4 <__gethex+0x3fa> + 800d59e: 6869 ldr r1, [r5, #4] + 800d5a0: 9802 ldr r0, [sp, #8] + 800d5a2: 3101 adds r1, #1 + 800d5a4: f000 f97f bl 800d8a6 <_Balloc> + 800d5a8: 692a ldr r2, [r5, #16] + 800d5aa: 3202 adds r2, #2 + 800d5ac: f105 010c add.w r1, r5, #12 + 800d5b0: 4683 mov fp, r0 + 800d5b2: 0092 lsls r2, r2, #2 + 800d5b4: 300c adds r0, #12 + 800d5b6: f000 f969 bl 800d88c + 800d5ba: 4629 mov r1, r5 + 800d5bc: 9802 ldr r0, [sp, #8] + 800d5be: f000 f9a6 bl 800d90e <_Bfree> + 800d5c2: 465d mov r5, fp + 800d5c4: 692b ldr r3, [r5, #16] + 800d5c6: 1c5a adds r2, r3, #1 + 800d5c8: eb05 0383 add.w r3, r5, r3, lsl #2 + 800d5cc: 612a str r2, [r5, #16] + 800d5ce: 2201 movs r2, #1 + 800d5d0: 615a str r2, [r3, #20] + 800d5d2: e7c2 b.n 800d55a <__gethex+0x390> + 800d5d4: 692a ldr r2, [r5, #16] + 800d5d6: 454a cmp r2, r9 + 800d5d8: dd0b ble.n 800d5f2 <__gethex+0x428> + 800d5da: 2101 movs r1, #1 + 800d5dc: 4628 mov r0, r5 + 800d5de: f7ff fda5 bl 800d12c + 800d5e2: f8d8 3008 ldr.w r3, [r8, #8] + 800d5e6: 3401 adds r4, #1 + 800d5e8: 42a3 cmp r3, r4 + 800d5ea: f6ff aed9 blt.w 800d3a0 <__gethex+0x1d6> + 800d5ee: 2701 movs r7, #1 + 800d5f0: e7c7 b.n 800d582 <__gethex+0x3b8> + 800d5f2: f016 061f ands.w r6, r6, #31 + 800d5f6: d0fa beq.n 800d5ee <__gethex+0x424> + 800d5f8: 449a add sl, r3 + 800d5fa: f1c6 0620 rsb r6, r6, #32 + 800d5fe: f85a 0c04 ldr.w r0, [sl, #-4] + 800d602: f000 fa14 bl 800da2e <__hi0bits> + 800d606: 42b0 cmp r0, r6 + 800d608: dbe7 blt.n 800d5da <__gethex+0x410> + 800d60a: e7f0 b.n 800d5ee <__gethex+0x424> + +0800d60c : + 800d60c: f1c2 0208 rsb r2, r2, #8 + 800d610: 0092 lsls r2, r2, #2 + 800d612: b570 push {r4, r5, r6, lr} + 800d614: f1c2 0620 rsb r6, r2, #32 + 800d618: 6843 ldr r3, [r0, #4] + 800d61a: 6804 ldr r4, [r0, #0] + 800d61c: fa03 f506 lsl.w r5, r3, r6 + 800d620: 432c orrs r4, r5 + 800d622: 40d3 lsrs r3, r2 + 800d624: 6004 str r4, [r0, #0] + 800d626: f840 3f04 str.w r3, [r0, #4]! + 800d62a: 4288 cmp r0, r1 + 800d62c: d3f4 bcc.n 800d618 + 800d62e: bd70 pop {r4, r5, r6, pc} + +0800d630 <__match>: + 800d630: b530 push {r4, r5, lr} + 800d632: 6803 ldr r3, [r0, #0] + 800d634: 3301 adds r3, #1 + 800d636: f811 4b01 ldrb.w r4, [r1], #1 + 800d63a: b914 cbnz r4, 800d642 <__match+0x12> + 800d63c: 6003 str r3, [r0, #0] + 800d63e: 2001 movs r0, #1 + 800d640: bd30 pop {r4, r5, pc} + 800d642: f813 2b01 ldrb.w r2, [r3], #1 + 800d646: f1a2 0541 sub.w r5, r2, #65 ; 0x41 + 800d64a: 2d19 cmp r5, #25 + 800d64c: bf98 it ls + 800d64e: 3220 addls r2, #32 + 800d650: 42a2 cmp r2, r4 + 800d652: d0f0 beq.n 800d636 <__match+0x6> + 800d654: 2000 movs r0, #0 + 800d656: e7f3 b.n 800d640 <__match+0x10> + +0800d658 <__hexnan>: + 800d658: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 800d65c: 680b ldr r3, [r1, #0] + 800d65e: 6801 ldr r1, [r0, #0] + 800d660: 115f asrs r7, r3, #5 + 800d662: eb02 0787 add.w r7, r2, r7, lsl #2 + 800d666: f013 031f ands.w r3, r3, #31 + 800d66a: b087 sub sp, #28 + 800d66c: bf18 it ne + 800d66e: 3704 addne r7, #4 + 800d670: 2500 movs r5, #0 + 800d672: 1f3e subs r6, r7, #4 + 800d674: 4682 mov sl, r0 + 800d676: 4690 mov r8, r2 + 800d678: 9301 str r3, [sp, #4] + 800d67a: f847 5c04 str.w r5, [r7, #-4] + 800d67e: 46b1 mov r9, r6 + 800d680: 4634 mov r4, r6 + 800d682: 9502 str r5, [sp, #8] + 800d684: 46ab mov fp, r5 + 800d686: 784a ldrb r2, [r1, #1] + 800d688: 1c4b adds r3, r1, #1 + 800d68a: 9303 str r3, [sp, #12] + 800d68c: b342 cbz r2, 800d6e0 <__hexnan+0x88> + 800d68e: 4610 mov r0, r2 + 800d690: 9105 str r1, [sp, #20] + 800d692: 9204 str r2, [sp, #16] + 800d694: f7ff fd84 bl 800d1a0 <__hexdig_fun> + 800d698: 2800 cmp r0, #0 + 800d69a: d143 bne.n 800d724 <__hexnan+0xcc> + 800d69c: 9a04 ldr r2, [sp, #16] + 800d69e: 9905 ldr r1, [sp, #20] + 800d6a0: 2a20 cmp r2, #32 + 800d6a2: d818 bhi.n 800d6d6 <__hexnan+0x7e> + 800d6a4: 9b02 ldr r3, [sp, #8] + 800d6a6: 459b cmp fp, r3 + 800d6a8: dd13 ble.n 800d6d2 <__hexnan+0x7a> + 800d6aa: 454c cmp r4, r9 + 800d6ac: d206 bcs.n 800d6bc <__hexnan+0x64> + 800d6ae: 2d07 cmp r5, #7 + 800d6b0: dc04 bgt.n 800d6bc <__hexnan+0x64> + 800d6b2: 462a mov r2, r5 + 800d6b4: 4649 mov r1, r9 + 800d6b6: 4620 mov r0, r4 + 800d6b8: f7ff ffa8 bl 800d60c + 800d6bc: 4544 cmp r4, r8 + 800d6be: d944 bls.n 800d74a <__hexnan+0xf2> + 800d6c0: 2300 movs r3, #0 + 800d6c2: f1a4 0904 sub.w r9, r4, #4 + 800d6c6: f844 3c04 str.w r3, [r4, #-4] + 800d6ca: f8cd b008 str.w fp, [sp, #8] + 800d6ce: 464c mov r4, r9 + 800d6d0: 461d mov r5, r3 + 800d6d2: 9903 ldr r1, [sp, #12] + 800d6d4: e7d7 b.n 800d686 <__hexnan+0x2e> + 800d6d6: 2a29 cmp r2, #41 ; 0x29 + 800d6d8: d14a bne.n 800d770 <__hexnan+0x118> + 800d6da: 3102 adds r1, #2 + 800d6dc: f8ca 1000 str.w r1, [sl] + 800d6e0: f1bb 0f00 cmp.w fp, #0 + 800d6e4: d044 beq.n 800d770 <__hexnan+0x118> + 800d6e6: 454c cmp r4, r9 + 800d6e8: d206 bcs.n 800d6f8 <__hexnan+0xa0> + 800d6ea: 2d07 cmp r5, #7 + 800d6ec: dc04 bgt.n 800d6f8 <__hexnan+0xa0> + 800d6ee: 462a mov r2, r5 + 800d6f0: 4649 mov r1, r9 + 800d6f2: 4620 mov r0, r4 + 800d6f4: f7ff ff8a bl 800d60c + 800d6f8: 4544 cmp r4, r8 + 800d6fa: d928 bls.n 800d74e <__hexnan+0xf6> + 800d6fc: 4643 mov r3, r8 + 800d6fe: f854 2b04 ldr.w r2, [r4], #4 + 800d702: f843 2b04 str.w r2, [r3], #4 + 800d706: 42a6 cmp r6, r4 + 800d708: d2f9 bcs.n 800d6fe <__hexnan+0xa6> + 800d70a: 2200 movs r2, #0 + 800d70c: f843 2b04 str.w r2, [r3], #4 + 800d710: 429e cmp r6, r3 + 800d712: d2fb bcs.n 800d70c <__hexnan+0xb4> + 800d714: 6833 ldr r3, [r6, #0] + 800d716: b91b cbnz r3, 800d720 <__hexnan+0xc8> + 800d718: 4546 cmp r6, r8 + 800d71a: d127 bne.n 800d76c <__hexnan+0x114> + 800d71c: 2301 movs r3, #1 + 800d71e: 6033 str r3, [r6, #0] + 800d720: 2005 movs r0, #5 + 800d722: e026 b.n 800d772 <__hexnan+0x11a> + 800d724: 3501 adds r5, #1 + 800d726: 2d08 cmp r5, #8 + 800d728: f10b 0b01 add.w fp, fp, #1 + 800d72c: dd06 ble.n 800d73c <__hexnan+0xe4> + 800d72e: 4544 cmp r4, r8 + 800d730: d9cf bls.n 800d6d2 <__hexnan+0x7a> + 800d732: 2300 movs r3, #0 + 800d734: f844 3c04 str.w r3, [r4, #-4] + 800d738: 2501 movs r5, #1 + 800d73a: 3c04 subs r4, #4 + 800d73c: 6822 ldr r2, [r4, #0] + 800d73e: f000 000f and.w r0, r0, #15 + 800d742: ea40 1002 orr.w r0, r0, r2, lsl #4 + 800d746: 6020 str r0, [r4, #0] + 800d748: e7c3 b.n 800d6d2 <__hexnan+0x7a> + 800d74a: 2508 movs r5, #8 + 800d74c: e7c1 b.n 800d6d2 <__hexnan+0x7a> + 800d74e: 9b01 ldr r3, [sp, #4] + 800d750: 2b00 cmp r3, #0 + 800d752: d0df beq.n 800d714 <__hexnan+0xbc> + 800d754: f04f 32ff mov.w r2, #4294967295 + 800d758: f1c3 0320 rsb r3, r3, #32 + 800d75c: fa22 f303 lsr.w r3, r2, r3 + 800d760: f857 2c04 ldr.w r2, [r7, #-4] + 800d764: 401a ands r2, r3 + 800d766: f847 2c04 str.w r2, [r7, #-4] + 800d76a: e7d3 b.n 800d714 <__hexnan+0xbc> + 800d76c: 3e04 subs r6, #4 + 800d76e: e7d1 b.n 800d714 <__hexnan+0xbc> + 800d770: 2004 movs r0, #4 + 800d772: b007 add sp, #28 + 800d774: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + +0800d778 <__locale_ctype_ptr_l>: + 800d778: f8d0 00ec ldr.w r0, [r0, #236] ; 0xec + 800d77c: 4770 bx lr + +0800d77e <__localeconv_l>: + 800d77e: 30f0 adds r0, #240 ; 0xf0 + 800d780: 4770 bx lr + ... + +0800d784 <_localeconv_r>: + 800d784: 4b04 ldr r3, [pc, #16] ; (800d798 <_localeconv_r+0x14>) + 800d786: 681b ldr r3, [r3, #0] + 800d788: 6a18 ldr r0, [r3, #32] + 800d78a: 4b04 ldr r3, [pc, #16] ; (800d79c <_localeconv_r+0x18>) + 800d78c: 2800 cmp r0, #0 + 800d78e: bf08 it eq + 800d790: 4618 moveq r0, r3 + 800d792: 30f0 adds r0, #240 ; 0xf0 + 800d794: 4770 bx lr + 800d796: bf00 nop + 800d798: 2000002c .word 0x2000002c + 800d79c: 20000090 .word 0x20000090 + +0800d7a0 <__swhatbuf_r>: + 800d7a0: b570 push {r4, r5, r6, lr} + 800d7a2: 460e mov r6, r1 + 800d7a4: f9b1 100e ldrsh.w r1, [r1, #14] + 800d7a8: 2900 cmp r1, #0 + 800d7aa: b096 sub sp, #88 ; 0x58 + 800d7ac: 4614 mov r4, r2 + 800d7ae: 461d mov r5, r3 + 800d7b0: da07 bge.n 800d7c2 <__swhatbuf_r+0x22> + 800d7b2: 2300 movs r3, #0 + 800d7b4: 602b str r3, [r5, #0] + 800d7b6: 89b3 ldrh r3, [r6, #12] + 800d7b8: 061a lsls r2, r3, #24 + 800d7ba: d410 bmi.n 800d7de <__swhatbuf_r+0x3e> + 800d7bc: f44f 6380 mov.w r3, #1024 ; 0x400 + 800d7c0: e00e b.n 800d7e0 <__swhatbuf_r+0x40> + 800d7c2: 466a mov r2, sp + 800d7c4: f000 ff92 bl 800e6ec <_fstat_r> + 800d7c8: 2800 cmp r0, #0 + 800d7ca: dbf2 blt.n 800d7b2 <__swhatbuf_r+0x12> + 800d7cc: 9a01 ldr r2, [sp, #4] + 800d7ce: f402 4270 and.w r2, r2, #61440 ; 0xf000 + 800d7d2: f5a2 5300 sub.w r3, r2, #8192 ; 0x2000 + 800d7d6: 425a negs r2, r3 + 800d7d8: 415a adcs r2, r3 + 800d7da: 602a str r2, [r5, #0] + 800d7dc: e7ee b.n 800d7bc <__swhatbuf_r+0x1c> + 800d7de: 2340 movs r3, #64 ; 0x40 + 800d7e0: 2000 movs r0, #0 + 800d7e2: 6023 str r3, [r4, #0] + 800d7e4: b016 add sp, #88 ; 0x58 + 800d7e6: bd70 pop {r4, r5, r6, pc} + +0800d7e8 <__smakebuf_r>: + 800d7e8: 898b ldrh r3, [r1, #12] + 800d7ea: b573 push {r0, r1, r4, r5, r6, lr} + 800d7ec: 079d lsls r5, r3, #30 + 800d7ee: 4606 mov r6, r0 + 800d7f0: 460c mov r4, r1 + 800d7f2: d507 bpl.n 800d804 <__smakebuf_r+0x1c> + 800d7f4: f104 0347 add.w r3, r4, #71 ; 0x47 + 800d7f8: 6023 str r3, [r4, #0] + 800d7fa: 6123 str r3, [r4, #16] + 800d7fc: 2301 movs r3, #1 + 800d7fe: 6163 str r3, [r4, #20] + 800d800: b002 add sp, #8 + 800d802: bd70 pop {r4, r5, r6, pc} + 800d804: ab01 add r3, sp, #4 + 800d806: 466a mov r2, sp + 800d808: f7ff ffca bl 800d7a0 <__swhatbuf_r> + 800d80c: 9900 ldr r1, [sp, #0] + 800d80e: 4605 mov r5, r0 + 800d810: 4630 mov r0, r6 + 800d812: f7fc fe13 bl 800a43c <_malloc_r> + 800d816: b948 cbnz r0, 800d82c <__smakebuf_r+0x44> + 800d818: f9b4 300c ldrsh.w r3, [r4, #12] + 800d81c: 059a lsls r2, r3, #22 + 800d81e: d4ef bmi.n 800d800 <__smakebuf_r+0x18> + 800d820: f023 0303 bic.w r3, r3, #3 + 800d824: f043 0302 orr.w r3, r3, #2 + 800d828: 81a3 strh r3, [r4, #12] + 800d82a: e7e3 b.n 800d7f4 <__smakebuf_r+0xc> + 800d82c: 4b0d ldr r3, [pc, #52] ; (800d864 <__smakebuf_r+0x7c>) + 800d82e: 62b3 str r3, [r6, #40] ; 0x28 + 800d830: 89a3 ldrh r3, [r4, #12] + 800d832: 6020 str r0, [r4, #0] + 800d834: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800d838: 81a3 strh r3, [r4, #12] + 800d83a: 9b00 ldr r3, [sp, #0] + 800d83c: 6163 str r3, [r4, #20] + 800d83e: 9b01 ldr r3, [sp, #4] + 800d840: 6120 str r0, [r4, #16] + 800d842: b15b cbz r3, 800d85c <__smakebuf_r+0x74> + 800d844: f9b4 100e ldrsh.w r1, [r4, #14] + 800d848: 4630 mov r0, r6 + 800d84a: f000 ff61 bl 800e710 <_isatty_r> + 800d84e: b128 cbz r0, 800d85c <__smakebuf_r+0x74> + 800d850: 89a3 ldrh r3, [r4, #12] + 800d852: f023 0303 bic.w r3, r3, #3 + 800d856: f043 0301 orr.w r3, r3, #1 + 800d85a: 81a3 strh r3, [r4, #12] + 800d85c: 89a3 ldrh r3, [r4, #12] + 800d85e: 431d orrs r5, r3 + 800d860: 81a5 strh r5, [r4, #12] + 800d862: e7cd b.n 800d800 <__smakebuf_r+0x18> + 800d864: 0800cfe1 .word 0x0800cfe1 + +0800d868 <__ascii_mbtowc>: + 800d868: b082 sub sp, #8 + 800d86a: b901 cbnz r1, 800d86e <__ascii_mbtowc+0x6> + 800d86c: a901 add r1, sp, #4 + 800d86e: b142 cbz r2, 800d882 <__ascii_mbtowc+0x1a> + 800d870: b14b cbz r3, 800d886 <__ascii_mbtowc+0x1e> + 800d872: 7813 ldrb r3, [r2, #0] + 800d874: 600b str r3, [r1, #0] + 800d876: 7812 ldrb r2, [r2, #0] + 800d878: 1c10 adds r0, r2, #0 + 800d87a: bf18 it ne + 800d87c: 2001 movne r0, #1 + 800d87e: b002 add sp, #8 + 800d880: 4770 bx lr + 800d882: 4610 mov r0, r2 + 800d884: e7fb b.n 800d87e <__ascii_mbtowc+0x16> + 800d886: f06f 0001 mvn.w r0, #1 + 800d88a: e7f8 b.n 800d87e <__ascii_mbtowc+0x16> + +0800d88c : + 800d88c: b510 push {r4, lr} + 800d88e: 1e43 subs r3, r0, #1 + 800d890: 440a add r2, r1 + 800d892: 4291 cmp r1, r2 + 800d894: d100 bne.n 800d898 + 800d896: bd10 pop {r4, pc} + 800d898: f811 4b01 ldrb.w r4, [r1], #1 + 800d89c: f803 4f01 strb.w r4, [r3, #1]! + 800d8a0: e7f7 b.n 800d892 + +0800d8a2 <__malloc_lock>: + 800d8a2: 4770 bx lr + +0800d8a4 <__malloc_unlock>: + 800d8a4: 4770 bx lr + +0800d8a6 <_Balloc>: + 800d8a6: b570 push {r4, r5, r6, lr} + 800d8a8: 6a45 ldr r5, [r0, #36] ; 0x24 + 800d8aa: 4604 mov r4, r0 + 800d8ac: 460e mov r6, r1 + 800d8ae: b93d cbnz r5, 800d8c0 <_Balloc+0x1a> + 800d8b0: 2010 movs r0, #16 + 800d8b2: f7fc fd5d bl 800a370 + 800d8b6: 6260 str r0, [r4, #36] ; 0x24 + 800d8b8: e9c0 5501 strd r5, r5, [r0, #4] + 800d8bc: 6005 str r5, [r0, #0] + 800d8be: 60c5 str r5, [r0, #12] + 800d8c0: 6a65 ldr r5, [r4, #36] ; 0x24 + 800d8c2: 68eb ldr r3, [r5, #12] + 800d8c4: b183 cbz r3, 800d8e8 <_Balloc+0x42> + 800d8c6: 6a63 ldr r3, [r4, #36] ; 0x24 + 800d8c8: 68db ldr r3, [r3, #12] + 800d8ca: f853 0026 ldr.w r0, [r3, r6, lsl #2] + 800d8ce: b9b8 cbnz r0, 800d900 <_Balloc+0x5a> + 800d8d0: 2101 movs r1, #1 + 800d8d2: fa01 f506 lsl.w r5, r1, r6 + 800d8d6: 1d6a adds r2, r5, #5 + 800d8d8: 0092 lsls r2, r2, #2 + 800d8da: 4620 mov r0, r4 + 800d8dc: f000 fbe1 bl 800e0a2 <_calloc_r> + 800d8e0: b160 cbz r0, 800d8fc <_Balloc+0x56> + 800d8e2: e9c0 6501 strd r6, r5, [r0, #4] + 800d8e6: e00e b.n 800d906 <_Balloc+0x60> + 800d8e8: 2221 movs r2, #33 ; 0x21 + 800d8ea: 2104 movs r1, #4 + 800d8ec: 4620 mov r0, r4 + 800d8ee: f000 fbd8 bl 800e0a2 <_calloc_r> + 800d8f2: 6a63 ldr r3, [r4, #36] ; 0x24 + 800d8f4: 60e8 str r0, [r5, #12] + 800d8f6: 68db ldr r3, [r3, #12] + 800d8f8: 2b00 cmp r3, #0 + 800d8fa: d1e4 bne.n 800d8c6 <_Balloc+0x20> + 800d8fc: 2000 movs r0, #0 + 800d8fe: bd70 pop {r4, r5, r6, pc} + 800d900: 6802 ldr r2, [r0, #0] + 800d902: f843 2026 str.w r2, [r3, r6, lsl #2] + 800d906: 2300 movs r3, #0 + 800d908: e9c0 3303 strd r3, r3, [r0, #12] + 800d90c: e7f7 b.n 800d8fe <_Balloc+0x58> + +0800d90e <_Bfree>: + 800d90e: b570 push {r4, r5, r6, lr} + 800d910: 6a44 ldr r4, [r0, #36] ; 0x24 + 800d912: 4606 mov r6, r0 + 800d914: 460d mov r5, r1 + 800d916: b93c cbnz r4, 800d928 <_Bfree+0x1a> + 800d918: 2010 movs r0, #16 + 800d91a: f7fc fd29 bl 800a370 + 800d91e: 6270 str r0, [r6, #36] ; 0x24 + 800d920: e9c0 4401 strd r4, r4, [r0, #4] + 800d924: 6004 str r4, [r0, #0] + 800d926: 60c4 str r4, [r0, #12] + 800d928: b13d cbz r5, 800d93a <_Bfree+0x2c> + 800d92a: 6a73 ldr r3, [r6, #36] ; 0x24 + 800d92c: 686a ldr r2, [r5, #4] + 800d92e: 68db ldr r3, [r3, #12] + 800d930: f853 1022 ldr.w r1, [r3, r2, lsl #2] + 800d934: 6029 str r1, [r5, #0] + 800d936: f843 5022 str.w r5, [r3, r2, lsl #2] + 800d93a: bd70 pop {r4, r5, r6, pc} + +0800d93c <__multadd>: + 800d93c: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 800d940: 690d ldr r5, [r1, #16] + 800d942: 461f mov r7, r3 + 800d944: 4606 mov r6, r0 + 800d946: 460c mov r4, r1 + 800d948: f101 0c14 add.w ip, r1, #20 + 800d94c: 2300 movs r3, #0 + 800d94e: f8dc 0000 ldr.w r0, [ip] + 800d952: b281 uxth r1, r0 + 800d954: fb02 7101 mla r1, r2, r1, r7 + 800d958: 0c0f lsrs r7, r1, #16 + 800d95a: 0c00 lsrs r0, r0, #16 + 800d95c: fb02 7000 mla r0, r2, r0, r7 + 800d960: b289 uxth r1, r1 + 800d962: 3301 adds r3, #1 + 800d964: eb01 4100 add.w r1, r1, r0, lsl #16 + 800d968: 429d cmp r5, r3 + 800d96a: ea4f 4710 mov.w r7, r0, lsr #16 + 800d96e: f84c 1b04 str.w r1, [ip], #4 + 800d972: dcec bgt.n 800d94e <__multadd+0x12> + 800d974: b1d7 cbz r7, 800d9ac <__multadd+0x70> + 800d976: 68a3 ldr r3, [r4, #8] + 800d978: 42ab cmp r3, r5 + 800d97a: dc12 bgt.n 800d9a2 <__multadd+0x66> + 800d97c: 6861 ldr r1, [r4, #4] + 800d97e: 4630 mov r0, r6 + 800d980: 3101 adds r1, #1 + 800d982: f7ff ff90 bl 800d8a6 <_Balloc> + 800d986: 6922 ldr r2, [r4, #16] + 800d988: 3202 adds r2, #2 + 800d98a: f104 010c add.w r1, r4, #12 + 800d98e: 4680 mov r8, r0 + 800d990: 0092 lsls r2, r2, #2 + 800d992: 300c adds r0, #12 + 800d994: f7ff ff7a bl 800d88c + 800d998: 4621 mov r1, r4 + 800d99a: 4630 mov r0, r6 + 800d99c: f7ff ffb7 bl 800d90e <_Bfree> + 800d9a0: 4644 mov r4, r8 + 800d9a2: eb04 0385 add.w r3, r4, r5, lsl #2 + 800d9a6: 3501 adds r5, #1 + 800d9a8: 615f str r7, [r3, #20] + 800d9aa: 6125 str r5, [r4, #16] + 800d9ac: 4620 mov r0, r4 + 800d9ae: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + +0800d9b2 <__s2b>: + 800d9b2: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} + 800d9b6: 460c mov r4, r1 + 800d9b8: 4615 mov r5, r2 + 800d9ba: 461f mov r7, r3 + 800d9bc: 2209 movs r2, #9 + 800d9be: 3308 adds r3, #8 + 800d9c0: 4606 mov r6, r0 + 800d9c2: fb93 f3f2 sdiv r3, r3, r2 + 800d9c6: 2100 movs r1, #0 + 800d9c8: 2201 movs r2, #1 + 800d9ca: 429a cmp r2, r3 + 800d9cc: db20 blt.n 800da10 <__s2b+0x5e> + 800d9ce: 4630 mov r0, r6 + 800d9d0: f7ff ff69 bl 800d8a6 <_Balloc> + 800d9d4: 9b08 ldr r3, [sp, #32] + 800d9d6: 6143 str r3, [r0, #20] + 800d9d8: 2d09 cmp r5, #9 + 800d9da: f04f 0301 mov.w r3, #1 + 800d9de: 6103 str r3, [r0, #16] + 800d9e0: dd19 ble.n 800da16 <__s2b+0x64> + 800d9e2: f104 0809 add.w r8, r4, #9 + 800d9e6: 46c1 mov r9, r8 + 800d9e8: 442c add r4, r5 + 800d9ea: f819 3b01 ldrb.w r3, [r9], #1 + 800d9ee: 4601 mov r1, r0 + 800d9f0: 3b30 subs r3, #48 ; 0x30 + 800d9f2: 220a movs r2, #10 + 800d9f4: 4630 mov r0, r6 + 800d9f6: f7ff ffa1 bl 800d93c <__multadd> + 800d9fa: 45a1 cmp r9, r4 + 800d9fc: d1f5 bne.n 800d9ea <__s2b+0x38> + 800d9fe: eb08 0405 add.w r4, r8, r5 + 800da02: 3c08 subs r4, #8 + 800da04: 1b2d subs r5, r5, r4 + 800da06: 1963 adds r3, r4, r5 + 800da08: 42bb cmp r3, r7 + 800da0a: db07 blt.n 800da1c <__s2b+0x6a> + 800da0c: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} + 800da10: 0052 lsls r2, r2, #1 + 800da12: 3101 adds r1, #1 + 800da14: e7d9 b.n 800d9ca <__s2b+0x18> + 800da16: 340a adds r4, #10 + 800da18: 2509 movs r5, #9 + 800da1a: e7f3 b.n 800da04 <__s2b+0x52> + 800da1c: f814 3b01 ldrb.w r3, [r4], #1 + 800da20: 4601 mov r1, r0 + 800da22: 3b30 subs r3, #48 ; 0x30 + 800da24: 220a movs r2, #10 + 800da26: 4630 mov r0, r6 + 800da28: f7ff ff88 bl 800d93c <__multadd> + 800da2c: e7eb b.n 800da06 <__s2b+0x54> + +0800da2e <__hi0bits>: + 800da2e: 0c02 lsrs r2, r0, #16 + 800da30: 0412 lsls r2, r2, #16 + 800da32: 4603 mov r3, r0 + 800da34: b9b2 cbnz r2, 800da64 <__hi0bits+0x36> + 800da36: 0403 lsls r3, r0, #16 + 800da38: 2010 movs r0, #16 + 800da3a: f013 4f7f tst.w r3, #4278190080 ; 0xff000000 + 800da3e: bf04 itt eq + 800da40: 021b lsleq r3, r3, #8 + 800da42: 3008 addeq r0, #8 + 800da44: f013 4f70 tst.w r3, #4026531840 ; 0xf0000000 + 800da48: bf04 itt eq + 800da4a: 011b lsleq r3, r3, #4 + 800da4c: 3004 addeq r0, #4 + 800da4e: f013 4f40 tst.w r3, #3221225472 ; 0xc0000000 + 800da52: bf04 itt eq + 800da54: 009b lsleq r3, r3, #2 + 800da56: 3002 addeq r0, #2 + 800da58: 2b00 cmp r3, #0 + 800da5a: db06 blt.n 800da6a <__hi0bits+0x3c> + 800da5c: 005b lsls r3, r3, #1 + 800da5e: d503 bpl.n 800da68 <__hi0bits+0x3a> + 800da60: 3001 adds r0, #1 + 800da62: 4770 bx lr + 800da64: 2000 movs r0, #0 + 800da66: e7e8 b.n 800da3a <__hi0bits+0xc> + 800da68: 2020 movs r0, #32 + 800da6a: 4770 bx lr + +0800da6c <__lo0bits>: + 800da6c: 6803 ldr r3, [r0, #0] + 800da6e: f013 0207 ands.w r2, r3, #7 + 800da72: 4601 mov r1, r0 + 800da74: d00b beq.n 800da8e <__lo0bits+0x22> + 800da76: 07da lsls r2, r3, #31 + 800da78: d423 bmi.n 800dac2 <__lo0bits+0x56> + 800da7a: 0798 lsls r0, r3, #30 + 800da7c: bf49 itett mi + 800da7e: 085b lsrmi r3, r3, #1 + 800da80: 089b lsrpl r3, r3, #2 + 800da82: 2001 movmi r0, #1 + 800da84: 600b strmi r3, [r1, #0] + 800da86: bf5c itt pl + 800da88: 600b strpl r3, [r1, #0] + 800da8a: 2002 movpl r0, #2 + 800da8c: 4770 bx lr + 800da8e: b298 uxth r0, r3 + 800da90: b9a8 cbnz r0, 800dabe <__lo0bits+0x52> + 800da92: 0c1b lsrs r3, r3, #16 + 800da94: 2010 movs r0, #16 + 800da96: f013 0fff tst.w r3, #255 ; 0xff + 800da9a: bf04 itt eq + 800da9c: 0a1b lsreq r3, r3, #8 + 800da9e: 3008 addeq r0, #8 + 800daa0: 071a lsls r2, r3, #28 + 800daa2: bf04 itt eq + 800daa4: 091b lsreq r3, r3, #4 + 800daa6: 3004 addeq r0, #4 + 800daa8: 079a lsls r2, r3, #30 + 800daaa: bf04 itt eq + 800daac: 089b lsreq r3, r3, #2 + 800daae: 3002 addeq r0, #2 + 800dab0: 07da lsls r2, r3, #31 + 800dab2: d402 bmi.n 800daba <__lo0bits+0x4e> + 800dab4: 085b lsrs r3, r3, #1 + 800dab6: d006 beq.n 800dac6 <__lo0bits+0x5a> + 800dab8: 3001 adds r0, #1 + 800daba: 600b str r3, [r1, #0] + 800dabc: 4770 bx lr + 800dabe: 4610 mov r0, r2 + 800dac0: e7e9 b.n 800da96 <__lo0bits+0x2a> + 800dac2: 2000 movs r0, #0 + 800dac4: 4770 bx lr + 800dac6: 2020 movs r0, #32 + 800dac8: 4770 bx lr + +0800daca <__i2b>: + 800daca: b510 push {r4, lr} + 800dacc: 460c mov r4, r1 + 800dace: 2101 movs r1, #1 + 800dad0: f7ff fee9 bl 800d8a6 <_Balloc> + 800dad4: 2201 movs r2, #1 + 800dad6: 6144 str r4, [r0, #20] + 800dad8: 6102 str r2, [r0, #16] + 800dada: bd10 pop {r4, pc} + +0800dadc <__multiply>: + 800dadc: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} + 800dae0: 4614 mov r4, r2 + 800dae2: 690a ldr r2, [r1, #16] + 800dae4: 6923 ldr r3, [r4, #16] + 800dae6: 429a cmp r2, r3 + 800dae8: bfb8 it lt + 800daea: 460b movlt r3, r1 + 800daec: 4688 mov r8, r1 + 800daee: bfbc itt lt + 800daf0: 46a0 movlt r8, r4 + 800daf2: 461c movlt r4, r3 + 800daf4: f8d8 7010 ldr.w r7, [r8, #16] + 800daf8: f8d4 9010 ldr.w r9, [r4, #16] + 800dafc: f8d8 3008 ldr.w r3, [r8, #8] + 800db00: f8d8 1004 ldr.w r1, [r8, #4] + 800db04: eb07 0609 add.w r6, r7, r9 + 800db08: 42b3 cmp r3, r6 + 800db0a: bfb8 it lt + 800db0c: 3101 addlt r1, #1 + 800db0e: f7ff feca bl 800d8a6 <_Balloc> + 800db12: f100 0514 add.w r5, r0, #20 + 800db16: eb05 0e86 add.w lr, r5, r6, lsl #2 + 800db1a: 462b mov r3, r5 + 800db1c: 2200 movs r2, #0 + 800db1e: 4573 cmp r3, lr + 800db20: d316 bcc.n 800db50 <__multiply+0x74> + 800db22: f104 0214 add.w r2, r4, #20 + 800db26: f108 0114 add.w r1, r8, #20 + 800db2a: eb02 0389 add.w r3, r2, r9, lsl #2 + 800db2e: eb01 0787 add.w r7, r1, r7, lsl #2 + 800db32: 9300 str r3, [sp, #0] + 800db34: 9b00 ldr r3, [sp, #0] + 800db36: 9201 str r2, [sp, #4] + 800db38: 4293 cmp r3, r2 + 800db3a: d80c bhi.n 800db56 <__multiply+0x7a> + 800db3c: 2e00 cmp r6, #0 + 800db3e: dd03 ble.n 800db48 <__multiply+0x6c> + 800db40: f85e 3d04 ldr.w r3, [lr, #-4]! + 800db44: 2b00 cmp r3, #0 + 800db46: d05d beq.n 800dc04 <__multiply+0x128> + 800db48: 6106 str r6, [r0, #16] + 800db4a: b003 add sp, #12 + 800db4c: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 800db50: f843 2b04 str.w r2, [r3], #4 + 800db54: e7e3 b.n 800db1e <__multiply+0x42> + 800db56: f8b2 b000 ldrh.w fp, [r2] + 800db5a: f1bb 0f00 cmp.w fp, #0 + 800db5e: d023 beq.n 800dba8 <__multiply+0xcc> + 800db60: 4689 mov r9, r1 + 800db62: 46ac mov ip, r5 + 800db64: f04f 0800 mov.w r8, #0 + 800db68: f859 4b04 ldr.w r4, [r9], #4 + 800db6c: f8dc a000 ldr.w sl, [ip] + 800db70: b2a3 uxth r3, r4 + 800db72: fa1f fa8a uxth.w sl, sl + 800db76: fb0b a303 mla r3, fp, r3, sl + 800db7a: ea4f 4a14 mov.w sl, r4, lsr #16 + 800db7e: f8dc 4000 ldr.w r4, [ip] + 800db82: 4443 add r3, r8 + 800db84: ea4f 4814 mov.w r8, r4, lsr #16 + 800db88: fb0b 840a mla r4, fp, sl, r8 + 800db8c: eb04 4413 add.w r4, r4, r3, lsr #16 + 800db90: 46e2 mov sl, ip + 800db92: b29b uxth r3, r3 + 800db94: ea43 4304 orr.w r3, r3, r4, lsl #16 + 800db98: 454f cmp r7, r9 + 800db9a: ea4f 4814 mov.w r8, r4, lsr #16 + 800db9e: f84a 3b04 str.w r3, [sl], #4 + 800dba2: d82b bhi.n 800dbfc <__multiply+0x120> + 800dba4: f8cc 8004 str.w r8, [ip, #4] + 800dba8: 9b01 ldr r3, [sp, #4] + 800dbaa: f8b3 a002 ldrh.w sl, [r3, #2] + 800dbae: 3204 adds r2, #4 + 800dbb0: f1ba 0f00 cmp.w sl, #0 + 800dbb4: d020 beq.n 800dbf8 <__multiply+0x11c> + 800dbb6: 682b ldr r3, [r5, #0] + 800dbb8: 4689 mov r9, r1 + 800dbba: 46a8 mov r8, r5 + 800dbbc: f04f 0b00 mov.w fp, #0 + 800dbc0: f8b9 c000 ldrh.w ip, [r9] + 800dbc4: f8b8 4002 ldrh.w r4, [r8, #2] + 800dbc8: fb0a 440c mla r4, sl, ip, r4 + 800dbcc: 445c add r4, fp + 800dbce: 46c4 mov ip, r8 + 800dbd0: b29b uxth r3, r3 + 800dbd2: ea43 4304 orr.w r3, r3, r4, lsl #16 + 800dbd6: f84c 3b04 str.w r3, [ip], #4 + 800dbda: f859 3b04 ldr.w r3, [r9], #4 + 800dbde: f8b8 b004 ldrh.w fp, [r8, #4] + 800dbe2: 0c1b lsrs r3, r3, #16 + 800dbe4: fb0a b303 mla r3, sl, r3, fp + 800dbe8: eb03 4314 add.w r3, r3, r4, lsr #16 + 800dbec: 454f cmp r7, r9 + 800dbee: ea4f 4b13 mov.w fp, r3, lsr #16 + 800dbf2: d805 bhi.n 800dc00 <__multiply+0x124> + 800dbf4: f8c8 3004 str.w r3, [r8, #4] + 800dbf8: 3504 adds r5, #4 + 800dbfa: e79b b.n 800db34 <__multiply+0x58> + 800dbfc: 46d4 mov ip, sl + 800dbfe: e7b3 b.n 800db68 <__multiply+0x8c> + 800dc00: 46e0 mov r8, ip + 800dc02: e7dd b.n 800dbc0 <__multiply+0xe4> + 800dc04: 3e01 subs r6, #1 + 800dc06: e799 b.n 800db3c <__multiply+0x60> + +0800dc08 <__pow5mult>: + 800dc08: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} + 800dc0c: 4615 mov r5, r2 + 800dc0e: f012 0203 ands.w r2, r2, #3 + 800dc12: 4606 mov r6, r0 + 800dc14: 460f mov r7, r1 + 800dc16: d007 beq.n 800dc28 <__pow5mult+0x20> + 800dc18: 3a01 subs r2, #1 + 800dc1a: 4c21 ldr r4, [pc, #132] ; (800dca0 <__pow5mult+0x98>) + 800dc1c: 2300 movs r3, #0 + 800dc1e: f854 2022 ldr.w r2, [r4, r2, lsl #2] + 800dc22: f7ff fe8b bl 800d93c <__multadd> + 800dc26: 4607 mov r7, r0 + 800dc28: 10ad asrs r5, r5, #2 + 800dc2a: d035 beq.n 800dc98 <__pow5mult+0x90> + 800dc2c: 6a74 ldr r4, [r6, #36] ; 0x24 + 800dc2e: b93c cbnz r4, 800dc40 <__pow5mult+0x38> + 800dc30: 2010 movs r0, #16 + 800dc32: f7fc fb9d bl 800a370 + 800dc36: 6270 str r0, [r6, #36] ; 0x24 + 800dc38: e9c0 4401 strd r4, r4, [r0, #4] + 800dc3c: 6004 str r4, [r0, #0] + 800dc3e: 60c4 str r4, [r0, #12] + 800dc40: f8d6 8024 ldr.w r8, [r6, #36] ; 0x24 + 800dc44: f8d8 4008 ldr.w r4, [r8, #8] + 800dc48: b94c cbnz r4, 800dc5e <__pow5mult+0x56> + 800dc4a: f240 2171 movw r1, #625 ; 0x271 + 800dc4e: 4630 mov r0, r6 + 800dc50: f7ff ff3b bl 800daca <__i2b> + 800dc54: 2300 movs r3, #0 + 800dc56: f8c8 0008 str.w r0, [r8, #8] + 800dc5a: 4604 mov r4, r0 + 800dc5c: 6003 str r3, [r0, #0] + 800dc5e: f04f 0800 mov.w r8, #0 + 800dc62: 07eb lsls r3, r5, #31 + 800dc64: d50a bpl.n 800dc7c <__pow5mult+0x74> + 800dc66: 4639 mov r1, r7 + 800dc68: 4622 mov r2, r4 + 800dc6a: 4630 mov r0, r6 + 800dc6c: f7ff ff36 bl 800dadc <__multiply> + 800dc70: 4639 mov r1, r7 + 800dc72: 4681 mov r9, r0 + 800dc74: 4630 mov r0, r6 + 800dc76: f7ff fe4a bl 800d90e <_Bfree> + 800dc7a: 464f mov r7, r9 + 800dc7c: 106d asrs r5, r5, #1 + 800dc7e: d00b beq.n 800dc98 <__pow5mult+0x90> + 800dc80: 6820 ldr r0, [r4, #0] + 800dc82: b938 cbnz r0, 800dc94 <__pow5mult+0x8c> + 800dc84: 4622 mov r2, r4 + 800dc86: 4621 mov r1, r4 + 800dc88: 4630 mov r0, r6 + 800dc8a: f7ff ff27 bl 800dadc <__multiply> + 800dc8e: 6020 str r0, [r4, #0] + 800dc90: f8c0 8000 str.w r8, [r0] + 800dc94: 4604 mov r4, r0 + 800dc96: e7e4 b.n 800dc62 <__pow5mult+0x5a> + 800dc98: 4638 mov r0, r7 + 800dc9a: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} + 800dc9e: bf00 nop + 800dca0: 0800eb38 .word 0x0800eb38 + +0800dca4 <__lshift>: + 800dca4: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 800dca8: 460c mov r4, r1 + 800dcaa: ea4f 1a62 mov.w sl, r2, asr #5 + 800dcae: 6923 ldr r3, [r4, #16] + 800dcb0: 6849 ldr r1, [r1, #4] + 800dcb2: eb0a 0903 add.w r9, sl, r3 + 800dcb6: 68a3 ldr r3, [r4, #8] + 800dcb8: 4607 mov r7, r0 + 800dcba: 4616 mov r6, r2 + 800dcbc: f109 0501 add.w r5, r9, #1 + 800dcc0: 42ab cmp r3, r5 + 800dcc2: db32 blt.n 800dd2a <__lshift+0x86> + 800dcc4: 4638 mov r0, r7 + 800dcc6: f7ff fdee bl 800d8a6 <_Balloc> + 800dcca: 2300 movs r3, #0 + 800dccc: 4680 mov r8, r0 + 800dcce: f100 0114 add.w r1, r0, #20 + 800dcd2: 461a mov r2, r3 + 800dcd4: 4553 cmp r3, sl + 800dcd6: db2b blt.n 800dd30 <__lshift+0x8c> + 800dcd8: 6920 ldr r0, [r4, #16] + 800dcda: ea2a 7aea bic.w sl, sl, sl, asr #31 + 800dcde: f104 0314 add.w r3, r4, #20 + 800dce2: f016 021f ands.w r2, r6, #31 + 800dce6: eb01 018a add.w r1, r1, sl, lsl #2 + 800dcea: eb03 0c80 add.w ip, r3, r0, lsl #2 + 800dcee: d025 beq.n 800dd3c <__lshift+0x98> + 800dcf0: f1c2 0e20 rsb lr, r2, #32 + 800dcf4: 2000 movs r0, #0 + 800dcf6: 681e ldr r6, [r3, #0] + 800dcf8: 468a mov sl, r1 + 800dcfa: 4096 lsls r6, r2 + 800dcfc: 4330 orrs r0, r6 + 800dcfe: f84a 0b04 str.w r0, [sl], #4 + 800dd02: f853 0b04 ldr.w r0, [r3], #4 + 800dd06: 459c cmp ip, r3 + 800dd08: fa20 f00e lsr.w r0, r0, lr + 800dd0c: d814 bhi.n 800dd38 <__lshift+0x94> + 800dd0e: 6048 str r0, [r1, #4] + 800dd10: b108 cbz r0, 800dd16 <__lshift+0x72> + 800dd12: f109 0502 add.w r5, r9, #2 + 800dd16: 3d01 subs r5, #1 + 800dd18: 4638 mov r0, r7 + 800dd1a: f8c8 5010 str.w r5, [r8, #16] + 800dd1e: 4621 mov r1, r4 + 800dd20: f7ff fdf5 bl 800d90e <_Bfree> + 800dd24: 4640 mov r0, r8 + 800dd26: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 800dd2a: 3101 adds r1, #1 + 800dd2c: 005b lsls r3, r3, #1 + 800dd2e: e7c7 b.n 800dcc0 <__lshift+0x1c> + 800dd30: f841 2023 str.w r2, [r1, r3, lsl #2] + 800dd34: 3301 adds r3, #1 + 800dd36: e7cd b.n 800dcd4 <__lshift+0x30> + 800dd38: 4651 mov r1, sl + 800dd3a: e7dc b.n 800dcf6 <__lshift+0x52> + 800dd3c: 3904 subs r1, #4 + 800dd3e: f853 2b04 ldr.w r2, [r3], #4 + 800dd42: f841 2f04 str.w r2, [r1, #4]! + 800dd46: 459c cmp ip, r3 + 800dd48: d8f9 bhi.n 800dd3e <__lshift+0x9a> + 800dd4a: e7e4 b.n 800dd16 <__lshift+0x72> + +0800dd4c <__mcmp>: + 800dd4c: 6903 ldr r3, [r0, #16] + 800dd4e: 690a ldr r2, [r1, #16] + 800dd50: 1a9b subs r3, r3, r2 + 800dd52: b530 push {r4, r5, lr} + 800dd54: d10c bne.n 800dd70 <__mcmp+0x24> + 800dd56: 0092 lsls r2, r2, #2 + 800dd58: 3014 adds r0, #20 + 800dd5a: 3114 adds r1, #20 + 800dd5c: 1884 adds r4, r0, r2 + 800dd5e: 4411 add r1, r2 + 800dd60: f854 5d04 ldr.w r5, [r4, #-4]! + 800dd64: f851 2d04 ldr.w r2, [r1, #-4]! + 800dd68: 4295 cmp r5, r2 + 800dd6a: d003 beq.n 800dd74 <__mcmp+0x28> + 800dd6c: d305 bcc.n 800dd7a <__mcmp+0x2e> + 800dd6e: 2301 movs r3, #1 + 800dd70: 4618 mov r0, r3 + 800dd72: bd30 pop {r4, r5, pc} + 800dd74: 42a0 cmp r0, r4 + 800dd76: d3f3 bcc.n 800dd60 <__mcmp+0x14> + 800dd78: e7fa b.n 800dd70 <__mcmp+0x24> + 800dd7a: f04f 33ff mov.w r3, #4294967295 + 800dd7e: e7f7 b.n 800dd70 <__mcmp+0x24> + +0800dd80 <__mdiff>: + 800dd80: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 800dd84: 460d mov r5, r1 + 800dd86: 4607 mov r7, r0 + 800dd88: 4611 mov r1, r2 + 800dd8a: 4628 mov r0, r5 + 800dd8c: 4614 mov r4, r2 + 800dd8e: f7ff ffdd bl 800dd4c <__mcmp> + 800dd92: 1e06 subs r6, r0, #0 + 800dd94: d108 bne.n 800dda8 <__mdiff+0x28> + 800dd96: 4631 mov r1, r6 + 800dd98: 4638 mov r0, r7 + 800dd9a: f7ff fd84 bl 800d8a6 <_Balloc> + 800dd9e: 2301 movs r3, #1 + 800dda0: e9c0 3604 strd r3, r6, [r0, #16] + 800dda4: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 800dda8: bfa4 itt ge + 800ddaa: 4623 movge r3, r4 + 800ddac: 462c movge r4, r5 + 800ddae: 4638 mov r0, r7 + 800ddb0: 6861 ldr r1, [r4, #4] + 800ddb2: bfa6 itte ge + 800ddb4: 461d movge r5, r3 + 800ddb6: 2600 movge r6, #0 + 800ddb8: 2601 movlt r6, #1 + 800ddba: f7ff fd74 bl 800d8a6 <_Balloc> + 800ddbe: 692b ldr r3, [r5, #16] + 800ddc0: 60c6 str r6, [r0, #12] + 800ddc2: 6926 ldr r6, [r4, #16] + 800ddc4: f105 0914 add.w r9, r5, #20 + 800ddc8: f104 0214 add.w r2, r4, #20 + 800ddcc: eb02 0786 add.w r7, r2, r6, lsl #2 + 800ddd0: eb09 0883 add.w r8, r9, r3, lsl #2 + 800ddd4: f100 0514 add.w r5, r0, #20 + 800ddd8: f04f 0e00 mov.w lr, #0 + 800dddc: f852 ab04 ldr.w sl, [r2], #4 + 800dde0: f859 4b04 ldr.w r4, [r9], #4 + 800dde4: fa1e f18a uxtah r1, lr, sl + 800dde8: b2a3 uxth r3, r4 + 800ddea: 1ac9 subs r1, r1, r3 + 800ddec: 0c23 lsrs r3, r4, #16 + 800ddee: ebc3 431a rsb r3, r3, sl, lsr #16 + 800ddf2: eb03 4321 add.w r3, r3, r1, asr #16 + 800ddf6: b289 uxth r1, r1 + 800ddf8: ea4f 4e23 mov.w lr, r3, asr #16 + 800ddfc: 45c8 cmp r8, r9 + 800ddfe: ea41 4303 orr.w r3, r1, r3, lsl #16 + 800de02: 4694 mov ip, r2 + 800de04: f845 3b04 str.w r3, [r5], #4 + 800de08: d8e8 bhi.n 800dddc <__mdiff+0x5c> + 800de0a: 45bc cmp ip, r7 + 800de0c: d304 bcc.n 800de18 <__mdiff+0x98> + 800de0e: f855 3d04 ldr.w r3, [r5, #-4]! + 800de12: b183 cbz r3, 800de36 <__mdiff+0xb6> + 800de14: 6106 str r6, [r0, #16] + 800de16: e7c5 b.n 800dda4 <__mdiff+0x24> + 800de18: f85c 1b04 ldr.w r1, [ip], #4 + 800de1c: fa1e f381 uxtah r3, lr, r1 + 800de20: 141a asrs r2, r3, #16 + 800de22: eb02 4211 add.w r2, r2, r1, lsr #16 + 800de26: b29b uxth r3, r3 + 800de28: ea43 4302 orr.w r3, r3, r2, lsl #16 + 800de2c: ea4f 4e22 mov.w lr, r2, asr #16 + 800de30: f845 3b04 str.w r3, [r5], #4 + 800de34: e7e9 b.n 800de0a <__mdiff+0x8a> + 800de36: 3e01 subs r6, #1 + 800de38: e7e9 b.n 800de0e <__mdiff+0x8e> + ... + +0800de3c <__ulp>: + 800de3c: 4b12 ldr r3, [pc, #72] ; (800de88 <__ulp+0x4c>) + 800de3e: ee10 2a90 vmov r2, s1 + 800de42: 401a ands r2, r3 + 800de44: f1a2 7350 sub.w r3, r2, #54525952 ; 0x3400000 + 800de48: 2b00 cmp r3, #0 + 800de4a: dd04 ble.n 800de56 <__ulp+0x1a> + 800de4c: 2000 movs r0, #0 + 800de4e: 4619 mov r1, r3 + 800de50: ec41 0b10 vmov d0, r0, r1 + 800de54: 4770 bx lr + 800de56: 425b negs r3, r3 + 800de58: 151b asrs r3, r3, #20 + 800de5a: 2b13 cmp r3, #19 + 800de5c: f04f 0000 mov.w r0, #0 + 800de60: f04f 0100 mov.w r1, #0 + 800de64: dc04 bgt.n 800de70 <__ulp+0x34> + 800de66: f44f 2200 mov.w r2, #524288 ; 0x80000 + 800de6a: fa42 f103 asr.w r1, r2, r3 + 800de6e: e7ef b.n 800de50 <__ulp+0x14> + 800de70: 3b14 subs r3, #20 + 800de72: 2b1e cmp r3, #30 + 800de74: f04f 0201 mov.w r2, #1 + 800de78: bfda itte le + 800de7a: f1c3 031f rsble r3, r3, #31 + 800de7e: fa02 f303 lslle.w r3, r2, r3 + 800de82: 4613 movgt r3, r2 + 800de84: 4618 mov r0, r3 + 800de86: e7e3 b.n 800de50 <__ulp+0x14> + 800de88: 7ff00000 .word 0x7ff00000 + +0800de8c <__b2d>: + 800de8c: b5f8 push {r3, r4, r5, r6, r7, lr} + 800de8e: 6905 ldr r5, [r0, #16] + 800de90: f100 0714 add.w r7, r0, #20 + 800de94: eb07 0585 add.w r5, r7, r5, lsl #2 + 800de98: 1f2e subs r6, r5, #4 + 800de9a: f855 4c04 ldr.w r4, [r5, #-4] + 800de9e: 4620 mov r0, r4 + 800dea0: f7ff fdc5 bl 800da2e <__hi0bits> + 800dea4: f1c0 0320 rsb r3, r0, #32 + 800dea8: 280a cmp r0, #10 + 800deaa: 600b str r3, [r1, #0] + 800deac: f8df c074 ldr.w ip, [pc, #116] ; 800df24 <__b2d+0x98> + 800deb0: dc14 bgt.n 800dedc <__b2d+0x50> + 800deb2: f1c0 0e0b rsb lr, r0, #11 + 800deb6: fa24 f10e lsr.w r1, r4, lr + 800deba: 42b7 cmp r7, r6 + 800debc: ea41 030c orr.w r3, r1, ip + 800dec0: bf34 ite cc + 800dec2: f855 1c08 ldrcc.w r1, [r5, #-8] + 800dec6: 2100 movcs r1, #0 + 800dec8: 3015 adds r0, #21 + 800deca: fa04 f000 lsl.w r0, r4, r0 + 800dece: fa21 f10e lsr.w r1, r1, lr + 800ded2: ea40 0201 orr.w r2, r0, r1 + 800ded6: ec43 2b10 vmov d0, r2, r3 + 800deda: bdf8 pop {r3, r4, r5, r6, r7, pc} + 800dedc: 42b7 cmp r7, r6 + 800dede: bf3a itte cc + 800dee0: f1a5 0608 subcc.w r6, r5, #8 + 800dee4: f855 1c08 ldrcc.w r1, [r5, #-8] + 800dee8: 2100 movcs r1, #0 + 800deea: 380b subs r0, #11 + 800deec: d015 beq.n 800df1a <__b2d+0x8e> + 800deee: 4084 lsls r4, r0 + 800def0: f1c0 0520 rsb r5, r0, #32 + 800def4: f044 547f orr.w r4, r4, #1069547520 ; 0x3fc00000 + 800def8: f444 1440 orr.w r4, r4, #3145728 ; 0x300000 + 800defc: 42be cmp r6, r7 + 800defe: fa21 fc05 lsr.w ip, r1, r5 + 800df02: ea44 030c orr.w r3, r4, ip + 800df06: bf8c ite hi + 800df08: f856 4c04 ldrhi.w r4, [r6, #-4] + 800df0c: 2400 movls r4, #0 + 800df0e: fa01 f000 lsl.w r0, r1, r0 + 800df12: 40ec lsrs r4, r5 + 800df14: ea40 0204 orr.w r2, r0, r4 + 800df18: e7dd b.n 800ded6 <__b2d+0x4a> + 800df1a: ea44 030c orr.w r3, r4, ip + 800df1e: 460a mov r2, r1 + 800df20: e7d9 b.n 800ded6 <__b2d+0x4a> + 800df22: bf00 nop + 800df24: 3ff00000 .word 0x3ff00000 + +0800df28 <__d2b>: + 800df28: e92d 43f7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr} + 800df2c: 460e mov r6, r1 + 800df2e: 2101 movs r1, #1 + 800df30: ec59 8b10 vmov r8, r9, d0 + 800df34: 4615 mov r5, r2 + 800df36: f7ff fcb6 bl 800d8a6 <_Balloc> + 800df3a: f3c9 540a ubfx r4, r9, #20, #11 + 800df3e: 4607 mov r7, r0 + 800df40: f3c9 0313 ubfx r3, r9, #0, #20 + 800df44: bb34 cbnz r4, 800df94 <__d2b+0x6c> + 800df46: 9301 str r3, [sp, #4] + 800df48: f1b8 0300 subs.w r3, r8, #0 + 800df4c: d027 beq.n 800df9e <__d2b+0x76> + 800df4e: a802 add r0, sp, #8 + 800df50: f840 3d08 str.w r3, [r0, #-8]! + 800df54: f7ff fd8a bl 800da6c <__lo0bits> + 800df58: 9900 ldr r1, [sp, #0] + 800df5a: b1f0 cbz r0, 800df9a <__d2b+0x72> + 800df5c: 9a01 ldr r2, [sp, #4] + 800df5e: f1c0 0320 rsb r3, r0, #32 + 800df62: fa02 f303 lsl.w r3, r2, r3 + 800df66: 430b orrs r3, r1 + 800df68: 40c2 lsrs r2, r0 + 800df6a: 617b str r3, [r7, #20] + 800df6c: 9201 str r2, [sp, #4] + 800df6e: 9b01 ldr r3, [sp, #4] + 800df70: 61bb str r3, [r7, #24] + 800df72: 2b00 cmp r3, #0 + 800df74: bf14 ite ne + 800df76: 2102 movne r1, #2 + 800df78: 2101 moveq r1, #1 + 800df7a: 6139 str r1, [r7, #16] + 800df7c: b1c4 cbz r4, 800dfb0 <__d2b+0x88> + 800df7e: f2a4 4433 subw r4, r4, #1075 ; 0x433 + 800df82: 4404 add r4, r0 + 800df84: 6034 str r4, [r6, #0] + 800df86: f1c0 0035 rsb r0, r0, #53 ; 0x35 + 800df8a: 6028 str r0, [r5, #0] + 800df8c: 4638 mov r0, r7 + 800df8e: b003 add sp, #12 + 800df90: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} + 800df94: f443 1380 orr.w r3, r3, #1048576 ; 0x100000 + 800df98: e7d5 b.n 800df46 <__d2b+0x1e> + 800df9a: 6179 str r1, [r7, #20] + 800df9c: e7e7 b.n 800df6e <__d2b+0x46> + 800df9e: a801 add r0, sp, #4 + 800dfa0: f7ff fd64 bl 800da6c <__lo0bits> + 800dfa4: 9b01 ldr r3, [sp, #4] + 800dfa6: 617b str r3, [r7, #20] + 800dfa8: 2101 movs r1, #1 + 800dfaa: 6139 str r1, [r7, #16] + 800dfac: 3020 adds r0, #32 + 800dfae: e7e5 b.n 800df7c <__d2b+0x54> + 800dfb0: eb07 0381 add.w r3, r7, r1, lsl #2 + 800dfb4: f2a0 4032 subw r0, r0, #1074 ; 0x432 + 800dfb8: 6030 str r0, [r6, #0] + 800dfba: 6918 ldr r0, [r3, #16] + 800dfbc: f7ff fd37 bl 800da2e <__hi0bits> + 800dfc0: ebc0 1041 rsb r0, r0, r1, lsl #5 + 800dfc4: e7e1 b.n 800df8a <__d2b+0x62> + +0800dfc6 <__ratio>: + 800dfc6: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} + 800dfca: 4688 mov r8, r1 + 800dfcc: 4669 mov r1, sp + 800dfce: 4681 mov r9, r0 + 800dfd0: f7ff ff5c bl 800de8c <__b2d> + 800dfd4: a901 add r1, sp, #4 + 800dfd6: 4640 mov r0, r8 + 800dfd8: ec57 6b10 vmov r6, r7, d0 + 800dfdc: f7ff ff56 bl 800de8c <__b2d> + 800dfe0: f8d9 3010 ldr.w r3, [r9, #16] + 800dfe4: f8d8 2010 ldr.w r2, [r8, #16] + 800dfe8: eba3 0c02 sub.w ip, r3, r2 + 800dfec: e9dd 3200 ldrd r3, r2, [sp] + 800dff0: 1a9b subs r3, r3, r2 + 800dff2: eb03 134c add.w r3, r3, ip, lsl #5 + 800dff6: ec5b ab10 vmov sl, fp, d0 + 800dffa: 2b00 cmp r3, #0 + 800dffc: bfce itee gt + 800dffe: 463a movgt r2, r7 + 800e000: ebc3 3303 rsble r3, r3, r3, lsl #12 + 800e004: 465a movle r2, fp + 800e006: 4659 mov r1, fp + 800e008: 463d mov r5, r7 + 800e00a: bfd4 ite le + 800e00c: eb02 5103 addle.w r1, r2, r3, lsl #20 + 800e010: eb02 5503 addgt.w r5, r2, r3, lsl #20 + 800e014: 4630 mov r0, r6 + 800e016: ee10 2a10 vmov r2, s0 + 800e01a: 460b mov r3, r1 + 800e01c: 4629 mov r1, r5 + 800e01e: f7f2 fc1d bl 800085c <__aeabi_ddiv> + 800e022: ec41 0b10 vmov d0, r0, r1 + 800e026: b003 add sp, #12 + 800e028: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + +0800e02c <__copybits>: + 800e02c: 3901 subs r1, #1 + 800e02e: b510 push {r4, lr} + 800e030: 1149 asrs r1, r1, #5 + 800e032: 6914 ldr r4, [r2, #16] + 800e034: 3101 adds r1, #1 + 800e036: f102 0314 add.w r3, r2, #20 + 800e03a: eb00 0181 add.w r1, r0, r1, lsl #2 + 800e03e: eb03 0484 add.w r4, r3, r4, lsl #2 + 800e042: 42a3 cmp r3, r4 + 800e044: 4602 mov r2, r0 + 800e046: d303 bcc.n 800e050 <__copybits+0x24> + 800e048: 2300 movs r3, #0 + 800e04a: 428a cmp r2, r1 + 800e04c: d305 bcc.n 800e05a <__copybits+0x2e> + 800e04e: bd10 pop {r4, pc} + 800e050: f853 2b04 ldr.w r2, [r3], #4 + 800e054: f840 2b04 str.w r2, [r0], #4 + 800e058: e7f3 b.n 800e042 <__copybits+0x16> + 800e05a: f842 3b04 str.w r3, [r2], #4 + 800e05e: e7f4 b.n 800e04a <__copybits+0x1e> + +0800e060 <__any_on>: + 800e060: f100 0214 add.w r2, r0, #20 + 800e064: 6900 ldr r0, [r0, #16] + 800e066: 114b asrs r3, r1, #5 + 800e068: 4298 cmp r0, r3 + 800e06a: b510 push {r4, lr} + 800e06c: db11 blt.n 800e092 <__any_on+0x32> + 800e06e: dd0a ble.n 800e086 <__any_on+0x26> + 800e070: f011 011f ands.w r1, r1, #31 + 800e074: d007 beq.n 800e086 <__any_on+0x26> + 800e076: f852 4023 ldr.w r4, [r2, r3, lsl #2] + 800e07a: fa24 f001 lsr.w r0, r4, r1 + 800e07e: fa00 f101 lsl.w r1, r0, r1 + 800e082: 428c cmp r4, r1 + 800e084: d10b bne.n 800e09e <__any_on+0x3e> + 800e086: eb02 0383 add.w r3, r2, r3, lsl #2 + 800e08a: 4293 cmp r3, r2 + 800e08c: d803 bhi.n 800e096 <__any_on+0x36> + 800e08e: 2000 movs r0, #0 + 800e090: bd10 pop {r4, pc} + 800e092: 4603 mov r3, r0 + 800e094: e7f7 b.n 800e086 <__any_on+0x26> + 800e096: f853 1d04 ldr.w r1, [r3, #-4]! + 800e09a: 2900 cmp r1, #0 + 800e09c: d0f5 beq.n 800e08a <__any_on+0x2a> + 800e09e: 2001 movs r0, #1 + 800e0a0: e7f6 b.n 800e090 <__any_on+0x30> + +0800e0a2 <_calloc_r>: + 800e0a2: b538 push {r3, r4, r5, lr} + 800e0a4: fb02 f401 mul.w r4, r2, r1 + 800e0a8: 4621 mov r1, r4 + 800e0aa: f7fc f9c7 bl 800a43c <_malloc_r> + 800e0ae: 4605 mov r5, r0 + 800e0b0: b118 cbz r0, 800e0ba <_calloc_r+0x18> + 800e0b2: 4622 mov r2, r4 + 800e0b4: 2100 movs r1, #0 + 800e0b6: f7fc f96b bl 800a390 + 800e0ba: 4628 mov r0, r5 + 800e0bc: bd38 pop {r3, r4, r5, pc} + +0800e0be <__ssputs_r>: + 800e0be: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 800e0c2: 688e ldr r6, [r1, #8] + 800e0c4: 429e cmp r6, r3 + 800e0c6: 4682 mov sl, r0 + 800e0c8: 460c mov r4, r1 + 800e0ca: 4690 mov r8, r2 + 800e0cc: 4699 mov r9, r3 + 800e0ce: d837 bhi.n 800e140 <__ssputs_r+0x82> + 800e0d0: 898a ldrh r2, [r1, #12] + 800e0d2: f412 6f90 tst.w r2, #1152 ; 0x480 + 800e0d6: d031 beq.n 800e13c <__ssputs_r+0x7e> + 800e0d8: 6825 ldr r5, [r4, #0] + 800e0da: 6909 ldr r1, [r1, #16] + 800e0dc: 1a6f subs r7, r5, r1 + 800e0de: 6965 ldr r5, [r4, #20] + 800e0e0: 2302 movs r3, #2 + 800e0e2: eb05 0545 add.w r5, r5, r5, lsl #1 + 800e0e6: fb95 f5f3 sdiv r5, r5, r3 + 800e0ea: f109 0301 add.w r3, r9, #1 + 800e0ee: 443b add r3, r7 + 800e0f0: 429d cmp r5, r3 + 800e0f2: bf38 it cc + 800e0f4: 461d movcc r5, r3 + 800e0f6: 0553 lsls r3, r2, #21 + 800e0f8: d530 bpl.n 800e15c <__ssputs_r+0x9e> + 800e0fa: 4629 mov r1, r5 + 800e0fc: f7fc f99e bl 800a43c <_malloc_r> + 800e100: 4606 mov r6, r0 + 800e102: b950 cbnz r0, 800e11a <__ssputs_r+0x5c> + 800e104: 230c movs r3, #12 + 800e106: f8ca 3000 str.w r3, [sl] + 800e10a: 89a3 ldrh r3, [r4, #12] + 800e10c: f043 0340 orr.w r3, r3, #64 ; 0x40 + 800e110: 81a3 strh r3, [r4, #12] + 800e112: f04f 30ff mov.w r0, #4294967295 + 800e116: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 800e11a: 463a mov r2, r7 + 800e11c: 6921 ldr r1, [r4, #16] + 800e11e: f7ff fbb5 bl 800d88c + 800e122: 89a3 ldrh r3, [r4, #12] + 800e124: f423 6390 bic.w r3, r3, #1152 ; 0x480 + 800e128: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800e12c: 81a3 strh r3, [r4, #12] + 800e12e: 6126 str r6, [r4, #16] + 800e130: 6165 str r5, [r4, #20] + 800e132: 443e add r6, r7 + 800e134: 1bed subs r5, r5, r7 + 800e136: 6026 str r6, [r4, #0] + 800e138: 60a5 str r5, [r4, #8] + 800e13a: 464e mov r6, r9 + 800e13c: 454e cmp r6, r9 + 800e13e: d900 bls.n 800e142 <__ssputs_r+0x84> + 800e140: 464e mov r6, r9 + 800e142: 4632 mov r2, r6 + 800e144: 4641 mov r1, r8 + 800e146: 6820 ldr r0, [r4, #0] + 800e148: f000 fb04 bl 800e754 + 800e14c: 68a3 ldr r3, [r4, #8] + 800e14e: 1b9b subs r3, r3, r6 + 800e150: 60a3 str r3, [r4, #8] + 800e152: 6823 ldr r3, [r4, #0] + 800e154: 441e add r6, r3 + 800e156: 6026 str r6, [r4, #0] + 800e158: 2000 movs r0, #0 + 800e15a: e7dc b.n 800e116 <__ssputs_r+0x58> + 800e15c: 462a mov r2, r5 + 800e15e: f000 fb12 bl 800e786 <_realloc_r> + 800e162: 4606 mov r6, r0 + 800e164: 2800 cmp r0, #0 + 800e166: d1e2 bne.n 800e12e <__ssputs_r+0x70> + 800e168: 6921 ldr r1, [r4, #16] + 800e16a: 4650 mov r0, sl + 800e16c: f7fc f918 bl 800a3a0 <_free_r> + 800e170: e7c8 b.n 800e104 <__ssputs_r+0x46> + ... + +0800e174 <_svfiprintf_r>: + 800e174: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 800e178: 461d mov r5, r3 + 800e17a: 898b ldrh r3, [r1, #12] + 800e17c: 061f lsls r7, r3, #24 + 800e17e: b09d sub sp, #116 ; 0x74 + 800e180: 4680 mov r8, r0 + 800e182: 460c mov r4, r1 + 800e184: 4616 mov r6, r2 + 800e186: d50f bpl.n 800e1a8 <_svfiprintf_r+0x34> + 800e188: 690b ldr r3, [r1, #16] + 800e18a: b96b cbnz r3, 800e1a8 <_svfiprintf_r+0x34> + 800e18c: 2140 movs r1, #64 ; 0x40 + 800e18e: f7fc f955 bl 800a43c <_malloc_r> + 800e192: 6020 str r0, [r4, #0] + 800e194: 6120 str r0, [r4, #16] + 800e196: b928 cbnz r0, 800e1a4 <_svfiprintf_r+0x30> + 800e198: 230c movs r3, #12 + 800e19a: f8c8 3000 str.w r3, [r8] + 800e19e: f04f 30ff mov.w r0, #4294967295 + 800e1a2: e0c8 b.n 800e336 <_svfiprintf_r+0x1c2> + 800e1a4: 2340 movs r3, #64 ; 0x40 + 800e1a6: 6163 str r3, [r4, #20] + 800e1a8: 2300 movs r3, #0 + 800e1aa: 9309 str r3, [sp, #36] ; 0x24 + 800e1ac: 2320 movs r3, #32 + 800e1ae: f88d 3029 strb.w r3, [sp, #41] ; 0x29 + 800e1b2: 2330 movs r3, #48 ; 0x30 + 800e1b4: f88d 302a strb.w r3, [sp, #42] ; 0x2a + 800e1b8: 9503 str r5, [sp, #12] + 800e1ba: f04f 0b01 mov.w fp, #1 + 800e1be: 4637 mov r7, r6 + 800e1c0: 463d mov r5, r7 + 800e1c2: f815 3b01 ldrb.w r3, [r5], #1 + 800e1c6: b10b cbz r3, 800e1cc <_svfiprintf_r+0x58> + 800e1c8: 2b25 cmp r3, #37 ; 0x25 + 800e1ca: d13e bne.n 800e24a <_svfiprintf_r+0xd6> + 800e1cc: ebb7 0a06 subs.w sl, r7, r6 + 800e1d0: d00b beq.n 800e1ea <_svfiprintf_r+0x76> + 800e1d2: 4653 mov r3, sl + 800e1d4: 4632 mov r2, r6 + 800e1d6: 4621 mov r1, r4 + 800e1d8: 4640 mov r0, r8 + 800e1da: f7ff ff70 bl 800e0be <__ssputs_r> + 800e1de: 3001 adds r0, #1 + 800e1e0: f000 80a4 beq.w 800e32c <_svfiprintf_r+0x1b8> + 800e1e4: 9b09 ldr r3, [sp, #36] ; 0x24 + 800e1e6: 4453 add r3, sl + 800e1e8: 9309 str r3, [sp, #36] ; 0x24 + 800e1ea: 783b ldrb r3, [r7, #0] + 800e1ec: 2b00 cmp r3, #0 + 800e1ee: f000 809d beq.w 800e32c <_svfiprintf_r+0x1b8> + 800e1f2: 2300 movs r3, #0 + 800e1f4: f04f 32ff mov.w r2, #4294967295 + 800e1f8: e9cd 2305 strd r2, r3, [sp, #20] + 800e1fc: 9304 str r3, [sp, #16] + 800e1fe: 9307 str r3, [sp, #28] + 800e200: f88d 3053 strb.w r3, [sp, #83] ; 0x53 + 800e204: 931a str r3, [sp, #104] ; 0x68 + 800e206: 462f mov r7, r5 + 800e208: 2205 movs r2, #5 + 800e20a: f817 1b01 ldrb.w r1, [r7], #1 + 800e20e: 4850 ldr r0, [pc, #320] ; (800e350 <_svfiprintf_r+0x1dc>) + 800e210: f7f1 ffee bl 80001f0 + 800e214: 9b04 ldr r3, [sp, #16] + 800e216: b9d0 cbnz r0, 800e24e <_svfiprintf_r+0xda> + 800e218: 06d9 lsls r1, r3, #27 + 800e21a: bf44 itt mi + 800e21c: 2220 movmi r2, #32 + 800e21e: f88d 2053 strbmi.w r2, [sp, #83] ; 0x53 + 800e222: 071a lsls r2, r3, #28 + 800e224: bf44 itt mi + 800e226: 222b movmi r2, #43 ; 0x2b + 800e228: f88d 2053 strbmi.w r2, [sp, #83] ; 0x53 + 800e22c: 782a ldrb r2, [r5, #0] + 800e22e: 2a2a cmp r2, #42 ; 0x2a + 800e230: d015 beq.n 800e25e <_svfiprintf_r+0xea> + 800e232: 9a07 ldr r2, [sp, #28] + 800e234: 462f mov r7, r5 + 800e236: 2000 movs r0, #0 + 800e238: 250a movs r5, #10 + 800e23a: 4639 mov r1, r7 + 800e23c: f811 3b01 ldrb.w r3, [r1], #1 + 800e240: 3b30 subs r3, #48 ; 0x30 + 800e242: 2b09 cmp r3, #9 + 800e244: d94d bls.n 800e2e2 <_svfiprintf_r+0x16e> + 800e246: b1b8 cbz r0, 800e278 <_svfiprintf_r+0x104> + 800e248: e00f b.n 800e26a <_svfiprintf_r+0xf6> + 800e24a: 462f mov r7, r5 + 800e24c: e7b8 b.n 800e1c0 <_svfiprintf_r+0x4c> + 800e24e: 4a40 ldr r2, [pc, #256] ; (800e350 <_svfiprintf_r+0x1dc>) + 800e250: 1a80 subs r0, r0, r2 + 800e252: fa0b f000 lsl.w r0, fp, r0 + 800e256: 4318 orrs r0, r3 + 800e258: 9004 str r0, [sp, #16] + 800e25a: 463d mov r5, r7 + 800e25c: e7d3 b.n 800e206 <_svfiprintf_r+0x92> + 800e25e: 9a03 ldr r2, [sp, #12] + 800e260: 1d11 adds r1, r2, #4 + 800e262: 6812 ldr r2, [r2, #0] + 800e264: 9103 str r1, [sp, #12] + 800e266: 2a00 cmp r2, #0 + 800e268: db01 blt.n 800e26e <_svfiprintf_r+0xfa> + 800e26a: 9207 str r2, [sp, #28] + 800e26c: e004 b.n 800e278 <_svfiprintf_r+0x104> + 800e26e: 4252 negs r2, r2 + 800e270: f043 0302 orr.w r3, r3, #2 + 800e274: 9207 str r2, [sp, #28] + 800e276: 9304 str r3, [sp, #16] + 800e278: 783b ldrb r3, [r7, #0] + 800e27a: 2b2e cmp r3, #46 ; 0x2e + 800e27c: d10c bne.n 800e298 <_svfiprintf_r+0x124> + 800e27e: 787b ldrb r3, [r7, #1] + 800e280: 2b2a cmp r3, #42 ; 0x2a + 800e282: d133 bne.n 800e2ec <_svfiprintf_r+0x178> + 800e284: 9b03 ldr r3, [sp, #12] + 800e286: 1d1a adds r2, r3, #4 + 800e288: 681b ldr r3, [r3, #0] + 800e28a: 9203 str r2, [sp, #12] + 800e28c: 2b00 cmp r3, #0 + 800e28e: bfb8 it lt + 800e290: f04f 33ff movlt.w r3, #4294967295 + 800e294: 3702 adds r7, #2 + 800e296: 9305 str r3, [sp, #20] + 800e298: 4d2e ldr r5, [pc, #184] ; (800e354 <_svfiprintf_r+0x1e0>) + 800e29a: 7839 ldrb r1, [r7, #0] + 800e29c: 2203 movs r2, #3 + 800e29e: 4628 mov r0, r5 + 800e2a0: f7f1 ffa6 bl 80001f0 + 800e2a4: b138 cbz r0, 800e2b6 <_svfiprintf_r+0x142> + 800e2a6: 2340 movs r3, #64 ; 0x40 + 800e2a8: 1b40 subs r0, r0, r5 + 800e2aa: fa03 f000 lsl.w r0, r3, r0 + 800e2ae: 9b04 ldr r3, [sp, #16] + 800e2b0: 4303 orrs r3, r0 + 800e2b2: 3701 adds r7, #1 + 800e2b4: 9304 str r3, [sp, #16] + 800e2b6: 7839 ldrb r1, [r7, #0] + 800e2b8: 4827 ldr r0, [pc, #156] ; (800e358 <_svfiprintf_r+0x1e4>) + 800e2ba: f88d 1028 strb.w r1, [sp, #40] ; 0x28 + 800e2be: 2206 movs r2, #6 + 800e2c0: 1c7e adds r6, r7, #1 + 800e2c2: f7f1 ff95 bl 80001f0 + 800e2c6: 2800 cmp r0, #0 + 800e2c8: d038 beq.n 800e33c <_svfiprintf_r+0x1c8> + 800e2ca: 4b24 ldr r3, [pc, #144] ; (800e35c <_svfiprintf_r+0x1e8>) + 800e2cc: bb13 cbnz r3, 800e314 <_svfiprintf_r+0x1a0> + 800e2ce: 9b03 ldr r3, [sp, #12] + 800e2d0: 3307 adds r3, #7 + 800e2d2: f023 0307 bic.w r3, r3, #7 + 800e2d6: 3308 adds r3, #8 + 800e2d8: 9303 str r3, [sp, #12] + 800e2da: 9b09 ldr r3, [sp, #36] ; 0x24 + 800e2dc: 444b add r3, r9 + 800e2de: 9309 str r3, [sp, #36] ; 0x24 + 800e2e0: e76d b.n 800e1be <_svfiprintf_r+0x4a> + 800e2e2: fb05 3202 mla r2, r5, r2, r3 + 800e2e6: 2001 movs r0, #1 + 800e2e8: 460f mov r7, r1 + 800e2ea: e7a6 b.n 800e23a <_svfiprintf_r+0xc6> + 800e2ec: 2300 movs r3, #0 + 800e2ee: 3701 adds r7, #1 + 800e2f0: 9305 str r3, [sp, #20] + 800e2f2: 4619 mov r1, r3 + 800e2f4: 250a movs r5, #10 + 800e2f6: 4638 mov r0, r7 + 800e2f8: f810 2b01 ldrb.w r2, [r0], #1 + 800e2fc: 3a30 subs r2, #48 ; 0x30 + 800e2fe: 2a09 cmp r2, #9 + 800e300: d903 bls.n 800e30a <_svfiprintf_r+0x196> + 800e302: 2b00 cmp r3, #0 + 800e304: d0c8 beq.n 800e298 <_svfiprintf_r+0x124> + 800e306: 9105 str r1, [sp, #20] + 800e308: e7c6 b.n 800e298 <_svfiprintf_r+0x124> + 800e30a: fb05 2101 mla r1, r5, r1, r2 + 800e30e: 2301 movs r3, #1 + 800e310: 4607 mov r7, r0 + 800e312: e7f0 b.n 800e2f6 <_svfiprintf_r+0x182> + 800e314: ab03 add r3, sp, #12 + 800e316: 9300 str r3, [sp, #0] + 800e318: 4622 mov r2, r4 + 800e31a: 4b11 ldr r3, [pc, #68] ; (800e360 <_svfiprintf_r+0x1ec>) + 800e31c: a904 add r1, sp, #16 + 800e31e: 4640 mov r0, r8 + 800e320: f7fc f97a bl 800a618 <_printf_float> + 800e324: f1b0 3fff cmp.w r0, #4294967295 + 800e328: 4681 mov r9, r0 + 800e32a: d1d6 bne.n 800e2da <_svfiprintf_r+0x166> + 800e32c: 89a3 ldrh r3, [r4, #12] + 800e32e: 065b lsls r3, r3, #25 + 800e330: f53f af35 bmi.w 800e19e <_svfiprintf_r+0x2a> + 800e334: 9809 ldr r0, [sp, #36] ; 0x24 + 800e336: b01d add sp, #116 ; 0x74 + 800e338: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 800e33c: ab03 add r3, sp, #12 + 800e33e: 9300 str r3, [sp, #0] + 800e340: 4622 mov r2, r4 + 800e342: 4b07 ldr r3, [pc, #28] ; (800e360 <_svfiprintf_r+0x1ec>) + 800e344: a904 add r1, sp, #16 + 800e346: 4640 mov r0, r8 + 800e348: f7fc fc1c bl 800ab84 <_printf_i> + 800e34c: e7ea b.n 800e324 <_svfiprintf_r+0x1b0> + 800e34e: bf00 nop + 800e350: 0800eb44 .word 0x0800eb44 + 800e354: 0800eb4a .word 0x0800eb4a + 800e358: 0800eb4e .word 0x0800eb4e + 800e35c: 0800a619 .word 0x0800a619 + 800e360: 0800e0bf .word 0x0800e0bf + +0800e364 <__sfputc_r>: + 800e364: 6893 ldr r3, [r2, #8] + 800e366: 3b01 subs r3, #1 + 800e368: 2b00 cmp r3, #0 + 800e36a: b410 push {r4} + 800e36c: 6093 str r3, [r2, #8] + 800e36e: da08 bge.n 800e382 <__sfputc_r+0x1e> + 800e370: 6994 ldr r4, [r2, #24] + 800e372: 42a3 cmp r3, r4 + 800e374: db01 blt.n 800e37a <__sfputc_r+0x16> + 800e376: 290a cmp r1, #10 + 800e378: d103 bne.n 800e382 <__sfputc_r+0x1e> + 800e37a: f85d 4b04 ldr.w r4, [sp], #4 + 800e37e: f7fd be55 b.w 800c02c <__swbuf_r> + 800e382: 6813 ldr r3, [r2, #0] + 800e384: 1c58 adds r0, r3, #1 + 800e386: 6010 str r0, [r2, #0] + 800e388: 7019 strb r1, [r3, #0] + 800e38a: 4608 mov r0, r1 + 800e38c: f85d 4b04 ldr.w r4, [sp], #4 + 800e390: 4770 bx lr + +0800e392 <__sfputs_r>: + 800e392: b5f8 push {r3, r4, r5, r6, r7, lr} + 800e394: 4606 mov r6, r0 + 800e396: 460f mov r7, r1 + 800e398: 4614 mov r4, r2 + 800e39a: 18d5 adds r5, r2, r3 + 800e39c: 42ac cmp r4, r5 + 800e39e: d101 bne.n 800e3a4 <__sfputs_r+0x12> + 800e3a0: 2000 movs r0, #0 + 800e3a2: e007 b.n 800e3b4 <__sfputs_r+0x22> + 800e3a4: 463a mov r2, r7 + 800e3a6: f814 1b01 ldrb.w r1, [r4], #1 + 800e3aa: 4630 mov r0, r6 + 800e3ac: f7ff ffda bl 800e364 <__sfputc_r> + 800e3b0: 1c43 adds r3, r0, #1 + 800e3b2: d1f3 bne.n 800e39c <__sfputs_r+0xa> + 800e3b4: bdf8 pop {r3, r4, r5, r6, r7, pc} + ... + +0800e3b8 <_vfiprintf_r>: + 800e3b8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 800e3bc: 460c mov r4, r1 + 800e3be: b09d sub sp, #116 ; 0x74 + 800e3c0: 4617 mov r7, r2 + 800e3c2: 461d mov r5, r3 + 800e3c4: 4606 mov r6, r0 + 800e3c6: b118 cbz r0, 800e3d0 <_vfiprintf_r+0x18> + 800e3c8: 6983 ldr r3, [r0, #24] + 800e3ca: b90b cbnz r3, 800e3d0 <_vfiprintf_r+0x18> + 800e3cc: f7fe fe24 bl 800d018 <__sinit> + 800e3d0: 4b7c ldr r3, [pc, #496] ; (800e5c4 <_vfiprintf_r+0x20c>) + 800e3d2: 429c cmp r4, r3 + 800e3d4: d158 bne.n 800e488 <_vfiprintf_r+0xd0> + 800e3d6: 6874 ldr r4, [r6, #4] + 800e3d8: 89a3 ldrh r3, [r4, #12] + 800e3da: 0718 lsls r0, r3, #28 + 800e3dc: d55e bpl.n 800e49c <_vfiprintf_r+0xe4> + 800e3de: 6923 ldr r3, [r4, #16] + 800e3e0: 2b00 cmp r3, #0 + 800e3e2: d05b beq.n 800e49c <_vfiprintf_r+0xe4> + 800e3e4: 2300 movs r3, #0 + 800e3e6: 9309 str r3, [sp, #36] ; 0x24 + 800e3e8: 2320 movs r3, #32 + 800e3ea: f88d 3029 strb.w r3, [sp, #41] ; 0x29 + 800e3ee: 2330 movs r3, #48 ; 0x30 + 800e3f0: f88d 302a strb.w r3, [sp, #42] ; 0x2a + 800e3f4: 9503 str r5, [sp, #12] + 800e3f6: f04f 0b01 mov.w fp, #1 + 800e3fa: 46b8 mov r8, r7 + 800e3fc: 4645 mov r5, r8 + 800e3fe: f815 3b01 ldrb.w r3, [r5], #1 + 800e402: b10b cbz r3, 800e408 <_vfiprintf_r+0x50> + 800e404: 2b25 cmp r3, #37 ; 0x25 + 800e406: d154 bne.n 800e4b2 <_vfiprintf_r+0xfa> + 800e408: ebb8 0a07 subs.w sl, r8, r7 + 800e40c: d00b beq.n 800e426 <_vfiprintf_r+0x6e> + 800e40e: 4653 mov r3, sl + 800e410: 463a mov r2, r7 + 800e412: 4621 mov r1, r4 + 800e414: 4630 mov r0, r6 + 800e416: f7ff ffbc bl 800e392 <__sfputs_r> + 800e41a: 3001 adds r0, #1 + 800e41c: f000 80c2 beq.w 800e5a4 <_vfiprintf_r+0x1ec> + 800e420: 9b09 ldr r3, [sp, #36] ; 0x24 + 800e422: 4453 add r3, sl + 800e424: 9309 str r3, [sp, #36] ; 0x24 + 800e426: f898 3000 ldrb.w r3, [r8] + 800e42a: 2b00 cmp r3, #0 + 800e42c: f000 80ba beq.w 800e5a4 <_vfiprintf_r+0x1ec> + 800e430: 2300 movs r3, #0 + 800e432: f04f 32ff mov.w r2, #4294967295 + 800e436: e9cd 2305 strd r2, r3, [sp, #20] + 800e43a: 9304 str r3, [sp, #16] + 800e43c: 9307 str r3, [sp, #28] + 800e43e: f88d 3053 strb.w r3, [sp, #83] ; 0x53 + 800e442: 931a str r3, [sp, #104] ; 0x68 + 800e444: 46a8 mov r8, r5 + 800e446: 2205 movs r2, #5 + 800e448: f818 1b01 ldrb.w r1, [r8], #1 + 800e44c: 485e ldr r0, [pc, #376] ; (800e5c8 <_vfiprintf_r+0x210>) + 800e44e: f7f1 fecf bl 80001f0 + 800e452: 9b04 ldr r3, [sp, #16] + 800e454: bb78 cbnz r0, 800e4b6 <_vfiprintf_r+0xfe> + 800e456: 06d9 lsls r1, r3, #27 + 800e458: bf44 itt mi + 800e45a: 2220 movmi r2, #32 + 800e45c: f88d 2053 strbmi.w r2, [sp, #83] ; 0x53 + 800e460: 071a lsls r2, r3, #28 + 800e462: bf44 itt mi + 800e464: 222b movmi r2, #43 ; 0x2b + 800e466: f88d 2053 strbmi.w r2, [sp, #83] ; 0x53 + 800e46a: 782a ldrb r2, [r5, #0] + 800e46c: 2a2a cmp r2, #42 ; 0x2a + 800e46e: d02a beq.n 800e4c6 <_vfiprintf_r+0x10e> + 800e470: 9a07 ldr r2, [sp, #28] + 800e472: 46a8 mov r8, r5 + 800e474: 2000 movs r0, #0 + 800e476: 250a movs r5, #10 + 800e478: 4641 mov r1, r8 + 800e47a: f811 3b01 ldrb.w r3, [r1], #1 + 800e47e: 3b30 subs r3, #48 ; 0x30 + 800e480: 2b09 cmp r3, #9 + 800e482: d969 bls.n 800e558 <_vfiprintf_r+0x1a0> + 800e484: b360 cbz r0, 800e4e0 <_vfiprintf_r+0x128> + 800e486: e024 b.n 800e4d2 <_vfiprintf_r+0x11a> + 800e488: 4b50 ldr r3, [pc, #320] ; (800e5cc <_vfiprintf_r+0x214>) + 800e48a: 429c cmp r4, r3 + 800e48c: d101 bne.n 800e492 <_vfiprintf_r+0xda> + 800e48e: 68b4 ldr r4, [r6, #8] + 800e490: e7a2 b.n 800e3d8 <_vfiprintf_r+0x20> + 800e492: 4b4f ldr r3, [pc, #316] ; (800e5d0 <_vfiprintf_r+0x218>) + 800e494: 429c cmp r4, r3 + 800e496: bf08 it eq + 800e498: 68f4 ldreq r4, [r6, #12] + 800e49a: e79d b.n 800e3d8 <_vfiprintf_r+0x20> + 800e49c: 4621 mov r1, r4 + 800e49e: 4630 mov r0, r6 + 800e4a0: f7fd fe16 bl 800c0d0 <__swsetup_r> + 800e4a4: 2800 cmp r0, #0 + 800e4a6: d09d beq.n 800e3e4 <_vfiprintf_r+0x2c> + 800e4a8: f04f 30ff mov.w r0, #4294967295 + 800e4ac: b01d add sp, #116 ; 0x74 + 800e4ae: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 800e4b2: 46a8 mov r8, r5 + 800e4b4: e7a2 b.n 800e3fc <_vfiprintf_r+0x44> + 800e4b6: 4a44 ldr r2, [pc, #272] ; (800e5c8 <_vfiprintf_r+0x210>) + 800e4b8: 1a80 subs r0, r0, r2 + 800e4ba: fa0b f000 lsl.w r0, fp, r0 + 800e4be: 4318 orrs r0, r3 + 800e4c0: 9004 str r0, [sp, #16] + 800e4c2: 4645 mov r5, r8 + 800e4c4: e7be b.n 800e444 <_vfiprintf_r+0x8c> + 800e4c6: 9a03 ldr r2, [sp, #12] + 800e4c8: 1d11 adds r1, r2, #4 + 800e4ca: 6812 ldr r2, [r2, #0] + 800e4cc: 9103 str r1, [sp, #12] + 800e4ce: 2a00 cmp r2, #0 + 800e4d0: db01 blt.n 800e4d6 <_vfiprintf_r+0x11e> + 800e4d2: 9207 str r2, [sp, #28] + 800e4d4: e004 b.n 800e4e0 <_vfiprintf_r+0x128> + 800e4d6: 4252 negs r2, r2 + 800e4d8: f043 0302 orr.w r3, r3, #2 + 800e4dc: 9207 str r2, [sp, #28] + 800e4de: 9304 str r3, [sp, #16] + 800e4e0: f898 3000 ldrb.w r3, [r8] + 800e4e4: 2b2e cmp r3, #46 ; 0x2e + 800e4e6: d10e bne.n 800e506 <_vfiprintf_r+0x14e> + 800e4e8: f898 3001 ldrb.w r3, [r8, #1] + 800e4ec: 2b2a cmp r3, #42 ; 0x2a + 800e4ee: d138 bne.n 800e562 <_vfiprintf_r+0x1aa> + 800e4f0: 9b03 ldr r3, [sp, #12] + 800e4f2: 1d1a adds r2, r3, #4 + 800e4f4: 681b ldr r3, [r3, #0] + 800e4f6: 9203 str r2, [sp, #12] + 800e4f8: 2b00 cmp r3, #0 + 800e4fa: bfb8 it lt + 800e4fc: f04f 33ff movlt.w r3, #4294967295 + 800e500: f108 0802 add.w r8, r8, #2 + 800e504: 9305 str r3, [sp, #20] + 800e506: 4d33 ldr r5, [pc, #204] ; (800e5d4 <_vfiprintf_r+0x21c>) + 800e508: f898 1000 ldrb.w r1, [r8] + 800e50c: 2203 movs r2, #3 + 800e50e: 4628 mov r0, r5 + 800e510: f7f1 fe6e bl 80001f0 + 800e514: b140 cbz r0, 800e528 <_vfiprintf_r+0x170> + 800e516: 2340 movs r3, #64 ; 0x40 + 800e518: 1b40 subs r0, r0, r5 + 800e51a: fa03 f000 lsl.w r0, r3, r0 + 800e51e: 9b04 ldr r3, [sp, #16] + 800e520: 4303 orrs r3, r0 + 800e522: f108 0801 add.w r8, r8, #1 + 800e526: 9304 str r3, [sp, #16] + 800e528: f898 1000 ldrb.w r1, [r8] + 800e52c: 482a ldr r0, [pc, #168] ; (800e5d8 <_vfiprintf_r+0x220>) + 800e52e: f88d 1028 strb.w r1, [sp, #40] ; 0x28 + 800e532: 2206 movs r2, #6 + 800e534: f108 0701 add.w r7, r8, #1 + 800e538: f7f1 fe5a bl 80001f0 + 800e53c: 2800 cmp r0, #0 + 800e53e: d037 beq.n 800e5b0 <_vfiprintf_r+0x1f8> + 800e540: 4b26 ldr r3, [pc, #152] ; (800e5dc <_vfiprintf_r+0x224>) + 800e542: bb1b cbnz r3, 800e58c <_vfiprintf_r+0x1d4> + 800e544: 9b03 ldr r3, [sp, #12] + 800e546: 3307 adds r3, #7 + 800e548: f023 0307 bic.w r3, r3, #7 + 800e54c: 3308 adds r3, #8 + 800e54e: 9303 str r3, [sp, #12] + 800e550: 9b09 ldr r3, [sp, #36] ; 0x24 + 800e552: 444b add r3, r9 + 800e554: 9309 str r3, [sp, #36] ; 0x24 + 800e556: e750 b.n 800e3fa <_vfiprintf_r+0x42> + 800e558: fb05 3202 mla r2, r5, r2, r3 + 800e55c: 2001 movs r0, #1 + 800e55e: 4688 mov r8, r1 + 800e560: e78a b.n 800e478 <_vfiprintf_r+0xc0> + 800e562: 2300 movs r3, #0 + 800e564: f108 0801 add.w r8, r8, #1 + 800e568: 9305 str r3, [sp, #20] + 800e56a: 4619 mov r1, r3 + 800e56c: 250a movs r5, #10 + 800e56e: 4640 mov r0, r8 + 800e570: f810 2b01 ldrb.w r2, [r0], #1 + 800e574: 3a30 subs r2, #48 ; 0x30 + 800e576: 2a09 cmp r2, #9 + 800e578: d903 bls.n 800e582 <_vfiprintf_r+0x1ca> + 800e57a: 2b00 cmp r3, #0 + 800e57c: d0c3 beq.n 800e506 <_vfiprintf_r+0x14e> + 800e57e: 9105 str r1, [sp, #20] + 800e580: e7c1 b.n 800e506 <_vfiprintf_r+0x14e> + 800e582: fb05 2101 mla r1, r5, r1, r2 + 800e586: 2301 movs r3, #1 + 800e588: 4680 mov r8, r0 + 800e58a: e7f0 b.n 800e56e <_vfiprintf_r+0x1b6> + 800e58c: ab03 add r3, sp, #12 + 800e58e: 9300 str r3, [sp, #0] + 800e590: 4622 mov r2, r4 + 800e592: 4b13 ldr r3, [pc, #76] ; (800e5e0 <_vfiprintf_r+0x228>) + 800e594: a904 add r1, sp, #16 + 800e596: 4630 mov r0, r6 + 800e598: f7fc f83e bl 800a618 <_printf_float> + 800e59c: f1b0 3fff cmp.w r0, #4294967295 + 800e5a0: 4681 mov r9, r0 + 800e5a2: d1d5 bne.n 800e550 <_vfiprintf_r+0x198> + 800e5a4: 89a3 ldrh r3, [r4, #12] + 800e5a6: 065b lsls r3, r3, #25 + 800e5a8: f53f af7e bmi.w 800e4a8 <_vfiprintf_r+0xf0> + 800e5ac: 9809 ldr r0, [sp, #36] ; 0x24 + 800e5ae: e77d b.n 800e4ac <_vfiprintf_r+0xf4> + 800e5b0: ab03 add r3, sp, #12 + 800e5b2: 9300 str r3, [sp, #0] + 800e5b4: 4622 mov r2, r4 + 800e5b6: 4b0a ldr r3, [pc, #40] ; (800e5e0 <_vfiprintf_r+0x228>) + 800e5b8: a904 add r1, sp, #16 + 800e5ba: 4630 mov r0, r6 + 800e5bc: f7fc fae2 bl 800ab84 <_printf_i> + 800e5c0: e7ec b.n 800e59c <_vfiprintf_r+0x1e4> + 800e5c2: bf00 nop + 800e5c4: 0800e9f8 .word 0x0800e9f8 + 800e5c8: 0800eb44 .word 0x0800eb44 + 800e5cc: 0800ea18 .word 0x0800ea18 + 800e5d0: 0800e9d8 .word 0x0800e9d8 + 800e5d4: 0800eb4a .word 0x0800eb4a + 800e5d8: 0800eb4e .word 0x0800eb4e + 800e5dc: 0800a619 .word 0x0800a619 + 800e5e0: 0800e393 .word 0x0800e393 + +0800e5e4 <__sread>: + 800e5e4: b510 push {r4, lr} + 800e5e6: 460c mov r4, r1 + 800e5e8: f9b1 100e ldrsh.w r1, [r1, #14] + 800e5ec: f000 f8f2 bl 800e7d4 <_read_r> + 800e5f0: 2800 cmp r0, #0 + 800e5f2: bfab itete ge + 800e5f4: 6d63 ldrge r3, [r4, #84] ; 0x54 + 800e5f6: 89a3 ldrhlt r3, [r4, #12] + 800e5f8: 181b addge r3, r3, r0 + 800e5fa: f423 5380 biclt.w r3, r3, #4096 ; 0x1000 + 800e5fe: bfac ite ge + 800e600: 6563 strge r3, [r4, #84] ; 0x54 + 800e602: 81a3 strhlt r3, [r4, #12] + 800e604: bd10 pop {r4, pc} + +0800e606 <__swrite>: + 800e606: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 800e60a: 461f mov r7, r3 + 800e60c: 898b ldrh r3, [r1, #12] + 800e60e: 05db lsls r3, r3, #23 + 800e610: 4605 mov r5, r0 + 800e612: 460c mov r4, r1 + 800e614: 4616 mov r6, r2 + 800e616: d505 bpl.n 800e624 <__swrite+0x1e> + 800e618: 2302 movs r3, #2 + 800e61a: 2200 movs r2, #0 + 800e61c: f9b1 100e ldrsh.w r1, [r1, #14] + 800e620: f000 f886 bl 800e730 <_lseek_r> + 800e624: 89a3 ldrh r3, [r4, #12] + 800e626: f9b4 100e ldrsh.w r1, [r4, #14] + 800e62a: f423 5380 bic.w r3, r3, #4096 ; 0x1000 + 800e62e: 81a3 strh r3, [r4, #12] + 800e630: 4632 mov r2, r6 + 800e632: 463b mov r3, r7 + 800e634: 4628 mov r0, r5 + 800e636: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} + 800e63a: f000 b835 b.w 800e6a8 <_write_r> + +0800e63e <__sseek>: + 800e63e: b510 push {r4, lr} + 800e640: 460c mov r4, r1 + 800e642: f9b1 100e ldrsh.w r1, [r1, #14] + 800e646: f000 f873 bl 800e730 <_lseek_r> + 800e64a: 1c43 adds r3, r0, #1 + 800e64c: 89a3 ldrh r3, [r4, #12] + 800e64e: bf15 itete ne + 800e650: 6560 strne r0, [r4, #84] ; 0x54 + 800e652: f423 5380 biceq.w r3, r3, #4096 ; 0x1000 + 800e656: f443 5380 orrne.w r3, r3, #4096 ; 0x1000 + 800e65a: 81a3 strheq r3, [r4, #12] + 800e65c: bf18 it ne + 800e65e: 81a3 strhne r3, [r4, #12] + 800e660: bd10 pop {r4, pc} + +0800e662 <__sclose>: + 800e662: f9b1 100e ldrsh.w r1, [r1, #14] + 800e666: f000 b831 b.w 800e6cc <_close_r> + +0800e66a : + 800e66a: b510 push {r4, lr} + 800e66c: b16a cbz r2, 800e68a + 800e66e: 3901 subs r1, #1 + 800e670: 1884 adds r4, r0, r2 + 800e672: f810 3b01 ldrb.w r3, [r0], #1 + 800e676: f811 2f01 ldrb.w r2, [r1, #1]! + 800e67a: 4293 cmp r3, r2 + 800e67c: d103 bne.n 800e686 + 800e67e: 42a0 cmp r0, r4 + 800e680: d001 beq.n 800e686 + 800e682: 2b00 cmp r3, #0 + 800e684: d1f5 bne.n 800e672 + 800e686: 1a98 subs r0, r3, r2 + 800e688: bd10 pop {r4, pc} + 800e68a: 4610 mov r0, r2 + 800e68c: e7fc b.n 800e688 + +0800e68e <__ascii_wctomb>: + 800e68e: b149 cbz r1, 800e6a4 <__ascii_wctomb+0x16> + 800e690: 2aff cmp r2, #255 ; 0xff + 800e692: bf85 ittet hi + 800e694: 238a movhi r3, #138 ; 0x8a + 800e696: 6003 strhi r3, [r0, #0] + 800e698: 700a strbls r2, [r1, #0] + 800e69a: f04f 30ff movhi.w r0, #4294967295 + 800e69e: bf98 it ls + 800e6a0: 2001 movls r0, #1 + 800e6a2: 4770 bx lr + 800e6a4: 4608 mov r0, r1 + 800e6a6: 4770 bx lr + +0800e6a8 <_write_r>: + 800e6a8: b538 push {r3, r4, r5, lr} + 800e6aa: 4c07 ldr r4, [pc, #28] ; (800e6c8 <_write_r+0x20>) + 800e6ac: 4605 mov r5, r0 + 800e6ae: 4608 mov r0, r1 + 800e6b0: 4611 mov r1, r2 + 800e6b2: 2200 movs r2, #0 + 800e6b4: 6022 str r2, [r4, #0] + 800e6b6: 461a mov r2, r3 + 800e6b8: f7f3 fa01 bl 8001abe <_write> + 800e6bc: 1c43 adds r3, r0, #1 + 800e6be: d102 bne.n 800e6c6 <_write_r+0x1e> + 800e6c0: 6823 ldr r3, [r4, #0] + 800e6c2: b103 cbz r3, 800e6c6 <_write_r+0x1e> + 800e6c4: 602b str r3, [r5, #0] + 800e6c6: bd38 pop {r3, r4, r5, pc} + 800e6c8: 20000ab0 .word 0x20000ab0 + +0800e6cc <_close_r>: + 800e6cc: b538 push {r3, r4, r5, lr} + 800e6ce: 4c06 ldr r4, [pc, #24] ; (800e6e8 <_close_r+0x1c>) + 800e6d0: 2300 movs r3, #0 + 800e6d2: 4605 mov r5, r0 + 800e6d4: 4608 mov r0, r1 + 800e6d6: 6023 str r3, [r4, #0] + 800e6d8: f7f3 fa0d bl 8001af6 <_close> + 800e6dc: 1c43 adds r3, r0, #1 + 800e6de: d102 bne.n 800e6e6 <_close_r+0x1a> + 800e6e0: 6823 ldr r3, [r4, #0] + 800e6e2: b103 cbz r3, 800e6e6 <_close_r+0x1a> + 800e6e4: 602b str r3, [r5, #0] + 800e6e6: bd38 pop {r3, r4, r5, pc} + 800e6e8: 20000ab0 .word 0x20000ab0 + +0800e6ec <_fstat_r>: + 800e6ec: b538 push {r3, r4, r5, lr} + 800e6ee: 4c07 ldr r4, [pc, #28] ; (800e70c <_fstat_r+0x20>) + 800e6f0: 2300 movs r3, #0 + 800e6f2: 4605 mov r5, r0 + 800e6f4: 4608 mov r0, r1 + 800e6f6: 4611 mov r1, r2 + 800e6f8: 6023 str r3, [r4, #0] + 800e6fa: f7f3 fa08 bl 8001b0e <_fstat> + 800e6fe: 1c43 adds r3, r0, #1 + 800e700: d102 bne.n 800e708 <_fstat_r+0x1c> + 800e702: 6823 ldr r3, [r4, #0] + 800e704: b103 cbz r3, 800e708 <_fstat_r+0x1c> + 800e706: 602b str r3, [r5, #0] + 800e708: bd38 pop {r3, r4, r5, pc} + 800e70a: bf00 nop + 800e70c: 20000ab0 .word 0x20000ab0 + +0800e710 <_isatty_r>: + 800e710: b538 push {r3, r4, r5, lr} + 800e712: 4c06 ldr r4, [pc, #24] ; (800e72c <_isatty_r+0x1c>) + 800e714: 2300 movs r3, #0 + 800e716: 4605 mov r5, r0 + 800e718: 4608 mov r0, r1 + 800e71a: 6023 str r3, [r4, #0] + 800e71c: f7f3 fa07 bl 8001b2e <_isatty> + 800e720: 1c43 adds r3, r0, #1 + 800e722: d102 bne.n 800e72a <_isatty_r+0x1a> + 800e724: 6823 ldr r3, [r4, #0] + 800e726: b103 cbz r3, 800e72a <_isatty_r+0x1a> + 800e728: 602b str r3, [r5, #0] + 800e72a: bd38 pop {r3, r4, r5, pc} + 800e72c: 20000ab0 .word 0x20000ab0 + +0800e730 <_lseek_r>: + 800e730: b538 push {r3, r4, r5, lr} + 800e732: 4c07 ldr r4, [pc, #28] ; (800e750 <_lseek_r+0x20>) + 800e734: 4605 mov r5, r0 + 800e736: 4608 mov r0, r1 + 800e738: 4611 mov r1, r2 + 800e73a: 2200 movs r2, #0 + 800e73c: 6022 str r2, [r4, #0] + 800e73e: 461a mov r2, r3 + 800e740: f7f3 fa00 bl 8001b44 <_lseek> + 800e744: 1c43 adds r3, r0, #1 + 800e746: d102 bne.n 800e74e <_lseek_r+0x1e> + 800e748: 6823 ldr r3, [r4, #0] + 800e74a: b103 cbz r3, 800e74e <_lseek_r+0x1e> + 800e74c: 602b str r3, [r5, #0] + 800e74e: bd38 pop {r3, r4, r5, pc} + 800e750: 20000ab0 .word 0x20000ab0 + +0800e754 : + 800e754: 4288 cmp r0, r1 + 800e756: b510 push {r4, lr} + 800e758: eb01 0302 add.w r3, r1, r2 + 800e75c: d807 bhi.n 800e76e + 800e75e: 1e42 subs r2, r0, #1 + 800e760: 4299 cmp r1, r3 + 800e762: d00a beq.n 800e77a + 800e764: f811 4b01 ldrb.w r4, [r1], #1 + 800e768: f802 4f01 strb.w r4, [r2, #1]! + 800e76c: e7f8 b.n 800e760 + 800e76e: 4283 cmp r3, r0 + 800e770: d9f5 bls.n 800e75e + 800e772: 1881 adds r1, r0, r2 + 800e774: 1ad2 subs r2, r2, r3 + 800e776: 42d3 cmn r3, r2 + 800e778: d100 bne.n 800e77c + 800e77a: bd10 pop {r4, pc} + 800e77c: f813 4d01 ldrb.w r4, [r3, #-1]! + 800e780: f801 4d01 strb.w r4, [r1, #-1]! + 800e784: e7f7 b.n 800e776 + +0800e786 <_realloc_r>: + 800e786: b5f8 push {r3, r4, r5, r6, r7, lr} + 800e788: 4607 mov r7, r0 + 800e78a: 4614 mov r4, r2 + 800e78c: 460e mov r6, r1 + 800e78e: b921 cbnz r1, 800e79a <_realloc_r+0x14> + 800e790: 4611 mov r1, r2 + 800e792: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr} + 800e796: f7fb be51 b.w 800a43c <_malloc_r> + 800e79a: b922 cbnz r2, 800e7a6 <_realloc_r+0x20> + 800e79c: f7fb fe00 bl 800a3a0 <_free_r> + 800e7a0: 4625 mov r5, r4 + 800e7a2: 4628 mov r0, r5 + 800e7a4: bdf8 pop {r3, r4, r5, r6, r7, pc} + 800e7a6: f000 f827 bl 800e7f8 <_malloc_usable_size_r> + 800e7aa: 42a0 cmp r0, r4 + 800e7ac: d20f bcs.n 800e7ce <_realloc_r+0x48> + 800e7ae: 4621 mov r1, r4 + 800e7b0: 4638 mov r0, r7 + 800e7b2: f7fb fe43 bl 800a43c <_malloc_r> + 800e7b6: 4605 mov r5, r0 + 800e7b8: 2800 cmp r0, #0 + 800e7ba: d0f2 beq.n 800e7a2 <_realloc_r+0x1c> + 800e7bc: 4631 mov r1, r6 + 800e7be: 4622 mov r2, r4 + 800e7c0: f7ff f864 bl 800d88c + 800e7c4: 4631 mov r1, r6 + 800e7c6: 4638 mov r0, r7 + 800e7c8: f7fb fdea bl 800a3a0 <_free_r> + 800e7cc: e7e9 b.n 800e7a2 <_realloc_r+0x1c> + 800e7ce: 4635 mov r5, r6 + 800e7d0: e7e7 b.n 800e7a2 <_realloc_r+0x1c> + ... + +0800e7d4 <_read_r>: + 800e7d4: b538 push {r3, r4, r5, lr} + 800e7d6: 4c07 ldr r4, [pc, #28] ; (800e7f4 <_read_r+0x20>) + 800e7d8: 4605 mov r5, r0 + 800e7da: 4608 mov r0, r1 + 800e7dc: 4611 mov r1, r2 + 800e7de: 2200 movs r2, #0 + 800e7e0: 6022 str r2, [r4, #0] + 800e7e2: 461a mov r2, r3 + 800e7e4: f7f3 f94e bl 8001a84 <_read> + 800e7e8: 1c43 adds r3, r0, #1 + 800e7ea: d102 bne.n 800e7f2 <_read_r+0x1e> + 800e7ec: 6823 ldr r3, [r4, #0] + 800e7ee: b103 cbz r3, 800e7f2 <_read_r+0x1e> + 800e7f0: 602b str r3, [r5, #0] + 800e7f2: bd38 pop {r3, r4, r5, pc} + 800e7f4: 20000ab0 .word 0x20000ab0 + +0800e7f8 <_malloc_usable_size_r>: + 800e7f8: f851 3c04 ldr.w r3, [r1, #-4] + 800e7fc: 1f18 subs r0, r3, #4 + 800e7fe: 2b00 cmp r3, #0 + 800e800: bfbc itt lt + 800e802: 580b ldrlt r3, [r1, r0] + 800e804: 18c0 addlt r0, r0, r3 + 800e806: 4770 bx lr + +0800e808 <_init>: + 800e808: b5f8 push {r3, r4, r5, r6, r7, lr} + 800e80a: bf00 nop + 800e80c: bcf8 pop {r3, r4, r5, r6, r7} + 800e80e: bc08 pop {r3} + 800e810: 469e mov lr, r3 + 800e812: 4770 bx lr + +0800e814 <_fini>: + 800e814: b5f8 push {r3, r4, r5, r6, r7, lr} + 800e816: bf00 nop + 800e818: bcf8 pop {r3, r4, r5, r6, r7} + 800e81a: bc08 pop {r3} + 800e81c: 469e mov lr, r3 + 800e81e: 4770 bx lr diff --git a/Debug/makefile b/Debug/makefile new file mode 100644 index 0000000..4c2252b --- /dev/null +++ b/Debug/makefile @@ -0,0 +1,115 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +-include ../makefile.init + +RM := rm -rf + +# All of the sources participating in the build are defined here +-include sources.mk +-include USB_HOST/Target/subdir.mk +-include USB_HOST/App/subdir.mk +-include Middlewares/ST/STM32_USB_Host_Library/Core/Src/subdir.mk +-include Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Src/subdir.mk +-include Drivers/STM32F4xx_HAL_Driver/Src/subdir.mk +-include Drivers/LSM303DLHC/subdir.mk +-include Drivers/COMPASS_LEDS/subdir.mk +-include Core/Startup/subdir.mk +-include Core/Src/subdir.mk +-include subdir.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(CC_DEPS)),) +-include $(CC_DEPS) +endif +ifneq ($(strip $(C++_DEPS)),) +-include $(C++_DEPS) +endif +ifneq ($(strip $(C_UPPER_DEPS)),) +-include $(C_UPPER_DEPS) +endif +ifneq ($(strip $(CXX_DEPS)),) +-include $(CXX_DEPS) +endif +ifneq ($(strip $(S_DEPS)),) +-include $(S_DEPS) +endif +ifneq ($(strip $(S_UPPER_DEPS)),) +-include $(S_UPPER_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +ifneq ($(strip $(CPP_DEPS)),) +-include $(CPP_DEPS) +endif +endif + +-include ../makefile.defs + +BUILD_ARTIFACT_NAME := eCompass +BUILD_ARTIFACT_EXTENSION := elf +BUILD_ARTIFACT_PREFIX := +BUILD_ARTIFACT := $(BUILD_ARTIFACT_PREFIX)$(BUILD_ARTIFACT_NAME).$(BUILD_ARTIFACT_EXTENSION) + +# Add inputs and outputs from these tool invocations to the build variables +EXECUTABLES += \ +eCompass.elf \ + +SIZE_OUTPUT += \ +default.size.stdout \ + +OBJDUMP_LIST += \ +eCompass.list \ + +OBJCOPY_BIN += \ +eCompass.bin \ + + +# All Target +all: main-build + +# Main-build Target +main-build: eCompass.elf secondary-outputs + +# Tool invocations +eCompass.elf: $(OBJS) $(USER_OBJS) D:\Users\Think\Programmation\STM32CUBEIDE\eCompass\STM32F401VCTX_FLASH.ld + arm-none-eabi-g++ -o "eCompass.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m4 -T"D:\Users\Think\Programmation\STM32CUBEIDE\eCompass\STM32F401VCTX_FLASH.ld" --specs=nosys.specs -Wl,-Map="eCompass.map" -Wl,--gc-sections -static --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -u _printf_float -u _scanf_float -Wl,--start-group -lc -lm -lstdc++ -lsupc++ -Wl,--end-group + @echo 'Finished building target: $@' + @echo ' ' + +default.size.stdout: $(EXECUTABLES) + arm-none-eabi-size $(EXECUTABLES) + @echo 'Finished building: $@' + @echo ' ' + +eCompass.list: $(EXECUTABLES) + arm-none-eabi-objdump -h -S $(EXECUTABLES) > "eCompass.list" + @echo 'Finished building: $@' + @echo ' ' + +eCompass.bin: $(EXECUTABLES) + arm-none-eabi-objcopy -O binary $(EXECUTABLES) "eCompass.bin" + @echo 'Finished building: $@' + @echo ' ' + +# Other Targets +clean: + -$(RM) * + -@echo ' ' + +secondary-outputs: $(SIZE_OUTPUT) $(OBJDUMP_LIST) $(OBJCOPY_BIN) + +fail-specified-linker-script-missing: + @echo 'Error: Cannot find the specified linker script. Check the linker settings in the build configuration.' + @exit 2 + +warn-no-linker-script-specified: + @echo 'Warning: No linker script specified. Check the linker settings in the build configuration.' + +.PHONY: all clean dependents fail-specified-linker-script-missing warn-no-linker-script-specified +.SECONDARY: + +-include ../makefile.targets diff --git a/Debug/objects.list b/Debug/objects.list new file mode 100644 index 0000000..14bd046 --- /dev/null +++ b/Debug/objects.list @@ -0,0 +1,41 @@ +"Core/Src/app.o" +"Core/Src/main.o" +"Core/Src/stm32f4xx_hal_msp.o" +"Core/Src/stm32f4xx_it.o" +"Core/Src/syscalls.o" +"Core/Src/sysmem.o" +"Core/Src/system_stm32f4xx.o" +"Core/Startup/startup_stm32f401vctx.o" +"Drivers/COMPASS_LEDS/COMPASS_LEDS.o" +"Drivers/LSM303DLHC/LSM303DLHC.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.o" +"Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Src/usbh_cdc.o" +"Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_core.o" +"Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ctlreq.o" +"Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ioreq.o" +"Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_pipes.o" +"USB_HOST/App/usb_host.o" +"USB_HOST/Target/usbh_conf.o" +"USB_HOST/Target/usbh_platform.o" diff --git a/Debug/objects.mk b/Debug/objects.mk new file mode 100644 index 0000000..742c2da --- /dev/null +++ b/Debug/objects.mk @@ -0,0 +1,8 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +USER_OBJS := + +LIBS := + diff --git a/Debug/sources.mk b/Debug/sources.mk new file mode 100644 index 0000000..66f231b --- /dev/null +++ b/Debug/sources.mk @@ -0,0 +1,41 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +ELF_SRCS := +C_UPPER_SRCS := +CXX_SRCS := +C++_SRCS := +OBJ_SRCS := +S_SRCS := +CC_SRCS := +C_SRCS := +CPP_SRCS := +S_UPPER_SRCS := +O_SRCS := +OBJDUMP_LIST := +C_UPPER_DEPS := +S_DEPS := +C_DEPS := +OBJCOPY_BIN := +CC_DEPS := +SIZE_OUTPUT := +C++_DEPS := +EXECUTABLES := +OBJS := +CXX_DEPS := +S_UPPER_DEPS := +CPP_DEPS := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +Core/Src \ +Core/Startup \ +Drivers/COMPASS_LEDS \ +Drivers/LSM303DLHC \ +Drivers/STM32F4xx_HAL_Driver/Src \ +Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Src \ +Middlewares/ST/STM32_USB_Host_Library/Core/Src \ +USB_HOST/App \ +USB_HOST/Target \ + diff --git a/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xc.h b/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xc.h new file mode 100644 index 0000000..812bae6 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xc.h @@ -0,0 +1,8634 @@ +/** + ****************************************************************************** + * @file stm32f401xc.h + * @author MCD Application Team + * @brief CMSIS STM32F401xC Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - peripherals registers declarations and bits definition + * - Macros to access peripheral’s registers hardware + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32f401xc + * @{ + */ + +#ifndef __STM32F401xC_H +#define __STM32F401xC_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001U /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */ +#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< FPU present */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32F4XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + SPI4_IRQn = 84 /*!< SPI4 global Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_stm32f4xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ + __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ + __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ + __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ + __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ + __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ + __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ + __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual + AND triple modes, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ +} CRC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ +} DMA_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ + __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ + __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ + __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ + __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ + __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */ + __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ +} GPIO_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ + __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */ + __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ + __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ + __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ + __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ + __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ +} IWDG_TypeDef; + + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ + __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, 0x1C */ + __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved, 0x3C */ + __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ + uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ + uint32_t RESERVED4; /*!< Reserved, 0x5C */ + __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ + uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ + __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ + uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ + __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ + __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ + uint32_t RESERVED7[1]; /*!< Reserved, 0x88 */ + __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */ + uint32_t RESERVED7; /*!< Reserved, 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ +} RTC_TypeDef; + +/** + * @brief SD host Interface + */ + +typedef struct +{ + __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ + __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ + __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ + __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ + __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ + __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ + __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ + __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ + __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ + uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ + __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ +} SDIO_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ +} USART_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; +/** + * @brief USB_OTG_Core_Registers + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */ + uint32_t Reserved30[2]; /*!< Reserved 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */ + __IO uint32_t CID; /*!< User ID Register 03Ch */ + uint32_t Reserved40[48]; /*!< Reserved 0x40-0xFF */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */ +} USB_OTG_GlobalTypeDef; + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register 800h */ + __IO uint32_t DCTL; /*!< dev Control Register 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */ + uint32_t Reserved0C; /*!< Reserved 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */ + uint32_t Reserved20; /*!< Reserved 820h */ + uint32_t Reserved9; /*!< Reserved 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */ + uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ +} USB_OTG_DeviceTypeDef; + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ + uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ + uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ +} USB_OTG_OUTEndpointTypeDef; + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */ + uint32_t Reserved40C; /*!< Reserved 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */ + uint32_t Reserved[2]; /*!< Reserved */ +} USB_OTG_HostChannelTypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define FLASH_BASE 0x08000000UL /*!< FLASH(up to 1 MB) base address in the alias region */ +#define SRAM1_BASE 0x20000000UL /*!< SRAM1(64 KB) base address in the alias region */ +#define PERIPH_BASE 0x40000000UL /*!< Peripheral base address in the alias region */ +#define SRAM1_BB_BASE 0x22000000UL /*!< SRAM1(64 KB) base address in the bit-band region */ +#define PERIPH_BB_BASE 0x42000000UL /*!< Peripheral base address in the bit-band region */ +#define BKPSRAM_BB_BASE 0x42480000UL /*!< Backup SRAM(4 KB) base address in the bit-band region */ +#define FLASH_END 0x0803FFFFUL /*!< FLASH end address */ +#define FLASH_OTP_BASE 0x1FFF7800UL /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */ +#define FLASH_OTP_END 0x1FFF7A0FUL /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */ + +/* Legacy defines */ +#define SRAM_BASE SRAM1_BASE +#define SRAM_BB_BASE SRAM1_BB_BASE + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000UL) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) +#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) +#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL) + +/*!< APB2 peripherals */ +#define TIM1_BASE (APB2PERIPH_BASE + 0x0000UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x1000UL) +#define USART6_BASE (APB2PERIPH_BASE + 0x1400UL) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2000UL) +#define ADC1_COMMON_BASE (APB2PERIPH_BASE + 0x2300UL) +/* Legacy define */ +#define ADC_BASE ADC1_COMMON_BASE +#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define SPI4_BASE (APB2PERIPH_BASE + 0x3400UL) +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800UL) +#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00UL) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4000UL) +#define TIM10_BASE (APB2PERIPH_BASE + 0x4400UL) +#define TIM11_BASE (APB2PERIPH_BASE + 0x4800UL) + +/*!< AHB1 peripherals */ +#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000UL) +#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00UL) +#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000UL) +#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00UL) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) +#define RCC_BASE (AHB1PERIPH_BASE + 0x3800UL) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00UL) +#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL) +#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL) +#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL) +#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL) +#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL) +#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL) +#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) +#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL) +#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL) +#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL) +#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) +#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL) +#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL) +#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL) +#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL) +#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL) +#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL) + + +/*!< Debug MCU registers base address */ +#define DBGMCU_BASE 0xE0042000UL +/*!< USB registers base address */ +#define USB_OTG_FS_PERIPH_BASE 0x50000000UL + +#define USB_OTG_GLOBAL_BASE 0x000UL +#define USB_OTG_DEVICE_BASE 0x800UL +#define USB_OTG_IN_ENDPOINT_BASE 0x900UL +#define USB_OTG_OUT_ENDPOINT_BASE 0xB00UL +#define USB_OTG_EP_REG_SIZE 0x20UL +#define USB_OTG_HOST_BASE 0x400UL +#define USB_OTG_HOST_PORT_BASE 0x440UL +#define USB_OTG_HOST_CHANNEL_BASE 0x500UL +#define USB_OTG_HOST_CHANNEL_SIZE 0x20UL +#define USB_OTG_PCGCCTL_BASE 0xE00UL +#define USB_OTG_FIFO_BASE 0x1000UL +#define USB_OTG_FIFO_SIZE 0x1000UL + +#define UID_BASE 0x1FFF7A10UL /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE 0x1FFF7A22UL /*!< FLASH Size register base address */ +#define PACKAGE_BASE 0x1FFF7BF0UL /*!< Package size register base address */ +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define USART6 ((USART_TypeDef *) USART6_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE) +/* Legacy define */ +#define ADC ADC1_COMMON +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SPI4 ((SPI_TypeDef *) SPI4_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) +#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) +#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) +#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) +#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) +#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) +#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) +#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) +#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) +#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) +#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) +#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) +#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) +#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) +#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) +#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for ADC_SR register ********************/ +#define ADC_SR_AWD_Pos (0U) +#define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos) /*!< 0x00000001 */ +#define ADC_SR_AWD ADC_SR_AWD_Msk /*!
© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.
+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx + * @{ + */ + +#ifndef __STM32F4xx_H +#define __STM32F4xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/** + * @brief STM32 Family + */ +#if !defined (STM32F4) +#define STM32F4 +#endif /* STM32F4 */ + +/* Uncomment the line below according to the target STM32 device used in your + application + */ +#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \ + !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \ + !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \ + !defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \ + !defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \ + !defined (STM32F412Zx) && !defined (STM32F413xx) && !defined (STM32F423xx) + /* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */ + /* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */ + /* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */ + /* #define STM32F417xx */ /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */ + /* #define STM32F427xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */ + /* #define STM32F437xx */ /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */ + /* #define STM32F429xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG, + STM32F439NI, STM32F429IG and STM32F429II Devices */ + /* #define STM32F439xx */ /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG, + STM32F439NI, STM32F439IG and STM32F439II Devices */ + /* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */ + /* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */ + /* #define STM32F410Tx */ /*!< STM32F410T8 and STM32F410TB Devices */ + /* #define STM32F410Cx */ /*!< STM32F410C8 and STM32F410CB Devices */ + /* #define STM32F410Rx */ /*!< STM32F410R8 and STM32F410RB Devices */ + /* #define STM32F411xE */ /*!< STM32F411CC, STM32F411RC, STM32F411VC, STM32F411CE, STM32F411RE and STM32F411VE Devices */ + /* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC, + and STM32F446ZE Devices */ + /* #define STM32F469xx */ /*!< STM32F469AI, STM32F469II, STM32F469BI, STM32F469NI, STM32F469AG, STM32F469IG, STM32F469BG, + STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */ + /* #define STM32F479xx */ /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG + and STM32F479NG Devices */ + /* #define STM32F412Cx */ /*!< STM32F412CEU and STM32F412CGU Devices */ + /* #define STM32F412Zx */ /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */ + /* #define STM32F412Vx */ /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */ + /* #define STM32F412Rx */ /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */ + /* #define STM32F413xx */ /*!< STM32F413CH, STM32F413MH, STM32F413RH, STM32F413VH, STM32F413ZH, STM32F413CG, STM32F413MG, + STM32F413RG, STM32F413VG and STM32F413ZG Devices */ + /* #define STM32F423xx */ /*!< STM32F423CH, STM32F423RH, STM32F423VH and STM32F423ZH Devices */ +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ +#if !defined (USE_HAL_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_HAL_DRIVER */ +#endif /* USE_HAL_DRIVER */ + +/** + * @brief CMSIS version number V2.6.5 + */ +#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */ +#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */ +#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x05U) /*!< [15:8] sub2 version */ +#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ +#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\ + |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\ + |(__STM32F4xx_CMSIS_VERSION_SUB2 << 8 )\ + |(__STM32F4xx_CMSIS_VERSION)) + +/** + * @} + */ + +/** @addtogroup Device_Included + * @{ + */ + +#if defined(STM32F405xx) + #include "stm32f405xx.h" +#elif defined(STM32F415xx) + #include "stm32f415xx.h" +#elif defined(STM32F407xx) + #include "stm32f407xx.h" +#elif defined(STM32F417xx) + #include "stm32f417xx.h" +#elif defined(STM32F427xx) + #include "stm32f427xx.h" +#elif defined(STM32F437xx) + #include "stm32f437xx.h" +#elif defined(STM32F429xx) + #include "stm32f429xx.h" +#elif defined(STM32F439xx) + #include "stm32f439xx.h" +#elif defined(STM32F401xC) + #include "stm32f401xc.h" +#elif defined(STM32F401xE) + #include "stm32f401xe.h" +#elif defined(STM32F410Tx) + #include "stm32f410tx.h" +#elif defined(STM32F410Cx) + #include "stm32f410cx.h" +#elif defined(STM32F410Rx) + #include "stm32f410rx.h" +#elif defined(STM32F411xE) + #include "stm32f411xe.h" +#elif defined(STM32F446xx) + #include "stm32f446xx.h" +#elif defined(STM32F469xx) + #include "stm32f469xx.h" +#elif defined(STM32F479xx) + #include "stm32f479xx.h" +#elif defined(STM32F412Cx) + #include "stm32f412cx.h" +#elif defined(STM32F412Zx) + #include "stm32f412zx.h" +#elif defined(STM32F412Rx) + #include "stm32f412rx.h" +#elif defined(STM32F412Vx) + #include "stm32f412vx.h" +#elif defined(STM32F413xx) + #include "stm32f413xx.h" +#elif defined(STM32F423xx) + #include "stm32f423xx.h" +#else + #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)" +#endif + +/** + * @} + */ + +/** @addtogroup Exported_types + * @{ + */ +typedef enum +{ + RESET = 0U, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0U, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + SUCCESS = 0U, + ERROR = !SUCCESS +} ErrorStatus; + +/** + * @} + */ + + +/** @addtogroup Exported_macro + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) + + +/** + * @} + */ + +#if defined (USE_HAL_DRIVER) + #include "stm32f4xx_hal.h" +#endif /* USE_HAL_DRIVER */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32F4xx_H */ +/** + * @} + */ + +/** + * @} + */ + + + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h b/Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h new file mode 100644 index 0000000..99cb936 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h @@ -0,0 +1,122 @@ +/** + ****************************************************************************** + * @file system_stm32f4xx.h + * @author MCD Application Team + * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32F4XX_H +#define __SYSTEM_STM32F4XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32F4xx_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32F4xx_System_Exported_types + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetSysClockFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ +extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32F4XX_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/CMSIS/Include/cmsis_armcc.h b/Drivers/CMSIS/Include/cmsis_armcc.h new file mode 100644 index 0000000..4d9d064 --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_armcc.h @@ -0,0 +1,865 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/Drivers/CMSIS/Include/cmsis_armclang.h b/Drivers/CMSIS/Include/cmsis_armclang.h new file mode 100644 index 0000000..162a400 --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_armclang.h @@ -0,0 +1,1869 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF); + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF); + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF); + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/Drivers/CMSIS/Include/cmsis_compiler.h b/Drivers/CMSIS/Include/cmsis_compiler.h new file mode 100644 index 0000000..94212eb --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_compiler.h @@ -0,0 +1,266 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/Drivers/CMSIS/Include/cmsis_gcc.h b/Drivers/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 0000000..2d9db15 --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,2085 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.0.4 + * @date 09. April 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/Drivers/CMSIS/Include/cmsis_iccarm.h b/Drivers/CMSIS/Include/cmsis_iccarm.h new file mode 100644 index 0000000..11c4af0 --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_iccarm.h @@ -0,0 +1,935 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.0.7 + * @date 19. June 2018 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2018 IAR Systems +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/Drivers/CMSIS/Include/cmsis_version.h b/Drivers/CMSIS/Include/cmsis_version.h new file mode 100644 index 0000000..660f612 --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.2 + * @date 19. April 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/Drivers/CMSIS/Include/core_armv8mbl.h b/Drivers/CMSIS/Include/core_armv8mbl.h new file mode 100644 index 0000000..251e4ed --- /dev/null +++ b/Drivers/CMSIS/Include/core_armv8mbl.h @@ -0,0 +1,1918 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 22. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_armv8mml.h b/Drivers/CMSIS/Include/core_armv8mml.h new file mode 100644 index 0000000..3a3148e --- /dev/null +++ b/Drivers/CMSIS/Include/core_armv8mml.h @@ -0,0 +1,2927 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 06. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm0.h b/Drivers/CMSIS/Include/core_cm0.h new file mode 100644 index 0000000..f929bba --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm0.h @@ -0,0 +1,949 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 28. May 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm0plus.h b/Drivers/CMSIS/Include/core_cm0plus.h new file mode 100644 index 0000000..424011a --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,1083 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 28. May 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; + +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm1.h b/Drivers/CMSIS/Include/core_cm1.h new file mode 100644 index 0000000..0ed678e --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm1.h @@ -0,0 +1,976 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 23. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm23.h b/Drivers/CMSIS/Include/core_cm23.h new file mode 100644 index 0000000..acbc5df --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm23.h @@ -0,0 +1,1993 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 22. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm3.h b/Drivers/CMSIS/Include/core_cm3.h new file mode 100644 index 0000000..74bff64 --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm3.h @@ -0,0 +1,1941 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 04. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm33.h b/Drivers/CMSIS/Include/core_cm33.h new file mode 100644 index 0000000..6cd2db7 --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm33.h @@ -0,0 +1,3002 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.0.9 + * @date 06. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_PCS_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm4.h b/Drivers/CMSIS/Include/core_cm4.h new file mode 100644 index 0000000..7d56873 --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm4.h @@ -0,0 +1,2129 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 04. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm7.h b/Drivers/CMSIS/Include/core_cm7.h new file mode 100644 index 0000000..a14dc62 --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm7.h @@ -0,0 +1,2671 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 04. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_INLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_INLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_INLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_INLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_INLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_INLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_INLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_INLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t)addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCIMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCIMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_sc000.h b/Drivers/CMSIS/Include/core_sc000.h new file mode 100644 index 0000000..9b67c92 --- /dev/null +++ b/Drivers/CMSIS/Include/core_sc000.h @@ -0,0 +1,1022 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 28. May 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_sc300.h b/Drivers/CMSIS/Include/core_sc300.h new file mode 100644 index 0000000..3e8a471 --- /dev/null +++ b/Drivers/CMSIS/Include/core_sc300.h @@ -0,0 +1,1915 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 04. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + uint32_t RESERVED1[1U]; +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/mpu_armv7.h b/Drivers/CMSIS/Include/mpu_armv7.h new file mode 100644 index 0000000..0142203 --- /dev/null +++ b/Drivers/CMSIS/Include/mpu_armv7.h @@ -0,0 +1,270 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if non-shareable) or 010b (if shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/Drivers/CMSIS/Include/mpu_armv8.h b/Drivers/CMSIS/Include/mpu_armv8.h new file mode 100644 index 0000000..62571da --- /dev/null +++ b/Drivers/CMSIS/Include/mpu_armv8.h @@ -0,0 +1,333 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M MPU + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + ((BASE & MPU_RBAR_BASE_Msk) | \ + ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/Drivers/CMSIS/Include/tz_context.h b/Drivers/CMSIS/Include/tz_context.h new file mode 100644 index 0000000..0d09749 --- /dev/null +++ b/Drivers/CMSIS/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/Drivers/COMPASS_LEDS/COMPASS_LEDS.c b/Drivers/COMPASS_LEDS/COMPASS_LEDS.c new file mode 100644 index 0000000..355c1da --- /dev/null +++ b/Drivers/COMPASS_LEDS/COMPASS_LEDS.c @@ -0,0 +1,77 @@ +/* + * COMPASS_LEDS.c + * + * Created on: Apr 3, 2021 + * Author: Think + */ + +#include "COMPASS_LEDS.h" + +bool COMPASS_LEDS_Init(COMPASS_LEDS *compassLeds) +{ + compassLeds->southLed.Pin = GPIO_PIN_15; + compassLeds->eastLed.Pin = GPIO_PIN_12; + compassLeds->northLed.Pin = GPIO_PIN_13; + compassLeds->westLed.Pin = GPIO_PIN_14; + + compassLeds->southLed.Mode = GPIO_MODE_OUTPUT_PP; + compassLeds->eastLed.Mode = GPIO_MODE_OUTPUT_PP; + compassLeds->northLed.Mode = GPIO_MODE_OUTPUT_PP; + compassLeds->westLed.Mode = GPIO_MODE_OUTPUT_PP; + + compassLeds->southLed.Speed = GPIO_SPEED_LOW; + compassLeds->eastLed.Speed = GPIO_SPEED_LOW; + compassLeds->northLed.Speed = GPIO_SPEED_LOW; + compassLeds->westLed.Speed = GPIO_SPEED_LOW; + + HAL_GPIO_Init(GPIOD, &compassLeds->southLed); + HAL_GPIO_Init(GPIOD, &compassLeds->eastLed); + HAL_GPIO_Init(GPIOD, &compassLeds->northLed); + HAL_GPIO_Init(GPIOD, &compassLeds->westLed); + + HAL_GPIO_WritePin(GPIOD, compassLeds->southLed.Pin, GPIO_PIN_RESET); + HAL_GPIO_WritePin(GPIOD, compassLeds->eastLed.Pin, GPIO_PIN_RESET); + HAL_GPIO_WritePin(GPIOD, compassLeds->northLed.Pin, GPIO_PIN_RESET); + HAL_GPIO_WritePin(GPIOD, compassLeds->westLed.Pin, GPIO_PIN_RESET); + + return true; +} + +bool COMPASS_LEDS_Light(COMPASS_LEDS *compassLeds, Heading heading) +{ + switch(heading) + { + case SOUTH: + HAL_GPIO_WritePin(GPIOD, compassLeds->southLed.Pin, GPIO_PIN_SET); + HAL_GPIO_WritePin(GPIOD, compassLeds->eastLed.Pin, GPIO_PIN_RESET); + HAL_GPIO_WritePin(GPIOD, compassLeds->northLed.Pin, GPIO_PIN_RESET); + HAL_GPIO_WritePin(GPIOD, compassLeds->westLed.Pin, GPIO_PIN_RESET); + break; + case NORTH: + HAL_GPIO_WritePin(GPIOD, compassLeds->southLed.Pin, GPIO_PIN_RESET); + HAL_GPIO_WritePin(GPIOD, compassLeds->eastLed.Pin, GPIO_PIN_RESET); + HAL_GPIO_WritePin(GPIOD, compassLeds->northLed.Pin, GPIO_PIN_SET); + HAL_GPIO_WritePin(GPIOD, compassLeds->westLed.Pin, GPIO_PIN_RESET); + break; + case EAST: + HAL_GPIO_WritePin(GPIOD, compassLeds->southLed.Pin, GPIO_PIN_RESET); + HAL_GPIO_WritePin(GPIOD, compassLeds->eastLed.Pin, GPIO_PIN_SET); + HAL_GPIO_WritePin(GPIOD, compassLeds->northLed.Pin, GPIO_PIN_RESET); + HAL_GPIO_WritePin(GPIOD, compassLeds->westLed.Pin, GPIO_PIN_RESET); + break; + case WEST: + HAL_GPIO_WritePin(GPIOD, compassLeds->southLed.Pin, GPIO_PIN_RESET); + HAL_GPIO_WritePin(GPIOD, compassLeds->eastLed.Pin, GPIO_PIN_RESET); + HAL_GPIO_WritePin(GPIOD, compassLeds->northLed.Pin, GPIO_PIN_RESET); + HAL_GPIO_WritePin(GPIOD, compassLeds->westLed.Pin, GPIO_PIN_SET); + break; + default: + HAL_GPIO_WritePin(GPIOD, compassLeds->southLed.Pin, GPIO_PIN_RESET); + HAL_GPIO_WritePin(GPIOD, compassLeds->eastLed.Pin, GPIO_PIN_RESET); + HAL_GPIO_WritePin(GPIOD, compassLeds->northLed.Pin, GPIO_PIN_RESET); + HAL_GPIO_WritePin(GPIOD, compassLeds->westLed.Pin, GPIO_PIN_RESET); + } + return true; +} + + diff --git a/Drivers/COMPASS_LEDS/COMPASS_LEDS.h b/Drivers/COMPASS_LEDS/COMPASS_LEDS.h new file mode 100644 index 0000000..b228950 --- /dev/null +++ b/Drivers/COMPASS_LEDS/COMPASS_LEDS.h @@ -0,0 +1,23 @@ +/* + * COMPASS_LEDS.h + * + * Created on: Apr 3, 2021 + * Author: Think + */ + +#ifndef COMPASS_LEDS_H_ +#define COMPASS_LEDS_H_ + +#include "stm32f4xx_hal.h" +#include "MY_TYPES.h" + +typedef enum {NORTH = 1, SOUTH = 2, WEST = 4, EAST = 8, NONE = 16} Heading; +typedef struct +{ + GPIO_InitTypeDef northLed, southLed, westLed, eastLed; +} COMPASS_LEDS; + +bool COMPASS_LEDS_Init(COMPASS_LEDS *compassLeds); +bool COMPASS_LEDS_Light(COMPASS_LEDS *compassLeds, Heading heading); + +#endif /* COMPASS_LEDS_H_ */ diff --git a/Drivers/LSM303DLHC/LSM303DLHC.c b/Drivers/LSM303DLHC/LSM303DLHC.c new file mode 100644 index 0000000..849132f --- /dev/null +++ b/Drivers/LSM303DLHC/LSM303DLHC.c @@ -0,0 +1,207 @@ +/* + * LSM303DLHC.c + * + * Created on: Apr 2, 2021 + * Author: Think + */ + +#include "LSM303DLHC.h" + +//Accelerometer sensor I2C address definition +static const uint8_t LMS303DLHC_ACCEL_ADDR = 0x19 << 1; + +//Magnetic sensor I2C address definition +static const uint8_t LMS303DLHC_COMP_ADDR = 0x1E << 1; + +//Accelerometer register definition +static const uint8_t _CTRL_REG1_A = 0x20; +static const uint8_t _CTRL_REG2_A = 0x21; +static const uint8_t _CTRL_REG3_A = 0x22; +static const uint8_t _CTRL_REG4_A = 0x23; +static const uint8_t _CTRL_REG5_A = 0x24; +static const uint8_t _CTRL_REG6_A = 0x25; +static const uint8_t _REFERENCE_A = 0x26; +static const uint8_t _STATUS_REG_A = 0x27; +static const uint8_t _OUT_X_L_A = 0x28; +static const uint8_t _OUT_X_H_A = 0x29; +static const uint8_t _OUT_Y_L_A = 0x2A; +static const uint8_t _OUT_Y_H_A = 0x2B; +static const uint8_t _OUT_Z_L_A = 0x2C; +static const uint8_t _OUT_Z_H_A = 0x2D; +static const uint8_t _FIFO_CTRL_REG_A = 0x2E; +static const uint8_t _FIFO_SRC_REG_A = 0x2F; +static const uint8_t _INT1_CFG_A = 0X30; +static const uint8_t _INT1_SRC_A = 0x31; +static const uint8_t _INT1_THS_A = 0x32; +static const uint8_t _INT1_DURATION_A = 0x33; +static const uint8_t _INT2_CFG_A = 0x34; +static const uint8_t _INT2_SRC_A = 0x35; +static const uint8_t _INT2_THS_A = 0x36; +static const uint8_t _INT2_DURATION_A = 0x37; +static const uint8_t _CLICK_CFG_A = 0x38; +static const uint8_t _CLICK_SRC_A = 0x39; +static const uint8_t _CLICK_THS_A = 0x3A; +static const uint8_t _TIME_LIMIT_A = 0x3B; +static const uint8_t _TIME_LATENCY_A = 0x3C; +static const uint8_t _TIME_WINDOW_A = 0x3D; + +//Magnetic sensor register definition +static const uint8_t _CRA_REG_M = 0x00; +static const uint8_t _CRB_REG_M = 0x01; +static const uint8_t _MR_REG_M = 0x02; +static const uint8_t _OUT_X_H_M = 0x03; +static const uint8_t _OUT_X_L_M = 0x04; +static const uint8_t _OUT_Z_H_M = 0x05; +static const uint8_t _OUT_Z_L_M = 0x06; +static const uint8_t _OUT_Y_H_M = 0x07; +static const uint8_t _OUT_Y_L_M = 0x08; +static const uint8_t _SR_REG_M = 0x09; +static const uint8_t _IRA_REG_M = 0x0A; +static const uint8_t _IRB_REG_M = 0x0B; +static const uint8_t _IRC_REG_M = 0x0C; +static const uint8_t _TEMP_OUT_H_M = 0x31; +static const uint8_t _TEMP_OUT_L_M = 0x32; + +//Driver function definition +bool LSM303_Init(LSM303 *device, I2C_HandleTypeDef *i2cHandler) +{ + if(!device || !i2cHandler)return false; + + device->i2cHandler = i2cHandler; + device->opMode = CONTINUOUS_CONVERSION; + device->enableTempSensor = false; + + return true; +} + +bool LSM303_EnableTemperatureSensor(LSM303 *device, bool enable) +{ + if(!device) return false; + + device->enableTempSensor = enable; + + return true; +} + + +bool LSM303_SetMagneticSensorOperationMode(LSM303 *device, OperationMode opMode) +{ + if(!device) return false; + + device->opMode = opMode; + + return true; +} + +bool LSM303_ApplyConfig(LSM303 *device) +{ + if(!device) return false; + + //We apply the temperature config + uint8_t data = 0; + if(!LSM303_ReadRegister(device, CRA_REG_M, &data)) + return false; + + if(device->enableTempSensor) + { + if(!LSM303_WriteRegister(device, CRA_REG_M, data | (1 << 7))) + return false; + } + else + { + if(!LSM303_WriteRegister(device, CRA_REG_M, data & ~(1 << 7))) + return false; + } + + //We apply the operation mode + if(!LSM303_WriteRegister(device, MR_REG_M, device->opMode)) + return false; + + return true; +} + +bool LSM303_GetDeviceID(LSM303 *device, uint8_t id[3]) +{ + if(!device) return false; + + HAL_StatusTypeDef status = HAL_I2C_Master_Transmit(device->i2cHandler, LMS303DLHC_COMP_ADDR, (uint8_t *)&_IRA_REG_M, 1, HAL_MAX_DELAY); + if(status != HAL_OK) + return false; + + return HAL_I2C_Master_Receive(device->i2cHandler, LMS303DLHC_COMP_ADDR, id, 3, HAL_MAX_DELAY) == HAL_OK ? true : false; +} + +bool LSM303_GetTemperature(LSM303 *device, float *temperature, int16_t *rawValue) +{ + if(!device) return false; + uint8_t data[2]; + int16_t orderedData; + + HAL_StatusTypeDef status = HAL_I2C_Master_Transmit(device->i2cHandler, LMS303DLHC_COMP_ADDR, (uint8_t *)&_TEMP_OUT_H_M, 1, HAL_MAX_DELAY); + if(status != HAL_OK) + return false; + + status = HAL_I2C_Master_Receive(device->i2cHandler, LMS303DLHC_COMP_ADDR, data, 2, HAL_MAX_DELAY); + if(status != HAL_OK) + return false; + + //We switch the bytes... + ((uint8_t *)&orderedData)[0] = data[1]; + ((uint8_t *)&orderedData)[1] = data[0]; + + if(rawValue) + *rawValue = orderedData; + + if(temperature) + *temperature = (float)orderedData / 256; + + return true; +} + +bool LSM303_GetMagneticFieldData(LSM303 *device, int16_t *xAxis, int16_t *yAxis, int16_t *zAxis) +{ + if(!device) return false; + + uint8_t data[6]; + int16_t x,y,z; + + HAL_StatusTypeDef status = HAL_I2C_Master_Transmit(device->i2cHandler, LMS303DLHC_COMP_ADDR, (uint8_t *)&_OUT_X_H_M, 1, HAL_MAX_DELAY); + if(status != HAL_OK) + return false; + + //We now read all six registers + status = HAL_I2C_Master_Receive(device->i2cHandler, LMS303DLHC_COMP_ADDR, data, 8, HAL_MAX_DELAY); + if(status != HAL_OK) + return false; + + //We switch the bytes... + ((uint8_t *)&x)[0] = data[1]; + ((uint8_t *)&x)[1] = data[0]; + ((uint8_t *)&z)[0] = data[3]; + ((uint8_t *)&z)[1] = data[2]; + ((uint8_t *)&y)[0] = data[5]; + ((uint8_t *)&y)[1] = data[4]; + + if(xAxis) + *xAxis = x; + if(yAxis) + *yAxis = y; + if(zAxis) + *zAxis = z; + + return true; +} + +bool LSM303_ReadRegister(LSM303 *device, uint8_t registerAddr, uint8_t *data) +{ + HAL_StatusTypeDef status = HAL_I2C_Master_Transmit(device->i2cHandler, LMS303DLHC_COMP_ADDR, ®isterAddr, 1, HAL_MAX_DELAY); + if(status != HAL_OK) + return false; + return HAL_I2C_Master_Receive(device->i2cHandler, LMS303DLHC_COMP_ADDR, data, 1, HAL_MAX_DELAY) == HAL_OK ? true : false; +} + +bool LSM303_WriteRegister(LSM303 *device, uint8_t registerAddr, uint8_t data) +{ + uint8_t regAndData[] = {registerAddr, data}; + return HAL_I2C_Master_Transmit(device->i2cHandler, LMS303DLHC_COMP_ADDR, regAndData, 2, HAL_MAX_DELAY) == HAL_OK ? true : false; +} diff --git a/Drivers/LSM303DLHC/LSM303DLHC.h b/Drivers/LSM303DLHC/LSM303DLHC.h new file mode 100644 index 0000000..c9cf251 --- /dev/null +++ b/Drivers/LSM303DLHC/LSM303DLHC.h @@ -0,0 +1,84 @@ +/** + * + * LSM303DLHC driver + * Anatole SCHRAMM-HENRY All right reserved + * + */ +#ifndef LSM303DLHC_H +#define LSM303DLHC_H + +#include +#include "stm32f4xx_hal.h" +#include "MY_TYPES.h" + +//Accelerometer register definition +#define CTRL_REG1_A 0x20 +#define CTRL_REG2_A 0x21 +#define CTRL_REG3_A 0x22 +#define CTRL_REG4_A 0x23 +#define CTRL_REG5_A 0x24 +#define CTRL_REG6_A 0x25 +#define REFERENCE_A 0x26 +#define STATUS_REG_A 0x27 +#define OUT_X_L_A 0x28 +#define OUT_X_H_A 0x29 +#define OUT_Y_L_A 0x2A +#define OUT_Y_H_A 0x2B +#define OUT_Z_L_A 0x2C +#define OUT_Z_H_A 0x2D +#define FIFO_CTRL_REG_A 0x2E +#define FIFO_SRC_REG_A 0x2F +#define INT1_CFG_A 0X30 +#define INT1_SRC_A 0x31 +#define INT1_THS_A 0x32 +#define INT1_DURATION_A 0x33 +#define INT2_CFG_A 0x34 +#define INT2_SRC_A 0x35 +#define INT2_THS_A 0x36 +#define INT2_DURATION_A 0x37 +#define CLICK_CFG_A 0x38 +#define CLICK_SRC_A 0x39 +#define CLICK_THS_A 0x3A +#define TIME_LIMIT_A 0x3B +#define TIME_LATENCY_A 0x3C +#define TIME_WINDOW_A 0x3D + +//Magnetic sensor register definition +#define CRA_REG_M 0x00 +#define CRB_REG_M 0x01 +#define MR_REG_M 0x02 +#define OUT_X_H_M 0x03 +#define OUT_X_L_M 0x04 +#define OUT_Z_H_M 0x05 +#define OUT_Z_L_M 0x06 +#define OUT_Y_H_M 0x07 +#define OUT_Y_L_M 0x08 +#define SR_REG_M 0x09 +#define IRA_REG_M 0x0A +#define IRB_REG_M 0x0B +#define IRC_REG_M 0x0C +#define TEMP_OUT_H_M 0x31 +#define TEMP_OUT_L_M 0x32 + +typedef enum {CONTINUOUS_CONVERSION = 0x00, SINGLE_CONVERSION = 0x01, SLEEP_MODE = 0x3} OperationMode; + +//LSM Structure +typedef struct +{ + I2C_HandleTypeDef *i2cHandler; + OperationMode opMode; + bool enableTempSensor : 1; +} LSM303; + +//Driver function declaration +bool LSM303_Init(LSM303 *device, I2C_HandleTypeDef *i2cHandler); +bool LSM303_EnableTemperatureSensor(LSM303 *device, bool enable); +bool LSM303_SetMagneticSensorOperationMode(LSM303 *device, OperationMode opMode); +bool LSM303_ApplyConfig(LSM303 *device); +bool LSM303_GetDeviceID(LSM303 *device, uint8_t id[3]); +bool LSM303_GetTemperature(LSM303 *device, float *temperature, int16_t *rawValue); +bool LSM303_GetMagneticFieldData(LSM303 *device, int16_t *xAxis, int16_t *yAxis, int16_t *zAxis); +bool LSM303_ReadRegister(LSM303 *device, uint8_t registerAddr, uint8_t *data); +bool LSM303_WriteRegister(LSM303 *device, uint8_t registerAddr, uint8_t data); + +#endif //LSM303DLHC_H diff --git a/Drivers/MY_TYPES/MY_TYPES.h b/Drivers/MY_TYPES/MY_TYPES.h new file mode 100644 index 0000000..b0be849 --- /dev/null +++ b/Drivers/MY_TYPES/MY_TYPES.h @@ -0,0 +1,13 @@ +/* + * MY_TYPES.h + * + * Created on: Apr 3, 2021 + * Author: Think + */ + +#ifndef MY_TYPES_H_ +#define MY_TYPES_H_ + +typedef enum {false = 0, true = !false} bool; + +#endif /* MY_TYPES_H_ */ diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h new file mode 100644 index 0000000..90767ed --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -0,0 +1,3776 @@ +/** + ****************************************************************************** + * @file stm32_hal_legacy.h + * @author MCD Application Team + * @brief This file contains aliases definition for the STM32Cube HAL constants + * macros and functions maintained for legacy purpose. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32_HAL_LEGACY +#define STM32_HAL_LEGACY + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose + * @{ + */ +#define AES_FLAG_RDERR CRYP_FLAG_RDERR +#define AES_FLAG_WRERR CRYP_FLAG_WRERR +#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF +#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR +#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR + +/** + * @} + */ + +/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose + * @{ + */ +#define ADC_RESOLUTION12b ADC_RESOLUTION_12B +#define ADC_RESOLUTION10b ADC_RESOLUTION_10B +#define ADC_RESOLUTION8b ADC_RESOLUTION_8B +#define ADC_RESOLUTION6b ADC_RESOLUTION_6B +#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN +#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED +#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV +#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV +#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV +#define REGULAR_GROUP ADC_REGULAR_GROUP +#define INJECTED_GROUP ADC_INJECTED_GROUP +#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP +#define AWD_EVENT ADC_AWD_EVENT +#define AWD1_EVENT ADC_AWD1_EVENT +#define AWD2_EVENT ADC_AWD2_EVENT +#define AWD3_EVENT ADC_AWD3_EVENT +#define OVR_EVENT ADC_OVR_EVENT +#define JQOVF_EVENT ADC_JQOVF_EVENT +#define ALL_CHANNELS ADC_ALL_CHANNELS +#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS +#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS +#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR +#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT +#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 +#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 +#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 +#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 +#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 +#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO +#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 +#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO +#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 +#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO +#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 +#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 +#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE +#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING +#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING +#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING +#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 + +#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY +#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY +#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC +#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC +#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL +#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL +#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 + +#if defined(STM32H7) +#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT +#endif /* STM32H7 */ +/** + * @} + */ + +/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose + * @{ + */ +#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE +#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE +#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 +#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 +#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 +#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 +#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 +#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 +#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 +#if defined(STM32L0) +#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ +#endif +#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR +#if defined(STM32F373xC) || defined(STM32F378xx) +#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 +#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR +#endif /* STM32F373xC || STM32F378xx */ + +#if defined(STM32L0) || defined(STM32L4) +#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON + +#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 +#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 +#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 +#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 +#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 +#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 + +#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT +#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT +#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT +#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT +#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 +#if defined(STM32L0) +/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ +/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ +/* to the second dedicated IO (only for COMP2). */ +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 +#else +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 +#endif +#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 +#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 + +#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW +#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH + +/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ +/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ +#if defined(COMP_CSR_LOCK) +#define COMP_FLAG_LOCK COMP_CSR_LOCK +#elif defined(COMP_CSR_COMP1LOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK +#elif defined(COMP_CSR_COMPxLOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK +#endif + +#if defined(STM32L4) +#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 +#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 +#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 +#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 +#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE +#endif + +#if defined(STM32L0) +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER +#else +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED +#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER +#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER +#endif + +#endif +/** + * @} + */ + +/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose + * @{ + */ +#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig +/** + * @} + */ + +/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE +#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define DAC1_CHANNEL_1 DAC_CHANNEL_1 +#define DAC1_CHANNEL_2 DAC_CHANNEL_2 +#define DAC2_CHANNEL_1 DAC_CHANNEL_1 +#define DAC_WAVE_NONE 0x00000000U +#define DAC_WAVE_NOISE DAC_CR_WAVE1_0 +#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 +#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE +#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE +#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE + +#if defined(STM32G4) || defined(STM32H7) +#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL +#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL +#endif + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) +#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID +#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID +#endif + +/** + * @} + */ + +/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 +#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 +#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 +#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 +#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 +#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 +#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 +#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 +#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 +#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 +#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 +#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 +#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 +#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 + +#define IS_HAL_REMAPDMA IS_DMA_REMAP +#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE +#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE + +#if defined(STM32L4) + +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15 +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE +#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT +#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT +#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI +#endif + +#endif /* STM32L4 */ + +#if defined(STM32G0) +#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 +#endif + +#if defined(STM32H7) + +#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 + +#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX +#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX + +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO + +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 +#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT +#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT +#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT + +#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT +#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT + +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD +#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD +#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS +#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES +#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES +#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE +#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE +#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE +#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE +#define OBEX_PCROP OPTIONBYTE_PCROP +#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG +#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE +#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE +#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE +#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD +#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD +#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE +#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD +#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD +#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE +#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD +#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD +#define PAGESIZE FLASH_PAGE_SIZE +#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD +#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 +#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 +#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 +#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 +#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST +#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST +#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA +#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB +#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA +#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB +#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE +#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN +#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE +#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN +#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE +#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD +#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP +#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV +#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR +#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA +#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS +#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST +#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR +#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO +#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS +#define OB_WDG_SW OB_IWDG_SW +#define OB_WDG_HW OB_IWDG_HW +#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET +#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET +#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET +#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET +#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR +#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 +#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 +#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 +#if defined(STM32G0) +#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE +#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH +#else +#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE +#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE +#endif +#if defined(STM32H7) +#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 +#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 +#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 +#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 +#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 +#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 +#define FLASH_FLAG_WDW FLASH_FLAG_WBNE +#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose + * @{ + */ + +#if defined(STM32H7) +#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE +#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE +#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET +#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET +#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE +#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose + * @{ + */ + +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 +#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 +#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 +#if defined(STM32G4) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD +#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD +#endif /* STM32G4 */ +/** + * @} + */ + + +/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose + * @{ + */ +#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) +#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE +#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE +#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 +#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 +#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) +#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE +#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE +#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 +#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 +#endif +/** + * @} + */ + +/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef +#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef +/** + * @} + */ + +/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose + * @{ + */ +#define GET_GPIO_SOURCE GPIO_GET_INDEX +#define GET_GPIO_INDEX GPIO_GET_INDEX + +#if defined(STM32F4) +#define GPIO_AF12_SDMMC GPIO_AF12_SDIO +#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO +#endif + +#if defined(STM32F7) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#if defined(STM32L4) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#if defined(STM32H7) +#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1 +#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1 +#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1 +#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 +#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 +#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 + +#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \ + defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx) +#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS +#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS +#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS +#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */ +#endif /* STM32H7 */ + +#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 +#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 +#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 + +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/ + +#if defined(STM32L1) + #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW + #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM + #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH + #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L1 */ + +#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) + #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW + #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM + #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH +#endif /* STM32F0 || STM32F3 || STM32F1 */ + +#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 +/** + * @} + */ + +/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 + +#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER +#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER +#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD +#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD +#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER +#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER +#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE +#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE + +#if defined(STM32G4) +#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig +#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable +#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable +#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset +#endif /* STM32G4 */ + +#if defined(STM32H7) +#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 + +#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 +#endif /* STM32H7 */ + +#if defined(STM32F3) +/** @brief Constants defining available sources associated to external events. + */ +#define HRTIM_EVENTSRC_1 (0x00000000U) +#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) +#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) +#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) + +/** @brief Constants defining the events that can be selected to configure the + * set/reset crossbar of a timer output + */ +#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) +#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) +#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) +#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) +#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) +#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) +#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) +#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) +#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) + +#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1) +#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2) +#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3) +#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4) +#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5) +#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6) +#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7) +#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8) +#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9) + +/** @brief Constants defining the event filtering applied to external events + * by a timer + */ +#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U) +#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) +#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) +#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) +#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) + +/** @brief Constants defining the DLL calibration periods (in micro seconds) + */ +#define HRTIM_CALIBRATIONRATE_7300 0x00000000U +#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) +#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) +#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) + +#endif /* STM32F3 */ +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE +#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE +#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE +#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE +#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE +#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE +#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE +#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE +#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) +#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX +#endif +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose + * @{ + */ +#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE +#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define KR_KEY_RELOAD IWDG_KEY_RELOAD +#define KR_KEY_ENABLE IWDG_KEY_ENABLE +#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE +#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE +/** + * @} + */ + +/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose + * @{ + */ + +#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION +#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS + +#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING +#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING +#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING + +#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION +#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS + +/* The following 3 definition have also been present in a temporary version of lptim.h */ +/* They need to be renamed also to the right name, just in case */ +#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS + +/** + * @} + */ + +/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b +#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b +#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b +#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b + +#define NAND_AddressTypedef NAND_AddressTypeDef + +#define __ARRAY_ADDRESS ARRAY_ADDRESS +#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE +#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE +#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE +#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE +/** + * @} + */ + +/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose + * @{ + */ +#define NOR_StatusTypedef HAL_NOR_StatusTypeDef +#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS +#define NOR_ONGOING HAL_NOR_STATUS_ONGOING +#define NOR_ERROR HAL_NOR_STATUS_ERROR +#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT + +#define __NOR_WRITE NOR_WRITE +#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT +/** + * @} + */ + +/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose + * @{ + */ + +#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 +#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 +#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 +#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 + +#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 +#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 +#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 +#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 + +#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 +#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO +#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 +#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) +#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID +#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID +#endif + + +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS + +#if defined(STM32H7) + #define I2S_IT_TXE I2S_IT_TXP + #define I2S_IT_RXNE I2S_IT_RXP + + #define I2S_FLAG_TXE I2S_FLAG_TXP + #define I2S_FLAG_RXNE I2S_FLAG_RXP +#endif + +#if defined(STM32F7) + #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL +#endif +/** + * @} + */ + +/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose + * @{ + */ + +/* Compact Flash-ATA registers description */ +#define CF_DATA ATA_DATA +#define CF_SECTOR_COUNT ATA_SECTOR_COUNT +#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER +#define CF_CYLINDER_LOW ATA_CYLINDER_LOW +#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH +#define CF_CARD_HEAD ATA_CARD_HEAD +#define CF_STATUS_CMD ATA_STATUS_CMD +#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE +#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA + +/* Compact Flash-ATA commands */ +#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD +#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD +#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD +#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD + +#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef +#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS +#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING +#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR +#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FORMAT_BIN RTC_FORMAT_BIN +#define FORMAT_BCD RTC_FORMAT_BCD + +#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE +#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE +#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE + +#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE +#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE +#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT +#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT + +#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT +#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 + +#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE +#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 +#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 + +#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT +#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 +#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 + +#if defined(STM32H7) +#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X +#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT + +#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 +#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 +#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 +#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL +#endif /* STM32H7 */ + +/** + * @} + */ + + +/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE +#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE + +#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE +#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE + +#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE +#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE + +#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE +#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE +/** + * @} + */ + + +/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE +#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE +#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE +#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE +#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE +#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE +#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE +#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE +#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE +#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE +#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose + * @{ + */ +#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE +#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE + +#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE +#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE + +#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE +#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE + +#if defined(STM32H7) + + #define SPI_FLAG_TXE SPI_FLAG_TXP + #define SPI_FLAG_RXNE SPI_FLAG_RXP + + #define SPI_IT_TXE SPI_IT_TXP + #define SPI_IT_RXNE SPI_IT_RXP + + #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET + #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET + #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET + #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET + +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose + * @{ + */ +#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK +#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK + +#define TIM_DMABase_CR1 TIM_DMABASE_CR1 +#define TIM_DMABase_CR2 TIM_DMABASE_CR2 +#define TIM_DMABase_SMCR TIM_DMABASE_SMCR +#define TIM_DMABase_DIER TIM_DMABASE_DIER +#define TIM_DMABase_SR TIM_DMABASE_SR +#define TIM_DMABase_EGR TIM_DMABASE_EGR +#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 +#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 +#define TIM_DMABase_CCER TIM_DMABASE_CCER +#define TIM_DMABase_CNT TIM_DMABASE_CNT +#define TIM_DMABase_PSC TIM_DMABASE_PSC +#define TIM_DMABase_ARR TIM_DMABASE_ARR +#define TIM_DMABase_RCR TIM_DMABASE_RCR +#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 +#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 +#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 +#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 +#define TIM_DMABase_BDTR TIM_DMABASE_BDTR +#define TIM_DMABase_DCR TIM_DMABASE_DCR +#define TIM_DMABase_DMAR TIM_DMABASE_DMAR +#define TIM_DMABase_OR1 TIM_DMABASE_OR1 +#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 +#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 +#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 +#define TIM_DMABase_OR2 TIM_DMABASE_OR2 +#define TIM_DMABase_OR3 TIM_DMABASE_OR3 +#define TIM_DMABase_OR TIM_DMABASE_OR + +#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE +#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 +#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 +#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 +#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 +#define TIM_EventSource_COM TIM_EVENTSOURCE_COM +#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER +#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK +#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 + +#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER +#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS +#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS +#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS +#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS +#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS +#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS +#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS +#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS +#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS +#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS +#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS +#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS +#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS +#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS +#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS +#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS +#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS + +#if defined(STM32L0) +#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO +#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO +#endif + +#if defined(STM32F3) +#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE +#endif + +#if defined(STM32H7) +#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1 +#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2 +#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1 +#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2 +#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1 +#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2 +#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1 +#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1 +#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2 +#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1 +#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2 +#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2 +#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1 +#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2 +#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 +#endif + +/** + * @} + */ + +/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose + * @{ + */ +#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING +#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose + * @{ + */ +#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE +#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE + +#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE +#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE + +#define __DIV_SAMPLING16 UART_DIV_SAMPLING16 +#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 +#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 +#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 + +#define __DIV_SAMPLING8 UART_DIV_SAMPLING8 +#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 +#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 +#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 + +#define __DIV_LPUART UART_DIV_LPUART + +#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE +#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose + * @{ + */ + +#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE +#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE + +#define USARTNACK_ENABLED USART_NACK_ENABLE +#define USARTNACK_DISABLED USART_NACK_DISABLE +/** + * @} + */ + +/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define CFR_BASE WWDG_CFR_BASE + +/** + * @} + */ + +/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose + * @{ + */ +#define CAN_FilterFIFO0 CAN_FILTER_FIFO0 +#define CAN_FilterFIFO1 CAN_FILTER_FIFO1 +#define CAN_IT_RQCP0 CAN_IT_TME +#define CAN_IT_RQCP1 CAN_IT_TME +#define CAN_IT_RQCP2 CAN_IT_TME +#define INAK_TIMEOUT CAN_TIMEOUT_VALUE +#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE +#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) +#define CAN_TXSTATUS_OK ((uint8_t)0x01U) +#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) + +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define VLAN_TAG ETH_VLAN_TAG +#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD +#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD +#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD +#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK +#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK +#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK +#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK + +#define ETH_MMCCR 0x00000100U +#define ETH_MMCRIR 0x00000104U +#define ETH_MMCTIR 0x00000108U +#define ETH_MMCRIMR 0x0000010CU +#define ETH_MMCTIMR 0x00000110U +#define ETH_MMCTGFSCCR 0x0000014CU +#define ETH_MMCTGFMSCCR 0x00000150U +#define ETH_MMCTGFCR 0x00000168U +#define ETH_MMCRFCECR 0x00000194U +#define ETH_MMCRFAECR 0x00000198U +#define ETH_MMCRGUFCR 0x000001C4U + +#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ +#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ +#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ +#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ +#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ +#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ +#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ +#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */ +#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ +#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ +#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ +#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ +#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ +#if defined(STM32F1) +#else +#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ +#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ +#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ +#endif +#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ +#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ +#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ +#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ +#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ + +/** + * @} + */ + +/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR +#define DCMI_IT_OVF DCMI_IT_OVR +#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI +#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI + +#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop +#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop +#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop + +/** + * @} + */ + +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ + || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ + || defined(STM32H7) +/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose + * @{ + */ +#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 +#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 +#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 +#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 +#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 + +#define CM_ARGB8888 DMA2D_INPUT_ARGB8888 +#define CM_RGB888 DMA2D_INPUT_RGB888 +#define CM_RGB565 DMA2D_INPUT_RGB565 +#define CM_ARGB1555 DMA2D_INPUT_ARGB1555 +#define CM_ARGB4444 DMA2D_INPUT_ARGB4444 +#define CM_L8 DMA2D_INPUT_L8 +#define CM_AL44 DMA2D_INPUT_AL44 +#define CM_AL88 DMA2D_INPUT_AL88 +#define CM_L4 DMA2D_INPUT_L4 +#define CM_A8 DMA2D_INPUT_A8 +#define CM_A4 DMA2D_INPUT_A4 +/** + * @} + */ +#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ + +/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback +/** + * @} + */ + +/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef +#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef +#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish +#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish +#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish +#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish + +/*HASH Algorithm Selection*/ + +#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 +#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 +#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 +#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 + +#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH +#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC + +#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY +#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY + +#if defined(STM32L4) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) + +#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt +#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End +#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT +#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT + +#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt +#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End +#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT +#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT + +#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt +#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End +#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT +#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT + +#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt +#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End +#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT +#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT + +#endif /* STM32L4 || STM32F4 || STM32F7 || STM32H7 */ +/** + * @} + */ + +/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode +#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode +#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode +#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode +#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode +#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode +#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) +#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect +#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) +#if defined(STM32L0) +#else +#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) +#endif +#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) +#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) +#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) +#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode +#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode +#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode +#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode +#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */ + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram +#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown +#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown +#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock +#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock +#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase +#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program + + /** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter +#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter +#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter +#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter + +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) + +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) +#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT +#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT +#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT +#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */ +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) +#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA +#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA +#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA +#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */ + +#if defined(STM32F4) +#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT +#define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT +#define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT +#define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT +#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA +#define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA +#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA +#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA +#endif /* STM32F4 */ + /** + * @} + */ + +/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose + * @{ + */ + +#if defined(STM32G0) +#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD +#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD +#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD +#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler +#endif +#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD +#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg +#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown +#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor +#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg +#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown +#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor +#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler +#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD +#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler +#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback +#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive +#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive +#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC +#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC +#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM + +#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL +#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING +#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING +#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING +#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING +#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING +#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING + +#define CR_OFFSET_BB PWR_CR_OFFSET_BB +#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB +#define PMODE_BIT_NUMBER VOS_BIT_NUMBER +#define CR_PMODE_BB CR_VOS_BB + +#define DBP_BitNumber DBP_BIT_NUMBER +#define PVDE_BitNumber PVDE_BIT_NUMBER +#define PMODE_BitNumber PMODE_BIT_NUMBER +#define EWUP_BitNumber EWUP_BIT_NUMBER +#define FPDS_BitNumber FPDS_BIT_NUMBER +#define ODEN_BitNumber ODEN_BIT_NUMBER +#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER +#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER +#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER +#define BRE_BitNumber BRE_BIT_NUMBER + +#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL + + /** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT +#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback +#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt +#define HAL_TIM_DMAError TIM_DMAError +#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt +#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt +#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) +#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro +#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT +#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback +#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent +#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT +#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA +#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */ +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback +#define HAL_LTDC_Relaod HAL_LTDC_Reload +#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig +#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig +/** + * @} + */ + + +/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported macros ------------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose + * @{ + */ +#define AES_IT_CC CRYP_IT_CC +#define AES_IT_ERR CRYP_IT_ERR +#define AES_FLAG_CCF CRYP_FLAG_CCF +/** + * @} + */ + +/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE +#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH +#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH +#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM +#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC +#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM +#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC +#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI +#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK +#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG +#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG +#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE +#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE +#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE + +#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY +#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 +#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS +#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER +#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER + +/** + * @} + */ + + +/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __ADC_ENABLE __HAL_ADC_ENABLE +#define __ADC_DISABLE __HAL_ADC_DISABLE +#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS +#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS +#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE +#define __ADC_IS_ENABLED ADC_IS_ENABLE +#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR +#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR +#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING +#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE + +#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION +#define __HAL_ADC_JSQR_RK ADC_JSQR_RK +#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT +#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR +#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION +#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE +#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS +#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM +#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT +#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS +#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN +#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ +#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET +#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET +#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL +#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL +#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET +#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET +#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD + +#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION +#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER +#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI +#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER +#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER +#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE + +#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT +#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT +#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL +#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM +#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET +#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE +#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE +#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER + +#define __HAL_ADC_SQR1 ADC_SQR1 +#define __HAL_ADC_SMPR1 ADC_SMPR1 +#define __HAL_ADC_SMPR2 ADC_SMPR2 +#define __HAL_ADC_SQR3_RK ADC_SQR3_RK +#define __HAL_ADC_SQR2_RK ADC_SQR2_RK +#define __HAL_ADC_SQR1_RK ADC_SQR1_RK +#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS +#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS +#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV +#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection +#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq +#define __HAL_ADC_JSQR ADC_JSQR + +#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL +#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF +#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT +#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS +#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN +#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR +#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT +#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT +#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT +#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE + +/** + * @} + */ + +/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 +#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 +#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 +#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 +#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 +#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 +#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 +#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 +#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 +#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 +#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 +#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 +#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 +#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 +#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 +#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 + +#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 +#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 +#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 +#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 +#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 +#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 +#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 +#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 +#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 +#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 +#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 +#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 +#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 +#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 + + +#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 +#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 +#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 +#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 +#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 +#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 +#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC +#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC +#if defined(STM32H7) + #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 + #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 + #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 + #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 +#else + #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG + #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG + #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG + #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG +#endif /* STM32H7 */ +#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT +#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT +#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT +#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT +#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT +#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT +#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 +#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 +#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 +#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 +#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 +#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32F3) +#define COMP_START __HAL_COMP_ENABLE +#define COMP_STOP __HAL_COMP_DISABLE +#define COMP_LOCK __HAL_COMP_LOCK + +#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +# endif +# if defined(STM32F302xE) || defined(STM32F302xC) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +# endif +# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP7_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) +# endif +# if defined(STM32F373xC) ||defined(STM32F378xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +# endif +#else +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +#endif + +#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE + +#if defined(STM32L0) || defined(STM32L4) +/* Note: On these STM32 families, the only argument of this macro */ +/* is COMP_FLAG_LOCK. */ +/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ +/* argument. */ +#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) +#endif +/** + * @} + */ + +#if defined(STM32L0) || defined(STM32L4) +/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ +#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ +/** + * @} + */ +#endif + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ + ((WAVE) == DAC_WAVE_NOISE)|| \ + ((WAVE) == DAC_WAVE_TRIANGLE)) + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_WRPAREA IS_OB_WRPAREA +#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM +#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM +#define IS_TYPEERASE IS_FLASH_TYPEERASE +#define IS_NBSECTORS IS_FLASH_NBSECTORS +#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE + +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 +#define __HAL_I2C_GENERATE_START I2C_GENERATE_START +#if defined(STM32F1) +#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE +#else +#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE +#endif /* STM32F1 */ +#define __HAL_I2C_RISE_TIME I2C_RISE_TIME +#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD +#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST +#define __HAL_I2C_SPEED I2C_SPEED +#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE +#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ +#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS +#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE +#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ +#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB +#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB +#define __HAL_I2C_FREQRANGE I2C_FREQRANGE +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE +#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT + +#if defined(STM32H7) + #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG +#endif + +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __IRDA_DISABLE __HAL_IRDA_DISABLE +#define __IRDA_ENABLE __HAL_IRDA_ENABLE + +#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION +#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION + +#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE + + +/** + * @} + */ + + +/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS +#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS +/** + * @} + */ + + +/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT +#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT +#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE + +/** + * @} + */ + + +/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose + * @{ + */ +#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD +#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX +#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX +#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX +#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX +#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L +#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H +#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM +#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES +#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX +#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT +#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION +#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET + +/** + * @} + */ + + +/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE +#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE +#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine +#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig +#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) +#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) +#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention +#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 +#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 +#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB +#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB + +#if defined (STM32F4) +#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() +#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() +#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() +#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() +#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() +#else +#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG +#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT +#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT +#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT +#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG +#endif /* STM32F4 */ +/** + * @} + */ + + +/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose + * @{ + */ + +#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI +#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI + +#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback +#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) + +#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE +#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE +#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE +#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE +#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET +#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET +#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE +#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE +#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET +#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET +#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE +#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE +#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE +#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE +#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET +#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET +#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE +#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE +#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET +#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET +#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE +#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE +#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE +#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE +#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET +#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET +#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE +#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE +#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET +#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET +#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET +#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET +#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET +#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET +#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET +#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET +#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET +#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET +#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET +#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET +#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET +#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET +#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE +#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE +#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET +#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET +#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE +#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE +#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE +#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE +#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET +#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET +#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE +#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE +#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE +#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE +#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET +#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET +#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE +#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE +#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET +#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET +#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE +#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE +#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE +#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE +#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET +#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET +#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE +#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE +#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET +#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET +#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE +#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE +#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE +#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE +#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET +#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET +#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE +#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE +#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET +#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET +#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE +#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE +#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE +#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE +#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET +#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET +#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE +#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE +#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE +#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE +#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET +#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET +#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE +#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE +#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE +#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE +#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET +#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET +#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE +#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE +#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET +#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET +#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE +#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE +#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE +#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE +#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE +#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE +#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE +#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE +#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE +#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE +#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET +#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET +#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE +#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE +#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET +#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET +#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE +#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE +#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE +#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE +#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE +#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE +#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET +#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET +#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE +#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE +#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE +#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE +#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE +#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE +#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET +#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET +#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE +#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE +#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE +#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE +#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET +#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET +#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE +#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE +#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE +#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE +#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET +#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET +#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE +#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE +#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE +#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE +#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET +#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET +#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE +#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE +#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE +#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE +#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET +#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET +#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE +#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE +#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE +#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE +#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET +#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET +#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE +#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE +#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE +#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE +#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET +#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET +#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE +#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE +#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE +#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE +#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET +#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET +#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE +#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE +#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE +#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE +#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET +#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET +#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE +#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE +#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE +#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE +#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET +#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET +#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE +#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE +#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE +#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE +#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET +#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET +#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE +#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE +#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE +#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE +#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET +#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET +#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE +#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE +#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE +#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE +#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET +#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET +#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE +#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE +#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE +#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE +#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET +#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET +#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE +#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE +#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE +#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE +#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET +#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET +#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE +#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE +#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE +#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE +#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET +#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET +#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE +#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE +#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE +#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE +#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET +#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET +#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE +#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE +#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE +#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE +#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET +#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET +#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE +#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE +#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE +#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE +#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET +#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET + +#if defined(STM32WB) +#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE +#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET +#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET +#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED +#define QSPI_IRQHandler QUADSPI_IRQHandler +#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ + +#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE +#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE +#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE +#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE +#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET +#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET +#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE +#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE +#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE +#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE +#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET +#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET +#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE +#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE +#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE +#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE +#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET +#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET +#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE +#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE +#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE +#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE +#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET +#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET +#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE +#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE +#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE +#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE +#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET +#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET +#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE +#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE +#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE +#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE +#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET +#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET +#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE +#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE +#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE +#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE +#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET +#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET +#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE +#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE +#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE +#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE +#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE +#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE +#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE +#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE +#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE +#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE +#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET +#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET +#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE +#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE +#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE +#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE +#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET +#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET +#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE +#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE +#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE +#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE +#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET +#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET +#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE +#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE +#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET +#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET +#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE +#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE +#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET +#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET +#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE +#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE +#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET +#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET +#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE +#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE +#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET +#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET +#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE +#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE +#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET +#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET +#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE +#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE +#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE +#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE +#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET +#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET +#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE +#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE +#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE +#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE +#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET +#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET +#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE +#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE +#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE +#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE +#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET +#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET +#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE +#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE +#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE +#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE +#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET +#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET +#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE +#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE +#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE +#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE +#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET +#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET +#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE +#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE +#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE +#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE +#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET +#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET +#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE +#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE +#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE +#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE +#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET +#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET +#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE +#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE +#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE +#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE +#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET +#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET +#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE +#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE +#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE +#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE +#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET +#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET +#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE +#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE +#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE +#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE +#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET +#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET +#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE +#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE +#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET +#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET +#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE +#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE +#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE +#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE +#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET +#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET +#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE +#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE +#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE +#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE +#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET +#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET +#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE +#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE +#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE +#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE +#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET +#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET +#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE +#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE +#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE +#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE +#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET +#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET +#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET +#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE +#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE +#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET +#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE +#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE +#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE +#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE +#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET + +#if defined(STM32H7) +#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE +#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE + +#define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/ +#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/ + + +#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED +#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED +#endif + +#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE +#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE +#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE +#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE +#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET +#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET + +#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE +#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE +#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET +#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET +#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE +#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE +#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE +#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE +#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET +#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET +#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE +#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE +#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE +#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE +#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE +#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE +#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET +#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET +#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE +#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE + +#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET +#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE +#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE +#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE +#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE +#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE +#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE +#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE +#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE +#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE +#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE +#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE +#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE +#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE +#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET +#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET +#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE +#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE +#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE +#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE +#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE +#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET +#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET +#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE +#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE +#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE +#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE +#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET +#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET +#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE +#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE +#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE +#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE +#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET +#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET +#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE +#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE +#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE +#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE +#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE +#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE +#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE +#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE +#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE +#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE +#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE +#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE +#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE +#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE +#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE +#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE +#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE +#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE +#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE +#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET +#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET +#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE +#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE +#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE +#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE +#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET +#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET +#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE +#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE +#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE +#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE +#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET +#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET +#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE +#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE +#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE +#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE +#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET +#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET +#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE +#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE +#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE +#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE +#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET +#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE +#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE +#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE +#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE +#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE +#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE +#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET +#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET +#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE +#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE +#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE +#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE +#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET +#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE +#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE +#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED +#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED +#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE +#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE +#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE +#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE +#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE +#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE +#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE +#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET +#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET +#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE +#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE +#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE +#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE +#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET +#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET +#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE + +/* alias define maintained for legacy */ +#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET + +#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE +#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE +#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE +#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE +#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE +#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE +#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE +#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE +#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE +#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE +#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE +#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE +#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE +#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE +#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE +#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE +#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE +#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE + +#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET +#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET +#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET +#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET +#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET +#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET +#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET +#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET +#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET +#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET +#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET +#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET +#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET +#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET +#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET +#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET +#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET +#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET + +#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED +#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED +#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED +#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED +#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED +#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED +#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED +#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED +#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED +#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED +#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED +#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED +#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED +#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED +#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED +#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED +#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED +#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED +#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED +#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED +#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED +#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED +#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED +#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED +#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED +#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED +#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED +#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED +#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED +#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED +#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED +#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED +#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED +#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED +#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED +#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED +#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED +#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED +#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED +#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED +#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED +#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED +#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED +#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED +#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED +#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED +#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED +#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED +#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED +#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED +#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED +#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED +#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED +#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED +#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED +#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED +#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED +#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED +#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED +#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED +#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED +#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED +#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED +#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED +#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED +#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED +#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED +#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED +#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED +#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED +#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED +#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED +#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED +#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED +#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED +#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED +#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED +#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED +#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED +#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED +#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED +#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED +#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED +#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED +#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED +#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED +#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED +#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED +#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED +#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED +#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED +#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED +#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED +#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED +#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED +#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED +#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED +#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED +#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED +#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED +#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED +#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED +#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED +#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED +#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED +#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED +#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED +#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED +#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED +#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED +#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED +#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED +#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED +#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED + +#if defined(STM32L1) +#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#endif /* STM32L1 */ + +#if defined(STM32F4) +#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED +#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED +#define Sdmmc1ClockSelection SdioClockSelection +#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO +#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 +#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK +#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG +#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET +#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET +#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE +#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE +#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED +#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED +#define SdioClockSelection Sdmmc1ClockSelection +#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 +#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG +#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE +#endif + +#if defined(STM32F7) +#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 +#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK +#endif + +#if defined(STM32H7) +#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() + +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() +#endif + +#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG +#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG + +#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE + +#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE +#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE +#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK +#define IS_RCC_HCLK_DIV IS_RCC_PCLK +#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK + +#define RCC_IT_HSI14 RCC_IT_HSI14RDY + +#define RCC_IT_CSSLSE RCC_IT_LSECSS +#define RCC_IT_CSSHSE RCC_IT_CSS + +#define RCC_PLLMUL_3 RCC_PLL_MUL3 +#define RCC_PLLMUL_4 RCC_PLL_MUL4 +#define RCC_PLLMUL_6 RCC_PLL_MUL6 +#define RCC_PLLMUL_8 RCC_PLL_MUL8 +#define RCC_PLLMUL_12 RCC_PLL_MUL12 +#define RCC_PLLMUL_16 RCC_PLL_MUL16 +#define RCC_PLLMUL_24 RCC_PLL_MUL24 +#define RCC_PLLMUL_32 RCC_PLL_MUL32 +#define RCC_PLLMUL_48 RCC_PLL_MUL48 + +#define RCC_PLLDIV_2 RCC_PLL_DIV2 +#define RCC_PLLDIV_3 RCC_PLL_DIV3 +#define RCC_PLLDIV_4 RCC_PLL_DIV4 + +#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE +#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG +#define RCC_MCO_NODIV RCC_MCODIV_1 +#define RCC_MCO_DIV1 RCC_MCODIV_1 +#define RCC_MCO_DIV2 RCC_MCODIV_2 +#define RCC_MCO_DIV4 RCC_MCODIV_4 +#define RCC_MCO_DIV8 RCC_MCODIV_8 +#define RCC_MCO_DIV16 RCC_MCODIV_16 +#define RCC_MCO_DIV32 RCC_MCODIV_32 +#define RCC_MCO_DIV64 RCC_MCODIV_64 +#define RCC_MCO_DIV128 RCC_MCODIV_128 +#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK +#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI +#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE +#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK +#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI +#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 +#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 +#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE +#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 + +#if defined(STM32L4) +#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE +#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) +#else +#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK +#endif + +#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 +#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL +#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI +#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 +#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 +#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 + +#define HSION_BitNumber RCC_HSION_BIT_NUMBER +#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER +#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER +#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER +#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER +#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER +#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER +#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER +#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER +#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER +#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER +#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER +#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER +#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER +#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER +#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER +#define LSION_BitNumber RCC_LSION_BIT_NUMBER +#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER +#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER +#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER +#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER +#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER +#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER +#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER +#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER +#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER +#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS +#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS +#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS +#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS +#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE +#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE + +#define CR_HSION_BB RCC_CR_HSION_BB +#define CR_CSSON_BB RCC_CR_CSSON_BB +#define CR_PLLON_BB RCC_CR_PLLON_BB +#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB +#define CR_MSION_BB RCC_CR_MSION_BB +#define CSR_LSION_BB RCC_CSR_LSION_BB +#define CSR_LSEON_BB RCC_CSR_LSEON_BB +#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB +#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB +#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB +#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB +#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB +#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB +#define CR_HSEON_BB RCC_CR_HSEON_BB +#define CSR_RMVF_BB RCC_CSR_RMVF_BB +#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB +#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB + +#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE +#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE +#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE +#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE +#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE + +#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT + +#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN +#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF + +#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 +#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ +#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP +#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ +#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE +#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 + +#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE +#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED +#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET +#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET +#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE +#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED +#define DfsdmClockSelection Dfsdm1ClockSelection +#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 +#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK +#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG +#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE +#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 +#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 +#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 + +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 +#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 + +/** + * @} + */ + +/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose + * @{ + */ +#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) + +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) +#else +#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG +#endif +#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT +#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT + +#if defined (STM32F1) +#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() + +#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() + +#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() + +#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() + +#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() +#else +#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) +#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) +#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) +#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) +#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) +#endif /* STM32F1 */ + +#define IS_ALARM IS_RTC_ALARM +#define IS_ALARM_MASK IS_RTC_ALARM_MASK +#define IS_TAMPER IS_RTC_TAMPER +#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE +#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER +#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT +#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE +#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION +#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE +#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ +#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION +#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER +#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK +#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER + +#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE +#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE + +/** + * @} + */ + +/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose + * @{ + */ + +#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE +#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS + +#if defined(STM32F4) || defined(STM32F2) +#define SD_SDMMC_DISABLED SD_SDIO_DISABLED +#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY +#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED +#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION +#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND +#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT +#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED +#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE +#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE +#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE +#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL +#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT +#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT +#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG +#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG +#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT +#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT +#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS +#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT +#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND +/* alias CMSIS */ +#define SDMMC1_IRQn SDIO_IRQn +#define SDMMC1_IRQHandler SDIO_IRQHandler +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define SD_SDIO_DISABLED SD_SDMMC_DISABLED +#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY +#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED +#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION +#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND +#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT +#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED +#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE +#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE +#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE +#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE +#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT +#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT +#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG +#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG +#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT +#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT +#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS +#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT +#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND +/* alias CMSIS for compatibilities */ +#define SDIO_IRQn SDMMC1_IRQn +#define SDIO_IRQHandler SDMMC1_IRQHandler +#endif + +#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7) +#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef +#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef +#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef +#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef +#endif + +#if defined(STM32H7) || defined(STM32L5) +#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback +#endif +/** + * @} + */ + +/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT +#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT +#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE +#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE +#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE +#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE + +#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE +#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE + +#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE + +/** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 +#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 +#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START +#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH +#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR +#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE +#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE +#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_SPI_1LINE_TX SPI_1LINE_TX +#define __HAL_SPI_1LINE_RX SPI_1LINE_RX +#define __HAL_SPI_RESET_CRC SPI_RESET_CRC + +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION +#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION + +#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD + +#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE +#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT +#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT +#define __USART_ENABLE __HAL_USART_ENABLE +#define __USART_DISABLE __HAL_USART_DISABLE + +#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE +#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE + +/** + * @} + */ + +/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose + * @{ + */ +#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE + +#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE +#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE +#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE + +#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE +#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE +#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE + +#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE + +#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT + +#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT + +#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup +#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup + +#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo +#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE +#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE + +#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE +#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT + +#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE + +#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN +#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER +#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER +#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER +#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD +#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD +#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION +#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION +#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER +#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER +#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE +#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE + +#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT +#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT +#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG +#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER + +#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE +#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE +#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_LTDC_LAYER LTDC_LAYER +#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG +/** + * @} + */ + +/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose + * @{ + */ +#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE +#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE +#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE +#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE +#define SAI_STREOMODE SAI_STEREOMODE +#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY +#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL +#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL +#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL +#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL +#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL +#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE +#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 +#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE +/** + * @} + */ + +/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32H7) +#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow +#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT +#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA +#endif +/** + * @} + */ + +/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose + * @{ + */ +#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3) +#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT +#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA +#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart +#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT +#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA +#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop +#endif +/** + * @} + */ + +/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) +#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE +#endif /* STM32L4 || STM32F4 || STM32F7 */ +/** + * @} + */ + +/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32_HAL_LEGACY */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h new file mode 100644 index 0000000..209864d --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h @@ -0,0 +1,298 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal.h + * @author MCD Application Team + * @brief This file contains all the functions prototypes for the HAL + * module driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_H +#define __STM32F4xx_HAL_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_conf.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup HAL + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Constants HAL Exported Constants + * @{ + */ + +/** @defgroup HAL_TICK_FREQ Tick Frequency + * @{ + */ +typedef enum +{ + HAL_TICK_FREQ_10HZ = 100U, + HAL_TICK_FREQ_100HZ = 10U, + HAL_TICK_FREQ_1KHZ = 1U, + HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ +} HAL_TickFreqTypeDef; +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup HAL_Exported_Macros HAL Exported Macros + * @{ + */ + +/** @brief Freeze/Unfreeze Peripherals in Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP)) +#define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP)) +#define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP)) +#define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP)) +#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) +#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)) +#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)) +#define __HAL_DBGMCU_FREEZE_CAN1() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP)) +#define __HAL_DBGMCU_FREEZE_CAN2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM9() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM10() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM11() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP)) + +#define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM4() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM5() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM12() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM13() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP)) +#define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP)) +#define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP)) +#define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP)) +#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) +#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)) +#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)) +#define __HAL_DBGMCU_UNFREEZE_CAN1() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP)) +#define __HAL_DBGMCU_UNFREEZE_CAN2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM8() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM9() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM10() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM11() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP)) + +/** @brief Main Flash memory mapped at 0x00000000 + */ +#define __HAL_SYSCFG_REMAPMEMORY_FLASH() (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE)) + +/** @brief System Flash memory mapped at 0x00000000 + */ +#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\ + SYSCFG->MEMRMP |= SYSCFG_MEMRMP_MEM_MODE_0;\ + }while(0); + +/** @brief Embedded SRAM mapped at 0x00000000 + */ +#define __HAL_SYSCFG_REMAPMEMORY_SRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\ + SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_0 | SYSCFG_MEMRMP_MEM_MODE_1);\ + }while(0); + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) +/** @brief FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 + */ +#define __HAL_SYSCFG_REMAPMEMORY_FSMC() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\ + SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\ + }while(0); +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) +/** @brief FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 + */ +#define __HAL_SYSCFG_REMAPMEMORY_FMC() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\ + SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\ + }while(0); + +/** @brief FMC/SDRAM Bank 1 and 2 mapped at 0x00000000 + */ +#define __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\ + SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_2);\ + }while(0); +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F413xx) || defined(STM32F423xx) +/** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable + * @{ + */ +/** @brief SYSCFG Break Lockup lock + * Enables and locks the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8 input + * @note The selected configuration is locked and can be unlocked by system reset + */ +#define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \ + SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \ + }while(0) +/** + * @} + */ + +/** @defgroup PVD_Lock_Enable PVD Lock + * @{ + */ +/** @brief SYSCFG Break PVD lock + * Enables and locks the PVD connection with Timer1/8 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register + * @note The selected configuration is locked and can be unlocked by system reset + */ +#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \ + SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \ + }while(0) +/** + * @} + */ +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx || STM32F413xx || STM32F423xx */ +/** + * @} + */ + +/** @defgroup HAL_Private_Macros HAL Private Macros + * @{ + */ +#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ + ((FREQ) == HAL_TICK_FREQ_100HZ) || \ + ((FREQ) == HAL_TICK_FREQ_1KHZ)) +/** + * @} + */ + +/* Exported variables --------------------------------------------------------*/ + +/** @addtogroup HAL_Exported_Variables + * @{ + */ +extern __IO uint32_t uwTick; +extern uint32_t uwTickPrio; +extern HAL_TickFreqTypeDef uwTickFreq; +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup HAL_Exported_Functions + * @{ + */ +/** @addtogroup HAL_Exported_Functions_Group1 + * @{ + */ +/* Initialization and Configuration functions ******************************/ +HAL_StatusTypeDef HAL_Init(void); +HAL_StatusTypeDef HAL_DeInit(void); +void HAL_MspInit(void); +void HAL_MspDeInit(void); +HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions ************************************************/ +void HAL_IncTick(void); +void HAL_Delay(uint32_t Delay); +uint32_t HAL_GetTick(void); +uint32_t HAL_GetTickPrio(void); +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); +HAL_TickFreqTypeDef HAL_GetTickFreq(void); +void HAL_SuspendTick(void); +void HAL_ResumeTick(void); +uint32_t HAL_GetHalVersion(void); +uint32_t HAL_GetREVID(void); +uint32_t HAL_GetDEVID(void); +void HAL_DBGMCU_EnableDBGSleepMode(void); +void HAL_DBGMCU_DisableDBGSleepMode(void); +void HAL_DBGMCU_EnableDBGStopMode(void); +void HAL_DBGMCU_DisableDBGStopMode(void); +void HAL_DBGMCU_EnableDBGStandbyMode(void); +void HAL_DBGMCU_DisableDBGStandbyMode(void); +void HAL_EnableCompensationCell(void); +void HAL_DisableCompensationCell(void); +uint32_t HAL_GetUIDw0(void); +uint32_t HAL_GetUIDw1(void); +uint32_t HAL_GetUIDw2(void); +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) +void HAL_EnableMemorySwappingBank(void); +void HAL_DisableMemorySwappingBank(void); +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup HAL_Private_Variables HAL Private Variables + * @{ + */ +/** + * @} + */ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup HAL_Private_Constants HAL Private Constants + * @{ + */ +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h new file mode 100644 index 0000000..95218cf --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h @@ -0,0 +1,410 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_cortex.h + * @author MCD Application Team + * @brief Header file of CORTEX HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_CORTEX_H +#define __STM32F4xx_HAL_CORTEX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup CORTEX + * @{ + */ +/* Exported types ------------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Types Cortex Exported Types + * @{ + */ + +#if (__MPU_PRESENT == 1U) +/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition + * @brief MPU Region initialization structure + * @{ + */ +typedef struct +{ + uint8_t Enable; /*!< Specifies the status of the region. + This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ + uint8_t Number; /*!< Specifies the number of the region to protect. + This parameter can be a value of @ref CORTEX_MPU_Region_Number */ + uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ + uint8_t Size; /*!< Specifies the size of the region to protect. + This parameter can be a value of @ref CORTEX_MPU_Region_Size */ + uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + uint8_t TypeExtField; /*!< Specifies the TEX field level. + This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ + uint8_t AccessPermission; /*!< Specifies the region access permission type. + This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ + uint8_t DisableExec; /*!< Specifies the instruction access status. + This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ + uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. + This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ + uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. + This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ + uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. + This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ +}MPU_Region_InitTypeDef; +/** + * @} + */ +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants + * @{ + */ + +/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group + * @{ + */ +#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority + 4 bits for subpriority */ +#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority + 3 bits for subpriority */ +#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority + 2 bits for subpriority */ +#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority + 1 bits for subpriority */ +#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority + 0 bits for subpriority */ +/** + * @} + */ + +/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source + * @{ + */ +#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U +#define SYSTICK_CLKSOURCE_HCLK 0x00000004U + +/** + * @} + */ + +#if (__MPU_PRESENT == 1) +/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control + * @{ + */ +#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U +#define MPU_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk +#define MPU_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk +#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) + +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable + * @{ + */ +#define MPU_REGION_ENABLE ((uint8_t)0x01) +#define MPU_REGION_DISABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access + * @{ + */ +#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) +#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable + * @{ + */ +#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) +#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable + * @{ + */ +#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) +#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable + * @{ + */ +#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) +#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels + * @{ + */ +#define MPU_TEX_LEVEL0 ((uint8_t)0x00) +#define MPU_TEX_LEVEL1 ((uint8_t)0x01) +#define MPU_TEX_LEVEL2 ((uint8_t)0x02) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size + * @{ + */ +#define MPU_REGION_SIZE_32B ((uint8_t)0x04) +#define MPU_REGION_SIZE_64B ((uint8_t)0x05) +#define MPU_REGION_SIZE_128B ((uint8_t)0x06) +#define MPU_REGION_SIZE_256B ((uint8_t)0x07) +#define MPU_REGION_SIZE_512B ((uint8_t)0x08) +#define MPU_REGION_SIZE_1KB ((uint8_t)0x09) +#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) +#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) +#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) +#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) +#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) +#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) +#define MPU_REGION_SIZE_128KB ((uint8_t)0x10) +#define MPU_REGION_SIZE_256KB ((uint8_t)0x11) +#define MPU_REGION_SIZE_512KB ((uint8_t)0x12) +#define MPU_REGION_SIZE_1MB ((uint8_t)0x13) +#define MPU_REGION_SIZE_2MB ((uint8_t)0x14) +#define MPU_REGION_SIZE_4MB ((uint8_t)0x15) +#define MPU_REGION_SIZE_8MB ((uint8_t)0x16) +#define MPU_REGION_SIZE_16MB ((uint8_t)0x17) +#define MPU_REGION_SIZE_32MB ((uint8_t)0x18) +#define MPU_REGION_SIZE_64MB ((uint8_t)0x19) +#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) +#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) +#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) +#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) +#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) +#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes + * @{ + */ +#define MPU_REGION_NO_ACCESS ((uint8_t)0x00) +#define MPU_REGION_PRIV_RW ((uint8_t)0x01) +#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) +#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) +#define MPU_REGION_PRIV_RO ((uint8_t)0x05) +#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number + * @{ + */ +#define MPU_REGION_NUMBER0 ((uint8_t)0x00) +#define MPU_REGION_NUMBER1 ((uint8_t)0x01) +#define MPU_REGION_NUMBER2 ((uint8_t)0x02) +#define MPU_REGION_NUMBER3 ((uint8_t)0x03) +#define MPU_REGION_NUMBER4 ((uint8_t)0x04) +#define MPU_REGION_NUMBER5 ((uint8_t)0x05) +#define MPU_REGION_NUMBER6 ((uint8_t)0x06) +#define MPU_REGION_NUMBER7 ((uint8_t)0x07) +/** + * @} + */ +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + + +/* Exported Macros -----------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CORTEX_Exported_Functions + * @{ + */ + +/** @addtogroup CORTEX_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); +void HAL_NVIC_SystemReset(void); +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); +/** + * @} + */ + +/** @addtogroup CORTEX_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions ***********************************************/ +uint32_t HAL_NVIC_GetPriorityGrouping(void); +void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); +uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); +void HAL_SYSTICK_IRQHandler(void); +void HAL_SYSTICK_Callback(void); + +#if (__MPU_PRESENT == 1U) +void HAL_MPU_Enable(uint32_t MPU_Control); +void HAL_MPU_Disable(void); +void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); +#endif /* __MPU_PRESENT */ +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup CORTEX_Private_Macros CORTEX Private Macros + * @{ + */ +#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ + ((GROUP) == NVIC_PRIORITYGROUP_1) || \ + ((GROUP) == NVIC_PRIORITYGROUP_2) || \ + ((GROUP) == NVIC_PRIORITYGROUP_3) || \ + ((GROUP) == NVIC_PRIORITYGROUP_4)) + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) + +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) + +#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U) + +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ + ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) + +#if (__MPU_PRESENT == 1U) +#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ + ((STATE) == MPU_REGION_DISABLE)) + +#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ + ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) + +#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ + ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) + +#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ + ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) + +#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ + ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) + +#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ + ((TYPE) == MPU_TEX_LEVEL1) || \ + ((TYPE) == MPU_TEX_LEVEL2)) + +#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ + ((TYPE) == MPU_REGION_PRIV_RW) || \ + ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ + ((TYPE) == MPU_REGION_FULL_ACCESS) || \ + ((TYPE) == MPU_REGION_PRIV_RO) || \ + ((TYPE) == MPU_REGION_PRIV_RO_URO)) + +#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ + ((NUMBER) == MPU_REGION_NUMBER1) || \ + ((NUMBER) == MPU_REGION_NUMBER2) || \ + ((NUMBER) == MPU_REGION_NUMBER3) || \ + ((NUMBER) == MPU_REGION_NUMBER4) || \ + ((NUMBER) == MPU_REGION_NUMBER5) || \ + ((NUMBER) == MPU_REGION_NUMBER6) || \ + ((NUMBER) == MPU_REGION_NUMBER7)) + +#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ + ((SIZE) == MPU_REGION_SIZE_64B) || \ + ((SIZE) == MPU_REGION_SIZE_128B) || \ + ((SIZE) == MPU_REGION_SIZE_256B) || \ + ((SIZE) == MPU_REGION_SIZE_512B) || \ + ((SIZE) == MPU_REGION_SIZE_1KB) || \ + ((SIZE) == MPU_REGION_SIZE_2KB) || \ + ((SIZE) == MPU_REGION_SIZE_4KB) || \ + ((SIZE) == MPU_REGION_SIZE_8KB) || \ + ((SIZE) == MPU_REGION_SIZE_16KB) || \ + ((SIZE) == MPU_REGION_SIZE_32KB) || \ + ((SIZE) == MPU_REGION_SIZE_64KB) || \ + ((SIZE) == MPU_REGION_SIZE_128KB) || \ + ((SIZE) == MPU_REGION_SIZE_256KB) || \ + ((SIZE) == MPU_REGION_SIZE_512KB) || \ + ((SIZE) == MPU_REGION_SIZE_1MB) || \ + ((SIZE) == MPU_REGION_SIZE_2MB) || \ + ((SIZE) == MPU_REGION_SIZE_4MB) || \ + ((SIZE) == MPU_REGION_SIZE_8MB) || \ + ((SIZE) == MPU_REGION_SIZE_16MB) || \ + ((SIZE) == MPU_REGION_SIZE_32MB) || \ + ((SIZE) == MPU_REGION_SIZE_64MB) || \ + ((SIZE) == MPU_REGION_SIZE_128MB) || \ + ((SIZE) == MPU_REGION_SIZE_256MB) || \ + ((SIZE) == MPU_REGION_SIZE_512MB) || \ + ((SIZE) == MPU_REGION_SIZE_1GB) || \ + ((SIZE) == MPU_REGION_SIZE_2GB) || \ + ((SIZE) == MPU_REGION_SIZE_4GB)) + +#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_CORTEX_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h new file mode 100644 index 0000000..e32e362 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h @@ -0,0 +1,197 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_def.h + * @author MCD Application Team + * @brief This file contains HAL common defines, enumeration, macros and + * structures definitions. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_DEF +#define __STM32F4xx_HAL_DEF + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" +#include "Legacy/stm32_hal_legacy.h" +#include + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief HAL Status structures definition + */ +typedef enum +{ + HAL_OK = 0x00U, + HAL_ERROR = 0x01U, + HAL_BUSY = 0x02U, + HAL_TIMEOUT = 0x03U +} HAL_StatusTypeDef; + +/** + * @brief HAL Lock structures definition + */ +typedef enum +{ + HAL_UNLOCKED = 0x00U, + HAL_LOCKED = 0x01U +} HAL_LockTypeDef; + +/* Exported macro ------------------------------------------------------------*/ + +#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ + +#define HAL_MAX_DELAY 0xFFFFFFFFU + +#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT)) +#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) + +#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ + do{ \ + (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ + (__DMA_HANDLE__).Parent = (__HANDLE__); \ + } while(0U) + +/** @brief Reset the Handle's State field. + * @param __HANDLE__ specifies the Peripheral Handle. + * @note This macro can be used for the following purpose: + * - When the Handle is declared as local variable; before passing it as parameter + * to HAL_PPP_Init() for the first time, it is mandatory to use this macro + * to set to 0 the Handle's "State" field. + * Otherwise, "State" field may have any random value and the first time the function + * HAL_PPP_Init() is called, the low level hardware initialization will be missed + * (i.e. HAL_PPP_MspInit() will not be executed). + * - When there is a need to reconfigure the low level hardware: instead of calling + * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). + * In this later function, when the Handle's "State" field is set to 0, it will execute the function + * HAL_PPP_MspInit() which will reconfigure the low level hardware. + * @retval None + */ +#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U) + +#if (USE_RTOS == 1U) + /* Reserved for future use */ + #error "USE_RTOS should be 0 in the current HAL release" +#else + #define __HAL_LOCK(__HANDLE__) \ + do{ \ + if((__HANDLE__)->Lock == HAL_LOCKED) \ + { \ + return HAL_BUSY; \ + } \ + else \ + { \ + (__HANDLE__)->Lock = HAL_LOCKED; \ + } \ + }while (0U) + + #define __HAL_UNLOCK(__HANDLE__) \ + do{ \ + (__HANDLE__)->Lock = HAL_UNLOCKED; \ + }while (0U) +#endif /* USE_RTOS */ + +#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ + #ifndef __weak + #define __weak __attribute__((weak)) + #endif /* __weak */ + #ifndef __packed + #define __packed __attribute__((__packed__)) + #endif /* __packed */ +#endif /* __GNUC__ */ + + +/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ +#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ + #ifndef __ALIGN_END +#define __ALIGN_END __attribute__ ((aligned (4))) + #endif /* __ALIGN_END */ + #ifndef __ALIGN_BEGIN + #define __ALIGN_BEGIN + #endif /* __ALIGN_BEGIN */ +#else + #ifndef __ALIGN_END + #define __ALIGN_END + #endif /* __ALIGN_END */ + #ifndef __ALIGN_BEGIN + #if defined (__CC_ARM) /* ARM Compiler */ +#define __ALIGN_BEGIN __align(4) + #elif defined (__ICCARM__) /* IAR Compiler */ + #define __ALIGN_BEGIN + #endif /* __CC_ARM */ + #endif /* __ALIGN_BEGIN */ +#endif /* __GNUC__ */ + + +/** + * @brief __RAM_FUNC definition + */ +#if defined ( __CC_ARM ) +/* ARM Compiler + ------------ + RAM functions are defined using the toolchain options. + Functions that are executed in RAM should reside in a separate source module. + Using the 'Options for File' dialog you can simply change the 'Code / Const' + area of a module to a memory space in physical RAM. + Available memory areas are declared in the 'Target' tab of the 'Options for Target' + dialog. +*/ +#define __RAM_FUNC + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- + RAM functions are defined using a specific toolchain keyword "__ramfunc". +*/ +#define __RAM_FUNC __ramfunc + +#elif defined ( __GNUC__ ) +/* GNU Compiler + ------------ + RAM functions are defined using a specific toolchain attribute + "__attribute__((section(".RamFunc")))". +*/ +#define __RAM_FUNC __attribute__((section(".RamFunc"))) + +#endif + +/** + * @brief __NOINLINE definition + */ +#if defined ( __CC_ARM ) || defined ( __GNUC__ ) +/* ARM & GNUCompiler + ---------------- +*/ +#define __NOINLINE __attribute__ ( (noinline) ) + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- +*/ +#define __NOINLINE _Pragma("optimize = no_inline") + +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* ___STM32F4xx_HAL_DEF */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h new file mode 100644 index 0000000..90dd292 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h @@ -0,0 +1,804 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_dma.h + * @author MCD Application Team + * @brief Header file of DMA HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_DMA_H +#define __STM32F4xx_HAL_DMA_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Types DMA Exported Types + * @brief DMA Exported Types + * @{ + */ + +/** + * @brief DMA Configuration Structure definition + */ +typedef struct +{ + uint32_t Channel; /*!< Specifies the channel used for the specified stream. + This parameter can be a value of @ref DMA_Channel_selection */ + + uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, + from memory to memory or from peripheral to memory. + This parameter can be a value of @ref DMA_Data_transfer_direction */ + + uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. + This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ + + uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. + This parameter can be a value of @ref DMA_Memory_incremented_mode */ + + uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_Peripheral_data_size */ + + uint32_t MemDataAlignment; /*!< Specifies the Memory data width. + This parameter can be a value of @ref DMA_Memory_data_size */ + + uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx. + This parameter can be a value of @ref DMA_mode + @note The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Stream */ + + uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx. + This parameter can be a value of @ref DMA_Priority_level */ + + uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream. + This parameter can be a value of @ref DMA_FIFO_direct_mode + @note The Direct mode (FIFO mode disabled) cannot be used if the + memory-to-memory data transfer is configured on the selected stream */ + + uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. + This parameter can be a value of @ref DMA_FIFO_threshold_level */ + + uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. + It specifies the amount of data to be transferred in a single non interruptible + transaction. + This parameter can be a value of @ref DMA_Memory_burst + @note The burst mode is possible only if the address Increment mode is enabled. */ + + uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. + It specifies the amount of data to be transferred in a single non interruptible + transaction. + This parameter can be a value of @ref DMA_Peripheral_burst + @note The burst mode is possible only if the address Increment mode is enabled. */ +}DMA_InitTypeDef; + + +/** + * @brief HAL DMA State structures definition + */ +typedef enum +{ + HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ + HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ + HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ + HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ + HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */ + HAL_DMA_STATE_ABORT = 0x05U, /*!< DMA Abort state */ +}HAL_DMA_StateTypeDef; + +/** + * @brief HAL DMA Error Code structure definition + */ +typedef enum +{ + HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ + HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ +}HAL_DMA_LevelCompleteTypeDef; + +/** + * @brief HAL DMA Error Code structure definition + */ +typedef enum +{ + HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ + HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */ + HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */ + HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */ + HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */ + HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */ + HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */ +}HAL_DMA_CallbackIDTypeDef; + +/** + * @brief DMA handle Structure definition + */ +typedef struct __DMA_HandleTypeDef +{ + DMA_Stream_TypeDef *Instance; /*!< Register base address */ + + DMA_InitTypeDef Init; /*!< DMA communication parameters */ + + HAL_LockTypeDef Lock; /*!< DMA locking object */ + + __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ + + void *Parent; /*!< Parent object state */ + + void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ + + void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ + + void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */ + + void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */ + + void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ + + void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */ + + __IO uint32_t ErrorCode; /*!< DMA Error code */ + + uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */ + + uint32_t StreamIndex; /*!< DMA Stream Index */ + +}DMA_HandleTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Constants DMA Exported Constants + * @brief DMA Exported constants + * @{ + */ + +/** @defgroup DMA_Error_Code DMA Error Code + * @brief DMA Error Code + * @{ + */ +#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ +#define HAL_DMA_ERROR_FE 0x00000002U /*!< FIFO error */ +#define HAL_DMA_ERROR_DME 0x00000004U /*!< Direct Mode error */ +#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ +#define HAL_DMA_ERROR_PARAM 0x00000040U /*!< Parameter error */ +#define HAL_DMA_ERROR_NO_XFER 0x00000080U /*!< Abort requested with no Xfer ongoing */ +#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ +/** + * @} + */ + +/** @defgroup DMA_Channel_selection DMA Channel selection + * @brief DMA channel selection + * @{ + */ +#define DMA_CHANNEL_0 0x00000000U /*!< DMA Channel 0 */ +#define DMA_CHANNEL_1 0x02000000U /*!< DMA Channel 1 */ +#define DMA_CHANNEL_2 0x04000000U /*!< DMA Channel 2 */ +#define DMA_CHANNEL_3 0x06000000U /*!< DMA Channel 3 */ +#define DMA_CHANNEL_4 0x08000000U /*!< DMA Channel 4 */ +#define DMA_CHANNEL_5 0x0A000000U /*!< DMA Channel 5 */ +#define DMA_CHANNEL_6 0x0C000000U /*!< DMA Channel 6 */ +#define DMA_CHANNEL_7 0x0E000000U /*!< DMA Channel 7 */ +#if defined (DMA_SxCR_CHSEL_3) +#define DMA_CHANNEL_8 0x10000000U /*!< DMA Channel 8 */ +#define DMA_CHANNEL_9 0x12000000U /*!< DMA Channel 9 */ +#define DMA_CHANNEL_10 0x14000000U /*!< DMA Channel 10 */ +#define DMA_CHANNEL_11 0x16000000U /*!< DMA Channel 11 */ +#define DMA_CHANNEL_12 0x18000000U /*!< DMA Channel 12 */ +#define DMA_CHANNEL_13 0x1A000000U /*!< DMA Channel 13 */ +#define DMA_CHANNEL_14 0x1C000000U /*!< DMA Channel 14 */ +#define DMA_CHANNEL_15 0x1E000000U /*!< DMA Channel 15 */ +#endif /* DMA_SxCR_CHSEL_3 */ +/** + * @} + */ + +/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction + * @brief DMA data transfer direction + * @{ + */ +#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ +#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */ +#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */ +/** + * @} + */ + +/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode + * @brief DMA peripheral incremented mode + * @{ + */ +#define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */ +#define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode disable */ +/** + * @} + */ + +/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode + * @brief DMA memory incremented mode + * @{ + */ +#define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */ +#define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode disable */ +/** + * @} + */ + +/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size + * @brief DMA peripheral data size + * @{ + */ +#define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */ +#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ +#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */ +/** + * @} + */ + +/** @defgroup DMA_Memory_data_size DMA Memory data size + * @brief DMA memory data size + * @{ + */ +#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */ +#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ +#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */ +/** + * @} + */ + +/** @defgroup DMA_mode DMA mode + * @brief DMA mode + * @{ + */ +#define DMA_NORMAL 0x00000000U /*!< Normal mode */ +#define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */ +#define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */ +/** + * @} + */ + +/** @defgroup DMA_Priority_level DMA Priority level + * @brief DMA priority levels + * @{ + */ +#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level: Low */ +#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */ +#define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */ +#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */ +/** + * @} + */ + +/** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode + * @brief DMA FIFO direct mode + * @{ + */ +#define DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ +#define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */ +/** + * @} + */ + +/** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level + * @brief DMA FIFO level + * @{ + */ +#define DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00000000U /*!< FIFO threshold 1 quart full configuration */ +#define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */ +#define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */ +#define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */ +/** + * @} + */ + +/** @defgroup DMA_Memory_burst DMA Memory burst + * @brief DMA memory burst + * @{ + */ +#define DMA_MBURST_SINGLE 0x00000000U +#define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0) +#define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1) +#define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST) +/** + * @} + */ + +/** @defgroup DMA_Peripheral_burst DMA Peripheral burst + * @brief DMA peripheral burst + * @{ + */ +#define DMA_PBURST_SINGLE 0x00000000U +#define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0) +#define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1) +#define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST) +/** + * @} + */ + +/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions + * @brief DMA interrupts definition + * @{ + */ +#define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE) +#define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE) +#define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE) +#define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE) +#define DMA_IT_FE 0x00000080U +/** + * @} + */ + +/** @defgroup DMA_flag_definitions DMA flag definitions + * @brief DMA flag definitions + * @{ + */ +#define DMA_FLAG_FEIF0_4 0x00000001U +#define DMA_FLAG_DMEIF0_4 0x00000004U +#define DMA_FLAG_TEIF0_4 0x00000008U +#define DMA_FLAG_HTIF0_4 0x00000010U +#define DMA_FLAG_TCIF0_4 0x00000020U +#define DMA_FLAG_FEIF1_5 0x00000040U +#define DMA_FLAG_DMEIF1_5 0x00000100U +#define DMA_FLAG_TEIF1_5 0x00000200U +#define DMA_FLAG_HTIF1_5 0x00000400U +#define DMA_FLAG_TCIF1_5 0x00000800U +#define DMA_FLAG_FEIF2_6 0x00010000U +#define DMA_FLAG_DMEIF2_6 0x00040000U +#define DMA_FLAG_TEIF2_6 0x00080000U +#define DMA_FLAG_HTIF2_6 0x00100000U +#define DMA_FLAG_TCIF2_6 0x00200000U +#define DMA_FLAG_FEIF3_7 0x00400000U +#define DMA_FLAG_DMEIF3_7 0x01000000U +#define DMA_FLAG_TEIF3_7 0x02000000U +#define DMA_FLAG_HTIF3_7 0x04000000U +#define DMA_FLAG_TCIF3_7 0x08000000U +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @brief Reset DMA handle state + * @param __HANDLE__ specifies the DMA handle. + * @retval None + */ +#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) + +/** + * @brief Return the current DMA Stream FIFO filled level. + * @param __HANDLE__ DMA handle + * @retval The FIFO filling state. + * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full + * and not empty. + * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full. + * - DMA_FIFOStatus_HalfFull: if more than 1 half-full. + * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full. + * - DMA_FIFOStatus_Empty: when FIFO is empty + * - DMA_FIFOStatus_Full: when FIFO is full + */ +#define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS))) + +/** + * @brief Enable the specified DMA Stream. + * @param __HANDLE__ DMA handle + * @retval None + */ +#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN) + +/** + * @brief Disable the specified DMA Stream. + * @param __HANDLE__ DMA handle + * @retval None + */ +#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN) + +/* Interrupt & Flag management */ + +/** + * @brief Return the current DMA Stream transfer complete flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer complete flag index. + */ +#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\ + DMA_FLAG_TCIF3_7) + +/** + * @brief Return the current DMA Stream half transfer complete flag. + * @param __HANDLE__ DMA handle + * @retval The specified half transfer complete flag index. + */ +#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\ + DMA_FLAG_HTIF3_7) + +/** + * @brief Return the current DMA Stream transfer error flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\ + DMA_FLAG_TEIF3_7) + +/** + * @brief Return the current DMA Stream FIFO error flag. + * @param __HANDLE__ DMA handle + * @retval The specified FIFO error flag index. + */ +#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\ + DMA_FLAG_FEIF3_7) + +/** + * @brief Return the current DMA Stream direct mode error flag. + * @param __HANDLE__ DMA handle + * @retval The specified direct mode error flag index. + */ +#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\ + DMA_FLAG_DMEIF3_7) + +/** + * @brief Get the DMA Stream pending flags. + * @param __HANDLE__ DMA handle + * @param __FLAG__ Get the specified flag. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCIFx: Transfer complete flag. + * @arg DMA_FLAG_HTIFx: Half transfer complete flag. + * @arg DMA_FLAG_TEIFx: Transfer error flag. + * @arg DMA_FLAG_DMEIFx: Direct mode error flag. + * @arg DMA_FLAG_FEIFx: FIFO error flag. + * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. + * @retval The state of FLAG (SET or RESET). + */ +#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ +(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__))) + +/** + * @brief Clear the DMA Stream pending flags. + * @param __HANDLE__ DMA handle + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCIFx: Transfer complete flag. + * @arg DMA_FLAG_HTIFx: Half transfer complete flag. + * @arg DMA_FLAG_TEIFx: Transfer error flag. + * @arg DMA_FLAG_DMEIFx: Direct mode error flag. + * @arg DMA_FLAG_FEIFx: FIFO error flag. + * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. + * @retval None + */ +#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ +(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__))) + +/** + * @brief Enable the specified DMA Stream interrupts. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask. + * @arg DMA_IT_HT: Half transfer complete interrupt mask. + * @arg DMA_IT_TE: Transfer error interrupt mask. + * @arg DMA_IT_FE: FIFO error interrupt mask. + * @arg DMA_IT_DME: Direct mode error interrupt. + * @retval None + */ +#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ +((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__))) + +/** + * @brief Disable the specified DMA Stream interrupts. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask. + * @arg DMA_IT_HT: Half transfer complete interrupt mask. + * @arg DMA_IT_TE: Transfer error interrupt mask. + * @arg DMA_IT_FE: FIFO error interrupt mask. + * @arg DMA_IT_DME: Direct mode error interrupt. + * @retval None + */ +#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ +((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__))) + +/** + * @brief Check whether the specified DMA Stream interrupt is enabled or disabled. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt source to check. + * This parameter can be one of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask. + * @arg DMA_IT_HT: Half transfer complete interrupt mask. + * @arg DMA_IT_TE: Transfer error interrupt mask. + * @arg DMA_IT_FE: FIFO error interrupt mask. + * @arg DMA_IT_DME: Direct mode error interrupt. + * @retval The state of DMA_IT. + */ +#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ + ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \ + ((__HANDLE__)->Instance->FCR & (__INTERRUPT__))) + +/** + * @brief Writes the number of data units to be transferred on the DMA Stream. + * @param __HANDLE__ DMA handle + * @param __COUNTER__ Number of data units to be transferred (from 0 to 65535) + * Number of data items depends only on the Peripheral data format. + * + * @note If Peripheral data format is Bytes: number of data units is equal + * to total number of bytes to be transferred. + * + * @note If Peripheral data format is Half-Word: number of data units is + * equal to total number of bytes to be transferred / 2. + * + * @note If Peripheral data format is Word: number of data units is equal + * to total number of bytes to be transferred / 4. + * + * @retval The number of remaining data units in the current DMAy Streamx transfer. + */ +#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__)) + +/** + * @brief Returns the number of remaining data units in the current DMAy Streamx transfer. + * @param __HANDLE__ DMA handle + * + * @retval The number of remaining data units in the current DMA Stream transfer. + */ +#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR) + + +/* Include DMA HAL Extension module */ +#include "stm32f4xx_hal_dma_ex.h" + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Functions DMA Exported Functions + * @brief DMA Exported functions + * @{ + */ + +/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * @{ + */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group2 I/O operation functions + * @brief I/O operation functions + * @{ + */ +HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)); +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); + +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions + * @brief Peripheral State functions + * @{ + */ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); +/** + * @} + */ +/** + * @} + */ +/* Private Constants -------------------------------------------------------------*/ +/** @defgroup DMA_Private_Constants DMA Private Constants + * @brief DMA private defines and constants + * @{ + */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DMA_Private_Macros DMA Private Macros + * @brief DMA private macros + * @{ + */ +#if defined (DMA_SxCR_CHSEL_3) +#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \ + ((CHANNEL) == DMA_CHANNEL_1) || \ + ((CHANNEL) == DMA_CHANNEL_2) || \ + ((CHANNEL) == DMA_CHANNEL_3) || \ + ((CHANNEL) == DMA_CHANNEL_4) || \ + ((CHANNEL) == DMA_CHANNEL_5) || \ + ((CHANNEL) == DMA_CHANNEL_6) || \ + ((CHANNEL) == DMA_CHANNEL_7) || \ + ((CHANNEL) == DMA_CHANNEL_8) || \ + ((CHANNEL) == DMA_CHANNEL_9) || \ + ((CHANNEL) == DMA_CHANNEL_10)|| \ + ((CHANNEL) == DMA_CHANNEL_11)|| \ + ((CHANNEL) == DMA_CHANNEL_12)|| \ + ((CHANNEL) == DMA_CHANNEL_13)|| \ + ((CHANNEL) == DMA_CHANNEL_14)|| \ + ((CHANNEL) == DMA_CHANNEL_15)) +#else +#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \ + ((CHANNEL) == DMA_CHANNEL_1) || \ + ((CHANNEL) == DMA_CHANNEL_2) || \ + ((CHANNEL) == DMA_CHANNEL_3) || \ + ((CHANNEL) == DMA_CHANNEL_4) || \ + ((CHANNEL) == DMA_CHANNEL_5) || \ + ((CHANNEL) == DMA_CHANNEL_6) || \ + ((CHANNEL) == DMA_CHANNEL_7)) +#endif /* DMA_SxCR_CHSEL_3 */ + +#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ + ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ + ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) + +#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U)) + +#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ + ((STATE) == DMA_PINC_DISABLE)) + +#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ + ((STATE) == DMA_MINC_DISABLE)) + +#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ + ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_PDATAALIGN_WORD)) + +#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ + ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_MDATAALIGN_WORD )) + +#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ + ((MODE) == DMA_CIRCULAR) || \ + ((MODE) == DMA_PFCTRL)) + +#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ + ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ + ((PRIORITY) == DMA_PRIORITY_HIGH) || \ + ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) + +#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \ + ((STATE) == DMA_FIFOMODE_ENABLE)) + +#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \ + ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \ + ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \ + ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL)) + +#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \ + ((BURST) == DMA_MBURST_INC4) || \ + ((BURST) == DMA_MBURST_INC8) || \ + ((BURST) == DMA_MBURST_INC16)) + +#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \ + ((BURST) == DMA_PBURST_INC4) || \ + ((BURST) == DMA_PBURST_INC8) || \ + ((BURST) == DMA_PBURST_INC16)) +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup DMA_Private_Functions DMA Private Functions + * @brief DMA private functions + * @{ + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_DMA_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h new file mode 100644 index 0000000..2e60aff --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h @@ -0,0 +1,104 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_dma_ex.h + * @author MCD Application Team + * @brief Header file of DMA HAL extension module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_DMA_EX_H +#define __STM32F4xx_HAL_DMA_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup DMAEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup DMAEx_Exported_Types DMAEx Exported Types + * @brief DMAEx Exported types + * @{ + */ + +/** + * @brief HAL DMA Memory definition + */ +typedef enum +{ + MEMORY0 = 0x00U, /*!< Memory 0 */ + MEMORY1 = 0x01U /*!< Memory 1 */ +}HAL_DMA_MemoryTypeDef; + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions + * @brief DMAEx Exported functions + * @{ + */ + +/** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions + * @brief Extended features functions + * @{ + */ + +/* IO operation functions *******************************************************/ +HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory); + +/** + * @} + */ +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup DMAEx_Private_Functions DMAEx Private Functions + * @brief DMAEx Private functions + * @{ + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F4xx_HAL_DMA_EX_H*/ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h new file mode 100644 index 0000000..ff74222 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h @@ -0,0 +1,368 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_exti.h + * @author MCD Application Team + * @brief Header file of EXTI HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32f4xx_HAL_EXTI_H +#define STM32f4xx_HAL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup EXTI EXTI + * @brief EXTI HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup EXTI_Exported_Types EXTI Exported Types + * @{ + */ +typedef enum +{ + HAL_EXTI_COMMON_CB_ID = 0x00U +} EXTI_CallbackIDTypeDef; + +/** + * @brief EXTI Handle structure definition + */ +typedef struct +{ + uint32_t Line; /*!< Exti line number */ + void (* PendingCallback)(void); /*!< Exti pending callback */ +} EXTI_HandleTypeDef; + +/** + * @brief EXTI Configuration structure definition + */ +typedef struct +{ + uint32_t Line; /*!< The Exti line to be configured. This parameter + can be a value of @ref EXTI_Line */ + uint32_t Mode; /*!< The Exit Mode to be configured for a core. + This parameter can be a combination of @ref EXTI_Mode */ + uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter + can be a value of @ref EXTI_Trigger */ + uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured. + This parameter is only possible for line 0 to 15. It + can be a value of @ref EXTI_GPIOSel */ +} EXTI_ConfigTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_Line EXTI Line + * @{ + */ +#define EXTI_LINE_0 (EXTI_GPIO | 0x00u) /*!< External interrupt line 0 */ +#define EXTI_LINE_1 (EXTI_GPIO | 0x01u) /*!< External interrupt line 1 */ +#define EXTI_LINE_2 (EXTI_GPIO | 0x02u) /*!< External interrupt line 2 */ +#define EXTI_LINE_3 (EXTI_GPIO | 0x03u) /*!< External interrupt line 3 */ +#define EXTI_LINE_4 (EXTI_GPIO | 0x04u) /*!< External interrupt line 4 */ +#define EXTI_LINE_5 (EXTI_GPIO | 0x05u) /*!< External interrupt line 5 */ +#define EXTI_LINE_6 (EXTI_GPIO | 0x06u) /*!< External interrupt line 6 */ +#define EXTI_LINE_7 (EXTI_GPIO | 0x07u) /*!< External interrupt line 7 */ +#define EXTI_LINE_8 (EXTI_GPIO | 0x08u) /*!< External interrupt line 8 */ +#define EXTI_LINE_9 (EXTI_GPIO | 0x09u) /*!< External interrupt line 9 */ +#define EXTI_LINE_10 (EXTI_GPIO | 0x0Au) /*!< External interrupt line 10 */ +#define EXTI_LINE_11 (EXTI_GPIO | 0x0Bu) /*!< External interrupt line 11 */ +#define EXTI_LINE_12 (EXTI_GPIO | 0x0Cu) /*!< External interrupt line 12 */ +#define EXTI_LINE_13 (EXTI_GPIO | 0x0Du) /*!< External interrupt line 13 */ +#define EXTI_LINE_14 (EXTI_GPIO | 0x0Eu) /*!< External interrupt line 14 */ +#define EXTI_LINE_15 (EXTI_GPIO | 0x0Fu) /*!< External interrupt line 15 */ +#define EXTI_LINE_16 (EXTI_CONFIG | 0x10u) /*!< External interrupt line 16 Connected to the PVD Output */ +#define EXTI_LINE_17 (EXTI_CONFIG | 0x11u) /*!< External interrupt line 17 Connected to the RTC Alarm event */ +#if defined(EXTI_IMR_IM18) +#define EXTI_LINE_18 (EXTI_CONFIG | 0x12u) /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */ +#else +#define EXTI_LINE_18 (EXTI_RESERVED | 0x12u) /*!< No interrupt supported in this line */ +#endif /* EXTI_IMR_IM18 */ +#if defined(EXTI_IMR_IM19) +#define EXTI_LINE_19 (EXTI_CONFIG | 0x13u) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ +#else +#define EXTI_LINE_19 (EXTI_RESERVED | 0x13u) /*!< No interrupt supported in this line */ +#endif /* EXTI_IMR_IM19 */ +#if defined(EXTI_IMR_IM20) +#define EXTI_LINE_20 (EXTI_CONFIG | 0x14u) /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */ +#else +#define EXTI_LINE_20 (EXTI_RESERVED | 0x14u) /*!< No interrupt supported in this line */ +#endif /* EXTI_IMR_IM20 */ +#define EXTI_LINE_21 (EXTI_CONFIG | 0x15u) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */ +#define EXTI_LINE_22 (EXTI_CONFIG | 0x16u) /*!< External interrupt line 22 Connected to the RTC Wakeup event */ +#if defined(EXTI_IMR_IM23) +#define EXTI_LINE_23 (EXTI_CONFIG | 0x17u) /*!< External interrupt line 23 Connected to the LPTIM1 asynchronous event */ +#endif /* EXTI_IMR_IM23 */ + +/** + * @} + */ + +/** @defgroup EXTI_Mode EXTI Mode + * @{ + */ +#define EXTI_MODE_NONE 0x00000000u +#define EXTI_MODE_INTERRUPT 0x00000001u +#define EXTI_MODE_EVENT 0x00000002u +/** + * @} + */ + +/** @defgroup EXTI_Trigger EXTI Trigger + * @{ + */ + +#define EXTI_TRIGGER_NONE 0x00000000u +#define EXTI_TRIGGER_RISING 0x00000001u +#define EXTI_TRIGGER_FALLING 0x00000002u +#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) +/** + * @} + */ + +/** @defgroup EXTI_GPIOSel EXTI GPIOSel + * @brief + * @{ + */ +#define EXTI_GPIOA 0x00000000u +#define EXTI_GPIOB 0x00000001u +#define EXTI_GPIOC 0x00000002u +#if defined (GPIOD) +#define EXTI_GPIOD 0x00000003u +#endif /* GPIOD */ +#if defined (GPIOE) +#define EXTI_GPIOE 0x00000004u +#endif /* GPIOE */ +#if defined (GPIOF) +#define EXTI_GPIOF 0x00000005u +#endif /* GPIOF */ +#if defined (GPIOG) +#define EXTI_GPIOG 0x00000006u +#endif /* GPIOG */ +#if defined (GPIOH) +#define EXTI_GPIOH 0x00000007u +#endif /* GPIOH */ +#if defined (GPIOI) +#define EXTI_GPIOI 0x00000008u +#endif /* GPIOI */ +#if defined (GPIOJ) +#define EXTI_GPIOJ 0x00000009u +#endif /* GPIOJ */ +#if defined (GPIOK) +#define EXTI_GPIOK 0x0000000Au +#endif /* GPIOK */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Macros EXTI Exported Macros + * @{ + */ + +/** + * @} + */ + +/* Private constants --------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ +/** + * @brief EXTI Line property definition + */ +#define EXTI_PROPERTY_SHIFT 24u +#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT) +#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) +#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT) +#define EXTI_PROPERTY_MASK (EXTI_CONFIG | EXTI_GPIO) + +/** + * @brief EXTI bit usage + */ +#define EXTI_PIN_MASK 0x0000001Fu + +/** + * @brief EXTI Mask for interrupt & event mode + */ +#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT) + +/** + * @brief EXTI Mask for trigger possibilities + */ +#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) + +/** + * @brief EXTI Line number + */ +#if defined(EXTI_IMR_IM23) +#define EXTI_LINE_NB 24UL +#else +#define EXTI_LINE_NB 23UL +#endif /* EXTI_IMR_IM23 */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup EXTI_Private_Macros EXTI Private Macros + * @{ + */ +#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \ + ((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ + (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ + (((__LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB)) + +#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & EXTI_MODE_MASK) != 0x00u) && \ + (((__LINE__) & ~EXTI_MODE_MASK) == 0x00u)) + +#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u) + +#define IS_EXTI_PENDING_EDGE(__LINE__) ((__LINE__) == EXTI_TRIGGER_RISING_FALLING) + +#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u) + +#if !defined (GPIOD) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOH)) +#elif !defined (GPIOE) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOH)) +#elif !defined (GPIOF) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOH)) +#elif !defined (GPIOI) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOF) || \ + ((__PORT__) == EXTI_GPIOG) || \ + ((__PORT__) == EXTI_GPIOH)) +#elif !defined (GPIOJ) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOF) || \ + ((__PORT__) == EXTI_GPIOG) || \ + ((__PORT__) == EXTI_GPIOH) || \ + ((__PORT__) == EXTI_GPIOI)) +#else +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOF) || \ + ((__PORT__) == EXTI_GPIOG) || \ + ((__PORT__) == EXTI_GPIOH) || \ + ((__PORT__) == EXTI_GPIOI) || \ + ((__PORT__) == EXTI_GPIOJ) || \ + ((__PORT__) == EXTI_GPIOK)) +#endif /* GPIOD */ + +#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16U) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Functions EXTI Exported Functions + * @brief EXTI Exported Functions + * @{ + */ + +/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions + * @brief Configuration functions + * @{ + */ +/* Configuration functions ****************************************************/ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti); +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)); +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine); +/** + * @} + */ + +/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * @{ + */ +/* IO operation functions *****************************************************/ +void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti); +uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32f4xx_HAL_EXTI_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h new file mode 100644 index 0000000..b817f63 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h @@ -0,0 +1,428 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_flash.h + * @author MCD Application Team + * @brief Header file of FLASH HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_FLASH_H +#define __STM32F4xx_HAL_FLASH_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Types FLASH Exported Types + * @{ + */ + +/** + * @brief FLASH Procedure structure definition + */ +typedef enum +{ + FLASH_PROC_NONE = 0U, + FLASH_PROC_SECTERASE, + FLASH_PROC_MASSERASE, + FLASH_PROC_PROGRAM +} FLASH_ProcedureTypeDef; + +/** + * @brief FLASH handle Structure definition + */ +typedef struct +{ + __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*Internal variable to indicate which procedure is ongoing or not in IT context*/ + + __IO uint32_t NbSectorsToErase; /*Internal variable to save the remaining sectors to erase in IT context*/ + + __IO uint8_t VoltageForErase; /*Internal variable to provide voltage range selected by user in IT context*/ + + __IO uint32_t Sector; /*Internal variable to define the current sector which is erasing*/ + + __IO uint32_t Bank; /*Internal variable to save current bank selected during mass erase*/ + + __IO uint32_t Address; /*Internal variable to save address selected for program*/ + + HAL_LockTypeDef Lock; /* FLASH locking object */ + + __IO uint32_t ErrorCode; /* FLASH error code */ + +}FLASH_ProcessTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Constants FLASH Exported Constants + * @{ + */ +/** @defgroup FLASH_Error_Code FLASH Error Code + * @brief FLASH Error Code + * @{ + */ +#define HAL_FLASH_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_FLASH_ERROR_RD 0x00000001U /*!< Read Protection error */ +#define HAL_FLASH_ERROR_PGS 0x00000002U /*!< Programming Sequence error */ +#define HAL_FLASH_ERROR_PGP 0x00000004U /*!< Programming Parallelism error */ +#define HAL_FLASH_ERROR_PGA 0x00000008U /*!< Programming Alignment error */ +#define HAL_FLASH_ERROR_WRP 0x00000010U /*!< Write protection error */ +#define HAL_FLASH_ERROR_OPERATION 0x00000020U /*!< Operation Error */ +/** + * @} + */ + +/** @defgroup FLASH_Type_Program FLASH Type Program + * @{ + */ +#define FLASH_TYPEPROGRAM_BYTE 0x00000000U /*!< Program byte (8-bit) at a specified address */ +#define FLASH_TYPEPROGRAM_HALFWORD 0x00000001U /*!< Program a half-word (16-bit) at a specified address */ +#define FLASH_TYPEPROGRAM_WORD 0x00000002U /*!< Program a word (32-bit) at a specified address */ +#define FLASH_TYPEPROGRAM_DOUBLEWORD 0x00000003U /*!< Program a double word (64-bit) at a specified address */ +/** + * @} + */ + +/** @defgroup FLASH_Flag_definition FLASH Flag definition + * @brief Flag definition + * @{ + */ +#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Operation flag */ +#define FLASH_FLAG_OPERR FLASH_SR_SOP /*!< FLASH operation Error flag */ +#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */ +#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming Alignment error flag */ +#define FLASH_FLAG_PGPERR FLASH_SR_PGPERR /*!< FLASH Programming Parallelism error flag */ +#define FLASH_FLAG_PGSERR FLASH_SR_PGSERR /*!< FLASH Programming Sequence error flag */ +#if defined(FLASH_SR_RDERR) +#define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< Read Protection error flag (PCROP) */ +#endif /* FLASH_SR_RDERR */ +#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ +/** + * @} + */ + +/** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition + * @brief FLASH Interrupt definition + * @{ + */ +#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */ +#define FLASH_IT_ERR 0x02000000U /*!< Error Interrupt source */ +/** + * @} + */ + +/** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism + * @{ + */ +#define FLASH_PSIZE_BYTE 0x00000000U +#define FLASH_PSIZE_HALF_WORD 0x00000100U +#define FLASH_PSIZE_WORD 0x00000200U +#define FLASH_PSIZE_DOUBLE_WORD 0x00000300U +#define CR_PSIZE_MASK 0xFFFFFCFFU +/** + * @} + */ + +/** @defgroup FLASH_Keys FLASH Keys + * @{ + */ +#define RDP_KEY ((uint16_t)0x00A5) +#define FLASH_KEY1 0x45670123U +#define FLASH_KEY2 0xCDEF89ABU +#define FLASH_OPT_KEY1 0x08192A3BU +#define FLASH_OPT_KEY2 0x4C5D6E7FU +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Macros FLASH Exported Macros + * @{ + */ +/** + * @brief Set the FLASH Latency. + * @param __LATENCY__ FLASH Latency + * The value of this parameter depend on device used within the same series + * @retval none + */ +#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (*(__IO uint8_t *)ACR_BYTE0_ADDRESS = (uint8_t)(__LATENCY__)) + +/** + * @brief Get the FLASH Latency. + * @retval FLASH Latency + * The value of this parameter depend on device used within the same series + */ +#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) + +/** + * @brief Enable the FLASH prefetch buffer. + * @retval none + */ +#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTEN) + +/** + * @brief Disable the FLASH prefetch buffer. + * @retval none + */ +#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTEN)) + +/** + * @brief Enable the FLASH instruction cache. + * @retval none + */ +#define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() (FLASH->ACR |= FLASH_ACR_ICEN) + +/** + * @brief Disable the FLASH instruction cache. + * @retval none + */ +#define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() (FLASH->ACR &= (~FLASH_ACR_ICEN)) + +/** + * @brief Enable the FLASH data cache. + * @retval none + */ +#define __HAL_FLASH_DATA_CACHE_ENABLE() (FLASH->ACR |= FLASH_ACR_DCEN) + +/** + * @brief Disable the FLASH data cache. + * @retval none + */ +#define __HAL_FLASH_DATA_CACHE_DISABLE() (FLASH->ACR &= (~FLASH_ACR_DCEN)) + +/** + * @brief Resets the FLASH instruction Cache. + * @note This function must be used only when the Instruction Cache is disabled. + * @retval None + */ +#define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_ICRST; \ + FLASH->ACR &= ~FLASH_ACR_ICRST; \ + }while(0U) + +/** + * @brief Resets the FLASH data Cache. + * @note This function must be used only when the data Cache is disabled. + * @retval None + */ +#define __HAL_FLASH_DATA_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_DCRST; \ + FLASH->ACR &= ~FLASH_ACR_DCRST; \ + }while(0U) +/** + * @brief Enable the specified FLASH interrupt. + * @param __INTERRUPT__ FLASH interrupt + * This parameter can be any combination of the following values: + * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt + * @arg FLASH_IT_ERR: Error Interrupt + * @retval none + */ +#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__)) + +/** + * @brief Disable the specified FLASH interrupt. + * @param __INTERRUPT__ FLASH interrupt + * This parameter can be any combination of the following values: + * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt + * @arg FLASH_IT_ERR: Error Interrupt + * @retval none + */ +#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(uint32_t)(__INTERRUPT__)) + +/** + * @brief Get the specified FLASH flag status. + * @param __FLAG__ specifies the FLASH flags to check. + * This parameter can be any combination of the following values: + * @arg FLASH_FLAG_EOP : FLASH End of Operation flag + * @arg FLASH_FLAG_OPERR : FLASH operation Error flag + * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag + * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag + * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag + * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag + * @arg FLASH_FLAG_RDERR : FLASH Read Protection error flag (PCROP) (*) + * @arg FLASH_FLAG_BSY : FLASH Busy flag + * (*) FLASH_FLAG_RDERR is not available for STM32F405xx/407xx/415xx/417xx devices + * @retval The new state of __FLAG__ (SET or RESET). + */ +#define __HAL_FLASH_GET_FLAG(__FLAG__) ((FLASH->SR & (__FLAG__))) + +/** + * @brief Clear the specified FLASH flags. + * @param __FLAG__ specifies the FLASH flags to clear. + * This parameter can be any combination of the following values: + * @arg FLASH_FLAG_EOP : FLASH End of Operation flag + * @arg FLASH_FLAG_OPERR : FLASH operation Error flag + * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag + * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag + * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag + * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag + * @arg FLASH_FLAG_RDERR : FLASH Read Protection error flag (PCROP) (*) + * (*) FLASH_FLAG_RDERR is not available for STM32F405xx/407xx/415xx/417xx devices + * @retval none + */ +#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) (FLASH->SR = (__FLAG__)) +/** + * @} + */ + +/* Include FLASH HAL Extension module */ +#include "stm32f4xx_hal_flash_ex.h" +#include "stm32f4xx_hal_flash_ramfunc.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FLASH_Exported_Functions + * @{ + */ +/** @addtogroup FLASH_Exported_Functions_Group1 + * @{ + */ +/* Program operation functions ***********************************************/ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); +/* FLASH IRQ handler method */ +void HAL_FLASH_IRQHandler(void); +/* Callbacks in non blocking modes */ +void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); +void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); +/** + * @} + */ + +/** @addtogroup FLASH_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions **********************************************/ +HAL_StatusTypeDef HAL_FLASH_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_Lock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); +/* Option bytes control */ +HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); +/** + * @} + */ + +/** @addtogroup FLASH_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State functions ************************************************/ +uint32_t HAL_FLASH_GetError(void); +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup FLASH_Private_Variables FLASH Private Variables + * @{ + */ + +/** + * @} + */ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup FLASH_Private_Constants FLASH Private Constants + * @{ + */ + +/** + * @brief ACR register byte 0 (Bits[7:0]) base address + */ +#define ACR_BYTE0_ADDRESS 0x40023C00U +/** + * @brief OPTCR register byte 0 (Bits[7:0]) base address + */ +#define OPTCR_BYTE0_ADDRESS 0x40023C14U +/** + * @brief OPTCR register byte 1 (Bits[15:8]) base address + */ +#define OPTCR_BYTE1_ADDRESS 0x40023C15U +/** + * @brief OPTCR register byte 2 (Bits[23:16]) base address + */ +#define OPTCR_BYTE2_ADDRESS 0x40023C16U +/** + * @brief OPTCR register byte 3 (Bits[31:24]) base address + */ +#define OPTCR_BYTE3_ADDRESS 0x40023C17U + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup FLASH_Private_Macros FLASH Private Macros + * @{ + */ + +/** @defgroup FLASH_IS_FLASH_Definitions FLASH Private macros to check input parameters + * @{ + */ +#define IS_FLASH_TYPEPROGRAM(VALUE)(((VALUE) == FLASH_TYPEPROGRAM_BYTE) || \ + ((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \ + ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \ + ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD)) +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup FLASH_Private_Functions FLASH Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_FLASH_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h new file mode 100644 index 0000000..4dbad67 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h @@ -0,0 +1,1066 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_flash_ex.h + * @author MCD Application Team + * @brief Header file of FLASH HAL Extension module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_FLASH_EX_H +#define __STM32F4xx_HAL_FLASH_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASHEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Types FLASH Exported Types + * @{ + */ + +/** + * @brief FLASH Erase structure definition + */ +typedef struct +{ + uint32_t TypeErase; /*!< Mass erase or sector Erase. + This parameter can be a value of @ref FLASHEx_Type_Erase */ + + uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled. + This parameter must be a value of @ref FLASHEx_Banks */ + + uint32_t Sector; /*!< Initial FLASH sector to erase when Mass erase is disabled + This parameter must be a value of @ref FLASHEx_Sectors */ + + uint32_t NbSectors; /*!< Number of sectors to be erased. + This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/ + + uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism + This parameter must be a value of @ref FLASHEx_Voltage_Range */ + +} FLASH_EraseInitTypeDef; + +/** + * @brief FLASH Option Bytes Program structure definition + */ +typedef struct +{ + uint32_t OptionType; /*!< Option byte to be configured. + This parameter can be a value of @ref FLASHEx_Option_Type */ + + uint32_t WRPState; /*!< Write protection activation or deactivation. + This parameter can be a value of @ref FLASHEx_WRP_State */ + + uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected. + The value of this parameter depend on device used within the same series */ + + uint32_t Banks; /*!< Select banks for WRP activation/deactivation of all sectors. + This parameter must be a value of @ref FLASHEx_Banks */ + + uint32_t RDPLevel; /*!< Set the read protection level. + This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */ + + uint32_t BORLevel; /*!< Set the BOR Level. + This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */ + + uint8_t USERConfig; /*!< Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. */ + +} FLASH_OBProgramInitTypeDef; + +/** + * @brief FLASH Advanced Option Bytes Program structure definition + */ +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ + defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ + defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ + defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +typedef struct +{ + uint32_t OptionType; /*!< Option byte to be configured for extension. + This parameter can be a value of @ref FLASHEx_Advanced_Option_Type */ + + uint32_t PCROPState; /*!< PCROP activation or deactivation. + This parameter can be a value of @ref FLASHEx_PCROP_State */ + +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\ + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) + uint16_t Sectors; /*!< specifies the sector(s) set for PCROP. + This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */ +#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx ||\ + STM32F412Cx || STM32F413xx || STM32F423xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) + uint32_t Banks; /*!< Select banks for PCROP activation/deactivation of all sectors. + This parameter must be a value of @ref FLASHEx_Banks */ + + uint16_t SectorsBank1; /*!< Specifies the sector(s) set for PCROP for Bank1. + This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */ + + uint16_t SectorsBank2; /*!< Specifies the sector(s) set for PCROP for Bank2. + This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */ + + uint8_t BootConfig; /*!< Specifies Option bytes for boot config. + This parameter can be a value of @ref FLASHEx_Dual_Boot */ + +#endif /*STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ +}FLASH_AdvOBProgramInitTypeDef; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || + STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants + * @{ + */ + +/** @defgroup FLASHEx_Type_Erase FLASH Type Erase + * @{ + */ +#define FLASH_TYPEERASE_SECTORS 0x00000000U /*!< Sectors erase only */ +#define FLASH_TYPEERASE_MASSERASE 0x00000001U /*!< Flash Mass erase activation */ +/** + * @} + */ + +/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range + * @{ + */ +#define FLASH_VOLTAGE_RANGE_1 0x00000000U /*!< Device operating range: 1.8V to 2.1V */ +#define FLASH_VOLTAGE_RANGE_2 0x00000001U /*!< Device operating range: 2.1V to 2.7V */ +#define FLASH_VOLTAGE_RANGE_3 0x00000002U /*!< Device operating range: 2.7V to 3.6V */ +#define FLASH_VOLTAGE_RANGE_4 0x00000003U /*!< Device operating range: 2.7V to 3.6V + External Vpp */ +/** + * @} + */ + +/** @defgroup FLASHEx_WRP_State FLASH WRP State + * @{ + */ +#define OB_WRPSTATE_DISABLE 0x00000000U /*!< Disable the write protection of the desired bank 1 sectors */ +#define OB_WRPSTATE_ENABLE 0x00000001U /*!< Enable the write protection of the desired bank 1 sectors */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Type FLASH Option Type + * @{ + */ +#define OPTIONBYTE_WRP 0x00000001U /*!< WRP option byte configuration */ +#define OPTIONBYTE_RDP 0x00000002U /*!< RDP option byte configuration */ +#define OPTIONBYTE_USER 0x00000004U /*!< USER option byte configuration */ +#define OPTIONBYTE_BOR 0x00000008U /*!< BOR option byte configuration */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection + * @{ + */ +#define OB_RDP_LEVEL_0 ((uint8_t)0xAA) +#define OB_RDP_LEVEL_1 ((uint8_t)0x55) +#define OB_RDP_LEVEL_2 ((uint8_t)0xCC) /*!< Warning: When enabling read protection level 2 + it s no more possible to go back to level 1 or 0 */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog + * @{ + */ +#define OB_IWDG_SW ((uint8_t)0x20) /*!< Software IWDG selected */ +#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP + * @{ + */ +#define OB_STOP_NO_RST ((uint8_t)0x40) /*!< No reset generated when entering in STOP */ +#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */ +/** + * @} + */ + + +/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY + * @{ + */ +#define OB_STDBY_NO_RST ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */ +/** + * @} + */ + +/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level + * @{ + */ +#define OB_BOR_LEVEL3 ((uint8_t)0x00) /*!< Supply voltage ranges from 2.70 to 3.60 V */ +#define OB_BOR_LEVEL2 ((uint8_t)0x04) /*!< Supply voltage ranges from 2.40 to 2.70 V */ +#define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< Supply voltage ranges from 2.10 to 2.40 V */ +#define OB_BOR_OFF ((uint8_t)0x0C) /*!< Supply voltage ranges from 1.62 to 2.10 V */ +/** + * @} + */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ + defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ + defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ + defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/** @defgroup FLASHEx_PCROP_State FLASH PCROP State + * @{ + */ +#define OB_PCROP_STATE_DISABLE 0x00000000U /*!< Disable PCROP */ +#define OB_PCROP_STATE_ENABLE 0x00000001U /*!< Enable PCROP */ +/** + * @} + */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\ + STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ + STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ + +/** @defgroup FLASHEx_Advanced_Option_Type FLASH Advanced Option Type + * @{ + */ +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) +#define OPTIONBYTE_PCROP 0x00000001U /*!< PCROP option byte configuration */ +#define OPTIONBYTE_BOOTCONFIG 0x00000002U /*!< BOOTConfig option byte configuration */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ + defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\ + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\ + defined(STM32F423xx) +#define OPTIONBYTE_PCROP 0x00000001U /*!= FLASH_BASE) && ((ADDRESS) <= FLASH_END)) || \ + (((ADDRESS) >= FLASH_OTP_BASE) && ((ADDRESS) <= FLASH_OTP_END))) + +#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL)) + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) +#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFF000000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F413xx) || defined(STM32F423xx) +#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFF8000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* STM32F413xx || STM32F423xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) +#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ + +#if defined(STM32F401xC) +#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* STM32F401xC */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + +#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\ + defined(STM32F412Rx) || defined(STM32F412Cx) +#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* STM32F401xE || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) +#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F413xx) || defined(STM32F423xx) +#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFF8000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* STM32F413xx || STM32F423xx */ + +#if defined(STM32F401xC) +#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* STM32F401xC */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + +#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\ + defined(STM32F412Rx) || defined(STM32F412Cx) +#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* STM32F401xE || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) +#define IS_OB_BOOT(BOOT) (((BOOT) == OB_DUAL_BOOT_ENABLE) || ((BOOT) == OB_DUAL_BOOT_DISABLE)) +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ + defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ + defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ + defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +#define IS_OB_PCROP_SELECT(PCROP) (((PCROP) == OB_PCROP_SELECTED) || ((PCROP) == OB_PCROP_DESELECTED)) +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\ + STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ + STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup FLASHEx_Private_Functions FLASH Private Functions + * @{ + */ +void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange); +void FLASH_FlushCaches(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_FLASH_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h new file mode 100644 index 0000000..9fab0c9 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h @@ -0,0 +1,79 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_flash_ramfunc.h + * @author MCD Application Team + * @brief Header file of FLASH RAMFUNC driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_FLASH_RAMFUNC_H +#define __STM32F4xx_FLASH_RAMFUNC_H + +#ifdef __cplusplus + extern "C" { +#endif +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\ + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASH_RAMFUNC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FLASH_RAMFUNC_Exported_Functions + * @{ + */ + +/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1 + * @{ + */ +__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StopFlashInterfaceClk(void); +__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StartFlashInterfaceClk(void); +__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableFlashSleepMode(void); +__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableFlashSleepMode(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F4xx_FLASH_RAMFUNC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h new file mode 100644 index 0000000..5a17538 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h @@ -0,0 +1,309 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_gpio.h + * @author MCD Application Team + * @brief Header file of GPIO HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_GPIO_H +#define __STM32F4xx_HAL_GPIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Types GPIO Exported Types + * @{ + */ + +/** + * @brief GPIO Init structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins_define */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_mode_define */ + + uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. + This parameter can be a value of @ref GPIO_pull_define */ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_speed_define */ + + uint32_t Alternate; /*!< Peripheral to be connected to the selected pins. + This parameter can be a value of @ref GPIO_Alternate_function_selection */ +}GPIO_InitTypeDef; + +/** + * @brief GPIO Bit SET and Bit RESET enumeration + */ +typedef enum +{ + GPIO_PIN_RESET = 0, + GPIO_PIN_SET +}GPIO_PinState; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup GPIO_Exported_Constants GPIO Exported Constants + * @{ + */ + +/** @defgroup GPIO_pins_define GPIO pins define + * @{ + */ +#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */ +#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */ +#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */ +#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */ +#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */ +#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */ +#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */ +#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ +#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */ + +#define GPIO_PIN_MASK 0x0000FFFFU /* PIN mask for assert test */ +/** + * @} + */ + +/** @defgroup GPIO_mode_define GPIO mode define + * @brief GPIO Configuration Mode + * Elements values convention: 0xX0yz00YZ + * - X : GPIO mode or EXTI Mode + * - y : External IT or Event trigger detection + * - z : IO configuration on External IT or Event + * - Y : Output type (Push Pull or Open Drain) + * - Z : IO Direction mode (Input, Output, Alternate or Analog) + * @{ + */ +#define GPIO_MODE_INPUT 0x00000000U /*!< Input Floating Mode */ +#define GPIO_MODE_OUTPUT_PP 0x00000001U /*!< Output Push Pull Mode */ +#define GPIO_MODE_OUTPUT_OD 0x00000011U /*!< Output Open Drain Mode */ +#define GPIO_MODE_AF_PP 0x00000002U /*!< Alternate Function Push Pull Mode */ +#define GPIO_MODE_AF_OD 0x00000012U /*!< Alternate Function Open Drain Mode */ + +#define GPIO_MODE_ANALOG 0x00000003U /*!< Analog Mode */ + +#define GPIO_MODE_IT_RISING 0x10110000U /*!< External Interrupt Mode with Rising edge trigger detection */ +#define GPIO_MODE_IT_FALLING 0x10210000U /*!< External Interrupt Mode with Falling edge trigger detection */ +#define GPIO_MODE_IT_RISING_FALLING 0x10310000U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ + +#define GPIO_MODE_EVT_RISING 0x10120000U /*!< External Event Mode with Rising edge trigger detection */ +#define GPIO_MODE_EVT_FALLING 0x10220000U /*!< External Event Mode with Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING_FALLING 0x10320000U /*!< External Event Mode with Rising/Falling edge trigger detection */ +/** + * @} + */ + +/** @defgroup GPIO_speed_define GPIO speed define + * @brief GPIO Output Maximum frequency + * @{ + */ +#define GPIO_SPEED_FREQ_LOW 0x00000000U /*!< IO works at 2 MHz, please refer to the product datasheet */ +#define GPIO_SPEED_FREQ_MEDIUM 0x00000001U /*!< range 12,5 MHz to 50 MHz, please refer to the product datasheet */ +#define GPIO_SPEED_FREQ_HIGH 0x00000002U /*!< range 25 MHz to 100 MHz, please refer to the product datasheet */ +#define GPIO_SPEED_FREQ_VERY_HIGH 0x00000003U /*!< range 50 MHz to 200 MHz, please refer to the product datasheet */ +/** + * @} + */ + + /** @defgroup GPIO_pull_define GPIO pull define + * @brief GPIO Pull-Up or Pull-Down Activation + * @{ + */ +#define GPIO_NOPULL 0x00000000U /*!< No Pull-up or Pull-down activation */ +#define GPIO_PULLUP 0x00000001U /*!< Pull-up activation */ +#define GPIO_PULLDOWN 0x00000002U /*!< Pull-down activation */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Macros GPIO Exported Macros + * @{ + */ + +/** + * @brief Checks whether the specified EXTI line flag is set or not. + * @param __EXTI_LINE__ specifies the EXTI line flag to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) + +/** + * @brief Clears the EXTI's line pending flags. + * @param __EXTI_LINE__ specifies the EXTI lines flags to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) + +/** + * @brief Checks whether the specified EXTI line is asserted or not. + * @param __EXTI_LINE__ specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) + +/** + * @brief Clears the EXTI's line pending bits. + * @param __EXTI_LINE__ specifies the EXTI lines to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) + +/** + * @brief Generates a Software interrupt on selected EXTI line. + * @param __EXTI_LINE__ specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__)) +/** + * @} + */ + +/* Include GPIO HAL Extension module */ +#include "stm32f4xx_hal_gpio_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup GPIO_Exported_Functions + * @{ + */ + +/** @addtogroup GPIO_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); +/** + * @} + */ + +/** @addtogroup GPIO_Exported_Functions_Group2 + * @{ + */ +/* IO operation functions *****************************************************/ +GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); +void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); + +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup GPIO_Private_Constants GPIO Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup GPIO_Private_Macros GPIO Private Macros + * @{ + */ +#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) +#define IS_GPIO_PIN(PIN) (((((uint32_t)PIN) & GPIO_PIN_MASK ) != 0x00U) && ((((uint32_t)PIN) & ~GPIO_PIN_MASK) == 0x00U)) +#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\ + ((MODE) == GPIO_MODE_OUTPUT_PP) ||\ + ((MODE) == GPIO_MODE_OUTPUT_OD) ||\ + ((MODE) == GPIO_MODE_AF_PP) ||\ + ((MODE) == GPIO_MODE_AF_OD) ||\ + ((MODE) == GPIO_MODE_IT_RISING) ||\ + ((MODE) == GPIO_MODE_IT_FALLING) ||\ + ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\ + ((MODE) == GPIO_MODE_EVT_RISING) ||\ + ((MODE) == GPIO_MODE_EVT_FALLING) ||\ + ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\ + ((MODE) == GPIO_MODE_ANALOG)) +#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || \ + ((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH)) +#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \ + ((PULL) == GPIO_PULLDOWN)) +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup GPIO_Private_Functions GPIO Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_GPIO_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h new file mode 100644 index 0000000..aa1e34d --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h @@ -0,0 +1,1592 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_gpio_ex.h + * @author MCD Application Team + * @brief Header file of GPIO HAL Extension module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_GPIO_EX_H +#define __STM32F4xx_HAL_GPIO_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIOEx GPIOEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants + * @{ + */ + +/** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection + * @{ + */ + +/*------------------------------------------ STM32F429xx/STM32F439xx ---------*/ +#if defined(STM32F429xx) || defined(STM32F439xx) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ +#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ +#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ +#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */ +#define GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */ +#define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */ +#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */ +#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ +#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ +#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ +#define GPIO_AF8_UART7 ((uint8_t)0x08) /* UART7 Alternate Function mapping */ +#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ +#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */ +#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ +#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ +#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ +#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LCD-TFT Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ +#define GPIO_AF10_OTG_HS ((uint8_t)0x0A) /* OTG_HS Alternate Function mapping */ + +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ +#define GPIO_AF12_OTG_HS_FS ((uint8_t)0x0C) /* OTG HS configured in FS, Alternate Function mapping */ +#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ + +/** + * @brief AF 13 selection + */ +#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */ + +/** + * @brief AF 14 selection + */ +#define GPIO_AF14_LTDC ((uint8_t)0x0E) /* LCD-TFT Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ +#endif /* STM32F429xx || STM32F439xx */ +/*----------------------------------------------------------------------------*/ + +/*---------------------------------- STM32F427xx/STM32F437xx------------------*/ +#if defined(STM32F427xx) || defined(STM32F437xx) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ +#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ +#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ +#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */ +#define GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */ +#define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */ +/** @brief GPIO_Legacy + */ +#define GPIO_AF5_I2S3ext GPIO_AF5_SPI3 /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */ +#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ +#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ +#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ +#define GPIO_AF8_UART7 ((uint8_t)0x08) /* UART7 Alternate Function mapping */ +#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ +#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */ +#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ +#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ +#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ +#define GPIO_AF10_OTG_HS ((uint8_t)0x0A) /* OTG_HS Alternate Function mapping */ + +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ +#define GPIO_AF12_OTG_HS_FS ((uint8_t)0x0C) /* OTG HS configured in FS, Alternate Function mapping */ +#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ + +/** + * @brief AF 13 selection + */ +#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ +#endif /* STM32F427xx || STM32F437xx */ +/*----------------------------------------------------------------------------*/ + +/*---------------------------------- STM32F407xx/STM32F417xx------------------*/ +#if defined(STM32F407xx) || defined(STM32F417xx) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ +#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ +#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ +#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ +#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ +#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ +#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */ +#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ +#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ +#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ +#define GPIO_AF10_OTG_HS ((uint8_t)0x0A) /* OTG_HS Alternate Function mapping */ + +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_FSMC ((uint8_t)0x0C) /* FSMC Alternate Function mapping */ +#define GPIO_AF12_OTG_HS_FS ((uint8_t)0x0C) /* OTG HS configured in FS, Alternate Function mapping */ +#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ + +/** + * @brief AF 13 selection + */ +#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ +#endif /* STM32F407xx || STM32F417xx */ +/*----------------------------------------------------------------------------*/ + +/*---------------------------------- STM32F405xx/STM32F415xx------------------*/ +#if defined(STM32F405xx) || defined(STM32F415xx) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ +#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ +#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ +#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ +#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ +#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ +#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */ +#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ +#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ +#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ +#define GPIO_AF10_OTG_HS ((uint8_t)0x0A) /* OTG_HS Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_FSMC ((uint8_t)0x0C) /* FSMC Alternate Function mapping */ +#define GPIO_AF12_OTG_HS_FS ((uint8_t)0x0C) /* OTG HS configured in FS, Alternate Function mapping */ +#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ +#endif /* STM32F405xx || STM32F415xx */ + +/*----------------------------------------------------------------------------*/ + +/*---------------------------------------- STM32F401xx------------------------*/ +#if defined(STM32F401xC) || defined(STM32F401xE) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ +#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ +#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3 Alternate Function mapping */ +#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */ +#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping */ +#define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping */ + + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ +#endif /* STM32F401xC || STM32F401xE */ +/*----------------------------------------------------------------------------*/ + +/*--------------- STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx-------------*/ +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ +#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ +#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ +#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ +#define GPIO_AF4_FMPI2C1 ((uint8_t)0x04) /* FMPI2C1 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4/I2S4 Alternate Function mapping */ +#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* I2S2 Alternate Function mapping */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_SPI4 ((uint8_t)0x06) /* SPI4/I2S4 Alternate Function mapping */ +#define GPIO_AF6_SPI5 ((uint8_t)0x06) /* SPI5/I2S5 Alternate Function mapping */ +#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */ +#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM1 Alternate Function mapping */ +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ +#define GPIO_AF8_USART3 ((uint8_t)0x08) /* USART3 Alternate Function mapping */ +#define GPIO_AF8_DFSDM1 ((uint8_t)0x08) /* DFSDM1 Alternate Function mapping */ +#define GPIO_AF8_CAN1 ((uint8_t)0x08) /* CAN1 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ +#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ +#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ +#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping */ +#define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping */ +#define GPIO_AF9_FMPI2C1 ((uint8_t)0x09) /* FMPI2C1 Alternate Function mapping */ +#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ +#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ +#define GPIO_AF9_QSPI ((uint8_t)0x09) /* QSPI Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ +#define GPIO_AF10_DFSDM1 ((uint8_t)0x0A) /* DFSDM1 Alternate Function mapping */ +#define GPIO_AF10_QSPI ((uint8_t)0x0A) /* QSPI Alternate Function mapping */ +#define GPIO_AF10_FMC ((uint8_t)0x0A) /* FMC Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ +#define GPIO_AF12_FSMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ + +/*----------------------------------------------------------------------------*/ + +/*--------------- STM32F413xx/STM32F423xx-------------------------------------*/ +#if defined(STM32F413xx) || defined(STM32F423xx) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ +#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ +#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ +#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ +#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ +#define GPIO_AF3_DFSDM2 ((uint8_t)0x03) /* DFSDM2 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ +#define GPIO_AF4_FMPI2C1 ((uint8_t)0x04) /* FMPI2C1 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4/I2S4 Alternate Function mapping */ +#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* I2S2 Alternate Function mapping */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_SPI4 ((uint8_t)0x06) /* SPI4/I2S4 Alternate Function mapping */ +#define GPIO_AF6_SPI5 ((uint8_t)0x06) /* SPI5/I2S5 Alternate Function mapping */ +#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */ +#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM1 Alternate Function mapping */ +#define GPIO_AF6_DFSDM2 ((uint8_t)0x06) /* DFSDM2 Alternate Function mapping */ +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF7_SAI1 ((uint8_t)0x07) /* SAI1 Alternate Function mapping */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */ +#define GPIO_AF7_DFSDM2 ((uint8_t)0x07) /* DFSDM2 Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ +#define GPIO_AF8_USART3 ((uint8_t)0x08) /* USART3 Alternate Function mapping */ +#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ +#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ +#define GPIO_AF8_UART7 ((uint8_t)0x08) /* UART8 Alternate Function mapping */ +#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */ +#define GPIO_AF8_DFSDM1 ((uint8_t)0x08) /* DFSDM1 Alternate Function mapping */ +#define GPIO_AF8_CAN1 ((uint8_t)0x08) /* CAN1 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ +#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ +#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ +#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping */ +#define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping */ +#define GPIO_AF9_FMPI2C1 ((uint8_t)0x09) /* FMPI2C1 Alternate Function mapping */ +#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ +#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ +#define GPIO_AF9_QSPI ((uint8_t)0x09) /* QSPI Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_SAI1 ((uint8_t)0x0A) /* SAI1 Alternate Function mapping */ +#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ +#define GPIO_AF10_DFSDM1 ((uint8_t)0x0A) /* DFSDM1 Alternate Function mapping */ +#define GPIO_AF10_DFSDM2 ((uint8_t)0x0A) /* DFSDM2 Alternate Function mapping */ +#define GPIO_AF10_QSPI ((uint8_t)0x0A) /* QSPI Alternate Function mapping */ +#define GPIO_AF10_FSMC ((uint8_t)0x0A) /* FSMC Alternate Function mapping */ + +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_UART4 ((uint8_t)0x0B) /* UART4 Alternate Function mapping */ +#define GPIO_AF11_UART5 ((uint8_t)0x0B) /* UART5 Alternate Function mapping */ +#define GPIO_AF11_UART9 ((uint8_t)0x0B) /* UART9 Alternate Function mapping */ +#define GPIO_AF11_UART10 ((uint8_t)0x0B) /* UART10 Alternate Function mapping */ +#define GPIO_AF11_CAN3 ((uint8_t)0x0B) /* CAN3 Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ +#define GPIO_AF12_FSMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ + +/** + * @brief AF 14 selection + */ +#define GPIO_AF14_RNG ((uint8_t)0x0E) /* RNG Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ +#endif /* STM32F413xx || STM32F423xx */ + +/*---------------------------------------- STM32F411xx------------------------*/ +#if defined(STM32F411xE) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ +#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ +#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */ +#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* I2S2 Alternate Function mapping */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_SPI4 ((uint8_t)0x06) /* SPI4/I2S4 Alternate Function mapping */ +#define GPIO_AF6_SPI5 ((uint8_t)0x06) /* SPI5/I2S5 Alternate Function mapping */ +#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ +#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping */ +#define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ +#endif /* STM32F411xE */ + +/*---------------------------------------- STM32F410xx------------------------*/ +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ +#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_FMPI2C1 ((uint8_t)0x04) /* FMPI2C1 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */ +#if defined(STM32F410Cx) || defined(STM32F410Rx) +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ +#endif /* STM32F410Cx || STM32F410Rx */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI1 ((uint8_t)0x06) /* SPI1 Alternate Function mapping */ +#if defined(STM32F410Cx) || defined(STM32F410Rx) +#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* I2S2 Alternate Function mapping */ +#endif /* STM32F410Cx || STM32F410Rx */ +#define GPIO_AF6_SPI5 ((uint8_t)0x06) /* SPI5/I2S5 Alternate Function mapping */ +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping */ +#define GPIO_AF9_FMPI2C1 ((uint8_t)0x09) /* FMPI2C1 Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + +/*---------------------------------------- STM32F446xx -----------------------*/ +#if defined(STM32F446xx) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ +#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ +#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ +#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ +#define GPIO_AF3_CEC ((uint8_t)0x03) /* CEC Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ +#define GPIO_AF4_FMPI2C1 ((uint8_t)0x04) /* FMPI2C1 Alternate Function mapping */ +#define GPIO_AF4_CEC ((uint8_t)0x04) /* CEC Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_SPI4 ((uint8_t)0x06) /* SPI4 Alternate Function mapping */ +#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_UART5 ((uint8_t)0x07) /* UART5 Alternate Function mapping */ +#define GPIO_AF7_SPI2 ((uint8_t)0x07) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF7_SPDIFRX ((uint8_t)0x07) /* SPDIFRX Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ +#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ +#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ +#define GPIO_AF8_SPDIFRX ((uint8_t)0x08) /* SPDIFRX Alternate Function mapping */ +#define GPIO_AF8_SAI2 ((uint8_t)0x08) /* SAI2 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ +#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */ +#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ +#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ +#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ +#define GPIO_AF9_QSPI ((uint8_t)0x09) /* QSPI Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ +#define GPIO_AF10_OTG_HS ((uint8_t)0x0A) /* OTG_HS Alternate Function mapping */ +#define GPIO_AF10_SAI2 ((uint8_t)0x0A) /* SAI2 Alternate Function mapping */ +#define GPIO_AF10_QSPI ((uint8_t)0x0A) /* QSPI Alternate Function mapping */ + +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ +#define GPIO_AF12_OTG_HS_FS ((uint8_t)0x0C) /* OTG HS configured in FS, Alternate Function mapping */ +#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ + +/** + * @brief AF 13 selection + */ +#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ + +#endif /* STM32F446xx */ +/*----------------------------------------------------------------------------*/ + +/*-------------------------------- STM32F469xx/STM32F479xx--------------------*/ +#if defined(STM32F469xx) || defined(STM32F479xx) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ +#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ +#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ +#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */ +#define GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */ +#define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */ +#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */ +#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ +#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ +#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ +#define GPIO_AF8_UART7 ((uint8_t)0x08) /* UART7 Alternate Function mapping */ +#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ +#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */ +#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ +#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ +#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ +#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LCD-TFT Alternate Function mapping */ +#define GPIO_AF9_QSPI ((uint8_t)0x09) /* QSPI Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ +#define GPIO_AF10_OTG_HS ((uint8_t)0x0A) /* OTG_HS Alternate Function mapping */ +#define GPIO_AF10_QSPI ((uint8_t)0x0A) /* QSPI Alternate Function mapping */ + +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ +#define GPIO_AF12_OTG_HS_FS ((uint8_t)0x0C) /* OTG HS configured in FS, Alternate Function mapping */ +#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ + +/** + * @brief AF 13 selection + */ +#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */ +#define GPIO_AF13_DSI ((uint8_t)0x0D) /* DSI Alternate Function mapping */ + +/** + * @brief AF 14 selection + */ +#define GPIO_AF14_LTDC ((uint8_t)0x0E) /* LCD-TFT Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ + +#endif /* STM32F469xx || STM32F479xx */ +/*----------------------------------------------------------------------------*/ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Macros GPIO Exported Macros + * @{ + */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Functions GPIO Exported Functions + * @{ + */ +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup GPIOEx_Private_Constants GPIO Private Constants + * @{ + */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup GPIOEx_Private_Macros GPIO Private Macros + * @{ + */ +/** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index + * @{ + */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) +#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOD))? 3U :\ + ((__GPIOx__) == (GPIOE))? 4U :\ + ((__GPIOx__) == (GPIOF))? 5U :\ + ((__GPIOx__) == (GPIOG))? 6U :\ + ((__GPIOx__) == (GPIOH))? 7U : 8U) +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) +#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOD))? 3U :\ + ((__GPIOx__) == (GPIOE))? 4U :\ + ((__GPIOx__) == (GPIOF))? 5U :\ + ((__GPIOx__) == (GPIOG))? 6U :\ + ((__GPIOx__) == (GPIOH))? 7U :\ + ((__GPIOx__) == (GPIOI))? 8U :\ + ((__GPIOx__) == (GPIOJ))? 9U : 10U) +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U : 7U) +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) +#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOD))? 3U :\ + ((__GPIOx__) == (GPIOE))? 4U : 7U) +#endif /* STM32F401xC || STM32F401xE || STM32F411xE */ + +#if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOD))? 3U :\ + ((__GPIOx__) == (GPIOE))? 4U :\ + ((__GPIOx__) == (GPIOF))? 5U :\ + ((__GPIOx__) == (GPIOG))? 6U : 7U) +#endif /* STM32F446xx || STM32F412Zx || STM32F413xx || STM32F423xx */ +#if defined(STM32F412Vx) +#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOD))? 3U :\ + ((__GPIOx__) == (GPIOE))? 4U : 7U) +#endif /* STM32F412Vx */ +#if defined(STM32F412Rx) +#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOD))? 3U : 7U) +#endif /* STM32F412Rx */ +#if defined(STM32F412Cx) +#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U : 7U) +#endif /* STM32F412Cx */ + +/** + * @} + */ + +/** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function + * @{ + */ +/*------------------------- STM32F429xx/STM32F439xx---------------------------*/ +#if defined(STM32F429xx) || defined(STM32F439xx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ + ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ + ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \ + ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \ + ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ + ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \ + ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \ + ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ + ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \ + ((AF) == GPIO_AF11_ETH) || ((AF) == GPIO_AF12_OTG_HS_FS) || \ + ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF13_DCMI) || \ + ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF5_SPI4) || \ + ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \ + ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \ + ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF6_SAI1) || \ + ((AF) == GPIO_AF14_LTDC)) + +#endif /* STM32F429xx || STM32F439xx */ +/*----------------------------------------------------------------------------*/ + +/*---------------------------------- STM32F427xx/STM32F437xx------------------*/ +#if defined(STM32F427xx) || defined(STM32F437xx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ + ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ + ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \ + ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \ + ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ + ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \ + ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \ + ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ + ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \ + ((AF) == GPIO_AF11_ETH) || ((AF) == GPIO_AF12_OTG_HS_FS) || \ + ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF13_DCMI) || \ + ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF5_SPI4) || \ + ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \ + ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \ + ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF6_SAI1)) + +#endif /* STM32F427xx || STM32F437xx */ +/*----------------------------------------------------------------------------*/ + +/*---------------------------------- STM32F407xx/STM32F417xx------------------*/ +#if defined(STM32F407xx) || defined(STM32F417xx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ + ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ + ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \ + ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \ + ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ + ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \ + ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \ + ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ + ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \ + ((AF) == GPIO_AF11_ETH) || ((AF) == GPIO_AF12_OTG_HS_FS) || \ + ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF13_DCMI) || \ + ((AF) == GPIO_AF12_FSMC) || ((AF) == GPIO_AF15_EVENTOUT)) + +#endif /* STM32F407xx || STM32F417xx */ +/*----------------------------------------------------------------------------*/ + +/*---------------------------------- STM32F405xx/STM32F415xx------------------*/ +#if defined(STM32F405xx) || defined(STM32F415xx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ + ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ + ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \ + ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \ + ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ + ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \ + ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \ + ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ + ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \ + ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDIO) || \ + ((AF) == GPIO_AF12_FSMC) || ((AF) == GPIO_AF15_EVENTOUT)) + +#endif /* STM32F405xx || STM32F415xx */ + +/*----------------------------------------------------------------------------*/ + +/*---------------------------------------- STM32F401xx------------------------*/ +#if defined(STM32F401xC) || defined(STM32F401xE) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF12_SDIO) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF4_I2C1) || \ + ((AF) == GPIO_AF4_I2C2) || ((AF) == GPIO_AF4_I2C3) || \ + ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF5_SPI4) || \ + ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ + ((AF) == GPIO_AF8_USART6) || ((AF) == GPIO_AF10_OTG_FS) || \ + ((AF) == GPIO_AF9_I2C2) || ((AF) == GPIO_AF9_I2C3) || \ + ((AF) == GPIO_AF15_EVENTOUT)) + +#endif /* STM32F401xC || STM32F401xE */ +/*----------------------------------------------------------------------------*/ +/*---------------------------------------- STM32F410xx------------------------*/ +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +#define IS_GPIO_AF(AF) (((AF) < 10U) || ((AF) == 15U)) +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + +/*---------------------------------------- STM32F411xx------------------------*/ +#if defined(STM32F411xE) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF4_I2C1) || \ + ((AF) == GPIO_AF4_I2C2) || ((AF) == GPIO_AF4_I2C3) || \ + ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \ + ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF6_SPI4) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF5_SPI4) || \ + ((AF) == GPIO_AF6_SPI5) || ((AF) == GPIO_AF7_SPI3) || \ + ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ + ((AF) == GPIO_AF8_USART6) || ((AF) == GPIO_AF10_OTG_FS) || \ + ((AF) == GPIO_AF9_I2C2) || ((AF) == GPIO_AF9_I2C3) || \ + ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF15_EVENTOUT)) + +#endif /* STM32F411xE */ +/*----------------------------------------------------------------------------*/ + +/*----------------------------------------------- STM32F446xx ----------------*/ +#if defined(STM32F446xx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ + ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ + ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \ + ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \ + ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ + ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \ + ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \ + ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ + ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \ + ((AF) == GPIO_AF11_ETH) || ((AF) == GPIO_AF12_OTG_HS_FS) || \ + ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF13_DCMI) || \ + ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF5_SPI4) || \ + ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF6_SAI1) || \ + ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \ + ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF6_SPI2) || \ + ((AF) == GPIO_AF6_SPI4) || ((AF) == GPIO_AF7_UART5) || \ + ((AF) == GPIO_AF7_SPI2) || ((AF) == GPIO_AF7_SPI3) || \ + ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \ + ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF9_QSPI) || \ + ((AF) == GPIO_AF10_SAI2) || ((AF) == GPIO_AF10_QSPI)) + +#endif /* STM32F446xx */ +/*----------------------------------------------------------------------------*/ + +/*------------------------------------------- STM32F469xx/STM32F479xx --------*/ +#if defined(STM32F469xx) || defined(STM32F479xx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ + ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ + ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \ + ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \ + ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ + ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \ + ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \ + ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ + ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \ + ((AF) == GPIO_AF11_ETH) || ((AF) == GPIO_AF12_OTG_HS_FS) || \ + ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF13_DCMI) || \ + ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF5_SPI4) || \ + ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \ + ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \ + ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF6_SAI1) || \ + ((AF) == GPIO_AF14_LTDC) || ((AF) == GPIO_AF13_DSI) || \ + ((AF) == GPIO_AF9_QSPI) || ((AF) == GPIO_AF10_QSPI)) + +#endif /* STM32F469xx || STM32F479xx */ +/*----------------------------------------------------------------------------*/ + +/*------------------STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx-----------*/ +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) +#define IS_GPIO_AF(AF) (((AF) < 16U) && ((AF) != 11U) && ((AF) != 14U) && ((AF) != 13U)) +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ +/*----------------------------------------------------------------------------*/ + +/*------------------STM32F413xx/STM32F423xx-----------------------------------*/ +#if defined(STM32F413xx) || defined(STM32F423xx) +#define IS_GPIO_AF(AF) (((AF) < 16U) && ((AF) != 13U)) +#endif /* STM32F413xx || STM32F423xx */ +/*----------------------------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup GPIOEx_Private_Functions GPIO Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_GPIO_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hcd.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hcd.h new file mode 100644 index 0000000..30c11f2 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hcd.h @@ -0,0 +1,321 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_hcd.h + * @author MCD Application Team + * @brief Header file of HCD HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F4xx_HAL_HCD_H +#define STM32F4xx_HAL_HCD_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_ll_usb.h" + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup HCD + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup HCD_Exported_Types HCD Exported Types + * @{ + */ + +/** @defgroup HCD_Exported_Types_Group1 HCD State Structure definition + * @{ + */ +typedef enum +{ + HAL_HCD_STATE_RESET = 0x00, + HAL_HCD_STATE_READY = 0x01, + HAL_HCD_STATE_ERROR = 0x02, + HAL_HCD_STATE_BUSY = 0x03, + HAL_HCD_STATE_TIMEOUT = 0x04 +} HCD_StateTypeDef; + +typedef USB_OTG_GlobalTypeDef HCD_TypeDef; +typedef USB_OTG_CfgTypeDef HCD_InitTypeDef; +typedef USB_OTG_HCTypeDef HCD_HCTypeDef; +typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef; +typedef USB_OTG_HCStateTypeDef HCD_HCStateTypeDef; +/** + * @} + */ + +/** @defgroup HCD_Exported_Types_Group2 HCD Handle Structure definition + * @{ + */ +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) +typedef struct __HCD_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ +{ + HCD_TypeDef *Instance; /*!< Register base address */ + HCD_InitTypeDef Init; /*!< HCD required parameters */ + HCD_HCTypeDef hc[16]; /*!< Host channels parameters */ + HAL_LockTypeDef Lock; /*!< HCD peripheral status */ + __IO HCD_StateTypeDef State; /*!< HCD communication state */ + __IO uint32_t ErrorCode; /*!< HCD Error code */ + void *pData; /*!< Pointer Stack Handler */ +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + void (* SOFCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD SOF callback */ + void (* ConnectCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Connect callback */ + void (* DisconnectCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Disconnect callback */ + void (* PortEnabledCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Port Enable callback */ + void (* PortDisabledCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Port Disable callback */ + void (* HC_NotifyURBChangeCallback)(struct __HCD_HandleTypeDef *hhcd, uint8_t chnum, + HCD_URBStateTypeDef urb_state); /*!< USB OTG HCD Host Channel Notify URB Change callback */ + + void (* MspInitCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Msp Init callback */ + void (* MspDeInitCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Msp DeInit callback */ +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ +} HCD_HandleTypeDef; +/** + * @} + */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup HCD_Exported_Constants HCD Exported Constants + * @{ + */ + +/** @defgroup HCD_Speed HCD Speed + * @{ + */ +#define HCD_SPEED_HIGH USBH_HS_SPEED +#define HCD_SPEED_FULL USBH_FSLS_SPEED +#define HCD_SPEED_LOW USBH_FSLS_SPEED + +/** + * @} + */ + +/** @defgroup HCD_PHY_Module HCD PHY Module + * @{ + */ +#define HCD_PHY_ULPI 1U +#define HCD_PHY_EMBEDDED 2U +/** + * @} + */ + +/** @defgroup HCD_Error_Code_definition HCD Error Code definition + * @brief HCD Error Code definition + * @{ + */ +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) +#define HAL_HCD_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */ +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup HCD_Exported_Macros HCD Exported Macros + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ +#define __HAL_HCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) +#define __HAL_HCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) + +#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) +#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__)) +#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U) + +#define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__)) +#define __HAL_HCD_MASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM) +#define __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM) +#define __HAL_HCD_MASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM) +#define __HAL_HCD_UNMASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup HCD_Exported_Functions HCD Exported Functions + * @{ + */ + +/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd); +HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd); +HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, + uint8_t epnum, uint8_t dev_address, + uint8_t speed, uint8_t ep_type, uint16_t mps); + +HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num); +void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd); +void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd); + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) +/** @defgroup HAL_HCD_Callback_ID_enumeration_definition HAL USB OTG HCD Callback ID enumeration definition + * @brief HAL USB OTG HCD Callback ID enumeration definition + * @{ + */ +typedef enum +{ + HAL_HCD_SOF_CB_ID = 0x01, /*!< USB HCD SOF callback ID */ + HAL_HCD_CONNECT_CB_ID = 0x02, /*!< USB HCD Connect callback ID */ + HAL_HCD_DISCONNECT_CB_ID = 0x03, /*!< USB HCD Disconnect callback ID */ + HAL_HCD_PORT_ENABLED_CB_ID = 0x04, /*!< USB HCD Port Enable callback ID */ + HAL_HCD_PORT_DISABLED_CB_ID = 0x05, /*!< USB HCD Port Disable callback ID */ + + HAL_HCD_MSPINIT_CB_ID = 0x06, /*!< USB HCD MspInit callback ID */ + HAL_HCD_MSPDEINIT_CB_ID = 0x07 /*!< USB HCD MspDeInit callback ID */ + +} HAL_HCD_CallbackIDTypeDef; +/** + * @} + */ + +/** @defgroup HAL_HCD_Callback_pointer_definition HAL USB OTG HCD Callback pointer definition + * @brief HAL USB OTG HCD Callback pointer definition + * @{ + */ + +typedef void (*pHCD_CallbackTypeDef)(HCD_HandleTypeDef *hhcd); /*!< pointer to a common USB OTG HCD callback function */ +typedef void (*pHCD_HC_NotifyURBChangeCallbackTypeDef)(HCD_HandleTypeDef *hhcd, + uint8_t epnum, + HCD_URBStateTypeDef urb_state); /*!< pointer to USB OTG HCD host channel callback */ +/** + * @} + */ + +HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, + HAL_HCD_CallbackIDTypeDef CallbackID, + pHCD_CallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, + HAL_HCD_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd, + pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* I/O operation functions ***************************************************/ +/** @addtogroup HCD_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ +HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint8_t ch_num, + uint8_t direction, uint8_t ep_type, + uint8_t token, uint8_t *pbuff, + uint16_t length, uint8_t do_ping); + +/* Non-Blocking mode: Interrupt */ +void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd); +void HAL_HCD_WKUP_IRQHandler(HCD_HandleTypeDef *hhcd); +void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd); +void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd); +void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd); +void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd); +void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd); +void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, + HCD_URBStateTypeDef urb_state); +/** + * @} + */ + +/* Peripheral Control functions **********************************************/ +/** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions + * @{ + */ +HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd); +HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd); +HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd); +/** + * @} + */ +/** + * @} + */ + +/* Peripheral State functions ************************************************/ +/** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions + * @{ + */ +HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd); +HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum); +HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum); +uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum); +uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd); +uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd); + +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup HCD_Private_Macros HCD Private Macros + * @{ + */ +/** + * @} + */ +/* Private functions prototypes ----------------------------------------------*/ +/** @defgroup HCD_Private_Functions_Prototypes HCD Private Functions Prototypes + * @{ + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup HCD_Private_Functions HCD Private Functions + * @{ + */ + +/** + * @} + */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F4xx_HAL_HCD_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h new file mode 100644 index 0000000..ff57655 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h @@ -0,0 +1,743 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_i2c.h + * @author MCD Application Team + * @brief Header file of I2C HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_I2C_H +#define __STM32F4xx_HAL_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup I2C_Exported_Types I2C Exported Types + * @{ + */ + +/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition + * @brief I2C Configuration Structure definition + * @{ + */ +typedef struct +{ + uint32_t ClockSpeed; /*!< Specifies the clock frequency. + This parameter must be set to a value lower than 400kHz */ + + uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle. + This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ + + uint32_t OwnAddress1; /*!< Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected. + This parameter can be a value of @ref I2C_addressing_mode */ + + uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. + This parameter can be a value of @ref I2C_dual_addressing_mode */ + + uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected + This parameter can be a 7-bit address. */ + + uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. + This parameter can be a value of @ref I2C_general_call_addressing_mode */ + + uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. + This parameter can be a value of @ref I2C_nostretch_mode */ + +} I2C_InitTypeDef; + +/** + * @} + */ + +/** @defgroup HAL_state_structure_definition HAL state structure definition + * @brief HAL State structure definition + * @note HAL I2C State value coding follow below described bitmap : + * b7-b6 Error information + * 00 : No Error + * 01 : Abort (Abort user request on going) + * 10 : Timeout + * 11 : Error + * b5 Peripheral initilisation status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral initialized and ready to use. HAL I2C Init function called) + * b4 (not used) + * x : Should be set to 0 + * b3 + * 0 : Ready or Busy (No Listen mode ongoing) + * 1 : Listen (Peripheral in Address Listen Mode) + * b2 Intrinsic process state + * 0 : Ready + * 1 : Busy (Peripheral busy with some configuration or internal operations) + * b1 Rx state + * 0 : Ready (no Rx operation ongoing) + * 1 : Busy (Rx operation ongoing) + * b0 Tx state + * 0 : Ready (no Tx operation ongoing) + * 1 : Busy (Tx operation ongoing) + * @{ + */ +typedef enum +{ + HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ + HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */ + HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */ + HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ + HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ + HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */ + HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission + process is ongoing */ + HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception + process is ongoing */ + HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ + HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ + HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ + +} HAL_I2C_StateTypeDef; + +/** + * @} + */ + +/** @defgroup HAL_mode_structure_definition HAL mode structure definition + * @brief HAL Mode structure definition + * @note HAL I2C Mode value coding follow below described bitmap :\n + * b7 (not used)\n + * x : Should be set to 0\n + * b6\n + * 0 : None\n + * 1 : Memory (HAL I2C communication is in Memory Mode)\n + * b5\n + * 0 : None\n + * 1 : Slave (HAL I2C communication is in Slave Mode)\n + * b4\n + * 0 : None\n + * 1 : Master (HAL I2C communication is in Master Mode)\n + * b3-b2-b1-b0 (not used)\n + * xxxx : Should be set to 0000 + * @{ + */ +typedef enum +{ + HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */ + HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */ + HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */ + HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */ + +} HAL_I2C_ModeTypeDef; + +/** + * @} + */ + +/** @defgroup I2C_Error_Code_definition I2C Error Code definition + * @brief I2C Error Code definition + * @{ + */ +#define HAL_I2C_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_I2C_ERROR_BERR 0x00000001U /*!< BERR error */ +#define HAL_I2C_ERROR_ARLO 0x00000002U /*!< ARLO error */ +#define HAL_I2C_ERROR_AF 0x00000004U /*!< AF error */ +#define HAL_I2C_ERROR_OVR 0x00000008U /*!< OVR error */ +#define HAL_I2C_ERROR_DMA 0x00000010U /*!< DMA transfer error */ +#define HAL_I2C_ERROR_TIMEOUT 0x00000020U /*!< Timeout Error */ +#define HAL_I2C_ERROR_SIZE 0x00000040U /*!< Size Management error */ +#define HAL_I2C_ERROR_DMA_PARAM 0x00000080U /*!< DMA Parameter Error */ +#define HAL_I2C_WRONG_START 0x00000200U /*!< Wrong start Error */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +#define HAL_I2C_ERROR_INVALID_CALLBACK 0x00000100U /*!< Invalid Callback error */ +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition + * @brief I2C handle Structure definition + * @{ + */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +typedef struct __I2C_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +{ + I2C_TypeDef *Instance; /*!< I2C registers base address */ + + I2C_InitTypeDef Init; /*!< I2C communication parameters */ + + uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */ + + uint16_t XferSize; /*!< I2C transfer size */ + + __IO uint16_t XferCount; /*!< I2C transfer counter */ + + __IO uint32_t XferOptions; /*!< I2C transfer options */ + + __IO uint32_t PreviousState; /*!< I2C communication Previous state and mode + context for internal usage */ + + DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ + + HAL_LockTypeDef Lock; /*!< I2C locking object */ + + __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ + + __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */ + + __IO uint32_t ErrorCode; /*!< I2C Error code */ + + __IO uint32_t Devaddress; /*!< I2C Target device address */ + + __IO uint32_t Memaddress; /*!< I2C Target memory address */ + + __IO uint32_t MemaddSize; /*!< I2C Target memory address size */ + + __IO uint32_t EventCount; /*!< I2C Event counter */ + + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Tx Transfer completed callback */ + void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Rx Transfer completed callback */ + void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Tx Transfer completed callback */ + void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Rx Transfer completed callback */ + void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Listen Complete callback */ + void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Tx Transfer completed callback */ + void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Rx Transfer completed callback */ + void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Error callback */ + void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Abort callback */ + + void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< I2C Slave Address Match callback */ + + void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp Init callback */ + void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp DeInit callback */ + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +} I2C_HandleTypeDef; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +/** + * @brief HAL I2C Callback ID enumeration definition + */ +typedef enum +{ + HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */ + HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */ + HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */ + HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */ + HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */ + HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */ + HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */ + HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */ + HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */ + + HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */ + HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */ + +} HAL_I2C_CallbackIDTypeDef; + +/** + * @brief HAL I2C Callback pointer definition + */ +typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */ +typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */ + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** + * @} + */ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Constants I2C Exported Constants + * @{ + */ + +/** @defgroup I2C_duty_cycle_in_fast_mode I2C duty cycle in fast mode + * @{ + */ +#define I2C_DUTYCYCLE_2 0x00000000U +#define I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY +/** + * @} + */ + +/** @defgroup I2C_addressing_mode I2C addressing mode + * @{ + */ +#define I2C_ADDRESSINGMODE_7BIT 0x00004000U +#define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | 0x00004000U) +/** + * @} + */ + +/** @defgroup I2C_dual_addressing_mode I2C dual addressing mode + * @{ + */ +#define I2C_DUALADDRESS_DISABLE 0x00000000U +#define I2C_DUALADDRESS_ENABLE I2C_OAR2_ENDUAL +/** + * @} + */ + +/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode + * @{ + */ +#define I2C_GENERALCALL_DISABLE 0x00000000U +#define I2C_GENERALCALL_ENABLE I2C_CR1_ENGC +/** + * @} + */ + +/** @defgroup I2C_nostretch_mode I2C nostretch mode + * @{ + */ +#define I2C_NOSTRETCH_DISABLE 0x00000000U +#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH +/** + * @} + */ + +/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size + * @{ + */ +#define I2C_MEMADD_SIZE_8BIT 0x00000001U +#define I2C_MEMADD_SIZE_16BIT 0x00000010U +/** + * @} + */ + +/** @defgroup I2C_XferDirection_definition I2C XferDirection definition + * @{ + */ +#define I2C_DIRECTION_RECEIVE 0x00000000U +#define I2C_DIRECTION_TRANSMIT 0x00000001U +/** + * @} + */ + +/** @defgroup I2C_XferOptions_definition I2C XferOptions definition + * @{ + */ +#define I2C_FIRST_FRAME 0x00000001U +#define I2C_FIRST_AND_NEXT_FRAME 0x00000002U +#define I2C_NEXT_FRAME 0x00000004U +#define I2C_FIRST_AND_LAST_FRAME 0x00000008U +#define I2C_LAST_FRAME_NO_STOP 0x00000010U +#define I2C_LAST_FRAME 0x00000020U + +/* List of XferOptions in usage of : + * 1- Restart condition in all use cases (direction change or not) + */ +#define I2C_OTHER_FRAME (0x00AA0000U) +#define I2C_OTHER_AND_LAST_FRAME (0xAA000000U) +/** + * @} + */ + +/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition + * @brief I2C Interrupt definition + * Elements values convention: 0xXXXXXXXX + * - XXXXXXXX : Interrupt control mask + * @{ + */ +#define I2C_IT_BUF I2C_CR2_ITBUFEN +#define I2C_IT_EVT I2C_CR2_ITEVTEN +#define I2C_IT_ERR I2C_CR2_ITERREN +/** + * @} + */ + +/** @defgroup I2C_Flag_definition I2C Flag definition + * @{ + */ + +#define I2C_FLAG_OVR 0x00010800U +#define I2C_FLAG_AF 0x00010400U +#define I2C_FLAG_ARLO 0x00010200U +#define I2C_FLAG_BERR 0x00010100U +#define I2C_FLAG_TXE 0x00010080U +#define I2C_FLAG_RXNE 0x00010040U +#define I2C_FLAG_STOPF 0x00010010U +#define I2C_FLAG_ADD10 0x00010008U +#define I2C_FLAG_BTF 0x00010004U +#define I2C_FLAG_ADDR 0x00010002U +#define I2C_FLAG_SB 0x00010001U +#define I2C_FLAG_DUALF 0x00100080U +#define I2C_FLAG_GENCALL 0x00100010U +#define I2C_FLAG_TRA 0x00100004U +#define I2C_FLAG_BUSY 0x00100002U +#define I2C_FLAG_MSL 0x00100001U +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Macros I2C Exported Macros + * @{ + */ + +/** @brief Reset I2C handle state. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_I2C_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) +#endif + +/** @brief Enable or disable the specified I2C interrupts. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable or disable. + * This parameter can be one of the following values: + * @arg I2C_IT_BUF: Buffer interrupt enable + * @arg I2C_IT_EVT: Event interrupt enable + * @arg I2C_IT_ERR: Error interrupt enable + * @retval None + */ +#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)) +#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) + +/** @brief Checks if the specified I2C interrupt source is enabled or disabled. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the I2C interrupt source to check. + * This parameter can be one of the following values: + * @arg I2C_IT_BUF: Buffer interrupt enable + * @arg I2C_IT_EVT: Event interrupt enable + * @arg I2C_IT_ERR: Error interrupt enable + * @retval The new state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Checks whether the specified I2C flag is set or not. + * @param __HANDLE__ specifies the I2C Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg I2C_FLAG_OVR: Overrun/Underrun flag + * @arg I2C_FLAG_AF: Acknowledge failure flag + * @arg I2C_FLAG_ARLO: Arbitration lost flag + * @arg I2C_FLAG_BERR: Bus error flag + * @arg I2C_FLAG_TXE: Data register empty flag + * @arg I2C_FLAG_RXNE: Data register not empty flag + * @arg I2C_FLAG_STOPF: Stop detection flag + * @arg I2C_FLAG_ADD10: 10-bit header sent flag + * @arg I2C_FLAG_BTF: Byte transfer finished flag + * @arg I2C_FLAG_ADDR: Address sent flag + * Address matched flag + * @arg I2C_FLAG_SB: Start bit flag + * @arg I2C_FLAG_DUALF: Dual flag + * @arg I2C_FLAG_GENCALL: General call header flag + * @arg I2C_FLAG_TRA: Transmitter/Receiver flag + * @arg I2C_FLAG_BUSY: Bus busy flag + * @arg I2C_FLAG_MSL: Master/Slave flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16U)) == 0x01U) ? \ + (((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) : \ + (((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)) + +/** @brief Clears the I2C pending flags which are cleared by writing 0 in a specific bit. + * @param __HANDLE__ specifies the I2C Handle. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) + * @arg I2C_FLAG_AF: Acknowledge failure flag + * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) + * @arg I2C_FLAG_BERR: Bus error flag + * @retval None + */ +#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & I2C_FLAG_MASK)) + +/** @brief Clears the I2C ADDR pending flag. + * @param __HANDLE__ specifies the I2C Handle. + * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. + * @retval None + */ +#define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg = 0x00U; \ + tmpreg = (__HANDLE__)->Instance->SR1; \ + tmpreg = (__HANDLE__)->Instance->SR2; \ + UNUSED(tmpreg); \ + } while(0) + +/** @brief Clears the I2C STOPF pending flag. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg = 0x00U; \ + tmpreg = (__HANDLE__)->Instance->SR1; \ + SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE); \ + UNUSED(tmpreg); \ + } while(0) + +/** @brief Enable the specified I2C peripheral. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE) + +/** @brief Disable the specified I2C peripheral. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE) + +/** + * @} + */ + +/* Include I2C HAL Extension module */ +#include "stm32f4xx_hal_i2c_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2C_Exported_Functions + * @{ + */ + +/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +/* Initialization and de-initialization functions******************************/ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ +/* IO operation functions ****************************************************/ +/******* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); + +/******* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); + +/******* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +/** + * @} + */ + +/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ +/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); +void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); +void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions + * @{ + */ +/* Peripheral State, Mode and Error functions *********************************/ +HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c); +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c); +uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); + +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Constants I2C Private Constants + * @{ + */ +#define I2C_FLAG_MASK 0x0000FFFFU +#define I2C_MIN_PCLK_FREQ_STANDARD 2000000U /*!< 2 MHz */ +#define I2C_MIN_PCLK_FREQ_FAST 4000000U /*!< 4 MHz */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2C_Private_Macros I2C Private Macros + * @{ + */ + +#define I2C_MIN_PCLK_FREQ(__PCLK__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__PCLK__) < I2C_MIN_PCLK_FREQ_STANDARD) : ((__PCLK__) < I2C_MIN_PCLK_FREQ_FAST)) +#define I2C_CCR_CALCULATION(__PCLK__, __SPEED__, __COEFF__) (((((__PCLK__) - 1U)/((__SPEED__) * (__COEFF__))) + 1U) & I2C_CCR_CCR) +#define I2C_FREQRANGE(__PCLK__) ((__PCLK__)/1000000U) +#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U)) +#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__) ((I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U) < 4U)? 4U:I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U)) +#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 3U) : (I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 25U) | I2C_DUTYCYCLE_16_9)) +#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__SPEED__) <= 100000U)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \ + ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U)? 1U : \ + ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS)) + +#define I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (uint8_t)(~I2C_OAR1_ADD0))) +#define I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0)) + +#define I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF))) +#define I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)0x00F0))) +#define I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)(0x00F1)))) + +#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0xFF00)) >> 8))) +#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF))) + +/** @defgroup I2C_IS_RTC_Definitions I2C Private macros to check input parameters + * @{ + */ +#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \ + ((CYCLE) == I2C_DUTYCYCLE_16_9)) +#define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \ + ((ADDRESS) == I2C_ADDRESSINGMODE_10BIT)) +#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \ + ((ADDRESS) == I2C_DUALADDRESS_ENABLE)) +#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \ + ((CALL) == I2C_GENERALCALL_ENABLE)) +#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \ + ((STRETCH) == I2C_NOSTRETCH_ENABLE)) +#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ + ((SIZE) == I2C_MEMADD_SIZE_16BIT)) +#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0U) && ((SPEED) <= 400000U)) +#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & 0xFFFFFC00U) == 0U) +#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & 0xFFFFFF01U) == 0U) +#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \ + ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \ + ((REQUEST) == I2C_NEXT_FRAME) || \ + ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \ + ((REQUEST) == I2C_LAST_FRAME) || \ + ((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \ + IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)) + +#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \ + ((REQUEST) == I2C_OTHER_AND_LAST_FRAME)) + +#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) +#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Functions I2C Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F4xx_HAL_I2C_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h new file mode 100644 index 0000000..6864d83 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h @@ -0,0 +1,117 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_i2c_ex.h + * @author MCD Application Team + * @brief Header file of I2C HAL Extension module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_I2C_EX_H +#define __STM32F4xx_HAL_I2C_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF) +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup I2CEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2CEx_Exported_Constants I2C Exported Constants + * @{ + */ + +/** @defgroup I2CEx_Analog_Filter I2C Analog Filter + * @{ + */ +#define I2C_ANALOGFILTER_ENABLE 0x00000000U +#define I2C_ANALOGFILTER_DISABLE I2C_FLTR_ANOFF +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2CEx_Exported_Functions + * @{ + */ + +/** @addtogroup I2CEx_Exported_Functions_Group1 + * @{ + */ +/* Peripheral Control functions ************************************************/ +HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); +HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Constants I2C Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Macros I2C Private Macros + * @{ + */ +#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ + ((FILTER) == I2C_ANALOGFILTER_DISABLE)) +#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_I2C_EX_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s.h new file mode 100644 index 0000000..203ffc1 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s.h @@ -0,0 +1,620 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_i2s.h + * @author MCD Application Team + * @brief Header file of I2S HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F4xx_HAL_I2S_H +#define STM32F4xx_HAL_I2S_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup I2S + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup I2S_Exported_Types I2S Exported Types + * @{ + */ + +/** + * @brief I2S Init structure definition + */ +typedef struct +{ + uint32_t Mode; /*!< Specifies the I2S operating mode. + This parameter can be a value of @ref I2S_Mode */ + + uint32_t Standard; /*!< Specifies the standard used for the I2S communication. + This parameter can be a value of @ref I2S_Standard */ + + uint32_t DataFormat; /*!< Specifies the data format for the I2S communication. + This parameter can be a value of @ref I2S_Data_Format */ + + uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. + This parameter can be a value of @ref I2S_MCLK_Output */ + + uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication. + This parameter can be a value of @ref I2S_Audio_Frequency */ + + uint32_t CPOL; /*!< Specifies the idle state of the I2S clock. + This parameter can be a value of @ref I2S_Clock_Polarity */ + + uint32_t ClockSource; /*!< Specifies the I2S Clock Source. + This parameter can be a value of @ref I2S_Clock_Source */ + uint32_t FullDuplexMode; /*!< Specifies the I2S FullDuplex mode. + This parameter can be a value of @ref I2S_FullDuplex_Mode */ +} I2S_InitTypeDef; + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_I2S_STATE_RESET = 0x00U, /*!< I2S not yet initialized or disabled */ + HAL_I2S_STATE_READY = 0x01U, /*!< I2S initialized and ready for use */ + HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */ + HAL_I2S_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */ + HAL_I2S_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */ + HAL_I2S_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */ + HAL_I2S_STATE_TIMEOUT = 0x06U, /*!< I2S timeout state */ + HAL_I2S_STATE_ERROR = 0x07U /*!< I2S error state */ +} HAL_I2S_StateTypeDef; + +/** + * @brief I2S handle Structure definition + */ +typedef struct __I2S_HandleTypeDef +{ + SPI_TypeDef *Instance; /*!< I2S registers base address */ + + I2S_InitTypeDef Init; /*!< I2S communication parameters */ + + uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */ + + __IO uint16_t TxXferSize; /*!< I2S Tx transfer size */ + + __IO uint16_t TxXferCount; /*!< I2S Tx transfer Counter */ + + uint16_t *pRxBuffPtr; /*!< Pointer to I2S Rx transfer buffer */ + + __IO uint16_t RxXferSize; /*!< I2S Rx transfer size */ + + __IO uint16_t RxXferCount; /*!< I2S Rx transfer counter + (This field is initialized at the + same value as transfer size at the + beginning of the transfer and + decremented when a sample is received + NbSamplesReceived = RxBufferSize-RxBufferCount) */ + void (*IrqHandlerISR)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S function pointer on IrqHandler */ + + DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */ + + __IO HAL_LockTypeDef Lock; /*!< I2S locking object */ + + __IO HAL_I2S_StateTypeDef State; /*!< I2S communication state */ + + __IO uint32_t ErrorCode; /*!< I2S Error code + This parameter can be a value of @ref I2S_Error */ + +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + void (* TxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Completed callback */ + void (* RxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Completed callback */ + void (* TxRxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S TxRx Completed callback */ + void (* TxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Half Completed callback */ + void (* RxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Half Completed callback */ + void (* TxRxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S TxRx Half Completed callback */ + void (* ErrorCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Error callback */ + void (* MspInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp Init callback */ + void (* MspDeInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp DeInit callback */ + +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +} I2S_HandleTypeDef; + +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) +/** + * @brief HAL I2S Callback ID enumeration definition + */ +typedef enum +{ + HAL_I2S_TX_COMPLETE_CB_ID = 0x00U, /*!< I2S Tx Completed callback ID */ + HAL_I2S_RX_COMPLETE_CB_ID = 0x01U, /*!< I2S Rx Completed callback ID */ + HAL_I2S_TX_RX_COMPLETE_CB_ID = 0x02U, /*!< I2S TxRx Completed callback ID */ + HAL_I2S_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< I2S Tx Half Completed callback ID */ + HAL_I2S_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< I2S Rx Half Completed callback ID */ + HAL_I2S_TX_RX_HALF_COMPLETE_CB_ID = 0x05U, /*!< I2S TxRx Half Completed callback ID */ + HAL_I2S_ERROR_CB_ID = 0x06U, /*!< I2S Error callback ID */ + HAL_I2S_MSPINIT_CB_ID = 0x07U, /*!< I2S Msp Init callback ID */ + HAL_I2S_MSPDEINIT_CB_ID = 0x08U /*!< I2S Msp DeInit callback ID */ + +} HAL_I2S_CallbackIDTypeDef; + +/** + * @brief HAL I2S Callback pointer definition + */ +typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to an I2S callback function */ + +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2S_Exported_Constants I2S Exported Constants + * @{ + */ +/** @defgroup I2S_Error I2S Error + * @{ + */ +#define HAL_I2S_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_I2S_ERROR_TIMEOUT (0x00000001U) /*!< Timeout error */ +#define HAL_I2S_ERROR_OVR (0x00000002U) /*!< OVR error */ +#define HAL_I2S_ERROR_UDR (0x00000004U) /*!< UDR error */ +#define HAL_I2S_ERROR_DMA (0x00000008U) /*!< DMA transfer error */ +#define HAL_I2S_ERROR_PRESCALER (0x00000010U) /*!< Prescaler Calculation error */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) +#define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000020U) /*!< Invalid Callback error */ +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +#define HAL_I2S_ERROR_BUSY_LINE_RX (0x00000040U) /*!< Busy Rx Line error */ +/** + * @} + */ + +/** @defgroup I2S_Mode I2S Mode + * @{ + */ +#define I2S_MODE_SLAVE_TX (0x00000000U) +#define I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) +#define I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) +#define I2S_MODE_MASTER_RX ((SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1)) +/** + * @} + */ + +/** @defgroup I2S_Standard I2S Standard + * @{ + */ +#define I2S_STANDARD_PHILIPS (0x00000000U) +#define I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) +#define I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) +#define I2S_STANDARD_PCM_SHORT ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)) +#define I2S_STANDARD_PCM_LONG ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC)) +/** + * @} + */ + +/** @defgroup I2S_Data_Format I2S Data Format + * @{ + */ +#define I2S_DATAFORMAT_16B (0x00000000U) +#define I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) +#define I2S_DATAFORMAT_24B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)) +#define I2S_DATAFORMAT_32B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)) +/** + * @} + */ + +/** @defgroup I2S_MCLK_Output I2S MCLK Output + * @{ + */ +#define I2S_MCLKOUTPUT_ENABLE (SPI_I2SPR_MCKOE) +#define I2S_MCLKOUTPUT_DISABLE (0x00000000U) +/** + * @} + */ + +/** @defgroup I2S_Audio_Frequency I2S Audio Frequency + * @{ + */ +#define I2S_AUDIOFREQ_192K (192000U) +#define I2S_AUDIOFREQ_96K (96000U) +#define I2S_AUDIOFREQ_48K (48000U) +#define I2S_AUDIOFREQ_44K (44100U) +#define I2S_AUDIOFREQ_32K (32000U) +#define I2S_AUDIOFREQ_22K (22050U) +#define I2S_AUDIOFREQ_16K (16000U) +#define I2S_AUDIOFREQ_11K (11025U) +#define I2S_AUDIOFREQ_8K (8000U) +#define I2S_AUDIOFREQ_DEFAULT (2U) +/** + * @} + */ + +/** @defgroup I2S_FullDuplex_Mode I2S FullDuplex Mode + * @{ + */ +#define I2S_FULLDUPLEXMODE_DISABLE (0x00000000U) +#define I2S_FULLDUPLEXMODE_ENABLE (0x00000001U) +/** + * @} + */ + +/** @defgroup I2S_Clock_Polarity I2S Clock Polarity + * @{ + */ +#define I2S_CPOL_LOW (0x00000000U) +#define I2S_CPOL_HIGH (SPI_I2SCFGR_CKPOL) +/** + * @} + */ + +/** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition + * @{ + */ +#define I2S_IT_TXE SPI_CR2_TXEIE +#define I2S_IT_RXNE SPI_CR2_RXNEIE +#define I2S_IT_ERR SPI_CR2_ERRIE +/** + * @} + */ + +/** @defgroup I2S_Flags_Definition I2S Flags Definition + * @{ + */ +#define I2S_FLAG_TXE SPI_SR_TXE +#define I2S_FLAG_RXNE SPI_SR_RXNE + +#define I2S_FLAG_UDR SPI_SR_UDR +#define I2S_FLAG_OVR SPI_SR_OVR +#define I2S_FLAG_FRE SPI_SR_FRE + +#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE +#define I2S_FLAG_BSY SPI_SR_BSY + +#define I2S_FLAG_MASK (SPI_SR_RXNE\ + | SPI_SR_TXE | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_CHSIDE | SPI_SR_BSY) +/** + * @} + */ + +/** @defgroup I2S_Clock_Source I2S Clock Source Definition + * @{ + */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) || defined(STM32F479xx) +#define I2S_CLOCK_PLL (0x00000000U) +#define I2S_CLOCK_EXTERNAL (0x00000001U) +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || + STM32F401xC || STM32F401xE || STM32F411xE || STM32F469xx || STM32F479xx */ + +#if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +#define I2S_CLOCK_PLL (0x00000000U) +#define I2S_CLOCK_EXTERNAL (0x00000001U) +#define I2S_CLOCK_PLLR (0x00000002U) +#define I2S_CLOCK_PLLSRC (0x00000003U) +#endif /* STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +#define I2S_CLOCK_PLLSRC (0x00000000U) +#define I2S_CLOCK_EXTERNAL (0x00000001U) +#define I2S_CLOCK_PLLR (0x00000002U) +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup I2S_Exported_macros I2S Exported Macros + * @{ + */ + +/** @brief Reset I2S handle state + * @param __HANDLE__ specifies the I2S Handle. + * @retval None + */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) +#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_I2S_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET) +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + +/** @brief Enable the specified SPI peripheral (in I2S mode). + * @param __HANDLE__ specifies the I2S Handle. + * @retval None + */ +#define __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) + +/** @brief Disable the specified SPI peripheral (in I2S mode). + * @param __HANDLE__ specifies the I2S Handle. + * @retval None + */ +#define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) + +/** @brief Enable the specified I2S interrupts. + * @param __HANDLE__ specifies the I2S Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable or disable. + * This parameter can be one of the following values: + * @arg I2S_IT_TXE: Tx buffer empty interrupt enable + * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable + * @arg I2S_IT_ERR: Error interrupt enable + * @retval None + */ +#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__))) + +/** @brief Disable the specified I2S interrupts. + * @param __HANDLE__ specifies the I2S Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable or disable. + * This parameter can be one of the following values: + * @arg I2S_IT_TXE: Tx buffer empty interrupt enable + * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable + * @arg I2S_IT_ERR: Error interrupt enable + * @retval None + */ +#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__))) + +/** @brief Checks if the specified I2S interrupt source is enabled or disabled. + * @param __HANDLE__ specifies the I2S Handle. + * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral. + * @param __INTERRUPT__ specifies the I2S interrupt source to check. + * This parameter can be one of the following values: + * @arg I2S_IT_TXE: Tx buffer empty interrupt enable + * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable + * @arg I2S_IT_ERR: Error interrupt enable + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\ + & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Checks whether the specified I2S flag is set or not. + * @param __HANDLE__ specifies the I2S Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg I2S_FLAG_RXNE: Receive buffer not empty flag + * @arg I2S_FLAG_TXE: Transmit buffer empty flag + * @arg I2S_FLAG_UDR: Underrun flag + * @arg I2S_FLAG_OVR: Overrun flag + * @arg I2S_FLAG_FRE: Frame error flag + * @arg I2S_FLAG_CHSIDE: Channel Side flag + * @arg I2S_FLAG_BSY: Busy flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) + +/** @brief Clears the I2S OVR pending flag. + * @param __HANDLE__ specifies the I2S Handle. + * @retval None + */ +#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{ \ + __IO uint32_t tmpreg_ovr = 0x00U; \ + tmpreg_ovr = (__HANDLE__)->Instance->DR; \ + tmpreg_ovr = (__HANDLE__)->Instance->SR; \ + UNUSED(tmpreg_ovr); \ + }while(0U) +/** @brief Clears the I2S UDR pending flag. + * @param __HANDLE__ specifies the I2S Handle. + * @retval None + */ +#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) do{\ + __IO uint32_t tmpreg_udr = 0x00U;\ + tmpreg_udr = ((__HANDLE__)->Instance->SR);\ + UNUSED(tmpreg_udr); \ + }while(0U) +/** @brief Flush the I2S DR Register. + * @param __HANDLE__ specifies the I2S Handle. + * @retval None + */ +#define __HAL_I2S_FLUSH_RX_DR(__HANDLE__) do{\ + __IO uint32_t tmpreg_dr = 0x00U;\ + tmpreg_dr = ((__HANDLE__)->Instance->DR);\ + UNUSED(tmpreg_dr); \ + }while(0U) +/** + * @} + */ + +/* Include I2S Extension module */ +#include "stm32f4xx_hal_i2s_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2S_Exported_Functions + * @{ + */ + +/** @addtogroup I2S_Exported_Functions_Group1 + * @{ + */ +/* Initialization/de-initialization functions ********************************/ +HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s); +HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s); +void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s); +void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) +HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, + pI2S_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup I2S_Exported_Functions_Group2 + * @{ + */ +/* I/O operation functions ***************************************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); +void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s); + +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); + +HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s); +HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s); +HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s); + +/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/ +void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s); +void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s); +void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s); +void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s); +void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s); +/** + * @} + */ + +/** @addtogroup I2S_Exported_Functions_Group3 + * @{ + */ +/* Peripheral Control and State functions ************************************/ +HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s); +uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2S_Private_Macros I2S Private Macros + * @{ + */ + +/** @brief Check whether the specified SPI flag is set or not. + * @param __SR__ copy of I2S SR regsiter. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg I2S_FLAG_RXNE: Receive buffer not empty flag + * @arg I2S_FLAG_TXE: Transmit buffer empty flag + * @arg I2S_FLAG_UDR: Underrun error flag + * @arg I2S_FLAG_OVR: Overrun flag + * @arg I2S_FLAG_CHSIDE: Channel side flag + * @arg I2S_FLAG_BSY: Busy flag + * @retval SET or RESET. + */ +#define I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__)\ + & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET) + +/** @brief Check whether the specified SPI Interrupt is set or not. + * @param __CR2__ copy of I2S CR2 regsiter. + * @param __INTERRUPT__ specifies the SPI interrupt source to check. + * This parameter can be one of the following values: + * @arg I2S_IT_TXE: Tx buffer empty interrupt enable + * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable + * @arg I2S_IT_ERR: Error interrupt enable + * @retval SET or RESET. + */ +#define I2S_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__)\ + & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Checks if I2S Mode parameter is in allowed range. + * @param __MODE__ specifies the I2S Mode. + * This parameter can be a value of @ref I2S_Mode + * @retval None + */ +#define IS_I2S_MODE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX) || \ + ((__MODE__) == I2S_MODE_SLAVE_RX) || \ + ((__MODE__) == I2S_MODE_MASTER_TX) || \ + ((__MODE__) == I2S_MODE_MASTER_RX)) + +#define IS_I2S_STANDARD(__STANDARD__) (((__STANDARD__) == I2S_STANDARD_PHILIPS) || \ + ((__STANDARD__) == I2S_STANDARD_MSB) || \ + ((__STANDARD__) == I2S_STANDARD_LSB) || \ + ((__STANDARD__) == I2S_STANDARD_PCM_SHORT) || \ + ((__STANDARD__) == I2S_STANDARD_PCM_LONG)) + +#define IS_I2S_DATA_FORMAT(__FORMAT__) (((__FORMAT__) == I2S_DATAFORMAT_16B) || \ + ((__FORMAT__) == I2S_DATAFORMAT_16B_EXTENDED) || \ + ((__FORMAT__) == I2S_DATAFORMAT_24B) || \ + ((__FORMAT__) == I2S_DATAFORMAT_32B)) + +#define IS_I2S_MCLK_OUTPUT(__OUTPUT__) (((__OUTPUT__) == I2S_MCLKOUTPUT_ENABLE) || \ + ((__OUTPUT__) == I2S_MCLKOUTPUT_DISABLE)) + +#define IS_I2S_AUDIO_FREQ(__FREQ__) ((((__FREQ__) >= I2S_AUDIOFREQ_8K) && \ + ((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \ + ((__FREQ__) == I2S_AUDIOFREQ_DEFAULT)) + +#define IS_I2S_FULLDUPLEX_MODE(MODE) (((MODE) == I2S_FULLDUPLEXMODE_DISABLE) || \ + ((MODE) == I2S_FULLDUPLEXMODE_ENABLE)) + +/** @brief Checks if I2S Serial clock steady state parameter is in allowed range. + * @param __CPOL__ specifies the I2S serial clock steady state. + * This parameter can be a value of @ref I2S_Clock_Polarity + * @retval None + */ +#define IS_I2S_CPOL(__CPOL__) (((__CPOL__) == I2S_CPOL_LOW) || \ + ((__CPOL__) == I2S_CPOL_HIGH)) + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) || defined(STM32F479xx) +#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) ||\ + ((CLOCK) == I2S_CLOCK_PLL)) +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || + STM32F401xC || STM32F401xE || STM32F411xE || STM32F469xx || STM32F479xx */ + +#if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined (STM32F413xx) || defined(STM32F423xx) +#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) ||\ + ((CLOCK) == I2S_CLOCK_PLL) ||\ + ((CLOCK) == I2S_CLOCK_PLLSRC) ||\ + ((CLOCK) == I2S_CLOCK_PLLR)) +#endif /* STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) ||\ + ((CLOCK) == I2S_CLOCK_PLLSRC) ||\ + ((CLOCK) == I2S_CLOCK_PLLR)) +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F4xx_HAL_I2S_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s_ex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s_ex.h new file mode 100644 index 0000000..10335f4 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s_ex.h @@ -0,0 +1,185 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_i2s_ex.h + * @author MCD Application Team + * @brief Header file of I2S HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F4xx_HAL_I2S_EX_H +#define STM32F4xx_HAL_I2S_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ +#if defined(SPI_I2S_FULLDUPLEX_SUPPORT) +/** @addtogroup I2SEx I2SEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup I2SEx_Exported_Macros I2S Extended Exported Macros + * @{ + */ + +#define I2SxEXT(__INSTANCE__) ((__INSTANCE__) == (SPI2)? (SPI_TypeDef *)(I2S2ext_BASE): (SPI_TypeDef *)(I2S3ext_BASE)) + +/** @brief Enable or disable the specified I2SExt peripheral. + * @param __HANDLE__ specifies the I2S Handle. + * @retval None + */ +#define __HAL_I2SEXT_ENABLE(__HANDLE__) (I2SxEXT((__HANDLE__)->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE) +#define __HAL_I2SEXT_DISABLE(__HANDLE__) (I2SxEXT((__HANDLE__)->Instance)->I2SCFGR &= ~SPI_I2SCFGR_I2SE) + +/** @brief Enable or disable the specified I2SExt interrupts. + * @param __HANDLE__ specifies the I2S Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable or disable. + * This parameter can be one of the following values: + * @arg I2S_IT_TXE: Tx buffer empty interrupt enable + * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable + * @arg I2S_IT_ERR: Error interrupt enable + * @retval None + */ +#define __HAL_I2SEXT_ENABLE_IT(__HANDLE__, __INTERRUPT__) (I2SxEXT((__HANDLE__)->Instance)->CR2 |= (__INTERRUPT__)) +#define __HAL_I2SEXT_DISABLE_IT(__HANDLE__, __INTERRUPT__) (I2SxEXT((__HANDLE__)->Instance)->CR2 &= ~(__INTERRUPT__)) + +/** @brief Checks if the specified I2SExt interrupt source is enabled or disabled. + * @param __HANDLE__ specifies the I2S Handle. + * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral. + * @param __INTERRUPT__ specifies the I2S interrupt source to check. + * This parameter can be one of the following values: + * @arg I2S_IT_TXE: Tx buffer empty interrupt enable + * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable + * @arg I2S_IT_ERR: Error interrupt enable + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_I2SEXT_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((I2SxEXT((__HANDLE__)->Instance)->CR2\ + & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Checks whether the specified I2SExt flag is set or not. + * @param __HANDLE__ specifies the I2S Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg I2S_FLAG_RXNE: Receive buffer not empty flag + * @arg I2S_FLAG_TXE: Transmit buffer empty flag + * @arg I2S_FLAG_UDR: Underrun flag + * @arg I2S_FLAG_OVR: Overrun flag + * @arg I2S_FLAG_FRE: Frame error flag + * @arg I2S_FLAG_CHSIDE: Channel Side flag + * @arg I2S_FLAG_BSY: Busy flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_I2SEXT_GET_FLAG(__HANDLE__, __FLAG__) (((I2SxEXT((__HANDLE__)->Instance)->SR) & (__FLAG__)) == (__FLAG__)) + +/** @brief Clears the I2SExt OVR pending flag. + * @param __HANDLE__ specifies the I2S Handle. + * @retval None + */ +#define __HAL_I2SEXT_CLEAR_OVRFLAG(__HANDLE__) do{ \ + __IO uint32_t tmpreg_ovr = 0x00U; \ + tmpreg_ovr = I2SxEXT((__HANDLE__)->Instance)->DR;\ + tmpreg_ovr = I2SxEXT((__HANDLE__)->Instance)->SR;\ + UNUSED(tmpreg_ovr); \ + }while(0U) +/** @brief Clears the I2SExt UDR pending flag. + * @param __HANDLE__ specifies the I2S Handle. + * @retval None + */ +#define __HAL_I2SEXT_CLEAR_UDRFLAG(__HANDLE__) do{ \ + __IO uint32_t tmpreg_udr = 0x00U; \ + tmpreg_udr = I2SxEXT((__HANDLE__)->Instance)->SR;\ + UNUSED(tmpreg_udr); \ + }while(0U) +/** @brief Flush the I2S and I2SExt DR Registers. + * @param __HANDLE__ specifies the I2S Handle. + * @retval None + */ +#define __HAL_I2SEXT_FLUSH_RX_DR(__HANDLE__) do{ \ + __IO uint32_t tmpreg_dr = 0x00U; \ + tmpreg_dr = I2SxEXT((__HANDLE__)->Instance)->DR; \ + tmpreg_dr = ((__HANDLE__)->Instance->DR); \ + UNUSED(tmpreg_dr); \ + }while(0U) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2SEx_Exported_Functions I2S Extended Exported Functions + * @{ + */ + +/** @addtogroup I2SEx_Exported_Functions_Group1 I2S Extended IO operation functions + * @{ + */ + +/* Extended features functions *************************************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, + uint16_t Size, uint32_t Timeout); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, + uint16_t Size); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, + uint16_t Size); +/* I2S IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ +void HAL_I2SEx_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s); +void HAL_I2SEx_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s); +void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s); +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32F4xx_HAL_I2S_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h new file mode 100644 index 0000000..6f3bf71 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h @@ -0,0 +1,431 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_pwr.h + * @author MCD Application Team + * @brief Header file of PWR HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_PWR_H +#define __STM32F4xx_HAL_PWR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup PWR + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Types PWR Exported Types + * @{ + */ + +/** + * @brief PWR PVD configuration structure definition + */ +typedef struct +{ + uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. + This parameter can be a value of @ref PWR_PVD_detection_level */ + + uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. + This parameter can be a value of @ref PWR_PVD_Mode */ +}PWR_PVDTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PWR_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins + * @{ + */ +#define PWR_WAKEUP_PIN1 0x00000100U +/** + * @} + */ + +/** @defgroup PWR_PVD_detection_level PWR PVD detection level + * @{ + */ +#define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0 +#define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1 +#define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2 +#define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3 +#define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4 +#define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5 +#define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6 +#define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7/* External input analog voltage + (Compare internally to VREFINT) */ +/** + * @} + */ + +/** @defgroup PWR_PVD_Mode PWR PVD Mode + * @{ + */ +#define PWR_PVD_MODE_NORMAL 0x00000000U /*!< basic mode is used */ +#define PWR_PVD_MODE_IT_RISING 0x00010001U /*!< External Interrupt Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_IT_FALLING 0x00010002U /*!< External Interrupt Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_IT_RISING_FALLING 0x00010003U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING 0x00020001U /*!< Event Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_EVENT_FALLING 0x00020002U /*!< Event Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING_FALLING 0x00020003U /*!< Event Mode with Rising/Falling edge trigger detection */ +/** + * @} + */ + + +/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode + * @{ + */ +#define PWR_MAINREGULATOR_ON 0x00000000U +#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS +/** + * @} + */ + +/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry + * @{ + */ +#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) +#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) +/** + * @} + */ + +/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry + * @{ + */ +#define PWR_STOPENTRY_WFI ((uint8_t)0x01) +#define PWR_STOPENTRY_WFE ((uint8_t)0x02) +/** + * @} + */ + +/** @defgroup PWR_Flag PWR Flag + * @{ + */ +#define PWR_FLAG_WU PWR_CSR_WUF +#define PWR_FLAG_SB PWR_CSR_SBF +#define PWR_FLAG_PVDO PWR_CSR_PVDO +#define PWR_FLAG_BRR PWR_CSR_BRR +#define PWR_FLAG_VOSRDY PWR_CSR_VOSRDY +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWR_Exported_Macro PWR Exported Macro + * @{ + */ + +/** @brief Check PWR flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event + * was received from the WKUP pin or from the RTC alarm (Alarm A + * or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup. + * An additional wakeup event is detected if the WKUP pin is enabled + * (by setting the EWUP bit) when the WKUP pin level is already high. + * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was + * resumed from StandBy mode. + * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled + * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode + * For this reason, this bit is equal to 0 after Standby or reset + * until the PVDE bit is set. + * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset + * when the device wakes up from Standby mode or by a system reset + * or power reset. + * @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage + * scaling output selection is ready. + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the PWR's pending flags. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag + * @arg PWR_FLAG_SB: StandBy flag + */ +#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2U) + +/** + * @brief Enable the PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD)) + +/** + * @brief Disable the PVD EXTI Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD)) + +/** + * @brief Enable event on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD)) + +/** + * @brief Disable event on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD)) + +/** + * @brief Enable the PVD Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) + +/** + * @brief Enable the PVD Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) + + +/** + * @brief Disable the PVD Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) + + +/** + * @brief PVD EXTI line configuration: set rising & falling edge trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() do{__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();\ + __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();\ + }while(0U) + +/** + * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. + * This parameter can be: + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() do{__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();\ + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();\ + }while(0U) + +/** + * @brief checks whether the specified PVD Exti interrupt flag is set or not. + * @retval EXTI PVD Line Status. + */ +#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) + +/** + * @brief Clear the PVD Exti flag. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) + +/** + * @brief Generates a Software interrupt on PVD EXTI line. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD)) + +/** + * @} + */ + +/* Include PWR HAL Extension module */ +#include "stm32f4xx_hal_pwr_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +void HAL_PWR_DeInit(void); +void HAL_PWR_EnableBkUpAccess(void); +void HAL_PWR_DisableBkUpAccess(void); +/** + * @} + */ + +/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions + * @{ + */ +/* Peripheral Control functions **********************************************/ +/* PVD configuration */ +void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); +void HAL_PWR_EnablePVD(void); +void HAL_PWR_DisablePVD(void); + +/* WakeUp pins configuration */ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx); +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); + +/* Low Power modes entry */ +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); +void HAL_PWR_EnterSTANDBYMode(void); + +/* Power PVD IRQ Handler */ +void HAL_PWR_PVD_IRQHandler(void); +void HAL_PWR_PVDCallback(void); + +/* Cortex System Control functions *******************************************/ +void HAL_PWR_EnableSleepOnExit(void); +void HAL_PWR_DisableSleepOnExit(void); +void HAL_PWR_EnableSEVOnPend(void); +void HAL_PWR_DisableSEVOnPend(void); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup PWR_Private_Constants PWR Private Constants + * @{ + */ + +/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line + * @{ + */ +#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_MR16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ +/** + * @} + */ + +/** @defgroup PWR_register_alias_address PWR Register alias address + * @{ + */ +/* ------------- PWR registers bit address in the alias region ---------------*/ +#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) +#define PWR_CR_OFFSET 0x00U +#define PWR_CSR_OFFSET 0x04U +#define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET) +#define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET) +/** + * @} + */ + +/** @defgroup PWR_CR_register_alias PWR CR Register alias address + * @{ + */ +/* --- CR Register ---*/ +/* Alias word address of DBP bit */ +#define DBP_BIT_NUMBER PWR_CR_DBP_Pos +#define CR_DBP_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U)) + +/* Alias word address of PVDE bit */ +#define PVDE_BIT_NUMBER PWR_CR_PVDE_Pos +#define CR_PVDE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U)) + +/* Alias word address of VOS bit */ +#define VOS_BIT_NUMBER PWR_CR_VOS_Pos +#define CR_VOS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (VOS_BIT_NUMBER * 4U)) +/** + * @} + */ + +/** @defgroup PWR_CSR_register_alias PWR CSR Register alias address + * @{ + */ +/* --- CSR Register ---*/ +/* Alias word address of EWUP bit */ +#define EWUP_BIT_NUMBER PWR_CSR_EWUP_Pos +#define CSR_EWUP_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (EWUP_BIT_NUMBER * 4U)) +/** + * @} + */ + +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup PWR_Private_Macros PWR Private Macros + * @{ + */ + +/** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters + * @{ + */ +#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ + ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ + ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ + ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) +#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ + ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ + ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \ + ((MODE) == PWR_PVD_MODE_NORMAL)) +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ + ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) +#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F4xx_HAL_PWR_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h new file mode 100644 index 0000000..10e017a --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h @@ -0,0 +1,344 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_pwr_ex.h + * @author MCD Application Team + * @brief Header file of PWR HAL Extension module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_PWR_EX_H +#define __STM32F4xx_HAL_PWR_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup PWREx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PWREx_Exported_Constants PWREx Exported Constants + * @{ + */ +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) + +/** @defgroup PWREx_Regulator_state_in_UnderDrive_mode PWREx Regulator state in UnderDrive mode + * @{ + */ +#define PWR_MAINREGULATOR_UNDERDRIVE_ON PWR_CR_MRUDS +#define PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON ((uint32_t)(PWR_CR_LPDS | PWR_CR_LPUDS)) +/** + * @} + */ + +/** @defgroup PWREx_Over_Under_Drive_Flag PWREx Over Under Drive Flag + * @{ + */ +#define PWR_FLAG_ODRDY PWR_CSR_ODRDY +#define PWR_FLAG_ODSWRDY PWR_CSR_ODSWRDY +#define PWR_FLAG_UDRDY PWR_CSR_UDSWRDY +/** + * @} + */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ + +/** @defgroup PWREx_Regulator_Voltage_Scale PWREx Regulator Voltage Scale + * @{ + */ +#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx) +#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS /* Scale 1 mode(default value at reset): the maximum value of fHCLK = 168 MHz. */ +#define PWR_REGULATOR_VOLTAGE_SCALE2 0x00000000U /* Scale 2 mode: the maximum value of fHCLK = 144 MHz. */ +#else +#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS /* Scale 1 mode(default value at reset): the maximum value of fHCLK is 168 MHz. It can be extended to + 180 MHz by activating the over-drive mode. */ +#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR_VOS_1 /* Scale 2 mode: the maximum value of fHCLK is 144 MHz. It can be extended to + 168 MHz by activating the over-drive mode. */ +#define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR_VOS_0 /* Scale 3 mode: the maximum value of fHCLK is 120 MHz. */ +#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */ +/** + * @} + */ +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ + defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/** @defgroup PWREx_WakeUp_Pins PWREx WakeUp Pins + * @{ + */ +#define PWR_WAKEUP_PIN2 0x00000080U +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ + defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +#define PWR_WAKEUP_PIN3 0x00000040U +#endif /* STM32F410xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Zx || STM32F412Vx || \ + STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ +/** + * @} + */ +#endif /* STM32F410xx || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || + STM32F413xx || STM32F423xx */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWREx_Exported_Constants PWREx Exported Constants + * @{ + */ + +#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx) +/** @brief macros configure the main internal regulator output voltage. + * @param __REGULATOR__ specifies the regulator output voltage to achieve + * a tradeoff between performance and power consumption when the device does + * not operate at the maximum frequency (refer to the datasheets for more details). + * This parameter can be one of the following values: + * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode + * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode + * @retval None + */ +#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \ + __IO uint32_t tmpreg = 0x00U; \ + MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS); \ + UNUSED(tmpreg); \ + } while(0U) +#else +/** @brief macros configure the main internal regulator output voltage. + * @param __REGULATOR__ specifies the regulator output voltage to achieve + * a tradeoff between performance and power consumption when the device does + * not operate at the maximum frequency (refer to the datasheets for more details). + * This parameter can be one of the following values: + * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode + * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode + * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode + * @retval None + */ +#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \ + __IO uint32_t tmpreg = 0x00U; \ + MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS); \ + UNUSED(tmpreg); \ + } while(0U) +#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +/** @brief Macros to enable or disable the Over drive mode. + * @note These macros can be used only for STM32F42xx/STM3243xx devices. + */ +#define __HAL_PWR_OVERDRIVE_ENABLE() (*(__IO uint32_t *) CR_ODEN_BB = ENABLE) +#define __HAL_PWR_OVERDRIVE_DISABLE() (*(__IO uint32_t *) CR_ODEN_BB = DISABLE) + +/** @brief Macros to enable or disable the Over drive switching. + * @note These macros can be used only for STM32F42xx/STM3243xx devices. + */ +#define __HAL_PWR_OVERDRIVESWITCHING_ENABLE() (*(__IO uint32_t *) CR_ODSWEN_BB = ENABLE) +#define __HAL_PWR_OVERDRIVESWITCHING_DISABLE() (*(__IO uint32_t *) CR_ODSWEN_BB = DISABLE) + +/** @brief Macros to enable or disable the Under drive mode. + * @note This mode is enabled only with STOP low power mode. + * In this mode, the 1.2V domain is preserved in reduced leakage mode. This + * mode is only available when the main regulator or the low power regulator + * is in low voltage mode. + * @note If the Under-drive mode was enabled, it is automatically disabled after + * exiting Stop mode. + * When the voltage regulator operates in Under-drive mode, an additional + * startup delay is induced when waking up from Stop mode. + */ +#define __HAL_PWR_UNDERDRIVE_ENABLE() (PWR->CR |= (uint32_t)PWR_CR_UDEN) +#define __HAL_PWR_UNDERDRIVE_DISABLE() (PWR->CR &= (uint32_t)(~PWR_CR_UDEN)) + +/** @brief Check PWR flag is set or not. + * @note These macros can be used only for STM32F42xx/STM3243xx devices. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode + * is ready + * @arg PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode + * switching is ready + * @arg PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode + * is enabled in Stop mode + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_PWR_GET_ODRUDR_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the Under-Drive Ready flag. + * @note These macros can be used only for STM32F42xx/STM3243xx devices. + */ +#define __HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR |= PWR_FLAG_UDRDY) + +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions + * @{ + */ + +/** @addtogroup PWREx_Exported_Functions_Group1 + * @{ + */ +void HAL_PWREx_EnableFlashPowerDown(void); +void HAL_PWREx_DisableFlashPowerDown(void); +HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void); +HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void); +uint32_t HAL_PWREx_GetVoltageRange(void); +HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling); + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F401xC) ||\ + defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\ + defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +void HAL_PWREx_EnableMainRegulatorLowVoltage(void); +void HAL_PWREx_DisableMainRegulatorLowVoltage(void); +void HAL_PWREx_EnableLowRegulatorLowVoltage(void); +void HAL_PWREx_DisableLowRegulatorLowVoltage(void); +#endif /* STM32F410xx || STM32F401xC || STM32F401xE || STM32F411xE || STM32F412Zx || STM32F412Vx ||\ + STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) +HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void); +HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void); +HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry); +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ + +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup PWREx_Private_Constants PWREx Private Constants + * @{ + */ + +/** @defgroup PWREx_register_alias_address PWREx Register alias address + * @{ + */ +/* ------------- PWR registers bit address in the alias region ---------------*/ +/* --- CR Register ---*/ +/* Alias word address of FPDS bit */ +#define FPDS_BIT_NUMBER PWR_CR_FPDS_Pos +#define CR_FPDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (FPDS_BIT_NUMBER * 4U)) + +/* Alias word address of ODEN bit */ +#define ODEN_BIT_NUMBER PWR_CR_ODEN_Pos +#define CR_ODEN_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (ODEN_BIT_NUMBER * 4U)) + +/* Alias word address of ODSWEN bit */ +#define ODSWEN_BIT_NUMBER PWR_CR_ODSWEN_Pos +#define CR_ODSWEN_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (ODSWEN_BIT_NUMBER * 4U)) + +/* Alias word address of MRLVDS bit */ +#define MRLVDS_BIT_NUMBER PWR_CR_MRLVDS_Pos +#define CR_MRLVDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (MRLVDS_BIT_NUMBER * 4U)) + +/* Alias word address of LPLVDS bit */ +#define LPLVDS_BIT_NUMBER PWR_CR_LPLVDS_Pos +#define CR_LPLVDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPLVDS_BIT_NUMBER * 4U)) + + /** + * @} + */ + +/** @defgroup PWREx_CSR_register_alias PWRx CSR Register alias address + * @{ + */ +/* --- CSR Register ---*/ +/* Alias word address of BRE bit */ +#define BRE_BIT_NUMBER PWR_CSR_BRE_Pos +#define CSR_BRE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (BRE_BIT_NUMBER * 4U)) + +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup PWREx_Private_Macros PWREx Private Macros + * @{ + */ + +/** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters + * @{ + */ +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +#define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_UNDERDRIVE_ON) || \ + ((REGULATOR) == PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON)) +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx) +#define IS_PWR_VOLTAGE_SCALING_RANGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ + ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2)) +#else +#define IS_PWR_VOLTAGE_SCALING_RANGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ + ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \ + ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3)) +#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */ + +#if defined(STM32F446xx) +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2)) +#elif defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F412Zx) ||\ + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\ + defined(STM32F423xx) +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2) || \ + ((PIN) == PWR_WAKEUP_PIN3)) +#else +#define IS_PWR_WAKEUP_PIN(PIN) ((PIN) == PWR_WAKEUP_PIN1) +#endif /* STM32F446xx */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F4xx_HAL_PWR_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h new file mode 100644 index 0000000..36a639b --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h @@ -0,0 +1,1464 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_rcc.h + * @author MCD Application Team + * @brief Header file of RCC HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_RCC_H +#define __STM32F4xx_HAL_RCC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/* Include RCC HAL Extended module */ +/* (include on top of file since RCC structures are defined in extended file) */ +#include "stm32f4xx_hal_rcc_ex.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup RCC_Exported_Types RCC Exported Types + * @{ + */ + +/** + * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition + */ +typedef struct +{ + uint32_t OscillatorType; /*!< The oscillators to be configured. + This parameter can be a value of @ref RCC_Oscillator_Type */ + + uint32_t HSEState; /*!< The new state of the HSE. + This parameter can be a value of @ref RCC_HSE_Config */ + + uint32_t LSEState; /*!< The new state of the LSE. + This parameter can be a value of @ref RCC_LSE_Config */ + + uint32_t HSIState; /*!< The new state of the HSI. + This parameter can be a value of @ref RCC_HSI_Config */ + + uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ + + uint32_t LSIState; /*!< The new state of the LSI. + This parameter can be a value of @ref RCC_LSI_Config */ + + RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ +}RCC_OscInitTypeDef; + +/** + * @brief RCC System, AHB and APB busses clock configuration structure definition + */ +typedef struct +{ + uint32_t ClockType; /*!< The clock to be configured. + This parameter can be a value of @ref RCC_System_Clock_Type */ + + uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. + This parameter can be a value of @ref RCC_System_Clock_Source */ + + uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). + This parameter can be a value of @ref RCC_AHB_Clock_Source */ + + uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ + + uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ + +}RCC_ClkInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_Exported_Constants RCC Exported Constants + * @{ + */ + +/** @defgroup RCC_Oscillator_Type Oscillator Type + * @{ + */ +#define RCC_OSCILLATORTYPE_NONE 0x00000000U +#define RCC_OSCILLATORTYPE_HSE 0x00000001U +#define RCC_OSCILLATORTYPE_HSI 0x00000002U +#define RCC_OSCILLATORTYPE_LSE 0x00000004U +#define RCC_OSCILLATORTYPE_LSI 0x00000008U +/** + * @} + */ + +/** @defgroup RCC_HSE_Config HSE Config + * @{ + */ +#define RCC_HSE_OFF 0x00000000U +#define RCC_HSE_ON RCC_CR_HSEON +#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) +/** + * @} + */ + +/** @defgroup RCC_LSE_Config LSE Config + * @{ + */ +#define RCC_LSE_OFF 0x00000000U +#define RCC_LSE_ON RCC_BDCR_LSEON +#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) +/** + * @} + */ + +/** @defgroup RCC_HSI_Config HSI Config + * @{ + */ +#define RCC_HSI_OFF ((uint8_t)0x00) +#define RCC_HSI_ON ((uint8_t)0x01) + +#define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */ +/** + * @} + */ + +/** @defgroup RCC_LSI_Config LSI Config + * @{ + */ +#define RCC_LSI_OFF ((uint8_t)0x00) +#define RCC_LSI_ON ((uint8_t)0x01) +/** + * @} + */ + +/** @defgroup RCC_PLL_Config PLL Config + * @{ + */ +#define RCC_PLL_NONE ((uint8_t)0x00) +#define RCC_PLL_OFF ((uint8_t)0x01) +#define RCC_PLL_ON ((uint8_t)0x02) +/** + * @} + */ + +/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider + * @{ + */ +#define RCC_PLLP_DIV2 0x00000002U +#define RCC_PLLP_DIV4 0x00000004U +#define RCC_PLLP_DIV6 0x00000006U +#define RCC_PLLP_DIV8 0x00000008U +/** + * @} + */ + +/** @defgroup RCC_PLL_Clock_Source PLL Clock Source + * @{ + */ +#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI +#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Type System Clock Type + * @{ + */ +#define RCC_CLOCKTYPE_SYSCLK 0x00000001U +#define RCC_CLOCKTYPE_HCLK 0x00000002U +#define RCC_CLOCKTYPE_PCLK1 0x00000004U +#define RCC_CLOCKTYPE_PCLK2 0x00000008U +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source System Clock Source + * @note The RCC_SYSCLKSOURCE_PLLRCLK parameter is available only for + * STM32F446xx devices. + * @{ + */ +#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI +#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE +#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL +#define RCC_SYSCLKSOURCE_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1)) +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status + * @note The RCC_SYSCLKSOURCE_STATUS_PLLRCLK parameter is available only for + * STM32F446xx devices. + * @{ + */ +#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_PLLRCLK ((uint32_t)(RCC_CFGR_SWS_0 | RCC_CFGR_SWS_1)) /*!< PLLR used as system clock */ +/** + * @} + */ + +/** @defgroup RCC_AHB_Clock_Source AHB Clock Source + * @{ + */ +#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 +#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 +#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 +#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 +#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 +#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 +#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 +#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 +#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 +/** + * @} + */ + +/** @defgroup RCC_APB1_APB2_Clock_Source APB1/APB2 Clock Source + * @{ + */ +#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 +#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 +#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 +#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 +#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 +/** + * @} + */ + +/** @defgroup RCC_RTC_Clock_Source RTC Clock Source + * @{ + */ +#define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U +#define RCC_RTCCLKSOURCE_LSE 0x00000100U +#define RCC_RTCCLKSOURCE_LSI 0x00000200U +#define RCC_RTCCLKSOURCE_HSE_DIVX 0x00000300U +#define RCC_RTCCLKSOURCE_HSE_DIV2 0x00020300U +#define RCC_RTCCLKSOURCE_HSE_DIV3 0x00030300U +#define RCC_RTCCLKSOURCE_HSE_DIV4 0x00040300U +#define RCC_RTCCLKSOURCE_HSE_DIV5 0x00050300U +#define RCC_RTCCLKSOURCE_HSE_DIV6 0x00060300U +#define RCC_RTCCLKSOURCE_HSE_DIV7 0x00070300U +#define RCC_RTCCLKSOURCE_HSE_DIV8 0x00080300U +#define RCC_RTCCLKSOURCE_HSE_DIV9 0x00090300U +#define RCC_RTCCLKSOURCE_HSE_DIV10 0x000A0300U +#define RCC_RTCCLKSOURCE_HSE_DIV11 0x000B0300U +#define RCC_RTCCLKSOURCE_HSE_DIV12 0x000C0300U +#define RCC_RTCCLKSOURCE_HSE_DIV13 0x000D0300U +#define RCC_RTCCLKSOURCE_HSE_DIV14 0x000E0300U +#define RCC_RTCCLKSOURCE_HSE_DIV15 0x000F0300U +#define RCC_RTCCLKSOURCE_HSE_DIV16 0x00100300U +#define RCC_RTCCLKSOURCE_HSE_DIV17 0x00110300U +#define RCC_RTCCLKSOURCE_HSE_DIV18 0x00120300U +#define RCC_RTCCLKSOURCE_HSE_DIV19 0x00130300U +#define RCC_RTCCLKSOURCE_HSE_DIV20 0x00140300U +#define RCC_RTCCLKSOURCE_HSE_DIV21 0x00150300U +#define RCC_RTCCLKSOURCE_HSE_DIV22 0x00160300U +#define RCC_RTCCLKSOURCE_HSE_DIV23 0x00170300U +#define RCC_RTCCLKSOURCE_HSE_DIV24 0x00180300U +#define RCC_RTCCLKSOURCE_HSE_DIV25 0x00190300U +#define RCC_RTCCLKSOURCE_HSE_DIV26 0x001A0300U +#define RCC_RTCCLKSOURCE_HSE_DIV27 0x001B0300U +#define RCC_RTCCLKSOURCE_HSE_DIV28 0x001C0300U +#define RCC_RTCCLKSOURCE_HSE_DIV29 0x001D0300U +#define RCC_RTCCLKSOURCE_HSE_DIV30 0x001E0300U +#define RCC_RTCCLKSOURCE_HSE_DIV31 0x001F0300U +/** + * @} + */ + +/** @defgroup RCC_MCO_Index MCO Index + * @{ + */ +#define RCC_MCO1 0x00000000U +#define RCC_MCO2 0x00000001U +/** + * @} + */ + +/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source + * @{ + */ +#define RCC_MCO1SOURCE_HSI 0x00000000U +#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0 +#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1 +#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1 +/** + * @} + */ + +/** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler + * @{ + */ +#define RCC_MCODIV_1 0x00000000U +#define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2 +#define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2) +#define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2) +#define RCC_MCODIV_5 RCC_CFGR_MCO1PRE +/** + * @} + */ + +/** @defgroup RCC_Interrupt Interrupts + * @{ + */ +#define RCC_IT_LSIRDY ((uint8_t)0x01) +#define RCC_IT_LSERDY ((uint8_t)0x02) +#define RCC_IT_HSIRDY ((uint8_t)0x04) +#define RCC_IT_HSERDY ((uint8_t)0x08) +#define RCC_IT_PLLRDY ((uint8_t)0x10) +#define RCC_IT_PLLI2SRDY ((uint8_t)0x20) +#define RCC_IT_CSS ((uint8_t)0x80) +/** + * @} + */ + +/** @defgroup RCC_Flag Flags + * Elements values convention: 0XXYYYYYb + * - YYYYY : Flag position in the register + * - 0XX : Register index + * - 01: CR register + * - 10: BDCR register + * - 11: CSR register + * @{ + */ +/* Flags in the CR register */ +#define RCC_FLAG_HSIRDY ((uint8_t)0x21) +#define RCC_FLAG_HSERDY ((uint8_t)0x31) +#define RCC_FLAG_PLLRDY ((uint8_t)0x39) +#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B) + +/* Flags in the BDCR register */ +#define RCC_FLAG_LSERDY ((uint8_t)0x41) + +/* Flags in the CSR register */ +#define RCC_FLAG_LSIRDY ((uint8_t)0x61) +#define RCC_FLAG_BORRST ((uint8_t)0x79) +#define RCC_FLAG_PINRST ((uint8_t)0x7A) +#define RCC_FLAG_PORRST ((uint8_t)0x7B) +#define RCC_FLAG_SFTRST ((uint8_t)0x7C) +#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) +#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) +#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RCC_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_DMA1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_DMA2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN)) +#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN)) +#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN)) +#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN)) +#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN)) +#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN)) +/** + * @} + */ + +/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) != RESET) +#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) != RESET) +#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) != RESET) +#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) != RESET) +#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) != RESET) +#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) != RESET) + +#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) == RESET) +#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) == RESET) +#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) == RESET) +#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) == RESET) +#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) == RESET) +#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) == RESET) +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable + * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_WWDG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USART2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_I2C1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_I2C2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_PWR_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) +#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) +#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) +#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) +#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) +#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) +#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) +/** + * @} + */ + +/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET) +#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET) +#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) +#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET) +#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET) +#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET) +#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET) + +#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET) +#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET) +#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) +#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET) +#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET) +#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET) +#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET) +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable + * @brief Enable or disable the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USART6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_ADC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM9_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM11_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) +#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) +#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN)) +#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) +#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) +#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN)) +#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN)) +#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN)) +/** + * @} + */ + +/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET) +#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET) +#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET) +#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET) +#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET) +#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET) +#define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET) +#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET) + +#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET) +#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET) +#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET) +#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET) +#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET) +#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET) +#define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET) +#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET) +/** + * @} + */ + +/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset + * @brief Force or release AHB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST)) +#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST)) +#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST)) +#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST)) +#define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST)) +#define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST)) + +#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U) +#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST)) +#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST)) +#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST)) +#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST)) +#define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST)) +#define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST)) +/** + * @} + */ + +/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) +#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) +#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) +#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) +#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) +#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) +#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) + +#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U) +#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) +#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) +#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) +#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) +#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) +#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) +#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) +/** + * @} + */ + +/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset + * @brief Force or release APB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)) +#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) +#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST)) +#define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST)) +#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) +#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST)) +#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST)) +#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST)) + +#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U) +#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) +#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) +#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST)) +#define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST)) +#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) +#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST)) +#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST)) +#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST)) +/** + * @} + */ + +/** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN)) +#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN)) +#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN)) +#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN)) +#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN)) +#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN)) + +#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN)) +#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN)) +#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN)) +#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN)) +#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN)) +#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN)) +/** + * @} + */ + +/** @defgroup RCC_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN)) +#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN)) +#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN)) +#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN)) +#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN)) +#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN)) +#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN)) + +#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN)) +#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN)) +#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN)) +#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN)) +#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN)) +#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN)) +#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN)) +/** + * @} + */ + +/** @defgroup RCC_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN)) +#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN)) +#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN)) +#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN)) +#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN)) +#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN)) +#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN)) +#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN)) + +#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN)) +#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN)) +#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN)) +#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN)) +#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN)) +#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN)) +#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN)) +#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN)) +/** + * @} + */ + +/** @defgroup RCC_HSI_Configuration HSI Configuration + * @{ + */ + +/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). + * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. + * It is used (enabled by hardware) as system clock source after startup + * from Reset, wake-up from STOP and STANDBY mode, or in case of failure + * of the HSE used directly or indirectly as system clock (if the Clock + * Security System CSS is enabled). + * @note HSI can not be stopped if it is used as system clock source. In this case, + * you have to select another source of the system clock then stop the HSI. + * @note After enabling the HSI, the application software should wait on HSIRDY + * flag to be set indicating that HSI clock is stable and can be used as + * system clock source. + * This parameter can be: ENABLE or DISABLE. + * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator + * clock cycles. + */ +#define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE) +#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE) + +/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal HSI RC. + * @param __HSICalibrationValue__ specifies the calibration trimming value. + * (default is RCC_HSICALIBRATION_DEFAULT). + * This parameter must be a number between 0 and 0x1F. + */ +#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\ + RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_CR_HSITRIM_Pos)) +/** + * @} + */ + +/** @defgroup RCC_LSI_Configuration LSI Configuration + * @{ + */ + +/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). + * @note After enabling the LSI, the application software should wait on + * LSIRDY flag to be set indicating that LSI clock is stable and can + * be used to clock the IWDG and/or the RTC. + * @note LSI can not be disabled if the IWDG is running. + * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator + * clock cycles. + */ +#define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE) +#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE) +/** + * @} + */ + +/** @defgroup RCC_HSE_Configuration HSE Configuration + * @{ + */ + +/** + * @brief Macro to configure the External High Speed oscillator (HSE). + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro. + * User should request a transition to HSE Off first and then HSE On or HSE Bypass. + * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application + * software should wait on HSERDY flag to be set indicating that HSE clock + * is stable and can be used to clock the PLL and/or system clock. + * @note HSE state can not be changed if it is used directly or through the + * PLL as system clock. In this case, you have to select another source + * of the system clock then change the HSE state (ex. disable it). + * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. + * @note This function reset the CSSON bit, so if the clock security system(CSS) + * was previously enabled you have to enable it again after calling this + * function. + * @param __STATE__ specifies the new state of the HSE. + * This parameter can be one of the following values: + * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after + * 6 HSE oscillator clock cycles. + * @arg RCC_HSE_ON: turn ON the HSE oscillator. + * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock. + */ +#define __HAL_RCC_HSE_CONFIG(__STATE__) \ + do { \ + if ((__STATE__) == RCC_HSE_ON) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else if ((__STATE__) == RCC_HSE_BYPASS) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + } \ + } while(0U) +/** + * @} + */ + +/** @defgroup RCC_LSE_Configuration LSE Configuration + * @{ + */ + +/** + * @brief Macro to configure the External Low Speed oscillator (LSE). + * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. + * User should request a transition to LSE Off first and then LSE On or LSE Bypass. + * @note As the LSE is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * HAL_PWR_EnableBkUpAccess() function before to configure the LSE + * (to be done once after reset). + * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application + * software should wait on LSERDY flag to be set indicating that LSE clock + * is stable and can be used to clock the RTC. + * @param __STATE__ specifies the new state of the LSE. + * This parameter can be one of the following values: + * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after + * 6 LSE oscillator clock cycles. + * @arg RCC_LSE_ON: turn ON the LSE oscillator. + * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock. + */ +#define __HAL_RCC_LSE_CONFIG(__STATE__) \ + do { \ + if((__STATE__) == RCC_LSE_ON) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else if((__STATE__) == RCC_LSE_BYPASS) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + } \ + } while(0U) +/** + * @} + */ + +/** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration + * @{ + */ + +/** @brief Macros to enable or disable the RTC clock. + * @note These macros must be used only after the RTC clock source was selected. + */ +#define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE) +#define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE) + +/** @brief Macros to configure the RTC clock (RTCCLK). + * @note As the RTC clock configuration bits are in the Backup domain and write + * access is denied to this domain after reset, you have to enable write + * access using the Power Backup Access macro before to configure + * the RTC clock source (to be done once after reset). + * @note Once the RTC clock is configured it can't be changed unless the + * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by + * a Power On Reset (POR). + * @param __RTCCLKSource__ specifies the RTC clock source. + * This parameter can be one of the following values: + @arg @ref RCC_RTCCLKSOURCE_NO_CLK: No clock selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected + * as RTC clock, where x:[2,31] + * @note If the LSE or LSI is used as RTC clock source, the RTC continues to + * work in STOP and STANDBY modes, and can be used as wake-up source. + * However, when the HSE clock is used as RTC clock source, the RTC + * cannot be used in STOP and STANDBY modes. + * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as + * RTC clock source). + */ +#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFFU)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) + +#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \ + RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU); \ + } while(0U) + +/** @brief Macro to get the RTC clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER() + */ +#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) + +/** + * @brief Get the RTC and HSE clock divider (RTCPRE). + * @retval Returned value can be one of the following values: + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected + * as RTC clock, where x:[2,31] + */ +#define __HAL_RCC_GET_RTC_HSE_PRESCALER() (READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) | RCC_BDCR_RTCSEL) + +/** @brief Macros to force or release the Backup domain reset. + * @note This function resets the RTC peripheral (including the backup registers) + * and the RTC clock source selection in RCC_CSR register. + * @note The BKPSRAM is not affected by this reset. + */ +#define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE) +#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE) +/** + * @} + */ + +/** @defgroup RCC_PLL_Configuration PLL Configuration + * @{ + */ + +/** @brief Macros to enable or disable the main PLL. + * @note After enabling the main PLL, the application software should wait on + * PLLRDY flag to be set indicating that PLL clock is stable and can + * be used as system clock source. + * @note The main PLL can not be disabled if it is used as system clock source + * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE) +#define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE) + +/** @brief Macro to configure the PLL clock source. + * @note This function must be used only when the main PLL is disabled. + * @param __PLLSOURCE__ specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry + * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry + * + */ +#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) + +/** @brief Macro to configure the PLL multiplication factor. + * @note This function must be used only when the main PLL is disabled. + * @param __PLLM__ specifies the division factor for PLL VCO input clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 63. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency + * of 2 MHz to limit PLL jitter. + * + */ +#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__)) +/** + * @} + */ + +/** @defgroup RCC_Get_Clock_source Get Clock source + * @{ + */ +/** + * @brief Macro to configure the system clock source. + * @param __RCC_SYSCLKSOURCE__ specifies the system clock source. + * This parameter can be one of the following values: + * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. + * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. + * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source. + * - RCC_SYSCLKSOURCE_PLLRCLK: PLLR output is used as system clock source. This + * parameter is available only for STM32F446xx devices. + */ +#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__)) + +/** @brief Macro to get the clock source used as system clock. + * @retval The clock source used as system clock. The returned value can be one + * of the following: + * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock. + * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock. + * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock. + * - RCC_SYSCLKSOURCE_STATUS_PLLRCLK: PLLR used as system clock. This parameter + * is available only for STM32F446xx devices. + */ +#define __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR & RCC_CFGR_SWS) + +/** @brief Macro to get the oscillator used as PLL clock source. + * @retval The oscillator used as PLL clock source. The returned value can be one + * of the following: + * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. + * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. + */ +#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC)) +/** + * @} + */ + +/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config + * @{ + */ + +/** @brief Macro to configure the MCO1 clock. + * @param __MCOCLKSOURCE__ specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg RCC_MCODIV_1: no division applied to MCOx clock + * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock + * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock + * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock + * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock + */ +#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) + +/** @brief Macro to configure the MCO2 clock. + * @param __MCOCLKSOURCE__ specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source + * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx + * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices + * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg RCC_MCODIV_1: no division applied to MCOx clock + * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock + * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock + * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock + * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock + * @note For STM32F410Rx devices, to output I2SCLK clock on MCO2, you should have + * at least one of the SPI clocks enabled (SPI1, SPI2 or SPI5). + */ +#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3U))); +/** + * @} + */ + +/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management + * @brief macros to manage the specified RCC Flags and interrupts. + * @{ + */ + +/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable + * the selected interrupts). + * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt. + * @arg RCC_IT_LSERDY: LSE ready interrupt. + * @arg RCC_IT_HSIRDY: HSI ready interrupt. + * @arg RCC_IT_HSERDY: HSE ready interrupt. + * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. + * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. + */ +#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) + +/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable + * the selected interrupts). + * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt. + * @arg RCC_IT_LSERDY: LSE ready interrupt. + * @arg RCC_IT_HSIRDY: HSI ready interrupt. + * @arg RCC_IT_HSERDY: HSE ready interrupt. + * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. + * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. + */ +#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__))) + +/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] + * bits to clear the selected interrupt pending bits. + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt. + * @arg RCC_IT_LSERDY: LSE ready interrupt. + * @arg RCC_IT_HSIRDY: HSI ready interrupt. + * @arg RCC_IT_HSERDY: HSE ready interrupt. + * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. + * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. + * @arg RCC_IT_CSS: Clock Security System interrupt + */ +#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__)) + +/** @brief Check the RCC's interrupt has occurred or not. + * @param __INTERRUPT__ specifies the RCC interrupt source to check. + * This parameter can be one of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt. + * @arg RCC_IT_LSERDY: LSE ready interrupt. + * @arg RCC_IT_HSIRDY: HSI ready interrupt. + * @arg RCC_IT_HSERDY: HSE ready interrupt. + * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. + * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. + * @arg RCC_IT_CSS: Clock Security System interrupt + * @retval The new state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST, + * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. + */ +#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) + +/** @brief Check RCC flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready. + * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready. + * @arg RCC_FLAG_PLLRDY: Main PLL clock ready. + * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready. + * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready. + * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready. + * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset. + * @arg RCC_FLAG_PINRST: Pin reset. + * @arg RCC_FLAG_PORRST: POR/PDR reset. + * @arg RCC_FLAG_SFTRST: Software reset. + * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset. + * @arg RCC_FLAG_WWDGRST: Window Watchdog reset. + * @arg RCC_FLAG_LPWRRST: Low Power reset. + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define RCC_FLAG_MASK ((uint8_t)0x1FU) +#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :((((__FLAG__) >> 5U) == 3U)? RCC->CSR :RCC->CIR))) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + /** @addtogroup RCC_Exported_Functions + * @{ + */ + +/** @addtogroup RCC_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions ******************************/ +HAL_StatusTypeDef HAL_RCC_DeInit(void); +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); +/** + * @} + */ + +/** @addtogroup RCC_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions ************************************************/ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); +void HAL_RCC_EnableCSS(void); +void HAL_RCC_DisableCSS(void); +uint32_t HAL_RCC_GetSysClockFreq(void); +uint32_t HAL_RCC_GetHCLKFreq(void); +uint32_t HAL_RCC_GetPCLK1Freq(void); +uint32_t HAL_RCC_GetPCLK2Freq(void); +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); + +/* CSS NMI IRQ handler */ +void HAL_RCC_NMI_IRQHandler(void); + +/* User Callbacks in non blocking mode (IT mode) */ +void HAL_RCC_CSSCallback(void); + +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RCC_Private_Constants RCC Private Constants + * @{ + */ + +/** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion + * @brief RCC registers bit address in the alias region + * @{ + */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) +/* --- CR Register --- */ +/* Alias word address of HSION bit */ +#define RCC_CR_OFFSET (RCC_OFFSET + 0x00U) +#define RCC_HSION_BIT_NUMBER 0x00U +#define RCC_CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_HSION_BIT_NUMBER * 4U)) +/* Alias word address of CSSON bit */ +#define RCC_CSSON_BIT_NUMBER 0x13U +#define RCC_CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_CSSON_BIT_NUMBER * 4U)) +/* Alias word address of PLLON bit */ +#define RCC_PLLON_BIT_NUMBER 0x18U +#define RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLON_BIT_NUMBER * 4U)) + +/* --- BDCR Register --- */ +/* Alias word address of RTCEN bit */ +#define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70U) +#define RCC_RTCEN_BIT_NUMBER 0x0FU +#define RCC_BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U)) +/* Alias word address of BDRST bit */ +#define RCC_BDRST_BIT_NUMBER 0x10U +#define RCC_BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_BDRST_BIT_NUMBER * 4U)) + +/* --- CSR Register --- */ +/* Alias word address of LSION bit */ +#define RCC_CSR_OFFSET (RCC_OFFSET + 0x74U) +#define RCC_LSION_BIT_NUMBER 0x00U +#define RCC_CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32U) + (RCC_LSION_BIT_NUMBER * 4U)) + +/* CR register byte 3 (Bits[23:16]) base address */ +#define RCC_CR_BYTE2_ADDRESS 0x40023802U + +/* CIR register byte 2 (Bits[15:8]) base address */ +#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x01U)) + +/* CIR register byte 3 (Bits[23:16]) base address */ +#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x02U)) + +/* BDCR register base address */ +#define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET) + +#define RCC_DBP_TIMEOUT_VALUE 2U +#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT + +#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT +#define HSI_TIMEOUT_VALUE 2U /* 2 ms */ +#define LSI_TIMEOUT_VALUE 2U /* 2 ms */ +#define CLOCKSWITCH_TIMEOUT_VALUE 5000U /* 5 s */ + +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup RCC_Private_Macros RCC Private Macros + * @{ + */ + +/** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters + * @{ + */ +#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15U) + +#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ + ((HSE) == RCC_HSE_BYPASS)) + +#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ + ((LSE) == RCC_LSE_BYPASS)) + +#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON)) + +#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON)) + +#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON)) + +#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \ + ((SOURCE) == RCC_PLLSOURCE_HSE)) + +#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_PLLRCLK)) + +#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV5) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV6) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV7) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV9) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV10) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV11) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV12) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV13) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV14) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV15) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV17) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV18) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV19) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV20) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV21) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV22) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV23) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV24) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV25) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV26) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV27) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV28) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV29) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV30) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV31)) + +#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63U) + +#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || ((VALUE) == 6U) || ((VALUE) == 8U)) + +#define IS_RCC_PLLQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U)) + +#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \ + ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \ + ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \ + ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \ + ((HCLK) == RCC_SYSCLK_DIV512)) + +#define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 15U)) + +#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \ + ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \ + ((PCLK) == RCC_HCLK_DIV16)) + +#define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2)) + +#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ + ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK)) + +#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \ + ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \ + ((DIV) == RCC_MCODIV_5)) +#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1FU) + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_RCC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h new file mode 100644 index 0000000..0b8152b --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h @@ -0,0 +1,7138 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_rcc_ex.h + * @author MCD Application Team + * @brief Header file of RCC HAL Extension module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_RCC_EX_H +#define __STM32F4xx_HAL_RCC_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCCEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Types RCCEx Exported Types + * @{ + */ + +/** + * @brief RCC PLL configuration structure definition + */ +typedef struct +{ + uint32_t PLLState; /*!< The new state of the PLL. + This parameter can be a value of @ref RCC_PLL_Config */ + + uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. + This parameter must be a value of @ref RCC_PLL_Clock_Source */ + + uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. + This parameter must be a number between Min_Data = 0 and Max_Data = 63 */ + + uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. + This parameter must be a number between Min_Data = 50 and Max_Data = 432 + except for STM32F411xE devices where the Min_Data = 192 */ + + uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK). + This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ + + uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks. + This parameter must be a number between Min_Data = 2 and Max_Data = 15 */ +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F469xx) ||\ + defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ + defined(STM32F413xx) || defined(STM32F423xx) + uint32_t PLLR; /*!< PLLR: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks. + This parameter is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx + and STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices. + This parameter must be a number between Min_Data = 2 and Max_Data = 7 */ +#endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ +}RCC_PLLInitTypeDef; + +#if defined(STM32F446xx) +/** + * @brief PLLI2S Clock structure definition + */ +typedef struct +{ + uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ + + uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. + This parameter must be a number between Min_Data = 50 and Max_Data = 432 */ + + uint32_t PLLI2SP; /*!< Specifies division factor for SPDIFRX Clock. + This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider */ + + uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 15. + This parameter will be used only when PLLI2S is selected as Clock Source SAI */ + + uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 7. + This parameter will be used only when PLLI2S is selected as Clock Source I2S */ +}RCC_PLLI2SInitTypeDef; + +/** + * @brief PLLSAI Clock structure definition + */ +typedef struct +{ + uint32_t PLLSAIM; /*!< Spcifies division factor for PLL VCO input clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ + + uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. + This parameter must be a number between Min_Data = 50 and Max_Data = 432 */ + + uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS, SDIO and RNG clocks. + This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */ + + uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 15. + This parameter will be used only when PLLSAI is selected as Clock Source SAI */ +}RCC_PLLSAIInitTypeDef; + +/** + * @brief RCC extended clocks structure definition + */ +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. + This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ + + RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters. + This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */ + + uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 32 + This parameter will be used only when PLLI2S is selected as Clock Source SAI */ + + uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 32 + This parameter will be used only when PLLSAI is selected as Clock Source SAI */ + + uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Source Selection. + This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ + + uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Source Selection. + This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */ + + uint32_t I2sApb1ClockSelection; /*!< Specifies I2S APB1 Clock Source Selection. + This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */ + + uint32_t I2sApb2ClockSelection; /*!< Specifies I2S APB2 Clock Source Selection. + This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection. + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection. + This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */ + + uint32_t CecClockSelection; /*!< Specifies CEC Clock Source Selection. + This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ + + uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection. + This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */ + + uint32_t SpdifClockSelection; /*!< Specifies SPDIFRX Clock Source Selection. + This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */ + + uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks. + This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */ + + uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection. + This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ +}RCC_PeriphCLKInitTypeDef; +#endif /* STM32F446xx */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +/** + * @brief RCC extended clocks structure definition + */ +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t I2SClockSelection; /*!< Specifies RTC Clock Source Selection. + This parameter can be a value of @ref RCCEx_I2S_APB_Clock_Source */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection. + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 Clock Source Selection. + This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ + + uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection. + This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */ + + uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection. + This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ +}RCC_PeriphCLKInitTypeDef; +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/** + * @brief PLLI2S Clock structure definition + */ +typedef struct +{ + uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ + + uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. + This parameter must be a number between Min_Data = 50 and Max_Data = 432 */ + + uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 15. + This parameter will be used only when PLLI2S is selected as Clock Source SAI */ + + uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 7. + This parameter will be used only when PLLI2S is selected as Clock Source I2S */ +}RCC_PLLI2SInitTypeDef; + +/** + * @brief RCC extended clocks structure definition + */ +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. + This parameter will be used only when PLLI2S is selected as Clock Source I2S */ + +#if defined(STM32F413xx) || defined(STM32F423xx) + uint32_t PLLDivR; /*!< Specifies the PLL division factor for SAI1 clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 32 + This parameter will be used only when PLL is selected as Clock Source SAI */ + + uint32_t PLLI2SDivR; /*!< Specifies the PLLI2S division factor for SAI1 clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 32 + This parameter will be used only when PLLI2S is selected as Clock Source SAI */ +#endif /* STM32F413xx || STM32F423xx */ + + uint32_t I2sApb1ClockSelection; /*!< Specifies I2S APB1 Clock Source Selection. + This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */ + + uint32_t I2sApb2ClockSelection; /*!< Specifies I2S APB2 Clock Source Selection. + This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection. + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection. + This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */ + + uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection. + This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */ + + uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks. + This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */ + + uint32_t Dfsdm1ClockSelection; /*!< Specifies DFSDM1 Clock Selection. + This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */ + + uint32_t Dfsdm1AudioClockSelection;/*!< Specifies DFSDM1 Audio Clock Selection. + This parameter can be a value of @ref RCCEx_DFSDM1_Audio_Clock_Source */ + +#if defined(STM32F413xx) || defined(STM32F423xx) + uint32_t Dfsdm2ClockSelection; /*!< Specifies DFSDM2 Clock Selection. + This parameter can be a value of @ref RCCEx_DFSDM2_Kernel_Clock_Source */ + + uint32_t Dfsdm2AudioClockSelection;/*!< Specifies DFSDM2 Audio Clock Selection. + This parameter can be a value of @ref RCCEx_DFSDM2_Audio_Clock_Source */ + + uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 Clock Source Selection. + This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ + + uint32_t SaiAClockSelection; /*!< Specifies SAI1_A Clock Prescalers Selection + This parameter can be a value of @ref RCCEx_SAI1_BlockA_Clock_Source */ + + uint32_t SaiBClockSelection; /*!< Specifies SAI1_B Clock Prescalers Selection + This parameter can be a value of @ref RCCEx_SAI1_BlockB_Clock_Source */ +#endif /* STM32F413xx || STM32F423xx */ + + uint32_t PLLI2SSelection; /*!< Specifies PLL I2S Clock Source Selection. + This parameter can be a value of @ref RCCEx_PLL_I2S_Clock_Source */ + + uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection. + This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ +}RCC_PeriphCLKInitTypeDef; +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) + +/** + * @brief PLLI2S Clock structure definition + */ +typedef struct +{ + uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. + This parameter must be a number between Min_Data = 50 and Max_Data = 432. + This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ + + uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 7. + This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ + + uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 15. + This parameter will be used only when PLLI2S is selected as Clock Source SAI */ +}RCC_PLLI2SInitTypeDef; + +/** + * @brief PLLSAI Clock structure definition + */ +typedef struct +{ + uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. + This parameter must be a number between Min_Data = 50 and Max_Data = 432. + This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ +#if defined(STM32F469xx) || defined(STM32F479xx) + uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS and SDIO clocks. + This parameter is only available in STM32F469xx/STM32F479xx devices. + This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */ +#endif /* STM32F469xx || STM32F479xx */ + + uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 15. + This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ + + uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock + This parameter must be a number between Min_Data = 2 and Max_Data = 7. + This parameter will be used only when PLLSAI is selected as Clock Source LTDC */ + +}RCC_PLLSAIInitTypeDef; + +/** + * @brief RCC extended clocks structure definition + */ +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. + This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ + + RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters. + This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */ + + uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 32 + This parameter will be used only when PLLI2S is selected as Clock Source SAI */ + + uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 32 + This parameter will be used only when PLLSAI is selected as Clock Source SAI */ + + uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock. + This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection. + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection. + This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ +#if defined(STM32F469xx) || defined(STM32F479xx) + uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks. + This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */ + + uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection. + This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */ +#endif /* STM32F469xx || STM32F479xx */ +}RCC_PeriphCLKInitTypeDef; + +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) +/** + * @brief PLLI2S Clock structure definition + */ +typedef struct +{ +#if defined(STM32F411xE) + uint32_t PLLI2SM; /*!< PLLM: Division factor for PLLI2S VCO input clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 62 */ +#endif /* STM32F411xE */ + + uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. + This parameter must be a number between Min_Data = 50 and Max_Data = 432 + Except for STM32F411xE devices where the Min_Data = 192. + This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ + + uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 7. + This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ + +}RCC_PLLI2SInitTypeDef; + +/** + * @brief RCC extended clocks structure definition + */ +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. + This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection. + This parameter can be a value of @ref RCC_RTC_Clock_Source */ +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) + uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection. + This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ +#endif /* STM32F401xC || STM32F401xE || STM32F411xE */ +}RCC_PeriphCLKInitTypeDef; +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants + * @{ + */ + +/** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection + * @{ + */ +/* Peripheral Clock source for STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx */ +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ + defined(STM32F413xx) || defined(STM32F423xx) +#define RCC_PERIPHCLK_I2S_APB1 0x00000001U +#define RCC_PERIPHCLK_I2S_APB2 0x00000002U +#define RCC_PERIPHCLK_TIM 0x00000004U +#define RCC_PERIPHCLK_RTC 0x00000008U +#define RCC_PERIPHCLK_FMPI2C1 0x00000010U +#define RCC_PERIPHCLK_CLK48 0x00000020U +#define RCC_PERIPHCLK_SDIO 0x00000040U +#define RCC_PERIPHCLK_PLLI2S 0x00000080U +#define RCC_PERIPHCLK_DFSDM1 0x00000100U +#define RCC_PERIPHCLK_DFSDM1_AUDIO 0x00000200U +#endif /* STM32F412Zx || STM32F412Vx) || STM32F412Rx || STM32F412Cx */ +#if defined(STM32F413xx) || defined(STM32F423xx) +#define RCC_PERIPHCLK_DFSDM2 0x00000400U +#define RCC_PERIPHCLK_DFSDM2_AUDIO 0x00000800U +#define RCC_PERIPHCLK_LPTIM1 0x00001000U +#define RCC_PERIPHCLK_SAIA 0x00002000U +#define RCC_PERIPHCLK_SAIB 0x00004000U +#endif /* STM32F413xx || STM32F423xx */ +/*----------------------------------------------------------------------------*/ + +/*------------------- Peripheral Clock source for STM32F410xx ----------------*/ +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +#define RCC_PERIPHCLK_I2S 0x00000001U +#define RCC_PERIPHCLK_TIM 0x00000002U +#define RCC_PERIPHCLK_RTC 0x00000004U +#define RCC_PERIPHCLK_FMPI2C1 0x00000008U +#define RCC_PERIPHCLK_LPTIM1 0x00000010U +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ +/*----------------------------------------------------------------------------*/ + +/*------------------- Peripheral Clock source for STM32F446xx ----------------*/ +#if defined(STM32F446xx) +#define RCC_PERIPHCLK_I2S_APB1 0x00000001U +#define RCC_PERIPHCLK_I2S_APB2 0x00000002U +#define RCC_PERIPHCLK_SAI1 0x00000004U +#define RCC_PERIPHCLK_SAI2 0x00000008U +#define RCC_PERIPHCLK_TIM 0x00000010U +#define RCC_PERIPHCLK_RTC 0x00000020U +#define RCC_PERIPHCLK_CEC 0x00000040U +#define RCC_PERIPHCLK_FMPI2C1 0x00000080U +#define RCC_PERIPHCLK_CLK48 0x00000100U +#define RCC_PERIPHCLK_SDIO 0x00000200U +#define RCC_PERIPHCLK_SPDIFRX 0x00000400U +#define RCC_PERIPHCLK_PLLI2S 0x00000800U +#endif /* STM32F446xx */ +/*-----------------------------------------------------------------------------*/ + +/*----------- Peripheral Clock source for STM32F469xx/STM32F479xx -------------*/ +#if defined(STM32F469xx) || defined(STM32F479xx) +#define RCC_PERIPHCLK_I2S 0x00000001U +#define RCC_PERIPHCLK_SAI_PLLI2S 0x00000002U +#define RCC_PERIPHCLK_SAI_PLLSAI 0x00000004U +#define RCC_PERIPHCLK_LTDC 0x00000008U +#define RCC_PERIPHCLK_TIM 0x00000010U +#define RCC_PERIPHCLK_RTC 0x00000020U +#define RCC_PERIPHCLK_PLLI2S 0x00000040U +#define RCC_PERIPHCLK_CLK48 0x00000080U +#define RCC_PERIPHCLK_SDIO 0x00000100U +#endif /* STM32F469xx || STM32F479xx */ +/*----------------------------------------------------------------------------*/ + +/*-------- Peripheral Clock source for STM32F42xxx/STM32F43xxx ---------------*/ +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +#define RCC_PERIPHCLK_I2S 0x00000001U +#define RCC_PERIPHCLK_SAI_PLLI2S 0x00000002U +#define RCC_PERIPHCLK_SAI_PLLSAI 0x00000004U +#define RCC_PERIPHCLK_LTDC 0x00000008U +#define RCC_PERIPHCLK_TIM 0x00000010U +#define RCC_PERIPHCLK_RTC 0x00000020U +#define RCC_PERIPHCLK_PLLI2S 0x00000040U +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +/*----------------------------------------------------------------------------*/ + +/*-------- Peripheral Clock source for STM32F40xxx/STM32F41xxx ---------------*/ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) +#define RCC_PERIPHCLK_I2S 0x00000001U +#define RCC_PERIPHCLK_RTC 0x00000002U +#define RCC_PERIPHCLK_PLLI2S 0x00000004U +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */ +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) +#define RCC_PERIPHCLK_TIM 0x00000008U +#endif /* STM32F401xC || STM32F401xE || STM32F411xE */ +/*----------------------------------------------------------------------------*/ +/** + * @} + */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) || \ + defined(STM32F479xx) +/** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source + * @{ + */ +#define RCC_I2SCLKSOURCE_PLLI2S 0x00000000U +#define RCC_I2SCLKSOURCE_EXT 0x00000001U +/** + * @} + */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || + STM32F401xC || STM32F401xE || STM32F411xE || STM32F469xx || STM32F479xx */ + +/** @defgroup RCCEx_PLLSAI_DIVR RCC PLLSAI DIVR + * @{ + */ +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) +#define RCC_PLLSAIDIVR_2 0x00000000U +#define RCC_PLLSAIDIVR_4 0x00010000U +#define RCC_PLLSAIDIVR_8 0x00020000U +#define RCC_PLLSAIDIVR_16 0x00030000U +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ +/** + * @} + */ + +/** @defgroup RCCEx_PLLI2SP_Clock_Divider RCC PLLI2SP Clock Divider + * @{ + */ +#if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ + defined(STM32F412Rx) || defined(STM32F412Cx) +#define RCC_PLLI2SP_DIV2 0x00000002U +#define RCC_PLLI2SP_DIV4 0x00000004U +#define RCC_PLLI2SP_DIV6 0x00000006U +#define RCC_PLLI2SP_DIV8 0x00000008U +#endif /* STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ +/** + * @} + */ + +/** @defgroup RCCEx_PLLSAIP_Clock_Divider RCC PLLSAIP Clock Divider + * @{ + */ +#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +#define RCC_PLLSAIP_DIV2 0x00000002U +#define RCC_PLLSAIP_DIV4 0x00000004U +#define RCC_PLLSAIP_DIV6 0x00000006U +#define RCC_PLLSAIP_DIV8 0x00000008U +#endif /* STM32F446xx || STM32F469xx || STM32F479xx */ +/** + * @} + */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) +/** @defgroup RCCEx_SAI_BlockA_Clock_Source RCC SAI BlockA Clock Source + * @{ + */ +#define RCC_SAIACLKSOURCE_PLLSAI 0x00000000U +#define RCC_SAIACLKSOURCE_PLLI2S 0x00100000U +#define RCC_SAIACLKSOURCE_EXT 0x00200000U +/** + * @} + */ + +/** @defgroup RCCEx_SAI_BlockB_Clock_Source RCC SAI BlockB Clock Source + * @{ + */ +#define RCC_SAIBCLKSOURCE_PLLSAI 0x00000000U +#define RCC_SAIBCLKSOURCE_PLLI2S 0x00400000U +#define RCC_SAIBCLKSOURCE_EXT 0x00800000U +/** + * @} + */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F469xx) || defined(STM32F479xx) +/** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source + * @{ + */ +#define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U +#define RCC_CLK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR_CK48MSEL) +/** + * @} + */ + +/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source + * @{ + */ +#define RCC_SDIOCLKSOURCE_CLK48 0x00000000U +#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_SDIOSEL) +/** + * @} + */ + +/** @defgroup RCCEx_DSI_Clock_Source RCC DSI Clock Source + * @{ + */ +#define RCC_DSICLKSOURCE_DSIPHY 0x00000000U +#define RCC_DSICLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_DSISEL) +/** + * @} + */ +#endif /* STM32F469xx || STM32F479xx */ + +#if defined(STM32F446xx) +/** @defgroup RCCEx_SAI1_Clock_Source RCC SAI1 Clock Source + * @{ + */ +#define RCC_SAI1CLKSOURCE_PLLSAI 0x00000000U +#define RCC_SAI1CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI1SRC_0) +#define RCC_SAI1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1SRC_1) +#define RCC_SAI1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1SRC) +/** + * @} + */ + +/** @defgroup RCCEx_SAI2_Clock_Source RCC SAI2 Clock Source + * @{ + */ +#define RCC_SAI2CLKSOURCE_PLLSAI 0x00000000U +#define RCC_SAI2CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI2SRC_0) +#define RCC_SAI2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI2SRC_1) +#define RCC_SAI2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI2SRC) +/** + * @} + */ + +/** @defgroup RCCEx_I2SAPB1_Clock_Source RCC I2S APB1 Clock Source + * @{ + */ +#define RCC_I2SAPB1CLKSOURCE_PLLI2S 0x00000000U +#define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0) +#define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1) +#define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC) +/** + * @} + */ + +/** @defgroup RCCEx_I2SAPB2_Clock_Source RCC I2S APB2 Clock Source + * @{ + */ +#define RCC_I2SAPB2CLKSOURCE_PLLI2S 0x00000000U +#define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0) +#define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1) +#define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC) +/** + * @} + */ + +/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source + * @{ + */ +#define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U +#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0) +#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1) +/** + * @} + */ + +/** @defgroup RCCEx_CEC_Clock_Source RCC CEC Clock Source + * @{ + */ +#define RCC_CECCLKSOURCE_HSI 0x00000000U +#define RCC_CECCLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_CECSEL) +/** + * @} + */ + +/** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source + * @{ + */ +#define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U +#define RCC_CLK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR2_CK48MSEL) +/** + * @} + */ + +/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source + * @{ + */ +#define RCC_SDIOCLKSOURCE_CLK48 0x00000000U +#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL) +/** + * @} + */ + +/** @defgroup RCCEx_SPDIFRX_Clock_Source RCC SPDIFRX Clock Source + * @{ + */ +#define RCC_SPDIFRXCLKSOURCE_PLLR 0x00000000U +#define RCC_SPDIFRXCLKSOURCE_PLLI2SP ((uint32_t)RCC_DCKCFGR2_SPDIFRXSEL) +/** + * @} + */ + +#endif /* STM32F446xx */ + +#if defined(STM32F413xx) || defined(STM32F423xx) +/** @defgroup RCCEx_SAI1_BlockA_Clock_Source RCC SAI BlockA Clock Source + * @{ + */ +#define RCC_SAIACLKSOURCE_PLLI2SR 0x00000000U +#define RCC_SAIACLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0) +#define RCC_SAIACLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1ASRC_1) +#define RCC_SAIACLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0 | RCC_DCKCFGR_SAI1ASRC_1) +/** + * @} + */ + +/** @defgroup RCCEx_SAI1_BlockB_Clock_Source RCC SAI BlockB Clock Source + * @{ + */ +#define RCC_SAIBCLKSOURCE_PLLI2SR 0x00000000U +#define RCC_SAIBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0) +#define RCC_SAIBCLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1BSRC_1) +#define RCC_SAIBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0 | RCC_DCKCFGR_SAI1BSRC_1) +/** + * @} + */ + +/** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source + * @{ + */ +#define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U +#define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0) +#define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1) +#define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1) +/** + * @} + */ + + +/** @defgroup RCCEx_DFSDM2_Audio_Clock_Source RCC DFSDM2 Audio Clock Source + * @{ + */ +#define RCC_DFSDM2AUDIOCLKSOURCE_I2S1 0x00000000U +#define RCC_DFSDM2AUDIOCLKSOURCE_I2S2 ((uint32_t)RCC_DCKCFGR_CKDFSDM2ASEL) +/** + * @} + */ + +/** @defgroup RCCEx_DFSDM2_Kernel_Clock_Source RCC DFSDM2 Kernel Clock Source + * @{ + */ +#define RCC_DFSDM2CLKSOURCE_PCLK2 0x00000000U +#define RCC_DFSDM2CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL) +/** + * @} + */ + +#endif /* STM32F413xx || STM32F423xx */ + +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/** @defgroup RCCEx_PLL_I2S_Clock_Source PLL I2S Clock Source + * @{ + */ +#define RCC_PLLI2SCLKSOURCE_PLLSRC 0x00000000U +#define RCC_PLLI2SCLKSOURCE_EXT ((uint32_t)RCC_PLLI2SCFGR_PLLI2SSRC) +/** + * @} + */ + +/** @defgroup RCCEx_DFSDM1_Audio_Clock_Source RCC DFSDM1 Audio Clock Source + * @{ + */ +#define RCC_DFSDM1AUDIOCLKSOURCE_I2S1 0x00000000U +#define RCC_DFSDM1AUDIOCLKSOURCE_I2S2 ((uint32_t)RCC_DCKCFGR_CKDFSDM1ASEL) +/** + * @} + */ + +/** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source RCC DFSDM1 Kernel Clock Source + * @{ + */ +#define RCC_DFSDM1CLKSOURCE_PCLK2 0x00000000U +#define RCC_DFSDM1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL) +/** + * @} + */ + +/** @defgroup RCCEx_I2SAPB1_Clock_Source RCC I2S APB1 Clock Source + * @{ + */ +#define RCC_I2SAPB1CLKSOURCE_PLLI2S 0x00000000U +#define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0) +#define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1) +#define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC) +/** + * @} + */ + +/** @defgroup RCCEx_I2SAPB2_Clock_Source RCC I2S APB2 Clock Source + * @{ + */ +#define RCC_I2SAPB2CLKSOURCE_PLLI2S 0x00000000U +#define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0) +#define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1) +#define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC) +/** + * @} + */ + +/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source + * @{ + */ +#define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U +#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0) +#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1) +/** + * @} + */ + +/** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source + * @{ + */ +#define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U +#define RCC_CLK48CLKSOURCE_PLLI2SQ ((uint32_t)RCC_DCKCFGR2_CK48MSEL) +/** + * @} + */ + +/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source + * @{ + */ +#define RCC_SDIOCLKSOURCE_CLK48 0x00000000U +#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL) +/** + * @} + */ +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) + +/** @defgroup RCCEx_I2S_APB_Clock_Source RCC I2S APB Clock Source + * @{ + */ +#define RCC_I2SAPBCLKSOURCE_PLLR 0x00000000U +#define RCC_I2SAPBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2SSRC_0) +#define RCC_I2SAPBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2SSRC_1) +/** + * @} + */ + +/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source + * @{ + */ +#define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U +#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0) +#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1) +/** + * @} + */ + +/** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source + * @{ + */ +#define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U +#define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0) +#define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1) +#define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1) +/** + * @} + */ +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ + defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ + defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ + defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/** @defgroup RCCEx_TIM_PRescaler_Selection RCC TIM PRescaler Selection + * @{ + */ +#define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00) +#define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01) +/** + * @} + */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\ + STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ + STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\ + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\ + defined(STM32F423xx) +/** @defgroup RCCEx_LSE_Dual_Mode_Selection RCC LSE Dual Mode Selection + * @{ + */ +#define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00) +#define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01) +/** + * @} + */ +#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||\ + STM32F412Rx || STM32F412Cx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ + defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ + defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) +/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source + * @{ + */ +#define RCC_MCO2SOURCE_SYSCLK 0x00000000U +#define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0 +#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1 +#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2 +/** + * @} + */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || + STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || + STM32F412Rx || STM32F413xx | STM32F423xx */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source + * @{ + */ +#define RCC_MCO2SOURCE_SYSCLK 0x00000000U +#define RCC_MCO2SOURCE_I2SCLK RCC_CFGR_MCO2_0 +#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1 +#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2 +/** + * @} + */ +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros + * @{ + */ +/*------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx --------*/ +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) +/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable + * @brief Enables or disables the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOK_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) +#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) +#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) +#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) +#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN)) +#define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN)) +#define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN)) +#define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN)) +#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN)) +#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN)) +#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN)) +#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN)) +#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN)) +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN)) +#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) +#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) +#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) + +/** + * @brief Enable ETHERNET clock. + */ +#define __HAL_RCC_ETH_CLK_ENABLE() do { \ + __HAL_RCC_ETHMAC_CLK_ENABLE(); \ + __HAL_RCC_ETHMACTX_CLK_ENABLE(); \ + __HAL_RCC_ETHMACRX_CLK_ENABLE(); \ + } while(0U) +/** + * @brief Disable ETHERNET clock. + */ +#define __HAL_RCC_ETH_CLK_DISABLE() do { \ + __HAL_RCC_ETHMACTX_CLK_DISABLE(); \ + __HAL_RCC_ETHMACRX_CLK_DISABLE(); \ + __HAL_RCC_ETHMAC_CLK_DISABLE(); \ + } while(0U) +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) +#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) +#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) +#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) +#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET) +#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET) +#define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET) +#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET) +#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET) +#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET) +#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET) +#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET) +#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET) +#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET) +#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET) +#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET) +#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) +#define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \ + __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \ + __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()) + +#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) +#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) +#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) +#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) +#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET) +#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET) +#define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET) +#define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET) +#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET) +#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET) +#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET) +#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET) +#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET) +#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET) +#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET) +#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) +#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) +#define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \ + __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \ + __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + #define __HAL_RCC_DCMI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) + +#if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) +#define __HAL_RCC_CRYP_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_HASH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN)) +#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN)) +#endif /* STM32F437xx || STM32F439xx || STM32F479xx */ + +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ + __HAL_RCC_SYSCFG_CLK_ENABLE();\ + }while(0U) + +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) + +#define __HAL_RCC_RNG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET) +#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) + +#if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) +#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET) +#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET) + +#define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET) +#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET) +#endif /* STM32F437xx || STM32F439xx || STM32F479xx */ + +#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) +#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) + +#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) +#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable + * @brief Enables or disables the AHB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_FMC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN)) +#if defined(STM32F469xx) || defined(STM32F479xx) +#define __HAL_RCC_QSPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN)) +#endif /* STM32F469xx || STM32F479xx */ +/** + * @} + */ + + +/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET) +#define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET) +#if defined(STM32F469xx) || defined(STM32F479xx) +#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET) +#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET) +#endif /* STM32F469xx || STM32F479xx */ +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable + * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM13_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USART3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_UART4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_UART5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CAN1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CAN2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_DAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_UART7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_UART8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_I2C3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) +#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) +#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) +#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) +#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) +#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) +#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) +#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) +#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) +#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) +#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) +#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) +#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) +#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) +#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) +#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) +#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN)) +#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) +#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) +#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) +#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) +#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) +#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) +#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) +#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) +#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) +#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) +#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) +#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) +#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) +#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) +#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) +#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) +#define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET) +#define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET) + +#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) +#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) +#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) +#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) +#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) +#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) +#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) +#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) +#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) +#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) +#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) +#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) +#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) +#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) +#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) +#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) +#define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET) +#define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable + * @brief Enable or disable the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_ADC2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_ADC3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SAI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SDIO_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM10_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) +#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) +#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) +#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) +#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) +#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) +#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) +#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN)) +#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) + +#if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) +#define __HAL_RCC_LTDC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN)) +#endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F469xx) || defined(STM32F479xx) +#define __HAL_RCC_DSI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN)) +#endif /* STM32F469xx || STM32F479xx */ +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) +#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) +#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) +#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) +#define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET) +#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET) +#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) +#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) +#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))!= RESET) + +#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) +#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) +#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))== RESET) +#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) +#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) +#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) +#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET) +#define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET) +#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET) + +#if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) +#define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET) +#define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET) +#endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F469xx) || defined(STM32F479xx) +#define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET) +#define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET) +#endif /* STM32F469xx || STM32F479xx */ +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset + * @brief Force or release AHB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) +#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) +#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) +#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) +#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST)) +#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST)) +#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST)) +#define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST)) +#define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST)) +#define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST)) +#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) + +#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) +#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) +#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) +#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) +#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST)) +#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST)) +#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST)) +#define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST)) +#define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST)) +#define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST)) +#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset + * @brief Force or release AHB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) +#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) +#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) + +#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) +#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) +#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) + +#if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) +#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST)) +#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST)) + +#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST)) +#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST)) +#endif /* STM32F437xx || STM32F439xx || STM32F479xx */ +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset + * @brief Force or release AHB3 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) +#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST)) +#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST)) + +#if defined(STM32F469xx) || defined(STM32F479xx) +#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) +#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST)) +#endif /* STM32F469xx || STM32F479xx */ +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) +#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) +#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) +#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) +#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) +#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) +#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) +#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) +#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) +#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST)) +#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST)) +#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) + +#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) +#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) +#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) +#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) +#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) +#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) +#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) +#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) +#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) +#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) +#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST)) +#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset + * @brief Force or release APB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) +#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) +#define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST)) +#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) +#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) +#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) + +#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) +#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) +#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) +#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) +#define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST)) +#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) + +#if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) +#define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST)) +#define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST)) +#endif /* STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F469xx) || defined(STM32F479xx) +#define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DSIRST)) +#define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST)) +#endif /* STM32F469xx || STM32F479xx */ +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) +#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) +#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) +#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN)) +#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) +#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN)) +#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN)) +#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN)) +#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN)) +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN)) +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN)) +#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN)) +#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN)) +#define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM3LPEN)) +#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) +#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN)) + +#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) +#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) +#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) +#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN)) +#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) +#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN)) +#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN)) +#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN)) +#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN)) +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN)) +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN)) +#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN)) +#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN)) +#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) +#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) + +#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) +#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) + +#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) +#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) + +#if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) +#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) +#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) + +#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN)) +#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN)) +#endif /* STM32F437xx || STM32F439xx || STM32F479xx */ +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN)) +#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN)) + +#if defined(STM32F469xx) || defined(STM32F479xx) +#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) +#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN)) +#endif /* STM32F469xx || STM32F479xx */ +/** + * @} + */ + +/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) +#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) +#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) +#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) +#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) +#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) +#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) +#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) +#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) +#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) +#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) +#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN)) +#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN)) +#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) + +#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) +#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) +#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) +#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) +#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) +#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) +#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) +#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) +#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) +#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) +#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) +#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) +#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN)) +#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) +#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN)) +#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN)) +#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) +#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN)) +#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) +#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) + +#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) +#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) +#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN)) +#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN)) +#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) +#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN)) +#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) + +#if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) +#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN)) + +#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN)) +#endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F469xx) || defined(STM32F479xx) +#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DSILPEN)) +#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN)) +#endif /* STM32F469xx || STM32F479xx */ +/** + * @} + */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */ +/*----------------------------------------------------------------------------*/ + +/*----------------------------------- STM32F40xxx/STM32F41xxx-----------------*/ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) +/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable + * @brief Enables or disables the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) +#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) +#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) +#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) +#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN)) +#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN)) +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN)) +#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) +#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) +#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) +#if defined(STM32F407xx)|| defined(STM32F417xx) +/** + * @brief Enable ETHERNET clock. + */ +#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_ETH_CLK_ENABLE() do { \ + __HAL_RCC_ETHMAC_CLK_ENABLE(); \ + __HAL_RCC_ETHMACTX_CLK_ENABLE(); \ + __HAL_RCC_ETHMACRX_CLK_ENABLE(); \ + } while(0U) + +/** + * @brief Disable ETHERNET clock. + */ +#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN)) +#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN)) +#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN)) +#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN)) +#define __HAL_RCC_ETH_CLK_DISABLE() do { \ + __HAL_RCC_ETHMACTX_CLK_DISABLE(); \ + __HAL_RCC_ETHMACRX_CLK_DISABLE(); \ + __HAL_RCC_ETHMAC_CLK_DISABLE(); \ + } while(0U) +#endif /* STM32F407xx || STM32F417xx */ +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET) +#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET) +#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) +#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) +#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) +#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET) +#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) +#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) +#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET) +#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET) + +#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) +#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) +#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) +#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) +#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET) +#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET) +#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN))== RESET) +#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET) +#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) +#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) +#if defined(STM32F407xx)|| defined(STM32F417xx) +/** + * @brief Enable ETHERNET clock. + */ +#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET) +#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET) +#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET) +#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET) +#define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \ + __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \ + __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()) +/** + * @brief Disable ETHERNET clock. + */ +#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET) +#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET) +#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET) +#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET) +#define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \ + __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \ + __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()) +#endif /* STM32F407xx || STM32F417xx */ +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ + __HAL_RCC_SYSCFG_CLK_ENABLE();\ + }while(0U) + +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) + +#define __HAL_RCC_RNG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) + +#if defined(STM32F407xx)|| defined(STM32F417xx) +#define __HAL_RCC_DCMI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) +#endif /* STM32F407xx || STM32F417xx */ + +#if defined(STM32F415xx) || defined(STM32F417xx) +#define __HAL_RCC_CRYP_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_HASH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN)) +#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN)) +#endif /* STM32F415xx || STM32F417xx */ +/** + * @} + */ + + +/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) +#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) + +#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) +#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) + +#if defined(STM32F407xx)|| defined(STM32F417xx) +#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET) +#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) +#endif /* STM32F407xx || STM32F417xx */ + +#if defined(STM32F415xx) || defined(STM32F417xx) +#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET) +#define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET) + +#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET) +#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET) +#endif /* STM32F415xx || STM32F417xx */ +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable + * @brief Enables or disables the AHB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_FSMC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET) +#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable + * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM13_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USART3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_UART4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_UART5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CAN1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CAN2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_DAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_I2C3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) +#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) +#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) +#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) +#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) +#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) +#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) +#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) +#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) +#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) +#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) +#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) +#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) +#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) +#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) +#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) +#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) +#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) +#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) +#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) +#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) +#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) +#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) +#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) +#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) +#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) +#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) +#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) +#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) +#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) +#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) + +#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) +#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) +#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) +#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) +#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) +#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) +#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) +#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) +#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) +#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) +#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) +#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) +#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) +#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) +#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) +#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) + /** + * @} + */ + +/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable + * @brief Enable or disable the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_ADC2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_ADC3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SDIO_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM10_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) +#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) +#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) +#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) +#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) +#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) +#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) +#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) +#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) +#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) +#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) + +#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) +#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) +#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) +#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) +#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) +#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset + * @brief Force or release AHB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) +#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) +#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) +#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) +#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST)) +#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST)) +#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST)) +#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) + +#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) +#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) +#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) +#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) +#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST)) +#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST)) +#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST)) +#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset + * @brief Force or release AHB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) + +#if defined(STM32F407xx)|| defined(STM32F417xx) +#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) +#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) +#endif /* STM32F407xx || STM32F417xx */ + +#if defined(STM32F415xx) || defined(STM32F417xx) +#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST)) +#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST)) + +#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST)) +#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST)) +#endif /* STM32F415xx || STM32F417xx */ + +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) + +#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) +#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset + * @brief Force or release AHB3 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) + +#define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST)) +#define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST)) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) +#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) +#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) +#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) +#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) +#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) +#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) +#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) +#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) +#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) + +#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) +#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) +#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) +#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) +#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) +#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) +#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) +#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) +#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) +#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset + * @brief Force or release APB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) +#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) +#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) + +#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) +#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) +#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) +#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) +#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) +#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN)) +#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) +#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN)) +#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN)) +#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN)) +#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN)) +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN)) +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) +#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN)) + +#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) +#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) +#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) +#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN)) +#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) +#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN)) +#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN)) +#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN)) +#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN)) +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN)) +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) +#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) + +#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) +#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) + +#if defined(STM32F407xx)|| defined(STM32F417xx) +#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) +#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) +#endif /* STM32F407xx || STM32F417xx */ + +#if defined(STM32F415xx) || defined(STM32F417xx) +#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) +#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) + +#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN)) +#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN)) +#endif /* STM32F415xx || STM32F417xx */ +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN)) +#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) +#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) +#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) +#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) +#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) +#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) +#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) +#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) +#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) +#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) +#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) +#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) + +#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) +#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) +#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) +#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) +#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) +#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) +#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) +#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) +#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) +#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) +#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) +#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) +#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN)) +#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN)) +#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) + +#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) +#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) +#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN)) +#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN)) +/** + * @} + */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ +/*----------------------------------------------------------------------------*/ + +/*------------------------- STM32F401xE/STM32F401xC --------------------------*/ +#if defined(STM32F401xC) || defined(STM32F401xE) +/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) +#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) +#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) +#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) +#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) +#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) +#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET) + +#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) +#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) +#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) +#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ + __HAL_RCC_SYSCFG_CLK_ENABLE();\ + }while(0U) + +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) +#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable + * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_I2C3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) +#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) +#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) +#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) +#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) +#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) +#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) +#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) +#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) + +#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) +#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) +#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) +#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) +#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable + * @brief Enable or disable the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_SDIO_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM10_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) +#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) +#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) +#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) +#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) + +#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) +#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) +#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) +/** + * @} + */ +/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset + * @brief Force or release AHB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) +#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) +#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) + +#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U) +#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) +#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) +#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset + * @brief Force or release AHB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) + +#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) + +#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U) +#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset + * @brief Force or release APB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) +#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) + +#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U) +#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) +#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset + * @brief Force or release AHB3 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) + +#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) + +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) + +#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) + +#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) +/** + * @} + */ +#endif /* STM32F401xC || STM32F401xE*/ +/*----------------------------------------------------------------------------*/ + +/*-------------------------------- STM32F410xx -------------------------------*/ +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable + * @brief Enables or disables the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_RNG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) +#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_RNGEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) +#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) != RESET) + +#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) +#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable + * @brief Enable or disable the High Speed APB (APB1) peripheral clock. + * @{ + */ +#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_DAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) +#define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN)) +#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN)) +#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN)) +#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) +#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET) +#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET) +#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET) +#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) + +#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) +#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET) +#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET) +#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET) +#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable + * @brief Enable or disable the High Speed APB (APB2) peripheral clock. + * @{ + */ +#define __HAL_RCC_SPI5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_EXTIT_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) +#define __HAL_RCC_EXTIT_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) +#define __HAL_RCC_EXTIT_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET) + +#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET) +#define __HAL_RCC_EXTIT_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset + * @brief Force or release AHB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) +#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_RNGRST)) +#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) +#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_RNGRST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset + * @brief Force or release AHB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB2_FORCE_RESET() +#define __HAL_RCC_AHB2_RELEASE_RESET() +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset + * @brief Force or release AHB3 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB3_FORCE_RESET() +#define __HAL_RCC_AHB3_RELEASE_RESET() +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST)) +#define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST)) +#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) + +#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST)) +#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST)) +#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset + * @brief Force or release APB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) +#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_RNGLPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) + +#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_RNGLPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. + * @{ + */ +#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) +#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN)) +#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCAPBLPEN)) +#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN)) +#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) + +#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) +#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN)) +#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN)) +#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN)) +#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. + * @{ + */ +#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) +#define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_EXTITLPEN)) +#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) +#define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN)) +/** + * @} + */ + +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ +/*----------------------------------------------------------------------------*/ + +/*-------------------------------- STM32F411xx -------------------------------*/ +#if defined(STM32F411xE) +/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable + * @brief Enables or disables the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) +#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) +#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) +#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) +#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) +#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET) +#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) + +#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) +#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) +#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) +#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEX_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ + __HAL_RCC_SYSCFG_CLK_ENABLE();\ + }while(0U) + +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) +#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable + * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_I2C3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) +#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) +#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) +#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) +#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) +#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) +#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) +#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) +#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) + +#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) +#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) +#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) +#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) +#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable + * @brief Enable or disable the High Speed APB (APB2) peripheral clock. + * @{ + */ +#define __HAL_RCC_SPI5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SDIO_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM10_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) +#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) +#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) +#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) +#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) +#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) +#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) + +#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) +#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) +#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) +#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset + * @brief Force or release AHB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) +#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) +#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) + +#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) +#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) +#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset + * @brief Force or release AHB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) + +#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset + * @brief Force or release AHB3 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) + +#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset + * @brief Force or release APB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) +#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) +#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) + +#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) +#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) +#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) + +#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. + * @{ + */ +#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) + +#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. + * @{ + */ +#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) +#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) + +#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) +#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) +/** + * @} + */ +#endif /* STM32F411xE */ +/*----------------------------------------------------------------------------*/ + +/*---------------------------------- STM32F446xx -----------------------------*/ +#if defined(STM32F446xx) +/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable + * @brief Enables or disables the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) +#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) +#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) +#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) +#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN)) +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN)) +#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) +#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) +#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) +#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) +#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) +#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) +#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET) +#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET) +#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET) +#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN))!= RESET) +#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) + +#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) +#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) +#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) +#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) +#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET) +#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET) +#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET) +#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) +#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_DCMI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ + __HAL_RCC_SYSCFG_CLK_ENABLE();\ + }while(0U) + +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) + +#define __HAL_RCC_RNG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET) +#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) + +#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) +#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) + +#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) +#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable + * @brief Enables or disables the AHB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_FMC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_QSPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN)) +#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET) +#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET) + +#define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET) +#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable + * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM13_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USART3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_UART4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_UART5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CAN1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CAN2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CEC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_DAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_I2C3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) +#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) +#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) +#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) +#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) +#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) +#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) +#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) +#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) +#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) +#define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN)) +#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) +#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) +#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) +#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN)) +#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) +#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) +#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) +#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) +#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) +#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) +#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) +#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) +#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) +#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) +#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) +#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) +#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) +#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET) +#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) +#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) +#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) +#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET) +#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) +#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) +#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET) +#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) + +#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) +#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) +#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) +#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) +#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) +#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) +#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) +#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) +#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) +#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) +#define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET) +#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) +#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) +#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) +#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET) +#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) +#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) +#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET) +#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable + * @brief Enable or disable the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_ADC2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_ADC3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SAI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SAI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SDIO_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM10_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) +#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) +#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) +#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) +#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) +#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) +#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) +#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) +#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) +#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) +#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) +#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) +#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) +#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET) +#define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET) + +#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) +#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) +#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) +#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) +#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) +#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) +#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET) +#define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset + * @brief Force or release AHB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) +#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) +#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) +#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) +#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST)) +#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) + +#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) +#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) +#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) +#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) +#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST)) +#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset + * @brief Force or release AHB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) +#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) +#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) + +#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) +#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) +#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset + * @brief Force or release AHB3 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) + +#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST)) +#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) + +#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST)) +#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST)) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) +#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) +#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) +#define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST)) +#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) +#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) +#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) +#define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST)) +#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) +#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) +#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) +#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) +#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) + +#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) +#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) +#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) +#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) +#define __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST)) +#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) +#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) +#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) +#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST)) +#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) +#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) +#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) +#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset + * @brief Force or release APB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) +#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) +#define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST)) +#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) +#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) + +#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) +#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) +#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) +#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) +#define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) +#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) +#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) +#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN)) +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) +#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN)) + +#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) +#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) +#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) +#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN)) +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) +#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) + +#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) +#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) + +#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) +#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN)) +#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) + +#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN)) +#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) +#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) +#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) +#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) +#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) +#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN)) +#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) +#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) +#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) +#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN)) +#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) +#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) +#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN)) +#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) +#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) + +#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) +#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) +#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) +#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) +#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) +#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) +#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN)) +#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) +#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) +#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) +#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN)) +#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) +#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) +#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN)) +#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) +#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN)) +#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN)) +#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) +#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN)) +#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) + +#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) +#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) +#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN)) +#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN)) +#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) +#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN)) +/** + * @} + */ + +#endif /* STM32F446xx */ +/*----------------------------------------------------------------------------*/ + +/*-------STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx-------*/ +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable + * @brief Enables or disables the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + UNUSED(tmpreg); \ + } while(0U) +#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ +#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + UNUSED(tmpreg); \ + } while(0U) +#endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ +#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ + UNUSED(tmpreg); \ + } while(0U) +#endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0U) +#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) +#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ +#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) +#endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ +#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) +#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) +#endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ +#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) +#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ +#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) +#endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ +#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) +#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) +#endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ +#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) + +#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) +#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ +#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) +#endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ +#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) +#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) +#endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ +#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#if defined(STM32F423xx) +#define __HAL_RCC_AES_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_AES_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_AESEN)) +#endif /* STM32F423xx */ + +#define __HAL_RCC_RNG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) + +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ + __HAL_RCC_SYSCFG_CLK_ENABLE();\ + }while(0U) + +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#if defined(STM32F423xx) +#define __HAL_RCC_AES_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) != RESET) +#define __HAL_RCC_AES_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) == RESET) +#endif /* STM32F423xx */ + +#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) +#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) + +#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) +#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable + * @brief Enables or disables the AHB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_FSMC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_QSPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN)) +#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN)) +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET) +#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET) + +#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET) +#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET) +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ + +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable + * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM13_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + UNUSED(tmpreg); \ + } while(0U) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\ + UNUSED(tmpreg); \ + } while(0U) +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_USART3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ + +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_UART4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_UART5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ + UNUSED(tmpreg); \ + } while(0U) +#endif /* STM32F413xx || STM32F423xx */ + +#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CAN1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CAN2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_CAN3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_I2C3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_DAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_UART7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_UART8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ + UNUSED(tmpreg); \ + } while(0U) +#endif /* STM32F413xx || STM32F423xx */ + +#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) +#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) +#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) +#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) +#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) +#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) +#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) +#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN)) +#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) +#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) +#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN)) +#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) +#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_CAN3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN)) +#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) +#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN)) +#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN)) +#endif /* STM32F413xx || STM32F423xx */ + +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) +#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) +#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) +#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) +#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) +#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) +#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) +#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET) +#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx | STM32F423xx */ +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) +#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) +#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET) +#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN))!= RESET) +#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_CAN3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) != RESET) +#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) +#define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET) +#define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET) +#endif /* STM32F413xx || STM32F423xx */ + +#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) +#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) +#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) +#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) +#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) +#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) +#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) +#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET) +#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx | STM32F423xx */ +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) +#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) +#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET) +#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) +#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_CAN3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) == RESET) +#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) +#define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET) +#define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET) +#endif /* STM32F413xx || STM32F423xx */ +/** + * @} + */ +/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable + * @brief Enable or disable the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ + UNUSED(tmpreg); \ + } while(0U) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_UART9_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_UART10_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART10EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART10EN);\ + UNUSED(tmpreg); \ + } while(0U) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_SDIO_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_EXTIT_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM10_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ + UNUSED(tmpreg); \ + } while(0U) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_SAI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_DFSDM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#endif /* STM32F413xx || STM32F423xx */ + +#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_UART9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_UART9EN)) +#define __HAL_RCC_UART10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_UART10EN)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) +#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) +#define __HAL_RCC_EXTIT_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN)) +#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) +#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_DFSDM2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM2EN)) +#endif /* STM32F413xx || STM32F423xx */ +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_UART9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART9EN)) != RESET) +#define __HAL_RCC_UART10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART10EN)) != RESET) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) +#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) +#define __HAL_RCC_EXTIT_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET) +#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) +#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_DFSDM2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM2EN)) != RESET) +#endif /* STM32F413xx || STM32F423xx */ + +#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_UART9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART9EN)) == RESET) +#define __HAL_RCC_UART10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART10EN)) == RESET) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) +#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) +#define __HAL_RCC_EXTIT_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET) +#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) +#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_DFSDM2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM2EN)) == RESET) +#endif /* STM32F413xx || STM32F423xx */ +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset + * @brief Force or release AHB1 peripheral reset. + * @{ + */ +#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) +#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ +#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) +#endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ +#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) +#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) +#endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ +#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) + +#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) +#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ +#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) +#endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ +#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) +#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) +#endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ +#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset + * @brief Force or release AHB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) + +#if defined(STM32F423xx) +#define __HAL_RCC_AES_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_AESRST)) +#define __HAL_RCC_AES_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_AESRST)) +#endif /* STM32F423xx */ + +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) + +#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) +#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset + * @brief Force or release AHB3 peripheral reset. + * @{ + */ +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) + +#define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST)) +#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) + +#define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST)) +#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST)) +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ +#if defined(STM32F412Cx) +#define __HAL_RCC_AHB3_FORCE_RESET() +#define __HAL_RCC_AHB3_RELEASE_RESET() + +#define __HAL_RCC_FSMC_FORCE_RESET() +#define __HAL_RCC_QSPI_FORCE_RESET() + +#define __HAL_RCC_FSMC_RELEASE_RESET() +#define __HAL_RCC_QSPI_RELEASE_RESET() +#endif /* STM32F412Cx */ +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) +#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) +#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) +#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) +#define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST)) +#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) +#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_CAN3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN3RST)) +#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) +#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST)) +#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST)) +#endif /* STM32F413xx || STM32F423xx */ + +#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) +#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) +#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) +#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) +#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST)) +#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) +#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_CAN3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN3RST)) +#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) +#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST)) +#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST)) +#endif /* STM32F413xx || STM32F423xx */ +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset + * @brief Force or release APB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_UART9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_UART9RST)) +#define __HAL_RCC_UART10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_UART10RST)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) +#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) +#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM1RST)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_DFSDM2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM2RST)) +#endif /* STM32F413xx || STM32F423xx */ + +#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_UART9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_UART9RST)) +#define __HAL_RCC_UART10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_UART10RST)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) +#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) +#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_DFSDM2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM2RST)) +#endif /* STM32F413xx || STM32F423xx */ +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) +#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) +#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) +#endif /* STM32F413xx || STM32F423xx */ + +#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) +#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) +#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) +#endif /* STM32F413xx || STM32F423xx */ +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#if defined(STM32F423xx) +#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AESLPEN)) +#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_AESLPEN)) +#endif /* STM32F423xx */ + +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) + +#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) +#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN)) +#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) + +#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN)) +#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN)) +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ + +/** + * @} + */ + +/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) +#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) +#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) +#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) +#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCAPBLPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) +#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) +#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN)) +#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) +#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_CAN3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN3LPEN)) +#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) +#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN)) +#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN)) +#endif /* STM32F413xx || STM32F423xx */ + +#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) +#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) +#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) +#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) +#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) +#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) +#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN)) +#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) +#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_CAN3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN3LPEN)) +#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) +#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN)) +#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN)) +#endif /* STM32F413xx || STM32F423xx */ +/** + * @} + */ + +/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_UART9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_UART9LPEN)) +#define __HAL_RCC_UART10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_UART10LPEN)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_EXTITLPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) +#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM1LPEN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_DFSDM2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM2LPEN)) +#endif /* STM32F413xx || STM32F423xx */ + +#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_UART9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_UART9LPEN)) +#define __HAL_RCC_UART10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_UART10LPEN)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) +#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_DFSDM2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM2LPEN)) +#endif /* STM32F413xx || STM32F423xx */ +/** + * @} + */ +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ +/*----------------------------------------------------------------------------*/ + +/*------------------------------- PLL Configuration --------------------------*/ +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ + defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/** @brief Macro to configure the main PLL clock source, multiplication and division factors. + * @note This function must be used only when the main PLL is disabled. + * @param __RCC_PLLSource__ specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry + * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry + * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. + * @param __PLLM__ specifies the division factor for PLL VCO input clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 63. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency + * of 2 MHz to limit PLL jitter. + * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. + * @note You have to set the PLLN parameter correctly to ensure that the VCO + * output frequency is between 100 and 432 MHz. + * + * @param __PLLP__ specifies the division factor for main system clock (SYSCLK) + * This parameter must be a number in the range {2, 4, 6, or 8}. + * + * @param __PLLQ__ specifies the division factor for OTG FS, SDIO and RNG clocks + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + * @note If the USB OTG FS is used in your application, you have to set the + * PLLQ parameter correctly to have 48 MHz clock for the USB. However, + * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work + * correctly. + * + * @param __PLLR__ PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks. + * This parameter must be a number between Min_Data = 2 and Max_Data = 7. + * @note This parameter is only available in STM32F446xx/STM32F469xx/STM32F479xx/ + STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices. + * + */ +#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \ + (RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__) | \ + ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ + ((((__PLLP__) >> 1U) -1U) << RCC_PLLCFGR_PLLP_Pos) | \ + ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos) | \ + ((__PLLR__) << RCC_PLLCFGR_PLLR_Pos))) +#else +/** @brief Macro to configure the main PLL clock source, multiplication and division factors. + * @note This function must be used only when the main PLL is disabled. + * @param __RCC_PLLSource__ specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry + * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry + * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. + * @param __PLLM__ specifies the division factor for PLL VCO input clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 63. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency + * of 2 MHz to limit PLL jitter. + * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock + * This parameter must be a number between Min_Data = 50 and Max_Data = 432 + * Except for STM32F411xE devices where Min_Data = 192. + * @note You have to set the PLLN parameter correctly to ensure that the VCO + * output frequency is between 100 and 432 MHz, Except for STM32F411xE devices + * where frequency is between 192 and 432 MHz. + * @param __PLLP__ specifies the division factor for main system clock (SYSCLK) + * This parameter must be a number in the range {2, 4, 6, or 8}. + * + * @param __PLLQ__ specifies the division factor for OTG FS, SDIO and RNG clocks + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + * @note If the USB OTG FS is used in your application, you have to set the + * PLLQ parameter correctly to have 48 MHz clock for the USB. However, + * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work + * correctly. + * + */ +#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \ + (RCC->PLLCFGR = (0x20000000U | (__RCC_PLLSource__) | (__PLLM__)| \ + ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ + ((((__PLLP__) >> 1U) -1U) << RCC_PLLCFGR_PLLP_Pos) | \ + ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos))) + #endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ +/*----------------------------------------------------------------------------*/ + +/*----------------------------PLLI2S Configuration ---------------------------*/ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ + defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ + defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) + +/** @brief Macros to enable or disable the PLLI2S. + * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE) +#define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE) + +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || + STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || + STM32F412Rx || STM32F412Cx */ +#if defined(STM32F446xx) +/** @brief Macro to configure the PLLI2S clock multiplication and division factors . + * @note This macro must be used only when the PLLI2S is disabled. + * @note PLLI2S clock source is common with the main PLL (configured in + * HAL_RCC_ClockConfig() API). + * @param __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 63. + * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency + * of 1 MHz to limit PLLI2S jitter. + * + * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. + * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO + * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. + * + * @param __PLLI2SP__ specifies division factor for SPDIFRX Clock. + * This parameter must be a number in the range {2, 4, 6, or 8}. + * @note the PLLI2SP parameter is only available with STM32F446xx Devices + * + * @param __PLLI2SR__ specifies the division factor for I2S clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 7. + * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz + * on the I2S clock frequency. + * + * @param __PLLI2SQ__ specifies the division factor for SAI clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + */ +#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \ + (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\ + ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ + ((((__PLLI2SP__) >> 1U) -1U) << RCC_PLLI2SCFGR_PLLI2SP_Pos) |\ + ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\ + ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))) +#elif defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ + defined(STM32F413xx) || defined(STM32F423xx) +/** @brief Macro to configure the PLLI2S clock multiplication and division factors . + * @note This macro must be used only when the PLLI2S is disabled. + * @note PLLI2S clock source is common with the main PLL (configured in + * HAL_RCC_ClockConfig() API). + * @param __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 63. + * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency + * of 1 MHz to limit PLLI2S jitter. + * + * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. + * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO + * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. + * + * @param __PLLI2SR__ specifies the division factor for I2S clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 7. + * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz + * on the I2S clock frequency. + * + * @param __PLLI2SQ__ specifies the division factor for SAI clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + */ +#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) \ + (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\ + ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ + ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\ + ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))) +#else +/** @brief Macro to configure the PLLI2S clock multiplication and division factors . + * @note This macro must be used only when the PLLI2S is disabled. + * @note PLLI2S clock source is common with the main PLL (configured in + * HAL_RCC_ClockConfig() API). + * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. + * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO + * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. + * + * @param __PLLI2SR__ specifies the division factor for I2S clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 7. + * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz + * on the I2S clock frequency. + * + */ +#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) \ + (RCC->PLLI2SCFGR = (((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ + ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))) +#endif /* STM32F446xx */ + +#if defined(STM32F411xE) +/** @brief Macro to configure the PLLI2S clock multiplication and division factors . + * @note This macro must be used only when the PLLI2S is disabled. + * @note This macro must be used only when the PLLI2S is disabled. + * @note PLLI2S clock source is common with the main PLL (configured in + * HAL_RCC_ClockConfig() API). + * @param __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 63. + * @note The PLLI2SM parameter is only used with STM32F411xE/STM32F410xx Devices + * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency + * of 2 MHz to limit PLLI2S jitter. + * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock + * This parameter must be a number between Min_Data = 192 and Max_Data = 432. + * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO + * output frequency is between Min_Data = 192 and Max_Data = 432 MHz. + * @param __PLLI2SR__ specifies the division factor for I2S clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 7. + * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz + * on the I2S clock frequency. + */ +#define __HAL_RCC_PLLI2S_I2SCLK_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\ + ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ + ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))) +#endif /* STM32F411xE */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) +/** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors. + * @note This macro must be used only when the PLLI2S is disabled. + * @note PLLI2S clock source is common with the main PLL (configured in + * HAL_RCC_ClockConfig() API) + * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock. + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. + * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO + * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. + * @param __PLLI2SQ__ specifies the division factor for SAI1 clock. + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + * @note the PLLI2SQ parameter is only available with STM32F427xx/437xx/429xx/439xx/469xx/479xx + * Devices and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro + * @param __PLLI2SR__ specifies the division factor for I2S clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 7. + * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz + * on the I2S clock frequency. + */ +#define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6U) |\ + ((__PLLI2SQ__) << 24U) |\ + ((__PLLI2SR__) << 28U)) +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ +/*----------------------------------------------------------------------------*/ + +/*------------------------------ PLLSAI Configuration ------------------------*/ +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +/** @brief Macros to Enable or Disable the PLLISAI. + * @note The PLLSAI is only available with STM32F429x/439x Devices. + * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLLSAI_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = ENABLE) +#define __HAL_RCC_PLLSAI_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = DISABLE) + +#if defined(STM32F446xx) +/** @brief Macro to configure the PLLSAI clock multiplication and division factors. + * + * @param __PLLSAIM__ specifies the division factor for PLLSAI VCO input clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 63. + * @note You have to set the PLLSAIM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency + * of 1 MHz to limit PLLI2S jitter. + * @note The PLLSAIM parameter is only used with STM32F446xx Devices + * + * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. + * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO + * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. + * + * @param __PLLSAIP__ specifies division factor for OTG FS, SDIO and RNG clocks. + * This parameter must be a number in the range {2, 4, 6, or 8}. + * @note the PLLSAIP parameter is only available with STM32F446xx Devices + * + * @param __PLLSAIQ__ specifies the division factor for SAI clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + * + * @param __PLLSAIR__ specifies the division factor for LTDC clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 7. + * @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices + */ +#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIM__, __PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \ + (RCC->PLLSAICFGR = ((__PLLSAIM__) | \ + ((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) | \ + ((((__PLLSAIP__) >> 1U) -1U) << RCC_PLLSAICFGR_PLLSAIP_Pos) | \ + ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos))) +#endif /* STM32F446xx */ + +#if defined(STM32F469xx) || defined(STM32F479xx) +/** @brief Macro to configure the PLLSAI clock multiplication and division factors. + * + * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. + * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO + * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. + * + * @param __PLLSAIP__ specifies division factor for SDIO and CLK48 clocks. + * This parameter must be a number in the range {2, 4, 6, or 8}. + * + * @param __PLLSAIQ__ specifies the division factor for SAI clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + * + * @param __PLLSAIR__ specifies the division factor for LTDC clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 7. + */ +#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \ + (RCC->PLLSAICFGR = (((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) |\ + ((((__PLLSAIP__) >> 1U) -1U) << RCC_PLLSAICFGR_PLLSAIP_Pos) |\ + ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos) |\ + ((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos))) +#endif /* STM32F469xx || STM32F479xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +/** @brief Macro to configure the PLLSAI clock multiplication and division factors. + * + * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. + * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO + * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. + * + * @param __PLLSAIQ__ specifies the division factor for SAI clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + * + * @param __PLLSAIR__ specifies the division factor for LTDC clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 7. + * @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices + */ +#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) \ + (RCC->PLLSAICFGR = (((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) | \ + ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos) | \ + ((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos))) +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ + +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ +/*----------------------------------------------------------------------------*/ + +/*------------------- PLLSAI/PLLI2S Dividers Configuration -------------------*/ +#if defined(STM32F413xx) || defined(STM32F423xx) +/** @brief Macro to configure the SAI clock Divider coming from PLLI2S. + * @note This function must be called before enabling the PLLI2S. + * @param __PLLI2SDivR__ specifies the PLLI2S division factor for SAI1 clock. + * This parameter must be a number between 1 and 32. + * SAI1 clock frequency = f(PLLI2SR) / __PLLI2SDivR__ + */ +#define __HAL_RCC_PLLI2S_PLLSAICLKDIVR_CONFIG(__PLLI2SDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR, (__PLLI2SDivR__)-1U)) + +/** @brief Macro to configure the SAI clock Divider coming from PLL. + * @param __PLLDivR__ specifies the PLL division factor for SAI1 clock. + * This parameter must be a number between 1 and 32. + * SAI1 clock frequency = f(PLLR) / __PLLDivR__ + */ +#define __HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(__PLLDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR, ((__PLLDivR__)-1U)<<8U)) +#endif /* STM32F413xx || STM32F423xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) +/** @brief Macro to configure the SAI clock Divider coming from PLLI2S. + * @note This function must be called before enabling the PLLI2S. + * @param __PLLI2SDivQ__ specifies the PLLI2S division factor for SAI1 clock. + * This parameter must be a number between 1 and 32. + * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__ + */ +#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1U)) + +/** @brief Macro to configure the SAI clock Divider coming from PLLSAI. + * @note This function must be called before enabling the PLLSAI. + * @param __PLLSAIDivQ__ specifies the PLLSAI division factor for SAI1 clock . + * This parameter must be a number between Min_Data = 1 and Max_Data = 32. + * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__ + */ +#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1U)<<8U)) +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) +/** @brief Macro to configure the LTDC clock Divider coming from PLLSAI. + * + * @note The LTDC peripheral is only available with STM32F427/437/429/439/469/479xx Devices. + * @note This function must be called before enabling the PLLSAI. + * @param __PLLSAIDivR__ specifies the PLLSAI division factor for LTDC clock . + * This parameter must be a number between Min_Data = 2 and Max_Data = 16. + * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__ + */ +#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__))) +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ +/*----------------------------------------------------------------------------*/ + +/*------------------------- Peripheral Clock selection -----------------------*/ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) ||\ + defined(STM32F479xx) +/** @brief Macro to configure the I2S clock source (I2SCLK). + * @note This function must be called before enabling the I2S APB clock. + * @param __SOURCE__ specifies the I2S clock source. + * This parameter can be one of the following values: + * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source. + * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin + * used as I2S clock source. + */ +#define __HAL_RCC_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_CFGR_I2SSRC_BB = (__SOURCE__)) + + +/** @brief Macro to get the I2S clock source (I2SCLK). + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source. + * @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin + * used as I2S clock source + */ +#define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC))) +#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) + +/** @brief Macro to configure SAI1BlockA clock source selection. + * @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices. + * @note This function must be called before enabling PLLSAI, PLLI2S and + * the SAI clock. + * @param __SOURCE__ specifies the SAI Block A clock source. + * This parameter can be one of the following values: + * @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used + * as SAI1 Block A clock. + * @arg RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used + * as SAI1 Block A clock. + * @arg RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin + * used as SAI1 Block A clock. + */ +#define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__))) + +/** @brief Macro to configure SAI1BlockB clock source selection. + * @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices. + * @note This function must be called before enabling PLLSAI, PLLI2S and + * the SAI clock. + * @param __SOURCE__ specifies the SAI Block B clock source. + * This parameter can be one of the following values: + * @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used + * as SAI1 Block B clock. + * @arg RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used + * as SAI1 Block B clock. + * @arg RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin + * used as SAI1 Block B clock. + */ +#define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__))) +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F446xx) +/** @brief Macro to configure SAI1 clock source selection. + * @note This configuration is only available with STM32F446xx Devices. + * @note This function must be called before enabling PLL, PLLSAI, PLLI2S and + * the SAI clock. + * @param __SOURCE__ specifies the SAI1 clock source. + * This parameter can be one of the following values: + * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock. + * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock. + * @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock. + * @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock. + */ +#define __HAL_RCC_SAI1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC, (__SOURCE__))) + +/** @brief Macro to Get SAI1 clock source selection. + * @note This configuration is only available with STM32F446xx Devices. + * @retval The clock source can be one of the following values: + * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock. + * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock. + * @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock. + * @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock. + */ +#define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC)) + +/** @brief Macro to configure SAI2 clock source selection. + * @note This configuration is only available with STM32F446xx Devices. + * @note This function must be called before enabling PLL, PLLSAI, PLLI2S and + * the SAI clock. + * @param __SOURCE__ specifies the SAI2 clock source. + * This parameter can be one of the following values: + * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock. + * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock. + * @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock. + * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock. + */ +#define __HAL_RCC_SAI2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC, (__SOURCE__))) + +/** @brief Macro to Get SAI2 clock source selection. + * @note This configuration is only available with STM32F446xx Devices. + * @retval The clock source can be one of the following values: + * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock. + * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock. + * @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock. + * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock. + */ +#define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC)) + +/** @brief Macro to configure I2S APB1 clock source selection. + * @note This function must be called before enabling PLL, PLLI2S and the I2S clock. + * @param __SOURCE__ specifies the I2S APB1 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. + * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB1 clock. + * @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB1 clock. + * @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. + */ +#define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__))) + +/** @brief Macro to Get I2S APB1 clock source selection. + * @retval The clock source can be one of the following values: + * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. + * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB1 clock. + * @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB1 clock. + * @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. + */ +#define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC)) + +/** @brief Macro to configure I2S APB2 clock source selection. + * @note This function must be called before enabling PLL, PLLI2S and the I2S clock. + * @param __SOURCE__ specifies the SAI Block A clock source. + * This parameter can be one of the following values: + * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. + * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB2 clock. + * @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB2 clock. + * @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. + */ +#define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__))) + +/** @brief Macro to Get I2S APB2 clock source selection. + * @retval The clock source can be one of the following values: + * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. + * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB2 clock. + * @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB2 clock. + * @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. + */ +#define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC)) + +/** @brief Macro to configure the CEC clock. + * @param __SOURCE__ specifies the CEC clock source. + * This parameter can be one of the following values: + * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock + * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock + */ +#define __HAL_RCC_CEC_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__SOURCE__))) + +/** @brief Macro to Get the CEC clock. + * @retval The clock source can be one of the following values: + * @arg RCC_CECCLKSOURCE_HSI488: HSI selected as CEC clock + * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock + */ +#define __HAL_RCC_GET_CEC_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL)) + +/** @brief Macro to configure the FMPI2C1 clock. + * @param __SOURCE__ specifies the FMPI2C1 clock source. + * This parameter can be one of the following values: + * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock + * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock + * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock + */ +#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__))) + +/** @brief Macro to Get the FMPI2C1 clock. + * @retval The clock source can be one of the following values: + * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock + * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock + * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock + */ +#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL)) + +/** @brief Macro to configure the CLK48 clock. + * @param __SOURCE__ specifies the CLK48 clock source. + * This parameter can be one of the following values: + * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. + * @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. + */ +#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__))) + +/** @brief Macro to Get the CLK48 clock. + * @retval The clock source can be one of the following values: + * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. + * @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. + */ +#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL)) + +/** @brief Macro to configure the SDIO clock. + * @param __SOURCE__ specifies the SDIO clock source. + * This parameter can be one of the following values: + * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. + * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. + */ +#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__))) + +/** @brief Macro to Get the SDIO clock. + * @retval The clock source can be one of the following values: + * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. + * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. + */ +#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL)) + +/** @brief Macro to configure the SPDIFRX clock. + * @param __SOURCE__ specifies the SPDIFRX clock source. + * This parameter can be one of the following values: + * @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock. + * @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock. + */ +#define __HAL_RCC_SPDIFRX_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, (uint32_t)(__SOURCE__))) + +/** @brief Macro to Get the SPDIFRX clock. + * @retval The clock source can be one of the following values: + * @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock. + * @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock. + */ +#define __HAL_RCC_GET_SPDIFRX_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL)) +#endif /* STM32F446xx */ + +#if defined(STM32F469xx) || defined(STM32F479xx) + +/** @brief Macro to configure the CLK48 clock. + * @param __SOURCE__ specifies the CLK48 clock source. + * This parameter can be one of the following values: + * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. + * @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. + */ +#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, (uint32_t)(__SOURCE__))) + +/** @brief Macro to Get the CLK48 clock. + * @retval The clock source can be one of the following values: + * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. + * @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. + */ +#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL)) + +/** @brief Macro to configure the SDIO clock. + * @param __SOURCE__ specifies the SDIO clock source. + * This parameter can be one of the following values: + * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. + * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. + */ +#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, (uint32_t)(__SOURCE__))) + +/** @brief Macro to Get the SDIO clock. + * @retval The clock source can be one of the following values: + * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. + * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. + */ +#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL)) + +/** @brief Macro to configure the DSI clock. + * @param __SOURCE__ specifies the DSI clock source. + * This parameter can be one of the following values: + * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. + * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. + */ +#define __HAL_RCC_DSI_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, (uint32_t)(__SOURCE__))) + +/** @brief Macro to Get the DSI clock. + * @retval The clock source can be one of the following values: + * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. + * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. + */ +#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL)) + +#endif /* STM32F469xx || STM32F479xx */ + +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ + defined(STM32F413xx) || defined(STM32F423xx) + /** @brief Macro to configure the DFSDM1 clock. + * @param __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source. + * This parameter can be one of the following values: + * @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. + * @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernal clock. + * @retval None + */ +#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM1_CLKSOURCE__)) + +/** @brief Macro to get the DFSDM1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. + * @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernal clock. + */ +#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL))) + +/** @brief Macro to configure DFSDM1 Audio clock source selection. + * @note This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/ + STM32F413xx/STM32F423xx Devices. + * @param __SOURCE__ specifies the DFSDM1 Audio clock source. + * This parameter can be one of the following values: + * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock + * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock + */ +#define __HAL_RCC_DFSDM1AUDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL, (__SOURCE__))) + +/** @brief Macro to Get DFSDM1 Audio clock source selection. + * @note This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/ + STM32F413xx/STM32F423xx Devices. + * @retval The clock source can be one of the following values: + * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock + * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock + */ +#define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL)) + +#if defined(STM32F413xx) || defined(STM32F423xx) + /** @brief Macro to configure the DFSDM2 clock. + * @param __DFSDM2_CLKSOURCE__ specifies the DFSDM1 clock source. + * This parameter can be one of the following values: + * @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. + * @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernal clock. + * @retval None + */ +#define __HAL_RCC_DFSDM2_CONFIG(__DFSDM2_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM2_CLKSOURCE__)) + +/** @brief Macro to get the DFSDM2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. + * @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernal clock. + */ +#define __HAL_RCC_GET_DFSDM2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL))) + +/** @brief Macro to configure DFSDM1 Audio clock source selection. + * @note This configuration is only available with STM32F413xx/STM32F423xx Devices. + * @param __SOURCE__ specifies the DFSDM2 Audio clock source. + * This parameter can be one of the following values: + * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock + * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock + */ +#define __HAL_RCC_DFSDM2AUDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM2ASEL, (__SOURCE__))) + +/** @brief Macro to Get DFSDM2 Audio clock source selection. + * @note This configuration is only available with STM32F413xx/STM32F423xx Devices. + * @retval The clock source can be one of the following values: + * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock + * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock + */ +#define __HAL_RCC_GET_DFSDM2AUDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM2ASEL)) + +/** @brief Macro to configure SAI1BlockA clock source selection. + * @note The SAI peripheral is only available with STM32F413xx/STM32F423xx Devices. + * @note This function must be called before enabling PLLSAI, PLLI2S and + * the SAI clock. + * @param __SOURCE__ specifies the SAI Block A clock source. + * This parameter can be one of the following values: + * @arg RCC_SAIACLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock. + * @arg RCC_SAIACLKSOURCE_EXT: External clock mapped on the I2S_CKIN pinused as SAI1 Block A clock. + * @arg RCC_SAIACLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock. + * @arg RCC_SAIACLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. + */ +#define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__))) + +/** @brief Macro to Get SAI1 BlockA clock source selection. + * @note This configuration is only available with STM32F413xx/STM32F423xx Devices. + * @retval The clock source can be one of the following values: + * @arg RCC_SAIACLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock. + * @arg RCC_SAIACLKSOURCE_EXT: External clock mapped on the I2S_CKIN pinused as SAI1 Block A clock. + * @arg RCC_SAIACLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock. + * @arg RCC_SAIACLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. + */ +#define __HAL_RCC_GET_SAI_BLOCKA_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC)) + +/** @brief Macro to configure SAI1 BlockB clock source selection. + * @note The SAI peripheral is only available with STM32F413xx/STM32F423xx Devices. + * @note This function must be called before enabling PLLSAI, PLLI2S and + * the SAI clock. + * @param __SOURCE__ specifies the SAI Block B clock source. + * This parameter can be one of the following values: + * @arg RCC_SAIBCLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock. + * @arg RCC_SAIBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 Block A clock. + * @arg RCC_SAIBCLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock. + * @arg RCC_SAIBCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. + */ +#define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__))) + +/** @brief Macro to Get SAI1 BlockB clock source selection. + * @note This configuration is only available with STM32F413xx/STM32F423xx Devices. + * @retval The clock source can be one of the following values: + * @arg RCC_SAIBCLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock. + * @arg RCC_SAIBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 Block A clock. + * @arg RCC_SAIBCLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock. + * @arg RCC_SAIBCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. + */ +#define __HAL_RCC_GET_SAI_BLOCKB_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC)) + +/** @brief Macro to configure the LPTIM1 clock. + * @param __SOURCE__ specifies the LPTIM1 clock source. + * This parameter can be one of the following values: + * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock + */ +#define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__))) + +/** @brief Macro to Get the LPTIM1 clock. + * @retval The clock source can be one of the following values: + * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock + */ +#define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)) +#endif /* STM32F413xx || STM32F423xx */ + +/** @brief Macro to configure I2S APB1 clock source selection. + * @param __SOURCE__ specifies the I2S APB1 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR. + * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. + * @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR. + * @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. + */ +#define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__))) + +/** @brief Macro to Get I2S APB1 clock source selection. + * @retval The clock source can be one of the following values: + * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR. + * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. + * @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR. + * @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. + */ +#define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC)) + +/** @brief Macro to configure I2S APB2 clock source selection. + * @param __SOURCE__ specifies the I2S APB2 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR. + * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. + * @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR. + * @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. + */ +#define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__))) + +/** @brief Macro to Get I2S APB2 clock source selection. + * @retval The clock source can be one of the following values: + * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR. + * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. + * @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR. + * @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. + */ +#define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC)) + +/** @brief Macro to configure the PLL I2S clock source (PLLI2SCLK). + * @note This macro must be called before enabling the I2S APB clock. + * @param __SOURCE__ specifies the I2S clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLI2SCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. + * @arg RCC_PLLI2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin + * used as I2S clock source. + */ +#define __HAL_RCC_PLL_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_PLLI2SCFGR_PLLI2SSRC_BB = (__SOURCE__)) + +/** @brief Macro to configure the FMPI2C1 clock. + * @param __SOURCE__ specifies the FMPI2C1 clock source. + * This parameter can be one of the following values: + * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock + * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock + * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock + */ +#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__))) + +/** @brief Macro to Get the FMPI2C1 clock. + * @retval The clock source can be one of the following values: + * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock + * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock + * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock + */ +#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL)) + +/** @brief Macro to configure the CLK48 clock. + * @param __SOURCE__ specifies the CLK48 clock source. + * This parameter can be one of the following values: + * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. + * @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock. + */ +#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__))) + +/** @brief Macro to Get the CLK48 clock. + * @retval The clock source can be one of the following values: + * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. + * @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock + */ +#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL)) + +/** @brief Macro to configure the SDIO clock. + * @param __SOURCE__ specifies the SDIO clock source. + * This parameter can be one of the following values: + * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. + * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. + */ +#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__))) + +/** @brief Macro to Get the SDIO clock. + * @retval The clock source can be one of the following values: + * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. + * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. + */ +#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL)) + +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +/** @brief Macro to configure I2S clock source selection. + * @param __SOURCE__ specifies the I2S clock source. + * This parameter can be one of the following values: + * @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR. + * @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. + * @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC. + */ +#define __HAL_RCC_I2S_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC, (__SOURCE__))) + +/** @brief Macro to Get I2S clock source selection. + * @retval The clock source can be one of the following values: + * @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR. + * @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. + * @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC. + */ +#define __HAL_RCC_GET_I2S_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC)) + +/** @brief Macro to configure the FMPI2C1 clock. + * @param __SOURCE__ specifies the FMPI2C1 clock source. + * This parameter can be one of the following values: + * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock + * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock + * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock + */ +#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__))) + +/** @brief Macro to Get the FMPI2C1 clock. + * @retval The clock source can be one of the following values: + * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock + * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock + * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock + */ +#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL)) + +/** @brief Macro to configure the LPTIM1 clock. + * @param __SOURCE__ specifies the LPTIM1 clock source. + * This parameter can be one of the following values: + * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK1 selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock + */ +#define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__))) + +/** @brief Macro to Get the LPTIM1 clock. + * @retval The clock source can be one of the following values: + * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK1 selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock + */ +#define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)) +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ + defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ + defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ + defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/** @brief Macro to configure the Timers clocks prescalers + * @note This feature is only available with STM32F429x/439x Devices. + * @param __PRESC__ specifies the Timers clocks prescalers selection + * This parameter can be one of the following values: + * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is + * equal to HPRE if PPREx is corresponding to division by 1 or 2, + * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to + * division by 4 or more. + * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is + * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, + * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding + * to division by 8 or more. + */ +#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) (*(__IO uint32_t *) RCC_DCKCFGR_TIMPRE_BB = (__PRESC__)) + +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx) || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE ||\ + STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx ||\ + STM32F423xx */ + +/*----------------------------------------------------------------------------*/ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +/** @brief Enable PLLSAI_RDY interrupt. + */ +#define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE)) + +/** @brief Disable PLLSAI_RDY interrupt. + */ +#define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE)) + +/** @brief Clear the PLLSAI RDY interrupt pending bits. + */ +#define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF)) + +/** @brief Check the PLLSAI RDY interrupt has occurred or not. + * @retval The new state (TRUE or FALSE). + */ +#define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE)) + +/** @brief Check PLLSAI RDY flag is set or not. + * @retval The new state (TRUE or FALSE). + */ +#define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY)) + +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +/** @brief Macros to enable or disable the RCC MCO1 feature. + */ +#define __HAL_RCC_MCO1_ENABLE() (*(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = ENABLE) +#define __HAL_RCC_MCO1_DISABLE() (*(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = DISABLE) + +/** @brief Macros to enable or disable the RCC MCO2 feature. + */ +#define __HAL_RCC_MCO2_ENABLE() (*(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = ENABLE) +#define __HAL_RCC_MCO2_DISABLE() (*(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = DISABLE) + +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCCEx_Exported_Functions + * @{ + */ + +/** @addtogroup RCCEx_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); + +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\ + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\ + defined(STM32F423xx) +void HAL_RCCEx_SelectLSEMode(uint8_t Mode); +#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ +#if defined(RCC_PLLI2S_SUPPORT) +HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit); +HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void); +#endif /* RCC_PLLI2S_SUPPORT */ +#if defined(RCC_PLLSAI_SUPPORT) +HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit); +HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void); +#endif /* RCC_PLLSAI_SUPPORT */ +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RCCEx_Private_Constants RCCEx Private Constants + * @{ + */ + +/** @defgroup RCCEx_BitAddress_AliasRegion RCC BitAddress AliasRegion + * @brief RCC registers bit address in the alias region + * @{ + */ +/* --- CR Register ---*/ +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +/* Alias word address of PLLSAION bit */ +#define RCC_PLLSAION_BIT_NUMBER 0x1CU +#define RCC_CR_PLLSAION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLSAION_BIT_NUMBER * 4U)) + +#define PLLSAI_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ + defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ + defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/* Alias word address of PLLI2SON bit */ +#define RCC_PLLI2SON_BIT_NUMBER 0x1AU +#define RCC_CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLI2SON_BIT_NUMBER * 4U)) +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || + STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || + STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ + +/* --- DCKCFGR Register ---*/ +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F401xC) ||\ + defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ + defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ + defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/* Alias word address of TIMPRE bit */ +#define RCC_DCKCFGR_OFFSET (RCC_OFFSET + 0x8CU) +#define RCC_TIMPRE_BIT_NUMBER 0x18U +#define RCC_DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32U) + (RCC_TIMPRE_BIT_NUMBER * 4U)) +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F410xx || STM32F401xC ||\ + STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ + STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ + +/* --- CFGR Register ---*/ +#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08U) +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ + defined(STM32F469xx) || defined(STM32F479xx) +/* Alias word address of I2SSRC bit */ +#define RCC_I2SSRC_BIT_NUMBER 0x17U +#define RCC_CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_I2SSRC_BIT_NUMBER * 4U)) + +#define PLLI2S_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || + STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ + defined(STM32F413xx) || defined(STM32F423xx) +/* --- PLLI2SCFGR Register ---*/ +#define RCC_PLLI2SCFGR_OFFSET (RCC_OFFSET + 0x84U) +/* Alias word address of PLLI2SSRC bit */ +#define RCC_PLLI2SSRC_BIT_NUMBER 0x16U +#define RCC_PLLI2SCFGR_PLLI2SSRC_BB (PERIPH_BB_BASE + (RCC_PLLI2SCFGR_OFFSET * 32U) + (RCC_PLLI2SSRC_BIT_NUMBER * 4U)) + +#define PLLI2S_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */ +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx | STM32F423xx */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +/* Alias word address of MCO1EN bit */ +#define RCC_MCO1EN_BIT_NUMBER 0x8U +#define RCC_CFGR_MCO1EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_MCO1EN_BIT_NUMBER * 4U)) + +/* Alias word address of MCO2EN bit */ +#define RCC_MCO2EN_BIT_NUMBER 0x9U +#define RCC_CFGR_MCO2EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_MCO2EN_BIT_NUMBER * 4U)) +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + +#define PLL_TIMEOUT_VALUE 2U /* 2 ms */ +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup RCCEx_Private_Macros RCCEx Private Macros + * @{ + */ +/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters + * @{ + */ +#if defined(STM32F411xE) +#define IS_RCC_PLLN_VALUE(VALUE) ((192U <= (VALUE)) && ((VALUE) <= 432U)) +#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192U <= (VALUE)) && ((VALUE) <= 432U)) +#else /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || + STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F410Tx || STM32F410Cx || + STM32F410Rx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Cx || STM32F412Rx || + STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ +#define IS_RCC_PLLN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U)) +#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U)) +#endif /* STM32F411xE */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) +#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000007FU)) +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) +#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00000007U)) +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ + +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) +#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000000FU)) +#endif /* STM32F401xC || STM32F401xE || STM32F411xE */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000001FU)) +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + +#if defined(STM32F446xx) +#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00000FFFU)) +#endif /* STM32F446xx */ + +#if defined(STM32F469xx) || defined(STM32F479xx) +#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x000001FFU)) +#endif /* STM32F469xx || STM32F479xx */ + +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) +#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x000003FFU)) +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ + +#if defined(STM32F413xx) || defined(STM32F423xx) +#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00007FFFU)) +#endif /* STM32F413xx || STM32F423xx */ + +#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\ + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U)) + +#define IS_RCC_PLLSAIN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U)) + +#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U)) + +#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) + +#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U)) + +#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U)) + +#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\ + ((VALUE) == RCC_PLLSAIDIVR_4) ||\ + ((VALUE) == RCC_PLLSAIDIVR_8) ||\ + ((VALUE) == RCC_PLLSAIDIVR_16)) +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ + defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +#define IS_RCC_PLLI2SM_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 63U)) + +#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\ + ((MODE) == RCC_LSE_HIGHDRIVE_MODE)) +#endif /* STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) + +#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\ + ((MODE) == RCC_LSE_HIGHDRIVE_MODE)) + +#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) ||\ + ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\ + ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI)) + +#define IS_RCC_LPTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) ||\ + ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) ||\ + ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) ||\ + ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE)) + +#define IS_RCC_I2SAPBCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLR) ||\ + ((SOURCE) == RCC_I2SAPBCLKSOURCE_EXT) ||\ + ((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLSRC)) +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + +#if defined(STM32F446xx) +#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) + +#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) ||\ + ((VALUE) == RCC_PLLI2SP_DIV4) ||\ + ((VALUE) == RCC_PLLI2SP_DIV6) ||\ + ((VALUE) == RCC_PLLI2SP_DIV8)) + +#define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63U) + +#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\ + ((VALUE) == RCC_PLLSAIP_DIV4) ||\ + ((VALUE) == RCC_PLLSAIP_DIV6) ||\ + ((VALUE) == RCC_PLLSAIP_DIV8)) + +#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) ||\ + ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) ||\ + ((SOURCE) == RCC_SAI1CLKSOURCE_PLLR) ||\ + ((SOURCE) == RCC_SAI1CLKSOURCE_EXT)) + +#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) ||\ + ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) ||\ + ((SOURCE) == RCC_SAI2CLKSOURCE_PLLR) ||\ + ((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC)) + +#define IS_RCC_I2SAPB1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) ||\ + ((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT) ||\ + ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR) ||\ + ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC)) + + #define IS_RCC_I2SAPB2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) ||\ + ((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT) ||\ + ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR) ||\ + ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC)) + +#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) ||\ + ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\ + ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI)) + +#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) ||\ + ((SOURCE) == RCC_CECCLKSOURCE_LSE)) + +#define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\ + ((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP)) + +#define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\ + ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK)) + +#define IS_RCC_SPDIFRXCLKSOURCE(SOURCE) (((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLR) ||\ + ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLI2SP)) +#endif /* STM32F446xx */ + +#if defined(STM32F469xx) || defined(STM32F479xx) +#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) + +#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\ + ((VALUE) == RCC_PLLSAIP_DIV4) ||\ + ((VALUE) == RCC_PLLSAIP_DIV6) ||\ + ((VALUE) == RCC_PLLSAIP_DIV8)) + +#define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\ + ((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP)) + +#define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\ + ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK)) + +#define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) ||\ + ((SOURCE) == RCC_DSICLKSOURCE_DSIPHY)) + +#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\ + ((MODE) == RCC_LSE_HIGHDRIVE_MODE)) +#endif /* STM32F469xx || STM32F479xx */ + +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ + defined(STM32F413xx) || defined(STM32F423xx) +#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U)) + +#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) + +#define IS_RCC_PLLI2SCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLI2SCLKSOURCE_PLLSRC) || \ + ((__SOURCE__) == RCC_PLLI2SCLKSOURCE_EXT)) + +#define IS_RCC_I2SAPB1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) ||\ + ((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT) ||\ + ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR) ||\ + ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC)) + + #define IS_RCC_I2SAPB2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) ||\ + ((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT) ||\ + ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR) ||\ + ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC)) + +#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) ||\ + ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\ + ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI)) + +#define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\ + ((SOURCE) == RCC_CLK48CLKSOURCE_PLLI2SQ)) + +#define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\ + ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK)) + +#define IS_RCC_DFSDM1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_PCLK2) || \ + ((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK)) + +#define IS_RCC_DFSDM1AUDIOCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2S1) || \ + ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2S2)) + +#if defined(STM32F413xx) || defined(STM32F423xx) +#define IS_RCC_DFSDM2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM2CLKSOURCE_PCLK2) || \ + ((__SOURCE__) == RCC_DFSDM2CLKSOURCE_SYSCLK)) + +#define IS_RCC_DFSDM2AUDIOCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM2AUDIOCLKSOURCE_I2S1) || \ + ((__SOURCE__) == RCC_DFSDM2AUDIOCLKSOURCE_I2S2)) + +#define IS_RCC_LPTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) ||\ + ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) ||\ + ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) ||\ + ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE)) + +#define IS_RCC_SAIACLKSOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSOURCE_PLLI2SR) ||\ + ((SOURCE) == RCC_SAIACLKSOURCE_EXT) ||\ + ((SOURCE) == RCC_SAIACLKSOURCE_PLLR) ||\ + ((SOURCE) == RCC_SAIACLKSOURCE_PLLSRC)) + +#define IS_RCC_SAIBCLKSOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSOURCE_PLLI2SR) ||\ + ((SOURCE) == RCC_SAIBCLKSOURCE_EXT) ||\ + ((SOURCE) == RCC_SAIBCLKSOURCE_PLLR) ||\ + ((SOURCE) == RCC_SAIBCLKSOURCE_PLLSRC)) + +#define IS_RCC_PLL_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U)) + +#define IS_RCC_PLLI2S_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U)) + +#endif /* STM32F413xx || STM32F423xx */ +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ + defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ + defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) + +#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \ + ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK)) + +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || + STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || \ + STM32F412Rx */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_I2SCLK)|| \ + ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK)) +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_RCC_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h new file mode 100644 index 0000000..41903da --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h @@ -0,0 +1,726 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_spi.h + * @author MCD Application Team + * @brief Header file of SPI HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F4xx_HAL_SPI_H +#define STM32F4xx_HAL_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SPI_Exported_Types SPI Exported Types + * @{ + */ + +/** + * @brief SPI Configuration Structure definition + */ +typedef struct +{ + uint32_t Mode; /*!< Specifies the SPI operating mode. + This parameter can be a value of @ref SPI_Mode */ + + uint32_t Direction; /*!< Specifies the SPI bidirectional mode state. + This parameter can be a value of @ref SPI_Direction */ + + uint32_t DataSize; /*!< Specifies the SPI data size. + This parameter can be a value of @ref SPI_Data_Size */ + + uint32_t CLKPolarity; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_Clock_Polarity */ + + uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_Clock_Phase */ + + uint32_t NSS; /*!< Specifies whether the NSS signal is managed by + hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref SPI_Slave_Select_management */ + + uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_BaudRate_Prescaler + @note The communication clock is derived from the master + clock. The slave clock does not need to be set. */ + + uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_MSB_LSB_transmission */ + + uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not. + This parameter can be a value of @ref SPI_TI_mode */ + + uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. + This parameter can be a value of @ref SPI_CRC_Calculation */ + + uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. + This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */ +} SPI_InitTypeDef; + +/** + * @brief HAL SPI State structure definition + */ +typedef enum +{ + HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */ + HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ + HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */ + HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */ + HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */ + HAL_SPI_STATE_ERROR = 0x06U, /*!< SPI error state */ + HAL_SPI_STATE_ABORT = 0x07U /*!< SPI abort is ongoing */ +} HAL_SPI_StateTypeDef; + +/** + * @brief SPI handle Structure definition + */ +typedef struct __SPI_HandleTypeDef +{ + SPI_TypeDef *Instance; /*!< SPI registers base address */ + + SPI_InitTypeDef Init; /*!< SPI communication parameters */ + + uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ + + uint16_t TxXferSize; /*!< SPI Tx Transfer size */ + + __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */ + + uint16_t RxXferSize; /*!< SPI Rx Transfer size */ + + __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */ + + void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */ + + void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */ + + DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */ + + HAL_LockTypeDef Lock; /*!< Locking object */ + + __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */ + + __IO uint32_t ErrorCode; /*!< SPI Error code */ + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Completed callback */ + void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Completed callback */ + void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Completed callback */ + void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Half Completed callback */ + void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Half Completed callback */ + void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback */ + void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Error callback */ + void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Abort callback */ + void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp Init callback */ + void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp DeInit callback */ + +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} SPI_HandleTypeDef; + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +/** + * @brief HAL SPI Callback ID enumeration definition + */ +typedef enum +{ + HAL_SPI_TX_COMPLETE_CB_ID = 0x00U, /*!< SPI Tx Completed callback ID */ + HAL_SPI_RX_COMPLETE_CB_ID = 0x01U, /*!< SPI Rx Completed callback ID */ + HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02U, /*!< SPI TxRx Completed callback ID */ + HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< SPI Tx Half Completed callback ID */ + HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< SPI Rx Half Completed callback ID */ + HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05U, /*!< SPI TxRx Half Completed callback ID */ + HAL_SPI_ERROR_CB_ID = 0x06U, /*!< SPI Error callback ID */ + HAL_SPI_ABORT_CB_ID = 0x07U, /*!< SPI Abort callback ID */ + HAL_SPI_MSPINIT_CB_ID = 0x08U, /*!< SPI Msp Init callback ID */ + HAL_SPI_MSPDEINIT_CB_ID = 0x09U /*!< SPI Msp DeInit callback ID */ + +} HAL_SPI_CallbackIDTypeDef; + +/** + * @brief HAL SPI Callback pointer definition + */ +typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */ + +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SPI_Exported_Constants SPI Exported Constants + * @{ + */ + +/** @defgroup SPI_Error_Code SPI Error Code + * @{ + */ +#define HAL_SPI_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_SPI_ERROR_MODF (0x00000001U) /*!< MODF error */ +#define HAL_SPI_ERROR_CRC (0x00000002U) /*!< CRC error */ +#define HAL_SPI_ERROR_OVR (0x00000004U) /*!< OVR error */ +#define HAL_SPI_ERROR_FRE (0x00000008U) /*!< FRE error */ +#define HAL_SPI_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_SPI_ERROR_FLAG (0x00000020U) /*!< Error on RXNE/TXE/BSY Flag */ +#define HAL_SPI_ERROR_ABORT (0x00000040U) /*!< Error during SPI Abort procedure */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +#define HAL_SPI_ERROR_INVALID_CALLBACK (0x00000080U) /*!< Invalid Callback error */ +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup SPI_Mode SPI Mode + * @{ + */ +#define SPI_MODE_SLAVE (0x00000000U) +#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) +/** + * @} + */ + +/** @defgroup SPI_Direction SPI Direction Mode + * @{ + */ +#define SPI_DIRECTION_2LINES (0x00000000U) +#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY +#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE +/** + * @} + */ + +/** @defgroup SPI_Data_Size SPI Data Size + * @{ + */ +#define SPI_DATASIZE_8BIT (0x00000000U) +#define SPI_DATASIZE_16BIT SPI_CR1_DFF +/** + * @} + */ + +/** @defgroup SPI_Clock_Polarity SPI Clock Polarity + * @{ + */ +#define SPI_POLARITY_LOW (0x00000000U) +#define SPI_POLARITY_HIGH SPI_CR1_CPOL +/** + * @} + */ + +/** @defgroup SPI_Clock_Phase SPI Clock Phase + * @{ + */ +#define SPI_PHASE_1EDGE (0x00000000U) +#define SPI_PHASE_2EDGE SPI_CR1_CPHA +/** + * @} + */ + +/** @defgroup SPI_Slave_Select_management SPI Slave Select Management + * @{ + */ +#define SPI_NSS_SOFT SPI_CR1_SSM +#define SPI_NSS_HARD_INPUT (0x00000000U) +#define SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U) +/** + * @} + */ + +/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler + * @{ + */ +#define SPI_BAUDRATEPRESCALER_2 (0x00000000U) +#define SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0) +#define SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1) +#define SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) +#define SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2) +#define SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) +#define SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) +#define SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) +/** + * @} + */ + +/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission + * @{ + */ +#define SPI_FIRSTBIT_MSB (0x00000000U) +#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST +/** + * @} + */ + +/** @defgroup SPI_TI_mode SPI TI Mode + * @{ + */ +#define SPI_TIMODE_DISABLE (0x00000000U) +#define SPI_TIMODE_ENABLE SPI_CR2_FRF +/** + * @} + */ + +/** @defgroup SPI_CRC_Calculation SPI CRC Calculation + * @{ + */ +#define SPI_CRCCALCULATION_DISABLE (0x00000000U) +#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN +/** + * @} + */ + +/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition + * @{ + */ +#define SPI_IT_TXE SPI_CR2_TXEIE +#define SPI_IT_RXNE SPI_CR2_RXNEIE +#define SPI_IT_ERR SPI_CR2_ERRIE +/** + * @} + */ + +/** @defgroup SPI_Flags_definition SPI Flags Definition + * @{ + */ +#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */ +#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */ +#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */ +#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */ +#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */ +#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */ +#define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */ +#define SPI_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR\ + | SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup SPI_Exported_Macros SPI Exported Macros + * @{ + */ + +/** @brief Reset SPI handle state. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_SPI_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + +/** @brief Enable the specified SPI interrupts. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @param __INTERRUPT__ specifies the interrupt source to enable. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Tx buffer empty interrupt enable + * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable + * @arg SPI_IT_ERR: Error interrupt enable + * @retval None + */ +#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) + +/** @brief Disable the specified SPI interrupts. + * @param __HANDLE__ specifies the SPI handle. + * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral. + * @param __INTERRUPT__ specifies the interrupt source to disable. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Tx buffer empty interrupt enable + * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable + * @arg SPI_IT_ERR: Error interrupt enable + * @retval None + */ +#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) + +/** @brief Check whether the specified SPI interrupt source is enabled or not. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @param __INTERRUPT__ specifies the SPI interrupt source to check. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Tx buffer empty interrupt enable + * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable + * @arg SPI_IT_ERR: Error interrupt enable + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\ + & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Check whether the specified SPI flag is set or not. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg SPI_FLAG_RXNE: Receive buffer not empty flag + * @arg SPI_FLAG_TXE: Transmit buffer empty flag + * @arg SPI_FLAG_CRCERR: CRC error flag + * @arg SPI_FLAG_MODF: Mode fault flag + * @arg SPI_FLAG_OVR: Overrun flag + * @arg SPI_FLAG_BSY: Busy flag + * @arg SPI_FLAG_FRE: Frame format error flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the SPI CRCERR pending flag. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR)) + +/** @brief Clear the SPI MODF pending flag. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg_modf = 0x00U; \ + tmpreg_modf = (__HANDLE__)->Instance->SR; \ + CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \ + UNUSED(tmpreg_modf); \ + } while(0U) + +/** @brief Clear the SPI OVR pending flag. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg_ovr = 0x00U; \ + tmpreg_ovr = (__HANDLE__)->Instance->DR; \ + tmpreg_ovr = (__HANDLE__)->Instance->SR; \ + UNUSED(tmpreg_ovr); \ + } while(0U) + +/** @brief Clear the SPI FRE pending flag. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg_fre = 0x00U; \ + tmpreg_fre = (__HANDLE__)->Instance->SR; \ + UNUSED(tmpreg_fre); \ + }while(0U) + +/** @brief Enable the SPI peripheral. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) + +/** @brief Disable the SPI peripheral. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SPI_Private_Macros SPI Private Macros + * @{ + */ + +/** @brief Set the SPI transmit-only mode. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) + +/** @brief Set the SPI receive-only mode. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) + +/** @brief Reset the CRC calculation of the SPI. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\ + SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U) + +/** @brief Check whether the specified SPI flag is set or not. + * @param __SR__ copy of SPI SR regsiter. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg SPI_FLAG_RXNE: Receive buffer not empty flag + * @arg SPI_FLAG_TXE: Transmit buffer empty flag + * @arg SPI_FLAG_CRCERR: CRC error flag + * @arg SPI_FLAG_MODF: Mode fault flag + * @arg SPI_FLAG_OVR: Overrun flag + * @arg SPI_FLAG_BSY: Busy flag + * @arg SPI_FLAG_FRE: Frame format error flag + * @retval SET or RESET. + */ +#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) + +/** @brief Check whether the specified SPI Interrupt is set or not. + * @param __CR2__ copy of SPI CR2 regsiter. + * @param __INTERRUPT__ specifies the SPI interrupt source to check. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Tx buffer empty interrupt enable + * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable + * @arg SPI_IT_ERR: Error interrupt enable + * @retval SET or RESET. + */ +#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Checks if SPI Mode parameter is in allowed range. + * @param __MODE__ specifies the SPI Mode. + * This parameter can be a value of @ref SPI_Mode + * @retval None + */ +#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \ + ((__MODE__) == SPI_MODE_MASTER)) + +/** @brief Checks if SPI Direction Mode parameter is in allowed range. + * @param __MODE__ specifies the SPI Direction Mode. + * This parameter can be a value of @ref SPI_Direction + * @retval None + */ +#define IS_SPI_DIRECTION(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ + ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \ + ((__MODE__) == SPI_DIRECTION_1LINE)) + +/** @brief Checks if SPI Direction Mode parameter is 2 lines. + * @param __MODE__ specifies the SPI Direction Mode. + * @retval None + */ +#define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES) + +/** @brief Checks if SPI Direction Mode parameter is 1 or 2 lines. + * @param __MODE__ specifies the SPI Direction Mode. + * @retval None + */ +#define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ + ((__MODE__) == SPI_DIRECTION_1LINE)) + +/** @brief Checks if SPI Data Size parameter is in allowed range. + * @param __DATASIZE__ specifies the SPI Data Size. + * This parameter can be a value of @ref SPI_Data_Size + * @retval None + */ +#define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_8BIT)) + +/** @brief Checks if SPI Serial clock steady state parameter is in allowed range. + * @param __CPOL__ specifies the SPI serial clock steady state. + * This parameter can be a value of @ref SPI_Clock_Polarity + * @retval None + */ +#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \ + ((__CPOL__) == SPI_POLARITY_HIGH)) + +/** @brief Checks if SPI Clock Phase parameter is in allowed range. + * @param __CPHA__ specifies the SPI Clock Phase. + * This parameter can be a value of @ref SPI_Clock_Phase + * @retval None + */ +#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \ + ((__CPHA__) == SPI_PHASE_2EDGE)) + +/** @brief Checks if SPI Slave Select parameter is in allowed range. + * @param __NSS__ specifies the SPI Slave Select management parameter. + * This parameter can be a value of @ref SPI_Slave_Select_management + * @retval None + */ +#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \ + ((__NSS__) == SPI_NSS_HARD_INPUT) || \ + ((__NSS__) == SPI_NSS_HARD_OUTPUT)) + +/** @brief Checks if SPI Baudrate prescaler parameter is in allowed range. + * @param __PRESCALER__ specifies the SPI Baudrate prescaler. + * This parameter can be a value of @ref SPI_BaudRate_Prescaler + * @retval None + */ +#define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256)) + +/** @brief Checks if SPI MSB LSB transmission parameter is in allowed range. + * @param __BIT__ specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit). + * This parameter can be a value of @ref SPI_MSB_LSB_transmission + * @retval None + */ +#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \ + ((__BIT__) == SPI_FIRSTBIT_LSB)) + +/** @brief Checks if SPI TI mode parameter is in allowed range. + * @param __MODE__ specifies the SPI TI mode. + * This parameter can be a value of @ref SPI_TI_mode + * @retval None + */ +#define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \ + ((__MODE__) == SPI_TIMODE_ENABLE)) + +/** @brief Checks if SPI CRC calculation enabled state is in allowed range. + * @param __CALCULATION__ specifies the SPI CRC calculation enable state. + * This parameter can be a value of @ref SPI_CRC_Calculation + * @retval None + */ +#define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \ + ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE)) + +/** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range. + * @param __POLYNOMIAL__ specifies the SPI polynomial value to be used for the CRC calculation. + * This parameter must be a number between Min_Data = 0 and Max_Data = 65535 + * @retval None + */ +#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && ((__POLYNOMIAL__) <= 0xFFFFU) && (((__POLYNOMIAL__)&0x1U) != 0U)) + +/** @brief Checks if DMA handle is valid. + * @param __HANDLE__ specifies a DMA Handle. + * @retval None + */ +#define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SPI_Exported_Functions + * @{ + */ + +/** @addtogroup SPI_Exported_Functions_Group1 + * @{ + */ +/* Initialization/de-initialization functions ********************************/ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi); +void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); +void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup SPI_Exported_Functions_Group2 + * @{ + */ +/* I/O operation functions ***************************************************/ +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); +HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi); +/* Transfer Abort functions */ +HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi); + +void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi); +/** + * @} + */ + +/** @addtogroup SPI_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); +uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F4xx_HAL_SPI_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h new file mode 100644 index 0000000..d6f1a1a --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h @@ -0,0 +1,2030 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_tim.h + * @author MCD Application Team + * @brief Header file of TIM HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F4xx_HAL_TIM_H +#define STM32F4xx_HAL_TIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup TIM + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup TIM_Exported_Types TIM Exported Types + * @{ + */ + +/** + * @brief TIM Time base Configuration Structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint32_t Period; /*!< Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_ClockDivision */ + + uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. + Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. + This parameter can be a value of @ref TIM_AutoReloadPreload */ +} TIM_Base_InitTypeDef; + +/** + * @brief TIM Output Compare Configuration Structure definition + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCFastMode; /*!< Specifies the Fast mode state. + This parameter can be a value of @ref TIM_Output_Fast_State + @note This parameter is valid only in PWM1 and PWM2 mode. */ + + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ +} TIM_OC_InitTypeDef; + +/** + * @brief TIM One Pulse Mode Configuration Structure definition + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_OnePulse_InitTypeDef; + +/** + * @brief TIM Input Capture Configuration Structure definition + */ +typedef struct +{ + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_IC_InitTypeDef; + +/** + * @brief TIM Encoder Configuration Structure definition + */ +typedef struct +{ + uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Mode */ + + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ + + uint32_t IC1Selection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC1Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ + + uint32_t IC2Selection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC2Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_Encoder_InitTypeDef; + +/** + * @brief Clock Configuration Handle Structure definition + */ +typedef struct +{ + uint32_t ClockSource; /*!< TIM clock sources + This parameter can be a value of @ref TIM_Clock_Source */ + uint32_t ClockPolarity; /*!< TIM clock polarity + This parameter can be a value of @ref TIM_Clock_Polarity */ + uint32_t ClockPrescaler; /*!< TIM clock prescaler + This parameter can be a value of @ref TIM_Clock_Prescaler */ + uint32_t ClockFilter; /*!< TIM clock filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_ClockConfigTypeDef; + +/** + * @brief TIM Clear Input Configuration Handle Structure definition + */ +typedef struct +{ + uint32_t ClearInputState; /*!< TIM clear Input state + This parameter can be ENABLE or DISABLE */ + uint32_t ClearInputSource; /*!< TIM clear Input sources + This parameter can be a value of @ref TIM_ClearInput_Source */ + uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity + This parameter can be a value of @ref TIM_ClearInput_Polarity */ + uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler + This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */ + uint32_t ClearInputFilter; /*!< TIM Clear Input filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_ClearInputConfigTypeDef; + +/** + * @brief TIM Master configuration Structure definition + */ +typedef struct +{ + uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection + This parameter can be a value of @ref TIM_Master_Mode_Selection */ + uint32_t MasterSlaveMode; /*!< Master/slave mode selection + This parameter can be a value of @ref TIM_Master_Slave_Mode + @note When the Master/slave mode is enabled, the effect of + an event on the trigger input (TRGI) is delayed to allow a + perfect synchronization between the current timer and its + slaves (through TRGO). It is not mandatory in case of timer + synchronization mode. */ +} TIM_MasterConfigTypeDef; + +/** + * @brief TIM Slave configuration Structure definition + */ +typedef struct +{ + uint32_t SlaveMode; /*!< Slave mode selection + This parameter can be a value of @ref TIM_Slave_Mode */ + uint32_t InputTrigger; /*!< Input Trigger source + This parameter can be a value of @ref TIM_Trigger_Selection */ + uint32_t TriggerPolarity; /*!< Input Trigger polarity + This parameter can be a value of @ref TIM_Trigger_Polarity */ + uint32_t TriggerPrescaler; /*!< Input trigger prescaler + This parameter can be a value of @ref TIM_Trigger_Prescaler */ + uint32_t TriggerFilter; /*!< Input trigger filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + +} TIM_SlaveConfigTypeDef; + +/** + * @brief TIM Break input(s) and Dead time configuration Structure definition + * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable + * filter and polarity. + */ +typedef struct +{ + uint32_t OffStateRunMode; /*!< TIM off state in run mode + This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ + uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode + This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ + uint32_t LockLevel; /*!< TIM Lock level + This parameter can be a value of @ref TIM_Lock_level */ + uint32_t DeadTime; /*!< TIM dead Time + This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + uint32_t BreakState; /*!< TIM Break State + This parameter can be a value of @ref TIM_Break_Input_enable_disable */ + uint32_t BreakPolarity; /*!< TIM Break input polarity + This parameter can be a value of @ref TIM_Break_Polarity */ + uint32_t BreakFilter; /*!< Specifies the break input filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state + This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ +} TIM_BreakDeadTimeConfigTypeDef; + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ + HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ + HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ +} HAL_TIM_StateTypeDef; + +/** + * @brief HAL Active channel structures definition + */ +typedef enum +{ + HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ + HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ + HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ + HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ + HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ +} HAL_TIM_ActiveChannel; + +/** + * @brief TIM Time Base Handle Structure definition + */ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +typedef struct __TIM_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +{ + TIM_TypeDef *Instance; /*!< Register base address */ + TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ + HAL_TIM_ActiveChannel Channel; /*!< Active channel */ + DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array + This array is accessed by a @ref DMA_Handle_index */ + HAL_LockTypeDef Lock; /*!< Locking object */ + __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ + void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ + void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ + void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ + void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ + void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ + void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ + void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ + void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ + void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ + void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ + void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ + void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ + void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ + void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ + void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */ + void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ + void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */ + void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ + void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */ + void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ + void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ + void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */ + void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ + void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ + void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */ + void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} TIM_HandleTypeDef; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief HAL TIM Callback ID enumeration definition + */ +typedef enum +{ + HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ + ,HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ + ,HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ + ,HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ + ,HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ + ,HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ + ,HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ + ,HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ + ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ + ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ + ,HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ + ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ + ,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ + ,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ + ,HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ + ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ + ,HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ + ,HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ + + ,HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ + ,HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ + ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ + ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ + ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ + ,HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ + ,HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ + ,HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ + ,HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ +} HAL_TIM_CallbackIDTypeDef; + +/** + * @brief HAL TIM Callback pointer definition + */ +typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ + +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ +/* End of exported types -----------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIM_Exported_Constants TIM Exported Constants + * @{ + */ + +/** @defgroup TIM_ClearInput_Source TIM Clear Input Source + * @{ + */ +#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */ +#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ +/** + * @} + */ + +/** @defgroup TIM_DMA_Base_address TIM DMA Base Address + * @{ + */ +#define TIM_DMABASE_CR1 0x00000000U +#define TIM_DMABASE_CR2 0x00000001U +#define TIM_DMABASE_SMCR 0x00000002U +#define TIM_DMABASE_DIER 0x00000003U +#define TIM_DMABASE_SR 0x00000004U +#define TIM_DMABASE_EGR 0x00000005U +#define TIM_DMABASE_CCMR1 0x00000006U +#define TIM_DMABASE_CCMR2 0x00000007U +#define TIM_DMABASE_CCER 0x00000008U +#define TIM_DMABASE_CNT 0x00000009U +#define TIM_DMABASE_PSC 0x0000000AU +#define TIM_DMABASE_ARR 0x0000000BU +#define TIM_DMABASE_RCR 0x0000000CU +#define TIM_DMABASE_CCR1 0x0000000DU +#define TIM_DMABASE_CCR2 0x0000000EU +#define TIM_DMABASE_CCR3 0x0000000FU +#define TIM_DMABASE_CCR4 0x00000010U +#define TIM_DMABASE_BDTR 0x00000011U +#define TIM_DMABASE_DCR 0x00000012U +#define TIM_DMABASE_DMAR 0x00000013U +/** + * @} + */ + +/** @defgroup TIM_Event_Source TIM Event Source + * @{ + */ +#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ +#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ +#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ +#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ +#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ +#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ +#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ +#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ +/** + * @} + */ + +/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity + * @{ + */ +#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ +/** + * @} + */ + +/** @defgroup TIM_ETR_Polarity TIM ETR Polarity + * @{ + */ +#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ +#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ +/** + * @} + */ + +/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler + * @{ + */ +#define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ +#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ +#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ +#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ +/** + * @} + */ + +/** @defgroup TIM_Counter_Mode TIM Counter Mode + * @{ + */ +#define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ +#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ +#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ +#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ +#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ +/** + * @} + */ + +/** @defgroup TIM_ClockDivision TIM Clock Division + * @{ + */ +#define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ +#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ +#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_State TIM Output Compare State + * @{ + */ +#define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ +#define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ +/** + * @} + */ + +/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload + * @{ + */ +#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ +#define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ + +/** + * @} + */ + +/** @defgroup TIM_Output_Fast_State TIM Output Fast State + * @{ + */ +#define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ +#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State + * @{ + */ +#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ +#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity + * @{ + */ +#define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ +#define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity + * @{ + */ +#define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */ +#define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State + * @{ + */ +#define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */ +#define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State + * @{ + */ +#define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */ +#define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity + * @{ + */ +#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ +#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ +#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ +/** + * @} + */ + +/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity + * @{ + */ +#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */ +#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection + * @{ + */ +#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC2, IC1, IC4 or IC3, respectively */ +#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler + * @{ + */ +#define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ +#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ +#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ +#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ +/** + * @} + */ + +/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode + * @{ + */ +#define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ +#define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ +/** + * @} + */ + +/** @defgroup TIM_Encoder_Mode TIM Encoder Mode + * @{ + */ +#define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ +#define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ +#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ +/** + * @} + */ + +/** @defgroup TIM_Interrupt_definition TIM interrupt Definition + * @{ + */ +#define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ +#define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ +#define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ +#define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ +#define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ +#define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */ +#define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ +#define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */ +/** + * @} + */ + +/** @defgroup TIM_Commutation_Source TIM Commutation Source + * @{ + */ +#define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */ +#define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */ +/** + * @} + */ + +/** @defgroup TIM_DMA_sources TIM DMA Sources + * @{ + */ +#define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ +#define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ +#define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ +#define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ +#define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ +#define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */ +#define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ +/** + * @} + */ + +/** @defgroup TIM_Flag_definition TIM Flag Definition + * @{ + */ +#define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ +#define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ +#define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ +#define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ +#define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ +#define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ +#define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ +#define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ +#define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ +#define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ +#define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ +#define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ +/** + * @} + */ + +/** @defgroup TIM_Channel TIM Channel + * @{ + */ +#define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ +#define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ +#define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ +#define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ +#define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Source TIM Clock Source + * @{ + */ +#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ +#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ +#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ +#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ +#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ +#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ +#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ +#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ +#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ +#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Polarity TIM Clock Polarity + * @{ + */ +#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler + * @{ + */ +#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ +#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ +#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity + * @{ + */ +#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ +#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler + * @{ + */ +#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state + * @{ + */ +#define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ +#define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ +/** + * @} + */ + +/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state + * @{ + */ +#define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ +#define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ +/** + * @} + */ +/** @defgroup TIM_Lock_level TIM Lock level + * @{ + */ +#define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */ +#define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ +#define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ +#define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ +/** + * @} + */ + +/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable + * @{ + */ +#define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */ +#define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */ +/** + * @} + */ + +/** @defgroup TIM_Break_Polarity TIM Break Input Polarity + * @{ + */ +#define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ +#define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ +/** + * @} + */ + +/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable + * @{ + */ +#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ +#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event + (if none of the break inputs BRK and BRK2 is active) */ +/** + * @} + */ + +/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection + * @{ + */ +#define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ +#define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ +#define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ +#define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ +#define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ +#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ +#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ +#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ +/** + * @} + */ + +/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode + * @{ + */ +#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ +#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ +/** + * @} + */ + +/** @defgroup TIM_Slave_Mode TIM Slave mode + * @{ + */ +#define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ +#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ +#define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ +#define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ +#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes + * @{ + */ +#define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ +#define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ +#define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ +#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ +#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ +#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ +#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ +#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Selection TIM Trigger Selection + * @{ + */ +#define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ +#define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ +#define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ +#define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ +#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ +#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ +#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ +#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ +#define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity + * @{ + */ +#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler + * @{ + */ +#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ +#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ +#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection + * @{ + */ +#define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ +#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ +/** + * @} + */ + +/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length + * @{ + */ +#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +/** + * @} + */ + +/** @defgroup DMA_Handle_index TIM DMA Handle Index + * @{ + */ +#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ +#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ +#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ +#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ +#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ +#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */ +#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ +/** + * @} + */ + +/** @defgroup Channel_CC_State TIM Capture/Compare Channel State + * @{ + */ +#define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ +#define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ +#define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */ +#define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */ +/** + * @} + */ + +/** + * @} + */ +/* End of exported constants -------------------------------------------------*/ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup TIM_Exported_Macros TIM Exported Macros + * @{ + */ + +/** @brief Reset TIM handle state. + * @param __HANDLE__ TIM handle. + * @retval None + */ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->Base_MspInitCallback = NULL; \ + (__HANDLE__)->Base_MspDeInitCallback = NULL; \ + (__HANDLE__)->IC_MspInitCallback = NULL; \ + (__HANDLE__)->IC_MspDeInitCallback = NULL; \ + (__HANDLE__)->OC_MspInitCallback = NULL; \ + (__HANDLE__)->OC_MspDeInitCallback = NULL; \ + (__HANDLE__)->PWM_MspInitCallback = NULL; \ + (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @brief Enable the TIM peripheral. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) + +/** + * @brief Enable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) + +/** + * @brief Disable the TIM peripheral. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_DISABLE(__HANDLE__) \ + do { \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ + { \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ + { \ + (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ + } \ + } \ + } while(0) + +/** + * @brief Disable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled + */ +#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ + do { \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ + { \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ + { \ + (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ + } \ + } \ + } while(0) + +/** + * @brief Disable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + * @note The Main Output Enable of a timer instance is disabled unconditionally + */ +#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) + +/** @brief Enable the specified TIM interrupt. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to enable. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) + +/** @brief Disable the specified TIM interrupt. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to disable. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) + +/** @brief Enable the specified DMA request. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to enable. + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: Update DMA request + * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request + * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request + * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request + * @arg TIM_DMA_COM: Commutation DMA request + * @arg TIM_DMA_TRIGGER: Trigger DMA request + * @retval None + */ +#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) + +/** @brief Disable the specified DMA request. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to disable. + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: Update DMA request + * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request + * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request + * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request + * @arg TIM_DMA_COM: Commutation DMA request + * @arg TIM_DMA_TRIGGER: Trigger DMA request + * @retval None + */ +#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) + +/** @brief Check whether the specified TIM interrupt flag is set or not. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to check. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE: Update interrupt flag + * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag + * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag + * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag + * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag + * @arg TIM_FLAG_COM: Commutation interrupt flag + * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag + * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag + * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag + * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) + +/** @brief Clear the specified TIM interrupt flag. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to clear. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE: Update interrupt flag + * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag + * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag + * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag + * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag + * @arg TIM_FLAG_COM: Commutation interrupt flag + * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag + * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag + * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag + * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) + +/** + * @brief Check whether the specified TIM interrupt source is enabled or not. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the TIM interrupt source to check. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval The state of TIM_IT (SET or RESET). + */ +#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \ + == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Clear the TIM interrupt pending bits. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) + +/** + * @brief Indicates whether or not the TIM Counter is used as downcounter. + * @param __HANDLE__ TIM handle. + * @retval False (Counter used as upcounter) or True (Counter used as downcounter) + * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder +mode. + */ +#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) + +/** + * @brief Set the TIM Prescaler on runtime. + * @param __HANDLE__ TIM handle. + * @param __PRESC__ specifies the Prescaler new value. + * @retval None + */ +#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) + +/** + * @brief Set the TIM Counter Register value on runtime. + * @param __HANDLE__ TIM handle. + * @param __COUNTER__ specifies the Counter register new value. + * @retval None + */ +#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) + +/** + * @brief Get the TIM Counter Register value on runtime. + * @param __HANDLE__ TIM handle. + * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) + */ +#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) + +/** + * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. + * @param __HANDLE__ TIM handle. + * @param __AUTORELOAD__ specifies the Counter register new value. + * @retval None + */ +#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ + do{ \ + (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ + (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ + } while(0) + +/** + * @brief Get the TIM Autoreload Register value on runtime. + * @param __HANDLE__ TIM handle. + * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) + */ +#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) + +/** + * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. + * @param __HANDLE__ TIM handle. + * @param __CKD__ specifies the clock division value. + * This parameter can be one of the following value: + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT + * @retval None + */ +#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ + do{ \ + (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ + (__HANDLE__)->Instance->CR1 |= (__CKD__); \ + (__HANDLE__)->Init.ClockDivision = (__CKD__); \ + } while(0) + +/** + * @brief Get the TIM Clock Division value on runtime. + * @param __HANDLE__ TIM handle. + * @retval The clock division can be one of the following values: + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT + */ +#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) + +/** + * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __ICPSC__ specifies the Input Capture4 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ + do{ \ + TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ + } while(0) + +/** + * @brief Get the TIM Input Capture prescaler on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: get input capture 1 prescaler value + * @arg TIM_CHANNEL_2: get input capture 2 prescaler value + * @arg TIM_CHANNEL_3: get input capture 3 prescaler value + * @arg TIM_CHANNEL_4: get input capture 4 prescaler value + * @retval The input capture prescaler can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + */ +#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ + (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) + +/** + * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __COMPARE__ specifies the Capture Compare register new value. + * @retval None + */ +#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ + ((__HANDLE__)->Instance->CCR4 = (__COMPARE__))) + +/** + * @brief Get the TIM Capture Compare Register value on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channel associated with the capture compare register + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: get capture/compare 1 register value + * @arg TIM_CHANNEL_2: get capture/compare 2 register value + * @arg TIM_CHANNEL_3: get capture/compare 3 register value + * @arg TIM_CHANNEL_4: get capture/compare 4 register value + * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) + */ +#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ + ((__HANDLE__)->Instance->CCR4)) + +/** + * @brief Set the TIM Output compare preload. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval None + */ +#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ + ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE)) + +/** + * @brief Reset the TIM Output compare preload. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval None + */ +#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ + ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE)) + +/** + * @brief Enable fast mode for a given channel. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @note When fast mode is enabled an active edge on the trigger input acts + * like a compare match on CCx output. Delay to sample the trigger + * input and to activate CCx output is reduced to 3 clock cycles. + * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. + * @retval None + */ +#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ + ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE)) + +/** + * @brief Disable fast mode for a given channel. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @note When fast mode is disabled CCx output behaves normally depending + * on counter and CCRx values even when the trigger is ON. The minimum + * delay to activate CCx output when an active edge occurs on the + * trigger input is 5 clock cycles. + * @retval None + */ +#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ + ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE)) + +/** + * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. + * @param __HANDLE__ TIM handle. + * @note When the URS bit of the TIMx_CR1 register is set, only counter + * overflow/underflow generates an update interrupt or DMA request (if + * enabled) + * @retval None + */ +#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) + +/** + * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. + * @param __HANDLE__ TIM handle. + * @note When the URS bit of the TIMx_CR1 register is reset, any of the + * following events generate an update interrupt or DMA request (if + * enabled): + * _ Counter overflow underflow + * _ Setting the UG bit + * _ Update generation through the slave mode controller + * @retval None + */ +#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) + +/** + * @brief Set the TIM Capture x input polarity on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __POLARITY__ Polarity for TIx source + * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge + * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge + * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge + * @retval None + */ +#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ + do{ \ + TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ + }while(0) + +/** + * @} + */ +/* End of exported macros ----------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup TIM_Private_Constants TIM Private Constants + * @{ + */ +/* The counter of a timer instance is disabled only if all the CCx and CCxN + channels have been disabled */ +#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) +#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) +/** + * @} + */ +/* End of private constants --------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup TIM_Private_Macros TIM Private Macros + * @{ + */ +#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \ + ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)) + +#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ + ((__BASE__) == TIM_DMABASE_CR2) || \ + ((__BASE__) == TIM_DMABASE_SMCR) || \ + ((__BASE__) == TIM_DMABASE_DIER) || \ + ((__BASE__) == TIM_DMABASE_SR) || \ + ((__BASE__) == TIM_DMABASE_EGR) || \ + ((__BASE__) == TIM_DMABASE_CCMR1) || \ + ((__BASE__) == TIM_DMABASE_CCMR2) || \ + ((__BASE__) == TIM_DMABASE_CCER) || \ + ((__BASE__) == TIM_DMABASE_CNT) || \ + ((__BASE__) == TIM_DMABASE_PSC) || \ + ((__BASE__) == TIM_DMABASE_ARR) || \ + ((__BASE__) == TIM_DMABASE_RCR) || \ + ((__BASE__) == TIM_DMABASE_CCR1) || \ + ((__BASE__) == TIM_DMABASE_CCR2) || \ + ((__BASE__) == TIM_DMABASE_CCR3) || \ + ((__BASE__) == TIM_DMABASE_CCR4) || \ + ((__BASE__) == TIM_DMABASE_BDTR)) + +#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFF00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) + +#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ + ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) + +#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ + ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ + ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) + +#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ + ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) + +#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ + ((__STATE__) == TIM_OCFAST_ENABLE)) + +#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ + ((__POLARITY__) == TIM_OCPOLARITY_LOW)) + +#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \ + ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) + +#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \ + ((__STATE__) == TIM_OCIDLESTATE_RESET)) + +#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ + ((__STATE__) == TIM_OCNIDLESTATE_RESET)) + +#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING)) + +#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ + ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) + +#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ + ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ + ((__SELECTION__) == TIM_ICSELECTION_TRC)) + +#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV8)) + +#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ + ((__MODE__) == TIM_OPMODE_REPETITIVE)) + +#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ + ((__MODE__) == TIM_ENCODERMODE_TI2) || \ + ((__MODE__) == TIM_ENCODERMODE_TI12)) + +#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) + +#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2) || \ + ((__CHANNEL__) == TIM_CHANNEL_3) || \ + ((__CHANNEL__) == TIM_CHANNEL_4) || \ + ((__CHANNEL__) == TIM_CHANNEL_ALL)) + +#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2)) + +#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2) || \ + ((__CHANNEL__) == TIM_CHANNEL_3)) + +#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)) + +#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) + +#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) + +#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ + ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) + +#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) + +#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ + ((__STATE__) == TIM_OSSR_DISABLE)) + +#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \ + ((__STATE__) == TIM_OSSI_DISABLE)) + +#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_1) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_3)) + +#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) + + +#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ + ((__STATE__) == TIM_BREAK_DISABLE)) + +#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ + ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) + +#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ + ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) + +#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ + ((__SOURCE__) == TIM_TRGO_ENABLE) || \ + ((__SOURCE__) == TIM_TRGO_UPDATE) || \ + ((__SOURCE__) == TIM_TRGO_OC1) || \ + ((__SOURCE__) == TIM_TRGO_OC1REF) || \ + ((__SOURCE__) == TIM_TRGO_OC2REF) || \ + ((__SOURCE__) == TIM_TRGO_OC3REF) || \ + ((__SOURCE__) == TIM_TRGO_OC4REF)) + +#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ + ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) + +#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ + ((__MODE__) == TIM_SLAVEMODE_RESET) || \ + ((__MODE__) == TIM_SLAVEMODE_GATED) || \ + ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ + ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1)) + +#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ + ((__MODE__) == TIM_OCMODE_PWM2)) + +#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ + ((__MODE__) == TIM_OCMODE_ACTIVE) || \ + ((__MODE__) == TIM_OCMODE_INACTIVE) || \ + ((__MODE__) == TIM_OCMODE_TOGGLE) || \ + ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ + ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)) + +#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF)) + +#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_NONE)) + +#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) + +#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) + +#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ + ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) + +#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) + +#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) + +#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) + +#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ + ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) + +#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ + ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) + +#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ + ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) + +#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ + ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) + +/** + * @} + */ +/* End of private macros -----------------------------------------------------*/ + +/* Include TIM HAL Extended module */ +#include "stm32f4xx_hal_tim_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIM_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions + * @brief Time Base functions + * @{ + */ +/* Time Base functions ********************************************************/ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions + * @brief TIM Output Compare functions + * @{ + */ +/* Timer Output Compare functions *********************************************/ +HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions + * @brief TIM PWM functions + * @{ + */ +/* Timer PWM functions ********************************************************/ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions + * @brief TIM Input Capture functions + * @{ + */ +/* Timer Input Capture functions **********************************************/ +HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions + * @brief TIM One Pulse functions + * @{ + */ +/* Timer One Pulse functions **************************************************/ +HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); +HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions + * @brief TIM Encoder functions + * @{ + */ +/* Timer Encoder functions ****************************************************/ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, + uint32_t *pData2, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management + * @brief IRQ handler management + * @{ + */ +/* Interrupt Handler functions ***********************************************/ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ +/* Control functions *********************************************************/ +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, + uint32_t OutputChannel, uint32_t InputChannel); +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig); +HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); +HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); +uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions + * @brief TIM Callbacks functions + * @{ + */ +/* Callback in non blocking modes (Interrupt and DMA) *************************/ +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, + pTIM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions + * @brief Peripheral State functions + * @{ + */ +/* Peripheral State functions ************************************************/ +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private functions----------------------------------------------------------*/ +/** @defgroup TIM_Private_Functions TIM Private Functions + * @{ + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); +void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); + +void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); +void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); +void TIM_DMAError(DMA_HandleTypeDef *hdma); +void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); +void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); +void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +void TIM_ResetCallback(TIM_HandleTypeDef *htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ +/* End of private functions --------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F4xx_HAL_TIM_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h new file mode 100644 index 0000000..88ce281 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h @@ -0,0 +1,356 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_tim_ex.h + * @author MCD Application Team + * @brief Header file of TIM HAL Extended module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F4xx_HAL_TIM_EX_H +#define STM32F4xx_HAL_TIM_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup TIMEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types + * @{ + */ + +/** + * @brief TIM Hall sensor Configuration Structure definition + */ + +typedef struct +{ + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC1Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ +} TIM_HallSensor_InitTypeDef; +/** + * @} + */ +/* End of exported types -----------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants + * @{ + */ + +/** @defgroup TIMEx_Remap TIM Extended Remapping + * @{ + */ +#if defined (TIM2) +#if defined(TIM8) +#define TIM_TIM2_TIM8_TRGO 0x00000000U /*!< TIM2 ITR1 is connected to TIM8 TRGO */ +#else +#define TIM_TIM2_ETH_PTP TIM_OR_ITR1_RMP_0 /*!< TIM2 ITR1 is connected to PTP trigger output */ +#endif /* TIM8 */ +#define TIM_TIM2_USBFS_SOF TIM_OR_ITR1_RMP_1 /*!< TIM2 ITR1 is connected to OTG FS SOF */ +#define TIM_TIM2_USBHS_SOF (TIM_OR_ITR1_RMP_1 | TIM_OR_ITR1_RMP_0) /*!< TIM2 ITR1 is connected to OTG HS SOF */ +#endif /* TIM2 */ + +#define TIM_TIM5_GPIO 0x00000000U /*!< TIM5 TI4 is connected to GPIO */ +#define TIM_TIM5_LSI TIM_OR_TI4_RMP_0 /*!< TIM5 TI4 is connected to LSI */ +#define TIM_TIM5_LSE TIM_OR_TI4_RMP_1 /*!< TIM5 TI4 is connected to LSE */ +#define TIM_TIM5_RTC (TIM_OR_TI4_RMP_1 | TIM_OR_TI4_RMP_0) /*!< TIM5 TI4 is connected to the RTC wakeup interrupt */ + +#define TIM_TIM11_GPIO 0x00000000U /*!< TIM11 TI1 is connected to GPIO */ +#define TIM_TIM11_HSE TIM_OR_TI1_RMP_1 /*!< TIM11 TI1 is connected to HSE_RTC clock */ +#if defined(SPDIFRX) +#define TIM_TIM11_SPDIFRX TIM_OR_TI1_RMP_0 /*!< TIM11 TI1 is connected to SPDIFRX_FRAME_SYNC */ +#endif /* SPDIFRX*/ + +#if defined(LPTIM_OR_TIM1_ITR2_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) +#define LPTIM_REMAP_MASK 0x10000000U + +#define TIM_TIM9_TIM3_TRGO LPTIM_REMAP_MASK /*!< TIM9 ITR1 is connected to TIM3 TRGO */ +#define TIM_TIM9_LPTIM (LPTIM_REMAP_MASK | LPTIM_OR_TIM9_ITR1_RMP) /*!< TIM9 ITR1 is connected to LPTIM1 output */ + +#define TIM_TIM5_TIM3_TRGO LPTIM_REMAP_MASK /*!< TIM5 ITR1 is connected to TIM3 TRGO */ +#define TIM_TIM5_LPTIM (LPTIM_REMAP_MASK | LPTIM_OR_TIM5_ITR1_RMP) /*!< TIM5 ITR1 is connected to LPTIM1 output */ + +#define TIM_TIM1_TIM3_TRGO LPTIM_REMAP_MASK /*!< TIM1 ITR2 is connected to TIM3 TRGO */ +#define TIM_TIM1_LPTIM (LPTIM_REMAP_MASK | LPTIM_OR_TIM1_ITR2_RMP) /*!< TIM1 ITR2 is connected to LPTIM1 output */ +#endif /* LPTIM_OR_TIM1_ITR2_RMP && LPTIM_OR_TIM5_ITR1_RMP && LPTIM_OR_TIM5_ITR1_RMP */ +/** + * @} + */ + +/** + * @} + */ +/* End of exported constants -------------------------------------------------*/ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros + * @{ + */ + +/** + * @} + */ +/* End of exported macro -----------------------------------------------------*/ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros + * @{ + */ +#if defined(SPDIFRX) +#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \ + ((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO) || \ + ((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \ + ((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \ + (((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \ + ((TIM_REMAP) == TIM_TIM5_LSI) || \ + ((TIM_REMAP) == TIM_TIM5_LSE) || \ + ((TIM_REMAP) == TIM_TIM5_RTC))) || \ + (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \ + ((TIM_REMAP) == TIM_TIM11_SPDIFRX) || \ + ((TIM_REMAP) == TIM_TIM11_HSE)))) +#elif defined(TIM2) +#if defined(LPTIM_OR_TIM1_ITR2_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) +#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \ + ((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO) || \ + ((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \ + ((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \ + (((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \ + ((TIM_REMAP) == TIM_TIM5_LSI) || \ + ((TIM_REMAP) == TIM_TIM5_LSE) || \ + ((TIM_REMAP) == TIM_TIM5_RTC))) || \ + (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \ + ((TIM_REMAP) == TIM_TIM11_HSE))) || \ + (((INSTANCE) == TIM1) && (((TIM_REMAP) == TIM_TIM1_TIM3_TRGO) || \ + ((TIM_REMAP) == TIM_TIM1_LPTIM))) || \ + (((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_TIM3_TRGO) || \ + ((TIM_REMAP) == TIM_TIM5_LPTIM))) || \ + (((INSTANCE) == TIM9) && (((TIM_REMAP) == TIM_TIM9_TIM3_TRGO) || \ + ((TIM_REMAP) == TIM_TIM9_LPTIM)))) +#elif defined(TIM8) +#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \ + ((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO) || \ + ((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \ + ((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \ + (((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \ + ((TIM_REMAP) == TIM_TIM5_LSI) || \ + ((TIM_REMAP) == TIM_TIM5_LSE) || \ + ((TIM_REMAP) == TIM_TIM5_RTC))) || \ + (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \ + ((TIM_REMAP) == TIM_TIM11_HSE)))) +#else +#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \ + ((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_ETH_PTP) || \ + ((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \ + ((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \ + (((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \ + ((TIM_REMAP) == TIM_TIM5_LSI) || \ + ((TIM_REMAP) == TIM_TIM5_LSE) || \ + ((TIM_REMAP) == TIM_TIM5_RTC))) || \ + (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \ + ((TIM_REMAP) == TIM_TIM11_HSE)))) +#endif /* LPTIM_OR_TIM1_ITR2_RMP && LPTIM_OR_TIM5_ITR1_RMP && LPTIM_OR_TIM5_ITR1_RMP */ +#else +#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \ + ((((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \ + ((TIM_REMAP) == TIM_TIM5_LSI) || \ + ((TIM_REMAP) == TIM_TIM5_LSE) || \ + ((TIM_REMAP) == TIM_TIM5_RTC))) || \ + (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \ + ((TIM_REMAP) == TIM_TIM11_HSE)))) +#endif /* SPDIFRX */ + +/** + * @} + */ +/* End of private macro ------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions + * @{ + */ + +/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions + * @brief Timer Hall Sensor functions + * @{ + */ +/* Timer Hall Sensor functions **********************************************/ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); + +void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); + +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions + * @brief Timer Complementary Output Compare functions + * @{ + */ +/* Timer Complementary Output Compare functions *****************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions + * @brief Timer Complementary PWM functions + * @{ + */ +/* Timer Complementary PWM functions ****************************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions + * @brief Timer Complementary One Pulse functions + * @{ + */ +/* Timer Complementary One Pulse functions **********************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ +/* Extended Control functions ************************************************/ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + TIM_MasterConfigTypeDef *sMasterConfig); +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, + TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); +HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions + * @brief Extended Callbacks functions + * @{ + */ +/* Extended Callback **********************************************************/ +void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions + * @brief Extended Peripheral State functions + * @{ + */ +/* Extended Peripheral State functions ***************************************/ +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private functions----------------------------------------------------------*/ +/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions + * @{ + */ +void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); +void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma); +/** + * @} + */ +/* End of private functions --------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32F4xx_HAL_TIM_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h new file mode 100644 index 0000000..2154a02 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h @@ -0,0 +1,846 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_uart.h + * @author MCD Application Team + * @brief Header file of UART HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_UART_H +#define __STM32F4xx_HAL_UART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup UART + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UART_Exported_Types UART Exported Types + * @{ + */ + +/** + * @brief UART Init Structure definition + */ +typedef struct +{ + uint32_t BaudRate; /*!< This member configures the UART communication baud rate. + The baud rate is computed using the following formula: + - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (huart->Init.BaudRate))) + - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8 * (OVR8+1)) + 0.5 + Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */ + + uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref UART_Word_Length */ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref UART_Stop_Bits */ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref UART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref UART_Mode */ + + uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled or disabled. + This parameter can be a value of @ref UART_Hardware_Flow_Control */ + + uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8). + This parameter can be a value of @ref UART_Over_Sampling */ +} UART_InitTypeDef; + +/** + * @brief HAL UART State structures definition + * @note HAL UART State value is a combination of 2 different substates: gState and RxState. + * - gState contains UART state information related to global Handle management + * and also information related to Tx operations. + * gState value coding follow below described bitmap : + * b7-b6 Error information + * 00 : No Error + * 01 : (Not Used) + * 10 : Timeout + * 11 : Error + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral not initialized. HAL UART Init function already called) + * b4-b3 (not used) + * xx : Should be set to 00 + * b2 Intrinsic process state + * 0 : Ready + * 1 : Busy (Peripheral busy with some configuration or internal operations) + * b1 (not used) + * x : Should be set to 0 + * b0 Tx state + * 0 : Ready (no Tx operation ongoing) + * 1 : Busy (Tx operation ongoing) + * - RxState contains information related to Rx operations. + * RxState value coding follow below described bitmap : + * b7-b6 (not used) + * xx : Should be set to 00 + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral not initialized) + * b4-b2 (not used) + * xxx : Should be set to 000 + * b1 Rx state + * 0 : Ready (no Rx operation ongoing) + * 1 : Busy (Rx operation ongoing) + * b0 (not used) + * x : Should be set to 0. + */ +typedef enum +{ + HAL_UART_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized + Value is allowed for gState and RxState */ + HAL_UART_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use + Value is allowed for gState and RxState */ + HAL_UART_STATE_BUSY = 0x24U, /*!< an internal process is ongoing + Value is allowed for gState only */ + HAL_UART_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing + Value is allowed for gState only */ + HAL_UART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing + Value is allowed for RxState only */ + HAL_UART_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing + Not to be used for neither gState nor RxState. + Value is result of combination (Or) between gState and RxState values */ + HAL_UART_STATE_TIMEOUT = 0xA0U, /*!< Timeout state + Value is allowed for gState only */ + HAL_UART_STATE_ERROR = 0xE0U /*!< Error + Value is allowed for gState only */ +} HAL_UART_StateTypeDef; + +/** + * @brief UART handle Structure definition + */ +typedef struct __UART_HandleTypeDef +{ + USART_TypeDef *Instance; /*!< UART registers base address */ + + UART_InitTypeDef Init; /*!< UART communication parameters */ + + uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */ + + uint16_t TxXferSize; /*!< UART Tx Transfer size */ + + __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */ + + uint16_t RxXferSize; /*!< UART Rx Transfer size */ + + __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */ + + DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */ + + HAL_LockTypeDef Lock; /*!< Locking object */ + + __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management + and also related to Tx operations. + This parameter can be a value of @ref HAL_UART_StateTypeDef */ + + __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. + This parameter can be a value of @ref HAL_UART_StateTypeDef */ + + __IO uint32_t ErrorCode; /*!< UART Error code */ + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Half Complete Callback */ + void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Complete Callback */ + void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Half Complete Callback */ + void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Complete Callback */ + void (* ErrorCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Error Callback */ + void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Complete Callback */ + void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */ + void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Receive Complete Callback */ + void (* WakeupCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */ + + void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */ + void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */ +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +} UART_HandleTypeDef; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +/** + * @brief HAL UART Callback ID enumeration definition + */ +typedef enum +{ + HAL_UART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< UART Tx Half Complete Callback ID */ + HAL_UART_TX_COMPLETE_CB_ID = 0x01U, /*!< UART Tx Complete Callback ID */ + HAL_UART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< UART Rx Half Complete Callback ID */ + HAL_UART_RX_COMPLETE_CB_ID = 0x03U, /*!< UART Rx Complete Callback ID */ + HAL_UART_ERROR_CB_ID = 0x04U, /*!< UART Error Callback ID */ + HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, /*!< UART Abort Complete Callback ID */ + HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< UART Abort Transmit Complete Callback ID */ + HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< UART Abort Receive Complete Callback ID */ + HAL_UART_WAKEUP_CB_ID = 0x08U, /*!< UART Wakeup Callback ID */ + + HAL_UART_MSPINIT_CB_ID = 0x0BU, /*!< UART MspInit callback ID */ + HAL_UART_MSPDEINIT_CB_ID = 0x0CU /*!< UART MspDeInit callback ID */ + +} HAL_UART_CallbackIDTypeDef; + +/** + * @brief HAL UART Callback pointer definition + */ +typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */ + +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UART_Exported_Constants UART Exported Constants + * @{ + */ + +/** @defgroup UART_Error_Code UART Error Code + * @{ + */ +#define HAL_UART_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_UART_ERROR_PE 0x00000001U /*!< Parity error */ +#define HAL_UART_ERROR_NE 0x00000002U /*!< Noise error */ +#define HAL_UART_ERROR_FE 0x00000004U /*!< Frame error */ +#define HAL_UART_ERROR_ORE 0x00000008U /*!< Overrun error */ +#define HAL_UART_ERROR_DMA 0x00000010U /*!< DMA transfer error */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +#define HAL_UART_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid Callback error */ +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup UART_Word_Length UART Word Length + * @{ + */ +#define UART_WORDLENGTH_8B 0x00000000U +#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M) +/** + * @} + */ + +/** @defgroup UART_Stop_Bits UART Number of Stop Bits + * @{ + */ +#define UART_STOPBITS_1 0x00000000U +#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) +/** + * @} + */ + +/** @defgroup UART_Parity UART Parity + * @{ + */ +#define UART_PARITY_NONE 0x00000000U +#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) +#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) +/** + * @} + */ + +/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control + * @{ + */ +#define UART_HWCONTROL_NONE 0x00000000U +#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE) +#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE) +#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE)) +/** + * @} + */ + +/** @defgroup UART_Mode UART Transfer Mode + * @{ + */ +#define UART_MODE_RX ((uint32_t)USART_CR1_RE) +#define UART_MODE_TX ((uint32_t)USART_CR1_TE) +#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE | USART_CR1_RE)) +/** + * @} + */ + +/** @defgroup UART_State UART State + * @{ + */ +#define UART_STATE_DISABLE 0x00000000U +#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE) +/** + * @} + */ + +/** @defgroup UART_Over_Sampling UART Over Sampling + * @{ + */ +#define UART_OVERSAMPLING_16 0x00000000U +#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8) +/** + * @} + */ + +/** @defgroup UART_LIN_Break_Detection_Length UART LIN Break Detection Length + * @{ + */ +#define UART_LINBREAKDETECTLENGTH_10B 0x00000000U +#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL) +/** + * @} + */ + +/** @defgroup UART_WakeUp_functions UART Wakeup Functions + * @{ + */ +#define UART_WAKEUPMETHOD_IDLELINE 0x00000000U +#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE) +/** + * @} + */ + +/** @defgroup UART_Flags UART FLags + * Elements values convention: 0xXXXX + * - 0xXXXX : Flag mask in the SR register + * @{ + */ +#define UART_FLAG_CTS ((uint32_t)USART_SR_CTS) +#define UART_FLAG_LBD ((uint32_t)USART_SR_LBD) +#define UART_FLAG_TXE ((uint32_t)USART_SR_TXE) +#define UART_FLAG_TC ((uint32_t)USART_SR_TC) +#define UART_FLAG_RXNE ((uint32_t)USART_SR_RXNE) +#define UART_FLAG_IDLE ((uint32_t)USART_SR_IDLE) +#define UART_FLAG_ORE ((uint32_t)USART_SR_ORE) +#define UART_FLAG_NE ((uint32_t)USART_SR_NE) +#define UART_FLAG_FE ((uint32_t)USART_SR_FE) +#define UART_FLAG_PE ((uint32_t)USART_SR_PE) +/** + * @} + */ + +/** @defgroup UART_Interrupt_definition UART Interrupt Definitions + * Elements values convention: 0xY000XXXX + * - XXXX : Interrupt mask (16 bits) in the Y register + * - Y : Interrupt source register (2bits) + * - 0001: CR1 register + * - 0010: CR2 register + * - 0011: CR3 register + * @{ + */ + +#define UART_IT_PE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_PEIE)) +#define UART_IT_TXE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE)) +#define UART_IT_TC ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TCIE)) +#define UART_IT_RXNE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE)) +#define UART_IT_IDLE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE)) + +#define UART_IT_LBD ((uint32_t)(UART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE)) + +#define UART_IT_CTS ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE)) +#define UART_IT_ERR ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_EIE)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup UART_Exported_Macros UART Exported Macros + * @{ + */ + +/** @brief Reset UART handle gstate & RxState + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @retval None + */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0U) +#else +#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ + } while(0U) +#endif /*USE_HAL_UART_REGISTER_CALLBACKS */ + +/** @brief Flushes the UART DR register + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + */ +#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR) + +/** @brief Checks whether the specified UART flag is set or not. + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) + * @arg UART_FLAG_LBD: LIN Break detection flag + * @arg UART_FLAG_TXE: Transmit data register empty flag + * @arg UART_FLAG_TC: Transmission Complete flag + * @arg UART_FLAG_RXNE: Receive data register not empty flag + * @arg UART_FLAG_IDLE: Idle Line detection flag + * @arg UART_FLAG_ORE: Overrun Error flag + * @arg UART_FLAG_NE: Noise Error flag + * @arg UART_FLAG_FE: Framing Error flag + * @arg UART_FLAG_PE: Parity Error flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) + +/** @brief Clears the specified UART pending flag. + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @param __FLAG__ specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5). + * @arg UART_FLAG_LBD: LIN Break detection flag. + * @arg UART_FLAG_TC: Transmission Complete flag. + * @arg UART_FLAG_RXNE: Receive data register not empty flag. + * + * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (Overrun + * error) and IDLE (Idle line detected) flags are cleared by software + * sequence: a read operation to USART_SR register followed by a read + * operation to USART_DR register. + * @note RXNE flag can be also cleared by a read to the USART_DR register. + * @note TC flag can be also cleared by software sequence: a read operation to + * USART_SR register followed by a write operation to USART_DR register. + * @note TXE flag is cleared only by a write to the USART_DR register. + * + * @retval None + */ +#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) + +/** @brief Clears the UART PE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @retval None + */ +#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg = 0x00U; \ + tmpreg = (__HANDLE__)->Instance->SR; \ + tmpreg = (__HANDLE__)->Instance->DR; \ + UNUSED(tmpreg); \ + } while(0U) + +/** @brief Clears the UART FE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @retval None + */ +#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) + +/** @brief Clears the UART NE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @retval None + */ +#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) + +/** @brief Clears the UART ORE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @retval None + */ +#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) + +/** @brief Clears the UART IDLE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @retval None + */ +#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) + +/** @brief Enable the specified UART interrupt. + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @param __INTERRUPT__ specifies the UART interrupt source to enable. + * This parameter can be one of the following values: + * @arg UART_IT_CTS: CTS change interrupt + * @arg UART_IT_LBD: LIN Break detection interrupt + * @arg UART_IT_TXE: Transmit Data Register empty interrupt + * @arg UART_IT_TC: Transmission complete interrupt + * @arg UART_IT_RXNE: Receive Data register not empty interrupt + * @arg UART_IT_IDLE: Idle line detection interrupt + * @arg UART_IT_PE: Parity Error interrupt + * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \ + (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): \ + ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK))) + +/** @brief Disable the specified UART interrupt. + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @param __INTERRUPT__ specifies the UART interrupt source to disable. + * This parameter can be one of the following values: + * @arg UART_IT_CTS: CTS change interrupt + * @arg UART_IT_LBD: LIN Break detection interrupt + * @arg UART_IT_TXE: Transmit Data Register empty interrupt + * @arg UART_IT_TC: Transmission complete interrupt + * @arg UART_IT_RXNE: Receive Data register not empty interrupt + * @arg UART_IT_IDLE: Idle line detection interrupt + * @arg UART_IT_PE: Parity Error interrupt + * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \ + (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \ + ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK))) + +/** @brief Checks whether the specified UART interrupt source is enabled or not. + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @param __IT__ specifies the UART interrupt source to check. + * This parameter can be one of the following values: + * @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) + * @arg UART_IT_LBD: LIN Break detection interrupt + * @arg UART_IT_TXE: Transmit Data Register empty interrupt + * @arg UART_IT_TC: Transmission complete interrupt + * @arg UART_IT_RXNE: Receive Data register not empty interrupt + * @arg UART_IT_IDLE: Idle line detection interrupt + * @arg UART_IT_ERR: Error interrupt + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == UART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == UART_CR2_REG_INDEX)? \ + (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & UART_IT_MASK)) + +/** @brief Enable CTS flow control + * @note This macro allows to enable CTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) + * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * The Handle Instance can be any USARTx (supporting the HW Flow control feature). + * It is used to select the USART peripheral (USART availability and x value depending on device). + * @retval None + */ +#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \ + } while(0U) + +/** @brief Disable CTS flow control + * @note This macro allows to disable CTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) + * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * The Handle Instance can be any USARTx (supporting the HW Flow control feature). + * It is used to select the USART peripheral (USART availability and x value depending on device). + * @retval None + */ +#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \ + do{ \ + CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \ + } while(0U) + +/** @brief Enable RTS flow control + * This macro allows to enable RTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) + * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * The Handle Instance can be any USARTx (supporting the HW Flow control feature). + * It is used to select the USART peripheral (USART availability and x value depending on device). + * @retval None + */ +#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \ + (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \ + } while(0U) + +/** @brief Disable RTS flow control + * This macro allows to disable RTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) + * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * The Handle Instance can be any USARTx (supporting the HW Flow control feature). + * It is used to select the USART peripheral (USART availability and x value depending on device). + * @retval None + */ +#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \ + do{ \ + CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ + (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \ + } while(0U) + +/** @brief Macro to enable the UART's one bit sample method + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) + +/** @brief Macro to disable the UART's one bit sample method + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT)) + +/** @brief Enable UART + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) + +/** @brief Disable UART + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup UART_Exported_Functions + * @{ + */ + +/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization/de-initialization functions **********************************/ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength); +HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod); +HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart); +void HAL_UART_MspInit(UART_HandleTypeDef *huart); +void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group2 IO operation functions + * @{ + */ + +/* IO operation functions *******************************************************/ +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart); +/* Transfer Abort functions */ +HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart); + +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart); +void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart); + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group3 + * @{ + */ +/* Peripheral Control functions ************************************************/ +HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart); +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group4 + * @{ + */ +/* Peripheral State functions **************************************************/ +HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart); +uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup UART_Private_Constants UART Private Constants + * @{ + */ +/** @brief UART interruptions flag mask + * + */ +#define UART_IT_MASK 0x0000FFFFU + +#define UART_CR1_REG_INDEX 1U +#define UART_CR2_REG_INDEX 2U +#define UART_CR3_REG_INDEX 3U +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup UART_Private_Macros UART Private Macros + * @{ + */ +#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \ + ((LENGTH) == UART_WORDLENGTH_9B)) +#define IS_UART_LIN_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B)) +#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \ + ((STOPBITS) == UART_STOPBITS_2)) +#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \ + ((PARITY) == UART_PARITY_EVEN) || \ + ((PARITY) == UART_PARITY_ODD)) +#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\ + (((CONTROL) == UART_HWCONTROL_NONE) || \ + ((CONTROL) == UART_HWCONTROL_RTS) || \ + ((CONTROL) == UART_HWCONTROL_CTS) || \ + ((CONTROL) == UART_HWCONTROL_RTS_CTS)) +#define IS_UART_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x00U)) +#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \ + ((STATE) == UART_STATE_ENABLE)) +#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \ + ((SAMPLING) == UART_OVERSAMPLING_8)) +#define IS_UART_LIN_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16)) +#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \ + ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B)) +#define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \ + ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK)) +#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) <= 10500000U) +#define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0x0FU) + +#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) ((uint32_t)((((uint64_t)(_PCLK_))*25U)/(4U*((uint64_t)(_BAUD_))))) +#define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_) (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100U) +#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) ((((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U) + 50U) / 100U) +/* UART BRR = mantissa + overflow + fraction + = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */ +#define UART_BRR_SAMPLING16(_PCLK_, _BAUD_) ((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4U) + \ + (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0xF0U) + \ + (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0FU)) + +#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) ((uint32_t)((((uint64_t)(_PCLK_))*25U)/(2U*((uint64_t)(_BAUD_))))) +#define UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_) (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100U) +#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) ((((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U) + 50U) / 100U) +/* UART BRR = mantissa + overflow + fraction + = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07U) */ +#define UART_BRR_SAMPLING8(_PCLK_, _BAUD_) ((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4U) + \ + ((UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0xF8U) << 1U) + \ + (UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x07U)) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup UART_Private_Functions UART Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_UART_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h new file mode 100644 index 0000000..302ab81 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h @@ -0,0 +1,511 @@ +/** + ****************************************************************************** + * @file stm32f4xx_ll_usb.h + * @author MCD Application Team + * @brief Header file of USB Low Layer HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F4xx_LL_USB_H +#define STM32F4xx_LL_USB_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup USB_LL + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief USB Mode definition + */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + +typedef enum +{ + USB_DEVICE_MODE = 0, + USB_HOST_MODE = 1, + USB_DRD_MODE = 2 +} USB_OTG_ModeTypeDef; + +/** + * @brief URB States definition + */ +typedef enum +{ + URB_IDLE = 0, + URB_DONE, + URB_NOTREADY, + URB_NYET, + URB_ERROR, + URB_STALL +} USB_OTG_URBStateTypeDef; + +/** + * @brief Host channel States definition + */ +typedef enum +{ + HC_IDLE = 0, + HC_XFRC, + HC_HALTED, + HC_NAK, + HC_NYET, + HC_STALL, + HC_XACTERR, + HC_BBLERR, + HC_DATATGLERR +} USB_OTG_HCStateTypeDef; + +/** + * @brief USB Instance Initialization Structure definition + */ +typedef struct +{ + uint32_t dev_endpoints; /*!< Device Endpoints number. + This parameter depends on the used USB core. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint32_t Host_channels; /*!< Host Channels number. + This parameter Depends on the used USB core. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint32_t speed; /*!< USB Core speed. + This parameter can be any value of @ref USB_Core_Speed */ + + uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA used only for OTG HS. */ + + uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ + + uint32_t phy_itface; /*!< Select the used PHY interface. + This parameter can be any value of @ref USB_Core_PHY */ + + uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ + + uint32_t low_power_enable; /*!< Enable or disable the low power mode. */ + + uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */ + + uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */ + + uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */ + + uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */ + + uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */ + +} USB_OTG_CfgTypeDef; + +typedef struct +{ + uint8_t num; /*!< Endpoint number + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint8_t is_in; /*!< Endpoint direction + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t is_stall; /*!< Endpoint stall condition + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t type; /*!< Endpoint type + This parameter can be any value of @ref USB_EP_Type_ */ + + uint8_t data_pid_start; /*!< Initial data PID + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t even_odd_frame; /*!< IFrame parity + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint16_t tx_fifo_num; /*!< Transmission FIFO number + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint32_t maxpacket; /*!< Endpoint Max packet size + This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ + + uint8_t *xfer_buff; /*!< Pointer to transfer buffer */ + + uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */ + + uint32_t xfer_len; /*!< Current transfer length */ + + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ +} USB_OTG_EPTypeDef; + +typedef struct +{ + uint8_t dev_addr; /*!< USB device address. + This parameter must be a number between Min_Data = 1 and Max_Data = 255 */ + + uint8_t ch_num; /*!< Host channel number. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint8_t ep_num; /*!< Endpoint number. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint8_t ep_is_in; /*!< Endpoint direction + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t speed; /*!< USB Host speed. + This parameter can be any value of @ref USB_Core_Speed_ */ + + uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */ + + uint8_t process_ping; /*!< Execute the PING protocol for HS mode. */ + + uint8_t ep_type; /*!< Endpoint Type. + This parameter can be any value of @ref USB_EP_Type_ */ + + uint16_t max_packet; /*!< Endpoint Max packet size. + This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ + + uint8_t data_pid; /*!< Initial data PID. + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */ + + uint32_t xfer_len; /*!< Current transfer length. */ + + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */ + + uint8_t toggle_in; /*!< IN transfer current toggle flag. + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t toggle_out; /*!< OUT transfer current toggle flag + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */ + + uint32_t ErrCnt; /*!< Host channel error count. */ + + USB_OTG_URBStateTypeDef urb_state; /*!< URB state. + This parameter can be any value of @ref USB_OTG_URBStateTypeDef */ + + USB_OTG_HCStateTypeDef state; /*!< Host Channel state. + This parameter can be any value of @ref USB_OTG_HCStateTypeDef */ +} USB_OTG_HCTypeDef; +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup PCD_Exported_Constants PCD Exported Constants + * @{ + */ + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** @defgroup USB_OTG_CORE VERSION ID + * @{ + */ +#define USB_OTG_CORE_ID_300A 0x4F54300AU +#define USB_OTG_CORE_ID_310A 0x4F54310AU +/** + * @} + */ + +/** @defgroup USB_Core_Mode_ USB Core Mode + * @{ + */ +#define USB_OTG_MODE_DEVICE 0U +#define USB_OTG_MODE_HOST 1U +#define USB_OTG_MODE_DRD 2U +/** + * @} + */ + +/** @defgroup USB_LL Device Speed + * @{ + */ +#define USBD_HS_SPEED 0U +#define USBD_HSINFS_SPEED 1U +#define USBH_HS_SPEED 0U +#define USBD_FS_SPEED 2U +#define USBH_FSLS_SPEED 1U +/** + * @} + */ + +/** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed + * @{ + */ +#define USB_OTG_SPEED_HIGH 0U +#define USB_OTG_SPEED_HIGH_IN_FULL 1U +#define USB_OTG_SPEED_FULL 3U +/** + * @} + */ + +/** @defgroup USB_LL_Core_PHY USB Low Layer Core PHY + * @{ + */ +#define USB_OTG_ULPI_PHY 1U +#define USB_OTG_EMBEDDED_PHY 2U +/** + * @} + */ + +/** @defgroup USB_LL_Turnaround_Timeout Turnaround Timeout Value + * @{ + */ +#ifndef USBD_HS_TRDT_VALUE +#define USBD_HS_TRDT_VALUE 9U +#endif /* USBD_HS_TRDT_VALUE */ +#ifndef USBD_FS_TRDT_VALUE +#define USBD_FS_TRDT_VALUE 5U +#define USBD_DEFAULT_TRDT_VALUE 9U +#endif /* USBD_HS_TRDT_VALUE */ +/** + * @} + */ + +/** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS + * @{ + */ +#define USB_OTG_HS_MAX_PACKET_SIZE 512U +#define USB_OTG_FS_MAX_PACKET_SIZE 64U +#define USB_OTG_MAX_EP0_SIZE 64U +/** + * @} + */ + +/** @defgroup USB_LL_Core_PHY_Frequency USB Low Layer Core PHY Frequency + * @{ + */ +#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << 1) +#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << 1) +#define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << 1) +/** + * @} + */ + +/** @defgroup USB_LL_CORE_Frame_Interval USB Low Layer Core Frame Interval + * @{ + */ +#define DCFG_FRAME_INTERVAL_80 0U +#define DCFG_FRAME_INTERVAL_85 1U +#define DCFG_FRAME_INTERVAL_90 2U +#define DCFG_FRAME_INTERVAL_95 3U +/** + * @} + */ + +/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS + * @{ + */ +#define EP_MPS_64 0U +#define EP_MPS_32 1U +#define EP_MPS_16 2U +#define EP_MPS_8 3U +/** + * @} + */ + +/** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed + * @{ + */ +#define EP_SPEED_LOW 0U +#define EP_SPEED_FULL 1U +#define EP_SPEED_HIGH 2U +/** + * @} + */ + +/** @defgroup USB_LL_EP_Type USB Low Layer EP Type + * @{ + */ +#define EP_TYPE_CTRL 0U +#define EP_TYPE_ISOC 1U +#define EP_TYPE_BULK 2U +#define EP_TYPE_INTR 3U +#define EP_TYPE_MSK 3U +/** + * @} + */ + +/** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines + * @{ + */ +#define STS_GOUT_NAK 1U +#define STS_DATA_UPDT 2U +#define STS_XFER_COMP 3U +#define STS_SETUP_COMP 4U +#define STS_SETUP_UPDT 6U +/** + * @} + */ + +/** @defgroup USB_LL_HCFG_SPEED_Defines USB Low Layer HCFG Speed Defines + * @{ + */ +#define HCFG_30_60_MHZ 0U +#define HCFG_48_MHZ 1U +#define HCFG_6_MHZ 2U +/** + * @} + */ + +/** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines + * @{ + */ +#define HPRT0_PRTSPD_HIGH_SPEED 0U +#define HPRT0_PRTSPD_FULL_SPEED 1U +#define HPRT0_PRTSPD_LOW_SPEED 2U +/** + * @} + */ + +#define HCCHAR_CTRL 0U +#define HCCHAR_ISOC 1U +#define HCCHAR_BULK 2U +#define HCCHAR_INTR 3U + +#define HC_PID_DATA0 0U +#define HC_PID_DATA2 1U +#define HC_PID_DATA1 2U +#define HC_PID_SETUP 3U + +#define GRXSTS_PKTSTS_IN 2U +#define GRXSTS_PKTSTS_IN_XFER_COMP 3U +#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U +#define GRXSTS_PKTSTS_CH_HALTED 7U + +#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE) +#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE) + +#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE)) +#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBx_BASE + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) +#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) +#define USBx_DFIFO(i) *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE)) + +#define USBx_HOST ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE)) +#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE + USB_OTG_HOST_CHANNEL_BASE + ((i) * USB_OTG_HOST_CHANNEL_SIZE))) +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +#define EP_ADDR_MSK 0xFU +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup USB_LL_Exported_Macros USB Low Layer Exported Macros + * @{ + */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__)) +#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__)) + +#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__)) +#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__)) +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions + * @{ + */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); +HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); +HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed); +HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode); +HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed); +HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num); +HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma); +HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma); +HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, + uint8_t ch_ep_num, uint16_t len, uint8_t dma); + +void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len); +HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address); +HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup); +uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); +uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); +void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt); + +HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); +HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq); +HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state); +uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, + uint8_t epnum, uint8_t dev_address, uint8_t speed, + uint8_t ep_type, uint16_t mps); +HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, + USB_OTG_HCTypeDef *hc, uint8_t dma); + +uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num); +HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num); +HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx); +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32F4xx_LL_USB_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c new file mode 100644 index 0000000..6a7910d --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c @@ -0,0 +1,615 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal.c + * @author MCD Application Team + * @brief HAL module driver. + * This is the common part of the HAL initialization + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The common HAL driver contains a set of generic and common APIs that can be + used by the PPP peripheral drivers and the user to start using the HAL. + [..] + The HAL contains two APIs' categories: + (+) Common HAL APIs + (+) Services HAL APIs + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup HAL HAL + * @brief HAL module driver. + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup HAL_Private_Constants + * @{ + */ +/** + * @brief STM32F4xx HAL Driver version number V1.7.10 + */ +#define __STM32F4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ +#define __STM32F4xx_HAL_VERSION_SUB1 (0x07U) /*!< [23:16] sub1 version */ +#define __STM32F4xx_HAL_VERSION_SUB2 (0x0AU) /*!< [15:8] sub2 version */ +#define __STM32F4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ +#define __STM32F4xx_HAL_VERSION ((__STM32F4xx_HAL_VERSION_MAIN << 24U)\ + |(__STM32F4xx_HAL_VERSION_SUB1 << 16U)\ + |(__STM32F4xx_HAL_VERSION_SUB2 << 8U )\ + |(__STM32F4xx_HAL_VERSION_RC)) + +#define IDCODE_DEVID_MASK 0x00000FFFU + +/* ------------ RCC registers bit address in the alias region ----------- */ +#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE) +/* --- MEMRMP Register ---*/ +/* Alias word address of UFB_MODE bit */ +#define MEMRMP_OFFSET SYSCFG_OFFSET +#define UFB_MODE_BIT_NUMBER SYSCFG_MEMRMP_UFB_MODE_Pos +#define UFB_MODE_BB (uint32_t)(PERIPH_BB_BASE + (MEMRMP_OFFSET * 32U) + (UFB_MODE_BIT_NUMBER * 4U)) + +/* --- CMPCR Register ---*/ +/* Alias word address of CMP_PD bit */ +#define CMPCR_OFFSET (SYSCFG_OFFSET + 0x20U) +#define CMP_PD_BIT_NUMBER SYSCFG_CMPCR_CMP_PD_Pos +#define CMPCR_CMP_PD_BB (uint32_t)(PERIPH_BB_BASE + (CMPCR_OFFSET * 32U) + (CMP_PD_BIT_NUMBER * 4U)) + +/* --- MCHDLYCR Register ---*/ +/* Alias word address of BSCKSEL bit */ +#define MCHDLYCR_OFFSET (SYSCFG_OFFSET + 0x30U) +#define BSCKSEL_BIT_NUMBER SYSCFG_MCHDLYCR_BSCKSEL_Pos +#define MCHDLYCR_BSCKSEL_BB (uint32_t)(PERIPH_BB_BASE + (MCHDLYCR_OFFSET * 32U) + (BSCKSEL_BIT_NUMBER * 4U)) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup HAL_Private_Variables + * @{ + */ +__IO uint32_t uwTick; +uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ +HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ +/** + * @} + */ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Functions HAL Exported Functions + * @{ + */ + +/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initializes the Flash interface the NVIC allocation and initial clock + configuration. It initializes the systick also when timeout is needed + and the backup domain when enabled. + (+) De-Initializes common part of the HAL. + (+) Configure the time base source to have 1ms time base with a dedicated + Tick interrupt priority. + (++) SysTick timer is used by default as source of time base, but user + can eventually implement his proper time base source (a general purpose + timer for example or other time source), keeping in mind that Time base + duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and + handled in milliseconds basis. + (++) Time base configuration function (HAL_InitTick ()) is called automatically + at the beginning of the program after reset by HAL_Init() or at any time + when clock is configured, by HAL_RCC_ClockConfig(). + (++) Source of time base is configured to generate interrupts at regular + time intervals. Care must be taken if HAL_Delay() is called from a + peripheral ISR process, the Tick interrupt line must have higher priority + (numerically lower) than the peripheral interrupt. Otherwise the caller + ISR process will be blocked. + (++) functions affecting time base configurations are declared as __weak + to make override possible in case of other implementations in user file. +@endverbatim + * @{ + */ + +/** + * @brief This function is used to initialize the HAL Library; it must be the first + * instruction to be executed in the main program (before to call any other + * HAL function), it performs the following: + * Configure the Flash prefetch, instruction and Data caches. + * Configures the SysTick to generate an interrupt each 1 millisecond, + * which is clocked by the HSI (at this stage, the clock is not yet + * configured and thus the system is running from the internal HSI at 16 MHz). + * Set NVIC Group Priority to 4. + * Calls the HAL_MspInit() callback function defined in user file + * "stm32f4xx_hal_msp.c" to do the global low level hardware initialization + * + * @note SysTick is used as time base for the HAL_Delay() function, the application + * need to ensure that the SysTick time base is always set to 1 millisecond + * to have correct HAL operation. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + /* Configure Flash prefetch, Instruction cache, Data cache */ +#if (INSTRUCTION_CACHE_ENABLE != 0U) + __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); +#endif /* INSTRUCTION_CACHE_ENABLE */ + +#if (DATA_CACHE_ENABLE != 0U) + __HAL_FLASH_DATA_CACHE_ENABLE(); +#endif /* DATA_CACHE_ENABLE */ + +#if (PREFETCH_ENABLE != 0U) + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); +#endif /* PREFETCH_ENABLE */ + + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + + /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ + HAL_InitTick(TICK_INT_PRIORITY); + + /* Init the low level hardware */ + HAL_MspInit(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief This function de-Initializes common part of the HAL and stops the systick. + * This function is optional. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DeInit(void) +{ + /* Reset of all peripherals */ + __HAL_RCC_APB1_FORCE_RESET(); + __HAL_RCC_APB1_RELEASE_RESET(); + + __HAL_RCC_APB2_FORCE_RESET(); + __HAL_RCC_APB2_RELEASE_RESET(); + + __HAL_RCC_AHB1_FORCE_RESET(); + __HAL_RCC_AHB1_RELEASE_RESET(); + + __HAL_RCC_AHB2_FORCE_RESET(); + __HAL_RCC_AHB2_RELEASE_RESET(); + + __HAL_RCC_AHB3_FORCE_RESET(); + __HAL_RCC_AHB3_RELEASE_RESET(); + + /* De-Init the low level hardware */ + HAL_MspDeInit(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initialize the MSP. + * @retval None + */ +__weak void HAL_MspInit(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the MSP. + * @retval None + */ +__weak void HAL_MspDeInit(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief This function configures the source of the time base. + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note This function is called automatically at the beginning of program after + * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals. + * Care must be taken if HAL_Delay() is called from a peripheral ISR process, + * The SysTick interrupt must have higher priority (numerically lower) + * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. + * The function is declared as __weak to be overwritten in case of other + * implementation in user file. + * @param TickPriority Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + /* Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) + { + return HAL_ERROR; + } + + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + uwTickPrio = TickPriority; + } + else + { + return HAL_ERROR; + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions + * @brief HAL Control functions + * +@verbatim + =============================================================================== + ##### HAL Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Provide a tick value in millisecond + (+) Provide a blocking delay in millisecond + (+) Suspend the time base source interrupt + (+) Resume the time base source interrupt + (+) Get the HAL API driver version + (+) Get the device identifier + (+) Get the device revision identifier + (+) Enable/Disable Debug module during SLEEP mode + (+) Enable/Disable Debug module during STOP mode + (+) Enable/Disable Debug module during STANDBY mode + +@endverbatim + * @{ + */ + +/** + * @brief This function is called to increment a global variable "uwTick" + * used as application time base. + * @note In the default implementation, this variable is incremented each 1ms + * in SysTick ISR. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + uwTick += uwTickFreq; +} + +/** + * @brief Provides a tick value in millisecond. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + return uwTick; +} + +/** + * @brief This function returns a tick priority. + * @retval tick priority + */ +uint32_t HAL_GetTickPrio(void) +{ + return uwTickPrio; +} + +/** + * @brief Set new tick Freq. + * @retval Status + */ +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) +{ + HAL_StatusTypeDef status = HAL_OK; + HAL_TickFreqTypeDef prevTickFreq; + + assert_param(IS_TICKFREQ(Freq)); + + if (uwTickFreq != Freq) + { + /* Back up uwTickFreq frequency */ + prevTickFreq = uwTickFreq; + + /* Update uwTickFreq global variable used by HAL_InitTick() */ + uwTickFreq = Freq; + + /* Apply the new tick Freq */ + status = HAL_InitTick(uwTickPrio); + + if (status != HAL_OK) + { + /* Restore previous tick frequency */ + uwTickFreq = prevTickFreq; + } + } + + return status; +} + +/** + * @brief Return tick frequency. + * @retval tick period in Hz + */ +HAL_TickFreqTypeDef HAL_GetTickFreq(void) +{ + return uwTickFreq; +} + +/** + * @brief This function provides minimum delay (in milliseconds) based + * on variable incremented. + * @note In the default implementation , SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals where uwTick + * is incremented. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void HAL_Delay(uint32_t Delay) +{ + uint32_t tickstart = HAL_GetTick(); + uint32_t wait = Delay; + + /* Add a freq to guarantee minimum wait */ + if (wait < HAL_MAX_DELAY) + { + wait += (uint32_t)(uwTickFreq); + } + + while((HAL_GetTick() - tickstart) < wait) + { + } +} + +/** + * @brief Suspend Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() + * is called, the SysTick interrupt will be disabled and so Tick increment + * is suspended. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_SuspendTick(void) +{ + /* Disable SysTick Interrupt */ + SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; +} + +/** + * @brief Resume Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() + * is called, the SysTick interrupt will be enabled and so Tick increment + * is resumed. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_ResumeTick(void) +{ + /* Enable SysTick Interrupt */ + SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; +} + +/** + * @brief Returns the HAL revision + * @retval version : 0xXYZR (8bits for each decimal, R for RC) + */ +uint32_t HAL_GetHalVersion(void) +{ + return __STM32F4xx_HAL_VERSION; +} + +/** + * @brief Returns the device revision identifier. + * @retval Device revision identifier + */ +uint32_t HAL_GetREVID(void) +{ + return((DBGMCU->IDCODE) >> 16U); +} + +/** + * @brief Returns the device identifier. + * @retval Device identifier + */ +uint32_t HAL_GetDEVID(void) +{ + return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); +} + +/** + * @brief Enable the Debug Module during SLEEP mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGSleepMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Disable the Debug Module during SLEEP mode + * @retval None + */ +void HAL_DBGMCU_DisableDBGSleepMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Enable the Debug Module during STOP mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Disable the Debug Module during STOP mode + * @retval None + */ +void HAL_DBGMCU_DisableDBGStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Enable the Debug Module during STANDBY mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Disable the Debug Module during STANDBY mode + * @retval None + */ +void HAL_DBGMCU_DisableDBGStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Enables the I/O Compensation Cell. + * @note The I/O compensation cell can be used only when the device supply + * voltage ranges from 2.4 to 3.6 V. + * @retval None + */ +void HAL_EnableCompensationCell(void) +{ + *(__IO uint32_t *)CMPCR_CMP_PD_BB = (uint32_t)ENABLE; +} + +/** + * @brief Power-down the I/O Compensation Cell. + * @note The I/O compensation cell can be used only when the device supply + * voltage ranges from 2.4 to 3.6 V. + * @retval None + */ +void HAL_DisableCompensationCell(void) +{ + *(__IO uint32_t *)CMPCR_CMP_PD_BB = (uint32_t)DISABLE; +} + +/** + * @brief Returns first word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw0(void) +{ + return (READ_REG(*((uint32_t *)UID_BASE))); +} + +/** + * @brief Returns second word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw1(void) +{ + return (READ_REG(*((uint32_t *)(UID_BASE + 4U)))); +} + +/** + * @brief Returns third word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw2(void) +{ + return (READ_REG(*((uint32_t *)(UID_BASE + 8U)))); +} + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) +/** + * @brief Enables the Internal FLASH Bank Swapping. + * + * @note This function can be used only for STM32F42xxx/43xxx/469xx/479xx devices. + * + * @note Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000) + * and Flash Bank1 mapped at 0x08100000 (and aliased at 0x00100000) + * + * @retval None + */ +void HAL_EnableMemorySwappingBank(void) +{ + *(__IO uint32_t *)UFB_MODE_BB = (uint32_t)ENABLE; +} + +/** + * @brief Disables the Internal FLASH Bank Swapping. + * + * @note This function can be used only for STM32F42xxx/43xxx/469xx/479xx devices. + * + * @note The default state : Flash Bank1 mapped at 0x08000000 (and aliased @0x00000000) + * and Flash Bank2 mapped at 0x08100000 (and aliased at 0x00100000) + * + * @retval None + */ +void HAL_DisableMemorySwappingBank(void) +{ + *(__IO uint32_t *)UFB_MODE_BB = (uint32_t)DISABLE; +} +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c new file mode 100644 index 0000000..2efb986 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c @@ -0,0 +1,505 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_cortex.c + * @author MCD Application Team + * @brief CORTEX HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the CORTEX: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + + [..] + *** How to configure Interrupts using CORTEX HAL driver *** + =========================================================== + [..] + This section provides functions allowing to configure the NVIC interrupts (IRQ). + The Cortex-M4 exceptions are managed by CMSIS functions. + + (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() + function according to the following table. + (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). + (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ(). + (#) please refer to programming manual for details in how to configure priority. + + -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible. + The pending IRQ priority will be managed only by the sub priority. + + -@- IRQ priority order (sorted by highest to lowest priority): + (+@) Lowest preemption priority + (+@) Lowest sub priority + (+@) Lowest hardware priority (IRQ number) + + [..] + *** How to configure Systick using CORTEX HAL driver *** + ======================================================== + [..] + Setup SysTick Timer for time base. + + (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which + is a CMSIS function that: + (++) Configures the SysTick Reload register with value passed as function parameter. + (++) Configures the SysTick IRQ priority to the lowest value 0x0F. + (++) Resets the SysTick Counter register. + (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). + (++) Enables the SysTick Interrupt. + (++) Starts the SysTick Counter. + + (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro + __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the + HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined + inside the stm32f4xx_hal_cortex.h file. + + (+) You can change the SysTick IRQ priority by calling the + HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function + call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. + + (+) To adjust the SysTick time base, use the following formula: + + Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) + (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function + (++) Reload Value should not exceed 0xFFFFFF + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup CORTEX CORTEX + * @brief CORTEX HAL module driver + * @{ + */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions + * @{ + */ + + +/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] + This section provides the CORTEX HAL driver functions allowing to configure Interrupts + Systick functionalities + +@endverbatim + * @{ + */ + + +/** + * @brief Sets the priority grouping field (preemption priority and subpriority) + * using the required unlock sequence. + * @param PriorityGroup The priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority + * 4 bits for subpriority + * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority + * 3 bits for subpriority + * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority + * 2 bits for subpriority + * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority + * 1 bits for subpriority + * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority + * 0 bits for subpriority + * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + NVIC_SetPriorityGrouping(PriorityGroup); +} + +/** + * @brief Sets the priority of an interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) + * @param PreemptPriority The preemption priority for the IRQn channel. + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority + * @param SubPriority the subpriority level for the IRQ channel. + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t prioritygroup = 0x00U; + + /* Check the parameters */ + assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + + prioritygroup = NVIC_GetPriorityGrouping(); + + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); +} + +/** + * @brief Enables a device specific interrupt in the NVIC interrupt controller. + * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() + * function should be called before. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); +} + +/** + * @brief Disables a device specific interrupt in the NVIC interrupt controller. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) + * @retval None + */ +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Disable interrupt */ + NVIC_DisableIRQ(IRQn); +} + +/** + * @brief Initiates a system reset request to reset the MCU. + * @retval None + */ +void HAL_NVIC_SystemReset(void) +{ + /* System Reset */ + NVIC_SystemReset(); +} + +/** + * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. + * Counter is in free running mode to generate periodic interrupts. + * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + return SysTick_Config(TicksNumb); +} +/** + * @} + */ + +/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions + * @brief Cortex control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the CORTEX + (NVIC, SYSTICK, MPU) functionalities. + + +@endverbatim + * @{ + */ + +#if (__MPU_PRESENT == 1U) +/** + * @brief Disables the MPU + * @retval None + */ +void HAL_MPU_Disable(void) +{ + /* Make sure outstanding transfers are done */ + __DMB(); + + /* Disable fault exceptions */ + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; + + /* Disable the MPU and clear the control register*/ + MPU->CTRL = 0U; +} + +/** + * @brief Enable the MPU. + * @param MPU_Control Specifies the control mode of the MPU during hard fault, + * NMI, FAULTMASK and privileged access to the default memory + * This parameter can be one of the following values: + * @arg MPU_HFNMI_PRIVDEF_NONE + * @arg MPU_HARDFAULT_NMI + * @arg MPU_PRIVILEGED_DEFAULT + * @arg MPU_HFNMI_PRIVDEF + * @retval None + */ +void HAL_MPU_Enable(uint32_t MPU_Control) +{ + /* Enable the MPU */ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; + + /* Enable fault exceptions */ + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; + + /* Ensure MPU setting take effects */ + __DSB(); + __ISB(); +} + +/** + * @brief Initializes and configures the Region and the memory to be protected. + * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains + * the initialization and configuration information. + * @retval None + */ +void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); + assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); + + /* Set the Region number */ + MPU->RNR = MPU_Init->Number; + + if ((MPU_Init->Enable) != RESET) + { + /* Check the parameters */ + assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); + assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); + assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); + assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); + assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); + assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); + assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); + assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); + + MPU->RBAR = MPU_Init->BaseAddress; + MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | + ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | + ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | + ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | + ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | + ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | + ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | + ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | + ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); + } + else + { + MPU->RBAR = 0x00U; + MPU->RASR = 0x00U; + } +} +#endif /* __MPU_PRESENT */ + +/** + * @brief Gets the priority grouping field from the NVIC Interrupt Controller. + * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) + */ +uint32_t HAL_NVIC_GetPriorityGrouping(void) +{ + /* Get the PRIGROUP[10:8] field value */ + return NVIC_GetPriorityGrouping(); +} + +/** + * @brief Gets the priority of an interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) + * @param PriorityGroup the priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority + * 4 bits for subpriority + * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority + * 3 bits for subpriority + * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority + * 2 bits for subpriority + * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority + * 1 bits for subpriority + * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority + * 0 bits for subpriority + * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0). + * @param pSubPriority Pointer on the Subpriority value (starting from 0). + * @retval None + */ +void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + /* Get priority for Cortex-M system or device specific interrupts */ + NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); +} + +/** + * @brief Sets Pending bit of an external interrupt. + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) + * @retval None + */ +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Set interrupt pending */ + NVIC_SetPendingIRQ(IRQn); +} + +/** + * @brief Gets Pending Interrupt (reads the pending register in the NVIC + * and returns the pending bit for the specified interrupt). + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) + * @retval status: - 0 Interrupt status is not pending. + * - 1 Interrupt status is pending. + */ +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Return 1 if pending else 0 */ + return NVIC_GetPendingIRQ(IRQn); +} + +/** + * @brief Clears the pending bit of an external interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) + * @retval None + */ +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Clear pending interrupt */ + NVIC_ClearPendingIRQ(IRQn); +} + +/** + * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit). + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) + * @retval status: - 0 Interrupt status is not pending. + * - 1 Interrupt status is pending. + */ +uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Return 1 if active else 0 */ + return NVIC_GetActive(IRQn); +} + +/** + * @brief Configures the SysTick clock source. + * @param CLKSource specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. + * @retval None + */ +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); + if (CLKSource == SYSTICK_CLKSOURCE_HCLK) + { + SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; + } + else + { + SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; + } +} + +/** + * @brief This function handles SYSTICK interrupt request. + * @retval None + */ +void HAL_SYSTICK_IRQHandler(void) +{ + HAL_SYSTICK_Callback(); +} + +/** + * @brief SYSTICK callback. + * @retval None + */ +__weak void HAL_SYSTICK_Callback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SYSTICK_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_CORTEX_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c new file mode 100644 index 0000000..69d848f --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c @@ -0,0 +1,1305 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_dma.c + * @author MCD Application Team + * @brief DMA HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the Direct Memory Access (DMA) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and errors functions + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable and configure the peripheral to be connected to the DMA Stream + (except for internal SRAM/FLASH memories: no initialization is + necessary) please refer to Reference manual for connection between peripherals + and DMA requests. + + (#) For a given Stream, program the required configuration through the following parameters: + Transfer Direction, Source and Destination data formats, + Circular, Normal or peripheral flow control mode, Stream Priority level, + Source and Destination Increment mode, FIFO mode and its Threshold (if needed), + Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function. + + -@- Prior to HAL_DMA_Init() the clock must be enabled for DMA through the following macros: + __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE(). + + *** Polling mode IO operation *** + ================================= + [..] + (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source + address and destination address and the Length of data to be transferred. + (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this + case a fixed Timeout can be configured by User depending from his application. + (+) Use HAL_DMA_Abort() function to abort the current transfer. + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() + (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() + (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of + Source address and destination address and the Length of data to be transferred. In this + case the DMA interrupt is configured + (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine + (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can + add his own function by customization of function pointer XferCpltCallback and + XferErrorCallback (i.e a member of DMA handle structure). + [..] + (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error + detection. + + (#) Use HAL_DMA_Abort_IT() function to abort the current transfer + + -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. + + -@- The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is + possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set + Half-Word data size for the peripheral to access its data register and set Word data size + for the Memory to gain in access time. Each two half words will be packed and written in + a single access to a Word in the Memory). + + -@- When FIFO is disabled, it is not allowed to configure different Data Sizes for Source + and Destination. In this case the Peripheral Data Size will be applied to both Source + and Destination. + + *** DMA HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in DMA HAL driver. + + (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream. + (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream. + (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not. + + [..] + (@) You can refer to the DMA HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup DMA DMA + * @brief DMA HAL module driver + * @{ + */ + +#ifdef HAL_DMA_MODULE_ENABLED + +/* Private types -------------------------------------------------------------*/ +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register */ + __IO uint32_t Reserved0; + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register */ +} DMA_Base_Registers; + +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup DMA_Private_Constants + * @{ + */ + #define HAL_TIMEOUT_DMA_ABORT 5U /* 5 ms */ +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup DMA_Private_Functions + * @{ + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma); + +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @addtogroup DMA_Exported_Functions + * @{ + */ + +/** @addtogroup DMA_Exported_Functions_Group1 + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to initialize the DMA Stream source + and destination addresses, incrementation and data sizes, transfer direction, + circular/normal mode selection, memory-to-memory mode selection and Stream priority value. + [..] + The HAL_DMA_Init() function follows the DMA configuration procedures as described in + reference manual. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the DMA according to the specified + * parameters in the DMA_InitTypeDef and create the associated handle. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) +{ + uint32_t tmp = 0U; + uint32_t tickstart = HAL_GetTick(); + DMA_Base_Registers *regs; + + /* Check the DMA peripheral state */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_CHANNEL(hdma->Init.Channel)); + assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); + assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); + assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); + assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); + assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); + assert_param(IS_DMA_MODE(hdma->Init.Mode)); + assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); + assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode)); + /* Check the memory burst, peripheral burst and FIFO threshold parameters only + when FIFO mode is enabled */ + if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE) + { + assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold)); + assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); + assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); + } + + /* Allocate lock resource */ + __HAL_UNLOCK(hdma); + + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Disable the peripheral */ + __HAL_DMA_DISABLE(hdma); + + /* Check if the DMA Stream is effectively disabled */ + while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_TIMEOUT; + + return HAL_TIMEOUT; + } + } + + /* Get the CR register value */ + tmp = hdma->Instance->CR; + + /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */ + tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ + DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ + DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ + DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM)); + + /* Prepare the DMA Stream configuration */ + tmp |= hdma->Init.Channel | hdma->Init.Direction | + hdma->Init.PeriphInc | hdma->Init.MemInc | + hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + hdma->Init.Mode | hdma->Init.Priority; + + /* the Memory burst and peripheral burst are not used when the FIFO is disabled */ + if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) + { + /* Get memory burst and peripheral burst */ + tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; + } + + /* Write to DMA Stream CR register */ + hdma->Instance->CR = tmp; + + /* Get the FCR register value */ + tmp = hdma->Instance->FCR; + + /* Clear Direct mode and FIFO threshold bits */ + tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); + + /* Prepare the DMA Stream FIFO configuration */ + tmp |= hdma->Init.FIFOMode; + + /* The FIFO threshold is not used when the FIFO mode is disabled */ + if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) + { + /* Get the FIFO threshold */ + tmp |= hdma->Init.FIFOThreshold; + + /* Check compatibility between FIFO threshold level and size of the memory burst */ + /* for INCR4, INCR8, INCR16 bursts */ + if (hdma->Init.MemBurst != DMA_MBURST_SINGLE) + { + if (DMA_CheckFifoParam(hdma) != HAL_OK) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_PARAM; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + return HAL_ERROR; + } + } + } + + /* Write to DMA Stream FCR */ + hdma->Instance->FCR = tmp; + + /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate + DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ + regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); + + /* Clear all interrupt flags */ + regs->IFCR = 0x3FU << hdma->StreamIndex; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Initialize the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the DMA peripheral + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) +{ + DMA_Base_Registers *regs; + + /* Check the DMA peripheral state */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the DMA peripheral state */ + if(hdma->State == HAL_DMA_STATE_BUSY) + { + /* Return error status */ + return HAL_BUSY; + } + + /* Check the parameters */ + assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance)); + + /* Disable the selected DMA Streamx */ + __HAL_DMA_DISABLE(hdma); + + /* Reset DMA Streamx control register */ + hdma->Instance->CR = 0U; + + /* Reset DMA Streamx number of data to transfer register */ + hdma->Instance->NDTR = 0U; + + /* Reset DMA Streamx peripheral address register */ + hdma->Instance->PAR = 0U; + + /* Reset DMA Streamx memory 0 address register */ + hdma->Instance->M0AR = 0U; + + /* Reset DMA Streamx memory 1 address register */ + hdma->Instance->M1AR = 0U; + + /* Reset DMA Streamx FIFO control register */ + hdma->Instance->FCR = 0x00000021U; + + /* Get DMA steam Base Address */ + regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); + + /* Clean all callbacks */ + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferM1CpltCallback = NULL; + hdma->XferM1HalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + + /* Clear all interrupt flags at correct offset within the register */ + regs->IFCR = 0x3FU << hdma->StreamIndex; + + /* Reset the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Reset the DMA state */ + hdma->State = HAL_DMA_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group2 + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the source, destination address and data length and Start DMA transfer + (+) Configure the source, destination address and data length and + Start DMA transfer with interrupt + (+) Abort DMA transfer + (+) Poll for transfer complete + (+) Handle DMA interrupt request + +@endverbatim + * @{ + */ + +/** + * @brief Starts the DMA Transfer. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Configure the source, destination address and the data length */ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + /* Return error status */ + status = HAL_BUSY; + } + return status; +} + +/** + * @brief Start the DMA Transfer with interrupt enabled. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* calculate DMA base and stream number */ + DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Configure the source, destination address and the data length */ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Clear all interrupt flags at correct offset within the register */ + regs->IFCR = 0x3FU << hdma->StreamIndex; + + /* Enable Common interrupts*/ + hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME; + + if(hdma->XferHalfCpltCallback != NULL) + { + hdma->Instance->CR |= DMA_IT_HT; + } + + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + /* Return error status */ + status = HAL_BUSY; + } + + return status; +} + +/** + * @brief Aborts the DMA Transfer. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * + * @note After disabling a DMA Stream, a check for wait until the DMA Stream is + * effectively disabled is added. If a Stream is disabled + * while a data transfer is ongoing, the current data will be transferred + * and the Stream will be effectively disabled only after the transfer of + * this single data is finished. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) +{ + /* calculate DMA base and stream number */ + DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; + + uint32_t tickstart = HAL_GetTick(); + + if(hdma->State != HAL_DMA_STATE_BUSY) + { + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + else + { + /* Disable all the transfer interrupts */ + hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); + hdma->Instance->FCR &= ~(DMA_IT_FE); + + if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) + { + hdma->Instance->CR &= ~(DMA_IT_HT); + } + + /* Disable the stream */ + __HAL_DMA_DISABLE(hdma); + + /* Check if the DMA Stream is effectively disabled */ + while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_TIMEOUT; + + return HAL_TIMEOUT; + } + } + + /* Clear all interrupt flags at correct offset within the register */ + regs->IFCR = 0x3FU << hdma->StreamIndex; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Change the DMA state*/ + hdma->State = HAL_DMA_STATE_READY; + } + return HAL_OK; +} + +/** + * @brief Aborts the DMA Transfer in Interrupt mode. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) +{ + if(hdma->State != HAL_DMA_STATE_BUSY) + { + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + return HAL_ERROR; + } + else + { + /* Set Abort State */ + hdma->State = HAL_DMA_STATE_ABORT; + + /* Disable the stream */ + __HAL_DMA_DISABLE(hdma); + } + + return HAL_OK; +} + +/** + * @brief Polling for transfer complete. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param CompleteLevel Specifies the DMA level complete. + * @note The polling mode is kept in this version for legacy. it is recommanded to use the IT model instead. + * This model could be used for debug purpose. + * @note The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode). + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t mask_cpltlevel; + uint32_t tickstart = HAL_GetTick(); + uint32_t tmpisr; + + /* calculate DMA base and stream number */ + DMA_Base_Registers *regs; + + if(HAL_DMA_STATE_BUSY != hdma->State) + { + /* No transfer ongoing */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + __HAL_UNLOCK(hdma); + return HAL_ERROR; + } + + /* Polling mode not supported in circular mode and double buffering mode */ + if ((hdma->Instance->CR & DMA_SxCR_CIRC) != RESET) + { + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + return HAL_ERROR; + } + + /* Get the level transfer complete flag */ + if(CompleteLevel == HAL_DMA_FULL_TRANSFER) + { + /* Transfer Complete flag */ + mask_cpltlevel = DMA_FLAG_TCIF0_4 << hdma->StreamIndex; + } + else + { + /* Half Transfer Complete flag */ + mask_cpltlevel = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; + } + + regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; + tmpisr = regs->ISR; + + while(((tmpisr & mask_cpltlevel) == RESET) && ((hdma->ErrorCode & HAL_DMA_ERROR_TE) == RESET)) + { + /* Check for the Timeout (Not applicable in circular mode)*/ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + return HAL_TIMEOUT; + } + } + + /* Get the ISR register value */ + tmpisr = regs->ISR; + + if((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET) + { + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_TE; + + /* Clear the transfer error flag */ + regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex; + } + + if((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET) + { + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_FE; + + /* Clear the FIFO error flag */ + regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex; + } + + if((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET) + { + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_DME; + + /* Clear the Direct Mode error flag */ + regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex; + } + } + + if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) + { + if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET) + { + HAL_DMA_Abort(hdma); + + /* Clear the half transfer and transfer complete flags */ + regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Change the DMA state */ + hdma->State= HAL_DMA_STATE_READY; + + return HAL_ERROR; + } + } + + /* Get the level transfer complete flag */ + if(CompleteLevel == HAL_DMA_FULL_TRANSFER) + { + /* Clear the half transfer and transfer complete flags */ + regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + hdma->State = HAL_DMA_STATE_READY; + } + else + { + /* Clear the half transfer and transfer complete flags */ + regs->IFCR = (DMA_FLAG_HTIF0_4) << hdma->StreamIndex; + } + + return status; +} + +/** + * @brief Handles DMA interrupt request. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval None + */ +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) +{ + uint32_t tmpisr; + __IO uint32_t count = 0U; + uint32_t timeout = SystemCoreClock / 9600U; + + /* calculate DMA base and stream number */ + DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; + + tmpisr = regs->ISR; + + /* Transfer Error Interrupt management ***************************************/ + if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET) + { + /* Disable the transfer error interrupt */ + hdma->Instance->CR &= ~(DMA_IT_TE); + + /* Clear the transfer error flag */ + regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_TE; + } + } + /* FIFO Error Interrupt management ******************************************/ + if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET) + { + /* Clear the FIFO error flag */ + regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_FE; + } + } + /* Direct Mode Error Interrupt management ***********************************/ + if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET) + { + /* Clear the direct mode error flag */ + regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_DME; + } + } + /* Half Transfer Complete Interrupt management ******************************/ + if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET) + { + /* Clear the half transfer complete flag */ + regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; + + /* Multi_Buffering mode enabled */ + if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) + { + /* Current memory buffer used is Memory 0 */ + if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) + { + if(hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + } + } + /* Current memory buffer used is Memory 1 */ + else + { + if(hdma->XferM1HalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferM1HalfCpltCallback(hdma); + } + } + } + else + { + /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ + if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) + { + /* Disable the half transfer interrupt */ + hdma->Instance->CR &= ~(DMA_IT_HT); + } + + if(hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + } + } + } + } + /* Transfer Complete Interrupt management ***********************************/ + if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET) + { + /* Clear the transfer complete flag */ + regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex; + + if(HAL_DMA_STATE_ABORT == hdma->State) + { + /* Disable all the transfer interrupts */ + hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); + hdma->Instance->FCR &= ~(DMA_IT_FE); + + if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) + { + hdma->Instance->CR &= ~(DMA_IT_HT); + } + + /* Clear all interrupt flags at correct offset within the register */ + regs->IFCR = 0x3FU << hdma->StreamIndex; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + if(hdma->XferAbortCallback != NULL) + { + hdma->XferAbortCallback(hdma); + } + return; + } + + if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) + { + /* Current memory buffer used is Memory 0 */ + if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) + { + if(hdma->XferM1CpltCallback != NULL) + { + /* Transfer complete Callback for memory1 */ + hdma->XferM1CpltCallback(hdma); + } + } + /* Current memory buffer used is Memory 1 */ + else + { + if(hdma->XferCpltCallback != NULL) + { + /* Transfer complete Callback for memory0 */ + hdma->XferCpltCallback(hdma); + } + } + } + /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */ + else + { + if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) + { + /* Disable the transfer complete interrupt */ + hdma->Instance->CR &= ~(DMA_IT_TC); + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + } + + if(hdma->XferCpltCallback != NULL) + { + /* Transfer complete callback */ + hdma->XferCpltCallback(hdma); + } + } + } + } + + /* manage error case */ + if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) + { + if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET) + { + hdma->State = HAL_DMA_STATE_ABORT; + + /* Disable the stream */ + __HAL_DMA_DISABLE(hdma); + + do + { + if (++count > timeout) + { + break; + } + } + while((hdma->Instance->CR & DMA_SxCR_EN) != RESET); + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + } + + if(hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } +} + +/** + * @brief Register callbacks + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param CallbackID User Callback identifer + * a DMA_HandleTypeDef structure as parameter. + * @param pCallback pointer to private callbacsk function which has pointer to + * a DMA_HandleTypeDef structure as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)) +{ + + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_M1CPLT_CB_ID: + hdma->XferM1CpltCallback = pCallback; + break; + + case HAL_DMA_XFER_M1HALFCPLT_CB_ID: + hdma->XferM1HalfCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = pCallback; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = pCallback; + break; + + default: + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return status; +} + +/** + * @brief UnRegister callbacks + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param CallbackID User Callback identifer + * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = NULL; + break; + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = NULL; + break; + + case HAL_DMA_XFER_M1CPLT_CB_ID: + hdma->XferM1CpltCallback = NULL; + break; + + case HAL_DMA_XFER_M1HALFCPLT_CB_ID: + hdma->XferM1HalfCpltCallback = NULL; + break; + + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = NULL; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = NULL; + break; + + case HAL_DMA_XFER_ALL_CB_ID: + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferM1CpltCallback = NULL; + hdma->XferM1HalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + break; + + default: + status = HAL_ERROR; + break; + } + } + else + { + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return status; +} + +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group3 + * +@verbatim + =============================================================================== + ##### State and Errors functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Check the DMA state + (+) Get error code + +@endverbatim + * @{ + */ + +/** + * @brief Returns the DMA state. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL state + */ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) +{ + return hdma->State; +} + +/** + * @brief Return the DMA error code + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval DMA Error Code + */ +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) +{ + return hdma->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DMA_Private_Functions + * @{ + */ + +/** + * @brief Sets the DMA Transfer parameter. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + /* Clear DBM bit */ + hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM); + + /* Configure DMA Stream data length */ + hdma->Instance->NDTR = DataLength; + + /* Memory to Peripheral */ + if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + /* Configure DMA Stream destination address */ + hdma->Instance->PAR = DstAddress; + + /* Configure DMA Stream source address */ + hdma->Instance->M0AR = SrcAddress; + } + /* Peripheral to Memory */ + else + { + /* Configure DMA Stream source address */ + hdma->Instance->PAR = SrcAddress; + + /* Configure DMA Stream destination address */ + hdma->Instance->M0AR = DstAddress; + } +} + +/** + * @brief Returns the DMA Stream base address depending on stream number + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval Stream base address + */ +static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) +{ + uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U; + + /* lookup table for necessary bitshift of flags within status registers */ + static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U}; + hdma->StreamIndex = flagBitshiftOffset[stream_number]; + + if (stream_number > 3U) + { + /* return pointer to HISR and HIFCR */ + hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U); + } + else + { + /* return pointer to LISR and LIFCR */ + hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)); + } + + return hdma->StreamBaseAddress; +} + +/** + * @brief Check compatibility between FIFO threshold level and size of the memory burst + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmp = hdma->Init.FIFOThreshold; + + /* Memory Data size equal to Byte */ + if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE) + { + switch (tmp) + { + case DMA_FIFO_THRESHOLD_1QUARTERFULL: + case DMA_FIFO_THRESHOLD_3QUARTERSFULL: + if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) + { + status = HAL_ERROR; + } + break; + case DMA_FIFO_THRESHOLD_HALFFULL: + if (hdma->Init.MemBurst == DMA_MBURST_INC16) + { + status = HAL_ERROR; + } + break; + case DMA_FIFO_THRESHOLD_FULL: + break; + default: + break; + } + } + + /* Memory Data size equal to Half-Word */ + else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) + { + switch (tmp) + { + case DMA_FIFO_THRESHOLD_1QUARTERFULL: + case DMA_FIFO_THRESHOLD_3QUARTERSFULL: + status = HAL_ERROR; + break; + case DMA_FIFO_THRESHOLD_HALFFULL: + if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) + { + status = HAL_ERROR; + } + break; + case DMA_FIFO_THRESHOLD_FULL: + if (hdma->Init.MemBurst == DMA_MBURST_INC16) + { + status = HAL_ERROR; + } + break; + default: + break; + } + } + + /* Memory Data size equal to Word */ + else + { + switch (tmp) + { + case DMA_FIFO_THRESHOLD_1QUARTERFULL: + case DMA_FIFO_THRESHOLD_HALFFULL: + case DMA_FIFO_THRESHOLD_3QUARTERSFULL: + status = HAL_ERROR; + break; + case DMA_FIFO_THRESHOLD_FULL: + if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) + { + status = HAL_ERROR; + } + break; + default: + break; + } + } + + return status; +} + +/** + * @} + */ + +#endif /* HAL_DMA_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c new file mode 100644 index 0000000..6e07376 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c @@ -0,0 +1,315 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_dma_ex.c + * @author MCD Application Team + * @brief DMA Extension HAL module driver + * This file provides firmware functions to manage the following + * functionalities of the DMA Extension peripheral: + * + Extended features functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The DMA Extension HAL driver can be used as follows: + (#) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function + for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode. + + -@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed. + -@- When Multi (Double) Buffer mode is enabled the, transfer is circular by default. + -@- In Multi (Double) buffer mode, it is possible to update the base address for + the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup DMAEx DMAEx + * @brief DMA Extended HAL module driver + * @{ + */ + +#ifdef HAL_DMA_MODULE_ENABLED + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private Constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup DMAEx_Private_Functions + * @{ + */ +static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @addtogroup DMAEx_Exported_Functions + * @{ + */ + + +/** @addtogroup DMAEx_Exported_Functions_Group1 + * +@verbatim + =============================================================================== + ##### Extended features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the source, destination address and data length and + Start MultiBuffer DMA transfer + (+) Configure the source, destination address and data length and + Start MultiBuffer DMA transfer with interrupt + (+) Change on the fly the memory0 or memory1 address. + +@endverbatim + * @{ + */ + + +/** + * @brief Starts the multi_buffer DMA Transfer. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Memory-to-memory transfer not supported in double buffering mode */ + if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) + { + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + status = HAL_ERROR; + } + else + { + /* Process Locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Enable the double buffer mode */ + hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM; + + /* Configure DMA Stream destination address */ + hdma->Instance->M1AR = SecondMemAddress; + + /* Configure the source, destination address and the data length */ + DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Enable the peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Return error status */ + status = HAL_BUSY; + } + } + return status; +} + +/** + * @brief Starts the multi_buffer DMA Transfer with interrupt enabled. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Memory-to-memory transfer not supported in double buffering mode */ + if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) + { + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + return HAL_ERROR; + } + + /* Check callback functions */ + if ((NULL == hdma->XferCpltCallback) || (NULL == hdma->XferM1CpltCallback) || (NULL == hdma->XferErrorCallback)) + { + hdma->ErrorCode = HAL_DMA_ERROR_PARAM; + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Enable the Double buffer mode */ + hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM; + + /* Configure DMA Stream destination address */ + hdma->Instance->M1AR = SecondMemAddress; + + /* Configure the source, destination address and the data length */ + DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Clear all flags */ + __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); + __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + + /* Enable Common interrupts*/ + hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME; + hdma->Instance->FCR |= DMA_IT_FE; + + if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) + { + hdma->Instance->CR |= DMA_IT_HT; + } + + /* Enable the peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + /* Return error status */ + status = HAL_BUSY; + } + return status; +} + +/** + * @brief Change the memory0 or memory1 address on the fly. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param Address The new address + * @param memory the memory to be changed, This parameter can be one of + * the following values: + * MEMORY0 / + * MEMORY1 + * @note The MEMORY0 address can be changed only when the current transfer use + * MEMORY1 and the MEMORY1 address can be changed only when the current + * transfer use MEMORY0. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory) +{ + if(memory == MEMORY0) + { + /* change the memory0 address */ + hdma->Instance->M0AR = Address; + } + else + { + /* change the memory1 address */ + hdma->Instance->M1AR = Address; + } + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DMAEx_Private_Functions + * @{ + */ + +/** + * @brief Set the DMA Transfer parameter. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + /* Configure DMA Stream data length */ + hdma->Instance->NDTR = DataLength; + + /* Peripheral to Memory */ + if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + /* Configure DMA Stream destination address */ + hdma->Instance->PAR = DstAddress; + + /* Configure DMA Stream source address */ + hdma->Instance->M0AR = SrcAddress; + } + /* Memory to Peripheral */ + else + { + /* Configure DMA Stream source address */ + hdma->Instance->PAR = SrcAddress; + + /* Configure DMA Stream destination address */ + hdma->Instance->M0AR = DstAddress; + } +} + +/** + * @} + */ + +#endif /* HAL_DMA_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c new file mode 100644 index 0000000..7cf3e09 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c @@ -0,0 +1,559 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_exti.c + * @author MCD Application Team + * @brief EXTI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Extended Interrupts and events controller (EXTI) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + @verbatim + ============================================================================== + ##### EXTI Peripheral features ##### + ============================================================================== + [..] + (+) Each Exti line can be configured within this driver. + + (+) Exti line can be configured in 3 different modes + (++) Interrupt + (++) Event + (++) Both of them + + (+) Configurable Exti lines can be configured with 3 different triggers + (++) Rising + (++) Falling + (++) Both of them + + (+) When set in interrupt mode, configurable Exti lines have two different + interrupts pending registers which allow to distinguish which transition + occurs: + (++) Rising edge pending interrupt + (++) Falling + + (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can + be selected through multiplexer. + + ##### How to use this driver ##### + ============================================================================== + [..] + + (#) Configure the EXTI line using HAL_EXTI_SetConfigLine(). + (++) Choose the interrupt line number by setting "Line" member from + EXTI_ConfigTypeDef structure. + (++) Configure the interrupt and/or event mode using "Mode" member from + EXTI_ConfigTypeDef structure. + (++) For configurable lines, configure rising and/or falling trigger + "Trigger" member from EXTI_ConfigTypeDef structure. + (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel" + member from GPIO_InitTypeDef structure. + + (#) Get current Exti configuration of a dedicated line using + HAL_EXTI_GetConfigLine(). + (++) Provide exiting handle as parameter. + (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter. + + (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine(). + (++) Provide exiting handle as parameter. + + (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback(). + (++) Provide exiting handle as first parameter. + (++) Provide which callback will be registered using one value from + EXTI_CallbackIDTypeDef. + (++) Provide callback function pointer. + + (#) Get interrupt pending bit using HAL_EXTI_GetPending(). + + (#) Clear interrupt pending bit using HAL_EXTI_GetPending(). + + (#) Generate software interrupt using HAL_EXTI_GenerateSWI(). + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup EXTI + * @{ + */ +/** MISRA C:2012 deviation rule has been granted for following rule: + * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out + * of bounds [0,3] in following API : + * HAL_EXTI_SetConfigLine + * HAL_EXTI_GetConfigLine + * HAL_EXTI_ClearConfigLine + */ + +#ifdef HAL_EXTI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup EXTI_Exported_Functions + * @{ + */ + +/** @addtogroup EXTI_Exported_Functions_Group1 + * @brief Configuration functions + * +@verbatim + =============================================================================== + ##### Configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Set configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on EXTI configuration to be set. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +{ + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check parameters */ + assert_param(IS_EXTI_LINE(pExtiConfig->Line)); + assert_param(IS_EXTI_MODE(pExtiConfig->Mode)); + + /* Assign line number to handle */ + hexti->Line = pExtiConfig->Line; + + /* Compute line mask */ + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* Configure triggers for configurable lines */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) + { + assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger)); + + /* Configure rising trigger */ + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u) + { + EXTI->RTSR |= maskline; + } + else + { + EXTI->RTSR &= ~maskline; + } + + /* Configure falling trigger */ + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u) + { + EXTI->FTSR |= maskline; + } + else + { + EXTI->FTSR &= ~maskline; + } + + + /* Configure gpio port selection in case of gpio exti line */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel)); + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = SYSCFG->EXTICR[linepos >> 2u]; + regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + SYSCFG->EXTICR[linepos >> 2u] = regval; + } + } + + /* Configure interrupt mode : read current mode */ + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u) + { + EXTI->IMR |= maskline; + } + else + { + EXTI->IMR &= ~maskline; + } + + /* Configure event mode : read current mode */ + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u) + { + EXTI->EMR |= maskline; + } + else + { + EXTI->EMR &= ~maskline; + } + + return HAL_OK; +} + +/** + * @brief Get configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on structure to store Exti configuration. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +{ + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* Store handle line number to configuration structure */ + pExtiConfig->Line = hexti->Line; + + /* Compute line mask */ + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* 1] Get core mode : interrupt */ + + /* Check if selected line is enable */ + if ((EXTI->IMR & maskline) != 0x00u) + { + pExtiConfig->Mode = EXTI_MODE_INTERRUPT; + } + else + { + pExtiConfig->Mode = EXTI_MODE_NONE; + } + + /* Get event mode */ + /* Check if selected line is enable */ + if ((EXTI->EMR & maskline) != 0x00u) + { + pExtiConfig->Mode |= EXTI_MODE_EVENT; + } + + /* 2] Get trigger for configurable lines : rising */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) + { + /* Check if configuration of selected line is enable */ + if ((EXTI->RTSR & maskline) != 0x00u) + { + pExtiConfig->Trigger = EXTI_TRIGGER_RISING; + } + else + { + pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + } + + /* Get falling configuration */ + /* Check if configuration of selected line is enable */ + if ((EXTI->FTSR & maskline) != 0x00u) + { + pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING; + } + + /* Get Gpio port selection for gpio lines */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = SYSCFG->EXTICR[linepos >> 2u]; + pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24); + } + else + { + pExtiConfig->GPIOSel = 0x00u; + } + } + else + { + /* No Trigger selected */ + pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + pExtiConfig->GPIOSel = 0x00u; + } + + return HAL_OK; +} + +/** + * @brief Clear whole configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti) +{ + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* compute line mask */ + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* 1] Clear interrupt mode */ + EXTI->IMR = (EXTI->IMR & ~maskline); + + /* 2] Clear event mode */ + EXTI->EMR = (EXTI->EMR & ~maskline); + + /* 3] Clear triggers in case of configurable lines */ + if ((hexti->Line & EXTI_CONFIG) != 0x00u) + { + EXTI->RTSR = (EXTI->RTSR & ~maskline); + EXTI->FTSR = (EXTI->FTSR & ~maskline); + + /* Get Gpio port selection for gpio lines */ + if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = SYSCFG->EXTICR[linepos >> 2u]; + regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + SYSCFG->EXTICR[linepos >> 2u] = regval; + } + } + + return HAL_OK; +} + +/** + * @brief Register callback for a dedicated Exti line. + * @param hexti Exti handle. + * @param CallbackID User callback identifier. + * This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values. + * @param pPendingCbfn function pointer to be stored as callback. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)) +{ + HAL_StatusTypeDef status = HAL_OK; + + switch (CallbackID) + { + case HAL_EXTI_COMMON_CB_ID: + hexti->PendingCallback = pPendingCbfn; + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} + +/** + * @brief Store line number as handle private field. + * @param hexti Exti handle. + * @param ExtiLine Exti line number. + * This parameter can be from 0 to @ref EXTI_LINE_NB. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(ExtiLine)); + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + else + { + /* Store line number as handle private field */ + hexti->Line = ExtiLine; + + return HAL_OK; + } +} + +/** + * @} + */ + +/** @addtogroup EXTI_Exported_Functions_Group2 + * @brief EXTI IO functions. + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Handle EXTI interrupt request. + * @param hexti Exti handle. + * @retval none. + */ +void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) +{ + uint32_t regval; + uint32_t maskline; + + /* Compute line mask */ + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + + /* Get pending bit */ + regval = (EXTI->PR & maskline); + if (regval != 0x00u) + { + /* Clear pending bit */ + EXTI->PR = maskline; + + /* Call callback */ + if (hexti->PendingCallback != NULL) + { + hexti->PendingCallback(); + } + } +} + +/** + * @brief Get interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be checked. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING_FALLING + * This parameter is kept for compatibility with other series. + * @retval 1 if interrupt is pending else 0. + */ +uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + assert_param(IS_EXTI_PENDING_EDGE(Edge)); + + /* Compute line mask */ + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* return 1 if bit is set else 0 */ + regval = ((EXTI->PR & maskline) >> linepos); + return regval; +} + +/** + * @brief Clear interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be clear. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING_FALLING + * This parameter is kept for compatibility with other series. + * @retval None. + */ +void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + uint32_t maskline; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + assert_param(IS_EXTI_PENDING_EDGE(Edge)); + + /* Compute line mask */ + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + + /* Clear Pending bit */ + EXTI->PR = maskline; +} + +/** + * @brief Generate a software interrupt for a dedicated line. + * @param hexti Exti handle. + * @retval None. + */ +void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) +{ + uint32_t maskline; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + + /* Compute line mask */ + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + + /* Generate Software interrupt */ + EXTI->SWIER = maskline; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_EXTI_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c new file mode 100644 index 0000000..69b47a6 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c @@ -0,0 +1,778 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_flash.c + * @author MCD Application Team + * @brief FLASH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the internal FLASH memory: + * + Program operations functions + * + Memory Control functions + * + Peripheral Errors functions + * + @verbatim + ============================================================================== + ##### FLASH peripheral features ##### + ============================================================================== + + [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses + to the Flash memory. It implements the erase and program Flash memory operations + and the read and write protection mechanisms. + + [..] The Flash memory interface accelerates code execution with a system of instruction + prefetch and cache lines. + + [..] The FLASH main features are: + (+) Flash memory read operations + (+) Flash memory program/erase operations + (+) Read / write protections + (+) Prefetch on I-Code + (+) 64 cache lines of 128 bits on I-Code + (+) 8 cache lines of 128 bits on D-Code + + + ##### How to use this driver ##### + ============================================================================== + [..] + This driver provides functions and macros to configure and program the FLASH + memory of all STM32F4xx devices. + + (#) FLASH Memory IO Programming functions: + (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and + HAL_FLASH_Lock() functions + (++) Program functions: byte, half word, word and double word + (++) There Two modes of programming : + (+++) Polling mode using HAL_FLASH_Program() function + (+++) Interrupt mode using HAL_FLASH_Program_IT() function + + (#) Interrupts and flags management functions : + (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler() + (++) Wait for last FLASH operation according to its status + (++) Get error flag status by calling HAL_SetErrorCode() + + [..] + In addition to these functions, this driver includes a set of macros allowing + to handle the following operations: + (+) Set the latency + (+) Enable/Disable the prefetch buffer + (+) Enable/Disable the Instruction cache and the Data cache + (+) Reset the Instruction cache and the Data cache + (+) Enable/Disable the FLASH interrupts + (+) Monitor the FLASH flags status + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup FLASH FLASH + * @brief FLASH HAL module driver + * @{ + */ + +#ifdef HAL_FLASH_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup FLASH_Private_Constants + * @{ + */ +#define FLASH_TIMEOUT_VALUE 50000U /* 50 s */ +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup FLASH_Private_Variables + * @{ + */ +/* Variable used for Erase sectors under interruption */ +FLASH_ProcessTypeDef pFlash; +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup FLASH_Private_Functions + * @{ + */ +/* Program operations */ +static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data); +static void FLASH_Program_Word(uint32_t Address, uint32_t Data); +static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data); +static void FLASH_Program_Byte(uint32_t Address, uint8_t Data); +static void FLASH_SetErrorCode(void); + +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Functions FLASH Exported Functions + * @{ + */ + +/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions + * @brief Programming operation functions + * +@verbatim + =============================================================================== + ##### Programming operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the FLASH + program operations. + +@endverbatim + * @{ + */ + +/** + * @brief Program byte, halfword, word or double word at a specified address + * @param TypeProgram Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + if(TypeProgram == FLASH_TYPEPROGRAM_BYTE) + { + /*Program byte (8-bit) at a specified address.*/ + FLASH_Program_Byte(Address, (uint8_t) Data); + } + else if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) + { + /*Program halfword (16-bit) at a specified address.*/ + FLASH_Program_HalfWord(Address, (uint16_t) Data); + } + else if(TypeProgram == FLASH_TYPEPROGRAM_WORD) + { + /*Program word (32-bit) at a specified address.*/ + FLASH_Program_Word(Address, (uint32_t) Data); + } + else + { + /*Program double word (64-bit) at a specified address.*/ + FLASH_Program_DoubleWord(Address, Data); + } + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the program operation is completed, disable the PG Bit */ + FLASH->CR &= (~FLASH_CR_PG); + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Program byte, halfword, word or double word at a specified address with interrupt enabled. + * @param TypeProgram Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + + /* Enable End of FLASH Operation interrupt */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP); + + /* Enable Error source interrupt */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR); + + pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM; + pFlash.Address = Address; + + if(TypeProgram == FLASH_TYPEPROGRAM_BYTE) + { + /*Program byte (8-bit) at a specified address.*/ + FLASH_Program_Byte(Address, (uint8_t) Data); + } + else if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) + { + /*Program halfword (16-bit) at a specified address.*/ + FLASH_Program_HalfWord(Address, (uint16_t) Data); + } + else if(TypeProgram == FLASH_TYPEPROGRAM_WORD) + { + /*Program word (32-bit) at a specified address.*/ + FLASH_Program_Word(Address, (uint32_t) Data); + } + else + { + /*Program double word (64-bit) at a specified address.*/ + FLASH_Program_DoubleWord(Address, Data); + } + + return status; +} + +/** + * @brief This function handles FLASH interrupt request. + * @retval None + */ +void HAL_FLASH_IRQHandler(void) +{ + uint32_t addresstmp = 0U; + + /* Check FLASH operation error flags */ +#if defined(FLASH_SR_RDERR) + if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \ + FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_RDERR)) != RESET) +#else + if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \ + FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR)) != RESET) +#endif /* FLASH_SR_RDERR */ + { + if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE) + { + /*return the faulty sector*/ + addresstmp = pFlash.Sector; + pFlash.Sector = 0xFFFFFFFFU; + } + else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) + { + /*return the faulty bank*/ + addresstmp = pFlash.Bank; + } + else + { + /*return the faulty address*/ + addresstmp = pFlash.Address; + } + + /*Save the Error code*/ + FLASH_SetErrorCode(); + + /* FLASH error interrupt user callback */ + HAL_FLASH_OperationErrorCallback(addresstmp); + + /*Stop the procedure ongoing*/ + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } + + /* Check FLASH End of Operation flag */ + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + + if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE) + { + /*Nb of sector to erased can be decreased*/ + pFlash.NbSectorsToErase--; + + /* Check if there are still sectors to erase*/ + if(pFlash.NbSectorsToErase != 0U) + { + addresstmp = pFlash.Sector; + /*Indicate user which sector has been erased*/ + HAL_FLASH_EndOfOperationCallback(addresstmp); + + /*Increment sector number*/ + pFlash.Sector++; + addresstmp = pFlash.Sector; + FLASH_Erase_Sector(addresstmp, pFlash.VoltageForErase); + } + else + { + /*No more sectors to Erase, user callback can be called.*/ + /*Reset Sector and stop Erase sectors procedure*/ + pFlash.Sector = addresstmp = 0xFFFFFFFFU; + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + + /* Flush the caches to be sure of the data consistency */ + FLASH_FlushCaches() ; + + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(addresstmp); + } + } + else + { + if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) + { + /* MassErase ended. Return the selected bank */ + /* Flush the caches to be sure of the data consistency */ + FLASH_FlushCaches() ; + + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(pFlash.Bank); + } + else + { + /*Program ended. Return the selected address*/ + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(pFlash.Address); + } + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } + } + + if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE) + { + /* Operation is completed, disable the PG, SER, SNB and MER Bits */ + CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_SER | FLASH_CR_SNB | FLASH_MER_BIT)); + + /* Disable End of FLASH Operation interrupt */ + __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP); + + /* Disable Error source interrupt */ + __HAL_FLASH_DISABLE_IT(FLASH_IT_ERR); + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + } +} + +/** + * @brief FLASH end of operation interrupt callback + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + * Mass Erase: Bank number which has been requested to erase + * Sectors Erase: Sector which has been erased + * (if 0xFFFFFFFFU, it means that all the selected sectors have been erased) + * Program: Address which was selected for data program + * @retval None + */ +__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FLASH_EndOfOperationCallback could be implemented in the user file + */ +} + +/** + * @brief FLASH operation error interrupt callback + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + * Mass Erase: Bank number which has been requested to erase + * Sectors Erase: Sector number which returned an error + * Program: Address which was selected for data program + * @retval None + */ +__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FLASH_OperationErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions + * @brief management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the FLASH + memory operations. + +@endverbatim + * @{ + */ + +/** + * @brief Unlock the FLASH control register access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Unlock(void) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) + { + /* Authorize the FLASH Registers access */ + WRITE_REG(FLASH->KEYR, FLASH_KEY1); + WRITE_REG(FLASH->KEYR, FLASH_KEY2); + + /* Verify Flash is unlocked */ + if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) + { + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief Locks the FLASH control register access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Lock(void) +{ + /* Set the LOCK Bit to lock the FLASH Registers access */ + FLASH->CR |= FLASH_CR_LOCK; + + return HAL_OK; +} + +/** + * @brief Unlock the FLASH Option Control Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) +{ + if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET) + { + /* Authorizes the Option Byte register programming */ + FLASH->OPTKEYR = FLASH_OPT_KEY1; + FLASH->OPTKEYR = FLASH_OPT_KEY2; + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Lock the FLASH Option Control Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) +{ + /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */ + FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK; + + return HAL_OK; +} + +/** + * @brief Launch the option byte loading. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) +{ + /* Set the OPTSTRT bit in OPTCR register */ + *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= FLASH_OPTCR_OPTSTRT; + + /* Wait for last operation to be completed */ + return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE)); +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief Peripheral Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral Errors functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time Errors of the FLASH peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Get the specific FLASH error flag. + * @retval FLASH_ErrorCode: The returned value can be a combination of: + * @arg HAL_FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP) + * @arg HAL_FLASH_ERROR_PGS: FLASH Programming Sequence error flag + * @arg HAL_FLASH_ERROR_PGP: FLASH Programming Parallelism error flag + * @arg HAL_FLASH_ERROR_PGA: FLASH Programming Alignment error flag + * @arg HAL_FLASH_ERROR_WRP: FLASH Write protected error flag + * @arg HAL_FLASH_ERROR_OPERATION: FLASH operation Error flag + */ +uint32_t HAL_FLASH_GetError(void) +{ + return pFlash.ErrorCode; +} + +/** + * @} + */ + +/** + * @brief Wait for a FLASH operation to complete. + * @param Timeout maximum flash operationtimeout + * @retval HAL Status + */ +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) +{ + uint32_t tickstart = 0U; + + /* Clear Error Code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. + Even if the FLASH operation fails, the BUSY flag will be reset and an error + flag will be set */ + /* Get tick */ + tickstart = HAL_GetTick(); + + while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) + { + return HAL_TIMEOUT; + } + } + } + + /* Check FLASH End of Operation flag */ + if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + } +#if defined(FLASH_SR_RDERR) + if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \ + FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_RDERR)) != RESET) +#else + if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \ + FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR)) != RESET) +#endif /* FLASH_SR_RDERR */ + { + /*Save the error code*/ + FLASH_SetErrorCode(); + return HAL_ERROR; + } + + /* If there is no error flag set */ + return HAL_OK; + +} + +/** + * @brief Program a double word (64-bit) at a specified address. + * @note This function must be used when the device voltage range is from + * 2.7V to 3.6V and Vpp in the range 7V to 9V. + * + * @note If an erase and a program operations are requested simultaneously, + * the erase operation is performed before the program one. + * + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed. + * @retval None + */ +static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data) +{ + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + + /* If the previous operation is completed, proceed to program the new data */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); + FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD; + FLASH->CR |= FLASH_CR_PG; + + /* Program first word */ + *(__IO uint32_t*)Address = (uint32_t)Data; + + /* Barrier to ensure programming is performed in 2 steps, in right order + (independently of compiler optimization behavior) */ + __ISB(); + + /* Program second word */ + *(__IO uint32_t*)(Address+4) = (uint32_t)(Data >> 32); +} + + +/** + * @brief Program word (32-bit) at a specified address. + * @note This function must be used when the device voltage range is from + * 2.7V to 3.6V. + * + * @note If an erase and a program operations are requested simultaneously, + * the erase operation is performed before the program one. + * + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed. + * @retval None + */ +static void FLASH_Program_Word(uint32_t Address, uint32_t Data) +{ + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + + /* If the previous operation is completed, proceed to program the new data */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); + FLASH->CR |= FLASH_PSIZE_WORD; + FLASH->CR |= FLASH_CR_PG; + + *(__IO uint32_t*)Address = Data; +} + +/** + * @brief Program a half-word (16-bit) at a specified address. + * @note This function must be used when the device voltage range is from + * 2.1V to 3.6V. + * + * @note If an erase and a program operations are requested simultaneously, + * the erase operation is performed before the program one. + * + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed. + * @retval None + */ +static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) +{ + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + + /* If the previous operation is completed, proceed to program the new data */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); + FLASH->CR |= FLASH_PSIZE_HALF_WORD; + FLASH->CR |= FLASH_CR_PG; + + *(__IO uint16_t*)Address = Data; +} + +/** + * @brief Program byte (8-bit) at a specified address. + * @note This function must be used when the device voltage range is from + * 1.8V to 3.6V. + * + * @note If an erase and a program operations are requested simultaneously, + * the erase operation is performed before the program one. + * + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed. + * @retval None + */ +static void FLASH_Program_Byte(uint32_t Address, uint8_t Data) +{ + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + + /* If the previous operation is completed, proceed to program the new data */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); + FLASH->CR |= FLASH_PSIZE_BYTE; + FLASH->CR |= FLASH_CR_PG; + + *(__IO uint8_t*)Address = Data; +} + +/** + * @brief Set the specific FLASH error flag. + * @retval None + */ +static void FLASH_SetErrorCode(void) +{ + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; + + /* Clear FLASH write protection error pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_WRPERR); + } + + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA; + + /* Clear FLASH Programming alignment error pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGAERR); + } + + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGPERR) != RESET) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_PGP; + + /* Clear FLASH Programming parallelism error pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGPERR); + } + + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGSERR) != RESET) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_PGS; + + /* Clear FLASH Programming sequence error pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGSERR); + } +#if defined(FLASH_SR_RDERR) + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_RD; + + /* Clear FLASH Proprietary readout protection error pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_RDERR); + } +#endif /* FLASH_SR_RDERR */ + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR) != RESET) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_OPERATION; + + /* Clear FLASH Operation error pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPERR); + } +} + +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c new file mode 100644 index 0000000..066aa50 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c @@ -0,0 +1,1350 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_flash_ex.c + * @author MCD Application Team + * @brief Extended FLASH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the FLASH extension peripheral: + * + Extended programming operations functions + * + @verbatim + ============================================================================== + ##### Flash Extension features ##### + ============================================================================== + + [..] Comparing to other previous devices, the FLASH interface for STM32F427xx/437xx and + STM32F429xx/439xx devices contains the following additional features + + (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write + capability (RWW) + (+) Dual bank memory organization + (+) PCROP protection for all banks + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to configure and program the FLASH memory + of all STM32F427xx/437xx, STM32F429xx/439xx, STM32F469xx/479xx and STM32F446xx + devices. It includes + (#) FLASH Memory Erase functions: + (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and + HAL_FLASH_Lock() functions + (++) Erase function: Erase sector, erase all sectors + (++) There are two modes of erase : + (+++) Polling Mode using HAL_FLASHEx_Erase() + (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT() + + (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to : + (++) Set/Reset the write protection + (++) Set the Read protection Level + (++) Set the BOR level + (++) Program the user Option Bytes + (#) Advanced Option Bytes Programming functions: Use HAL_FLASHEx_AdvOBProgram() to : + (++) Extended space (bank 2) erase function + (++) Full FLASH space (2 Mo) erase (bank 1 and bank 2) + (++) Dual Boot activation + (++) Write protection configuration for bank 2 + (++) PCROP protection configuration and control for both banks + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup FLASHEx FLASHEx + * @brief FLASH HAL Extension module driver + * @{ + */ + +#ifdef HAL_FLASH_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup FLASHEx_Private_Constants + * @{ + */ +#define FLASH_TIMEOUT_VALUE 50000U /* 50 s */ +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup FLASHEx_Private_Variables + * @{ + */ +extern FLASH_ProcessTypeDef pFlash; +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup FLASHEx_Private_Functions + * @{ + */ +/* Option bytes control */ +static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks); +static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks); +static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks); +static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level); +static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t Iwdg, uint8_t Stop, uint8_t Stdby); +static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level); +static uint8_t FLASH_OB_GetUser(void); +static uint16_t FLASH_OB_GetWRP(void); +static uint8_t FLASH_OB_GetRDP(void); +static uint8_t FLASH_OB_GetBOR(void); + +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\ + defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\ + defined(STM32F423xx) +static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t Sector); +static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t Sector); +#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx + STM32F413xx || STM32F423xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) +static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks); +static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks); +static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t BootConfig); +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions + * @{ + */ + +/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions + * @brief Extended IO operation functions + * +@verbatim + =============================================================================== + ##### Extended programming operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the Extension FLASH + programming operations. + +@endverbatim + * @{ + */ +/** + * @brief Perform a mass erase or erase the specified FLASH memory sectors + * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * + * @param[out] SectorError pointer to variable that + * contains the configuration information on faulty sector in case of error + * (0xFFFFFFFFU means that all the sectors have been correctly erased) + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError) +{ + HAL_StatusTypeDef status = HAL_ERROR; + uint32_t index = 0U; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /*Initialization of SectorError variable*/ + *SectorError = 0xFFFFFFFFU; + + if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) + { + /*Mass erase to be done*/ + FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* if the erase operation is completed, disable the MER Bit */ + FLASH->CR &= (~FLASH_MER_BIT); + } + else + { + /* Check the parameters */ + assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector)); + + /* Erase by sector by sector to be done*/ + for(index = pEraseInit->Sector; index < (pEraseInit->NbSectors + pEraseInit->Sector); index++) + { + FLASH_Erase_Sector(index, (uint8_t) pEraseInit->VoltageRange); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the erase operation is completed, disable the SER and SNB Bits */ + CLEAR_BIT(FLASH->CR, (FLASH_CR_SER | FLASH_CR_SNB)); + + if(status != HAL_OK) + { + /* In case of error, stop erase procedure and return the faulty sector*/ + *SectorError = index; + break; + } + } + } + /* Flush the caches to be sure of the data consistency */ + FLASH_FlushCaches(); + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled + * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + + /* Enable End of FLASH Operation interrupt */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP); + + /* Enable Error source interrupt */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR); + + /* Clear pending flags (if any) */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\ + FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_PGSERR); + + if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) + { + /*Mass erase to be done*/ + pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE; + pFlash.Bank = pEraseInit->Banks; + FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks); + } + else + { + /* Erase by sector to be done*/ + + /* Check the parameters */ + assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector)); + + pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE; + pFlash.NbSectorsToErase = pEraseInit->NbSectors; + pFlash.Sector = pEraseInit->Sector; + pFlash.VoltageForErase = (uint8_t)pEraseInit->VoltageRange; + + /*Erase 1st sector and wait for IT*/ + FLASH_Erase_Sector(pEraseInit->Sector, pEraseInit->VoltageRange); + } + + return status; +} + +/** + * @brief Program option bytes + * @param pOBInit pointer to an FLASH_OBInitStruct structure that + * contains the configuration information for the programming. + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); + + /*Write protection configuration*/ + if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP) + { + assert_param(IS_WRPSTATE(pOBInit->WRPState)); + if(pOBInit->WRPState == OB_WRPSTATE_ENABLE) + { + /*Enable of Write protection on the selected Sector*/ + status = FLASH_OB_EnableWRP(pOBInit->WRPSector, pOBInit->Banks); + } + else + { + /*Disable of Write protection on the selected Sector*/ + status = FLASH_OB_DisableWRP(pOBInit->WRPSector, pOBInit->Banks); + } + } + + /*Read protection configuration*/ + if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP) + { + status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel); + } + + /*USER configuration*/ + if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER) + { + status = FLASH_OB_UserConfig(pOBInit->USERConfig&OB_IWDG_SW, + pOBInit->USERConfig&OB_STOP_NO_RST, + pOBInit->USERConfig&OB_STDBY_NO_RST); + } + + /*BOR Level configuration*/ + if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR) + { + status = FLASH_OB_BOR_LevelConfig(pOBInit->BORLevel); + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Get the Option byte configuration + * @param pOBInit pointer to an FLASH_OBInitStruct structure that + * contains the configuration information for the programming. + * + * @retval None + */ +void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) +{ + pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_BOR; + + /*Get WRP*/ + pOBInit->WRPSector = (uint32_t)FLASH_OB_GetWRP(); + + /*Get RDP Level*/ + pOBInit->RDPLevel = (uint32_t)FLASH_OB_GetRDP(); + + /*Get USER*/ + pOBInit->USERConfig = (uint8_t)FLASH_OB_GetUser(); + + /*Get BOR Level*/ + pOBInit->BORLevel = (uint32_t)FLASH_OB_GetBOR(); +} + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ + defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ + defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ + defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/** + * @brief Program option bytes + * @param pAdvOBInit pointer to an FLASH_AdvOBProgramInitTypeDef structure that + * contains the configuration information for the programming. + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* Check the parameters */ + assert_param(IS_OBEX(pAdvOBInit->OptionType)); + + /*Program PCROP option byte*/ + if(((pAdvOBInit->OptionType) & OPTIONBYTE_PCROP) == OPTIONBYTE_PCROP) + { + /* Check the parameters */ + assert_param(IS_PCROPSTATE(pAdvOBInit->PCROPState)); + if((pAdvOBInit->PCROPState) == OB_PCROP_STATE_ENABLE) + { + /*Enable of Write protection on the selected Sector*/ +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\ + defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ + defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) + status = FLASH_OB_EnablePCROP(pAdvOBInit->Sectors); +#else /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */ + status = FLASH_OB_EnablePCROP(pAdvOBInit->SectorsBank1, pAdvOBInit->SectorsBank2, pAdvOBInit->Banks); +#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || + STM32F413xx || STM32F423xx */ + } + else + { + /*Disable of Write protection on the selected Sector*/ +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\ + defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ + defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) + status = FLASH_OB_DisablePCROP(pAdvOBInit->Sectors); +#else /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */ + status = FLASH_OB_DisablePCROP(pAdvOBInit->SectorsBank1, pAdvOBInit->SectorsBank2, pAdvOBInit->Banks); +#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || + STM32F413xx || STM32F423xx */ + } + } + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) + /*Program BOOT config option byte*/ + if(((pAdvOBInit->OptionType) & OPTIONBYTE_BOOTCONFIG) == OPTIONBYTE_BOOTCONFIG) + { + status = FLASH_OB_BootConfig(pAdvOBInit->BootConfig); + } +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + + return status; +} + +/** + * @brief Get the OBEX byte configuration + * @param pAdvOBInit pointer to an FLASH_AdvOBProgramInitTypeDef structure that + * contains the configuration information for the programming. + * + * @retval None + */ +void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit) +{ +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\ + defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ + defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) + /*Get Sector*/ + pAdvOBInit->Sectors = (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS)); +#else /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */ + /*Get Sector for Bank1*/ + pAdvOBInit->SectorsBank1 = (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS)); + + /*Get Sector for Bank2*/ + pAdvOBInit->SectorsBank2 = (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS)); + + /*Get Boot config OB*/ + pAdvOBInit->BootConfig = *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS; +#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || + STM32F413xx || STM32F423xx */ +} + +/** + * @brief Select the Protection Mode + * + * @note After PCROP activated Option Byte modification NOT POSSIBLE! excepted + * Global Read Out Protection modification (from level1 to level0) + * @note Once SPRMOD bit is active unprotection of a protected sector is not possible + * @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag + * @note This function can be used only for STM32F42xxx/STM32F43xxx/STM32F401xx/STM32F411xx/STM32F446xx/ + * STM32F469xx/STM32F479xx/STM32F412xx/STM32F413xx devices. + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void) +{ + uint8_t optiontmp = 0xFF; + + /* Mask SPRMOD bit */ + optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7F); + + /* Update Option Byte */ + *(__IO uint8_t *)OPTCR_BYTE3_ADDRESS = (uint8_t)(OB_PCROP_SELECTED | optiontmp); + + return HAL_OK; +} + +/** + * @brief Deselect the Protection Mode + * + * @note After PCROP activated Option Byte modification NOT POSSIBLE! excepted + * Global Read Out Protection modification (from level1 to level0) + * @note Once SPRMOD bit is active unprotection of a protected sector is not possible + * @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag + * @note This function can be used only for STM32F42xxx/STM32F43xxx/STM32F401xx/STM32F411xx/STM32F446xx/ + * STM32F469xx/STM32F479xx/STM32F412xx/STM32F413xx devices. + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void) +{ + uint8_t optiontmp = 0xFF; + + /* Mask SPRMOD bit */ + optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7F); + + /* Update Option Byte */ + *(__IO uint8_t *)OPTCR_BYTE3_ADDRESS = (uint8_t)(OB_PCROP_DESELECTED | optiontmp); + + return HAL_OK; +} +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F410xx ||\ + STM32F411xE || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || + STM32F413xx || STM32F423xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) +/** + * @brief Returns the FLASH Write Protection Option Bytes value for Bank 2 + * @note This function can be used only for STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx devices. + * @retval The FLASH Write Protection Option Bytes value + */ +uint16_t HAL_FLASHEx_OB_GetBank2WRP(void) +{ + /* Return the FLASH write protection Register value */ + return (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS)); +} +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +/** + * @} + */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) +/** + * @brief Full erase of FLASH memory sectors + * @param VoltageRange The device voltage range which defines the erase parallelism. + * This parameter can be one of the following values: + * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, + * the operation will be done by byte (8-bit) + * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, + * the operation will be done by half word (16-bit) + * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, + * the operation will be done by word (32-bit) + * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, + * the operation will be done by double word (64-bit) + * + * @param Banks Banks to be erased + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: Bank1 to be erased + * @arg FLASH_BANK_2: Bank2 to be erased + * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased + * + * @retval HAL Status + */ +static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks) +{ + /* Check the parameters */ + assert_param(IS_VOLTAGERANGE(VoltageRange)); + assert_param(IS_FLASH_BANK(Banks)); + + /* if the previous operation is completed, proceed to erase all sectors */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); + + if(Banks == FLASH_BANK_BOTH) + { + /* bank1 & bank2 will be erased*/ + FLASH->CR |= FLASH_MER_BIT; + } + else if(Banks == FLASH_BANK_1) + { + /*Only bank1 will be erased*/ + FLASH->CR |= FLASH_CR_MER1; + } + else + { + /*Only bank2 will be erased*/ + FLASH->CR |= FLASH_CR_MER2; + } + FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8U); +} + +/** + * @brief Erase the specified FLASH memory sector + * @param Sector FLASH sector to erase + * The value of this parameter depend on device used within the same series + * @param VoltageRange The device voltage range which defines the erase parallelism. + * This parameter can be one of the following values: + * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, + * the operation will be done by byte (8-bit) + * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, + * the operation will be done by half word (16-bit) + * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, + * the operation will be done by word (32-bit) + * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, + * the operation will be done by double word (64-bit) + * + * @retval None + */ +void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange) +{ + uint32_t tmp_psize = 0U; + + /* Check the parameters */ + assert_param(IS_FLASH_SECTOR(Sector)); + assert_param(IS_VOLTAGERANGE(VoltageRange)); + + if(VoltageRange == FLASH_VOLTAGE_RANGE_1) + { + tmp_psize = FLASH_PSIZE_BYTE; + } + else if(VoltageRange == FLASH_VOLTAGE_RANGE_2) + { + tmp_psize = FLASH_PSIZE_HALF_WORD; + } + else if(VoltageRange == FLASH_VOLTAGE_RANGE_3) + { + tmp_psize = FLASH_PSIZE_WORD; + } + else + { + tmp_psize = FLASH_PSIZE_DOUBLE_WORD; + } + + /* Need to add offset of 4 when sector higher than FLASH_SECTOR_11 */ + if(Sector > FLASH_SECTOR_11) + { + Sector += 4U; + } + /* If the previous operation is completed, proceed to erase the sector */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); + FLASH->CR |= tmp_psize; + CLEAR_BIT(FLASH->CR, FLASH_CR_SNB); + FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos); + FLASH->CR |= FLASH_CR_STRT; +} + +/** + * @brief Enable the write protection of the desired bank1 or bank 2 sectors + * + * @note When the memory read protection level is selected (RDP level = 1), + * it is not possible to program or erase the flash sector i if CortexM4 + * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1). + * + * @param WRPSector specifies the sector(s) to be write protected. + * This parameter can be one of the following values: + * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_23 + * @arg OB_WRP_SECTOR_All + * @note BANK2 starts from OB_WRP_SECTOR_12 + * + * @param Banks Enable write protection on all the sectors for the specific bank + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: WRP on all sectors of bank1 + * @arg FLASH_BANK_2: WRP on all sectors of bank2 + * @arg FLASH_BANK_BOTH: WRP on all sectors of bank1 & bank2 + * + * @retval HAL FLASH State + */ +static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_WRP_SECTOR(WRPSector)); + assert_param(IS_FLASH_BANK(Banks)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + if(((WRPSector == OB_WRP_SECTOR_All) && ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))) || + (WRPSector < OB_WRP_SECTOR_12)) + { + if(WRPSector == OB_WRP_SECTOR_All) + { + /*Write protection on all sector of BANK1*/ + *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~(WRPSector>>12)); + } + else + { + /*Write protection done on sectors of BANK1*/ + *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~WRPSector); + } + } + else + { + /*Write protection done on sectors of BANK2*/ + *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~(WRPSector>>12)); + } + + /*Write protection on all sector of BANK2*/ + if((WRPSector == OB_WRP_SECTOR_All) && (Banks == FLASH_BANK_BOTH)) + { + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~(WRPSector>>12)); + } + } + + } + return status; +} + +/** + * @brief Disable the write protection of the desired bank1 or bank 2 sectors + * + * @note When the memory read protection level is selected (RDP level = 1), + * it is not possible to program or erase the flash sector i if CortexM4 + * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1). + * + * @param WRPSector specifies the sector(s) to be write protected. + * This parameter can be one of the following values: + * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_23 + * @arg OB_WRP_Sector_All + * @note BANK2 starts from OB_WRP_SECTOR_12 + * + * @param Banks Disable write protection on all the sectors for the specific bank + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: Bank1 to be erased + * @arg FLASH_BANK_2: Bank2 to be erased + * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased + * + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_WRP_SECTOR(WRPSector)); + assert_param(IS_FLASH_BANK(Banks)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + if(((WRPSector == OB_WRP_SECTOR_All) && ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))) || + (WRPSector < OB_WRP_SECTOR_12)) + { + if(WRPSector == OB_WRP_SECTOR_All) + { + /*Write protection on all sector of BANK1*/ + *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)(WRPSector>>12); + } + else + { + /*Write protection done on sectors of BANK1*/ + *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)WRPSector; + } + } + else + { + /*Write protection done on sectors of BANK2*/ + *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)(WRPSector>>12); + } + + /*Write protection on all sector of BANK2*/ + if((WRPSector == OB_WRP_SECTOR_All) && (Banks == FLASH_BANK_BOTH)) + { + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)(WRPSector>>12); + } + } + + } + + return status; +} + +/** + * @brief Configure the Dual Bank Boot. + * + * @note This function can be used only for STM32F42xxx/43xxx devices. + * + * @param BootConfig specifies the Dual Bank Boot Option byte. + * This parameter can be one of the following values: + * @arg OB_Dual_BootEnabled: Dual Bank Boot Enable + * @arg OB_Dual_BootDisabled: Dual Bank Boot Disabled + * @retval None + */ +static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t BootConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_BOOT(BootConfig)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Set Dual Bank Boot */ + *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BFB2); + *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= BootConfig; + } + + return status; +} + +/** + * @brief Enable the read/write protection (PCROP) of the desired + * sectors of Bank 1 and/or Bank 2. + * @note This function can be used only for STM32F42xxx/43xxx devices. + * @param SectorBank1 Specifies the sector(s) to be read/write protected or unprotected for bank1. + * This parameter can be one of the following values: + * @arg OB_PCROP: A value between OB_PCROP_SECTOR_0 and OB_PCROP_SECTOR_11 + * @arg OB_PCROP_SECTOR__All + * @param SectorBank2 Specifies the sector(s) to be read/write protected or unprotected for bank2. + * This parameter can be one of the following values: + * @arg OB_PCROP: A value between OB_PCROP_SECTOR_12 and OB_PCROP_SECTOR_23 + * @arg OB_PCROP_SECTOR__All + * @param Banks Enable PCROP protection on all the sectors for the specific bank + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: WRP on all sectors of bank1 + * @arg FLASH_BANK_2: WRP on all sectors of bank2 + * @arg FLASH_BANK_BOTH: WRP on all sectors of bank1 & bank2 + * + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks) +{ + HAL_StatusTypeDef status = HAL_OK; + + assert_param(IS_FLASH_BANK(Banks)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + if((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH)) + { + assert_param(IS_OB_PCROP(SectorBank1)); + /*Write protection done on sectors of BANK1*/ + *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)SectorBank1; + } + else + { + assert_param(IS_OB_PCROP(SectorBank2)); + /*Write protection done on sectors of BANK2*/ + *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)SectorBank2; + } + + /*Write protection on all sector of BANK2*/ + if(Banks == FLASH_BANK_BOTH) + { + assert_param(IS_OB_PCROP(SectorBank2)); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /*Write protection done on sectors of BANK2*/ + *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)SectorBank2; + } + } + + } + + return status; +} + + +/** + * @brief Disable the read/write protection (PCROP) of the desired + * sectors of Bank 1 and/or Bank 2. + * @note This function can be used only for STM32F42xxx/43xxx devices. + * @param SectorBank1 specifies the sector(s) to be read/write protected or unprotected for bank1. + * This parameter can be one of the following values: + * @arg OB_PCROP: A value between OB_PCROP_SECTOR_0 and OB_PCROP_SECTOR_11 + * @arg OB_PCROP_SECTOR__All + * @param SectorBank2 Specifies the sector(s) to be read/write protected or unprotected for bank2. + * This parameter can be one of the following values: + * @arg OB_PCROP: A value between OB_PCROP_SECTOR_12 and OB_PCROP_SECTOR_23 + * @arg OB_PCROP_SECTOR__All + * @param Banks Disable PCROP protection on all the sectors for the specific bank + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: WRP on all sectors of bank1 + * @arg FLASH_BANK_2: WRP on all sectors of bank2 + * @arg FLASH_BANK_BOTH: WRP on all sectors of bank1 & bank2 + * + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_FLASH_BANK(Banks)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + if((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH)) + { + assert_param(IS_OB_PCROP(SectorBank1)); + /*Write protection done on sectors of BANK1*/ + *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~SectorBank1); + } + else + { + /*Write protection done on sectors of BANK2*/ + assert_param(IS_OB_PCROP(SectorBank2)); + *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~SectorBank2); + } + + /*Write protection on all sector of BANK2*/ + if(Banks == FLASH_BANK_BOTH) + { + assert_param(IS_OB_PCROP(SectorBank2)); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /*Write protection done on sectors of BANK2*/ + *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~SectorBank2); + } + } + + } + + return status; + +} + +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ + defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\ + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\ + defined(STM32F423xx) +/** + * @brief Mass erase of FLASH memory + * @param VoltageRange The device voltage range which defines the erase parallelism. + * This parameter can be one of the following values: + * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, + * the operation will be done by byte (8-bit) + * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, + * the operation will be done by half word (16-bit) + * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, + * the operation will be done by word (32-bit) + * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, + * the operation will be done by double word (64-bit) + * + * @param Banks Banks to be erased + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: Bank1 to be erased + * + * @retval None + */ +static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks) +{ + /* Check the parameters */ + assert_param(IS_VOLTAGERANGE(VoltageRange)); + assert_param(IS_FLASH_BANK(Banks)); + + /* If the previous operation is completed, proceed to erase all sectors */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); + FLASH->CR |= FLASH_CR_MER; + FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8U); +} + +/** + * @brief Erase the specified FLASH memory sector + * @param Sector FLASH sector to erase + * The value of this parameter depend on device used within the same series + * @param VoltageRange The device voltage range which defines the erase parallelism. + * This parameter can be one of the following values: + * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, + * the operation will be done by byte (8-bit) + * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, + * the operation will be done by half word (16-bit) + * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, + * the operation will be done by word (32-bit) + * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, + * the operation will be done by double word (64-bit) + * + * @retval None + */ +void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange) +{ + uint32_t tmp_psize = 0U; + + /* Check the parameters */ + assert_param(IS_FLASH_SECTOR(Sector)); + assert_param(IS_VOLTAGERANGE(VoltageRange)); + + if(VoltageRange == FLASH_VOLTAGE_RANGE_1) + { + tmp_psize = FLASH_PSIZE_BYTE; + } + else if(VoltageRange == FLASH_VOLTAGE_RANGE_2) + { + tmp_psize = FLASH_PSIZE_HALF_WORD; + } + else if(VoltageRange == FLASH_VOLTAGE_RANGE_3) + { + tmp_psize = FLASH_PSIZE_WORD; + } + else + { + tmp_psize = FLASH_PSIZE_DOUBLE_WORD; + } + + /* If the previous operation is completed, proceed to erase the sector */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); + FLASH->CR |= tmp_psize; + CLEAR_BIT(FLASH->CR, FLASH_CR_SNB); + FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos); + FLASH->CR |= FLASH_CR_STRT; +} + +/** + * @brief Enable the write protection of the desired bank 1 sectors + * + * @note When the memory read protection level is selected (RDP level = 1), + * it is not possible to program or erase the flash sector i if CortexM4 + * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1). + * + * @param WRPSector specifies the sector(s) to be write protected. + * The value of this parameter depend on device used within the same series + * + * @param Banks Enable write protection on all the sectors for the specific bank + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: WRP on all sectors of bank1 + * + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_WRP_SECTOR(WRPSector)); + assert_param(IS_FLASH_BANK(Banks)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~WRPSector); + } + + return status; +} + +/** + * @brief Disable the write protection of the desired bank 1 sectors + * + * @note When the memory read protection level is selected (RDP level = 1), + * it is not possible to program or erase the flash sector i if CortexM4 + * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1). + * + * @param WRPSector specifies the sector(s) to be write protected. + * The value of this parameter depend on device used within the same series + * + * @param Banks Enable write protection on all the sectors for the specific bank + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: WRP on all sectors of bank1 + * + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_WRP_SECTOR(WRPSector)); + assert_param(IS_FLASH_BANK(Banks)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)WRPSector; + } + + return status; +} +#endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx + STM32F413xx || STM32F423xx */ + +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\ + defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ + defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/** + * @brief Enable the read/write protection (PCROP) of the desired sectors. + * @note This function can be used only for STM32F401xx devices. + * @param Sector specifies the sector(s) to be read/write protected or unprotected. + * This parameter can be one of the following values: + * @arg OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector5 + * @arg OB_PCROP_Sector_All + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t Sector) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_PCROP(Sector)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)Sector; + } + + return status; +} + + +/** + * @brief Disable the read/write protection (PCROP) of the desired sectors. + * @note This function can be used only for STM32F401xx devices. + * @param Sector specifies the sector(s) to be read/write protected or unprotected. + * This parameter can be one of the following values: + * @arg OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector5 + * @arg OB_PCROP_Sector_All + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t Sector) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_PCROP(Sector)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~Sector); + } + + return status; + +} +#endif /* STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx + STM32F413xx || STM32F423xx */ + +/** + * @brief Set the read protection level. + * @param Level specifies the read protection level. + * This parameter can be one of the following values: + * @arg OB_RDP_LEVEL_0: No protection + * @arg OB_RDP_LEVEL_1: Read protection of the memory + * @arg OB_RDP_LEVEL_2: Full chip protection + * + * @note WARNING: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0 + * + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_RDP_LEVEL(Level)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = Level; + } + + return status; +} + +/** + * @brief Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. + * @param Iwdg Selects the IWDG mode + * This parameter can be one of the following values: + * @arg OB_IWDG_SW: Software IWDG selected + * @arg OB_IWDG_HW: Hardware IWDG selected + * @param Stop Reset event when entering STOP mode. + * This parameter can be one of the following values: + * @arg OB_STOP_NO_RST: No reset generated when entering in STOP + * @arg OB_STOP_RST: Reset generated when entering in STOP + * @param Stdby Reset event when entering Standby mode. + * This parameter can be one of the following values: + * @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY + * @arg OB_STDBY_RST: Reset generated when entering in STANDBY + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t Iwdg, uint8_t Stop, uint8_t Stdby) +{ + uint8_t optiontmp = 0xFF; + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_IWDG_SOURCE(Iwdg)); + assert_param(IS_OB_STOP_SOURCE(Stop)); + assert_param(IS_OB_STDBY_SOURCE(Stdby)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Mask OPTLOCK, OPTSTRT, BOR_LEV and BFB2 bits */ + optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x1F); + + /* Update User Option Byte */ + *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS = Iwdg | (uint8_t)(Stdby | (uint8_t)(Stop | ((uint8_t)optiontmp))); + } + + return status; +} + +/** + * @brief Set the BOR Level. + * @param Level specifies the Option Bytes BOR Reset Level. + * This parameter can be one of the following values: + * @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V + * @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V + * @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V + * @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level) +{ + /* Check the parameters */ + assert_param(IS_OB_BOR_LEVEL(Level)); + + /* Set the BOR Level */ + *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BOR_LEV); + *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= Level; + + return HAL_OK; + +} + +/** + * @brief Return the FLASH User Option Byte value. + * @retval uint8_t FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1) + * and RST_STDBY(Bit2). + */ +static uint8_t FLASH_OB_GetUser(void) +{ + /* Return the User Option Byte */ + return ((uint8_t)(FLASH->OPTCR & 0xE0)); +} + +/** + * @brief Return the FLASH Write Protection Option Bytes value. + * @retval uint16_t FLASH Write Protection Option Bytes value + */ +static uint16_t FLASH_OB_GetWRP(void) +{ + /* Return the FLASH write protection Register value */ + return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS)); +} + +/** + * @brief Returns the FLASH Read Protection level. + * @retval FLASH ReadOut Protection Status: + * This parameter can be one of the following values: + * @arg OB_RDP_LEVEL_0: No protection + * @arg OB_RDP_LEVEL_1: Read protection of the memory + * @arg OB_RDP_LEVEL_2: Full chip protection + */ +static uint8_t FLASH_OB_GetRDP(void) +{ + uint8_t readstatus = OB_RDP_LEVEL_0; + + if((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_2)) + { + readstatus = OB_RDP_LEVEL_2; + } + else if((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_0)) + { + readstatus = OB_RDP_LEVEL_0; + } + else + { + readstatus = OB_RDP_LEVEL_1; + } + + return readstatus; +} + +/** + * @brief Returns the FLASH BOR level. + * @retval uint8_t The FLASH BOR level: + * - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V + * - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V + * - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V + * - OB_BOR_OFF : Supply voltage ranges from 1.62 to 2.1 V + */ +static uint8_t FLASH_OB_GetBOR(void) +{ + /* Return the FLASH BOR level */ + return (uint8_t)(*(__IO uint8_t *)(OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0C); +} + +/** + * @brief Flush the instruction and data caches + * @retval None + */ +void FLASH_FlushCaches(void) +{ + /* Flush instruction cache */ + if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN)!= RESET) + { + /* Disable instruction cache */ + __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); + /* Reset instruction cache */ + __HAL_FLASH_INSTRUCTION_CACHE_RESET(); + /* Enable instruction cache */ + __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); + } + + /* Flush data cache */ + if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET) + { + /* Disable data cache */ + __HAL_FLASH_DATA_CACHE_DISABLE(); + /* Reset data cache */ + __HAL_FLASH_DATA_CACHE_RESET(); + /* Enable data cache */ + __HAL_FLASH_DATA_CACHE_ENABLE(); + } +} + +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c new file mode 100644 index 0000000..12db458 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c @@ -0,0 +1,175 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_flash_ramfunc.c + * @author MCD Application Team + * @brief FLASH RAMFUNC module driver. + * This file provides a FLASH firmware functions which should be + * executed from internal SRAM + * + Stop/Start the flash interface while System Run + * + Enable/Disable the flash sleep while System Run + @verbatim + ============================================================================== + ##### APIs executed from Internal RAM ##### + ============================================================================== + [..] + *** ARM Compiler *** + -------------------- + [..] RAM functions are defined using the toolchain options. + Functions that are be executed in RAM should reside in a separate + source module. Using the 'Options for File' dialog you can simply change + the 'Code / Const' area of a module to a memory space in physical RAM. + Available memory areas are declared in the 'Target' tab of the + Options for Target' dialog. + + *** ICCARM Compiler *** + ----------------------- + [..] RAM functions are defined using a specific toolchain keyword "__ramfunc". + + *** GNU Compiler *** + -------------------- + [..] RAM functions are defined using a specific toolchain attribute + "__attribute__((section(".RamFunc")))". + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup FLASH_RAMFUNC FLASH RAMFUNC + * @brief FLASH functions executed from RAM + * @{ + */ +#ifdef HAL_FLASH_MODULE_ENABLED +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ + defined(STM32F412Rx) || defined(STM32F412Cx) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH RAMFUNC Exported Functions + * @{ + */ + +/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions executed from internal RAM + * @brief Peripheral Extended features functions + * +@verbatim + + =============================================================================== + ##### ramfunc functions ##### + =============================================================================== + [..] + This subsection provides a set of functions that should be executed from RAM + transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Stop the flash interface while System Run + * @note This mode is only available for STM32F41xxx/STM32F446xx devices. + * @note This mode couldn't be set while executing with the flash itself. + * It should be done with specific routine executed from RAM. + * @retval HAL status + */ +__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StopFlashInterfaceClk(void) +{ + /* Enable Power ctrl clock */ + __HAL_RCC_PWR_CLK_ENABLE(); + /* Stop the flash interface while System Run */ + SET_BIT(PWR->CR, PWR_CR_FISSR); + + return HAL_OK; +} + +/** + * @brief Start the flash interface while System Run + * @note This mode is only available for STM32F411xx/STM32F446xx devices. + * @note This mode couldn't be set while executing with the flash itself. + * It should be done with specific routine executed from RAM. + * @retval HAL status + */ +__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StartFlashInterfaceClk(void) +{ + /* Enable Power ctrl clock */ + __HAL_RCC_PWR_CLK_ENABLE(); + /* Start the flash interface while System Run */ + CLEAR_BIT(PWR->CR, PWR_CR_FISSR); + + return HAL_OK; +} + +/** + * @brief Enable the flash sleep while System Run + * @note This mode is only available for STM32F41xxx/STM32F446xx devices. + * @note This mode could n't be set while executing with the flash itself. + * It should be done with specific routine executed from RAM. + * @retval HAL status + */ +__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableFlashSleepMode(void) +{ + /* Enable Power ctrl clock */ + __HAL_RCC_PWR_CLK_ENABLE(); + /* Enable the flash sleep while System Run */ + SET_BIT(PWR->CR, PWR_CR_FMSSR); + + return HAL_OK; +} + +/** + * @brief Disable the flash sleep while System Run + * @note This mode is only available for STM32F41xxx/STM32F446xx devices. + * @note This mode couldn't be set while executing with the flash itself. + * It should be done with specific routine executed from RAM. + * @retval HAL status + */ +__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableFlashSleepMode(void) +{ + /* Enable Power ctrl clock */ + __HAL_RCC_PWR_CLK_ENABLE(); + /* Disable the flash sleep while System Run */ + CLEAR_BIT(PWR->CR, PWR_CR_FMSSR); + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ +#endif /* HAL_FLASH_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c new file mode 100644 index 0000000..89090d6 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c @@ -0,0 +1,537 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_gpio.c + * @author MCD Application Team + * @brief GPIO HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (GPIO) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + @verbatim + ============================================================================== + ##### GPIO Peripheral features ##### + ============================================================================== + [..] + Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each + port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software + in several modes: + (+) Input mode + (+) Analog mode + (+) Output mode + (+) Alternate function mode + (+) External interrupt/event lines + + [..] + During and just after reset, the alternate functions and external interrupt + lines are not active and the I/O ports are configured in input floating mode. + + [..] + All GPIO pins have weak internal pull-up and pull-down resistors, which can be + activated or not. + + [..] + In Output or Alternate mode, each IO can be configured on open-drain or push-pull + type and the IO speed can be selected depending on the VDD value. + + [..] + All ports have external interrupt/event capability. To use external interrupt + lines, the port must be configured in input mode. All available GPIO pins are + connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. + + [..] + The external interrupt/event controller consists of up to 23 edge detectors + (16 lines are connected to GPIO) for generating event/interrupt requests (each + input line can be independently configured to select the type (interrupt or event) + and the corresponding trigger event (rising or falling or both). Each line can + also be masked independently. + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(). + + (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). + (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure + (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef + structure. + (++) In case of Output or alternate function mode selection: the speed is + configured through "Speed" member from GPIO_InitTypeDef structure. + (++) In alternate mode is selection, the alternate function connected to the IO + is configured through "Alternate" member from GPIO_InitTypeDef structure. + (++) Analog mode is required when a pin is to be used as ADC channel + or DAC output. + (++) In case of external interrupt/event selection the "Mode" member from + GPIO_InitTypeDef structure select the type (interrupt or event) and + the corresponding trigger event (rising or falling or both). + + (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority + mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using + HAL_NVIC_EnableIRQ(). + + (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). + + (#) To set/reset the level of a pin configured in output mode use + HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). + + (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). + + + (#) During and just after reset, the alternate functions are not + active and the GPIO pins are configured in input floating mode (except JTAG + pins). + + (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose + (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has + priority over the GPIO function. + + (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as + general purpose PH0 and PH1, respectively, when the HSE oscillator is off. + The HSE has priority over the GPIO function. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIO GPIO + * @brief GPIO HAL module driver + * @{ + */ + +#ifdef HAL_GPIO_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup GPIO_Private_Constants GPIO Private Constants + * @{ + */ +#define GPIO_MODE 0x00000003U +#define EXTI_MODE 0x10000000U +#define GPIO_MODE_IT 0x00010000U +#define GPIO_MODE_EVT 0x00020000U +#define RISING_EDGE 0x00100000U +#define FALLING_EDGE 0x00200000U +#define GPIO_OUTPUT_TYPE 0x00000010U + +#define GPIO_NUMBER 16U +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Functions GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to initialize and de-initialize the GPIOs + to be ready for use. + +@endverbatim + * @{ + */ + + +/** + * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init. + * @param GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or + * x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices. + * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + uint32_t position; + uint32_t ioposition = 0x00U; + uint32_t iocurrent = 0x00U; + uint32_t temp = 0x00U; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Configure the port pins */ + for(position = 0U; position < GPIO_NUMBER; position++) + { + /* Get the IO position */ + ioposition = 0x01U << position; + /* Get the current IO position */ + iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; + + if(iocurrent == ioposition) + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Output or Alternate function mode selection */ + if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || + (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + /* Configure the IO Speed */ + temp = GPIOx->OSPEEDR; + temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U)); + temp |= (GPIO_Init->Speed << (position * 2U)); + GPIOx->OSPEEDR = temp; + + /* Configure the IO Output Type */ + temp = GPIOx->OTYPER; + temp &= ~(GPIO_OTYPER_OT_0 << position) ; + temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position); + GPIOx->OTYPER = temp; + } + + /* Activate the Pull-up or Pull down resistor for the current IO */ + temp = GPIOx->PUPDR; + temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U)); + temp |= ((GPIO_Init->Pull) << (position * 2U)); + GPIOx->PUPDR = temp; + + /* In case of Alternate function mode selection */ + if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + { + /* Check the Alternate function parameter */ + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + /* Configure Alternate function mapped with the current IO */ + temp = GPIOx->AFR[position >> 3U]; + temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ; + temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U)); + GPIOx->AFR[position >> 3U] = temp; + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + temp &= ~(GPIO_MODER_MODER0 << (position * 2U)); + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); + GPIOx->MODER = temp; + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) + { + /* Enable SYSCFG Clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + temp = SYSCFG->EXTICR[position >> 2U]; + temp &= ~(0x0FU << (4U * (position & 0x03U))); + temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))); + SYSCFG->EXTICR[position >> 2U] = temp; + + /* Clear EXTI line configuration */ + temp = EXTI->IMR; + temp &= ~((uint32_t)iocurrent); + if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) + { + temp |= iocurrent; + } + EXTI->IMR = temp; + + temp = EXTI->EMR; + temp &= ~((uint32_t)iocurrent); + if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) + { + temp |= iocurrent; + } + EXTI->EMR = temp; + + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR; + temp &= ~((uint32_t)iocurrent); + if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) + { + temp |= iocurrent; + } + EXTI->RTSR = temp; + + temp = EXTI->FTSR; + temp &= ~((uint32_t)iocurrent); + if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) + { + temp |= iocurrent; + } + EXTI->FTSR = temp; + } + } + } +} + +/** + * @brief De-initializes the GPIOx peripheral registers to their default reset values. + * @param GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or + * x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices. + * @param GPIO_Pin specifies the port bit to be written. + * This parameter can be one of GPIO_PIN_x where x can be (0..15). + * @retval None + */ +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) +{ + uint32_t position; + uint32_t ioposition = 0x00U; + uint32_t iocurrent = 0x00U; + uint32_t tmp = 0x00U; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + + /* Configure the port pins */ + for(position = 0U; position < GPIO_NUMBER; position++) + { + /* Get the IO position */ + ioposition = 0x01U << position; + /* Get the current IO position */ + iocurrent = (GPIO_Pin) & ioposition; + + if(iocurrent == ioposition) + { + /*------------------------- EXTI Mode Configuration --------------------*/ + tmp = SYSCFG->EXTICR[position >> 2U]; + tmp &= (0x0FU << (4U * (position & 0x03U))); + if(tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)))) + { + /* Clear EXTI line configuration */ + EXTI->IMR &= ~((uint32_t)iocurrent); + EXTI->EMR &= ~((uint32_t)iocurrent); + + /* Clear Rising Falling edge configuration */ + EXTI->RTSR &= ~((uint32_t)iocurrent); + EXTI->FTSR &= ~((uint32_t)iocurrent); + + /* Configure the External Interrupt or event for the current IO */ + tmp = 0x0FU << (4U * (position & 0x03U)); + SYSCFG->EXTICR[position >> 2U] &= ~tmp; + } + + /*------------------------- GPIO Mode Configuration --------------------*/ + /* Configure IO Direction in Input Floating Mode */ + GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2U)); + + /* Configure the default Alternate Function in current IO */ + GPIOx->AFR[position >> 3U] &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ; + + /* Deactivate the Pull-up and Pull-down resistor for the current IO */ + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U)); + + /* Configure the default value IO Output Type */ + GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ; + + /* Configure the default value for IO Speed */ + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U)); + } + } +} + +/** + * @} + */ + +/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions + * @brief GPIO Read and Write + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Reads the specified input port pin. + * @param GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or + * x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices. + * @param GPIO_Pin specifies the port bit to read. + * This parameter can be GPIO_PIN_x where x can be (0..15). + * @retval The input port pin value. + */ +GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + GPIO_PinState bitstatus; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) + { + bitstatus = GPIO_PIN_SET; + } + else + { + bitstatus = GPIO_PIN_RESET; + } + return bitstatus; +} + +/** + * @brief Sets or clears the selected data port bit. + * + * @note This function uses GPIOx_BSRR register to allow atomic read/modify + * accesses. In this way, there is no risk of an IRQ occurring between + * the read and the modify access. + * + * @param GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or + * x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices. + * @param GPIO_Pin specifies the port bit to be written. + * This parameter can be one of GPIO_PIN_x where x can be (0..15). + * @param PinState specifies the value to be written to the selected bit. + * This parameter can be one of the GPIO_PinState enum values: + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if(PinState != GPIO_PIN_RESET) + { + GPIOx->BSRR = GPIO_Pin; + } + else + { + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; + } +} + +/** + * @brief Toggles the specified GPIO pins. + * @param GPIOx Where x can be (A..K) to select the GPIO peripheral for STM32F429X device or + * x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices. + * @param GPIO_Pin Specifies the pins to be toggled. + * @retval None + */ +void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->ODR & GPIO_Pin) == GPIO_Pin) + { + GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER; + } + else + { + GPIOx->BSRR = GPIO_Pin; + } +} + +/** + * @brief Locks GPIO Pins configuration registers. + * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, + * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. + * @note The configuration of the locked GPIO pins can no longer be modified + * until the next reset. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F4 family + * @param GPIO_Pin specifies the port bit to be locked. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). + * @retval None + */ +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + __IO uint32_t tmp = GPIO_LCKR_LCKK; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Apply lock key write sequence */ + tmp |= GPIO_Pin; + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ + GPIOx->LCKR = GPIO_Pin; + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Read LCKR register. This read is mandatory to complete key lock sequence */ + tmp = GPIOx->LCKR; + + /* Read again in order to confirm lock is active */ + if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET) + { + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief This function handles EXTI interrupt request. + * @param GPIO_Pin Specifies the pins connected EXTI line + * @retval None + */ +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) +{ + /* EXTI line interrupt detected */ + if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) + { + __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); + HAL_GPIO_EXTI_Callback(GPIO_Pin); + } +} + +/** + * @brief EXTI line detection callbacks. + * @param GPIO_Pin Specifies the pins connected EXTI line + * @retval None + */ +__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(GPIO_Pin); + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_GPIO_EXTI_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + + +/** + * @} + */ + +#endif /* HAL_GPIO_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.c new file mode 100644 index 0000000..f0ffd0b --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.c @@ -0,0 +1,1676 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_hcd.c + * @author MCD Application Team + * @brief HCD HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the USB Peripheral Controller: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#)Declare a HCD_HandleTypeDef handle structure, for example: + HCD_HandleTypeDef hhcd; + + (#)Fill parameters of Init structure in HCD handle + + (#)Call HAL_HCD_Init() API to initialize the HCD peripheral (Core, Host core, ...) + + (#)Initialize the HCD low level resources through the HAL_HCD_MspInit() API: + (##) Enable the HCD/USB Low Level interface clock using the following macros + (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); + (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode) + (+++) __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE(); (For High Speed Mode) + + (##) Initialize the related GPIO clocks + (##) Configure HCD pin-out + (##) Configure HCD NVIC interrupt + + (#)Associate the Upper USB Host stack to the HAL HCD Driver: + (##) hhcd.pData = phost; + + (#)Enable HCD transmission and reception: + (##) HAL_HCD_Start(); + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +#ifdef HAL_HCD_MODULE_ENABLED + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + +/** @defgroup HCD HCD + * @brief HCD HAL module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup HCD_Private_Functions HCD Private Functions + * @{ + */ +static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum); +static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum); +static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd); +static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup HCD_Exported_Functions HCD Exported Functions + * @{ + */ + +/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the host driver. + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd) +{ + USB_OTG_GlobalTypeDef *USBx; + + /* Check the HCD handle allocation */ + if (hhcd == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance)); + + USBx = hhcd->Instance; + + if (hhcd->State == HAL_HCD_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hhcd->Lock = HAL_UNLOCKED; + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->SOFCallback = HAL_HCD_SOF_Callback; + hhcd->ConnectCallback = HAL_HCD_Connect_Callback; + hhcd->DisconnectCallback = HAL_HCD_Disconnect_Callback; + hhcd->PortEnabledCallback = HAL_HCD_PortEnabled_Callback; + hhcd->PortDisabledCallback = HAL_HCD_PortDisabled_Callback; + hhcd->HC_NotifyURBChangeCallback = HAL_HCD_HC_NotifyURBChange_Callback; + + if (hhcd->MspInitCallback == NULL) + { + hhcd->MspInitCallback = HAL_HCD_MspInit; + } + + /* Init the low level hardware */ + hhcd->MspInitCallback(hhcd); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_HCD_MspInit(hhcd); +#endif /* (USE_HAL_HCD_REGISTER_CALLBACKS) */ + } + + hhcd->State = HAL_HCD_STATE_BUSY; + + /* Disable DMA mode for FS instance */ + if ((USBx->CID & (0x1U << 8)) == 0U) + { + hhcd->Init.dma_enable = 0U; + } + + /* Disable the Interrupts */ + __HAL_HCD_DISABLE(hhcd); + + /* Init the Core (common init.) */ + (void)USB_CoreInit(hhcd->Instance, hhcd->Init); + + /* Force Host Mode*/ + (void)USB_SetCurrentMode(hhcd->Instance, USB_HOST_MODE); + + /* Init Host */ + (void)USB_HostInit(hhcd->Instance, hhcd->Init); + + hhcd->State = HAL_HCD_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Initialize a host channel. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @param epnum Endpoint number. + * This parameter can be a value from 1 to 15 + * @param dev_address Current device address + * This parameter can be a value from 0 to 255 + * @param speed Current device speed. + * This parameter can be one of these values: + * HCD_SPEED_HIGH: High speed mode, + * HCD_SPEED_FULL: Full speed mode, + * HCD_SPEED_LOW: Low speed mode + * @param ep_type Endpoint Type. + * This parameter can be one of these values: + * EP_TYPE_CTRL: Control type, + * EP_TYPE_ISOC: Isochronous type, + * EP_TYPE_BULK: Bulk type, + * EP_TYPE_INTR: Interrupt type + * @param mps Max Packet Size. + * This parameter can be a value from 0 to32K + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, + uint8_t ch_num, + uint8_t epnum, + uint8_t dev_address, + uint8_t speed, + uint8_t ep_type, + uint16_t mps) +{ + HAL_StatusTypeDef status; + + __HAL_LOCK(hhcd); + hhcd->hc[ch_num].do_ping = 0U; + hhcd->hc[ch_num].dev_addr = dev_address; + hhcd->hc[ch_num].max_packet = mps; + hhcd->hc[ch_num].ch_num = ch_num; + hhcd->hc[ch_num].ep_type = ep_type; + hhcd->hc[ch_num].ep_num = epnum & 0x7FU; + + if ((epnum & 0x80U) == 0x80U) + { + hhcd->hc[ch_num].ep_is_in = 1U; + } + else + { + hhcd->hc[ch_num].ep_is_in = 0U; + } + + hhcd->hc[ch_num].speed = speed; + + status = USB_HC_Init(hhcd->Instance, + ch_num, + epnum, + dev_address, + speed, + ep_type, + mps); + __HAL_UNLOCK(hhcd); + + return status; +} + +/** + * @brief Halt a host channel. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num) +{ + HAL_StatusTypeDef status = HAL_OK; + + __HAL_LOCK(hhcd); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_UNLOCK(hhcd); + + return status; +} + +/** + * @brief DeInitialize the host driver. + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd) +{ + /* Check the HCD handle allocation */ + if (hhcd == NULL) + { + return HAL_ERROR; + } + + hhcd->State = HAL_HCD_STATE_BUSY; + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + if (hhcd->MspDeInitCallback == NULL) + { + hhcd->MspDeInitCallback = HAL_HCD_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware */ + hhcd->MspDeInitCallback(hhcd); +#else + /* DeInit the low level hardware: CLOCK, NVIC.*/ + HAL_HCD_MspDeInit(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + + __HAL_HCD_DISABLE(hhcd); + + hhcd->State = HAL_HCD_STATE_RESET; + + return HAL_OK; +} + +/** + * @brief Initialize the HCD MSP. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitialize the HCD MSP. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup HCD_Exported_Functions_Group2 Input and Output operation functions + * @brief HCD IO operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to manage the USB Host Data + Transfer + +@endverbatim + * @{ + */ + +/** + * @brief Submit a new URB for processing. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @param direction Channel number. + * This parameter can be one of these values: + * 0 : Output / 1 : Input + * @param ep_type Endpoint Type. + * This parameter can be one of these values: + * EP_TYPE_CTRL: Control type/ + * EP_TYPE_ISOC: Isochronous type/ + * EP_TYPE_BULK: Bulk type/ + * EP_TYPE_INTR: Interrupt type/ + * @param token Endpoint Type. + * This parameter can be one of these values: + * 0: HC_PID_SETUP / 1: HC_PID_DATA1 + * @param pbuff pointer to URB data + * @param length Length of URB data + * @param do_ping activate do ping protocol (for high speed only). + * This parameter can be one of these values: + * 0 : do ping inactive / 1 : do ping active + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, + uint8_t ch_num, + uint8_t direction, + uint8_t ep_type, + uint8_t token, + uint8_t *pbuff, + uint16_t length, + uint8_t do_ping) +{ + hhcd->hc[ch_num].ep_is_in = direction; + hhcd->hc[ch_num].ep_type = ep_type; + + if (token == 0U) + { + hhcd->hc[ch_num].data_pid = HC_PID_SETUP; + hhcd->hc[ch_num].do_ping = do_ping; + } + else + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + + /* Manage Data Toggle */ + switch (ep_type) + { + case EP_TYPE_CTRL: + if ((token == 1U) && (direction == 0U)) /*send data */ + { + if (length == 0U) + { + /* For Status OUT stage, Length==0, Status Out PID = 1 */ + hhcd->hc[ch_num].toggle_out = 1U; + } + + /* Set the Data Toggle bit as per the Flag */ + if (hhcd->hc[ch_num].toggle_out == 0U) + { + /* Put the PID 0 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + /* Put the PID 1 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + } + break; + + case EP_TYPE_BULK: + if (direction == 0U) + { + /* Set the Data Toggle bit as per the Flag */ + if (hhcd->hc[ch_num].toggle_out == 0U) + { + /* Put the PID 0 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + /* Put the PID 1 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + } + else + { + if (hhcd->hc[ch_num].toggle_in == 0U) + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + } + + break; + case EP_TYPE_INTR: + if (direction == 0U) + { + /* Set the Data Toggle bit as per the Flag */ + if (hhcd->hc[ch_num].toggle_out == 0U) + { + /* Put the PID 0 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + /* Put the PID 1 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + } + else + { + if (hhcd->hc[ch_num].toggle_in == 0U) + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + } + break; + + case EP_TYPE_ISOC: + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + break; + + default: + break; + } + + hhcd->hc[ch_num].xfer_buff = pbuff; + hhcd->hc[ch_num].xfer_len = length; + hhcd->hc[ch_num].urb_state = URB_IDLE; + hhcd->hc[ch_num].xfer_count = 0U; + hhcd->hc[ch_num].ch_num = ch_num; + hhcd->hc[ch_num].state = HC_IDLE; + + return USB_HC_StartXfer(hhcd->Instance, &hhcd->hc[ch_num], (uint8_t)hhcd->Init.dma_enable); +} + +/** + * @brief Handle HCD interrupt request. + * @param hhcd HCD handle + * @retval None + */ +void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) +{ + USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t i, interrupt; + + /* Ensure that we are in device mode */ + if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST) + { + /* Avoid spurious interrupt */ + if (__HAL_HCD_IS_INVALID_INTERRUPT(hhcd)) + { + return; + } + + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) + { + /* Incorrect mode, acknowledge the interrupt */ + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); + } + + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR)) + { + /* Incorrect mode, acknowledge the interrupt */ + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR); + } + + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE)) + { + /* Incorrect mode, acknowledge the interrupt */ + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE); + } + + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS)) + { + /* Incorrect mode, acknowledge the interrupt */ + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_MMIS); + } + + /* Handle Host Disconnect Interrupts */ + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT)) + { + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT); + + if ((USBx_HPRT0 & USB_OTG_HPRT_PCSTS) == 0U) + { + /* Handle Host Port Disconnect Interrupt */ +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->DisconnectCallback(hhcd); +#else + HAL_HCD_Disconnect_Callback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + + (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ); + } + } + + /* Handle Host Port Interrupts */ + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HPRTINT)) + { + HCD_Port_IRQHandler(hhcd); + } + + /* Handle Host SOF Interrupt */ + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_SOF)) + { +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->SOFCallback(hhcd); +#else + HAL_HCD_SOF_Callback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF); + } + + /* Handle Host channel Interrupt */ + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT)) + { + interrupt = USB_HC_ReadInterrupt(hhcd->Instance); + for (i = 0U; i < hhcd->Init.Host_channels; i++) + { + if ((interrupt & (1UL << (i & 0xFU))) != 0U) + { + if ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_EPDIR) == USB_OTG_HCCHAR_EPDIR) + { + HCD_HC_IN_IRQHandler(hhcd, (uint8_t)i); + } + else + { + HCD_HC_OUT_IRQHandler(hhcd, (uint8_t)i); + } + } + } + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT); + } + + /* Handle Rx Queue Level Interrupts */ + if ((__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) != 0U) + { + USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); + + HCD_RXQLVL_IRQHandler(hhcd); + + USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); + } + } +} + + +/** + * @brief Handles HCD Wakeup interrupt request. + * @param hhcd HCD handle + * @retval HAL status + */ +void HAL_HCD_WKUP_IRQHandler(HCD_HandleTypeDef *hhcd) +{ + UNUSED(hhcd); +} + + +/** + * @brief SOF callback. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_SOF_Callback could be implemented in the user file + */ +} + +/** + * @brief Connection Event callback. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_Connect_Callback could be implemented in the user file + */ +} + +/** + * @brief Disconnection Event callback. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_Disconnect_Callback could be implemented in the user file + */ +} + +/** + * @brief Port Enabled Event callback. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_Disconnect_Callback could be implemented in the user file + */ +} + +/** + * @brief Port Disabled Event callback. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_Disconnect_Callback could be implemented in the user file + */ +} + +/** + * @brief Notify URB state change callback. + * @param hhcd HCD handle + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @param urb_state: + * This parameter can be one of these values: + * URB_IDLE/ + * URB_DONE/ + * URB_NOTREADY/ + * URB_NYET/ + * URB_ERROR/ + * URB_STALL/ + * @retval None + */ +__weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + UNUSED(chnum); + UNUSED(urb_state); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_HC_NotifyURBChange_Callback could be implemented in the user file + */ +} + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) +/** + * @brief Register a User USB HCD Callback + * To be used instead of the weak predefined callback + * @param hhcd USB HCD handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_HCD_SOF_CB_ID USB HCD SOF callback ID + * @arg @ref HAL_HCD_CONNECT_CB_ID USB HCD Connect callback ID + * @arg @ref HAL_HCD_DISCONNECT_CB_ID OTG HCD Disconnect callback ID + * @arg @ref HAL_HCD_PORT_ENABLED_CB_ID USB HCD Port Enable callback ID + * @arg @ref HAL_HCD_PORT_DISABLED_CB_ID USB HCD Port Disable callback ID + * @arg @ref HAL_HCD_MSPINIT_CB_ID MspDeInit callback ID + * @arg @ref HAL_HCD_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, + HAL_HCD_CallbackIDTypeDef CallbackID, + pHCD_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hhcd); + + if (hhcd->State == HAL_HCD_STATE_READY) + { + switch (CallbackID) + { + case HAL_HCD_SOF_CB_ID : + hhcd->SOFCallback = pCallback; + break; + + case HAL_HCD_CONNECT_CB_ID : + hhcd->ConnectCallback = pCallback; + break; + + case HAL_HCD_DISCONNECT_CB_ID : + hhcd->DisconnectCallback = pCallback; + break; + + case HAL_HCD_PORT_ENABLED_CB_ID : + hhcd->PortEnabledCallback = pCallback; + break; + + case HAL_HCD_PORT_DISABLED_CB_ID : + hhcd->PortDisabledCallback = pCallback; + break; + + case HAL_HCD_MSPINIT_CB_ID : + hhcd->MspInitCallback = pCallback; + break; + + case HAL_HCD_MSPDEINIT_CB_ID : + hhcd->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hhcd->State == HAL_HCD_STATE_RESET) + { + switch (CallbackID) + { + case HAL_HCD_MSPINIT_CB_ID : + hhcd->MspInitCallback = pCallback; + break; + + case HAL_HCD_MSPDEINIT_CB_ID : + hhcd->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hhcd); + return status; +} + +/** + * @brief Unregister an USB HCD Callback + * USB HCD callback is redirected to the weak predefined callback + * @param hhcd USB HCD handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_HCD_SOF_CB_ID USB HCD SOF callback ID + * @arg @ref HAL_HCD_CONNECT_CB_ID USB HCD Connect callback ID + * @arg @ref HAL_HCD_DISCONNECT_CB_ID OTG HCD Disconnect callback ID + * @arg @ref HAL_HCD_PORT_ENABLED_CB_ID USB HCD Port Enabled callback ID + * @arg @ref HAL_HCD_PORT_DISABLED_CB_ID USB HCD Port Disabled callback ID + * @arg @ref HAL_HCD_MSPINIT_CB_ID MspDeInit callback ID + * @arg @ref HAL_HCD_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hhcd); + + /* Setup Legacy weak Callbacks */ + if (hhcd->State == HAL_HCD_STATE_READY) + { + switch (CallbackID) + { + case HAL_HCD_SOF_CB_ID : + hhcd->SOFCallback = HAL_HCD_SOF_Callback; + break; + + case HAL_HCD_CONNECT_CB_ID : + hhcd->ConnectCallback = HAL_HCD_Connect_Callback; + break; + + case HAL_HCD_DISCONNECT_CB_ID : + hhcd->DisconnectCallback = HAL_HCD_Disconnect_Callback; + break; + + case HAL_HCD_PORT_ENABLED_CB_ID : + hhcd->PortEnabledCallback = HAL_HCD_PortEnabled_Callback; + break; + + case HAL_HCD_PORT_DISABLED_CB_ID : + hhcd->PortDisabledCallback = HAL_HCD_PortDisabled_Callback; + break; + + case HAL_HCD_MSPINIT_CB_ID : + hhcd->MspInitCallback = HAL_HCD_MspInit; + break; + + case HAL_HCD_MSPDEINIT_CB_ID : + hhcd->MspDeInitCallback = HAL_HCD_MspDeInit; + break; + + default : + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hhcd->State == HAL_HCD_STATE_RESET) + { + switch (CallbackID) + { + case HAL_HCD_MSPINIT_CB_ID : + hhcd->MspInitCallback = HAL_HCD_MspInit; + break; + + case HAL_HCD_MSPDEINIT_CB_ID : + hhcd->MspDeInitCallback = HAL_HCD_MspDeInit; + break; + + default : + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hhcd); + return status; +} + +/** + * @brief Register USB HCD Host Channel Notify URB Change Callback + * To be used instead of the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback + * @param hhcd HCD handle + * @param pCallback pointer to the USB HCD Host Channel Notify URB Change Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd, + pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hhcd); + + if (hhcd->State == HAL_HCD_STATE_READY) + { + hhcd->HC_NotifyURBChangeCallback = pCallback; + } + else + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hhcd); + + return status; +} + +/** + * @brief Unregister the USB HCD Host Channel Notify URB Change Callback + * USB HCD Host Channel Notify URB Change Callback is redirected to the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hhcd); + + if (hhcd->State == HAL_HCD_STATE_READY) + { + hhcd->HC_NotifyURBChangeCallback = HAL_HCD_HC_NotifyURBChange_Callback; /* Legacy weak DataOutStageCallback */ + } + else + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hhcd); + + return status; +} +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions + * @brief Management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the HCD data + transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Start the host driver. + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd) +{ + __HAL_LOCK(hhcd); + __HAL_HCD_ENABLE(hhcd); + (void)USB_DriveVbus(hhcd->Instance, 1U); + __HAL_UNLOCK(hhcd); + + return HAL_OK; +} + +/** + * @brief Stop the host driver. + * @param hhcd HCD handle + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd) +{ + __HAL_LOCK(hhcd); + (void)USB_StopHost(hhcd->Instance); + __HAL_UNLOCK(hhcd); + + return HAL_OK; +} + +/** + * @brief Reset the host port. + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd) +{ + return (USB_ResetPort(hhcd->Instance)); +} + +/** + * @} + */ + +/** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the HCD handle state. + * @param hhcd HCD handle + * @retval HAL state + */ +HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd) +{ + return hhcd->State; +} + +/** + * @brief Return URB state for a channel. + * @param hhcd HCD handle + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @retval URB state. + * This parameter can be one of these values: + * URB_IDLE/ + * URB_DONE/ + * URB_NOTREADY/ + * URB_NYET/ + * URB_ERROR/ + * URB_STALL + */ +HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum) +{ + return hhcd->hc[chnum].urb_state; +} + + +/** + * @brief Return the last host transfer size. + * @param hhcd HCD handle + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @retval last transfer size in byte + */ +uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum) +{ + return hhcd->hc[chnum].xfer_count; +} + +/** + * @brief Return the Host Channel state. + * @param hhcd HCD handle + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @retval Host channel state + * This parameter can be one of these values: + * HC_IDLE/ + * HC_XFRC/ + * HC_HALTED/ + * HC_NYET/ + * HC_NAK/ + * HC_STALL/ + * HC_XACTERR/ + * HC_BBLERR/ + * HC_DATATGLERR + */ +HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum) +{ + return hhcd->hc[chnum].state; +} + +/** + * @brief Return the current Host frame number. + * @param hhcd HCD handle + * @retval Current Host frame number + */ +uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd) +{ + return (USB_GetCurrentFrame(hhcd->Instance)); +} + +/** + * @brief Return the Host enumeration speed. + * @param hhcd HCD handle + * @retval Enumeration speed + */ +uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd) +{ + return (USB_GetHostSpeed(hhcd->Instance)); +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup HCD_Private_Functions + * @{ + */ +/** + * @brief Handle Host Channel IN interrupt requests. + * @param hhcd HCD handle + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @retval none + */ +static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) +{ + USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t ch_num = (uint32_t)chnum; + + uint32_t tmpreg; + + if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR) + { + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR); + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_BBERR) == USB_OTG_HCINT_BBERR) + { + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_BBERR); + hhcd->hc[ch_num].state = HC_BBLERR; + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK) + { + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_ACK); + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL) + { + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + hhcd->hc[ch_num].state = HC_STALL; + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR) + { + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); + hhcd->hc[ch_num].state = HC_DATATGLERR; + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR); + } + else + { + /* ... */ + } + + if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR) + { + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR); + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC) + { + if (hhcd->Init.dma_enable != 0U) + { + hhcd->hc[ch_num].xfer_count = hhcd->hc[ch_num].xfer_len - \ + (USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ); + } + + hhcd->hc[ch_num].state = HC_XFRC; + hhcd->hc[ch_num].ErrCnt = 0U; + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC); + + if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[ch_num].ep_type == EP_TYPE_BULK)) + { + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); + } + else if (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR) + { + USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM; + hhcd->hc[ch_num].urb_state = URB_DONE; + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); +#else + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + else if (hhcd->hc[ch_num].ep_type == EP_TYPE_ISOC) + { + hhcd->hc[ch_num].urb_state = URB_DONE; + hhcd->hc[ch_num].toggle_in ^= 1U; + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); +#else + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + else + { + /* ... */ + } + hhcd->hc[ch_num].toggle_in ^= 1U; + + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH) + { + __HAL_HCD_MASK_HALT_HC_INT(ch_num); + + if (hhcd->hc[ch_num].state == HC_XFRC) + { + hhcd->hc[ch_num].urb_state = URB_DONE; + } + else if (hhcd->hc[ch_num].state == HC_STALL) + { + hhcd->hc[ch_num].urb_state = URB_STALL; + } + else if ((hhcd->hc[ch_num].state == HC_XACTERR) || + (hhcd->hc[ch_num].state == HC_DATATGLERR)) + { + hhcd->hc[ch_num].ErrCnt++; + if (hhcd->hc[ch_num].ErrCnt > 3U) + { + hhcd->hc[ch_num].ErrCnt = 0U; + hhcd->hc[ch_num].urb_state = URB_ERROR; + } + else + { + hhcd->hc[ch_num].urb_state = URB_NOTREADY; + } + + /* re-activate the channel */ + tmpreg = USBx_HC(ch_num)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(ch_num)->HCCHAR = tmpreg; + } + else if (hhcd->hc[ch_num].state == HC_NAK) + { + hhcd->hc[ch_num].urb_state = URB_NOTREADY; + /* re-activate the channel */ + tmpreg = USBx_HC(ch_num)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(ch_num)->HCCHAR = tmpreg; + } + else if (hhcd->hc[ch_num].state == HC_BBLERR) + { + hhcd->hc[ch_num].ErrCnt++; + hhcd->hc[ch_num].urb_state = URB_ERROR; + } + else + { + /* ... */ + } + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH); + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR) + { + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + hhcd->hc[ch_num].ErrCnt++; + hhcd->hc[ch_num].state = HC_XACTERR; + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR); + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK) + { + if (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR) + { + hhcd->hc[ch_num].ErrCnt = 0U; + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + } + else if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[ch_num].ep_type == EP_TYPE_BULK)) + { + hhcd->hc[ch_num].ErrCnt = 0U; + + if (hhcd->Init.dma_enable == 0U) + { + hhcd->hc[ch_num].state = HC_NAK; + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + } + } + else + { + /* ... */ + } + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); + } + else + { + /* ... */ + } +} + +/** + * @brief Handle Host Channel OUT interrupt requests. + * @param hhcd HCD handle + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @retval none + */ +static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) +{ + USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t ch_num = (uint32_t)chnum; + uint32_t tmpreg; + + if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR) + { + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR); + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK) + { + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_ACK); + + if (hhcd->hc[ch_num].do_ping == 1U) + { + hhcd->hc[ch_num].do_ping = 0U; + hhcd->hc[ch_num].urb_state = URB_NOTREADY; + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + } + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NYET) == USB_OTG_HCINT_NYET) + { + hhcd->hc[ch_num].state = HC_NYET; + hhcd->hc[ch_num].do_ping = 1U; + hhcd->hc[ch_num].ErrCnt = 0U; + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET); + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR) + { + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR); + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC) + { + hhcd->hc[ch_num].ErrCnt = 0U; + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC); + hhcd->hc[ch_num].state = HC_XFRC; + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL) + { + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL); + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + hhcd->hc[ch_num].state = HC_STALL; + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK) + { + hhcd->hc[ch_num].ErrCnt = 0U; + hhcd->hc[ch_num].state = HC_NAK; + + if (hhcd->hc[ch_num].do_ping == 0U) + { + if (hhcd->hc[ch_num].speed == HCD_SPEED_HIGH) + { + hhcd->hc[ch_num].do_ping = 1U; + } + } + + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR) + { + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + hhcd->hc[ch_num].state = HC_XACTERR; + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR); + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR) + { + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR); + hhcd->hc[ch_num].state = HC_DATATGLERR; + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH) + { + __HAL_HCD_MASK_HALT_HC_INT(ch_num); + + if (hhcd->hc[ch_num].state == HC_XFRC) + { + hhcd->hc[ch_num].urb_state = URB_DONE; + if ((hhcd->hc[ch_num].ep_type == EP_TYPE_BULK) || + (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR)) + { + hhcd->hc[ch_num].toggle_out ^= 1U; + } + } + else if (hhcd->hc[ch_num].state == HC_NAK) + { + hhcd->hc[ch_num].urb_state = URB_NOTREADY; + } + else if (hhcd->hc[ch_num].state == HC_NYET) + { + hhcd->hc[ch_num].urb_state = URB_NOTREADY; + } + else if (hhcd->hc[ch_num].state == HC_STALL) + { + hhcd->hc[ch_num].urb_state = URB_STALL; + } + else if ((hhcd->hc[ch_num].state == HC_XACTERR) || + (hhcd->hc[ch_num].state == HC_DATATGLERR)) + { + hhcd->hc[ch_num].ErrCnt++; + if (hhcd->hc[ch_num].ErrCnt > 3U) + { + hhcd->hc[ch_num].ErrCnt = 0U; + hhcd->hc[ch_num].urb_state = URB_ERROR; + } + else + { + hhcd->hc[ch_num].urb_state = URB_NOTREADY; + } + + /* re-activate the channel */ + tmpreg = USBx_HC(ch_num)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(ch_num)->HCCHAR = tmpreg; + } + else + { + /* ... */ + } + + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH); + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); + } + else + { + /* ... */ + } +} + +/** + * @brief Handle Rx Queue Level interrupt requests. + * @param hhcd HCD handle + * @retval none + */ +static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd) +{ + USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t pktsts; + uint32_t pktcnt; + uint32_t temp; + uint32_t tmpreg; + uint32_t ch_num; + + temp = hhcd->Instance->GRXSTSP; + ch_num = temp & USB_OTG_GRXSTSP_EPNUM; + pktsts = (temp & USB_OTG_GRXSTSP_PKTSTS) >> 17; + pktcnt = (temp & USB_OTG_GRXSTSP_BCNT) >> 4; + + switch (pktsts) + { + case GRXSTS_PKTSTS_IN: + /* Read the data into the host buffer. */ + if ((pktcnt > 0U) && (hhcd->hc[ch_num].xfer_buff != (void *)0)) + { + (void)USB_ReadPacket(hhcd->Instance, hhcd->hc[ch_num].xfer_buff, (uint16_t)pktcnt); + + /*manage multiple Xfer */ + hhcd->hc[ch_num].xfer_buff += pktcnt; + hhcd->hc[ch_num].xfer_count += pktcnt; + + if ((USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0U) + { + /* re-activate the channel when more packets are expected */ + tmpreg = USBx_HC(ch_num)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(ch_num)->HCCHAR = tmpreg; + hhcd->hc[ch_num].toggle_in ^= 1U; + } + } + break; + + case GRXSTS_PKTSTS_DATA_TOGGLE_ERR: + break; + + case GRXSTS_PKTSTS_IN_XFER_COMP: + case GRXSTS_PKTSTS_CH_HALTED: + default: + break; + } +} + +/** + * @brief Handle Host Port interrupt requests. + * @param hhcd HCD handle + * @retval None + */ +static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) +{ + USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + __IO uint32_t hprt0, hprt0_dup; + + /* Handle Host Port Interrupts */ + hprt0 = USBx_HPRT0; + hprt0_dup = USBx_HPRT0; + + hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | \ + USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); + + /* Check whether Port Connect detected */ + if ((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET) + { + if ((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS) + { +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->ConnectCallback(hhcd); +#else + HAL_HCD_Connect_Callback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + hprt0_dup |= USB_OTG_HPRT_PCDET; + } + + /* Check whether Port Enable Changed */ + if ((hprt0 & USB_OTG_HPRT_PENCHNG) == USB_OTG_HPRT_PENCHNG) + { + hprt0_dup |= USB_OTG_HPRT_PENCHNG; + + if ((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA) + { + if (hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY) + { + if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17)) + { + (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_6_MHZ); + } + else + { + (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ); + } + } + else + { + if (hhcd->Init.speed == HCD_SPEED_FULL) + { + USBx_HOST->HFIR = 60000U; + } + } +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->PortEnabledCallback(hhcd); +#else + HAL_HCD_PortEnabled_Callback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + + } + else + { +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->PortDisabledCallback(hhcd); +#else + HAL_HCD_PortDisabled_Callback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + } + + /* Check for an overcurrent */ + if ((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG) + { + hprt0_dup |= USB_OTG_HPRT_POCCHNG; + } + + /* Clear Port Interrupts */ + USBx_HPRT0 = hprt0_dup; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +#endif /* HAL_HCD_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c new file mode 100644 index 0000000..3fb6c3c --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c @@ -0,0 +1,7338 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_i2c.c + * @author MCD Application Team + * @brief I2C HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Inter Integrated Circuit (I2C) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State, Mode and Error functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The I2C HAL driver can be used as follows: + + (#) Declare a I2C_HandleTypeDef handle structure, for example: + I2C_HandleTypeDef hi2c; + + (#)Initialize the I2C low level resources by implementing the @ref HAL_I2C_MspInit() API: + (##) Enable the I2Cx interface clock + (##) I2C pins configuration + (+++) Enable the clock for the I2C GPIOs + (+++) Configure I2C pins as alternate function open-drain + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the I2Cx interrupt priority + (+++) Enable the NVIC I2C IRQ Channel + (##) DMA Configuration if you need to use DMA process + (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream + (+++) Enable the DMAx interface clock using + (+++) Configure the DMA handle parameters + (+++) Configure the DMA Tx or Rx stream + (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on + the DMA Tx or Rx stream + + (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1, + Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure. + + (#) Initialize the I2C registers by calling the @ref HAL_I2C_Init(), configures also the low level Hardware + (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_I2C_MspInit() API. + + (#) To check if target device is ready for communication, use the function @ref HAL_I2C_IsDeviceReady() + + (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Transmit in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Transmit() + (+) Receive in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Receive() + (+) Transmit in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Transmit() + (+) Receive in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Receive() + + *** Polling mode IO MEM operation *** + ===================================== + [..] + (+) Write an amount of data in blocking mode to a specific memory address using @ref HAL_I2C_Mem_Write() + (+) Read an amount of data in blocking mode from a specific memory address using @ref HAL_I2C_Mem_Read() + + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Transmit in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Transmit_IT() + (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Receive_IT() + (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Transmit_IT() + (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Receive_IT() + (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() + (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() + + *** Interrupt mode or DMA mode IO sequential operation *** + ========================================================== + [..] + (@) These interfaces allow to manage a sequential transfer with a repeated start condition + when a direction change during transfer + [..] + (+) A specific option field manage the different steps of a sequential transfer + (+) Option field values are defined through @ref I2C_XferOptions_definition and are listed below: + (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode + (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address + and data to transfer without a final stop condition + (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address + and data to transfer without a final stop condition, an then permit a call the same master sequential interface + several times (like @ref HAL_I2C_Master_Seq_Transmit_IT() then @ref HAL_I2C_Master_Seq_Transmit_IT() + or @ref HAL_I2C_Master_Seq_Transmit_DMA() then @ref HAL_I2C_Master_Seq_Transmit_DMA()) + (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to transfer + if no direction change and without a final stop condition in both cases + (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to transfer + if no direction change and with a final stop condition in both cases + (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential + interface several times (link with option I2C_FIRST_AND_NEXT_FRAME). + Usage can, transfer several bytes one by one using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) + or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) + or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) + or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME). + Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the oposite interface Receive or Transmit + without stopping the communication and so generate a restart condition. + (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential + interface. + Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) + or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) + or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) + or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME). + Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition. + + (+) Differents sequential I2C interfaces are listed below: + (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Transmit_IT() + or using @ref HAL_I2C_Master_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() + (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Receive_IT() + or using @ref HAL_I2C_Master_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() + (++) Abort a master IT or DMA I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() + (+++) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() + (++) Enable/disable the Address listen mode in slave I2C mode using @ref HAL_I2C_EnableListen_IT() @ref HAL_I2C_DisableListen_IT() + (+++) When address slave I2C match, @ref HAL_I2C_AddrCallback() is executed and user can + add his own code to check the Address Match Code and the transmission direction request by master (Write/Read). + (+++) At Listen mode end @ref HAL_I2C_ListenCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_ListenCpltCallback() + (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Transmit_IT() + or using @ref HAL_I2C_Slave_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() + (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Receive_IT() + or using @ref HAL_I2C_Slave_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() + (++) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + + *** Interrupt mode IO MEM operation *** + ======================================= + [..] + (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using + @ref HAL_I2C_Mem_Write_IT() + (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback() + (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using + @ref HAL_I2C_Mem_Read_IT() + (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + + *** DMA mode IO operation *** + ============================== + [..] + (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using + @ref HAL_I2C_Master_Transmit_DMA() + (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode (DMA) using + @ref HAL_I2C_Master_Receive_DMA() + (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using + @ref HAL_I2C_Slave_Transmit_DMA() + (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using + @ref HAL_I2C_Slave_Receive_DMA() + (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() + (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() + + *** DMA mode IO MEM operation *** + ================================= + [..] + (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using + @ref HAL_I2C_Mem_Write_DMA() + (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback() + (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using + @ref HAL_I2C_Mem_Read_DMA() + (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + + + *** I2C HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in I2C HAL driver. + + (+) @ref __HAL_I2C_ENABLE: Enable the I2C peripheral + (+) @ref __HAL_I2C_DISABLE: Disable the I2C peripheral + (+) @ref __HAL_I2C_GET_FLAG: Checks whether the specified I2C flag is set or not + (+) @ref __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag + (+) @ref __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt + (+) @ref __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt + + *** Callback registration *** + ============================================= + [..] + The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback() + to register an interrupt callback. + [..] + Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks: + (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + (+) MasterRxCpltCallback : callback for Master reception end of transfer. + (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + (+) ListenCpltCallback : callback for end of listen mode. + (+) MemTxCpltCallback : callback for Memory transmission end of transfer. + (+) MemRxCpltCallback : callback for Memory reception end of transfer. + (+) ErrorCallback : callback for error detection. + (+) AbortCpltCallback : callback for abort completion process. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + [..] + For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback(). + [..] + Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default + weak function. + @ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + (+) MasterRxCpltCallback : callback for Master reception end of transfer. + (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + (+) ListenCpltCallback : callback for end of listen mode. + (+) MemTxCpltCallback : callback for Memory transmission end of transfer. + (+) MemRxCpltCallback : callback for Memory reception end of transfer. + (+) ErrorCallback : callback for error detection. + (+) AbortCpltCallback : callback for abort completion process. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + [..] + For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback(). + [..] + By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() only when + these callbacks are null (not registered beforehand). + If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + [..] + Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + Then, the user first registers the MspInit/MspDeInit user callbacks + using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit() + or @ref HAL_I2C_Init() function. + [..] + When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + + + [..] + (@) You can refer to the I2C HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup I2C I2C + * @brief I2C HAL module driver + * @{ + */ + +#ifdef HAL_I2C_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup I2C_Private_Define + * @{ + */ +#define I2C_TIMEOUT_FLAG 35U /*!< Timeout 35 ms */ +#define I2C_TIMEOUT_BUSY_FLAG 25U /*!< Timeout 25 ms */ +#define I2C_TIMEOUT_STOP_FLAG 5U /*!< Timeout 5 ms */ +#define I2C_NO_OPTION_FRAME 0xFFFF0000U /*!< XferOptions default value */ + +/* Private define for @ref PreviousState usage */ +#define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */ +#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */ +#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/** @defgroup I2C_Private_Functions I2C Private Functions + * @{ + */ +/* Private functions to handle DMA transfer */ +static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMAError(DMA_HandleTypeDef *hdma); +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); + +static void I2C_ITError(I2C_HandleTypeDef *hi2c); + +static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); + +/* Private functions to handle flags during polling transfer */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnSTOPRequestThroughIT(I2C_HandleTypeDef *hi2c); +static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c); + +/* Private functions for I2C transfer IRQ handler */ +static void I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c); +static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c); +static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c); +static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c); +static void I2C_Master_SB(I2C_HandleTypeDef *hi2c); +static void I2C_Master_ADD10(I2C_HandleTypeDef *hi2c); +static void I2C_Master_ADDR(I2C_HandleTypeDef *hi2c); + +static void I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c); +static void I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c); +static void I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c); +static void I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c); +static void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags); +static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c); +static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c); + +static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c); + +/* Private function to Convert Specific options */ +static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Functions I2C Exported Functions + * @{ + */ + +/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + deinitialize the I2Cx peripheral: + + (+) User must Implement HAL_I2C_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC). + + (+) Call the function HAL_I2C_Init() to configure the selected device with + the selected configuration: + (++) Communication Speed + (++) Duty cycle + (++) Addressing mode + (++) Own Address 1 + (++) Dual Addressing mode + (++) Own Address 2 + (++) General call mode + (++) Nostretch mode + + (+) Call the function HAL_I2C_DeInit() to restore the default configuration + of the selected I2Cx peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the I2C according to the specified parameters + * in the I2C_InitTypeDef and initialize the associated handle. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) +{ + uint32_t freqrange; + uint32_t pclk1; + + /* Check the I2C handle allocation */ + if (hi2c == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_CLOCK_SPEED(hi2c->Init.ClockSpeed)); + assert_param(IS_I2C_DUTY_CYCLE(hi2c->Init.DutyCycle)); + assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); + assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); + assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); + assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); + assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); + assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); + + if (hi2c->State == HAL_I2C_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hi2c->Lock = HAL_UNLOCKED; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + /* Init the I2C Callback settings */ + hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ + hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ + hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ + hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ + hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ + hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ + hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ + hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ + hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ + + if (hi2c->MspInitCallback == NULL) + { + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + hi2c->MspInitCallback(hi2c); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_I2C_MspInit(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /*Reset I2C*/ + hi2c->Instance->CR1 |= I2C_CR1_SWRST; + hi2c->Instance->CR1 &= ~I2C_CR1_SWRST; + + /* Get PCLK1 frequency */ + pclk1 = HAL_RCC_GetPCLK1Freq(); + + /* Check the minimum allowed PCLK1 frequency */ + if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U) + { + return HAL_ERROR; + } + + /* Calculate frequency range */ + freqrange = I2C_FREQRANGE(pclk1); + + /*---------------------------- I2Cx CR2 Configuration ----------------------*/ + /* Configure I2Cx: Frequency range */ + MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange); + + /*---------------------------- I2Cx TRISE Configuration --------------------*/ + /* Configure I2Cx: Rise Time */ + MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed)); + + /*---------------------------- I2Cx CCR Configuration ----------------------*/ + /* Configure I2Cx: Speed */ + MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle)); + + /*---------------------------- I2Cx CR1 Configuration ----------------------*/ + /* Configure I2Cx: Generalcall and NoStretch mode */ + MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode)); + + /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ + /* Configure I2Cx: Own Address1 and addressing mode */ + MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1)); + + /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ + /* Configure I2Cx: Dual mode and Own Address2 */ + MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2)); + + /* Enable the selected I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + + return HAL_OK; +} + +/** + * @brief DeInitialize the I2C peripheral. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) +{ + /* Check the I2C handle allocation */ + if (hi2c == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the I2C Peripheral Clock */ + __HAL_I2C_DISABLE(hi2c); + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + if (hi2c->MspDeInitCallback == NULL) + { + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + hi2c->MspDeInitCallback(hi2c); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_I2C_MspDeInit(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_RESET; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Initialize the I2C MSP. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitialize the I2C MSP. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User I2C Callback + * To be used instead of the weak predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID + * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID + * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID + * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID + * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hi2c); + + if (HAL_I2C_STATE_READY == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : + hi2c->MasterTxCpltCallback = pCallback; + break; + + case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : + hi2c->MasterRxCpltCallback = pCallback; + break; + + case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : + hi2c->SlaveTxCpltCallback = pCallback; + break; + + case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : + hi2c->SlaveRxCpltCallback = pCallback; + break; + + case HAL_I2C_LISTEN_COMPLETE_CB_ID : + hi2c->ListenCpltCallback = pCallback; + break; + + case HAL_I2C_MEM_TX_COMPLETE_CB_ID : + hi2c->MemTxCpltCallback = pCallback; + break; + + case HAL_I2C_MEM_RX_COMPLETE_CB_ID : + hi2c->MemRxCpltCallback = pCallback; + break; + + case HAL_I2C_ERROR_CB_ID : + hi2c->ErrorCallback = pCallback; + break; + + case HAL_I2C_ABORT_CB_ID : + hi2c->AbortCpltCallback = pCallback; + break; + + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = pCallback; + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_I2C_STATE_RESET == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = pCallback; + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + return status; +} + +/** + * @brief Unregister an I2C Callback + * I2C callback is redirected to the weak predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * This parameter can be one of the following values: + * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID + * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID + * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID + * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID + * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hi2c); + + if (HAL_I2C_STATE_READY == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : + hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ + break; + + case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : + hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ + break; + + case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : + hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ + break; + + case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : + hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ + break; + + case HAL_I2C_LISTEN_COMPLETE_CB_ID : + hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ + break; + + case HAL_I2C_MEM_TX_COMPLETE_CB_ID : + hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ + break; + + case HAL_I2C_MEM_RX_COMPLETE_CB_ID : + hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ + break; + + case HAL_I2C_ERROR_CB_ID : + hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_I2C_ABORT_CB_ID : + hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_I2C_STATE_RESET == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + return status; +} + +/** + * @brief Register the Slave Address Match I2C Callback + * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pCallback pointer to the Address Match Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hi2c); + + if (HAL_I2C_STATE_READY == hi2c->State) + { + hi2c->AddrCallback = pCallback; + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + return status; +} + +/** + * @brief UnRegister the Slave Address Match I2C Callback + * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hi2c); + + if (HAL_I2C_STATE_READY == hi2c->State) + { + hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + return status; +} + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the I2C data + transfers. + + (#) There are two modes of transfer: + (++) Blocking mode : The communication is performed in the polling mode. + The status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode : The communication is performed using Interrupts + or DMA. These functions return the status of the transfer startup. + The end of the data processing will be indicated through the + dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + + (#) Blocking mode functions are : + (++) HAL_I2C_Master_Transmit() + (++) HAL_I2C_Master_Receive() + (++) HAL_I2C_Slave_Transmit() + (++) HAL_I2C_Slave_Receive() + (++) HAL_I2C_Mem_Write() + (++) HAL_I2C_Mem_Read() + (++) HAL_I2C_IsDeviceReady() + + (#) No-Blocking mode functions with Interrupt are : + (++) HAL_I2C_Master_Transmit_IT() + (++) HAL_I2C_Master_Receive_IT() + (++) HAL_I2C_Slave_Transmit_IT() + (++) HAL_I2C_Slave_Receive_IT() + (++) HAL_I2C_Mem_Write_IT() + (++) HAL_I2C_Mem_Read_IT() + (++) HAL_I2C_Master_Seq_Transmit_IT() + (++) HAL_I2C_Master_Seq_Receive_IT() + (++) HAL_I2C_Slave_Seq_Transmit_IT() + (++) HAL_I2C_Slave_Seq_Receive_IT() + (++) HAL_I2C_EnableListen_IT() + (++) HAL_I2C_DisableListen_IT() + (++) HAL_I2C_Master_Abort_IT() + + (#) No-Blocking mode functions with DMA are : + (++) HAL_I2C_Master_Transmit_DMA() + (++) HAL_I2C_Master_Receive_DMA() + (++) HAL_I2C_Slave_Transmit_DMA() + (++) HAL_I2C_Slave_Receive_DMA() + (++) HAL_I2C_Mem_Write_DMA() + (++) HAL_I2C_Mem_Read_DMA() + (++) HAL_I2C_Master_Seq_Transmit_DMA() + (++) HAL_I2C_Master_Seq_Receive_DMA() + (++) HAL_I2C_Slave_Seq_Transmit_DMA() + (++) HAL_I2C_Slave_Seq_Receive_DMA() + + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (++) HAL_I2C_MasterTxCpltCallback() + (++) HAL_I2C_MasterRxCpltCallback() + (++) HAL_I2C_SlaveTxCpltCallback() + (++) HAL_I2C_SlaveRxCpltCallback() + (++) HAL_I2C_MemTxCpltCallback() + (++) HAL_I2C_MemRxCpltCallback() + (++) HAL_I2C_AddrCallback() + (++) HAL_I2C_ListenCpltCallback() + (++) HAL_I2C_ErrorCallback() + (++) HAL_I2C_AbortCpltCallback() + +@endverbatim + * @{ + */ + +/** + * @brief Transmits in master mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + /* Init tickstart for timeout management*/ + uint32_t tickstart = HAL_GetTick(); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + /* Send Slave Address */ + if (I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + while (hi2c->XferSize > 0U) + { + /* Wait until TXE flag is set */ + if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + return HAL_ERROR; + } + + /* Write data to DR */ + hi2c->Instance->DR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + hi2c->XferSize--; + + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) + { + /* Write data to DR */ + hi2c->Instance->DR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + hi2c->XferSize--; + } + + /* Wait until BTF flag is set */ + if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + return HAL_ERROR; + } + } + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receives in master mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + /* Init tickstart for timeout management*/ + uint32_t tickstart = HAL_GetTick(); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + /* Send Slave Address */ + if (I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferSize == 0U) + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + else if (hi2c->XferSize == 1U) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + else if (hi2c->XferSize == 2U) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Enable Pos */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + else + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + + while (hi2c->XferSize > 0U) + { + if (hi2c->XferSize <= 3U) + { + /* One byte */ + if (hi2c->XferSize == 1U) + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + } + /* Two bytes */ + else if (hi2c->XferSize == 2U) + { + /* Wait until BTF flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + } + /* 3 Last bytes */ + else + { + /* Wait until BTF flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + + /* Wait until BTF flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + } + } + else + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) + { + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + } + } + } + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmits in slave mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + /* Init tickstart for timeout management*/ + uint32_t tickstart = HAL_GetTick(); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + /* Enable Address Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* If 10bit addressing mode is selected */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + + while (hi2c->XferSize > 0U) + { + /* Wait until TXE flag is set */ + if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + return HAL_ERROR; + } + + /* Write data to DR */ + hi2c->Instance->DR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + hi2c->XferSize--; + + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) + { + /* Write data to DR */ + hi2c->Instance->DR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + hi2c->XferSize--; + } + } + + /* Wait until AF flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Disable Address Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in blocking mode + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + /* Init tickstart for timeout management*/ + uint32_t tickstart = HAL_GetTick(); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == (uint16_t)0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + /* Enable Address Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + while (hi2c->XferSize > 0U) + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + return HAL_ERROR; + } + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) + { + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + } + } + + /* Wait until STOP flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + return HAL_ERROR; + } + + /* Clear STOP flag */ + __HAL_I2C_CLEAR_STOPFLAG(hi2c); + + /* Disable Address Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->Devaddress = DevAddress; + + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->Devaddress = DevAddress; + + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + /* Enable Address Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + /* Enable Address Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->Devaddress = DevAddress; + + if (hi2c->XferSize > 0U) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferM1CpltCallback = NULL; + hi2c->hdmatx->XferM1HalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); + + if (dmaxferstatus == HAL_OK) + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* Enable DMA Request */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->Devaddress = DevAddress; + + if (hi2c->XferSize > 0U) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferM1CpltCallback = NULL; + hi2c->hdmarx->XferM1HalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); + + if (dmaxferstatus == HAL_OK) + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* Enable DMA Request */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferM1CpltCallback = NULL; + hi2c->hdmatx->XferM1HalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); + + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* Enable DMA Request */ + hi2c->Instance->CR2 |= I2C_CR2_DMAEN; + + return HAL_OK; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferM1CpltCallback = NULL; + hi2c->hdmarx->XferM1HalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); + + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* Enable DMA Request */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + return HAL_OK; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Write an amount of data in blocking mode to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + /* Init tickstart for timeout management*/ + uint32_t tickstart = HAL_GetTick(); + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + while (hi2c->XferSize > 0U) + { + /* Wait until TXE flag is set */ + if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + return HAL_ERROR; + } + + /* Write data to DR */ + hi2c->Instance->DR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) + { + /* Write data to DR */ + hi2c->Instance->DR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + } + } + + /* Wait until BTF flag is set */ + if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + return HAL_ERROR; + } + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Read an amount of data in blocking mode from a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + /* Init tickstart for timeout management*/ + uint32_t tickstart = HAL_GetTick(); + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferSize == 0U) + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + else if (hi2c->XferSize == 1U) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + else if (hi2c->XferSize == 2U) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Enable Pos */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + else + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + + while (hi2c->XferSize > 0U) + { + if (hi2c->XferSize <= 3U) + { + /* One byte */ + if (hi2c->XferSize == 1U) + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + } + /* Two bytes */ + else if (hi2c->XferSize == 2U) + { + /* Wait until BTF flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + } + /* 3 Last bytes */ + else + { + /* Wait until BTF flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + + /* Wait until BTF flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + } + } + else + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) + { + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + } + } + } + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->Devaddress = DevAddress; + hi2c->Memaddress = MemAddress; + hi2c->MemaddSize = MemAddSize; + hi2c->EventCount = 0U; + + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->Devaddress = DevAddress; + hi2c->Memaddress = MemAddress; + hi2c->MemaddSize = MemAddSize; + hi2c->EventCount = 0U; + + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + if (hi2c->XferSize > 0U) + { + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + } + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + HAL_StatusTypeDef dmaxferstatus; + + /* Init tickstart for timeout management*/ + uint32_t tickstart = HAL_GetTick(); + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + if (hi2c->XferSize > 0U) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferM1CpltCallback = NULL; + hi2c->hdmatx->XferM1HalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + { + /* Abort the ongoing DMA */ + dmaxferstatus = HAL_DMA_Abort_IT(hi2c->hdmatx); + + /* Prevent unused argument(s) compilation and MISRA warning */ + UNUSED(dmaxferstatus); + + /* Clear directly Complete callback as no XferAbortCallback is used to finalize Abort treatment */ + if (hi2c->hdmatx != NULL) + { + hi2c->hdmatx->XferCpltCallback = NULL; + } + + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + hi2c->XferSize = 0U; + hi2c->XferCount = 0U; + + /* Disable I2C peripheral to prevent dummy data in buffer */ + __HAL_I2C_DISABLE(hi2c); + + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR); + + /* Enable DMA Request */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + return HAL_OK; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be read + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + /* Init tickstart for timeout management*/ + uint32_t tickstart = HAL_GetTick(); + __IO uint32_t count = 0U; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + if (hi2c->XferSize > 0U) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferM1CpltCallback = NULL; + hi2c->hdmarx->XferM1HalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + { + /* Abort the ongoing DMA */ + dmaxferstatus = HAL_DMA_Abort_IT(hi2c->hdmarx); + + /* Prevent unused argument(s) compilation and MISRA warning */ + UNUSED(dmaxferstatus); + + /* Clear directly Complete callback as no XferAbortCallback is used to finalize Abort treatment */ + if (hi2c->hdmarx != NULL) + { + hi2c->hdmarx->XferCpltCallback = NULL; + } + + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + hi2c->XferSize = 0U; + hi2c->XferCount = 0U; + + /* Disable I2C peripheral to prevent dummy data in buffer */ + __HAL_I2C_DISABLE(hi2c); + + return HAL_ERROR; + } + + if (hi2c->XferSize == 1U) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + else + { + /* Enable Last DMA bit */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR); + + /* Enable DMA Request */ + hi2c->Instance->CR2 |= I2C_CR2_DMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Checks if target device is ready for communication. + * @note This function is used with Memory devices + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param Trials Number of trials + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) +{ + /* Get tick */ + uint32_t tickstart = HAL_GetTick(); + uint32_t I2C_Trials = 1U; + FlagStatus tmp1; + FlagStatus tmp2; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + do + { + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Wait until SB flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK) + { + if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) + { + hi2c->ErrorCode = HAL_I2C_WRONG_START; + } + return HAL_TIMEOUT; + } + + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); + + /* Wait until ADDR or AF flag are set */ + /* Get tick */ + tickstart = HAL_GetTick(); + + tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + while ((hi2c->State != HAL_I2C_STATE_TIMEOUT) && (tmp1 == RESET) && (tmp2 == RESET)) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + hi2c->State = HAL_I2C_STATE_TIMEOUT; + } + tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + } + + hi2c->State = HAL_I2C_STATE_READY; + + /* Check if the ADDR flag has been set */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + /* Clear ADDR Flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + /* Clear AF Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + } + + /* Increment Trials */ + I2C_Trials++; + } + while (I2C_Trials < Trials); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt. + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + __IO uint32_t Prev_State = 0x00U; + __IO uint32_t count = 0x00U; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Check Busy Flag only if FIRST call of Master interface */ + if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->Devaddress = DevAddress; + + Prev_State = hi2c->PreviousState; + + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) + { + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA. + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + __IO uint32_t Prev_State = 0x00U; + __IO uint32_t count = 0x00U; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Check Busy Flag only if FIRST call of Master interface */ + if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->Devaddress = DevAddress; + + Prev_State = hi2c->PreviousState; + + if (hi2c->XferSize > 0U) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); + + if (dmaxferstatus == HAL_OK) + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) + { + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* If XferOptions is not associated to a new frame, mean no start bit is request, enable directly the DMA request */ + /* In other cases, DMA request is enabled after Slave address treatment in IRQHandler */ + if ((XferOptions == I2C_NEXT_FRAME) || (XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)) + { + /* Enable DMA Request */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + } + + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) + { + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + __IO uint32_t Prev_State = 0x00U; + __IO uint32_t count = 0U; + uint32_t enableIT = (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Check Busy Flag only if FIRST call of Master interface */ + if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->Devaddress = DevAddress; + + Prev_State = hi2c->PreviousState; + + if ((hi2c->XferCount == 2U) && ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))) + { + if (Prev_State == I2C_STATE_MASTER_BUSY_RX) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Enable Pos */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + /* Remove Enabling of IT_BUF, mean RXNE treatment, treat the 2 bytes through BTF */ + enableIT &= ~I2C_IT_BUF; + } + else + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + } + else + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) + { + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable interrupts */ + __HAL_I2C_ENABLE_IT(hi2c, enableIT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential receive in master mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + __IO uint32_t Prev_State = 0x00U; + __IO uint32_t count = 0U; + uint32_t enableIT = (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Check Busy Flag only if FIRST call of Master interface */ + if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + /* Clear Last DMA bit */ + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->Devaddress = DevAddress; + + Prev_State = hi2c->PreviousState; + + if (hi2c->XferSize > 0U) + { + if ((hi2c->XferCount == 2U) && ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))) + { + if (Prev_State == I2C_STATE_MASTER_BUSY_RX) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Enable Pos */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + /* Enable Last DMA bit */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); + } + else + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + } + else + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + if ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_OTHER_AND_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)) + { + /* Enable Last DMA bit */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); + } + } + + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); + + if (dmaxferstatus == HAL_OK) + { + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) + { + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Update interrupt for only EVT and ERR */ + enableIT = (I2C_IT_EVT | I2C_IT_ERR); + } + else + { + /* Update interrupt for only ERR */ + enableIT = I2C_IT_ERR; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* If XferOptions is not associated to a new frame, mean no start bit is request, enable directly the DMA request */ + /* In other cases, DMA request is enabled after Slave address treatment in IRQHandler */ + if ((XferOptions == I2C_NEXT_FRAME) || (XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)) + { + /* Enable DMA Request */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + } + + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, enableIT); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) + { + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable interrupts */ + __HAL_I2C_ENABLE_IT(hi2c, enableIT); + } + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in slave mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in slave mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave RX state to TX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) + { + /* Abort DMA Xfer if any */ + if (hi2c->hdmarx != NULL) + { + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) + { + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } + } + else + { + /* Nothing to do */ + } + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); + + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* Enable DMA Request */ + hi2c->Instance->CR2 |= I2C_CR2_DMAEN; + + return HAL_OK; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential receive in slave mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential receive in slave mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave RX state to TX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) + { + /* Abort DMA Xfer if any */ + if (hi2c->hdmarx != NULL) + { + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) + { + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } + } + else + { + /* Nothing to do */ + } + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); + + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Enable DMA Request */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + return HAL_OK; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Enable the Address listen mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + hi2c->State = HAL_I2C_STATE_LISTEN; + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Enable Address Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Disable the Address listen mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp; + + /* Disable Address listen mode only if a transfer is not ongoing */ + if (hi2c->State == HAL_I2C_STATE_LISTEN) + { + tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; + hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Disable Address Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Disable EVT and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Abort a master I2C IT or DMA process communication with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) +{ + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(DevAddress); + + /* Abort Master transfer during Receive or Transmit process */ + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && (CurrentMode == HAL_I2C_MODE_MASTER)) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_ABORT; + + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + hi2c->XferCount = 0U; + + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c); + + return HAL_OK; + } + else + { + /* Wrong usage of abort function */ + /* This function should be used only in case of abort monitored by master device */ + /* Or periphal is not in busy state, mean there is no active sequence to be abort */ + return HAL_ERROR; + } +} + +/** + * @} + */ + +/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ + +/** + * @brief This function handles I2C event interrupt request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) +{ + uint32_t sr1itflags; + uint32_t sr2itflags = 0U; + uint32_t itsources = READ_REG(hi2c->Instance->CR2); + uint32_t CurrentXferOptions = hi2c->XferOptions; + HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; + HAL_I2C_StateTypeDef CurrentState = hi2c->State; + + /* Master or Memory mode selected */ + if ((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) + { + sr2itflags = READ_REG(hi2c->Instance->SR2); + sr1itflags = READ_REG(hi2c->Instance->SR1); + + /* Exit IRQ event until Start Bit detected in case of Other frame requested */ + if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_SB) == RESET) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(CurrentXferOptions) == 1U)) + { + return; + } + + /* SB Set ----------------------------------------------------------------*/ + if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_SB) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + I2C_Master_SB(hi2c); + } + /* ADD10 Set -------------------------------------------------------------*/ + else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADD10) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) + { + I2C_Master_ADD10(hi2c); + } + /* ADDR Set --------------------------------------------------------------*/ + else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) + { + I2C_Master_ADDR(hi2c); + } + /* I2C in mode Transmitter -----------------------------------------------*/ + else if (I2C_CHECK_FLAG(sr2itflags, I2C_FLAG_TRA) != RESET) + { + /* Do not check buffer and BTF flag if a Xfer DMA is on going */ + if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN) + { + /* TXE set and BTF reset -----------------------------------------------*/ + if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_TXE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET)) + { + I2C_MasterTransmit_TXE(hi2c); + } + /* BTF set -------------------------------------------------------------*/ + else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) + { + if (CurrentMode == HAL_I2C_MODE_MASTER) + { + I2C_MasterTransmit_BTF(hi2c); + } + else /* HAL_I2C_MODE_MEM */ + { + I2C_MemoryTransmit_TXE_BTF(hi2c); + } + } + else + { + /* Do nothing */ + } + } + } + /* I2C in mode Receiver --------------------------------------------------*/ + else + { + /* Do not check buffer and BTF flag if a Xfer DMA is on going */ + if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN) + { + /* RXNE set and BTF reset -----------------------------------------------*/ + if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET)) + { + I2C_MasterReceive_RXNE(hi2c); + } + /* BTF set -------------------------------------------------------------*/ + else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) + { + I2C_MasterReceive_BTF(hi2c); + } + else + { + /* Do nothing */ + } + } + } + } + /* Slave mode selected */ + else + { + /* If an error is detected, read only SR1 register to prevent */ + /* a clear of ADDR flags by reading SR2 after reading SR1 in Error treatment */ + if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + sr1itflags = READ_REG(hi2c->Instance->SR1); + } + else + { + sr2itflags = READ_REG(hi2c->Instance->SR2); + sr1itflags = READ_REG(hi2c->Instance->SR1); + } + + /* ADDR set --------------------------------------------------------------*/ + if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) + { + /* Now time to read SR2, this will clear ADDR flag automatically */ + if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + sr2itflags = READ_REG(hi2c->Instance->SR2); + } + I2C_Slave_ADDR(hi2c, sr2itflags); + } + /* STOPF set --------------------------------------------------------------*/ + else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) + { + I2C_Slave_STOPF(hi2c); + } + /* I2C in mode Transmitter -----------------------------------------------*/ + else if ((CurrentState == HAL_I2C_STATE_BUSY_TX) || (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + /* TXE set and BTF reset -----------------------------------------------*/ + if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_TXE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET)) + { + I2C_SlaveTransmit_TXE(hi2c); + } + /* BTF set -------------------------------------------------------------*/ + else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) + { + I2C_SlaveTransmit_BTF(hi2c); + } + else + { + /* Do nothing */ + } + } + /* I2C in mode Receiver --------------------------------------------------*/ + else + { + /* RXNE set and BTF reset ----------------------------------------------*/ + if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET)) + { + I2C_SlaveReceive_RXNE(hi2c); + } + /* BTF set -------------------------------------------------------------*/ + else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) + { + I2C_SlaveReceive_BTF(hi2c); + } + else + { + /* Do nothing */ + } + } + } +} + +/** + * @brief This function handles I2C error interrupt request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) +{ + HAL_I2C_ModeTypeDef tmp1; + uint32_t tmp2; + HAL_I2C_StateTypeDef tmp3; + uint32_t tmp4; + uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1); + uint32_t itsources = READ_REG(hi2c->Instance->CR2); + uint32_t error = HAL_I2C_ERROR_NONE; + HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; + + /* I2C Bus error interrupt occurred ----------------------------------------*/ + if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET)) + { + error |= HAL_I2C_ERROR_BERR; + + /* Clear BERR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); + } + + /* I2C Arbitration Lost error interrupt occurred ---------------------------*/ + if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ARLO) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET)) + { + error |= HAL_I2C_ERROR_ARLO; + + /* Clear ARLO flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); + } + + /* I2C Acknowledge failure error interrupt occurred ------------------------*/ + if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET)) + { + tmp1 = CurrentMode; + tmp2 = hi2c->XferCount; + tmp3 = hi2c->State; + tmp4 = hi2c->PreviousState; + if ((tmp1 == HAL_I2C_MODE_SLAVE) && (tmp2 == 0U) && \ + ((tmp3 == HAL_I2C_STATE_BUSY_TX) || (tmp3 == HAL_I2C_STATE_BUSY_TX_LISTEN) || \ + ((tmp3 == HAL_I2C_STATE_LISTEN) && (tmp4 == I2C_STATE_SLAVE_BUSY_TX)))) + { + I2C_Slave_AF(hi2c); + } + else + { + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + error |= HAL_I2C_ERROR_AF; + + /* Do not generate a STOP in case of Slave receive non acknowledge during transfer (mean not at the end of transfer) */ + if ((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + } + } + + /* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/ + if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_OVR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET)) + { + error |= HAL_I2C_ERROR_OVR; + /* Clear OVR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); + } + + /* Call the Error Callback in case of Error detected -----------------------*/ + if (error != HAL_I2C_ERROR_NONE) + { + hi2c->ErrorCode |= error; + I2C_ITError(hi2c); + } +} + +/** + * @brief Master Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Master Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterRxCpltCallback could be implemented in the user file + */ +} + +/** @brief Slave Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Slave Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Slave Address Match callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XferDirection_definition + * @param AddrMatchCode Address Match Code + * @retval None + */ +__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + UNUSED(TransferDirection); + UNUSED(AddrMatchCode); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AddrCallback() could be implemented in the user file + */ +} + +/** + * @brief Listen Complete callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_ListenCpltCallback() could be implemented in the user file + */ +} + +/** + * @brief Memory Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Memory Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemRxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief I2C error callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief I2C abort callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AbortCpltCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions + * @brief Peripheral State, Mode and Error functions + * +@verbatim + =============================================================================== + ##### Peripheral State, Mode and Error functions ##### + =============================================================================== + [..] + This subsection permit to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the I2C handle state. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL state + */ +HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) +{ + /* Return I2C handle state */ + return hi2c->State; +} + +/** + * @brief Returns the I2C Master, Slave, Memory or no mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL mode + */ +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) +{ + return hi2c->Mode; +} + +/** + * @brief Return the I2C error code. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval I2C Error Code + */ +uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) +{ + return hi2c->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup I2C_Private_Functions + * @{ + */ + +/** + * @brief Handle TXE flag for Master + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + HAL_I2C_StateTypeDef CurrentState = hi2c->State; + HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; + uint32_t CurrentXferOptions = hi2c->XferOptions; + + if ((hi2c->XferSize == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX)) + { + /* Call TxCpltCallback() directly if no stop mode is set */ + if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME)) + { + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterTxCpltCallback(hi2c); +#else + HAL_I2C_MasterTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else /* Generate Stop condition then Call TxCpltCallback() */ + { + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemTxCpltCallback(hi2c); +#else + HAL_I2C_MemTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterTxCpltCallback(hi2c); +#else + HAL_I2C_MasterTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + } + else if ((CurrentState == HAL_I2C_STATE_BUSY_TX) || \ + ((CurrentMode == HAL_I2C_MODE_MEM) && (CurrentState == HAL_I2C_STATE_BUSY_RX))) + { + if (hi2c->XferCount == 0U) + { + /* Disable BUF interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); + } + else + { + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + I2C_MemoryTransmit_TXE_BTF(hi2c); + } + else + { + /* Write data to DR */ + hi2c->Instance->DR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + } + } + } + else + { + /* Do nothing */ + } +} + +/** + * @brief Handle BTF flag for Master transmitter + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + uint32_t CurrentXferOptions = hi2c->XferOptions; + + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + if (hi2c->XferCount != 0U) + { + /* Write data to DR */ + hi2c->Instance->DR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + } + else + { + /* Call TxCpltCallback() directly if no stop mode is set */ + if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME)) + { + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterTxCpltCallback(hi2c); +#else + HAL_I2C_MasterTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else /* Generate Stop condition then Call TxCpltCallback() */ + { + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterTxCpltCallback(hi2c); +#else + HAL_I2C_MasterTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + } + else + { + /* Do nothing */ + } +} + +/** + * @brief Handle TXE and BTF flag for Memory transmitter + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + HAL_I2C_StateTypeDef CurrentState = hi2c->State; + + if (hi2c->EventCount == 0U) + { + /* If Memory address size is 8Bit */ + if (hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress); + + hi2c->EventCount += 2U; + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_MSB(hi2c->Memaddress); + + hi2c->EventCount++; + } + } + else if (hi2c->EventCount == 1U) + { + /* Send LSB of Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress); + + hi2c->EventCount++; + } + else if (hi2c->EventCount == 2U) + { + if (CurrentState == HAL_I2C_STATE_BUSY_RX) + { + /* Generate Restart */ + hi2c->Instance->CR1 |= I2C_CR1_START; + } + else if ((hi2c->XferCount > 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX)) + { + /* Write data to DR */ + hi2c->Instance->DR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + } + else if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX)) + { + /* Generate Stop condition then Call TxCpltCallback() */ + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemTxCpltCallback(hi2c); +#else + HAL_I2C_MemTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + /* Do nothing */ + } + } + else + { + /* Do nothing */ + } +} + +/** + * @brief Handle RXNE flag for Master + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + uint32_t tmp; + + tmp = hi2c->XferCount; + if (tmp > 3U) + { + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + + if (hi2c->XferCount == (uint16_t)3) + { + /* Disable BUF interrupt, this help to treat correctly the last 4 bytes + on BTF subroutine */ + /* Disable BUF interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); + } + } + else if ((hi2c->XferOptions != I2C_FIRST_AND_NEXT_FRAME) && ((tmp == 1U) || (tmp == 0U))) + { + if (I2C_WaitOnSTOPRequestThroughIT(hi2c) == HAL_OK) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + + hi2c->State = HAL_I2C_STATE_READY; + + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->PreviousState = I2C_STATE_NONE; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemRxCpltCallback(hi2c); +#else + HAL_I2C_MemRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterRxCpltCallback(hi2c); +#else + HAL_I2C_MasterRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + else + { + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Call user error callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ErrorCallback(hi2c); +#else + HAL_I2C_ErrorCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + else + { + /* Do nothing */ + } + } +} + +/** + * @brief Handle BTF flag for Master receiver + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + uint32_t CurrentXferOptions = hi2c->XferOptions; + + if (hi2c->XferCount == 4U) + { + /* Disable BUF interrupt, this help to treat correctly the last 2 bytes + on BTF subroutine if there is a reception delay between N-1 and N byte */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + } + else if (hi2c->XferCount == 3U) + { + /* Disable BUF interrupt, this help to treat correctly the last 2 bytes + on BTF subroutine if there is a reception delay between N-1 and N byte */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); + + if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME)) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + } + else if (hi2c->XferCount == 2U) + { + /* Prepare next transfer or stop current transfer */ + if ((CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP)) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + else if ((CurrentXferOptions == I2C_NEXT_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_NEXT_FRAME)) + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + else if (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + else + { + /* Do nothing */ + } + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + + /* Disable EVT and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + hi2c->State = HAL_I2C_STATE_READY; + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->PreviousState = I2C_STATE_NONE; +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemRxCpltCallback(hi2c); +#else + HAL_I2C_MemRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterRxCpltCallback(hi2c); +#else + HAL_I2C_MasterRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + else + { + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + } +} + +/** + * @brief Handle SB flag for Master + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_Master_SB(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + if (hi2c->EventCount == 0U) + { + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress); + } + else + { + hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress); + } + } + else + { + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + { + /* Send slave 7 Bits address */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress); + } + else + { + hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress); + } + + if (((hi2c->hdmatx != NULL) && (hi2c->hdmatx->XferCpltCallback != NULL)) + || ((hi2c->hdmarx != NULL) && (hi2c->hdmarx->XferCpltCallback != NULL))) + { + /* Enable DMA Request */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + } + } + else + { + if (hi2c->EventCount == 0U) + { + /* Send header of slave address */ + hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(hi2c->Devaddress); + } + else if (hi2c->EventCount == 1U) + { + /* Send header of slave address */ + hi2c->Instance->DR = I2C_10BIT_HEADER_READ(hi2c->Devaddress); + } + else + { + /* Do nothing */ + } + } + } +} + +/** + * @brief Handle ADD10 flag for Master + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_Master_ADD10(I2C_HandleTypeDef *hi2c) +{ + /* Send slave address */ + hi2c->Instance->DR = I2C_10BIT_ADDRESS(hi2c->Devaddress); + + if ((hi2c->hdmatx != NULL) || (hi2c->hdmarx != NULL)) + { + if ((hi2c->hdmatx->XferCpltCallback != NULL) || (hi2c->hdmarx->XferCpltCallback != NULL)) + { + /* Enable DMA Request */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + } + } +} + +/** + * @brief Handle ADDR flag for Master + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_Master_ADDR(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; + uint32_t CurrentXferOptions = hi2c->XferOptions; + uint32_t Prev_State = hi2c->PreviousState; + + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + if ((hi2c->EventCount == 0U) && (CurrentMode == HAL_I2C_MODE_MEM)) + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + else if ((hi2c->EventCount == 0U) && (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)) + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Restart */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + hi2c->EventCount++; + } + else + { + if (hi2c->XferCount == 0U) + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + else if (hi2c->XferCount == 1U) + { + if (CurrentXferOptions == I2C_NO_OPTION_FRAME) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + else + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + } + /* Prepare next transfer or stop current transfer */ + else if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) \ + && ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (CurrentXferOptions == I2C_FIRST_FRAME))) + { + if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP)) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + else + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + else + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + } + else if (hi2c->XferCount == 2U) + { + if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP)) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Enable Pos */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + } + else + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + + if (((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) && ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP) || (CurrentXferOptions == I2C_LAST_FRAME))) + { + /* Enable Last DMA bit */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + else + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + if (((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) && ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP) || (CurrentXferOptions == I2C_LAST_FRAME))) + { + /* Enable Last DMA bit */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + + /* Reset Event counter */ + hi2c->EventCount = 0U; + } + } + else + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } +} + +/** + * @brief Handle TXE flag for Slave + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + HAL_I2C_StateTypeDef CurrentState = hi2c->State; + + if (hi2c->XferCount != 0U) + { + /* Write data to DR */ + hi2c->Instance->DR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + + if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + /* Last Byte is received, disable Interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); + + /* Set state at HAL_I2C_STATE_LISTEN */ + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + hi2c->State = HAL_I2C_STATE_LISTEN; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveTxCpltCallback(hi2c); +#else + HAL_I2C_SlaveTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } +} + +/** + * @brief Handle BTF flag for Slave transmitter + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->XferCount != 0U) + { + /* Write data to DR */ + hi2c->Instance->DR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + } +} + +/** + * @brief Handle RXNE flag for Slave + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + HAL_I2C_StateTypeDef CurrentState = hi2c->State; + + if (hi2c->XferCount != 0U) + { + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + + if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + /* Last Byte is received, disable Interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); + + /* Set state at HAL_I2C_STATE_LISTEN */ + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + hi2c->State = HAL_I2C_STATE_LISTEN; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveRxCpltCallback(hi2c); +#else + HAL_I2C_SlaveRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } +} + +/** + * @brief Handle BTF flag for Slave receiver + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->XferCount != 0U) + { + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + } +} + +/** + * @brief Handle ADD flag for Slave + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param IT2Flags Interrupt2 flags to handle. + * @retval None + */ +static void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags) +{ + uint8_t TransferDirection = I2C_DIRECTION_RECEIVE; + uint16_t SlaveAddrCode; + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + /* Disable BUF interrupt, BUF enabling is manage through slave specific interface */ + __HAL_I2C_DISABLE_IT(hi2c, (I2C_IT_BUF)); + + /* Transfer Direction requested by Master */ + if (I2C_CHECK_FLAG(IT2Flags, I2C_FLAG_TRA) == RESET) + { + TransferDirection = I2C_DIRECTION_TRANSMIT; + } + + if (I2C_CHECK_FLAG(IT2Flags, I2C_FLAG_DUALF) == RESET) + { + SlaveAddrCode = (uint16_t)hi2c->Init.OwnAddress1; + } + else + { + SlaveAddrCode = (uint16_t)hi2c->Init.OwnAddress2; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AddrCallback(hi2c, TransferDirection, SlaveAddrCode); +#else + HAL_I2C_AddrCallback(hi2c, TransferDirection, SlaveAddrCode); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + } +} + +/** + * @brief Handle STOPF flag for Slave + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + HAL_I2C_StateTypeDef CurrentState = hi2c->State; + + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Clear STOPF flag */ + __HAL_I2C_CLEAR_STOPFLAG(hi2c); + + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* If a DMA is ongoing, Update handle size context */ + if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) + { + if ((CurrentState == HAL_I2C_STATE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + hi2c->XferCount = (uint16_t)(__HAL_DMA_GET_COUNTER(hi2c->hdmarx)); + + if (hi2c->XferCount != 0U) + { + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + /* Disable, stop the current DMA */ + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + /* Abort DMA Xfer if any */ + if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + else + { + hi2c->XferCount = (uint16_t)(__HAL_DMA_GET_COUNTER(hi2c->hdmatx)); + + if (hi2c->XferCount != 0U) + { + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + /* Disable, stop the current DMA */ + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + /* Abort DMA Xfer if any */ + if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } + } + + /* All data are not transferred, so set error code accordingly */ + if (hi2c->XferCount != 0U) + { + /* Store Last receive data if any */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) + { + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + } + + /* Store Last receive data if any */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + { + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + } + + if (hi2c->XferCount != 0U) + { + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + } + + if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c); + } + else + { + if (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Set state at HAL_I2C_STATE_LISTEN */ + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_LISTEN; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveRxCpltCallback(hi2c); +#else + HAL_I2C_SlaveRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + + if (hi2c->State == HAL_I2C_STATE_LISTEN) + { + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ListenCpltCallback(hi2c); +#else + HAL_I2C_ListenCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + if ((hi2c->PreviousState == I2C_STATE_SLAVE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveRxCpltCallback(hi2c); +#else + HAL_I2C_SlaveRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + } +} + +/** + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + HAL_I2C_StateTypeDef CurrentState = hi2c->State; + uint32_t CurrentXferOptions = hi2c->XferOptions; + + if (((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) && \ + (CurrentState == HAL_I2C_STATE_LISTEN)) + { + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ListenCpltCallback(hi2c); +#else + HAL_I2C_ListenCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else if (CurrentState == HAL_I2C_STATE_BUSY_TX) + { + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveTxCpltCallback(hi2c); +#else + HAL_I2C_SlaveTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + /* Clear AF flag only */ + /* State Listen, but XferOptions == FIRST or NEXT */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } +} + +/** + * @brief I2C interrupts error process + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ITError(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + HAL_I2C_StateTypeDef CurrentState = hi2c->State; + HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; + uint32_t CurrentError; + + if (((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) && (CurrentState == HAL_I2C_STATE_BUSY_RX)) + { + /* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + } + + if (((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + /* keep HAL_I2C_STATE_LISTEN */ + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_LISTEN; + } + else + { + /* If state is an abort treatment on going, don't change state */ + /* This change will be do later */ + if ((READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN) && (CurrentState != HAL_I2C_STATE_ABORT)) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + } + hi2c->PreviousState = I2C_STATE_NONE; + } + + /* Abort DMA transfer */ + if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) == I2C_CR2_DMAEN) + { + hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN; + + if (hi2c->hdmatx->State != HAL_DMA_STATE_READY) + { + /* Set the DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Disable I2C peripheral to prevent dummy data in buffer */ + __HAL_I2C_DISABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + else + { + /* Set the DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Store Last receive data if any */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + { + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + } + + /* Disable I2C peripheral to prevent dummy data in buffer */ + __HAL_I2C_DISABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + else if (hi2c->State == HAL_I2C_STATE_ABORT) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Store Last receive data if any */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + { + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + } + + /* Disable I2C peripheral to prevent dummy data in buffer */ + __HAL_I2C_DISABLE(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AbortCpltCallback(hi2c); +#else + HAL_I2C_AbortCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + /* Store Last receive data if any */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + { + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + } + + /* Call user error callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ErrorCallback(hi2c); +#else + HAL_I2C_ErrorCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + + /* STOP Flag is not set after a NACK reception, BusError, ArbitrationLost, OverRun */ + CurrentError = hi2c->ErrorCode; + + if (((CurrentError & HAL_I2C_ERROR_BERR) == HAL_I2C_ERROR_BERR) || \ + ((CurrentError & HAL_I2C_ERROR_ARLO) == HAL_I2C_ERROR_ARLO) || \ + ((CurrentError & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF) || \ + ((CurrentError & HAL_I2C_ERROR_OVR) == HAL_I2C_ERROR_OVR)) + { + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + } + + /* So may inform upper layer that listen phase is stopped */ + /* during NACK error treatment */ + CurrentState = hi2c->State; + if (((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF) && (CurrentState == HAL_I2C_STATE_LISTEN)) + { + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ListenCpltCallback(hi2c); +#else + HAL_I2C_ListenCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart) +{ + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + uint32_t CurrentXferOptions = hi2c->XferOptions; + + /* Generate Start condition if first transfer */ + if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME)) + { + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + } + else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) + { + /* Generate ReStart */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + } + else + { + /* Do nothing */ + } + + /* Wait until SB flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) + { + if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) + { + hi2c->ErrorCode = HAL_I2C_WRONG_START; + } + return HAL_TIMEOUT; + } + + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + { + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); + } + else + { + /* Send header of slave address */ + hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress); + + /* Wait until ADD10 flag is set */ + if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Send slave address */ + hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress); + } + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Master sends target device address for read request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart) +{ + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + uint32_t CurrentXferOptions = hi2c->XferOptions; + + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Generate Start condition if first transfer */ + if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME)) + { + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + } + else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) + { + /* Generate ReStart */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + } + else + { + /* Do nothing */ + } + + /* Wait until SB flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) + { + if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) + { + hi2c->ErrorCode = HAL_I2C_WRONG_START; + } + return HAL_TIMEOUT; + } + + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + { + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress); + } + else + { + /* Send header of slave address */ + hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress); + + /* Wait until ADD10 flag is set */ + if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Send slave address */ + hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress); + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Restart */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Wait until SB flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) + { + if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) + { + hi2c->ErrorCode = HAL_I2C_WRONG_START; + } + return HAL_TIMEOUT; + } + + /* Send header of slave address */ + hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress); + } + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for write request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) +{ + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Wait until SB flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) + { + if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) + { + hi2c->ErrorCode = HAL_I2C_WRONG_START; + } + return HAL_TIMEOUT; + } + + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Wait until TXE flag is set */ + if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + return HAL_ERROR; + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress); + + /* Wait until TXE flag is set */ + if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + return HAL_ERROR; + } + + /* Send LSB of Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); + } + + return HAL_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for read request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) +{ + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Wait until SB flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) + { + if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) + { + hi2c->ErrorCode = HAL_I2C_WRONG_START; + } + return HAL_TIMEOUT; + } + + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Wait until TXE flag is set */ + if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + return HAL_ERROR; + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress); + + /* Wait until TXE flag is set */ + if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + return HAL_ERROR; + } + + /* Send LSB of Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); + } + + /* Wait until TXE flag is set */ + if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + return HAL_ERROR; + } + + /* Generate Restart */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Wait until SB flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) + { + if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) + { + hi2c->ErrorCode = HAL_I2C_WRONG_START; + } + return HAL_TIMEOUT; + } + + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress); + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief DMA I2C process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ + + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + HAL_I2C_StateTypeDef CurrentState = hi2c->State; + HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; + uint32_t CurrentXferOptions = hi2c->XferOptions; + + /* Disable EVT and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* Clear Complete callback */ + if (hi2c->hdmatx != NULL) + { + hi2c->hdmatx->XferCpltCallback = NULL; + } + if (hi2c->hdmarx != NULL) + { + hi2c->hdmarx->XferCpltCallback = NULL; + } + + if ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_TX) == (uint32_t)HAL_I2C_STATE_BUSY_TX) || ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_RX) == (uint32_t)HAL_I2C_STATE_BUSY_RX) && (CurrentMode == HAL_I2C_MODE_SLAVE))) + { + /* Disable DMA Request */ + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + hi2c->XferCount = 0U; + + if (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Set state at HAL_I2C_STATE_LISTEN */ + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + hi2c->State = HAL_I2C_STATE_LISTEN; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveTxCpltCallback(hi2c); +#else + HAL_I2C_SlaveTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else if (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Set state at HAL_I2C_STATE_LISTEN */ + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + hi2c->State = HAL_I2C_STATE_LISTEN; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveRxCpltCallback(hi2c); +#else + HAL_I2C_SlaveRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + /* Do nothing */ + } + + /* Enable EVT and ERR interrupt to treat end of transfer in IRQ handler */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + } + /* Check current Mode, in case of treatment DMA handler have been preempted by a prior interrupt */ + else if (hi2c->Mode != HAL_I2C_MODE_NONE) + { + if (hi2c->XferCount == (uint16_t)1) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + + /* Disable EVT and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* Prepare next transfer or stop current transfer */ + if ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_OTHER_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + + /* Disable Last DMA */ + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); + + /* Disable DMA Request */ + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + hi2c->XferCount = 0U; + + /* Check if Errors has been detected during transfer */ + if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ErrorCallback(hi2c); +#else + HAL_I2C_ErrorCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->State = HAL_I2C_STATE_READY; + + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->PreviousState = I2C_STATE_NONE; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemRxCpltCallback(hi2c); +#else + HAL_I2C_MemRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterRxCpltCallback(hi2c); +#else + HAL_I2C_MasterRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + } + else + { + /* Do nothing */ + } +} + +/** + * @brief DMA I2C communication error callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAError(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ + + /* Clear Complete callback */ + if (hi2c->hdmatx != NULL) + { + hi2c->hdmatx->XferCpltCallback = NULL; + } + if (hi2c->hdmarx != NULL) + { + hi2c->hdmarx->XferCpltCallback = NULL; + } + + /* Ignore DMA FIFO error */ + if (HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE) + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + hi2c->XferCount = 0U; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ErrorCallback(hi2c); +#else + HAL_I2C_ErrorCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA I2C communication abort callback + * (To be called at end of DMA Abort procedure). + * @param hdma DMA handle. + * @retval None + */ +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) +{ + __IO uint32_t count = 0U; + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ + + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + HAL_I2C_StateTypeDef CurrentState = hi2c->State; + + /* During abort treatment, check that there is no pending STOP request */ + /* Wait until STOP flag is reset */ + count = I2C_TIMEOUT_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + if (count == 0U) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + break; + } + count--; + } + while (READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP); + + /* Clear Complete callback */ + if (hi2c->hdmatx != NULL) + { + hi2c->hdmatx->XferCpltCallback = NULL; + } + if (hi2c->hdmarx != NULL) + { + hi2c->hdmarx->XferCpltCallback = NULL; + } + + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + hi2c->XferCount = 0U; + + /* Reset XferAbortCallback */ + if (hi2c->hdmatx != NULL) + { + hi2c->hdmatx->XferAbortCallback = NULL; + } + if (hi2c->hdmarx != NULL) + { + hi2c->hdmarx->XferAbortCallback = NULL; + } + + /* Disable I2C peripheral to prevent dummy data in buffer */ + __HAL_I2C_DISABLE(hi2c); + + /* Check if come from abort from user */ + if (hi2c->State == HAL_I2C_STATE_ABORT) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AbortCpltCallback(hi2c); +#else + HAL_I2C_AbortCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + if (((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + /* Renable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* keep HAL_I2C_STATE_LISTEN */ + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_LISTEN; + } + else + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + } + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ErrorCallback(hi2c); +#else + HAL_I2C_ErrorCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @brief This function handles I2C Communication Timeout. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param Flag specifies the I2C flag to check. + * @param Status The new Flag status (SET or RESET). + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) +{ + /* Wait until flag is set */ + while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for Master addressing phase. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param Flag specifies the I2C flag to check. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + /* Clear AF Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of TXE flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) + { + /* Check if a NACK is detected */ + if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of BTF flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET) + { + /* Check if a NACK is detected */ + if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + { + /* Check if a NACK is detected */ + if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of STOP request through Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnSTOPRequestThroughIT(I2C_HandleTypeDef *hi2c) +{ + __IO uint32_t count = 0U; + + /* Wait until STOP flag is reset */ + count = I2C_TIMEOUT_STOP_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + return HAL_ERROR; + } + } + while (READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP); + + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) + { + /* Check if a STOPF is detected */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + return HAL_OK; +} + +/** + * @brief This function handles Acknowledge failed detection during an I2C Communication. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c) +{ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + { + /* Clear NACKF Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + return HAL_OK; +} + +/** + * @brief Convert I2Cx OTHER_xxx XferOptions to functionnal XferOptions. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c) +{ + /* if user set XferOptions to I2C_OTHER_FRAME */ + /* it request implicitly to generate a restart condition */ + /* set XferOptions to I2C_FIRST_FRAME */ + if (hi2c->XferOptions == I2C_OTHER_FRAME) + { + hi2c->XferOptions = I2C_FIRST_FRAME; + } + /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */ + /* it request implicitly to generate a restart condition */ + /* then generate a stop condition at the end of transfer */ + /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */ + else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME) + { + hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME; + } + else + { + /* Nothing to do */ + } +} + +/** + * @} + */ + +#endif /* HAL_I2C_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c new file mode 100644 index 0000000..ed50332 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c @@ -0,0 +1,184 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_i2c_ex.c + * @author MCD Application Team + * @brief I2C Extension HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of I2C extension peripheral: + * + Extension features functions + * + @verbatim + ============================================================================== + ##### I2C peripheral extension features ##### + ============================================================================== + + [..] Comparing to other previous devices, the I2C interface for STM32F427xx/437xx/ + 429xx/439xx devices contains the following additional features : + + (+) Possibility to disable or enable Analog Noise Filter + (+) Use of a configured Digital Noise Filter + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to configure Noise Filter + (#) Configure I2C Analog noise filter using the function HAL_I2C_AnalogFilter_Config() + (#) Configure I2C Digital noise filter using the function HAL_I2C_DigitalFilter_Config() + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup I2CEx I2CEx + * @brief I2C HAL module driver + * @{ + */ + +#ifdef HAL_I2C_MODULE_ENABLED + +#if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF) +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup I2CEx_Exported_Functions I2C Exported Functions + * @{ + */ + + +/** @defgroup I2CEx_Exported_Functions_Group1 Extension features functions + * @brief Extension features functions + * +@verbatim + =============================================================================== + ##### Extension features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Noise Filters + +@endverbatim + * @{ + */ + +/** + * @brief Configures I2C Analog noise filter. + * @param hi2c pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param AnalogFilter new state of the Analog filter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Reset I2Cx ANOFF bit */ + hi2c->Instance->FLTR &= ~(I2C_FLTR_ANOFF); + + /* Disable the analog filter */ + hi2c->Instance->FLTR |= AnalogFilter; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Configures I2C Digital noise filter. + * @param hi2c pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param DigitalFilter Coefficient of digital noise filter between 0x00 and 0x0F. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) +{ + uint16_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Get the old register value */ + tmpreg = hi2c->Instance->FLTR; + + /* Reset I2Cx DNF bit [3:0] */ + tmpreg &= ~(I2C_FLTR_DNF); + + /* Set I2Cx DNF coefficient */ + tmpreg |= DigitalFilter; + + /* Store the new register value */ + hi2c->Instance->FLTR = tmpreg; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @} + */ + +/** + * @} + */ +#endif + +#endif /* HAL_I2C_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.c new file mode 100644 index 0000000..35e29f8 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.c @@ -0,0 +1,2093 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_i2s.c + * @author MCD Application Team + * @brief I2S HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Integrated Interchip Sound (I2S) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and Errors functions + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + The I2S HAL driver can be used as follow: + + (#) Declare a I2S_HandleTypeDef handle structure. + (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API: + (##) Enable the SPIx interface clock. + (##) I2S pins configuration: + (+++) Enable the clock for the I2S GPIOs. + (+++) Configure these I2S pins as alternate function pull-up. + (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT() + and HAL_I2S_Receive_IT() APIs). + (+++) Configure the I2Sx interrupt priority. + (+++) Enable the NVIC I2S IRQ handle. + (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA() + and HAL_I2S_Receive_DMA() APIs: + (+++) Declare a DMA handle structure for the Tx/Rx Stream/Channel. + (+++) Enable the DMAx interface clock. + (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. + (+++) Configure the DMA Tx/Rx Stream/Channel. + (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle. + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the + DMA Tx/Rx Stream/Channel. + + (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity + using HAL_I2S_Init() function. + + -@- The specific I2S interrupts (Transmission complete interrupt, + RXNE interrupt and Error Interrupts) will be managed using the macros + __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process. + -@- Make sure that either: + (+@) I2S PLL clock is configured or + (+@) External clock source is configured after setting correctly + the define constant EXTERNAL_CLOCK_VALUE in the stm32f4xx_hal_conf.h file. + + (#) Three mode of operations are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Send an amount of data in blocking mode using HAL_I2S_Transmit() + (+) Receive an amount of data in blocking mode using HAL_I2S_Receive() + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT() + (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback + (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_TxCpltCallback + (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT() + (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback + (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_RxCpltCallback + (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2S_ErrorCallback + + *** DMA mode IO operation *** + ============================== + [..] + (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA() + (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback + (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_TxCpltCallback + (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA() + (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback + (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_RxCpltCallback + (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2S_ErrorCallback + (+) Pause the DMA Transfer using HAL_I2S_DMAPause() + (+) Resume the DMA Transfer using HAL_I2S_DMAResume() + (+) Stop the DMA Transfer using HAL_I2S_DMAStop() + In Slave mode, if HAL_I2S_DMAStop is used to stop the communication, an error + HAL_I2S_ERROR_BUSY_LINE_RX is raised as the master continue to transmit data. + In this case __HAL_I2S_FLUSH_RX_DR macro must be used to flush the remaining data + inside DR register and avoid using DeInit/Init process for the next transfer. + + *** I2S HAL driver macros list *** + =================================== + [..] + Below the list of most used macros in I2S HAL driver. + + (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode) + (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode) + (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts + (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts + (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not + + (+) __HAL_I2S_FLUSH_RX_DR: Read DR Register to Flush RX Data + [..] + (@) You can refer to the I2S HAL driver header file for more useful macros + + *** I2S HAL driver macros list *** + =================================== + [..] + Callback registration: + + (#) The compilation flag USE_HAL_I2S_REGISTER_CALLBACKS when set to 1U + allows the user to configure dynamically the driver callbacks. + Use Functions HAL_I2S_RegisterCallback() to register an interrupt callback. + + Function HAL_I2S_RegisterCallback() allows to register following callbacks: + (++) TxCpltCallback : I2S Tx Completed callback + (++) RxCpltCallback : I2S Rx Completed callback + (++) TxRxCpltCallback : I2S TxRx Completed callback + (++) TxHalfCpltCallback : I2S Tx Half Completed callback + (++) RxHalfCpltCallback : I2S Rx Half Completed callback + (++) ErrorCallback : I2S Error callback + (++) MspInitCallback : I2S Msp Init callback + (++) MspDeInitCallback : I2S Msp DeInit callback + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + + (#) Use function HAL_I2S_UnRegisterCallback to reset a callback to the default + weak function. + HAL_I2S_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (++) TxCpltCallback : I2S Tx Completed callback + (++) RxCpltCallback : I2S Rx Completed callback + (++) TxRxCpltCallback : I2S TxRx Completed callback + (++) TxHalfCpltCallback : I2S Tx Half Completed callback + (++) RxHalfCpltCallback : I2S Rx Half Completed callback + (++) ErrorCallback : I2S Error callback + (++) MspInitCallback : I2S Msp Init callback + (++) MspDeInitCallback : I2S Msp DeInit callback + + [..] + By default, after the HAL_I2S_Init() and when the state is HAL_I2S_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_I2S_MasterTxCpltCallback(), HAL_I2S_MasterRxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the HAL_I2S_Init()/ HAL_I2S_DeInit() only when + these callbacks are null (not registered beforehand). + If MspInit or MspDeInit are not null, the HAL_I2S_Init()/ HAL_I2S_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + + [..] + Callbacks can be registered/unregistered in HAL_I2S_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in HAL_I2S_STATE_READY or HAL_I2S_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + Then, the user first registers the MspInit/MspDeInit user callbacks + using HAL_I2S_RegisterCallback() before calling HAL_I2S_DeInit() + or HAL_I2S_Init() function. + + [..] + When the compilation define USE_HAL_I2S_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +#ifdef HAL_I2S_MODULE_ENABLED + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup I2S I2S + * @brief I2S HAL module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define I2S_TIMEOUT_FLAG 100U /*!< Timeout 100 ms */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup I2S_Private_Functions I2S Private Functions + * @{ + */ +static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma); +static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma); +static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma); +static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma); +static void I2S_DMAError(DMA_HandleTypeDef *hdma); +static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s); +static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s); +static void I2S_IRQHandler(I2S_HandleTypeDef *hi2s); +static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State, + uint32_t Timeout); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup I2S_Exported_Functions I2S Exported Functions + * @{ + */ + +/** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + de-initialize the I2Sx peripheral in simplex mode: + + (+) User must Implement HAL_I2S_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + + (+) Call the function HAL_I2S_Init() to configure the selected device with + the selected configuration: + (++) Mode + (++) Standard + (++) Data Format + (++) MCLK Output + (++) Audio frequency + (++) Polarity + (++) Full duplex mode + + (+) Call the function HAL_I2S_DeInit() to restore the default configuration + of the selected I2Sx peripheral. + @endverbatim + * @{ + */ + +/** + * @brief Initializes the I2S according to the specified parameters + * in the I2S_InitTypeDef and create the associated handle. + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) +{ + uint32_t i2sdiv; + uint32_t i2sodd; + uint32_t packetlength; + uint32_t tmp; + uint32_t i2sclk; +#if defined (SPI_I2S_FULLDUPLEX_SUPPORT) + uint16_t tmpreg; +#endif + + /* Check the I2S handle allocation */ + if (hi2s == NULL) + { + return HAL_ERROR; + } + + /* Check the I2S parameters */ + assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance)); + assert_param(IS_I2S_MODE(hi2s->Init.Mode)); + assert_param(IS_I2S_STANDARD(hi2s->Init.Standard)); + assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat)); + assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput)); + assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq)); + assert_param(IS_I2S_CPOL(hi2s->Init.CPOL)); + assert_param(IS_I2S_CLOCKSOURCE(hi2s->Init.ClockSource)); + + if (hi2s->State == HAL_I2S_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hi2s->Lock = HAL_UNLOCKED; + + /* Initialize Default I2S IrqHandler ISR */ + hi2s->IrqHandlerISR = I2S_IRQHandler; + +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + /* Init the I2S Callback settings */ + hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback; /* Legacy weak TxCpltCallback */ + hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback; /* Legacy weak RxCpltCallback */ +#if defined (SPI_I2S_FULLDUPLEX_SUPPORT) + hi2s->TxRxCpltCallback = HAL_I2SEx_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ +#endif + hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ +#if defined (SPI_I2S_FULLDUPLEX_SUPPORT) + hi2s->TxRxHalfCpltCallback = HAL_I2SEx_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */ +#endif + hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */ + + if (hi2s->MspInitCallback == NULL) + { + hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + hi2s->MspInitCallback(hi2s); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_I2S_MspInit(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } + + hi2s->State = HAL_I2S_STATE_BUSY; + + /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/ + /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ + CLEAR_BIT(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \ + SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \ + SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD)); + hi2s->Instance->I2SPR = 0x0002U; + + /*----------------------- I2SPR: I2SDIV and ODD Calculation -----------------*/ + /* If the requested audio frequency is not the default, compute the prescaler */ + if (hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT) + { + /* Check the frame length (For the Prescaler computing) ********************/ + if (hi2s->Init.DataFormat == I2S_DATAFORMAT_16B) + { + /* Packet length is 16 bits */ + packetlength = 16U; + } + else + { + /* Packet length is 32 bits */ + packetlength = 32U; + } + + /* I2S standard */ + if (hi2s->Init.Standard <= I2S_STANDARD_LSB) + { + /* In I2S standard packet lenght is multiplied by 2 */ + packetlength = packetlength * 2U; + } + + /* Get the source clock value **********************************************/ +#if defined(I2S_APB1_APB2_FEATURE) + if (IS_I2S_APB1_INSTANCE(hi2s->Instance)) + { + i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S_APB1); + } + else + { + i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S_APB2); + } +#else + i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S); +#endif + + /* Compute the Real divider depending on the MCLK output state, with a floating point */ + if (hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE) + { + /* MCLK output is enabled */ + if (hi2s->Init.DataFormat != I2S_DATAFORMAT_16B) + { + tmp = (uint32_t)(((((i2sclk / (packetlength * 4U)) * 10U) / hi2s->Init.AudioFreq)) + 5U); + } + else + { + tmp = (uint32_t)(((((i2sclk / (packetlength * 8U)) * 10U) / hi2s->Init.AudioFreq)) + 5U); + } + } + else + { + /* MCLK output is disabled */ + tmp = (uint32_t)(((((i2sclk / packetlength) * 10U) / hi2s->Init.AudioFreq)) + 5U); + } + + /* Remove the flatting point */ + tmp = tmp / 10U; + + /* Check the parity of the divider */ + i2sodd = (uint32_t)(tmp & (uint32_t)1U); + + /* Compute the i2sdiv prescaler */ + i2sdiv = (uint32_t)((tmp - i2sodd) / 2U); + + /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ + i2sodd = (uint32_t)(i2sodd << 8U); + } + else + { + /* Set the default values */ + i2sdiv = 2U; + i2sodd = 0U; + } + + /* Test if the divider is 1 or 0 or greater than 0xFF */ + if ((i2sdiv < 2U) || (i2sdiv > 0xFFU)) + { + /* Set the error code and execute error callback*/ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_PRESCALER); + return HAL_ERROR; + } + + /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/ + + /* Write to SPIx I2SPR register the computed value */ + hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput)); + + /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ + /* And configure the I2S with the I2S_InitStruct values */ + MODIFY_REG(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \ + SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \ + SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \ + SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD), \ + (SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | \ + hi2s->Init.Standard | hi2s->Init.DataFormat | \ + hi2s->Init.CPOL)); + +#if defined(SPI_I2SCFGR_ASTRTEN) + if ((hi2s->Init.Standard == I2S_STANDARD_PCM_SHORT) || ((hi2s->Init.Standard == I2S_STANDARD_PCM_LONG))) + { + /* Write to SPIx I2SCFGR */ + SET_BIT(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_ASTRTEN); + } +#endif /* SPI_I2SCFGR_ASTRTEN */ + +#if defined (SPI_I2S_FULLDUPLEX_SUPPORT) + + /* Configure the I2S extended if the full duplex mode is enabled */ + assert_param(IS_I2S_FULLDUPLEX_MODE(hi2s->Init.FullDuplexMode)); + + if (hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE) + { + /* Set FullDuplex I2S IrqHandler ISR if FULLDUPLEXMODE is enabled */ + hi2s->IrqHandlerISR = HAL_I2SEx_FullDuplex_IRQHandler; + + /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ + CLEAR_BIT(I2SxEXT(hi2s->Instance)->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \ + SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \ + SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD)); + I2SxEXT(hi2s->Instance)->I2SPR = 2U; + + /* Get the I2SCFGR register value */ + tmpreg = I2SxEXT(hi2s->Instance)->I2SCFGR; + + /* Get the mode to be configured for the extended I2S */ + if ((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX)) + { + tmp = I2S_MODE_SLAVE_RX; + } + else /* I2S_MODE_MASTER_RX || I2S_MODE_SLAVE_RX */ + { + tmp = I2S_MODE_SLAVE_TX; + } + + /* Configure the I2S Slave with the I2S Master parameter values */ + tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(tmp | \ + (uint16_t)(hi2s->Init.Standard | (uint16_t)(hi2s->Init.DataFormat | \ + (uint16_t)hi2s->Init.CPOL)))); + + /* Write to SPIx I2SCFGR */ + WRITE_REG(I2SxEXT(hi2s->Instance)->I2SCFGR, tmpreg); + } +#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */ + + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + hi2s->State = HAL_I2S_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the I2S peripheral + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) +{ + /* Check the I2S handle allocation */ + if (hi2s == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance)); + + hi2s->State = HAL_I2S_STATE_BUSY; + + /* Disable the I2S Peripheral Clock */ + __HAL_I2S_DISABLE(hi2s); + +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + if (hi2s->MspDeInitCallback == NULL) + { + hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + hi2s->MspDeInitCallback(hi2s); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + HAL_I2S_MspDeInit(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + hi2s->State = HAL_I2S_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hi2s); + + return HAL_OK; +} + +/** + * @brief I2S MSP Init + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +__weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2s); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2S_MspInit could be implemented in the user file + */ +} + +/** + * @brief I2S MSP DeInit + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +__weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2s); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2S_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) +/** + * @brief Register a User I2S Callback + * To be used instead of the weak predefined callback + * @param hi2s Pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for the specified I2S. + * @param CallbackID ID of the callback to be registered + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, + pI2S_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hi2s->ErrorCode |= HAL_I2S_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hi2s); + + if (HAL_I2S_STATE_READY == hi2s->State) + { + switch (CallbackID) + { + case HAL_I2S_TX_COMPLETE_CB_ID : + hi2s->TxCpltCallback = pCallback; + break; + + case HAL_I2S_RX_COMPLETE_CB_ID : + hi2s->RxCpltCallback = pCallback; + break; + +#if defined (SPI_I2S_FULLDUPLEX_SUPPORT) + case HAL_I2S_TX_RX_COMPLETE_CB_ID : + hi2s->TxRxCpltCallback = pCallback; + break; +#endif + + case HAL_I2S_TX_HALF_COMPLETE_CB_ID : + hi2s->TxHalfCpltCallback = pCallback; + break; + + case HAL_I2S_RX_HALF_COMPLETE_CB_ID : + hi2s->RxHalfCpltCallback = pCallback; + break; + +#if defined (SPI_I2S_FULLDUPLEX_SUPPORT) + case HAL_I2S_TX_RX_HALF_COMPLETE_CB_ID : + hi2s->TxRxHalfCpltCallback = pCallback; + break; +#endif + + case HAL_I2S_ERROR_CB_ID : + hi2s->ErrorCallback = pCallback; + break; + + case HAL_I2S_MSPINIT_CB_ID : + hi2s->MspInitCallback = pCallback; + break; + + case HAL_I2S_MSPDEINIT_CB_ID : + hi2s->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_I2S_STATE_RESET == hi2s->State) + { + switch (CallbackID) + { + case HAL_I2S_MSPINIT_CB_ID : + hi2s->MspInitCallback = pCallback; + break; + + case HAL_I2S_MSPDEINIT_CB_ID : + hi2s->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2s); + return status; +} + +/** + * @brief Unregister an I2S Callback + * I2S callback is redirected to the weak predefined callback + * @param hi2s Pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for the specified I2S. + * @param CallbackID ID of the callback to be unregistered + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hi2s); + + if (HAL_I2S_STATE_READY == hi2s->State) + { + switch (CallbackID) + { + case HAL_I2S_TX_COMPLETE_CB_ID : + hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_I2S_RX_COMPLETE_CB_ID : + hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + +#if defined (SPI_I2S_FULLDUPLEX_SUPPORT) + case HAL_I2S_TX_RX_COMPLETE_CB_ID : + hi2s->TxRxCpltCallback = HAL_I2SEx_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ + break; +#endif + + case HAL_I2S_TX_HALF_COMPLETE_CB_ID : + hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + break; + + case HAL_I2S_RX_HALF_COMPLETE_CB_ID : + hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + break; + +#if defined (SPI_I2S_FULLDUPLEX_SUPPORT) + case HAL_I2S_TX_RX_HALF_COMPLETE_CB_ID : + hi2s->TxRxHalfCpltCallback = HAL_I2SEx_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */ + break; +#endif + + case HAL_I2S_ERROR_CB_ID : + hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_I2S_MSPINIT_CB_ID : + hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_I2S_MSPDEINIT_CB_ID : + hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_I2S_STATE_RESET == hi2s->State) + { + switch (CallbackID) + { + case HAL_I2S_MSPINIT_CB_ID : + hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_I2S_MSPDEINIT_CB_ID : + hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2s); + return status; +} +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup I2S_Exported_Functions_Group2 IO operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the I2S data + transfers. + + (#) There are two modes of transfer: + (++) Blocking mode : The communication is performed in the polling mode. + The status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode : The communication is performed using Interrupts + or DMA. These functions return the status of the transfer startup. + The end of the data processing will be indicated through the + dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + + (#) Blocking mode functions are : + (++) HAL_I2S_Transmit() + (++) HAL_I2S_Receive() + + (#) No-Blocking mode functions with Interrupt are : + (++) HAL_I2S_Transmit_IT() + (++) HAL_I2S_Receive_IT() + + (#) No-Blocking mode functions with DMA are : + (++) HAL_I2S_Transmit_DMA() + (++) HAL_I2S_Receive_DMA() + + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (++) HAL_I2S_TxCpltCallback() + (++) HAL_I2S_RxCpltCallback() + (++) HAL_I2S_ErrorCallback() + +@endverbatim + * @{ + */ + +/** + * @brief Transmit an amount of data in blocking mode + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @param pData a 16-bit pointer to data buffer. + * @param Size number of data sample to be sent: + * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S + * configuration phase, the Size parameter means the number of 16-bit data length + * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected + * the Size parameter means the number of 16-bit data length. + * @param Timeout Timeout duration + * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization + * between Master and Slave(example: audio streaming). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tmpreg_cfgr; + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2s); + + if (hi2s->State != HAL_I2S_STATE_READY) + { + __HAL_UNLOCK(hi2s); + return HAL_BUSY; + } + + /* Set state and reset error code */ + hi2s->State = HAL_I2S_STATE_BUSY_TX; + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + hi2s->pTxBuffPtr = pData; + + tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); + + if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B)) + { + hi2s->TxXferSize = (Size << 1U); + hi2s->TxXferCount = (Size << 1U); + } + else + { + hi2s->TxXferSize = Size; + hi2s->TxXferCount = Size; + } + + tmpreg_cfgr = hi2s->Instance->I2SCFGR; + + /* Check if the I2S is already enabled */ + if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + + /* Wait until TXE flag is set */ + if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK) + { + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); + hi2s->State = HAL_I2S_STATE_READY; + __HAL_UNLOCK(hi2s); + return HAL_ERROR; + } + + while (hi2s->TxXferCount > 0U) + { + hi2s->Instance->DR = (*hi2s->pTxBuffPtr); + hi2s->pTxBuffPtr++; + hi2s->TxXferCount--; + + /* Wait until TXE flag is set */ + if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK) + { + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); + hi2s->State = HAL_I2S_STATE_READY; + __HAL_UNLOCK(hi2s); + return HAL_ERROR; + } + + /* Check if an underrun occurs */ + if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET) + { + /* Clear underrun flag */ + __HAL_I2S_CLEAR_UDRFLAG(hi2s); + + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR); + } + } + + /* Check if Slave mode is selected */ + if (((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) + || ((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX)) + { + /* Wait until Busy flag is reset */ + if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, Timeout) != HAL_OK) + { + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); + hi2s->State = HAL_I2S_STATE_READY; + __HAL_UNLOCK(hi2s); + return HAL_ERROR; + } + } + + hi2s->State = HAL_I2S_STATE_READY; + __HAL_UNLOCK(hi2s); + return HAL_OK; +} + +/** + * @brief Receive an amount of data in blocking mode + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @param pData a 16-bit pointer to data buffer. + * @param Size number of data sample to be sent: + * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S + * configuration phase, the Size parameter means the number of 16-bit data length + * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected + * the Size parameter means the number of 16-bit data length. + * @param Timeout Timeout duration + * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization + * between Master and Slave(example: audio streaming). + * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate + * in continuous way and as the I2S is not disabled at the end of the I2S transaction. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tmpreg_cfgr; + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2s); + + if (hi2s->State != HAL_I2S_STATE_READY) + { + __HAL_UNLOCK(hi2s); + return HAL_BUSY; + } + + /* Set state and reset error code */ + hi2s->State = HAL_I2S_STATE_BUSY_RX; + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + hi2s->pRxBuffPtr = pData; + + tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); + + if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B)) + { + hi2s->RxXferSize = (Size << 1U); + hi2s->RxXferCount = (Size << 1U); + } + else + { + hi2s->RxXferSize = Size; + hi2s->RxXferCount = Size; + } + + /* Check if the I2S is already enabled */ + if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + + /* Check if Master Receiver mode is selected */ + if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX) + { + /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read + access to the SPI_SR register. */ + __HAL_I2S_CLEAR_OVRFLAG(hi2s); + } + + /* Receive data */ + while (hi2s->RxXferCount > 0U) + { + /* Wait until RXNE flag is set */ + if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout) != HAL_OK) + { + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); + hi2s->State = HAL_I2S_STATE_READY; + __HAL_UNLOCK(hi2s); + return HAL_ERROR; + } + + (*hi2s->pRxBuffPtr) = (uint16_t)hi2s->Instance->DR; + hi2s->pRxBuffPtr++; + hi2s->RxXferCount--; + + /* Check if an overrun occurs */ + if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET) + { + /* Clear overrun flag */ + __HAL_I2S_CLEAR_OVRFLAG(hi2s); + + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR); + } + } + + hi2s->State = HAL_I2S_STATE_READY; + __HAL_UNLOCK(hi2s); + return HAL_OK; +} + +/** + * @brief Transmit an amount of data in non-blocking mode with Interrupt + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @param pData a 16-bit pointer to data buffer. + * @param Size number of data sample to be sent: + * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S + * configuration phase, the Size parameter means the number of 16-bit data length + * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected + * the Size parameter means the number of 16-bit data length. + * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization + * between Master and Slave(example: audio streaming). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) +{ + uint32_t tmpreg_cfgr; + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2s); + + if (hi2s->State != HAL_I2S_STATE_READY) + { + __HAL_UNLOCK(hi2s); + return HAL_BUSY; + } + + /* Set state and reset error code */ + hi2s->State = HAL_I2S_STATE_BUSY_TX; + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + hi2s->pTxBuffPtr = pData; + + tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); + + if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B)) + { + hi2s->TxXferSize = (Size << 1U); + hi2s->TxXferCount = (Size << 1U); + } + else + { + hi2s->TxXferSize = Size; + hi2s->TxXferCount = Size; + } + + /* Enable TXE and ERR interrupt */ + __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); + + /* Check if the I2S is already enabled */ + if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + + __HAL_UNLOCK(hi2s); + return HAL_OK; +} + +/** + * @brief Receive an amount of data in non-blocking mode with Interrupt + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @param pData a 16-bit pointer to the Receive data buffer. + * @param Size number of data sample to be sent: + * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S + * configuration phase, the Size parameter means the number of 16-bit data length + * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected + * the Size parameter means the number of 16-bit data length. + * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization + * between Master and Slave(example: audio streaming). + * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronization + * between Master and Slave otherwise the I2S interrupt should be optimized. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) +{ + uint32_t tmpreg_cfgr; + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2s); + + if (hi2s->State != HAL_I2S_STATE_READY) + { + __HAL_UNLOCK(hi2s); + return HAL_BUSY; + } + + /* Set state and reset error code */ + hi2s->State = HAL_I2S_STATE_BUSY_RX; + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + hi2s->pRxBuffPtr = pData; + + tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); + + if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B)) + { + hi2s->RxXferSize = (Size << 1U); + hi2s->RxXferCount = (Size << 1U); + } + else + { + hi2s->RxXferSize = Size; + hi2s->RxXferCount = Size; + } + + /* Enable RXNE and ERR interrupt */ + __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); + + /* Check if the I2S is already enabled */ + if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + + __HAL_UNLOCK(hi2s); + return HAL_OK; +} + +/** + * @brief Transmit an amount of data in non-blocking mode with DMA + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @param pData a 16-bit pointer to the Transmit data buffer. + * @param Size number of data sample to be sent: + * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S + * configuration phase, the Size parameter means the number of 16-bit data length + * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected + * the Size parameter means the number of 16-bit data length. + * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization + * between Master and Slave(example: audio streaming). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) +{ + uint32_t tmpreg_cfgr; + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2s); + + if (hi2s->State != HAL_I2S_STATE_READY) + { + __HAL_UNLOCK(hi2s); + return HAL_BUSY; + } + + /* Set state and reset error code */ + hi2s->State = HAL_I2S_STATE_BUSY_TX; + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + hi2s->pTxBuffPtr = pData; + + tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); + + if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B)) + { + hi2s->TxXferSize = (Size << 1U); + hi2s->TxXferCount = (Size << 1U); + } + else + { + hi2s->TxXferSize = Size; + hi2s->TxXferCount = Size; + } + + /* Set the I2S Tx DMA Half transfer complete callback */ + hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt; + + /* Set the I2S Tx DMA transfer complete callback */ + hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt; + + /* Set the DMA error callback */ + hi2s->hdmatx->XferErrorCallback = I2S_DMAError; + + /* Enable the Tx DMA Stream/Channel */ + if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmatx, + (uint32_t)hi2s->pTxBuffPtr, + (uint32_t)&hi2s->Instance->DR, + hi2s->TxXferSize)) + { + /* Update SPI error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); + hi2s->State = HAL_I2S_STATE_READY; + + __HAL_UNLOCK(hi2s); + return HAL_ERROR; + } + + /* Check if the I2S is already enabled */ + if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + + /* Check if the I2S Tx request is already enabled */ + if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_TXDMAEN)) + { + /* Enable Tx DMA Request */ + SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); + } + + __HAL_UNLOCK(hi2s); + return HAL_OK; +} + +/** + * @brief Receive an amount of data in non-blocking mode with DMA + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @param pData a 16-bit pointer to the Receive data buffer. + * @param Size number of data sample to be sent: + * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S + * configuration phase, the Size parameter means the number of 16-bit data length + * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected + * the Size parameter means the number of 16-bit data length. + * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization + * between Master and Slave(example: audio streaming). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) +{ + uint32_t tmpreg_cfgr; + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2s); + + if (hi2s->State != HAL_I2S_STATE_READY) + { + __HAL_UNLOCK(hi2s); + return HAL_BUSY; + } + + /* Set state and reset error code */ + hi2s->State = HAL_I2S_STATE_BUSY_RX; + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + hi2s->pRxBuffPtr = pData; + + tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); + + if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B)) + { + hi2s->RxXferSize = (Size << 1U); + hi2s->RxXferCount = (Size << 1U); + } + else + { + hi2s->RxXferSize = Size; + hi2s->RxXferCount = Size; + } + + /* Set the I2S Rx DMA Half transfer complete callback */ + hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt; + + /* Set the I2S Rx DMA transfer complete callback */ + hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt; + + /* Set the DMA error callback */ + hi2s->hdmarx->XferErrorCallback = I2S_DMAError; + + /* Check if Master Receiver mode is selected */ + if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX) + { + /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read + access to the SPI_SR register. */ + __HAL_I2S_CLEAR_OVRFLAG(hi2s); + } + + /* Enable the Rx DMA Stream/Channel */ + if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr, + hi2s->RxXferSize)) + { + /* Update SPI error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); + hi2s->State = HAL_I2S_STATE_READY; + + __HAL_UNLOCK(hi2s); + return HAL_ERROR; + } + + /* Check if the I2S is already enabled */ + if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + + /* Check if the I2S Rx request is already enabled */ + if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_RXDMAEN)) + { + /* Enable Rx DMA Request */ + SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); + } + + __HAL_UNLOCK(hi2s); + return HAL_OK; +} + +/** + * @brief Pauses the audio DMA Stream/Channel playing from the Media. + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s) +{ + /* Process Locked */ + __HAL_LOCK(hi2s); + + if (hi2s->State == HAL_I2S_STATE_BUSY_TX) + { + /* Disable the I2S DMA Tx request */ + CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); + } + else if (hi2s->State == HAL_I2S_STATE_BUSY_RX) + { + /* Disable the I2S DMA Rx request */ + CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); + } +#if defined (SPI_I2S_FULLDUPLEX_SUPPORT) + else if (hi2s->State == HAL_I2S_STATE_BUSY_TX_RX) + { + /* Pause the audio file playing by disabling the I2S DMA request */ + CLEAR_BIT(hi2s->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN)); + CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN)); + } +#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */ + else + { + /* nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); + + return HAL_OK; +} + +/** + * @brief Resumes the audio DMA Stream/Channel playing from the Media. + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s) +{ + /* Process Locked */ + __HAL_LOCK(hi2s); + + if (hi2s->State == HAL_I2S_STATE_BUSY_TX) + { + /* Enable the I2S DMA Tx request */ + SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); + } + else if (hi2s->State == HAL_I2S_STATE_BUSY_RX) + { + /* Enable the I2S DMA Rx request */ + SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); + } +#if defined (SPI_I2S_FULLDUPLEX_SUPPORT) + else if (hi2s->State == HAL_I2S_STATE_BUSY_TX_RX) + { + /* Pause the audio file playing by disabling the I2S DMA request */ + SET_BIT(hi2s->Instance->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN)); + SET_BIT(I2SxEXT(hi2s->Instance)->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN)); + + /* If the I2Sext peripheral is still not enabled, enable it */ + if ((I2SxEXT(hi2s->Instance)->I2SCFGR & SPI_I2SCFGR_I2SE) == 0U) + { + /* Enable I2Sext peripheral */ + __HAL_I2SEXT_ENABLE(hi2s); + } + } +#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */ + else + { + /* nothing to do */ + } + + /* If the I2S peripheral is still not enabled, enable it */ + if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); + + return HAL_OK; +} + +/** + * @brief Stops the audio DMA Stream/Channel playing from the Media. + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s) +{ +#if defined (SPI_I2S_FULLDUPLEX_SUPPORT) + uint32_t tickstart; +#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */ + HAL_StatusTypeDef errorcode = HAL_OK; + /* The Lock is not implemented on this API to allow the user application + to call the HAL SPI API under callbacks HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback() + when calling HAL_DMA_Abort() API the DMA TX or RX Transfer complete interrupt is generated + and the correspond call back is executed HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback() + */ + + if ((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX)) + { + /* Abort the I2S DMA tx Stream/Channel */ + if (hi2s->hdmatx != NULL) + { + /* Disable the I2S DMA tx Stream/Channel */ + if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx)) + { + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); + errorcode = HAL_ERROR; + } + } + + /* Wait until TXE flag is set */ + if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, I2S_TIMEOUT_FLAG) != HAL_OK) + { + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); + hi2s->State = HAL_I2S_STATE_READY; + errorcode = HAL_ERROR; + } + + /* Wait until BSY flag is Reset */ + if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, I2S_TIMEOUT_FLAG) != HAL_OK) + { + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); + hi2s->State = HAL_I2S_STATE_READY; + errorcode = HAL_ERROR; + } + + /* Disable I2S peripheral */ + __HAL_I2S_DISABLE(hi2s); + + /* Clear UDR flag */ + __HAL_I2S_CLEAR_UDRFLAG(hi2s); + + /* Disable the I2S Tx DMA requests */ + CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); + +#if defined (SPI_I2S_FULLDUPLEX_SUPPORT) + + if (hi2s->State == HAL_I2S_STATE_BUSY_TX_RX) + { + /* Abort the I2S DMA rx Stream/Channel */ + if (hi2s->hdmarx != NULL) + { + /* Disable the I2S DMA rx Stream/Channel */ + if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx)) + { + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); + errorcode = HAL_ERROR; + } + } + + /* Disable I2Sext peripheral */ + __HAL_I2SEXT_DISABLE(hi2s); + + /* Clear OVR flag */ + __HAL_I2SEXT_CLEAR_OVRFLAG(hi2s); + + /* Disable the I2SxEXT DMA request */ + CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_RXDMAEN); + + if (hi2s->Init.Mode == I2S_MODE_SLAVE_TX) + { + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_BUSY_LINE_RX); + + /* Set the I2S State ready */ + hi2s->State = HAL_I2S_STATE_READY; + errorcode = HAL_ERROR; + } + else + { + /* Read DR to Flush RX Data */ + READ_REG(I2SxEXT(hi2s->Instance)->DR); + } + } +#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */ + } + + else if ((hi2s->Init.Mode == I2S_MODE_MASTER_RX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_RX)) + { + /* Abort the I2S DMA rx Stream/Channel */ + if (hi2s->hdmarx != NULL) + { + /* Disable the I2S DMA rx Stream/Channel */ + if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx)) + { + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); + errorcode = HAL_ERROR; + } + } +#if defined (SPI_I2S_FULLDUPLEX_SUPPORT) + + if (hi2s->State == HAL_I2S_STATE_BUSY_TX_RX) + { + /* Abort the I2S DMA tx Stream/Channel */ + if (hi2s->hdmatx != NULL) + { + /* Disable the I2S DMA tx Stream/Channel */ + if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx)) + { + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); + errorcode = HAL_ERROR; + } + } + + tickstart = HAL_GetTick(); + + /* Wait until TXE flag is set */ + while (__HAL_I2SEXT_GET_FLAG(hi2s, I2S_FLAG_TXE) != SET) + { + if (((HAL_GetTick() - tickstart) > I2S_TIMEOUT_FLAG)) + { + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); + + /* Set the I2S State ready */ + hi2s->State = HAL_I2S_STATE_READY; + errorcode = HAL_ERROR; + } + } + + /* Wait until BSY flag is Reset */ + while (__HAL_I2SEXT_GET_FLAG(hi2s, I2S_FLAG_BSY) != RESET) + { + if (((HAL_GetTick() - tickstart) > I2S_TIMEOUT_FLAG)) + { + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); + + /* Set the I2S State ready */ + hi2s->State = HAL_I2S_STATE_READY; + errorcode = HAL_ERROR; + } + } + + /* Disable I2Sext peripheral */ + __HAL_I2SEXT_DISABLE(hi2s); + + /* Clear UDR flag */ + __HAL_I2SEXT_CLEAR_UDRFLAG(hi2s); + + /* Disable the I2SxEXT DMA request */ + CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_TXDMAEN); + } +#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */ + + /* Disable I2S peripheral */ + __HAL_I2S_DISABLE(hi2s); + + /* Clear OVR flag */ + __HAL_I2S_CLEAR_OVRFLAG(hi2s); + + /* Disable the I2S Rx DMA request */ + CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); + + if (hi2s->Init.Mode == I2S_MODE_SLAVE_RX) + { + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_BUSY_LINE_RX); + + /* Set the I2S State ready */ + hi2s->State = HAL_I2S_STATE_READY; + errorcode = HAL_ERROR; + } + else + { + /* Read DR to Flush RX Data */ + READ_REG((hi2s->Instance)->DR); + } + } + + hi2s->State = HAL_I2S_STATE_READY; + + return errorcode; +} + +/** + * @brief This function handles I2S interrupt request. + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) +{ + /* Call the IrqHandler ISR set during HAL_I2S_INIT */ + hi2s->IrqHandlerISR(hi2s); +} + +/** + * @brief Tx Transfer Half completed callbacks + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +__weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2s); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2S_TxHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Tx Transfer completed callbacks + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +__weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2s); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2S_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Transfer half completed callbacks + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +__weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2s); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2S_RxHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callbacks + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +__weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2s); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2S_RxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief I2S error callbacks + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +__weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2s); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2S_ErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the I2S state + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval HAL state + */ +HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s) +{ + return hi2s->State; +} + +/** + * @brief Return the I2S error code + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval I2S Error Code + */ +uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s) +{ + return hi2s->ErrorCode; +} +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup I2S_Private_Functions I2S Private Functions + * @{ + */ +/** + * @brief DMA I2S transmit process complete callback + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma) +{ + I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ + + /* if DMA is configured in DMA_NORMAL Mode */ + if (hdma->Init.Mode == DMA_NORMAL) + { + /* Disable Tx DMA Request */ + CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); + + hi2s->TxXferCount = 0U; + hi2s->State = HAL_I2S_STATE_READY; + } + /* Call user Tx complete callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + hi2s->TxCpltCallback(hi2s); +#else + HAL_I2S_TxCpltCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA I2S transmit process half complete callback + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma) +{ + I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ + + /* Call user Tx half complete callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + hi2s->TxHalfCpltCallback(hi2s); +#else + HAL_I2S_TxHalfCpltCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA I2S receive process complete callback + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma) +{ + I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ + + /* if DMA is configured in DMA_NORMAL Mode */ + if (hdma->Init.Mode == DMA_NORMAL) + { + /* Disable Rx DMA Request */ + CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); + hi2s->RxXferCount = 0U; + hi2s->State = HAL_I2S_STATE_READY; + } + /* Call user Rx complete callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + hi2s->RxCpltCallback(hi2s); +#else + HAL_I2S_RxCpltCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA I2S receive process half complete callback + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma) +{ + I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ + + /* Call user Rx half complete callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + hi2s->RxHalfCpltCallback(hi2s); +#else + HAL_I2S_RxHalfCpltCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA I2S communication error callback + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void I2S_DMAError(DMA_HandleTypeDef *hdma) +{ + I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ + + /* Disable Rx and Tx DMA Request */ + CLEAR_BIT(hi2s->Instance->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN)); + hi2s->TxXferCount = 0U; + hi2s->RxXferCount = 0U; + + hi2s->State = HAL_I2S_STATE_READY; + + /* Set the error code and execute error callback*/ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); + /* Call user error callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + hi2s->ErrorCallback(hi2s); +#else + HAL_I2S_ErrorCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +} + +/** + * @brief Transmit an amount of data in non-blocking mode with Interrupt + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s) +{ + /* Transmit data */ + hi2s->Instance->DR = (*hi2s->pTxBuffPtr); + hi2s->pTxBuffPtr++; + hi2s->TxXferCount--; + + if (hi2s->TxXferCount == 0U) + { + /* Disable TXE and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); + + hi2s->State = HAL_I2S_STATE_READY; + /* Call user Tx complete callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + hi2s->TxCpltCallback(hi2s); +#else + HAL_I2S_TxCpltCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Receive an amount of data in non-blocking mode with Interrupt + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s) +{ + /* Receive data */ + (*hi2s->pRxBuffPtr) = (uint16_t)hi2s->Instance->DR; + hi2s->pRxBuffPtr++; + hi2s->RxXferCount--; + + if (hi2s->RxXferCount == 0U) + { + /* Disable RXNE and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); + + hi2s->State = HAL_I2S_STATE_READY; + /* Call user Rx complete callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + hi2s->RxCpltCallback(hi2s); +#else + HAL_I2S_RxCpltCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } +} + +/** + * @brief This function handles I2S interrupt request. + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +static void I2S_IRQHandler(I2S_HandleTypeDef *hi2s) +{ + __IO uint32_t i2ssr = hi2s->Instance->SR; + + if (hi2s->State == HAL_I2S_STATE_BUSY_RX) + { + /* I2S in mode Receiver ------------------------------------------------*/ + if (((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET)) + { + I2S_Receive_IT(hi2s); + } + + /* I2S Overrun error interrupt occurred -------------------------------------*/ + if (((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) + { + /* Disable RXNE and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); + + /* Clear Overrun flag */ + __HAL_I2S_CLEAR_OVRFLAG(hi2s); + + /* Set the I2S State ready */ + hi2s->State = HAL_I2S_STATE_READY; + + + /* Set the error code and execute error callback*/ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR); + /* Call user error callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + hi2s->ErrorCallback(hi2s); +#else + HAL_I2S_ErrorCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } + } + + if (hi2s->State == HAL_I2S_STATE_BUSY_TX) + { + /* I2S in mode Transmitter -----------------------------------------------*/ + if (((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET)) + { + I2S_Transmit_IT(hi2s); + } + + /* I2S Underrun error interrupt occurred --------------------------------*/ + if (((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) + { + /* Disable TXE and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); + + /* Clear Underrun flag */ + __HAL_I2S_CLEAR_UDRFLAG(hi2s); + + /* Set the I2S State ready */ + hi2s->State = HAL_I2S_STATE_READY; + + /* Set the error code and execute error callback*/ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR); + /* Call user error callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + hi2s->ErrorCallback(hi2s); +#else + HAL_I2S_ErrorCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } + } +} + +/** + * @brief This function handles I2S Communication Timeout. + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @param Flag Flag checked + * @param State Value of the flag expected + * @param Timeout Duration of the timeout + * @retval HAL status + */ +static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State, + uint32_t Timeout) +{ + uint32_t tickstart; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until flag is set to status*/ + while (((__HAL_I2S_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Set the I2S State ready */ + hi2s->State = HAL_I2S_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); + + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_I2S_MODULE_ENABLED */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.c new file mode 100644 index 0000000..791c219 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.c @@ -0,0 +1,1156 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_i2s_ex.c + * @author MCD Application Team + * @brief I2S HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of I2S extension peripheral: + * + Extension features Functions + * + @verbatim + ============================================================================== + ##### I2S Extension features ##### + ============================================================================== + [..] + (#) In I2S full duplex mode, each SPI peripheral is able to manage sending and receiving + data simultaneously using two data lines. Each SPI peripheral has an extended block + called I2Sxext (i.e I2S2ext for SPI2 and I2S3ext for SPI3). + (#) The extension block is not a full SPI IP, it is used only as I2S slave to + implement full duplex mode. The extension block uses the same clock sources + as its master. + + (#) Both I2Sx and I2Sx_ext can be configured as transmitters or receivers. + + [..] + (@) Only I2Sx can deliver SCK and WS to I2Sx_ext in full duplex mode, where + I2Sx can be I2S2 or I2S3. + + ##### How to use this driver ##### + =============================================================================== + [..] + Three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Send and receive in the same time an amount of data in blocking mode using HAL_I2SEx_TransmitReceive() + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Send and receive in the same time an amount of data in non blocking mode using HAL_I2SEx_TransmitReceive_IT() + (+) At transmission/reception end of transfer HAL_I2SEx_TxRxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2SEx_TxRxCpltCallback + (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2S_ErrorCallback + + *** DMA mode IO operation *** + ============================== + [..] + (+) Send and receive an amount of data in non blocking mode (DMA) using HAL_I2SEx_TransmitReceive_DMA() + (+) At transmission/reception end of transfer HAL_I2SEx_TxRxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_TxRxCpltCallback + (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2S_ErrorCallback + (+) __HAL_I2SEXT_FLUSH_RX_DR: In Full-Duplex Slave mode, if HAL_I2S_DMAStop is used to stop the + communication, an error HAL_I2S_ERROR_BUSY_LINE_RX is raised as the master continue to transmit data. + In this case __HAL_I2SEXT_FLUSH_RX_DR macro must be used to flush the remaining data + inside I2Sx and I2Sx_ext DR registers and avoid using DeInit/Init process for the next transfer. + @endverbatim + + Additional Figure: The Extended block uses the same clock sources as its master. + + +-----------------------+ + I2Sx_SCK | | + ----------+-->| I2Sx |------------------->I2Sx_SD(in/out) + +--|-->| | + | | +-----------------------+ + | | + I2S_WS | | + ------>| | + | | +-----------------------+ + | +-->| | + | | I2Sx_ext |------------------->I2Sx_extSD(in/out) + +----->| | + +-----------------------+ + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +#ifdef HAL_I2S_MODULE_ENABLED + +/** @defgroup I2SEx I2SEx + * @brief I2S Extended HAL module driver + * @{ + */ + +#if defined (SPI_I2S_FULLDUPLEX_SUPPORT) + +/* Private typedef -----------------------------------------------------------*/ +/** @defgroup I2SEx_Private_Typedef I2S Extended Private Typedef + * @{ + */ +typedef enum +{ + I2S_USE_I2S = 0x00U, /*!< I2Sx should be used */ + I2S_USE_I2SEXT = 0x01U, /*!< I2Sx_ext should be used */ +} I2S_UseTypeDef; +/** + * @} + */ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup I2SEx_Private_Functions I2S Extended Private Functions + * @{ + */ +static void I2SEx_TxRxDMAHalfCplt(DMA_HandleTypeDef *hdma); +static void I2SEx_TxRxDMACplt(DMA_HandleTypeDef *hdma); +static void I2SEx_TxRxDMAError(DMA_HandleTypeDef *hdma); +static void I2SEx_RxISR_I2S(I2S_HandleTypeDef *hi2s); +static void I2SEx_RxISR_I2SExt(I2S_HandleTypeDef *hi2s); +static void I2SEx_TxISR_I2S(I2S_HandleTypeDef *hi2s); +static void I2SEx_TxISR_I2SExt(I2S_HandleTypeDef *hi2s); +static HAL_StatusTypeDef I2SEx_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, + uint32_t State, uint32_t Timeout, I2S_UseTypeDef i2sUsed); +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup I2SEx I2SEx + * @{ + */ + +/** @addtogroup I2SEx_Exported_Functions I2S Extended Exported Functions + * @{ + */ + +/** @defgroup I2SEx_Exported_Functions_Group1 I2S Extended IO operation functions + * @brief I2SEx IO operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the I2S data + transfers. + + (#) There are two modes of transfer: + (++) Blocking mode : The communication is performed in the polling mode. + The status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode : The communication is performed using Interrupts + or DMA. These functions return the status of the transfer startup. + The end of the data processing will be indicated through the + dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + + (#) Blocking mode functions are : + (++) HAL_I2SEx_TransmitReceive() + + (#) No-Blocking mode functions with Interrupt are : + (++) HAL_I2SEx_TransmitReceive_IT() + (++) HAL_I2SEx_FullDuplex_IRQHandler() + + (#) No-Blocking mode functions with DMA are : + (++) HAL_I2SEx_TransmitReceive_DMA() + + (#) A set of Transfer Complete Callback are provided in non Blocking mode: + (++) HAL_I2SEx_TxRxCpltCallback() +@endverbatim + * @{ + */ +/** + * @brief Full-Duplex Transmit/Receive data in blocking mode. + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @param pTxData a 16-bit pointer to the Transmit data buffer. + * @param pRxData a 16-bit pointer to the Receive data buffer. + * @param Size number of data sample to be sent: + * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S + * configuration phase, the Size parameter means the number of 16-bit data length + * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected + * the Size parameter means the number of 16-bit data length. + * @param Timeout Timeout duration + * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization + * between Master and Slave(example: audio streaming). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, + uint16_t Size, uint32_t Timeout) +{ + uint32_t tmp1 = 0U; + HAL_StatusTypeDef errorcode = HAL_OK; + + if (hi2s->State != HAL_I2S_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } + + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2s); + + tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); + /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended + is selected during the I2S configuration phase, the Size parameter means the number + of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data + frame is selected the Size parameter means the number of 16-bit data length. */ + if ((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B)) + { + hi2s->TxXferSize = (Size << 1U); + hi2s->TxXferCount = (Size << 1U); + hi2s->RxXferSize = (Size << 1U); + hi2s->RxXferCount = (Size << 1U); + } + else + { + hi2s->TxXferSize = Size; + hi2s->TxXferCount = Size; + hi2s->RxXferSize = Size; + hi2s->RxXferCount = Size; + } + + /* Set state and reset error code */ + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + hi2s->State = HAL_I2S_STATE_BUSY_TX_RX; + + tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG; + /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */ + if ((tmp1 == I2S_MODE_MASTER_TX) || (tmp1 == I2S_MODE_SLAVE_TX)) + { + /* Prepare the First Data before enabling the I2S */ + hi2s->Instance->DR = (*pTxData++); + hi2s->TxXferCount--; + + /* Enable I2Sext(receiver) before enabling I2Sx peripheral */ + __HAL_I2SEXT_ENABLE(hi2s); + + /* Enable I2Sx peripheral */ + __HAL_I2S_ENABLE(hi2s); + + /* Check if Master Receiver mode is selected */ + if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) + { + /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read + access to the SPI_SR register. */ + __HAL_I2SEXT_CLEAR_OVRFLAG(hi2s); + } + + while ((hi2s->RxXferCount > 0U) || (hi2s->TxXferCount > 0U)) + { + if (hi2s->TxXferCount > 0U) + { + /* Wait until TXE flag is set */ + if (I2SEx_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout, I2S_USE_I2S) != HAL_OK) + { + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); + errorcode = HAL_ERROR; + goto error; + } + /* Write Data on DR register */ + hi2s->Instance->DR = (*pTxData++); + hi2s->TxXferCount--; + + /* Check if an underrun occurs */ + if ((__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET) && (tmp1 == I2S_MODE_SLAVE_TX)) + { + /* Clear Underrun flag */ + __HAL_I2S_CLEAR_UDRFLAG(hi2s); + + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR); + } + } + if (hi2s->RxXferCount > 0U) + { + /* Wait until RXNE flag is set */ + if (I2SEx_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout, I2S_USE_I2SEXT) != HAL_OK) + { + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); + errorcode = HAL_ERROR; + goto error; + } + /* Read Data from DR register */ + (*pRxData++) = I2SxEXT(hi2s->Instance)->DR; + hi2s->RxXferCount--; + + /* Check if an overrun occurs */ + if (__HAL_I2SEXT_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET) + { + /* Clear Overrun flag */ + __HAL_I2S_CLEAR_OVRFLAG(hi2s); + + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR); + } + } + } + } + /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */ + else + { + /* Prepare the First Data before enabling the I2S */ + I2SxEXT(hi2s->Instance)->DR = (*pTxData++); + hi2s->TxXferCount--; + + /* Enable I2Sext(transmitter) after enabling I2Sx peripheral */ + __HAL_I2SEXT_ENABLE(hi2s); + + /* Enable I2S peripheral before the I2Sext*/ + __HAL_I2S_ENABLE(hi2s); + + /* Check if Master Receiver mode is selected */ + if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX) + { + /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read + access to the SPI_SR register. */ + __HAL_I2S_CLEAR_OVRFLAG(hi2s); + } + + while ((hi2s->RxXferCount > 0U) || (hi2s->TxXferCount > 0U)) + { + if (hi2s->TxXferCount > 0U) + { + /* Wait until TXE flag is set */ + if (I2SEx_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout, I2S_USE_I2SEXT) != HAL_OK) + { + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); + errorcode = HAL_ERROR; + goto error; + } + /* Write Data on DR register */ + I2SxEXT(hi2s->Instance)->DR = (*pTxData++); + hi2s->TxXferCount--; + + /* Check if an underrun occurs */ + if ((__HAL_I2SEXT_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET) && (tmp1 == I2S_MODE_SLAVE_RX)) + { + /* Clear Underrun flag */ + __HAL_I2S_CLEAR_UDRFLAG(hi2s); + + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR); + } + } + if (hi2s->RxXferCount > 0U) + { + /* Wait until RXNE flag is set */ + if (I2SEx_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout, I2S_USE_I2S) != HAL_OK) + { + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); + errorcode = HAL_ERROR; + goto error; + } + /* Read Data from DR register */ + (*pRxData++) = hi2s->Instance->DR; + hi2s->RxXferCount--; + + /* Check if an overrun occurs */ + if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET) + { + /* Clear Overrun flag */ + __HAL_I2S_CLEAR_OVRFLAG(hi2s); + + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR); + } + } + } + } + + if (hi2s->ErrorCode != HAL_I2S_ERROR_NONE) + { + errorcode = HAL_ERROR; + } + +error : + hi2s->State = HAL_I2S_STATE_READY; + __HAL_UNLOCK(hi2s); + return errorcode; +} + +/** + * @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @param pTxData a 16-bit pointer to the Transmit data buffer. + * @param pRxData a 16-bit pointer to the Receive data buffer. + * @param Size number of data sample to be sent: + * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S + * configuration phase, the Size parameter means the number of 16-bit data length + * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected + * the Size parameter means the number of 16-bit data length. + * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization + * between Master and Slave(example: audio streaming). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, + uint16_t Size) +{ + uint32_t tmp1 = 0U; + HAL_StatusTypeDef errorcode = HAL_OK; + + if (hi2s->State != HAL_I2S_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } + + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2s); + + hi2s->pTxBuffPtr = pTxData; + hi2s->pRxBuffPtr = pRxData; + + tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); + /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended + is selected during the I2S configuration phase, the Size parameter means the number + of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data + frame is selected the Size parameter means the number of 16-bit data length. */ + if ((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B)) + { + hi2s->TxXferSize = (Size << 1U); + hi2s->TxXferCount = (Size << 1U); + hi2s->RxXferSize = (Size << 1U); + hi2s->RxXferCount = (Size << 1U); + } + else + { + hi2s->TxXferSize = Size; + hi2s->TxXferCount = Size; + hi2s->RxXferSize = Size; + hi2s->RxXferCount = Size; + } + + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + hi2s->State = HAL_I2S_STATE_BUSY_TX_RX; + + /* Set the function for IT treatment */ + if ((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX)) + { + /* Enable I2Sext RXNE and ERR interrupts */ + __HAL_I2SEXT_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); + + /* Enable I2Sx TXE and ERR interrupts */ + __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); + + /* Transmit First data */ + hi2s->Instance->DR = (*hi2s->pTxBuffPtr++); + hi2s->TxXferCount--; + + if (hi2s->TxXferCount == 0U) + { + /* Disable TXE and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); + } + } + else /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */ + { + /* Enable I2Sext TXE and ERR interrupts */ + __HAL_I2SEXT_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); + + /* Enable I2Sext RXNE and ERR interrupts */ + __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); + + /* Transmit First data */ + I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++); + hi2s->TxXferCount--; + + if (hi2s->TxXferCount == 0U) + { + /* Disable I2Sext TXE and ERR interrupt */ + __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); + } + } + + /* Enable I2Sext peripheral */ + __HAL_I2SEXT_ENABLE(hi2s); + + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + +error : + __HAL_UNLOCK(hi2s); + return errorcode; +} + +/** + * @brief Full-Duplex Transmit/Receive data in non-blocking mode using DMA + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @param pTxData a 16-bit pointer to the Transmit data buffer. + * @param pRxData a 16-bit pointer to the Receive data buffer. + * @param Size number of data sample to be sent: + * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S + * configuration phase, the Size parameter means the number of 16-bit data length + * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected + * the Size parameter means the number of 16-bit data length. + * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization + * between Master and Slave(example: audio streaming). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, + uint16_t Size) +{ + uint32_t *tmp = NULL; + uint32_t tmp1 = 0U; + HAL_StatusTypeDef errorcode = HAL_OK; + + if (hi2s->State != HAL_I2S_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } + + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2s); + + hi2s->pTxBuffPtr = pTxData; + hi2s->pRxBuffPtr = pRxData; + + tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); + /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended + is selected during the I2S configuration phase, the Size parameter means the number + of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data + frame is selected the Size parameter means the number of 16-bit data length. */ + if ((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B)) + { + hi2s->TxXferSize = (Size << 1U); + hi2s->TxXferCount = (Size << 1U); + hi2s->RxXferSize = (Size << 1U); + hi2s->RxXferCount = (Size << 1U); + } + else + { + hi2s->TxXferSize = Size; + hi2s->TxXferCount = Size; + hi2s->RxXferSize = Size; + hi2s->RxXferCount = Size; + } + + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + hi2s->State = HAL_I2S_STATE_BUSY_TX_RX; + + /* Set the I2S Rx DMA Half transfer complete callback */ + hi2s->hdmarx->XferHalfCpltCallback = I2SEx_TxRxDMAHalfCplt; + + /* Set the I2S Rx DMA transfer complete callback */ + hi2s->hdmarx->XferCpltCallback = I2SEx_TxRxDMACplt; + + /* Set the I2S Rx DMA error callback */ + hi2s->hdmarx->XferErrorCallback = I2SEx_TxRxDMAError; + + /* Set the I2S Tx DMA Half transfer complete callback */ + hi2s->hdmatx->XferHalfCpltCallback = I2SEx_TxRxDMAHalfCplt; + + /* Set the I2S Tx DMA transfer complete callback */ + hi2s->hdmatx->XferCpltCallback = I2SEx_TxRxDMACplt; + + /* Set the I2S Tx DMA error callback */ + hi2s->hdmatx->XferErrorCallback = I2SEx_TxRxDMAError; + + tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG; + /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */ + if ((tmp1 == I2S_MODE_MASTER_TX) || (tmp1 == I2S_MODE_SLAVE_TX)) + { + /* Enable the Rx DMA Stream */ + tmp = (uint32_t *)&pRxData; + HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, *(uint32_t *)tmp, hi2s->RxXferSize); + + /* Enable Rx DMA Request */ + SET_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_RXDMAEN); + + /* Enable the Tx DMA Stream */ + tmp = (uint32_t *)&pTxData; + HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t *)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize); + + /* Enable Tx DMA Request */ + SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); + + /* Check if the I2S is already enabled */ + if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) + { + /* Enable I2Sext(receiver) before enabling I2Sx peripheral */ + __HAL_I2SEXT_ENABLE(hi2s); + + /* Enable I2S peripheral after the I2Sext */ + __HAL_I2S_ENABLE(hi2s); + } + } + else + { + /* Check if Master Receiver mode is selected */ + if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX) + { + /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read + access to the SPI_SR register. */ + __HAL_I2S_CLEAR_OVRFLAG(hi2s); + } + /* Enable the Tx DMA Stream */ + tmp = (uint32_t *)&pTxData; + HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t *)tmp, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, hi2s->TxXferSize); + + /* Enable Tx DMA Request */ + SET_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_TXDMAEN); + + /* Enable the Rx DMA Stream */ + tmp = (uint32_t *)&pRxData; + HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t *)tmp, hi2s->RxXferSize); + + /* Enable Rx DMA Request */ + SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); + + /* Check if the I2S is already enabled */ + if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) + { + /* Enable I2Sext(transmitter) before enabling I2Sx peripheral */ + __HAL_I2SEXT_ENABLE(hi2s); + /* Enable I2S peripheral before the I2Sext */ + __HAL_I2S_ENABLE(hi2s); + } + } + +error : + __HAL_UNLOCK(hi2s); + return errorcode; +} + +/** + * @brief This function handles I2S/I2Sext interrupt requests in full-duplex mode. + * @param hi2s I2S handle + * @retval HAL status + */ +void HAL_I2SEx_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s) +{ + __IO uint32_t i2ssr = hi2s->Instance->SR; + __IO uint32_t i2sextsr = I2SxEXT(hi2s->Instance)->SR; + __IO uint32_t i2scr2 = hi2s->Instance->CR2; + __IO uint32_t i2sextcr2 = I2SxEXT(hi2s->Instance)->CR2; + + /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */ + if ((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX)) + { + /* I2S in mode Transmitter -------------------------------------------------*/ + if (((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && ((i2scr2 & I2S_IT_TXE) != RESET)) + { + /* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX, + the I2S TXE interrupt will be generated to manage the full-duplex transmit phase. */ + I2SEx_TxISR_I2S(hi2s); + } + + /* I2Sext in mode Receiver -----------------------------------------------*/ + if (((i2sextsr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && ((i2sextcr2 & I2S_IT_RXNE) != RESET)) + { + /* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX, + the I2Sext RXNE interrupt will be generated to manage the full-duplex receive phase. */ + I2SEx_RxISR_I2SExt(hi2s); + } + + /* I2Sext Overrun error interrupt occurred --------------------------------*/ + if (((i2sextsr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && ((i2sextcr2 & I2S_IT_ERR) != RESET)) + { + /* Disable RXNE and ERR interrupt */ + __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); + + /* Disable TXE and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); + + /* Clear Overrun flag */ + __HAL_I2S_CLEAR_OVRFLAG(hi2s); + + /* Set the I2S State ready */ + hi2s->State = HAL_I2S_STATE_READY; + + /* Set the error code and execute error callback*/ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR); + /* Call user error callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + hi2s->ErrorCallback(hi2s); +#else + HAL_I2S_ErrorCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } + + /* I2S Underrun error interrupt occurred ----------------------------------*/ + if (((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && ((i2scr2 & I2S_IT_ERR) != RESET)) + { + /* Disable TXE and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); + + /* Disable RXNE and ERR interrupt */ + __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); + + /* Clear underrun flag */ + __HAL_I2S_CLEAR_UDRFLAG(hi2s); + + /* Set the I2S State ready */ + hi2s->State = HAL_I2S_STATE_READY; + + /* Set the error code and execute error callback*/ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR); + /* Call user error callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + hi2s->ErrorCallback(hi2s); +#else + HAL_I2S_ErrorCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } + } + /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */ + else + { + /* I2Sext in mode Transmitter ----------------------------------------------*/ + if (((i2sextsr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && ((i2sextcr2 & I2S_IT_TXE) != RESET)) + { + /* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX, + the I2Sext TXE interrupt will be generated to manage the full-duplex transmit phase. */ + I2SEx_TxISR_I2SExt(hi2s); + } + + /* I2S in mode Receiver --------------------------------------------------*/ + if (((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && ((i2scr2 & I2S_IT_RXNE) != RESET)) + { + /* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX, + the I2S RXNE interrupt will be generated to manage the full-duplex receive phase. */ + I2SEx_RxISR_I2S(hi2s); + } + + /* I2S Overrun error interrupt occurred -------------------------------------*/ + if (((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && ((i2scr2 & I2S_IT_ERR) != RESET)) + { + /* Disable RXNE and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); + + /* Disable TXE and ERR interrupt */ + __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); + + /* Set the I2S State ready */ + hi2s->State = HAL_I2S_STATE_READY; + + /* Set the error code and execute error callback*/ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR); + /* Call user error callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + hi2s->ErrorCallback(hi2s); +#else + HAL_I2S_ErrorCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } + + /* I2Sext Underrun error interrupt occurred -------------------------------*/ + if (((i2sextsr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && ((i2sextcr2 & I2S_IT_ERR) != RESET)) + { + /* Disable TXE and ERR interrupt */ + __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); + + /* Disable RXNE and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); + + /* Set the I2S State ready */ + hi2s->State = HAL_I2S_STATE_READY; + + /* Set the error code and execute error callback*/ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR); + /* Call user error callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + hi2s->ErrorCallback(hi2s); +#else + HAL_I2S_ErrorCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } + } +} + +/** + * @brief Tx and Rx Transfer half completed callback + * @param hi2s I2S handle + * @retval None + */ +__weak void HAL_I2SEx_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2s); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2SEx_TxRxHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Tx and Rx Transfer completed callback + * @param hi2s I2S handle + * @retval None + */ +__weak void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2s); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2SEx_TxRxCpltCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup I2SEx_Private_Functions I2S Extended Private Functions + * @{ + */ + +/** + * @brief DMA I2S transmit receive process half complete callback + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void I2SEx_TxRxDMAHalfCplt(DMA_HandleTypeDef *hdma) +{ + I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Call user TxRx Half complete callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + hi2s->TxRxHalfCpltCallback(hi2s); +#else + HAL_I2SEx_TxRxHalfCpltCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA I2S transmit receive process complete callback + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void I2SEx_TxRxDMACplt(DMA_HandleTypeDef *hdma) +{ + I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* if DMA is configured in DMA_NORMAL mode */ + if (hdma->Init.Mode == DMA_NORMAL) + { + if (hi2s->hdmarx == hdma) + { + /* Disable Rx DMA Request */ + if (((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) || \ + ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX)) + { + CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_RXDMAEN); + } + else + { + CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); + } + + hi2s->RxXferCount = 0U; + + if (hi2s->TxXferCount == 0U) + { + hi2s->State = HAL_I2S_STATE_READY; + + /* Call user TxRx complete callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + hi2s->TxRxCpltCallback(hi2s); +#else + HAL_I2SEx_TxRxCpltCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } + } + + if (hi2s->hdmatx == hdma) + { + /* Disable Tx DMA Request */ + if (((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) || \ + ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX)) + { + CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); + } + else + { + CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_TXDMAEN); + } + + hi2s->TxXferCount = 0U; + + if (hi2s->RxXferCount == 0U) + { + hi2s->State = HAL_I2S_STATE_READY; + + /* Call user TxRx complete callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + hi2s->TxRxCpltCallback(hi2s); +#else + HAL_I2SEx_TxRxCpltCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } + } + } +} + +/** + * @brief DMA I2S communication error callback + * @param hdma DMA handle + * @retval None + */ +static void I2SEx_TxRxDMAError(DMA_HandleTypeDef *hdma) +{ + I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Disable Rx and Tx DMA Request */ + CLEAR_BIT(hi2s->Instance->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN)); + CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN)); + + hi2s->TxXferCount = 0U; + hi2s->RxXferCount = 0U; + + hi2s->State = HAL_I2S_STATE_READY; + + /* Set the error code and execute error callback*/ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); + /* Call user error callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + hi2s->ErrorCallback(hi2s); +#else + HAL_I2S_ErrorCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +} + +/** + * @brief I2S Full-Duplex IT handler transmit function + * @param hi2s I2S handle + * @retval None + */ +static void I2SEx_TxISR_I2S(I2S_HandleTypeDef *hi2s) +{ + /* Write Data on DR register */ + hi2s->Instance->DR = (*hi2s->pTxBuffPtr++); + hi2s->TxXferCount--; + + if (hi2s->TxXferCount == 0U) + { + /* Disable TXE and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); + + if (hi2s->RxXferCount == 0U) + { + hi2s->State = HAL_I2S_STATE_READY; + /* Call user TxRx complete callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + hi2s->TxRxCpltCallback(hi2s); +#else + HAL_I2SEx_TxRxCpltCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } + } +} + +/** + * @brief I2SExt Full-Duplex IT handler transmit function + * @param hi2s I2S handle + * @retval None + */ +static void I2SEx_TxISR_I2SExt(I2S_HandleTypeDef *hi2s) +{ + /* Write Data on DR register */ + I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++); + hi2s->TxXferCount--; + + if (hi2s->TxXferCount == 0U) + { + /* Disable I2Sext TXE and ERR interrupt */ + __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); + + if (hi2s->RxXferCount == 0U) + { + hi2s->State = HAL_I2S_STATE_READY; + /* Call user TxRx complete callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + hi2s->TxRxCpltCallback(hi2s); +#else + HAL_I2SEx_TxRxCpltCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } + } +} + +/** + * @brief I2S Full-Duplex IT handler receive function + * @param hi2s I2S handle + * @retval None + */ +static void I2SEx_RxISR_I2S(I2S_HandleTypeDef *hi2s) +{ + /* Read Data from DR register */ + (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR; + hi2s->RxXferCount--; + + if (hi2s->RxXferCount == 0U) + { + /* Disable RXNE and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); + + if (hi2s->TxXferCount == 0U) + { + hi2s->State = HAL_I2S_STATE_READY; + /* Call user TxRx complete callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + hi2s->TxRxCpltCallback(hi2s); +#else + HAL_I2SEx_TxRxCpltCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } + } +} + +/** + * @brief I2SExt Full-Duplex IT handler receive function + * @param hi2s I2S handle + * @retval None + */ +static void I2SEx_RxISR_I2SExt(I2S_HandleTypeDef *hi2s) +{ + /* Read Data from DR register */ + (*hi2s->pRxBuffPtr++) = I2SxEXT(hi2s->Instance)->DR; + hi2s->RxXferCount--; + + if (hi2s->RxXferCount == 0U) + { + /* Disable I2Sext RXNE and ERR interrupt */ + __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); + + if (hi2s->TxXferCount == 0U) + { + hi2s->State = HAL_I2S_STATE_READY; + /* Call user TxRx complete callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + hi2s->TxRxCpltCallback(hi2s); +#else + HAL_I2SEx_TxRxCpltCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } + } +} + +/** + * @brief This function handles I2S Communication Timeout. + * @param hi2s I2S handle + * @param Flag Flag checked + * @param State Value of the flag expected + * @param Timeout Duration of the timeout + * @param i2sUsed I2S instance reference + * @retval HAL status + */ +static HAL_StatusTypeDef I2SEx_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, + uint32_t State, uint32_t Timeout, I2S_UseTypeDef i2sUsed) +{ + uint32_t tickstart = HAL_GetTick(); + + if (i2sUsed == I2S_USE_I2S) + { + /* Wait until flag is reset */ + while (((__HAL_I2S_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State) + { + if (Timeout != HAL_MAX_DELAY) + { + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + { + /* Set the I2S State ready */ + hi2s->State = HAL_I2S_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); + + return HAL_TIMEOUT; + } + } + } + } + else /* i2sUsed == I2S_USE_I2SEXT */ + { + /* Wait until flag is reset */ + while (((__HAL_I2SEXT_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State) + { + if (Timeout != HAL_MAX_DELAY) + { + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + { + /* Set the I2S State ready */ + hi2s->State = HAL_I2S_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); + + return HAL_TIMEOUT; + } + } + } + } + return HAL_OK; +} + +/** + * @} + */ +#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */ + +/** + * @} + */ +#endif /* HAL_I2S_MODULE_ENABLED */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c new file mode 100644 index 0000000..ba2ce59 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c @@ -0,0 +1,559 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_pwr.c + * @author MCD Application Team + * @brief PWR HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Power Controller (PWR) peripheral: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup PWR PWR + * @brief PWR HAL module driver + * @{ + */ + +#ifdef HAL_PWR_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup PWR_Private_Constants + * @{ + */ + +/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask + * @{ + */ +#define PVD_MODE_IT 0x00010000U +#define PVD_MODE_EVT 0x00020000U +#define PVD_RISING_EDGE 0x00000001U +#define PVD_FALLING_EDGE 0x00000002U +/** + * @} + */ + +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + After reset, the backup domain (RTC registers, RTC backup data + registers and backup SRAM) is protected against possible unwanted + write accesses. + To enable access to the RTC Domain and RTC registers, proceed as follows: + (+) Enable the Power Controller (PWR) APB1 interface clock using the + __HAL_RCC_PWR_CLK_ENABLE() macro. + (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the HAL PWR peripheral registers to their default reset values. + * @retval None + */ +void HAL_PWR_DeInit(void) +{ + __HAL_RCC_PWR_FORCE_RESET(); + __HAL_RCC_PWR_RELEASE_RESET(); +} + +/** + * @brief Enables access to the backup domain (RTC registers, RTC + * backup data registers and backup SRAM). + * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the + * Backup Domain Access should be kept enabled. + * @retval None + */ +void HAL_PWR_EnableBkUpAccess(void) +{ + *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE; +} + +/** + * @brief Disables access to the backup domain (RTC registers, RTC + * backup data registers and backup SRAM). + * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the + * Backup Domain Access should be kept enabled. + * @retval None + */ +void HAL_PWR_DisableBkUpAccess(void) +{ + *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE; +} + +/** + * @} + */ + +/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions + * @brief Low Power modes configuration functions + * +@verbatim + + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + + *** PVD configuration *** + ========================= + [..] + (+) The PVD is used to monitor the VDD power supply by comparing it to a + threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). + (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower + than the PVD threshold. This event is internally connected to the EXTI + line16 and can generate an interrupt if enabled. This is done through + __HAL_PWR_PVD_EXTI_ENABLE_IT() macro. + (+) The PVD is stopped in Standby mode. + + *** Wake-up pin configuration *** + ================================ + [..] + (+) Wake-up pin is used to wake up the system from Standby mode. This pin is + forced in input pull-down configuration and is active on rising edges. + (+) There is one Wake-up pin: Wake-up Pin 1 on PA.00. + (++) For STM32F446xx there are two Wake-Up pins: Pin1 on PA.00 and Pin2 on PC.13 + (++) For STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx there are three Wake-Up pins: Pin1 on PA.00, Pin2 on PC.00 and Pin3 on PC.01 + + *** Low Power modes configuration *** + ===================================== + [..] + The devices feature 3 low-power modes: + (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running. + (+) Stop mode: all clocks are stopped, regulator running, regulator + in low power mode + (+) Standby mode: 1.2V domain powered off. + + *** Sleep mode *** + ================== + [..] + (+) Entry: + The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI) + functions with + (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction + (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + + -@@- The Regulator parameter is not used for the STM32F4 family + and is kept as parameter just to maintain compatibility with the + lower power families (STM32L). + (+) Exit: + Any peripheral interrupt acknowledged by the nested vectored interrupt + controller (NVIC) can wake up the device from Sleep mode. + + *** Stop mode *** + ================= + [..] + In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI, + and the HSE RC oscillators are disabled. Internal SRAM and register contents + are preserved. + The voltage regulator can be configured either in normal or low-power mode. + To minimize the consumption In Stop mode, FLASH can be powered off before + entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function. + It can be switched on again by software after exiting the Stop mode using + the HAL_PWREx_DisableFlashPowerDown() function. + + (+) Entry: + The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON) + function with: + (++) Main regulator ON. + (++) Low Power regulator ON. + (+) Exit: + Any EXTI Line (Internal or External) configured in Interrupt/Event mode. + + *** Standby mode *** + ==================== + [..] + (+) + The Standby mode allows to achieve the lowest power consumption. It is based + on the Cortex-M4 deep sleep mode, with the voltage regulator disabled. + The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and + the HSE oscillator are also switched off. SRAM and register contents are lost + except for the RTC registers, RTC backup registers, backup SRAM and Standby + circuitry. + + The voltage regulator is OFF. + + (++) Entry: + (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. + (++) Exit: + (+++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wake-up, + tamper event, time-stamp event, external reset in NRST pin, IWDG reset. + + *** Auto-wake-up (AWU) from low-power mode *** + ============================================= + [..] + + (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC + Wake-up event, a tamper event or a time-stamp event, without depending on + an external interrupt (Auto-wake-up mode). + + (+) RTC auto-wake-up (AWU) from the Stop and Standby modes + + (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to + configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. + + (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it + is necessary to configure the RTC to detect the tamper or time stamp event using the + HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions. + + (++) To wake up from the Stop mode with an RTC Wake-up event, it is necessary to + configure the RTC to generate the RTC Wake-up event using the HAL_RTCEx_SetWakeUpTimer_IT() function. + +@endverbatim + * @{ + */ + +/** + * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). + * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration + * information for the PVD. + * @note Refer to the electrical characteristics of your device datasheet for + * more details about the voltage threshold corresponding to each + * detection level. + * @retval None + */ +void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) +{ + /* Check the parameters */ + assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); + assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); + + /* Set PLS[7:5] bits according to PVDLevel value */ + MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel); + + /* Clear any previous config. Keep it clear if no event or IT mode is selected */ + __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); + __HAL_PWR_PVD_EXTI_DISABLE_IT(); + __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); + + /* Configure interrupt mode */ + if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) + { + __HAL_PWR_PVD_EXTI_ENABLE_IT(); + } + + /* Configure event mode */ + if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) + { + __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); + } + + /* Configure the edge */ + if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) + { + __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); + } + + if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) + { + __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); + } +} + +/** + * @brief Enables the Power Voltage Detector(PVD). + * @retval None + */ +void HAL_PWR_EnablePVD(void) +{ + *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE; +} + +/** + * @brief Disables the Power Voltage Detector(PVD). + * @retval None + */ +void HAL_PWR_DisablePVD(void) +{ + *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE; +} + +/** + * @brief Enables the Wake-up PINx functionality. + * @param WakeUpPinx Specifies the Power Wake-Up pin to enable. + * This parameter can be one of the following values: + * @arg PWR_WAKEUP_PIN1 + * @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412xx/STM32F413xx/STM32F423xx devices + * @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx devices + * @retval None + */ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) +{ + /* Check the parameter */ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); + + /* Enable the wake up pin */ + SET_BIT(PWR->CSR, WakeUpPinx); +} + +/** + * @brief Disables the Wake-up PINx functionality. + * @param WakeUpPinx Specifies the Power Wake-Up pin to disable. + * This parameter can be one of the following values: + * @arg PWR_WAKEUP_PIN1 + * @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412xx/STM32F413xx/STM32F423xx devices + * @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx devices + * @retval None + */ +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) +{ + /* Check the parameter */ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); + + /* Disable the wake up pin */ + CLEAR_BIT(PWR->CSR, WakeUpPinx); +} + +/** + * @brief Enters Sleep mode. + * + * @note In Sleep mode, all I/O pins keep the same state as in Run mode. + * + * @note In Sleep mode, the systick is stopped to avoid exit from this mode with + * systick interrupt when used as time base for Timeout + * + * @param Regulator Specifies the regulator state in SLEEP mode. + * This parameter can be one of the following values: + * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON + * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON + * @note This parameter is not used for the STM32F4 family and is kept as parameter + * just to maintain compatibility with the lower power families. + * @param SLEEPEntry Specifies if SLEEP mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction + * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + * @retval None + */ +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) +{ + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(Regulator)); + assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); + + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* Select SLEEP mode entry -------------------------------------------------*/ + if(SLEEPEntry == PWR_SLEEPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } +} + +/** + * @brief Enters Stop mode. + * @note In Stop mode, all I/O pins keep the same state as in Run mode. + * @note When exiting Stop mode by issuing an interrupt or a wake-up event, + * the HSI RC oscillator is selected as system clock. + * @note When the voltage regulator operates in low power mode, an additional + * startup delay is incurred when waking up from Stop mode. + * By keeping the internal regulator ON during Stop mode, the consumption + * is higher although the startup time is reduced. + * @param Regulator Specifies the regulator state in Stop mode. + * This parameter can be one of the following values: + * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON + * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON + * @param STOPEntry Specifies if Stop mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction + * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction + * @retval None + */ +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) +{ + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(Regulator)); + assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); + + /* Select the regulator state in Stop mode: Set PDDS and LPDS bits according to PWR_Regulator value */ + MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS), Regulator); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* Select Stop mode entry --------------------------------------------------*/ + if(STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Enters Standby mode. + * @note In Standby mode, all I/O pins are high impedance except for: + * - Reset pad (still available) + * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC + * Alarm out, or RTC clock calibration out. + * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp. + * - WKUP pin 1 (PA0) if enabled. + * @retval None + */ +void HAL_PWR_EnterSTANDBYMode(void) +{ + /* Select Standby mode */ + SET_BIT(PWR->CR, PWR_CR_PDDS); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* This option is used to ensure that store operations are completed */ +#if defined ( __CC_ARM) + __force_stores(); +#endif + /* Request Wait For Interrupt */ + __WFI(); +} + +/** + * @brief This function handles the PWR PVD interrupt request. + * @note This API should be called under the PVD_IRQHandler(). + * @retval None + */ +void HAL_PWR_PVD_IRQHandler(void) +{ + /* Check PWR Exti flag */ + if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) + { + /* PWR PVD interrupt user callback */ + HAL_PWR_PVDCallback(); + + /* Clear PWR Exti pending bit */ + __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); + } +} + +/** + * @brief PWR PVD interrupt callback + * @retval None + */ +__weak void HAL_PWR_PVDCallback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PWR_PVDCallback could be implemented in the user file + */ +} + +/** + * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. + * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor + * re-enters SLEEP mode when an interruption handling is over. + * Setting this bit is useful when the processor is expected to run only on + * interruptions handling. + * @retval None + */ +void HAL_PWR_EnableSleepOnExit(void) +{ + /* Set SLEEPONEXIT bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. + * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor + * re-enters SLEEP mode when an interruption handling is over. + * @retval None + */ +void HAL_PWR_DisableSleepOnExit(void) +{ + /* Clear SLEEPONEXIT bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Enables CORTEX M4 SEVONPEND bit. + * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes + * WFE to wake up when an interrupt moves from inactive to pended. + * @retval None + */ +void HAL_PWR_EnableSEVOnPend(void) +{ + /* Set SEVONPEND bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @brief Disables CORTEX M4 SEVONPEND bit. + * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes + * WFE to wake up when an interrupt moves from inactive to pended. + * @retval None + */ +void HAL_PWR_DisableSEVOnPend(void) +{ + /* Clear SEVONPEND bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_PWR_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c new file mode 100644 index 0000000..0d26083 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c @@ -0,0 +1,604 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_pwr_ex.c + * @author MCD Application Team + * @brief Extended PWR HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of PWR extension peripheral: + * + Peripheral Extended features functions + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup PWREx PWREx + * @brief PWR HAL module driver + * @{ + */ + +#ifdef HAL_PWR_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup PWREx_Private_Constants + * @{ + */ +#define PWR_OVERDRIVE_TIMEOUT_VALUE 1000U +#define PWR_UDERDRIVE_TIMEOUT_VALUE 1000U +#define PWR_BKPREG_TIMEOUT_VALUE 1000U +#define PWR_VOSRDY_TIMEOUT_VALUE 1000U +/** + * @} + */ + + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @defgroup PWREx_Exported_Functions PWREx Exported Functions + * @{ + */ + +/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended features functions + * @brief Peripheral Extended features functions + * +@verbatim + + =============================================================================== + ##### Peripheral extended features functions ##### + =============================================================================== + + *** Main and Backup Regulators configuration *** + ================================================ + [..] + (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from + the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is + retained even in Standby or VBAT mode when the low power backup regulator + is enabled. It can be considered as an internal EEPROM when VBAT is + always present. You can use the HAL_PWREx_EnableBkUpReg() function to + enable the low power backup regulator. + + (+) When the backup domain is supplied by VDD (analog switch connected to VDD) + the backup SRAM is powered from VDD which replaces the VBAT power supply to + save battery life. + + (+) The backup SRAM is not mass erased by a tamper event. It is read + protected to prevent confidential data, such as cryptographic private + key, from being accessed. The backup SRAM can be erased only through + the Flash interface when a protection level change from level 1 to + level 0 is requested. + -@- Refer to the description of Read protection (RDP) in the Flash + programming manual. + + (+) The main internal regulator can be configured to have a tradeoff between + performance and power consumption when the device does not operate at + the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG() + macro which configure VOS bit in PWR_CR register + + Refer to the product datasheets for more details. + + *** FLASH Power Down configuration **** + ======================================= + [..] + (+) By setting the FPDS bit in the PWR_CR register by using the + HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power + down mode when the device enters Stop mode. When the Flash memory + is in power down mode, an additional startup delay is incurred when + waking up from Stop mode. + + (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, the scale can be modified only when the PLL + is OFF and the HSI or HSE clock source is selected as system clock. + The new value programmed is active only when the PLL is ON. + When the PLL is OFF, the voltage scale 3 is automatically selected. + Refer to the datasheets for more details. + + *** Over-Drive and Under-Drive configuration **** + ================================================= + [..] + (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, in Run mode: the main regulator has + 2 operating modes available: + (++) Normal mode: The CPU and core logic operate at maximum frequency at a given + voltage scaling (scale 1, scale 2 or scale 3) + (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a + higher frequency than the normal mode for a given voltage scaling (scale 1, + scale 2 or scale 3). This mode is enabled through HAL_PWREx_EnableOverDrive() function and + disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mode please follow + the sequence described in Reference manual. + + (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, in Stop mode: the main regulator or low power regulator + supplies a low power voltage to the 1.2V domain, thus preserving the content of registers + and internal SRAM. 2 operating modes are available: + (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only + available when the main regulator or the low power regulator is used in Scale 3 or + low voltage mode. + (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only + available when the main regulator or the low power regulator is in low voltage mode. + +@endverbatim + * @{ + */ + +/** + * @brief Enables the Backup Regulator. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void) +{ + uint32_t tickstart = 0U; + + *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)ENABLE; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait till Backup regulator ready flag is set */ + while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET) + { + if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @brief Disables the Backup Regulator. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void) +{ + uint32_t tickstart = 0U; + + *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)DISABLE; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait till Backup regulator ready flag is set */ + while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET) + { + if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @brief Enables the Flash Power Down in Stop mode. + * @retval None + */ +void HAL_PWREx_EnableFlashPowerDown(void) +{ + *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)ENABLE; +} + +/** + * @brief Disables the Flash Power Down in Stop mode. + * @retval None + */ +void HAL_PWREx_DisableFlashPowerDown(void) +{ + *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)DISABLE; +} + +/** + * @brief Return Voltage Scaling Range. + * @retval The configured scale for the regulator voltage(VOS bit field). + * The returned value can be one of the following: + * - @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode + * - @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode + * - @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode + */ +uint32_t HAL_PWREx_GetVoltageRange(void) +{ + return (PWR->CR & PWR_CR_VOS); +} + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) +/** + * @brief Configures the main internal regulator output voltage. + * @param VoltageScaling specifies the regulator output voltage to achieve + * a tradeoff between performance and power consumption. + * This parameter can be one of the following values: + * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode, + * the maximum value of fHCLK = 168 MHz. + * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode, + * the maximum value of fHCLK = 144 MHz. + * @note When moving from Range 1 to Range 2, the system frequency must be decreased to + * a value below 144 MHz before calling HAL_PWREx_ConfigVoltageScaling() API. + * When moving from Range 2 to Range 1, the system frequency can be increased to + * a value up to 168 MHz after calling HAL_PWREx_ConfigVoltageScaling() API. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) +{ + uint32_t tickstart = 0U; + + assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); + + /* Enable PWR RCC Clock Peripheral */ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Set Range */ + __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET)) + { + if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +#elif defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \ + defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) || \ + defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || \ + defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/** + * @brief Configures the main internal regulator output voltage. + * @param VoltageScaling specifies the regulator output voltage to achieve + * a tradeoff between performance and power consumption. + * This parameter can be one of the following values: + * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode, + * the maximum value of fHCLK is 168 MHz. It can be extended to + * 180 MHz by activating the over-drive mode. + * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode, + * the maximum value of fHCLK is 144 MHz. It can be extended to, + * 168 MHz by activating the over-drive mode. + * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 3 mode, + * the maximum value of fHCLK is 120 MHz. + * @note To update the system clock frequency(SYSCLK): + * - Set the HSI or HSE as system clock frequency using the HAL_RCC_ClockConfig(). + * - Call the HAL_RCC_OscConfig() to configure the PLL. + * - Call HAL_PWREx_ConfigVoltageScaling() API to adjust the voltage scale. + * - Set the new system clock frequency using the HAL_RCC_ClockConfig(). + * @note The scale can be modified only when the HSI or HSE clock source is selected + * as system clock source, otherwise the API returns HAL_ERROR. + * @note When the PLL is OFF, the voltage scale 3 is automatically selected and the VOS bits + * value in the PWR_CR1 register are not taken in account. + * @note This API forces the PLL state ON to allow the possibility to configure the voltage scale 1 or 2. + * @note The new voltage scale is active only when the PLL is ON. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) +{ + uint32_t tickstart = 0U; + + assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); + + /* Enable PWR RCC Clock Peripheral */ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Check if the PLL is used as system clock or not */ + if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) + { + /* Disable the main PLL */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + /* Wait till PLL is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Set Range */ + __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling); + + /* Enable the main PLL */ + __HAL_RCC_PLL_ENABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET)) + { + if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ + +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\ + defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ + defined(STM32F413xx) || defined(STM32F423xx) +/** + * @brief Enables Main Regulator low voltage mode. + * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/ + * STM32F413xx/STM32F423xx devices. + * @retval None + */ +void HAL_PWREx_EnableMainRegulatorLowVoltage(void) +{ + *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)ENABLE; +} + +/** + * @brief Disables Main Regulator low voltage mode. + * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/ + * STM32F413xx/STM32F423xxdevices. + * @retval None + */ +void HAL_PWREx_DisableMainRegulatorLowVoltage(void) +{ + *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)DISABLE; +} + +/** + * @brief Enables Low Power Regulator low voltage mode. + * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/ + * STM32F413xx/STM32F423xx devices. + * @retval None + */ +void HAL_PWREx_EnableLowRegulatorLowVoltage(void) +{ + *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)ENABLE; +} + +/** + * @brief Disables Low Power Regulator low voltage mode. + * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/ + * STM32F413xx/STM32F423xx devices. + * @retval None + */ +void HAL_PWREx_DisableLowRegulatorLowVoltage(void) +{ + *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)DISABLE; +} + +#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx || + STM32F413xx || STM32F423xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +/** + * @brief Activates the Over-Drive mode. + * @note This function can be used only for STM32F42xx/STM32F43xx/STM32F446xx/STM32F469xx/STM32F479xx devices. + * This mode allows the CPU and the core logic to operate at a higher frequency + * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). + * @note It is recommended to enter or exit Over-drive mode when the application is not running + * critical tasks and when the system clock source is either HSI or HSE. + * During the Over-drive switch activation, no peripheral clocks should be enabled. + * The peripheral clocks must be enabled once the Over-drive mode is activated. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void) +{ + uint32_t tickstart = 0U; + + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Enable the Over-drive to extend the clock frequency to 180 Mhz */ + __HAL_PWR_OVERDRIVE_ENABLE(); + + /* Get tick */ + tickstart = HAL_GetTick(); + + while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY)) + { + if((HAL_GetTick() - tickstart) > PWR_OVERDRIVE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Enable the Over-drive switch */ + __HAL_PWR_OVERDRIVESWITCHING_ENABLE(); + + /* Get tick */ + tickstart = HAL_GetTick(); + + while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY)) + { + if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @brief Deactivates the Over-Drive mode. + * @note This function can be used only for STM32F42xx/STM32F43xx/STM32F446xx/STM32F469xx/STM32F479xx devices. + * This mode allows the CPU and the core logic to operate at a higher frequency + * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). + * @note It is recommended to enter or exit Over-drive mode when the application is not running + * critical tasks and when the system clock source is either HSI or HSE. + * During the Over-drive switch activation, no peripheral clocks should be enabled. + * The peripheral clocks must be enabled once the Over-drive mode is activated. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void) +{ + uint32_t tickstart = 0U; + + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Disable the Over-drive switch */ + __HAL_PWR_OVERDRIVESWITCHING_DISABLE(); + + /* Get tick */ + tickstart = HAL_GetTick(); + + while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY)) + { + if((HAL_GetTick() - tickstart) > PWR_OVERDRIVE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Disable the Over-drive */ + __HAL_PWR_OVERDRIVE_DISABLE(); + + /* Get tick */ + tickstart = HAL_GetTick(); + + while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY)) + { + if((HAL_GetTick() - tickstart) > PWR_OVERDRIVE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Enters in Under-Drive STOP mode. + * + * @note This mode is only available for STM32F42xxx/STM32F43xxx/STM32F446xx/STM32F469xx/STM32F479xx devices. + * + * @note This mode can be selected only when the Under-Drive is already active + * + * @note This mode is enabled only with STOP low power mode. + * In this mode, the 1.2V domain is preserved in reduced leakage mode. This + * mode is only available when the main regulator or the low power regulator + * is in low voltage mode + * + * @note If the Under-drive mode was enabled, it is automatically disabled after + * exiting Stop mode. + * When the voltage regulator operates in Under-drive mode, an additional + * startup delay is induced when waking up from Stop mode. + * + * @note In Stop mode, all I/O pins keep the same state as in Run mode. + * + * @note When exiting Stop mode by issuing an interrupt or a wake-up event, + * the HSI RC oscillator is selected as system clock. + * + * @note When the voltage regulator operates in low power mode, an additional + * startup delay is incurred when waking up from Stop mode. + * By keeping the internal regulator ON during Stop mode, the consumption + * is higher although the startup time is reduced. + * + * @param Regulator specifies the regulator state in STOP mode. + * This parameter can be one of the following values: + * @arg PWR_MAINREGULATOR_UNDERDRIVE_ON: Main Regulator in under-drive mode + * and Flash memory in power-down when the device is in Stop under-drive mode + * @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON: Low Power Regulator in under-drive mode + * and Flash memory in power-down when the device is in Stop under-drive mode + * @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction + * @arg PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction + * @retval None + */ +HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry) +{ + uint32_t tmpreg1 = 0U; + + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR_UNDERDRIVE(Regulator)); + assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); + + /* Enable Power ctrl clock */ + __HAL_RCC_PWR_CLK_ENABLE(); + /* Enable the Under-drive Mode ---------------------------------------------*/ + /* Clear Under-drive flag */ + __HAL_PWR_CLEAR_ODRUDR_FLAG(); + + /* Enable the Under-drive */ + __HAL_PWR_UNDERDRIVE_ENABLE(); + + /* Select the regulator state in STOP mode ---------------------------------*/ + tmpreg1 = PWR->CR; + /* Clear PDDS, LPDS, MRLUDS and LPLUDS bits */ + tmpreg1 &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_LPUDS | PWR_CR_MRUDS); + + /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */ + tmpreg1 |= Regulator; + + /* Store the new value */ + PWR->CR = tmpreg1; + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* Select STOP mode entry --------------------------------------------------*/ + if(STOPEntry == PWR_SLEEPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __WFE(); + } + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); + + return HAL_OK; +} + +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_PWR_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c new file mode 100644 index 0000000..7640b65 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c @@ -0,0 +1,1114 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_rcc.c + * @author MCD Application Team + * @brief RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Reset and Clock Control (RCC) peripheral: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + @verbatim + ============================================================================== + ##### RCC specific features ##### + ============================================================================== + [..] + After reset the device is running from Internal High Speed oscillator + (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache + and I-Cache are disabled, and all peripherals are off except internal + SRAM, Flash and JTAG. + (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses; + all peripherals mapped on these busses are running at HSI speed. + (+) The clock for all peripherals is switched off, except the SRAM and FLASH. + (+) All GPIOs are in input floating state, except the JTAG pins which + are assigned to be used for debug purpose. + + [..] + Once the device started from reset, the user application has to: + (+) Configure the clock source to be used to drive the System clock + (if the application needs higher frequency/performance) + (+) Configure the System clock frequency and Flash settings + (+) Configure the AHB and APB busses prescalers + (+) Enable the clock for the peripheral(s) to be used + (+) Configure the clock source(s) for peripherals which clocks are not + derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG) + + ##### RCC Limitations ##### + ============================================================================== + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write + from/to registers. + (+) This delay depends on the peripheral mapping. + (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle + after the clock enable bit is set on the hardware register + (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle + after the clock enable bit is set on the hardware register + + [..] + Implemented Workaround: + (+) For AHB & APB peripherals, a dummy read to the peripheral register has been + inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup RCC RCC + * @brief RCC HAL module driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup RCC_Private_Constants + * @{ + */ + +/* Private macro -------------------------------------------------------------*/ +#define __MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define MCO1_GPIO_PORT GPIOA +#define MCO1_PIN GPIO_PIN_8 + +#define __MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE() +#define MCO2_GPIO_PORT GPIOC +#define MCO2_PIN GPIO_PIN_9 +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup RCC_Private_Variables RCC Private Variables + * @{ + */ +/** + * @} + */ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to configure the internal/external oscillators + (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1 + and APB2). + + [..] Internal/external clock and PLL configuration + (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through + the PLL as System clock source. + + (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC + clock source. + + (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or + through the PLL as System clock source. Can be used also as RTC clock source. + + (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. + + (#) PLL (clocked by HSI or HSE), featuring two different output clocks: + (++) The first output is used to generate the high speed system clock (up to 168 MHz) + (++) The second output is used to generate the clock for the USB OTG FS (48 MHz), + the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz). + + (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE() + and if a HSE clock failure occurs(HSE used directly or through PLL as System + clock source), the System clocks automatically switched to HSI and an interrupt + is generated if enabled. The interrupt is linked to the Cortex-M4 NMI + (Non-Maskable Interrupt) exception vector. + + (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL + clock (through a configurable prescaler) on PA8 pin. + + (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S + clock (through a configurable prescaler) on PC9 pin. + + [..] System, AHB and APB busses clocks configuration + (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI, + HSE and PLL. + The AHB clock (HCLK) is derived from System clock through configurable + prescaler and used to clock the CPU, memory and peripherals mapped + on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived + from AHB clock through configurable prescalers and used to clock + the peripherals mapped on these busses. You can use + "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. + + (#) For the STM32F405xx/07xx and STM32F415xx/17xx devices, the maximum + frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz. + Depending on the device voltage range, the maximum frequency should + be adapted accordingly (refer to the product datasheets for more details). + + (#) For the STM32F42xxx, STM32F43xxx, STM32F446xx, STM32F469xx and STM32F479xx devices, + the maximum frequency of the SYSCLK and HCLK is 180 MHz, PCLK2 90 MHz and PCLK1 45 MHz. + Depending on the device voltage range, the maximum frequency should + be adapted accordingly (refer to the product datasheets for more details). + + (#) For the STM32F401xx, the maximum frequency of the SYSCLK and HCLK is 84 MHz, + PCLK2 84 MHz and PCLK1 42 MHz. + Depending on the device voltage range, the maximum frequency should + be adapted accordingly (refer to the product datasheets for more details). + + (#) For the STM32F41xxx, the maximum frequency of the SYSCLK and HCLK is 100 MHz, + PCLK2 100 MHz and PCLK1 50 MHz. + Depending on the device voltage range, the maximum frequency should + be adapted accordingly (refer to the product datasheets for more details). + +@endverbatim + * @{ + */ + +/** + * @brief Resets the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - HSI ON and used as system clock source + * - HSE and PLL OFF + * - AHB, APB1 and APB2 prescaler set to 1. + * - CSS, MCO1 and MCO2 OFF + * - All interrupts disabled + * @note This function doesn't modify the configuration of the + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_RCC_DeInit(void) +{ + return HAL_OK; +} + +/** + * @brief Initializes the RCC Oscillators according to the specified parameters in the + * RCC_OscInitTypeDef. + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC Oscillators. + * @note The PLL is not disabled when used as system clock. + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not + * supported by this API. User should request a transition to LSE Off + * first and then LSE On or LSE Bypass. + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this API. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + uint32_t tickstart, pll_config; + + /* Check Null pointer */ + if(RCC_OscInitStruct == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + /*------------------------------- HSE Configuration ------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\ + ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) + { + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + { + return HAL_ERROR; + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + + /* Check the HSE State */ + if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF) + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSE is bypassed or disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\ + ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) + { + /* When HSI is used as system clock it will not disabled */ + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + { + return HAL_ERROR; + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + } + else + { + /* Check the HSI State */ + if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF) + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF) + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + { + FlagStatus pwrclkchanged = RESET; + + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + { + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + + if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + /* Check the LSE State */ + if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Restore clock configuration if changed */ + if(pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } + } + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + { + /* Check if the PLL is used as system clock or not */ + if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) + { + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + { + /* Check the parameters */ + assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM)); + assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); + assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); + assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure the main PLL clock source, multiplication and division factors. */ + WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \ + RCC_OscInitStruct->PLL.PLLM | \ + (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \ + (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \ + (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos))); + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + else + { + /* Check if there is a request to disable the PLL used as System clock source */ + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) + { + return HAL_ERROR; + } + else + { + /* Do not return HAL_ERROR if request repeats the current configuration */ + pll_config = RCC->PLLCFGR; + if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != RCC_OscInitStruct->PLL.PLLN) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ)) + { + return HAL_ERROR; + } + } + } + } + return HAL_OK; +} + +/** + * @brief Initializes the CPU, AHB and APB busses clocks according to the specified + * parameters in the RCC_ClkInitStruct. + * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC peripheral. + * @param FLatency FLASH Latency, this parameter depend on device selected + * + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * and updated by HAL_RCC_GetHCLKFreq() function called within this function + * + * @note The HSI is used (enabled by hardware) as system clock source after + * startup from Reset, wake-up from STOP and STANDBY mode, or in case + * of failure of the HSE used directly or indirectly as system clock + * (if the Clock Security System CSS is enabled). + * + * @note A switch from one clock source to another occurs only if the target + * clock source is ready (clock stable after startup delay or PLL locked). + * If a clock source which is not yet ready is selected, the switch will + * occur when the clock source will be ready. + * + * @note Depending on the device voltage range, the software has to set correctly + * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency + * (for more details refer to section above "Initialization/de-initialization functions") + * @retval None + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + uint32_t tickstart; + + /* Check Null pointer */ + if(RCC_ClkInitStruct == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); + assert_param(IS_FLASH_LATENCY(FLatency)); + + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. */ + + /* Increasing the number of wait states because of higher CPU frequency */ + if(FLatency > __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != FLatency) + { + return HAL_ERROR; + } + } + + /*-------------------------- HCLK Configuration --------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + { + /* Set the highest APBx dividers in order to ensure that we do not go through + a non-spec phase whatever we decrease or increase HCLK. */ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); + } + + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); + } + + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + { + /* Check the HSE ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + { + return HAL_ERROR; + } + } + /* PLL is selected as System Clock Source */ + else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || + (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK)) + { + /* Check the PLL ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + { + return HAL_ERROR; + } + } + /* HSI is selected as System Clock Source */ + else + { + /* Check the HSI ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + { + return HAL_ERROR; + } + } + + __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Decreasing the number of wait states because of lower CPU frequency */ + if(FLatency < __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != FLatency) + { + return HAL_ERROR; + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos]; + + /* Configure the source of time base considering new system clocks settings */ + HAL_InitTick (uwTickPrio); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions + * @brief RCC clocks control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the RCC Clocks + frequencies. + +@endverbatim + * @{ + */ + +/** + * @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9). + * @note PA8/PC9 should be configured in alternate function mode. + * @param RCC_MCOx specifies the output direction for the clock source. + * This parameter can be one of the following values: + * @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8). + * @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9). + * @param RCC_MCOSource specifies the clock source to output. + * This parameter can be one of the following values: + * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source + * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source + * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx + * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices + * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source + * @param RCC_MCODiv specifies the MCOx prescaler. + * This parameter can be one of the following values: + * @arg RCC_MCODIV_1: no division applied to MCOx clock + * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock + * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock + * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock + * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock + * @note For STM32F410Rx devices to output I2SCLK clock on MCO2 you should have + * at last one of the SPI clocks enabled (SPI1, SPI2 or SPI5). + * @retval None + */ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) +{ + GPIO_InitTypeDef GPIO_InitStruct; + /* Check the parameters */ + assert_param(IS_RCC_MCO(RCC_MCOx)); + assert_param(IS_RCC_MCODIV(RCC_MCODiv)); + /* RCC_MCO1 */ + if(RCC_MCOx == RCC_MCO1) + { + assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); + + /* MCO1 Clock Enable */ + __MCO1_CLK_ENABLE(); + + /* Configure the MCO1 pin in alternate function mode */ + GPIO_InitStruct.Pin = MCO1_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Alternate = GPIO_AF0_MCO; + HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct); + + /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv)); + + /* This RCC MCO1 enable feature is available only on STM32F410xx devices */ +#if defined(RCC_CFGR_MCO1EN) + __HAL_RCC_MCO1_ENABLE(); +#endif /* RCC_CFGR_MCO1EN */ + } +#if defined(RCC_CFGR_MCO2) + else + { + assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource)); + + /* MCO2 Clock Enable */ + __MCO2_CLK_ENABLE(); + + /* Configure the MCO2 pin in alternate function mode */ + GPIO_InitStruct.Pin = MCO2_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Alternate = GPIO_AF0_MCO; + HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct); + + /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3U))); + + /* This RCC MCO2 enable feature is available only on STM32F410Rx devices */ +#if defined(RCC_CFGR_MCO2EN) + __HAL_RCC_MCO2_ENABLE(); +#endif /* RCC_CFGR_MCO2EN */ + } +#endif /* RCC_CFGR_MCO2 */ +} + +/** + * @brief Enables the Clock Security System. + * @note If a failure is detected on the HSE oscillator clock, this oscillator + * is automatically disabled and an interrupt is generated to inform the + * software about the failure (Clock Security System Interrupt, CSSI), + * allowing the MCU to perform rescue operations. The CSSI is linked to + * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector. + * @retval None + */ +void HAL_RCC_EnableCSS(void) +{ + *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE; +} + +/** + * @brief Disables the Clock Security System. + * @retval None + */ +void HAL_RCC_DisableCSS(void) +{ + *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE; +} + +/** + * @brief Returns the SYSCLK frequency + * + * @note The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) + * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) + * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * @note (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * @note The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @note This function can be used by the user application to compute the + * baudrate for the communication peripherals or configure other parameters. + * + * @note Each time SYSCLK changes, this function must be called to update the + * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * + * @retval SYSCLK frequency + */ +__weak uint32_t HAL_RCC_GetSysClockFreq(void) +{ + uint32_t pllm = 0U, pllvco = 0U, pllp = 0U; + uint32_t sysclockfreq = 0U; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR & RCC_CFGR_SWS) + { + case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ + { + sysclockfreq = HSI_VALUE; + break; + } + case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ + { + sysclockfreq = HSE_VALUE; + break; + } + case RCC_CFGR_SWS_PLL: /* PLL used as system clock source */ + { + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + SYSCLK = PLL_VCO / PLLP */ + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) + { + /* HSE used as PLL clock source */ + pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); + } + pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U); + + sysclockfreq = pllvco/pllp; + break; + } + default: + { + sysclockfreq = HSI_VALUE; + break; + } + } + return sysclockfreq; +} + +/** + * @brief Returns the HCLK frequency + * @note Each time HCLK changes, this function must be called to update the + * right HCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * and updated within this function + * @retval HCLK frequency + */ +uint32_t HAL_RCC_GetHCLKFreq(void) +{ + return SystemCoreClock; +} + +/** + * @brief Returns the PCLK1 frequency + * @note Each time PCLK1 changes, this function must be called to update the + * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK1 frequency + */ +uint32_t HAL_RCC_GetPCLK1Freq(void) +{ + /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]); +} + +/** + * @brief Returns the PCLK2 frequency + * @note Each time PCLK2 changes, this function must be called to update the + * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK2 frequency + */ +uint32_t HAL_RCC_GetPCLK2Freq(void) +{ + /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]); +} + +/** + * @brief Configures the RCC_OscInitStruct according to the internal + * RCC configuration registers. + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that + * will be configured. + * @retval None + */ +__weak void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + /* Set all possible values for the Oscillator type parameter ---------------*/ + RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI; + + /* Get the HSE configuration -----------------------------------------------*/ + if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP) + { + RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; + } + else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON) + { + RCC_OscInitStruct->HSEState = RCC_HSE_ON; + } + else + { + RCC_OscInitStruct->HSEState = RCC_HSE_OFF; + } + + /* Get the HSI configuration -----------------------------------------------*/ + if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION) + { + RCC_OscInitStruct->HSIState = RCC_HSI_ON; + } + else + { + RCC_OscInitStruct->HSIState = RCC_HSI_OFF; + } + + RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); + + /* Get the LSE configuration -----------------------------------------------*/ + if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) + { + RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; + } + else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON) + { + RCC_OscInitStruct->LSEState = RCC_LSE_ON; + } + else + { + RCC_OscInitStruct->LSEState = RCC_LSE_OFF; + } + + /* Get the LSI configuration -----------------------------------------------*/ + if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION) + { + RCC_OscInitStruct->LSIState = RCC_LSI_ON; + } + else + { + RCC_OscInitStruct->LSIState = RCC_LSI_OFF; + } + + /* Get the PLL configuration -----------------------------------------------*/ + if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON) + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; + } + else + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; + } + RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); + RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM); + RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1U) >> RCC_PLLCFGR_PLLP_Pos); + RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos); +} + +/** + * @brief Configures the RCC_ClkInitStruct according to the internal + * RCC configuration registers. + * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that + * will be configured. + * @param pFLatency Pointer on the Flash Latency. + * @retval None + */ +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) +{ + /* Set all possible values for the Clock type parameter --------------------*/ + RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + + /* Get the SYSCLK configuration --------------------------------------------*/ + RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); + + /* Get the HCLK configuration ----------------------------------------------*/ + RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); + + /* Get the APB1 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); + + /* Get the APB2 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U); + + /* Get the Flash Wait State (Latency) configuration ------------------------*/ + *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); +} + +/** + * @brief This function handles the RCC CSS interrupt request. + * @note This API should be called under the NMI_Handler(). + * @retval None + */ +void HAL_RCC_NMI_IRQHandler(void) +{ + /* Check RCC CSSF flag */ + if(__HAL_RCC_GET_IT(RCC_IT_CSS)) + { + /* RCC Clock Security System interrupt user callback */ + HAL_RCC_CSSCallback(); + + /* Clear RCC CSS pending bit */ + __HAL_RCC_CLEAR_IT(RCC_IT_CSS); + } +} + +/** + * @brief RCC Clock Security System interrupt callback + * @retval None + */ +__weak void HAL_RCC_CSSCallback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RCC_CSSCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_RCC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c new file mode 100644 index 0000000..0d3aacc --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c @@ -0,0 +1,3754 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_rcc_ex.c + * @author MCD Application Team + * @brief Extension RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities RCC extension peripheral: + * + Extended Peripheral Control functions + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup RCCEx RCCEx + * @brief RCCEx HAL module driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup RCCEx_Private_Constants + * @{ + */ +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions + * @{ + */ + +/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Extended Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the RCC Clocks + frequencies. + [..] + (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to + select the RTC clock source; in this case the Backup domain will be reset in + order to modify the RTC Clock source, as consequence RTC registers (including + the backup registers) and RCC_BDCR register are set to their reset values. + +@endverbatim + * @{ + */ + +#if defined(STM32F446xx) +/** + * @brief Initializes the RCC extended peripherals clocks according to the specified + * parameters in the RCC_PeriphCLKInitTypeDef. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * contains the configuration information for the Extended Peripherals + * clocks(I2S, SAI, LTDC RTC and TIM). + * + * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source; in this case the Backup domain will be reset in + * order to modify the RTC Clock source, as consequence RTC registers (including + * the backup registers) and RCC_BDCR register are set to their reset values. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tickstart = 0U; + uint32_t tmpreg1 = 0U; + uint32_t plli2sp = 0U; + uint32_t plli2sq = 0U; + uint32_t plli2sr = 0U; + uint32_t pllsaip = 0U; + uint32_t pllsaiq = 0U; + uint32_t plli2sused = 0U; + uint32_t pllsaiused = 0U; + + /* Check the peripheral clock selection parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*------------------------ I2S APB1 configuration --------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1)) + { + /* Check the parameters */ + assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection)); + + /* Configure I2S Clock source */ + __HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection); + /* Enable the PLLI2S when it's used as clock source for I2S */ + if(PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S) + { + plli2sused = 1U; + } + } + /*--------------------------------------------------------------------------*/ + + /*---------------------------- I2S APB2 configuration ----------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2)) + { + /* Check the parameters */ + assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection)); + + /* Configure I2S Clock source */ + __HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection); + /* Enable the PLLI2S when it's used as clock source for I2S */ + if(PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S) + { + plli2sused = 1U; + } + } + /*--------------------------------------------------------------------------*/ + + /*--------------------------- SAI1 configuration ---------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1)) + { + /* Check the parameters */ + assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); + + /* Configure SAI1 Clock source */ + __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); + /* Enable the PLLI2S when it's used as clock source for SAI */ + if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S) + { + plli2sused = 1U; + } + /* Enable the PLLSAI when it's used as clock source for SAI */ + if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI) + { + pllsaiused = 1U; + } + } + /*--------------------------------------------------------------------------*/ + + /*-------------------------- SAI2 configuration ----------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2)) + { + /* Check the parameters */ + assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection)); + + /* Configure SAI2 Clock source */ + __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection); + + /* Enable the PLLI2S when it's used as clock source for SAI */ + if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S) + { + plli2sused = 1U; + } + /* Enable the PLLSAI when it's used as clock source for SAI */ + if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI) + { + pllsaiused = 1U; + } + } + /*--------------------------------------------------------------------------*/ + + /*----------------------------- RTC configuration --------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) + { + /* Check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + /* Enable Power Clock*/ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Enable write access to Backup domain */ + PWR->CR |= PWR_CR_DBP; + + /* Get tick */ + tickstart = HAL_GetTick(); + + while((PWR->CR & PWR_CR_DBP) == RESET) + { + if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ + tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL); + if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) + { + /* Store the content of BDCR register before the reset of Backup Domain */ + tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + /* Restore the Content of BDCR register */ + RCC->BDCR = tmpreg1; + + /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ + if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + } + /*--------------------------------------------------------------------------*/ + + /*---------------------------- TIM configuration ---------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) + { + /* Configure Timer Prescaler */ + __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); + } + /*--------------------------------------------------------------------------*/ + + /*---------------------------- FMPI2C1 Configuration -----------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1) + { + /* Check the parameters */ + assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection)); + + /* Configure the FMPI2C1 clock source */ + __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection); + } + /*--------------------------------------------------------------------------*/ + + /*------------------------------ CEC Configuration -------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) + { + /* Check the parameters */ + assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); + + /* Configure the CEC clock source */ + __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); + } + /*--------------------------------------------------------------------------*/ + + /*----------------------------- CLK48 Configuration ------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) + { + /* Check the parameters */ + assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection)); + + /* Configure the CLK48 clock source */ + __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); + + /* Enable the PLLSAI when it's used as clock source for CLK48 */ + if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP) + { + pllsaiused = 1U; + } + } + /*--------------------------------------------------------------------------*/ + + /*----------------------------- SDIO Configuration -------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO) + { + /* Check the parameters */ + assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection)); + + /* Configure the SDIO clock source */ + __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection); + } + /*--------------------------------------------------------------------------*/ + + /*------------------------------ SPDIFRX Configuration ---------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) + { + /* Check the parameters */ + assert_param(IS_RCC_SPDIFRXCLKSOURCE(PeriphClkInit->SpdifClockSelection)); + + /* Configure the SPDIFRX clock source */ + __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifClockSelection); + /* Enable the PLLI2S when it's used as clock source for SPDIFRX */ + if(PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP) + { + plli2sused = 1U; + } + } + /*--------------------------------------------------------------------------*/ + + /*---------------------------- PLLI2S Configuration ------------------------*/ + /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S on APB1, + I2S on APB2 or SPDIFRX */ + if((plli2sused == 1U) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S)) + { + /* Disable the PLLI2S */ + __HAL_RCC_PLLI2S_DISABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLI2S is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /* check for common PLLI2S Parameters */ + assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM)); + assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); + + /*------ In Case of PLLI2S is selected as source clock for I2S -----------*/ + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) || + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S))) + { + /* check for Parameters */ + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + + /* Read PLLI2SP/PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */ + plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); + plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ + /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , plli2sp, plli2sq, PeriphClkInit->PLLI2S.PLLI2SR); + } + + /*------- In Case of PLLI2S is selected as source clock for SAI ----------*/ + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) + { + /* Check for PLLI2S Parameters */ + assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + /* Check for PLLI2S/DIVQ parameters */ + assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); + + /* Read PLLI2SP/PLLI2SR value from PLLI2SCFGR register (this value is not needed for SAI configuration) */ + plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); + plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , plli2sp, PeriphClkInit->PLLI2S.PLLI2SQ, plli2sr); + + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ + __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); + } + + /*------ In Case of PLLI2S is selected as source clock for SPDIFRX -------*/ + if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) && (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP)) + { + /* check for Parameters */ + assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP)); + /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */ + plli2sq = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); + plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ + /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, plli2sq, plli2sr); + } + + /*----------------- In Case of PLLI2S is just selected -----------------*/ + if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) + { + /* Check for Parameters */ + assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP)); + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); + } + + /* Enable the PLLI2S */ + __HAL_RCC_PLLI2S_ENABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLI2S is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + } + /*--------------------------------------------------------------------------*/ + + /*----------------------------- PLLSAI Configuration -----------------------*/ + /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, CLK48 or SDIO */ + if(pllsaiused == 1U) + { + /* Disable PLLSAI Clock */ + __HAL_RCC_PLLSAI_DISABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLSAI is disabled */ + while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) + { + if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /* Check the PLLSAI division factors */ + assert_param(IS_RCC_PLLSAIM_VALUE(PeriphClkInit->PLLSAI.PLLSAIM)); + assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); + + /*------ In Case of PLLSAI is selected as source clock for SAI -----------*/ + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) || + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) + { + /* check for PLLSAIQ Parameter */ + assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); + /* check for PLLSAI/DIVQ Parameter */ + assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); + + /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ + pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U); + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN , pllsaip, PeriphClkInit->PLLSAI.PLLSAIQ, 0U); + + /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ + __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); + } + + /*------ In Case of PLLSAI is selected as source clock for CLK48 ---------*/ + /* In Case of PLLI2S is selected as source clock for CLK48 */ + if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)) + { + /* check for Parameters */ + assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP)); + /* Read PLLSAIQ value from PLLI2SCFGR register (this value is not need for SAI configuration) */ + pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + /* Configure the PLLSAI division factors */ + /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * (PLLI2SN/PLLSAIM) */ + /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, pllsaiq, 0U); + } + + /* Enable PLLSAI Clock */ + __HAL_RCC_PLLSAI_ENABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLSAI is ready */ + while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) + { + if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + +/** + * @brief Get the RCC_PeriphCLKInitTypeDef according to the internal + * RCC configuration registers. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * will be configured. + * @retval None + */ +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tempreg; + + /* Set all possible values for the extended clock type parameter------------*/ + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 | RCC_PERIPHCLK_I2S_APB2 |\ + RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\ + RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\ + RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_FMPI2C1 |\ + RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_SDIO |\ + RCC_PERIPHCLK_SPDIFRX; + + /* Get the PLLI2S Clock configuration --------------------------------------*/ + PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM) >> RCC_PLLI2SCFGR_PLLI2SM_Pos); + PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); + PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); + PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); + PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + /* Get the PLLSAI Clock configuration --------------------------------------*/ + PeriphClkInit->PLLSAI.PLLSAIM = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM) >> RCC_PLLSAICFGR_PLLSAIM_Pos); + PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos); + PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U); + PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + /* Get the PLLSAI/PLLI2S division factors ----------------------------------*/ + PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos); + PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos); + + /* Get the SAI1 clock configuration ----------------------------------------*/ + PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE(); + + /* Get the SAI2 clock configuration ----------------------------------------*/ + PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE(); + + /* Get the I2S APB1 clock configuration ------------------------------------*/ + PeriphClkInit->I2sApb1ClockSelection = __HAL_RCC_GET_I2S_APB1_SOURCE(); + + /* Get the I2S APB2 clock configuration ------------------------------------*/ + PeriphClkInit->I2sApb2ClockSelection = __HAL_RCC_GET_I2S_APB2_SOURCE(); + + /* Get the RTC Clock configuration -----------------------------------------*/ + tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); + PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); + + /* Get the CEC clock configuration -----------------------------------------*/ + PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE(); + + /* Get the FMPI2C1 clock configuration -------------------------------------*/ + PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE(); + + /* Get the CLK48 clock configuration ----------------------------------------*/ + PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE(); + + /* Get the SDIO clock configuration ----------------------------------------*/ + PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE(); + + /* Get the SPDIFRX clock configuration -------------------------------------*/ + PeriphClkInit->SpdifClockSelection = __HAL_RCC_GET_SPDIFRX_SOURCE(); + + /* Get the TIM Prescaler configuration -------------------------------------*/ + if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET) + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; + } + else + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; + } +} + +/** + * @brief Return the peripheral clock frequency for a given peripheral(SAI..) + * @note Return 0 if peripheral clock identifier not managed by this API + * @param PeriphClk Peripheral clock identifier + * This parameter can be one of the following values: + * @arg RCC_PERIPHCLK_SAI1: SAI1 peripheral clock + * @arg RCC_PERIPHCLK_SAI2: SAI2 peripheral clock + * @arg RCC_PERIPHCLK_I2S_APB1: I2S APB1 peripheral clock + * @arg RCC_PERIPHCLK_I2S_APB2: I2S APB2 peripheral clock + * @retval Frequency in KHz + */ +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) +{ + uint32_t tmpreg1 = 0U; + /* This variable used to store the SAI clock frequency (value in Hz) */ + uint32_t frequency = 0U; + /* This variable used to store the VCO Input (value in Hz) */ + uint32_t vcoinput = 0U; + /* This variable used to store the SAI clock source */ + uint32_t saiclocksource = 0U; + uint32_t srcclk = 0U; + /* This variable used to store the VCO Output (value in Hz) */ + uint32_t vcooutput = 0U; + switch (PeriphClk) + { + case RCC_PERIPHCLK_SAI1: + case RCC_PERIPHCLK_SAI2: + { + saiclocksource = RCC->DCKCFGR; + saiclocksource &= (RCC_DCKCFGR_SAI1SRC | RCC_DCKCFGR_SAI2SRC); + switch (saiclocksource) + { + case 0U: /* PLLSAI is the clock source for SAI*/ + { + /* Configure the PLLSAI division factor */ + /* PLLSAI_VCO Input = PLL_SOURCE/PLLSAIM */ + if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) + { + /* In Case the PLL Source is HSI (Internal Clock) */ + vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM)); + } + else + { + /* In Case the PLL Source is HSE (External Clock) */ + vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM))); + } + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ + tmpreg1 = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24U; + frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6U))/(tmpreg1); + + /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ + tmpreg1 = (((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> 8U) + 1U); + frequency = frequency/(tmpreg1); + break; + } + case RCC_DCKCFGR_SAI1SRC_0: /* PLLI2S is the clock source for SAI*/ + case RCC_DCKCFGR_SAI2SRC_0: /* PLLI2S is the clock source for SAI*/ + { + /* Configure the PLLI2S division factor */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ + if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) + { + /* In Case the PLL Source is HSI (Internal Clock) */ + vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); + } + else + { + /* In Case the PLL Source is HSE (External Clock) */ + vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM))); + } + + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ + tmpreg1 = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24U; + frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U))/(tmpreg1); + + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ + tmpreg1 = ((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) + 1U); + frequency = frequency/(tmpreg1); + break; + } + case RCC_DCKCFGR_SAI1SRC_1: /* PLLR is the clock source for SAI*/ + case RCC_DCKCFGR_SAI2SRC_1: /* PLLR is the clock source for SAI*/ + { + /* Configure the PLLI2S division factor */ + /* PLL_VCO Input = PLL_SOURCE/PLLM */ + if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) + { + /* In Case the PLL Source is HSI (Internal Clock) */ + vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + else + { + /* In Case the PLL Source is HSE (External Clock) */ + vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM))); + } + + /* PLL_VCO Output = PLL_VCO Input * PLLN */ + /* SAI_CLK_x = PLL_VCO Output/PLLR */ + tmpreg1 = (RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U; + frequency = (vcoinput * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U))/(tmpreg1); + break; + } + case RCC_DCKCFGR_SAI1SRC: /* External clock is the clock source for SAI*/ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + case RCC_DCKCFGR_SAI2SRC: /* PLLSRC(HSE or HSI) is the clock source for SAI*/ + { + if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) + { + /* In Case the PLL Source is HSI (Internal Clock) */ + frequency = (uint32_t)(HSI_VALUE); + } + else + { + /* In Case the PLL Source is HSE (External Clock) */ + frequency = (uint32_t)(HSE_VALUE); + } + break; + } + default : + { + break; + } + } + break; + } + case RCC_PERIPHCLK_I2S_APB1: + { + /* Get the current I2S source */ + srcclk = __HAL_RCC_GET_I2S_APB1_SOURCE(); + switch (srcclk) + { + /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ + case RCC_I2SAPB1CLKSOURCE_EXT: + { + /* Set the I2S clock to the external clock value */ + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */ + case RCC_I2SAPB1CLKSOURCE_PLLI2S: + { + /* Configure the PLLI2S division factor */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ + if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); + } + else + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); + } + + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U))); + /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */ + frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U))); + break; + } + /* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */ + case RCC_I2SAPB1CLKSOURCE_PLLR: + { + /* Configure the PLL division factor R */ + /* PLL_VCO Input = PLL_SOURCE/PLLM */ + if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + else + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + + /* PLL_VCO Output = PLL_VCO Input * PLLN */ + vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U))); + /* I2S_CLK = PLL_VCO Output/PLLR */ + frequency = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U))); + break; + } + /* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */ + case RCC_I2SAPB1CLKSOURCE_PLLSRC: + { + if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + frequency = HSE_VALUE; + } + else + { + frequency = HSI_VALUE; + } + break; + } + /* Clock not enabled for I2S*/ + default: + { + frequency = 0U; + break; + } + } + break; + } + case RCC_PERIPHCLK_I2S_APB2: + { + /* Get the current I2S source */ + srcclk = __HAL_RCC_GET_I2S_APB2_SOURCE(); + switch (srcclk) + { + /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ + case RCC_I2SAPB2CLKSOURCE_EXT: + { + /* Set the I2S clock to the external clock value */ + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */ + case RCC_I2SAPB2CLKSOURCE_PLLI2S: + { + /* Configure the PLLI2S division factor */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ + if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); + } + else + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); + } + + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U))); + /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */ + frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U))); + break; + } + /* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */ + case RCC_I2SAPB2CLKSOURCE_PLLR: + { + /* Configure the PLL division factor R */ + /* PLL_VCO Input = PLL_SOURCE/PLLM */ + if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + else + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + + /* PLL_VCO Output = PLL_VCO Input * PLLN */ + vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U))); + /* I2S_CLK = PLL_VCO Output/PLLR */ + frequency = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U))); + break; + } + /* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */ + case RCC_I2SAPB2CLKSOURCE_PLLSRC: + { + if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + frequency = HSE_VALUE; + } + else + { + frequency = HSI_VALUE; + } + break; + } + /* Clock not enabled for I2S*/ + default: + { + frequency = 0U; + break; + } + } + break; + } + } + return frequency; +} +#endif /* STM32F446xx */ + +#if defined(STM32F469xx) || defined(STM32F479xx) +/** + * @brief Initializes the RCC extended peripherals clocks according to the specified + * parameters in the RCC_PeriphCLKInitTypeDef. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * contains the configuration information for the Extended Peripherals + * clocks(I2S, SAI, LTDC, RTC and TIM). + * + * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source; in this case the Backup domain will be reset in + * order to modify the RTC Clock source, as consequence RTC registers (including + * the backup registers) and RCC_BDCR register are set to their reset values. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tickstart = 0U; + uint32_t tmpreg1 = 0U; + uint32_t pllsaip = 0U; + uint32_t pllsaiq = 0U; + uint32_t pllsair = 0U; + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*--------------------------- CLK48 Configuration --------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) + { + /* Check the parameters */ + assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection)); + + /* Configure the CLK48 clock source */ + __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); + } + /*--------------------------------------------------------------------------*/ + + /*------------------------------ SDIO Configuration ------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO) + { + /* Check the parameters */ + assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection)); + + /* Configure the SDIO clock source */ + __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection); + } + /*--------------------------------------------------------------------------*/ + + /*----------------------- SAI/I2S Configuration (PLLI2S) -------------------*/ + /*------------------- Common configuration SAI/I2S -------------------------*/ + /* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division + factor is common parameters for both peripherals */ + if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || + (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S) || + (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)) + { + /* check for Parameters */ + assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); + + /* Disable the PLLI2S */ + __HAL_RCC_PLLI2S_DISABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLI2S is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /*---------------------- I2S configuration -------------------------------*/ + /* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added + only for I2S configuration */ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S)) + { + /* check for Parameters */ + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */ + /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR); + } + + /*---------------------------- SAI configuration -------------------------*/ + /* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must + be added only for SAI configuration */ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S)) + { + /* Check the PLLI2S division factors */ + assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); + + /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */ + tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ + __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg1); + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ + __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); + } + + /*----------------- In Case of PLLI2S is just selected -----------------*/ + if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) + { + /* Check for Parameters */ + assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + + /* Configure the PLLI2S multiplication and division factors */ + __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); + } + + /* Enable the PLLI2S */ + __HAL_RCC_PLLI2S_ENABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLI2S is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + } + /*--------------------------------------------------------------------------*/ + + /*----------------------- SAI/LTDC Configuration (PLLSAI) ------------------*/ + /*----------------------- Common configuration SAI/LTDC --------------------*/ + /* In Case of SAI, LTDC or CLK48 Clock Configuration through PLLSAI, PLLSAIN division + factor is common parameters for these peripherals */ + if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) || + (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && + (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP))) + { + /* Check the PLLSAI division factors */ + assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); + + /* Disable PLLSAI Clock */ + __HAL_RCC_PLLSAI_DISABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLSAI is disabled */ + while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) + { + if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /*---------------------------- SAI configuration -------------------------*/ + /* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must + be added only for SAI configuration */ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI)) + { + assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); + assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); + + /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ + pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U); + /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */ + pllsair = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, PeriphClkInit->PLLSAI.PLLSAIQ, pllsair); + /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ + __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); + } + + /*---------------------------- LTDC configuration ------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC)) + { + assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR)); + assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR)); + + /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ + pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U); + /* Read PLLSAIQ value from PLLSAICFGR register (this value is not need for SAI configuration) */ + pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, pllsaiq, PeriphClkInit->PLLSAI.PLLSAIR); + /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ + __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR); + } + + /*---------------------------- CLK48 configuration ------------------------*/ + /* Configure the PLLSAI when it is used as clock source for CLK48 */ + if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == (RCC_PERIPHCLK_CLK48)) && + (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)) + { + assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP)); + + /* Read PLLSAIQ value from PLLSAICFGR register (this value is not need for SAI configuration) */ + pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */ + pllsair = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + /* CLK48_CLK(first level) = PLLSAI_VCO Output/PLLSAIP */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, PeriphClkInit->PLLSAI.PLLSAIP, pllsaiq, pllsair); + } + + /* Enable PLLSAI Clock */ + __HAL_RCC_PLLSAI_ENABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLSAI is ready */ + while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) + { + if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + } + + /*--------------------------------------------------------------------------*/ + + /*---------------------------- RTC configuration ---------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) + { + /* Check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + /* Enable Power Clock*/ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Enable write access to Backup domain */ + PWR->CR |= PWR_CR_DBP; + + /* Get tick */ + tickstart = HAL_GetTick(); + + while((PWR->CR & PWR_CR_DBP) == RESET) + { + if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ + tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL); + if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) + { + /* Store the content of BDCR register before the reset of Backup Domain */ + tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + /* Restore the Content of BDCR register */ + RCC->BDCR = tmpreg1; + + /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ + if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + } + /*--------------------------------------------------------------------------*/ + + /*---------------------------- TIM configuration ---------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) + { + __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); + } + return HAL_OK; +} + +/** + * @brief Configures the RCC_PeriphCLKInitTypeDef according to the internal + * RCC configuration registers. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * will be configured. + * @retval None + */ +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tempreg; + + /* Set all possible values for the extended clock type parameter------------*/ + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_SAI_PLLSAI |\ + RCC_PERIPHCLK_SAI_PLLI2S | RCC_PERIPHCLK_LTDC |\ + RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\ + RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_SDIO; + + /* Get the PLLI2S Clock configuration --------------------------------------*/ + PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); + PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); + /* Get the PLLSAI Clock configuration --------------------------------------*/ + PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos); + PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); + PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + /* Get the PLLSAI/PLLI2S division factors ----------------------------------*/ + PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos); + PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos); + PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR); + /* Get the RTC Clock configuration -----------------------------------------*/ + tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); + PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); + + /* Get the CLK48 clock configuration -------------------------------------*/ + PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE(); + + /* Get the SDIO clock configuration ----------------------------------------*/ + PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE(); + + if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET) + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; + } + else + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; + } +} + +/** + * @brief Return the peripheral clock frequency for a given peripheral(SAI..) + * @note Return 0 if peripheral clock identifier not managed by this API + * @param PeriphClk Peripheral clock identifier + * This parameter can be one of the following values: + * @arg RCC_PERIPHCLK_I2S: I2S peripheral clock + * @retval Frequency in KHz + */ +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) +{ + /* This variable used to store the I2S clock frequency (value in Hz) */ + uint32_t frequency = 0U; + /* This variable used to store the VCO Input (value in Hz) */ + uint32_t vcoinput = 0U; + uint32_t srcclk = 0U; + /* This variable used to store the VCO Output (value in Hz) */ + uint32_t vcooutput = 0U; + switch (PeriphClk) + { + case RCC_PERIPHCLK_I2S: + { + /* Get the current I2S source */ + srcclk = __HAL_RCC_GET_I2S_SOURCE(); + switch (srcclk) + { + /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ + case RCC_I2SCLKSOURCE_EXT: + { + /* Set the I2S clock to the external clock value */ + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */ + case RCC_I2SCLKSOURCE_PLLI2S: + { + /* Configure the PLLI2S division factor */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ + if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + else + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U))); + /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */ + frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U))); + break; + } + /* Clock not enabled for I2S*/ + default: + { + frequency = 0U; + break; + } + } + break; + } + } + return frequency; +} +#endif /* STM32F469xx || STM32F479xx */ + +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/** + * @brief Initializes the RCC extended peripherals clocks according to the specified + * parameters in the RCC_PeriphCLKInitTypeDef. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * contains the configuration information for the Extended Peripherals + * clocks(I2S, LTDC RTC and TIM). + * + * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source; in this case the Backup domain will be reset in + * order to modify the RTC Clock source, as consequence RTC registers (including + * the backup registers) and RCC_BDCR register are set to their reset values. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tickstart = 0U; + uint32_t tmpreg1 = 0U; +#if defined(STM32F413xx) || defined(STM32F423xx) + uint32_t plli2sq = 0U; +#endif /* STM32F413xx || STM32F423xx */ + uint32_t plli2sused = 0U; + + /* Check the peripheral clock selection parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*----------------------------------- I2S APB1 configuration ---------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1)) + { + /* Check the parameters */ + assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection)); + + /* Configure I2S Clock source */ + __HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection); + /* Enable the PLLI2S when it's used as clock source for I2S */ + if(PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S) + { + plli2sused = 1U; + } + } + /*--------------------------------------------------------------------------*/ + + /*----------------------------------- I2S APB2 configuration ---------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2)) + { + /* Check the parameters */ + assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection)); + + /* Configure I2S Clock source */ + __HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection); + /* Enable the PLLI2S when it's used as clock source for I2S */ + if(PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S) + { + plli2sused = 1U; + } + } + /*--------------------------------------------------------------------------*/ + +#if defined(STM32F413xx) || defined(STM32F423xx) + /*----------------------- SAI1 Block A configuration -----------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIA) == (RCC_PERIPHCLK_SAIA)) + { + /* Check the parameters */ + assert_param(IS_RCC_SAIACLKSOURCE(PeriphClkInit->SaiAClockSelection)); + + /* Configure SAI1 Clock source */ + __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(PeriphClkInit->SaiAClockSelection); + /* Enable the PLLI2S when it's used as clock source for SAI */ + if(PeriphClkInit->SaiAClockSelection == RCC_SAIACLKSOURCE_PLLI2SR) + { + plli2sused = 1U; + } + /* Enable the PLLSAI when it's used as clock source for SAI */ + if(PeriphClkInit->SaiAClockSelection == RCC_SAIACLKSOURCE_PLLR) + { + /* Check for PLL/DIVR parameters */ + assert_param(IS_RCC_PLL_DIVR_VALUE(PeriphClkInit->PLLDivR)); + + /* SAI_CLK_x = SAI_CLK(first level)/PLLDIVR */ + __HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLDivR); + } + } + /*--------------------------------------------------------------------------*/ + + /*---------------------- SAI1 Block B configuration ------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIB) == (RCC_PERIPHCLK_SAIB)) + { + /* Check the parameters */ + assert_param(IS_RCC_SAIBCLKSOURCE(PeriphClkInit->SaiBClockSelection)); + + /* Configure SAI1 Clock source */ + __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(PeriphClkInit->SaiBClockSelection); + /* Enable the PLLI2S when it's used as clock source for SAI */ + if(PeriphClkInit->SaiBClockSelection == RCC_SAIBCLKSOURCE_PLLI2SR) + { + plli2sused = 1U; + } + /* Enable the PLLSAI when it's used as clock source for SAI */ + if(PeriphClkInit->SaiBClockSelection == RCC_SAIBCLKSOURCE_PLLR) + { + /* Check for PLL/DIVR parameters */ + assert_param(IS_RCC_PLL_DIVR_VALUE(PeriphClkInit->PLLDivR)); + + /* SAI_CLK_x = SAI_CLK(first level)/PLLDIVR */ + __HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLDivR); + } + } + /*--------------------------------------------------------------------------*/ +#endif /* STM32F413xx || STM32F423xx */ + + /*------------------------------------ RTC configuration -------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) + { + /* Check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + /* Enable Power Clock*/ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Enable write access to Backup domain */ + PWR->CR |= PWR_CR_DBP; + + /* Get tick */ + tickstart = HAL_GetTick(); + + while((PWR->CR & PWR_CR_DBP) == RESET) + { + if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ + tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL); + if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) + { + /* Store the content of BDCR register before the reset of Backup Domain */ + tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + /* Restore the Content of BDCR register */ + RCC->BDCR = tmpreg1; + + /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ + if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + } + /*--------------------------------------------------------------------------*/ + + /*------------------------------------ TIM configuration -------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) + { + /* Configure Timer Prescaler */ + __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); + } + /*--------------------------------------------------------------------------*/ + + /*------------------------------------- FMPI2C1 Configuration --------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1) + { + /* Check the parameters */ + assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection)); + + /* Configure the FMPI2C1 clock source */ + __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection); + } + /*--------------------------------------------------------------------------*/ + + /*------------------------------------- CLK48 Configuration ----------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) + { + /* Check the parameters */ + assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection)); + + /* Configure the SDIO clock source */ + __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); + + /* Enable the PLLI2S when it's used as clock source for CLK48 */ + if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ) + { + plli2sused = 1U; + } + } + /*--------------------------------------------------------------------------*/ + + /*------------------------------------- SDIO Configuration -----------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO) + { + /* Check the parameters */ + assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection)); + + /* Configure the SDIO clock source */ + __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection); + } + /*--------------------------------------------------------------------------*/ + + /*-------------------------------------- PLLI2S Configuration --------------*/ + /* PLLI2S is configured when a peripheral will use it as source clock : I2S on APB1 or + I2S on APB2*/ + if((plli2sused == 1U) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S)) + { + /* Disable the PLLI2S */ + __HAL_RCC_PLLI2S_DISABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLI2S is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /* check for common PLLI2S Parameters */ + assert_param(IS_RCC_PLLI2SCLKSOURCE(PeriphClkInit->PLLI2SSelection)); + assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM)); + assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); + /*-------------------- Set the PLL I2S clock -----------------------------*/ + __HAL_RCC_PLL_I2S_CONFIG(PeriphClkInit->PLLI2SSelection); + + /*------- In Case of PLLI2S is selected as source clock for I2S ----------*/ + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) || + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)) || + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ)) || + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO) && (PeriphClkInit->SdioClockSelection == RCC_SDIOCLKSOURCE_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ))) + { + /* check for Parameters */ + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM)*/ + /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); + } + +#if defined(STM32F413xx) || defined(STM32F423xx) + /*------- In Case of PLLI2S is selected as source clock for SAI ----------*/ + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIA) == RCC_PERIPHCLK_SAIA) && (PeriphClkInit->SaiAClockSelection == RCC_SAIACLKSOURCE_PLLI2SR)) || + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIB) == RCC_PERIPHCLK_SAIB) && (PeriphClkInit->SaiBClockSelection == RCC_SAIBCLKSOURCE_PLLI2SR))) + { + /* Check for PLLI2S Parameters */ + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + /* Check for PLLI2S/DIVR parameters */ + assert_param(IS_RCC_PLLI2S_DIVR_VALUE(PeriphClkInit->PLLI2SDivR)); + + /* Read PLLI2SQ value from PLLI2SCFGR register (this value is not needed for SAI configuration) */ + plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, plli2sq, PeriphClkInit->PLLI2S.PLLI2SR); + + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVR */ + __HAL_RCC_PLLI2S_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLI2SDivR); + } +#endif /* STM32F413xx || STM32F423xx */ + + /*----------------- In Case of PLLI2S is just selected ------------------*/ + if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) + { + /* Check for Parameters */ + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM)*/ + /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); + } + + /* Enable the PLLI2S */ + __HAL_RCC_PLLI2S_ENABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLI2S is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + } + /*--------------------------------------------------------------------------*/ + + /*-------------------- DFSDM1 clock source configuration -------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) + { + /* Check the parameters */ + assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection)); + + /* Configure the DFSDM1 interface clock source */ + __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); + } + /*--------------------------------------------------------------------------*/ + + /*-------------------- DFSDM1 Audio clock source configuration -------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) + { + /* Check the parameters */ + assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection)); + + /* Configure the DFSDM1 Audio interface clock source */ + __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection); + } + /*--------------------------------------------------------------------------*/ + +#if defined(STM32F413xx) || defined(STM32F423xx) + /*-------------------- DFSDM2 clock source configuration -------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2) == RCC_PERIPHCLK_DFSDM2) + { + /* Check the parameters */ + assert_param(IS_RCC_DFSDM2CLKSOURCE(PeriphClkInit->Dfsdm2ClockSelection)); + + /* Configure the DFSDM1 interface clock source */ + __HAL_RCC_DFSDM2_CONFIG(PeriphClkInit->Dfsdm2ClockSelection); + } + /*--------------------------------------------------------------------------*/ + + /*-------------------- DFSDM2 Audio clock source configuration -------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2_AUDIO) == RCC_PERIPHCLK_DFSDM2_AUDIO) + { + /* Check the parameters */ + assert_param(IS_RCC_DFSDM2AUDIOCLKSOURCE(PeriphClkInit->Dfsdm2AudioClockSelection)); + + /* Configure the DFSDM1 Audio interface clock source */ + __HAL_RCC_DFSDM2AUDIO_CONFIG(PeriphClkInit->Dfsdm2AudioClockSelection); + } + /*--------------------------------------------------------------------------*/ + + /*---------------------------- LPTIM1 Configuration ------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) + { + /* Check the parameters */ + assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection)); + + /* Configure the LPTIM1 clock source */ + __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); + } + /*--------------------------------------------------------------------------*/ +#endif /* STM32F413xx || STM32F423xx */ + + return HAL_OK; +} + +/** + * @brief Get the RCC_PeriphCLKInitTypeDef according to the internal + * RCC configuration registers. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * will be configured. + * @retval None + */ +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tempreg; + + /* Set all possible values for the extended clock type parameter------------*/ +#if defined(STM32F413xx) || defined(STM32F423xx) + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 | RCC_PERIPHCLK_I2S_APB2 |\ + RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\ + RCC_PERIPHCLK_FMPI2C1 | RCC_PERIPHCLK_CLK48 |\ + RCC_PERIPHCLK_SDIO | RCC_PERIPHCLK_DFSDM1 |\ + RCC_PERIPHCLK_DFSDM1_AUDIO | RCC_PERIPHCLK_DFSDM2 |\ + RCC_PERIPHCLK_DFSDM2_AUDIO | RCC_PERIPHCLK_LPTIM1 |\ + RCC_PERIPHCLK_SAIA | RCC_PERIPHCLK_SAIB; +#else /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 | RCC_PERIPHCLK_I2S_APB2 |\ + RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\ + RCC_PERIPHCLK_FMPI2C1 | RCC_PERIPHCLK_CLK48 |\ + RCC_PERIPHCLK_SDIO | RCC_PERIPHCLK_DFSDM1 |\ + RCC_PERIPHCLK_DFSDM1_AUDIO; +#endif /* STM32F413xx || STM32F423xx */ + + + + /* Get the PLLI2S Clock configuration --------------------------------------*/ + PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM) >> RCC_PLLI2SCFGR_PLLI2SM_Pos); + PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); + PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); + PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); +#if defined(STM32F413xx) || defined(STM32F423xx) + /* Get the PLL/PLLI2S division factors -------------------------------------*/ + PeriphClkInit->PLLI2SDivR = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVR) >> RCC_DCKCFGR_PLLI2SDIVR_Pos); + PeriphClkInit->PLLDivR = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLDIVR) >> RCC_DCKCFGR_PLLDIVR_Pos); +#endif /* STM32F413xx || STM32F423xx */ + + /* Get the I2S APB1 clock configuration ------------------------------------*/ + PeriphClkInit->I2sApb1ClockSelection = __HAL_RCC_GET_I2S_APB1_SOURCE(); + + /* Get the I2S APB2 clock configuration ------------------------------------*/ + PeriphClkInit->I2sApb2ClockSelection = __HAL_RCC_GET_I2S_APB2_SOURCE(); + + /* Get the RTC Clock configuration -----------------------------------------*/ + tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); + PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); + + /* Get the FMPI2C1 clock configuration -------------------------------------*/ + PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE(); + + /* Get the CLK48 clock configuration ---------------------------------------*/ + PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE(); + + /* Get the SDIO clock configuration ----------------------------------------*/ + PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE(); + + /* Get the DFSDM1 clock configuration --------------------------------------*/ + PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE(); + + /* Get the DFSDM1 Audio clock configuration --------------------------------*/ + PeriphClkInit->Dfsdm1AudioClockSelection = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE(); + +#if defined(STM32F413xx) || defined(STM32F423xx) + /* Get the DFSDM2 clock configuration --------------------------------------*/ + PeriphClkInit->Dfsdm2ClockSelection = __HAL_RCC_GET_DFSDM2_SOURCE(); + + /* Get the DFSDM2 Audio clock configuration --------------------------------*/ + PeriphClkInit->Dfsdm2AudioClockSelection = __HAL_RCC_GET_DFSDM2AUDIO_SOURCE(); + + /* Get the LPTIM1 clock configuration --------------------------------------*/ + PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); + + /* Get the SAI1 Block Aclock configuration ---------------------------------*/ + PeriphClkInit->SaiAClockSelection = __HAL_RCC_GET_SAI_BLOCKA_SOURCE(); + + /* Get the SAI1 Block B clock configuration --------------------------------*/ + PeriphClkInit->SaiBClockSelection = __HAL_RCC_GET_SAI_BLOCKB_SOURCE(); +#endif /* STM32F413xx || STM32F423xx */ + + /* Get the TIM Prescaler configuration -------------------------------------*/ + if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET) + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; + } + else + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; + } +} + +/** + * @brief Return the peripheral clock frequency for a given peripheral(I2S..) + * @note Return 0 if peripheral clock identifier not managed by this API + * @param PeriphClk Peripheral clock identifier + * This parameter can be one of the following values: + * @arg RCC_PERIPHCLK_I2S_APB1: I2S APB1 peripheral clock + * @arg RCC_PERIPHCLK_I2S_APB2: I2S APB2 peripheral clock + * @retval Frequency in KHz + */ +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) +{ + /* This variable used to store the I2S clock frequency (value in Hz) */ + uint32_t frequency = 0U; + /* This variable used to store the VCO Input (value in Hz) */ + uint32_t vcoinput = 0U; + uint32_t srcclk = 0U; + /* This variable used to store the VCO Output (value in Hz) */ + uint32_t vcooutput = 0U; + switch (PeriphClk) + { + case RCC_PERIPHCLK_I2S_APB1: + { + /* Get the current I2S source */ + srcclk = __HAL_RCC_GET_I2S_APB1_SOURCE(); + switch (srcclk) + { + /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ + case RCC_I2SAPB1CLKSOURCE_EXT: + { + /* Set the I2S clock to the external clock value */ + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */ + case RCC_I2SAPB1CLKSOURCE_PLLI2S: + { + if((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SSRC) == RCC_PLLI2SCFGR_PLLI2SSRC) + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(EXTERNAL_CLOCK_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); + } + else + { + /* Configure the PLLI2S division factor */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ + if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); + } + else + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); + } + } + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U))); + /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */ + frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U))); + break; + } + /* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */ + case RCC_I2SAPB1CLKSOURCE_PLLR: + { + /* Configure the PLL division factor R */ + /* PLL_VCO Input = PLL_SOURCE/PLLM */ + if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + else + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + + /* PLL_VCO Output = PLL_VCO Input * PLLN */ + vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U))); + /* I2S_CLK = PLL_VCO Output/PLLR */ + frequency = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U))); + break; + } + /* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */ + case RCC_I2SAPB1CLKSOURCE_PLLSRC: + { + if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + frequency = HSE_VALUE; + } + else + { + frequency = HSI_VALUE; + } + break; + } + /* Clock not enabled for I2S*/ + default: + { + frequency = 0U; + break; + } + } + break; + } + case RCC_PERIPHCLK_I2S_APB2: + { + /* Get the current I2S source */ + srcclk = __HAL_RCC_GET_I2S_APB2_SOURCE(); + switch (srcclk) + { + /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ + case RCC_I2SAPB2CLKSOURCE_EXT: + { + /* Set the I2S clock to the external clock value */ + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */ + case RCC_I2SAPB2CLKSOURCE_PLLI2S: + { + if((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SSRC) == RCC_PLLI2SCFGR_PLLI2SSRC) + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(EXTERNAL_CLOCK_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); + } + else + { + /* Configure the PLLI2S division factor */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ + if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); + } + else + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); + } + } + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U))); + /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */ + frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U))); + break; + } + /* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */ + case RCC_I2SAPB2CLKSOURCE_PLLR: + { + /* Configure the PLL division factor R */ + /* PLL_VCO Input = PLL_SOURCE/PLLM */ + if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + else + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + + /* PLL_VCO Output = PLL_VCO Input * PLLN */ + vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U))); + /* I2S_CLK = PLL_VCO Output/PLLR */ + frequency = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U))); + break; + } + /* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */ + case RCC_I2SAPB2CLKSOURCE_PLLSRC: + { + if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + frequency = HSE_VALUE; + } + else + { + frequency = HSI_VALUE; + } + break; + } + /* Clock not enabled for I2S*/ + default: + { + frequency = 0U; + break; + } + } + break; + } + } + return frequency; +} +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +/** + * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the + * RCC_PeriphCLKInitTypeDef. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks). + * + * @note A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case + * the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup + * domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tickstart = 0U; + uint32_t tmpreg1 = 0U; + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*---------------------------- RTC configuration ---------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) + { + /* Check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + /* Enable Power Clock*/ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Enable write access to Backup domain */ + PWR->CR |= PWR_CR_DBP; + + /* Get tick */ + tickstart = HAL_GetTick(); + + while((PWR->CR & PWR_CR_DBP) == RESET) + { + if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ + tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL); + if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) + { + /* Store the content of BDCR register before the reset of Backup Domain */ + tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + /* Restore the Content of BDCR register */ + RCC->BDCR = tmpreg1; + + /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ + if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + } + /*--------------------------------------------------------------------------*/ + + /*---------------------------- TIM configuration ---------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) + { + __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); + } + /*--------------------------------------------------------------------------*/ + + /*---------------------------- FMPI2C1 Configuration -----------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1) + { + /* Check the parameters */ + assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection)); + + /* Configure the FMPI2C1 clock source */ + __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection); + } + /*--------------------------------------------------------------------------*/ + + /*---------------------------- LPTIM1 Configuration ------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) + { + /* Check the parameters */ + assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection)); + + /* Configure the LPTIM1 clock source */ + __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); + } + + /*---------------------------- I2S Configuration ---------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) + { + /* Check the parameters */ + assert_param(IS_RCC_I2SAPBCLKSOURCE(PeriphClkInit->I2SClockSelection)); + + /* Configure the I2S clock source */ + __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2SClockSelection); + } + + return HAL_OK; +} + +/** + * @brief Configures the RCC_OscInitStruct according to the internal + * RCC configuration registers. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * will be configured. + * @retval None + */ +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tempreg; + + /* Set all possible values for the extended clock type parameter------------*/ + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_FMPI2C1 | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC; + + tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); + PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); + + if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET) + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; + } + else + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; + } + /* Get the FMPI2C1 clock configuration -------------------------------------*/ + PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE(); + + /* Get the I2S clock configuration -----------------------------------------*/ + PeriphClkInit->I2SClockSelection = __HAL_RCC_GET_I2S_SOURCE(); + + +} +/** + * @brief Return the peripheral clock frequency for a given peripheral(SAI..) + * @note Return 0 if peripheral clock identifier not managed by this API + * @param PeriphClk Peripheral clock identifier + * This parameter can be one of the following values: + * @arg RCC_PERIPHCLK_I2S: I2S peripheral clock + * @retval Frequency in KHz + */ +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) +{ + /* This variable used to store the I2S clock frequency (value in Hz) */ + uint32_t frequency = 0U; + /* This variable used to store the VCO Input (value in Hz) */ + uint32_t vcoinput = 0U; + uint32_t srcclk = 0U; + /* This variable used to store the VCO Output (value in Hz) */ + uint32_t vcooutput = 0U; + switch (PeriphClk) + { + case RCC_PERIPHCLK_I2S: + { + /* Get the current I2S source */ + srcclk = __HAL_RCC_GET_I2S_SOURCE(); + switch (srcclk) + { + /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ + case RCC_I2SAPBCLKSOURCE_EXT: + { + /* Set the I2S clock to the external clock value */ + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + /* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */ + case RCC_I2SAPBCLKSOURCE_PLLR: + { + /* Configure the PLL division factor R */ + /* PLL_VCO Input = PLL_SOURCE/PLLM */ + if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + else + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + + /* PLL_VCO Output = PLL_VCO Input * PLLN */ + vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U))); + /* I2S_CLK = PLL_VCO Output/PLLR */ + frequency = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U))); + break; + } + /* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */ + case RCC_I2SAPBCLKSOURCE_PLLSRC: + { + if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + frequency = HSE_VALUE; + } + else + { + frequency = HSI_VALUE; + } + break; + } + /* Clock not enabled for I2S*/ + default: + { + frequency = 0U; + break; + } + } + break; + } + } + return frequency; +} +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +/** + * @brief Initializes the RCC extended peripherals clocks according to the specified + * parameters in the RCC_PeriphCLKInitTypeDef. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * contains the configuration information for the Extended Peripherals + * clocks(I2S, SAI, LTDC RTC and TIM). + * + * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source; in this case the Backup domain will be reset in + * order to modify the RTC Clock source, as consequence RTC registers (including + * the backup registers) and RCC_BDCR register are set to their reset values. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tickstart = 0U; + uint32_t tmpreg1 = 0U; + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*----------------------- SAI/I2S Configuration (PLLI2S) -------------------*/ + /*----------------------- Common configuration SAI/I2S ---------------------*/ + /* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division + factor is common parameters for both peripherals */ + if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || + (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S) || + (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)) + { + /* check for Parameters */ + assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); + + /* Disable the PLLI2S */ + __HAL_RCC_PLLI2S_DISABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLI2S is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /*---------------------------- I2S configuration -------------------------*/ + /* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added + only for I2S configuration */ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S)) + { + /* check for Parameters */ + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLM) */ + /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR); + } + + /*---------------------------- SAI configuration -------------------------*/ + /* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must + be added only for SAI configuration */ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S)) + { + /* Check the PLLI2S division factors */ + assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); + + /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */ + tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ + __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg1); + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ + __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); + } + + /*----------------- In Case of PLLI2S is just selected -----------------*/ + if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) + { + /* Check for Parameters */ + assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + + /* Configure the PLLI2S multiplication and division factors */ + __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); + } + + /* Enable the PLLI2S */ + __HAL_RCC_PLLI2S_ENABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLI2S is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + } + /*--------------------------------------------------------------------------*/ + + /*----------------------- SAI/LTDC Configuration (PLLSAI) ------------------*/ + /*----------------------- Common configuration SAI/LTDC --------------------*/ + /* In Case of SAI or LTDC Clock Configuration through PLLSAI, PLLSAIN division + factor is common parameters for both peripherals */ + if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) || + (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)) + { + /* Check the PLLSAI division factors */ + assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); + + /* Disable PLLSAI Clock */ + __HAL_RCC_PLLSAI_DISABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLSAI is disabled */ + while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) + { + if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /*---------------------------- SAI configuration -------------------------*/ + /* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must + be added only for SAI configuration */ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI)) + { + assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); + assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); + + /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */ + tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1); + /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ + __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); + } + + /*---------------------------- LTDC configuration ------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC)) + { + assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR)); + assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR)); + + /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */ + tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, PeriphClkInit->PLLSAI.PLLSAIR); + /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ + __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR); + } + /* Enable PLLSAI Clock */ + __HAL_RCC_PLLSAI_ENABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLSAI is ready */ + while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) + { + if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + } + /*--------------------------------------------------------------------------*/ + + /*---------------------------- RTC configuration ---------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) + { + /* Check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + /* Enable Power Clock*/ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Enable write access to Backup domain */ + PWR->CR |= PWR_CR_DBP; + + /* Get tick */ + tickstart = HAL_GetTick(); + + while((PWR->CR & PWR_CR_DBP) == RESET) + { + if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ + tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL); + if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) + { + /* Store the content of BDCR register before the reset of Backup Domain */ + tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + /* Restore the Content of BDCR register */ + RCC->BDCR = tmpreg1; + + /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ + if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + } + /*--------------------------------------------------------------------------*/ + + /*---------------------------- TIM configuration ---------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) + { + __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); + } + return HAL_OK; +} + +/** + * @brief Configures the PeriphClkInit according to the internal + * RCC configuration registers. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * will be configured. + * @retval None + */ +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tempreg; + + /* Set all possible values for the extended clock type parameter------------*/ + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_SAI_PLLSAI | RCC_PERIPHCLK_SAI_PLLI2S | RCC_PERIPHCLK_LTDC | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC; + + /* Get the PLLI2S Clock configuration -----------------------------------------------*/ + PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); + PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); + /* Get the PLLSAI Clock configuration -----------------------------------------------*/ + PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos); + PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); + PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + /* Get the PLLSAI/PLLI2S division factors -----------------------------------------------*/ + PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos); + PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos); + PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR); + /* Get the RTC Clock configuration -----------------------------------------------*/ + tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); + PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); + + if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET) + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; + } + else + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; + } +} + +/** + * @brief Return the peripheral clock frequency for a given peripheral(SAI..) + * @note Return 0 if peripheral clock identifier not managed by this API + * @param PeriphClk Peripheral clock identifier + * This parameter can be one of the following values: + * @arg RCC_PERIPHCLK_I2S: I2S peripheral clock + * @retval Frequency in KHz + */ +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) +{ + /* This variable used to store the I2S clock frequency (value in Hz) */ + uint32_t frequency = 0U; + /* This variable used to store the VCO Input (value in Hz) */ + uint32_t vcoinput = 0U; + uint32_t srcclk = 0U; + /* This variable used to store the VCO Output (value in Hz) */ + uint32_t vcooutput = 0U; + switch (PeriphClk) + { + case RCC_PERIPHCLK_I2S: + { + /* Get the current I2S source */ + srcclk = __HAL_RCC_GET_I2S_SOURCE(); + switch (srcclk) + { + /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ + case RCC_I2SCLKSOURCE_EXT: + { + /* Set the I2S clock to the external clock value */ + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */ + case RCC_I2SCLKSOURCE_PLLI2S: + { + /* Configure the PLLI2S division factor */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ + if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + else + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U))); + /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */ + frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U))); + break; + } + /* Clock not enabled for I2S*/ + default: + { + frequency = 0U; + break; + } + } + break; + } + } + return frequency; +} +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) +/** + * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the + * RCC_PeriphCLKInitTypeDef. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks). + * + * @note A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case + * the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup + * domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tickstart = 0U; + uint32_t tmpreg1 = 0U; + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*---------------------------- I2S configuration ---------------------------*/ + if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || + (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)) + { + /* check for Parameters */ + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); +#if defined(STM32F411xE) + assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM)); +#endif /* STM32F411xE */ + /* Disable the PLLI2S */ + __HAL_RCC_PLLI2S_DISABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLI2S is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + +#if defined(STM32F411xE) + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ + /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ + __HAL_RCC_PLLI2S_I2SCLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SR); +#else + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLM) */ + /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR); +#endif /* STM32F411xE */ + + /* Enable the PLLI2S */ + __HAL_RCC_PLLI2S_ENABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLI2S is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + } + + /*---------------------------- RTC configuration ---------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) + { + /* Check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + /* Enable Power Clock*/ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Enable write access to Backup domain */ + PWR->CR |= PWR_CR_DBP; + + /* Get tick */ + tickstart = HAL_GetTick(); + + while((PWR->CR & PWR_CR_DBP) == RESET) + { + if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ + tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL); + if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) + { + /* Store the content of BDCR register before the reset of Backup Domain */ + tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + /* Restore the Content of BDCR register */ + RCC->BDCR = tmpreg1; + + /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ + if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + } +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) + /*---------------------------- TIM configuration ---------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) + { + __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); + } +#endif /* STM32F401xC || STM32F401xE || STM32F411xE */ + return HAL_OK; +} + +/** + * @brief Configures the RCC_OscInitStruct according to the internal + * RCC configuration registers. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * will be configured. + * @retval None + */ +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tempreg; + + /* Set all possible values for the extended clock type parameter------------*/ + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_RTC; + + /* Get the PLLI2S Clock configuration --------------------------------------*/ + PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); + PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); +#if defined(STM32F411xE) + PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM); +#endif /* STM32F411xE */ + /* Get the RTC Clock configuration -----------------------------------------*/ + tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); + PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); + +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) + /* Get the TIM Prescaler configuration -------------------------------------*/ + if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET) + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; + } + else + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; + } +#endif /* STM32F401xC || STM32F401xE || STM32F411xE */ +} + +/** + * @brief Return the peripheral clock frequency for a given peripheral(SAI..) + * @note Return 0 if peripheral clock identifier not managed by this API + * @param PeriphClk Peripheral clock identifier + * This parameter can be one of the following values: + * @arg RCC_PERIPHCLK_I2S: I2S peripheral clock + * @retval Frequency in KHz + */ +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) +{ + /* This variable used to store the I2S clock frequency (value in Hz) */ + uint32_t frequency = 0U; + /* This variable used to store the VCO Input (value in Hz) */ + uint32_t vcoinput = 0U; + uint32_t srcclk = 0U; + /* This variable used to store the VCO Output (value in Hz) */ + uint32_t vcooutput = 0U; + switch (PeriphClk) + { + case RCC_PERIPHCLK_I2S: + { + /* Get the current I2S source */ + srcclk = __HAL_RCC_GET_I2S_SOURCE(); + switch (srcclk) + { + /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ + case RCC_I2SCLKSOURCE_EXT: + { + /* Set the I2S clock to the external clock value */ + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */ + case RCC_I2SCLKSOURCE_PLLI2S: + { +#if defined(STM32F411xE) + /* Configure the PLLI2S division factor */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ + if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); + } + else + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); + } +#else + /* Configure the PLLI2S division factor */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ + if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + else + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } +#endif /* STM32F411xE */ + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U))); + /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */ + frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U))); + break; + } + /* Clock not enabled for I2S*/ + default: + { + frequency = 0U; + break; + } + } + break; + } + } + return frequency; +} +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/** + * @brief Select LSE mode + * + * @note This mode is only available for STM32F410xx/STM32F411xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices. + * + * @param Mode specifies the LSE mode. + * This parameter can be one of the following values: + * @arg RCC_LSE_LOWPOWER_MODE: LSE oscillator in low power mode selection + * @arg RCC_LSE_HIGHDRIVE_MODE: LSE oscillator in High Drive mode selection + * @retval None + */ +void HAL_RCCEx_SelectLSEMode(uint8_t Mode) +{ + /* Check the parameters */ + assert_param(IS_RCC_LSE_MODE(Mode)); + if(Mode == RCC_LSE_HIGHDRIVE_MODE) + { + SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD); + } + else + { + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD); + } +} + +#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ + +/** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions + * @brief Extended Clock management functions + * +@verbatim + =============================================================================== + ##### Extended clock management functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the + activation or deactivation of PLLI2S, PLLSAI. +@endverbatim + * @{ + */ + +#if defined(RCC_PLLI2S_SUPPORT) +/** + * @brief Enable PLLI2S. + * @param PLLI2SInit pointer to an RCC_PLLI2SInitTypeDef structure that + * contains the configuration information for the PLLI2S + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit) +{ + uint32_t tickstart; + + /* Check for parameters */ + assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SInit->PLLI2SN)); + assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SInit->PLLI2SR)); +#if defined(RCC_PLLI2SCFGR_PLLI2SM) + assert_param(IS_RCC_PLLI2SM_VALUE(PLLI2SInit->PLLI2SM)); +#endif /* RCC_PLLI2SCFGR_PLLI2SM */ +#if defined(RCC_PLLI2SCFGR_PLLI2SP) + assert_param(IS_RCC_PLLI2SP_VALUE(PLLI2SInit->PLLI2SP)); +#endif /* RCC_PLLI2SCFGR_PLLI2SP */ +#if defined(RCC_PLLI2SCFGR_PLLI2SQ) + assert_param(IS_RCC_PLLI2SQ_VALUE(PLLI2SInit->PLLI2SQ)); +#endif /* RCC_PLLI2SCFGR_PLLI2SQ */ + + /* Disable the PLLI2S */ + __HAL_RCC_PLLI2S_DISABLE(); + + /* Wait till PLLI2S is disabled */ + tickstart = HAL_GetTick(); + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /* Configure the PLLI2S division factors */ +#if defined(STM32F446xx) + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ + /* I2SPCLK = PLLI2S_VCO / PLLI2SP */ + /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */ + /* I2SRCLK = PLLI2S_VCO / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SM, PLLI2SInit->PLLI2SN, \ + PLLI2SInit->PLLI2SP, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR); +#elif defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ + defined(STM32F413xx) || defined(STM32F423xx) + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM)*/ + /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */ + /* I2SRCLK = PLLI2S_VCO / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SM, PLLI2SInit->PLLI2SN, \ + PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR); +#elif defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * PLLI2SN */ + /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */ + /* I2SRCLK = PLLI2S_VCO / PLLI2SR */ + __HAL_RCC_PLLI2S_SAICLK_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR); +#elif defined(STM32F411xE) + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ + /* I2SRCLK = PLLI2S_VCO / PLLI2SR */ + __HAL_RCC_PLLI2S_I2SCLK_CONFIG(PLLI2SInit->PLLI2SM, PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SR); +#else + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x PLLI2SN */ + /* I2SRCLK = PLLI2S_VCO / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SR); +#endif /* STM32F446xx */ + + /* Enable the PLLI2S */ + __HAL_RCC_PLLI2S_ENABLE(); + + /* Wait till PLLI2S is ready */ + tickstart = HAL_GetTick(); + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Disable PLLI2S. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void) +{ + uint32_t tickstart; + + /* Disable the PLLI2S */ + __HAL_RCC_PLLI2S_DISABLE(); + + /* Wait till PLLI2S is disabled */ + tickstart = HAL_GetTick(); + while(READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET) + { + if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +#endif /* RCC_PLLI2S_SUPPORT */ + +#if defined(RCC_PLLSAI_SUPPORT) +/** + * @brief Enable PLLSAI. + * @param PLLSAIInit pointer to an RCC_PLLSAIInitTypeDef structure that + * contains the configuration information for the PLLSAI + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit) +{ + uint32_t tickstart; + + /* Check for parameters */ + assert_param(IS_RCC_PLLSAIN_VALUE(PLLSAIInit->PLLSAIN)); + assert_param(IS_RCC_PLLSAIQ_VALUE(PLLSAIInit->PLLSAIQ)); +#if defined(RCC_PLLSAICFGR_PLLSAIM) + assert_param(IS_RCC_PLLSAIM_VALUE(PLLSAIInit->PLLSAIM)); +#endif /* RCC_PLLSAICFGR_PLLSAIM */ +#if defined(RCC_PLLSAICFGR_PLLSAIP) + assert_param(IS_RCC_PLLSAIP_VALUE(PLLSAIInit->PLLSAIP)); +#endif /* RCC_PLLSAICFGR_PLLSAIP */ +#if defined(RCC_PLLSAICFGR_PLLSAIR) + assert_param(IS_RCC_PLLSAIR_VALUE(PLLSAIInit->PLLSAIR)); +#endif /* RCC_PLLSAICFGR_PLLSAIR */ + + /* Disable the PLLSAI */ + __HAL_RCC_PLLSAI_DISABLE(); + + /* Wait till PLLSAI is disabled */ + tickstart = HAL_GetTick(); + while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) + { + if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /* Configure the PLLSAI division factors */ +#if defined(STM32F446xx) + /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * (PLLSAIN/PLLSAIM) */ + /* SAIPCLK = PLLSAI_VCO / PLLSAIP */ + /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */ + /* SAIRCLK = PLLSAI_VCO / PLLSAIR */ + __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIM, PLLSAIInit->PLLSAIN, \ + PLLSAIInit->PLLSAIP, PLLSAIInit->PLLSAIQ, 0U); +#elif defined(STM32F469xx) || defined(STM32F479xx) + /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * PLLSAIN */ + /* SAIPCLK = PLLSAI_VCO / PLLSAIP */ + /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */ + /* SAIRCLK = PLLSAI_VCO / PLLSAIR */ + __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIP, \ + PLLSAIInit->PLLSAIQ, PLLSAIInit->PLLSAIR); +#else + /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x PLLSAIN */ + /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */ + /* SAIRCLK = PLLSAI_VCO / PLLSAIR */ + __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIQ, PLLSAIInit->PLLSAIR); +#endif /* STM32F446xx */ + + /* Enable the PLLSAI */ + __HAL_RCC_PLLSAI_ENABLE(); + + /* Wait till PLLSAI is ready */ + tickstart = HAL_GetTick(); + while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) + { + if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Disable PLLSAI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void) +{ + uint32_t tickstart; + + /* Disable the PLLSAI */ + __HAL_RCC_PLLSAI_DISABLE(); + + /* Wait till PLLSAI is disabled */ + tickstart = HAL_GetTick(); + while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) + { + if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +#endif /* RCC_PLLSAI_SUPPORT */ + +/** + * @} + */ + +#if defined(STM32F446xx) +/** + * @brief Returns the SYSCLK frequency + * + * @note This function implementation is valid only for STM32F446xx devices. + * @note This function add the PLL/PLLR System clock source + * + * @note The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) + * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) + * @note If SYSCLK source is PLL or PLLR, function returns values based on HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * @note (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * @note The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @note This function can be used by the user application to compute the + * baudrate for the communication peripherals or configure other parameters. + * + * @note Each time SYSCLK changes, this function must be called to update the + * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + uint32_t pllm = 0U; + uint32_t pllvco = 0U; + uint32_t pllp = 0U; + uint32_t pllr = 0U; + uint32_t sysclockfreq = 0U; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR & RCC_CFGR_SWS) + { + case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ + { + sysclockfreq = HSI_VALUE; + break; + } + case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ + { + sysclockfreq = HSE_VALUE; + break; + } + case RCC_CFGR_SWS_PLL: /* PLL/PLLP used as system clock source */ + { + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + SYSCLK = PLL_VCO / PLLP */ + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) + { + /* HSE used as PLL clock source */ + pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); + } + pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U); + + sysclockfreq = pllvco/pllp; + break; + } + case RCC_CFGR_SWS_PLLR: /* PLL/PLLR used as system clock source */ + { + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR */ + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) + { + /* HSE used as PLL clock source */ + pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); + } + pllr = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos); + + sysclockfreq = pllvco/pllr; + break; + } + default: + { + sysclockfreq = HSI_VALUE; + break; + } + } + return sysclockfreq; +} +#endif /* STM32F446xx */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @brief Resets the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - HSI ON and used as system clock source + * - HSE, PLL, PLLI2S and PLLSAI OFF + * - AHB, APB1 and APB2 prescaler set to 1. + * - CSS, MCO1 and MCO2 OFF + * - All interrupts disabled + * @note This function doesn't modify the configuration of the + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_DeInit(void) +{ + uint32_t tickstart; + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Set HSION bit to the reset value */ + SET_BIT(RCC->CR, RCC_CR_HSION); + + /* Wait till HSI is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Set HSITRIM[4:0] bits to the reset value */ + SET_BIT(RCC->CR, RCC_CR_HSITRIM_4); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Reset CFGR register */ + CLEAR_REG(RCC->CFGR); + + /* Wait till clock switch is ready */ + while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Clear HSEON, HSEBYP and CSSON bits */ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON); + + /* Wait till HSE is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Clear PLLON bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLLON); + + /* Wait till PLL is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + +#if defined(RCC_PLLI2S_SUPPORT) + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Reset PLLI2SON bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON); + + /* Wait till PLLI2S is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } +#endif /* RCC_PLLI2S_SUPPORT */ + +#if defined(RCC_PLLSAI_SUPPORT) + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Reset PLLSAI bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION); + + /* Wait till PLLSAI is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } +#endif /* RCC_PLLSAI_SUPPORT */ + + /* Once PLL, PLLI2S and PLLSAI are OFF, reset PLLCFGR register to default value */ +#if defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || \ + defined(STM32F423xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) + RCC->PLLCFGR = RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLR_1; +#elif defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) + RCC->PLLCFGR = RCC_PLLCFGR_PLLR_0 | RCC_PLLCFGR_PLLR_1 | RCC_PLLCFGR_PLLR_2 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_0 | RCC_PLLCFGR_PLLQ_1 | RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLQ_3; +#else + RCC->PLLCFGR = RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2; +#endif /* STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx || STM32F446xx || STM32F469xx || STM32F479xx */ + + /* Reset PLLI2SCFGR register to default value */ +#if defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || \ + defined(STM32F423xx) || defined(STM32F446xx) + RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SR_1; +#elif defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) + RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1; +#elif defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) + RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SR_1; +#elif defined(STM32F411xE) + RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1; +#endif /* STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx || STM32F446xx */ + + /* Reset PLLSAICFGR register */ +#if defined(STM32F427xx) || defined(STM32F429xx) || defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) + RCC->PLLSAICFGR = RCC_PLLSAICFGR_PLLSAIN_6 | RCC_PLLSAICFGR_PLLSAIN_7 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIR_1; +#elif defined(STM32F446xx) + RCC->PLLSAICFGR = RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIN_6 | RCC_PLLSAICFGR_PLLSAIN_7 | RCC_PLLSAICFGR_PLLSAIQ_2; +#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F469xx || STM32F479xx */ + + /* Disable all interrupts */ + CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE | RCC_CIR_LSERDYIE | RCC_CIR_HSIRDYIE | RCC_CIR_HSERDYIE | RCC_CIR_PLLRDYIE); + +#if defined(RCC_CIR_PLLI2SRDYIE) + CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE); +#endif /* RCC_CIR_PLLI2SRDYIE */ + +#if defined(RCC_CIR_PLLSAIRDYIE) + CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE); +#endif /* RCC_CIR_PLLSAIRDYIE */ + + /* Clear all interrupt flags */ + SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_CSSC); + +#if defined(RCC_CIR_PLLI2SRDYC) + SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC); +#endif /* RCC_CIR_PLLI2SRDYC */ + +#if defined(RCC_CIR_PLLSAIRDYC) + SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC); +#endif /* RCC_CIR_PLLSAIRDYC */ + + /* Clear LSION bit */ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); + + /* Reset all CSR flags */ + SET_BIT(RCC->CSR, RCC_CSR_RMVF); + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HSI_VALUE; + + /* Adapt Systick interrupt period */ + if(HAL_InitTick(uwTickPrio) != HAL_OK) + { + return HAL_ERROR; + } + else + { + return HAL_OK; + } +} + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/** + * @brief Initializes the RCC Oscillators according to the specified parameters in the + * RCC_OscInitTypeDef. + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC Oscillators. + * @note The PLL is not disabled when used as system clock. + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not + * supported by this API. User should request a transition to LSE Off + * first and then LSE On or LSE Bypass. + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this API. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @note This function add the PLL/PLLR factor management during PLL configuration this feature + * is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + uint32_t tickstart = 0U; + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + /*------------------------------- HSE Configuration ------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ +#if defined(STM32F446xx) + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\ + ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) ||\ + ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) +#else + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\ + ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) +#endif /* STM32F446xx */ + { + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + { + return HAL_ERROR; + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + + /* Check the HSE State */ + if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSE is bypassed or disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ +#if defined(STM32F446xx) + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\ + ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) ||\ + ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) +#else + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\ + ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) +#endif /* STM32F446xx */ + { + /* When HSI is used as system clock it will not disabled */ + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + { + return HAL_ERROR; + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + } + else + { + /* Check the HSI State */ + if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF) + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF) + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + { + FlagStatus pwrclkchanged = RESET; + + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + { + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + + if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + /* Check the LSE State */ + if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Restore clock configuration if changed */ + if(pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } + } + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + { + /* Check if the PLL is used as system clock or not */ + if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) + { + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + { + /* Check the parameters */ + assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM)); + assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); + assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); + assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); + assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure the main PLL clock source, multiplication and division factors. */ + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + RCC_OscInitStruct->PLL.PLLM, + RCC_OscInitStruct->PLL.PLLN, + RCC_OscInitStruct->PLL.PLLP, + RCC_OscInitStruct->PLL.PLLQ, + RCC_OscInitStruct->PLL.PLLR); + + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + else + { + return HAL_ERROR; + } + } + return HAL_OK; +} + +/** + * @brief Configures the RCC_OscInitStruct according to the internal + * RCC configuration registers. + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that will be configured. + * + * @note This function is only available in case of STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices. + * @note This function add the PLL/PLLR factor management + * @retval None + */ +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + /* Set all possible values for the Oscillator type parameter ---------------*/ + RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI; + + /* Get the HSE configuration -----------------------------------------------*/ + if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP) + { + RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; + } + else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON) + { + RCC_OscInitStruct->HSEState = RCC_HSE_ON; + } + else + { + RCC_OscInitStruct->HSEState = RCC_HSE_OFF; + } + + /* Get the HSI configuration -----------------------------------------------*/ + if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION) + { + RCC_OscInitStruct->HSIState = RCC_HSI_ON; + } + else + { + RCC_OscInitStruct->HSIState = RCC_HSI_OFF; + } + + RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); + + /* Get the LSE configuration -----------------------------------------------*/ + if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) + { + RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; + } + else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON) + { + RCC_OscInitStruct->LSEState = RCC_LSE_ON; + } + else + { + RCC_OscInitStruct->LSEState = RCC_LSE_OFF; + } + + /* Get the LSI configuration -----------------------------------------------*/ + if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION) + { + RCC_OscInitStruct->LSIState = RCC_LSI_ON; + } + else + { + RCC_OscInitStruct->LSIState = RCC_LSI_OFF; + } + + /* Get the PLL configuration -----------------------------------------------*/ + if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON) + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; + } + else + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; + } + RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); + RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM); + RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1U) >> RCC_PLLCFGR_PLLP_Pos); + RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos); + RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos); +} +#endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ + +#endif /* HAL_RCC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c new file mode 100644 index 0000000..99531f7 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c @@ -0,0 +1,3820 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_spi.c + * @author MCD Application Team + * @brief SPI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Serial Peripheral Interface (SPI) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The SPI HAL driver can be used as follows: + + (#) Declare a SPI_HandleTypeDef handle structure, for example: + SPI_HandleTypeDef hspi; + + (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API: + (##) Enable the SPIx interface clock + (##) SPI pins configuration + (+++) Enable the clock for the SPI GPIOs + (+++) Configure these SPI pins as alternate function push-pull + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the SPIx interrupt priority + (+++) Enable the NVIC SPI IRQ handle + (##) DMA Configuration if you need to use DMA process + (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel + (+++) Enable the DMAx clock + (+++) Configure the DMA handle parameters + (+++) Configure the DMA Tx or Rx Stream/Channel + (+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel + + (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS + management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. + + (#) Initialize the SPI registers by calling the HAL_SPI_Init() API: + (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) + by calling the customized HAL_SPI_MspInit() API. + [..] + Circular mode restriction: + (#) The DMA circular mode cannot be used when the SPI is configured in these modes: + (##) Master 2Lines RxOnly + (##) Master 1Line Rx + (#) The CRC feature is not managed when the DMA circular mode is enabled + (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs + the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks + [..] + Master Receive mode restriction: + (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or + bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI + does not initiate a new transfer the following procedure has to be respected: + (##) HAL_SPI_DeInit() + (##) HAL_SPI_Init() + [..] + Callback registration: + + (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U + allows the user to configure dynamically the driver callbacks. + Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback. + + Function HAL_SPI_RegisterCallback() allows to register following callbacks: + (++) TxCpltCallback : SPI Tx Completed callback + (++) RxCpltCallback : SPI Rx Completed callback + (++) TxRxCpltCallback : SPI TxRx Completed callback + (++) TxHalfCpltCallback : SPI Tx Half Completed callback + (++) RxHalfCpltCallback : SPI Rx Half Completed callback + (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback + (++) ErrorCallback : SPI Error callback + (++) AbortCpltCallback : SPI Abort callback + (++) MspInitCallback : SPI Msp Init callback + (++) MspDeInitCallback : SPI Msp DeInit callback + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + + (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default + weak function. + HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (++) TxCpltCallback : SPI Tx Completed callback + (++) RxCpltCallback : SPI Rx Completed callback + (++) TxRxCpltCallback : SPI TxRx Completed callback + (++) TxHalfCpltCallback : SPI Tx Half Completed callback + (++) RxHalfCpltCallback : SPI Rx Half Completed callback + (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback + (++) ErrorCallback : SPI Error callback + (++) AbortCpltCallback : SPI Abort callback + (++) MspInitCallback : SPI Msp Init callback + (++) MspDeInitCallback : SPI Msp DeInit callback + + [..] + By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when + these callbacks are null (not registered beforehand). + If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + + [..] + Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + Then, the user first registers the MspInit/MspDeInit user callbacks + using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit() + or HAL_SPI_Init() function. + + [..] + When the compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + + [..] + Using the HAL it is not possible to reach all supported SPI frequency with the different SPI Modes, + the following table resume the max SPI frequency reached with data size 8bits/16bits, + according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance. + + @endverbatim + + Additional table : + + DataSize = SPI_DATASIZE_8BIT: + +----------------------------------------------------------------------------------------------+ + | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | + | Process | Tranfert mode |---------------------|----------------------|----------------------| + | | | Master | Slave | Master | Slave | Master | Slave | + |==============================================================================================| + | T | Polling | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | / | Interrupt | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA | + | R |----------------|----------|----------|-----------|----------|-----------|----------| + | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | + |=========|================|==========|==========|===========|==========|===========|==========| + | | Polling | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/64 | Fpclk/2 | + | |----------------|----------|----------|-----------|----------|-----------|----------| + | R | Interrupt | Fpclk/8 | Fpclk/8 | Fpclk/64 | Fpclk/2 | Fpclk/64 | Fpclk/2 | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | | DMA | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/128 | Fpclk/2 | + |=========|================|==========|==========|===========|==========|===========|==========| + | | Polling | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/2 | Fpclk/64 | + | |----------------|----------|----------|-----------|----------|-----------|----------| + | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/2 | Fpclk/64 | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/128| + +----------------------------------------------------------------------------------------------+ + + DataSize = SPI_DATASIZE_16BIT: + +----------------------------------------------------------------------------------------------+ + | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | + | Process | Tranfert mode |---------------------|----------------------|----------------------| + | | | Master | Slave | Master | Slave | Master | Slave | + |==============================================================================================| + | T | Polling | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | / | Interrupt | Fpclk/4 | Fpclk/4 | NA | NA | NA | NA | + | R |----------------|----------|----------|-----------|----------|-----------|----------| + | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | + |=========|================|==========|==========|===========|==========|===========|==========| + | | Polling | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/32 | Fpclk/2 | + | |----------------|----------|----------|-----------|----------|-----------|----------| + | R | Interrupt | Fpclk/4 | Fpclk/4 | Fpclk/64 | Fpclk/2 | Fpclk/64 | Fpclk/2 | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | | DMA | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/128 | Fpclk/2 | + |=========|================|==========|==========|===========|==========|===========|==========| + | | Polling | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/32 | + | |----------------|----------|----------|-----------|----------|-----------|----------| + | T | Interrupt | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/64 | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/128| + +----------------------------------------------------------------------------------------------+ + @note The max SPI frequency depend on SPI data size (8bits, 16bits), + SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA). + @note + (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA() + (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() + (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA() + + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup SPI SPI + * @brief SPI HAL module driver + * @{ + */ +#ifdef HAL_SPI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup SPI_Private_Constants SPI Private Constants + * @{ + */ +#define SPI_DEFAULT_TIMEOUT 100U +#define SPI_BSY_FLAG_WORKAROUND_TIMEOUT 1000U /*!< Timeout 1000 µs */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup SPI_Private_Functions SPI Private Functions + * @{ + */ +static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAError(DMA_HandleTypeDef *hdma); +static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma); +static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma); +static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, + uint32_t Timeout, uint32_t Tickstart); +static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi); +#if (USE_SPI_CRC != 0U) +static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi); +static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi); +#endif /* USE_SPI_CRC */ +static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi); +static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi); +static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi); +static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi); +static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi); +static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SPI_Exported_Functions SPI Exported Functions + * @{ + */ + +/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + de-initialize the SPIx peripheral: + + (+) User must implement HAL_SPI_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + + (+) Call the function HAL_SPI_Init() to configure the selected device with + the selected configuration: + (++) Mode + (++) Direction + (++) Data Size + (++) Clock Polarity and Phase + (++) NSS Management + (++) BaudRate Prescaler + (++) FirstBit + (++) TIMode + (++) CRC Calculation + (++) CRC Polynomial if CRC enabled + + (+) Call the function HAL_SPI_DeInit() to restore the default configuration + of the selected SPIx peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the SPI according to the specified parameters + * in the SPI_InitTypeDef and initialize the associated handle. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) +{ + /* Check the SPI handle allocation */ + if (hspi == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); + assert_param(IS_SPI_MODE(hspi->Init.Mode)); + assert_param(IS_SPI_DIRECTION(hspi->Init.Direction)); + assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize)); + assert_param(IS_SPI_NSS(hspi->Init.NSS)); + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); + assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); + if (hspi->Init.TIMode == SPI_TIMODE_DISABLE) + { + assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); + assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); + } +#if (USE_SPI_CRC != 0U) + assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation)); + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); + } +#else + hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; +#endif /* USE_SPI_CRC */ + + if (hspi->State == HAL_SPI_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hspi->Lock = HAL_UNLOCKED; + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + /* Init the SPI Callback settings */ + hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */ + hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */ + hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ + hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */ + hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */ + hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + + if (hspi->MspInitCallback == NULL) + { + hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + hspi->MspInitCallback(hspi); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_SPI_MspInit(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + + hspi->State = HAL_SPI_STATE_BUSY; + + /* Disable the selected SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + + /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ + /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management, + Communication speed, First bit and CRC calculation state */ + WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize | + hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) | + hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation)); + + /* Configure : NSS management, TI Mode */ + WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode)); + +#if (USE_SPI_CRC != 0U) + /*---------------------------- SPIx CRCPOLY Configuration ------------------*/ + /* Configure : CRC Polynomial */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial); + } +#endif /* USE_SPI_CRC */ + +#if defined(SPI_I2SCFGR_I2SMOD) + /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ + CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); +#endif /* SPI_I2SCFGR_I2SMOD */ + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->State = HAL_SPI_STATE_READY; + + return HAL_OK; +} + +/** + * @brief De-Initialize the SPI peripheral. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) +{ + /* Check the SPI handle allocation */ + if (hspi == NULL) + { + return HAL_ERROR; + } + + /* Check SPI Instance parameter */ + assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); + + hspi->State = HAL_SPI_STATE_BUSY; + + /* Disable the SPI Peripheral Clock */ + __HAL_SPI_DISABLE(hspi); + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + if (hspi->MspDeInitCallback == NULL) + { + hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + hspi->MspDeInitCallback(hspi); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + HAL_SPI_MspDeInit(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->State = HAL_SPI_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief Initialize the SPI MSP. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_MspInit should be implemented in the user file + */ +} + +/** + * @brief De-Initialize the SPI MSP. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_MspDeInit should be implemented in the user file + */ +} + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +/** + * @brief Register a User SPI Callback + * To be used instead of the weak predefined callback + * @param hspi Pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI. + * @param CallbackID ID of the callback to be registered + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, + pSPI_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hspi); + + if (HAL_SPI_STATE_READY == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_TX_COMPLETE_CB_ID : + hspi->TxCpltCallback = pCallback; + break; + + case HAL_SPI_RX_COMPLETE_CB_ID : + hspi->RxCpltCallback = pCallback; + break; + + case HAL_SPI_TX_RX_COMPLETE_CB_ID : + hspi->TxRxCpltCallback = pCallback; + break; + + case HAL_SPI_TX_HALF_COMPLETE_CB_ID : + hspi->TxHalfCpltCallback = pCallback; + break; + + case HAL_SPI_RX_HALF_COMPLETE_CB_ID : + hspi->RxHalfCpltCallback = pCallback; + break; + + case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID : + hspi->TxRxHalfCpltCallback = pCallback; + break; + + case HAL_SPI_ERROR_CB_ID : + hspi->ErrorCallback = pCallback; + break; + + case HAL_SPI_ABORT_CB_ID : + hspi->AbortCpltCallback = pCallback; + break; + + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = pCallback; + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_SPI_STATE_RESET == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = pCallback; + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hspi); + return status; +} + +/** + * @brief Unregister an SPI Callback + * SPI callback is redirected to the weak predefined callback + * @param hspi Pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI. + * @param CallbackID ID of the callback to be unregistered + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hspi); + + if (HAL_SPI_STATE_READY == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_TX_COMPLETE_CB_ID : + hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_SPI_RX_COMPLETE_CB_ID : + hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + + case HAL_SPI_TX_RX_COMPLETE_CB_ID : + hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ + break; + + case HAL_SPI_TX_HALF_COMPLETE_CB_ID : + hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + break; + + case HAL_SPI_RX_HALF_COMPLETE_CB_ID : + hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + break; + + case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID : + hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */ + break; + + case HAL_SPI_ERROR_CB_ID : + hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_SPI_ABORT_CB_ID : + hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_SPI_STATE_RESET == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hspi); + return status; +} +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup SPI_Exported_Functions_Group2 IO operation functions + * @brief Data transfers functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the SPI + data transfers. + + [..] The SPI supports master and slave mode : + + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode: The communication is performed using Interrupts + or DMA, These APIs return the HAL status. + The end of the data processing will be indicated through the + dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks + will be executed respectively at the end of the transmit or Receive process + The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected + + (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA) + exist for 1Line (simplex) and 2Lines (full duplex) modes. + +@endverbatim + * @{ + */ + +/** + * @brief Transmit an amount of data in blocking mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData pointer to data buffer + * @param Size amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + HAL_StatusTypeDef errorcode = HAL_OK; + uint16_t initial_TxXferCount; + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + initial_TxXferCount = Size; + + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } + + if ((pData == NULL) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->pRxBuffPtr = (uint8_t *)NULL; + hspi->RxXferSize = 0U; + hspi->RxXferCount = 0U; + hspi->TxISR = NULL; + hspi->RxISR = NULL; + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_TX(hspi); + } + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Transmit data in 16 Bit mode */ + if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + { + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + } + /* Transmit data in 16 Bit mode */ + while (hspi->TxXferCount > 0U) + { + /* Wait until TXE flag is set to send data */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) + { + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + errorcode = HAL_TIMEOUT; + goto error; + } + } + } + } + /* Transmit data in 8 Bit mode */ + else + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + { + *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint8_t); + hspi->TxXferCount--; + } + while (hspi->TxXferCount > 0U) + { + /* Wait until TXE flag is set to send data */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) + { + *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint8_t); + hspi->TxXferCount--; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + errorcode = HAL_TIMEOUT; + goto error; + } + } + } + } +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + } + + /* Clear overrun flag in 2 Lines communication mode because received is not read */ + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + errorcode = HAL_ERROR; + } + +error: + hspi->State = HAL_SPI_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; +} + +/** + * @brief Receive an amount of data in blocking mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData pointer to data buffer + * @param Size amount of data to be received + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + HAL_StatusTypeDef errorcode = HAL_OK; + + if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) + { + hspi->State = HAL_SPI_STATE_BUSY_RX; + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout); + } + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } + + if ((pData == NULL) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = (uint8_t *)pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->pTxBuffPtr = (uint8_t *)NULL; + hspi->TxXferSize = 0U; + hspi->TxXferCount = 0U; + hspi->RxISR = NULL; + hspi->TxISR = NULL; + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + /* this is done to handle the CRCNEXT before the latest data */ + hspi->RxXferCount--; + } +#endif /* USE_SPI_CRC */ + + /* Configure communication direction: 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_RX(hspi); + } + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Receive data in 8 Bit mode */ + if (hspi->Init.DataSize == SPI_DATASIZE_8BIT) + { + /* Transfer loop */ + while (hspi->RxXferCount > 0U) + { + /* Check the RXNE flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) + { + /* read the received data */ + (* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR; + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount--; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + errorcode = HAL_TIMEOUT; + goto error; + } + } + } + } + else + { + /* Transfer loop */ + while (hspi->RxXferCount > 0U) + { + /* Check the RXNE flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) + { + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + errorcode = HAL_TIMEOUT; + goto error; + } + } + } + } + +#if (USE_SPI_CRC != 0U) + /* Handle the CRC Transmission */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* freeze the CRC before the latest data */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + + /* Read the latest data */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) + { + /* the latest data has not been received */ + errorcode = HAL_TIMEOUT; + goto error; + } + + /* Receive last data in 16 Bit mode */ + if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) + { + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; + } + /* Receive last data in 8 Bit mode */ + else + { + (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR; + } + + /* Wait the CRC data */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + errorcode = HAL_TIMEOUT; + goto error; + } + + /* Read CRC to Flush DR and RXNE flag */ + READ_REG(hspi->Instance->DR); + } +#endif /* USE_SPI_CRC */ + + /* Check the end of the transaction */ + if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + } + +#if (USE_SPI_CRC != 0U) + /* Check if CRC error occurred */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } +#endif /* USE_SPI_CRC */ + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + errorcode = HAL_ERROR; + } + +error : + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return errorcode; +} + +/** + * @brief Transmit and Receive an amount of data in blocking mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData pointer to transmission data buffer + * @param pRxData pointer to reception data buffer + * @param Size amount of data to be sent and received + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, + uint32_t Timeout) +{ + uint16_t initial_TxXferCount; + uint32_t tmp_mode; + HAL_SPI_StateTypeDef tmp_state; + uint32_t tickstart; + + /* Variable used to alternate Rx and Tx during transfer */ + uint32_t txallowed = 1U; + HAL_StatusTypeDef errorcode = HAL_OK; + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* Init temporary variables */ + tmp_state = hspi->State; + tmp_mode = hspi->Init.Mode; + initial_TxXferCount = Size; + + if (!((tmp_state == HAL_SPI_STATE_READY) || \ + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + { + errorcode = HAL_BUSY; + goto error; + } + + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } + + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ + if (hspi->State != HAL_SPI_STATE_BUSY_RX) + { + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + } + + /* Set the transaction information */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = (uint8_t *)pRxData; + hspi->RxXferCount = Size; + hspi->RxXferSize = Size; + hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->TxXferCount = Size; + hspi->TxXferSize = Size; + + /*Init field not used in handle to zero */ + hspi->RxISR = NULL; + hspi->TxISR = NULL; + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Transmit and Receive data in 16 Bit mode */ + if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + { + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + } + while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) + { + /* Check TXE flag */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) + { + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + /* Next Data is a reception (Rx). Tx not allowed */ + txallowed = 0U; + +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + } + + /* Check RXNE flag */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U)) + { + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + /* Next Data is a Transmission (Tx). Tx is allowed */ + txallowed = 1U; + } + if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) + { + errorcode = HAL_TIMEOUT; + goto error; + } + } + } + /* Transmit and Receive data in 8 Bit mode */ + else + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + { + *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint8_t); + hspi->TxXferCount--; + } + while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) + { + /* Check TXE flag */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) + { + *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + hspi->pTxBuffPtr++; + hspi->TxXferCount--; + /* Next Data is a reception (Rx). Tx not allowed */ + txallowed = 0U; + +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + } + + /* Wait until RXNE flag is reset */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U)) + { + (*(uint8_t *)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr++; + hspi->RxXferCount--; + /* Next Data is a Transmission (Tx). Tx is allowed */ + txallowed = 1U; + } + if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U)) + { + errorcode = HAL_TIMEOUT; + goto error; + } + } + } + +#if (USE_SPI_CRC != 0U) + /* Read CRC from DR to close CRC calculation process */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Wait until TXE flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) + { + /* Error on the CRC reception */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + errorcode = HAL_TIMEOUT; + goto error; + } + /* Read CRC */ + READ_REG(hspi->Instance->DR); + } + + /* Check if CRC error occurred */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + /* Clear CRC Flag */ + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + + errorcode = HAL_ERROR; + } +#endif /* USE_SPI_CRC */ + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) + { + errorcode = HAL_ERROR; + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + goto error; + } + + /* Clear overrun flag in 2 Lines communication mode because received is not read */ + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + +error : + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return errorcode; +} + +/** + * @brief Transmit an amount of data in non-blocking mode with Interrupt. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData pointer to data buffer + * @param Size amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef errorcode = HAL_OK; + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + + /* Process Locked */ + __HAL_LOCK(hspi); + + if ((pData == NULL) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } + + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /* Init field not used in handle to zero */ + hspi->pRxBuffPtr = (uint8_t *)NULL; + hspi->RxXferSize = 0U; + hspi->RxXferCount = 0U; + hspi->RxISR = NULL; + + /* Set the function for IT treatment */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + hspi->TxISR = SPI_TxISR_16BIT; + } + else + { + hspi->TxISR = SPI_TxISR_8BIT; + } + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_TX(hspi); + } + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Enable TXE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); + + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + +error : + __HAL_UNLOCK(hspi); + return errorcode; +} + +/** + * @brief Receive an amount of data in non-blocking mode with Interrupt. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData pointer to data buffer + * @param Size amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef errorcode = HAL_OK; + + if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + hspi->State = HAL_SPI_STATE_BUSY_RX; + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size); + } + + /* Process Locked */ + __HAL_LOCK(hspi); + + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } + + if ((pData == NULL) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = (uint8_t *)pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /* Init field not used in handle to zero */ + hspi->pTxBuffPtr = (uint8_t *)NULL; + hspi->TxXferSize = 0U; + hspi->TxXferCount = 0U; + hspi->TxISR = NULL; + + /* Set the function for IT treatment */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + hspi->RxISR = SPI_RxISR_16BIT; + } + else + { + hspi->RxISR = SPI_RxISR_8BIT; + } + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_RX(hspi); + } + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Enable TXE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + /* Note : The SPI must be enabled after unlocking current process + to avoid the risk of SPI interrupt handle execution before current + process unlock */ + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + +error : + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; +} + +/** + * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData pointer to transmission data buffer + * @param pRxData pointer to reception data buffer + * @param Size amount of data to be sent and received + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +{ + uint32_t tmp_mode; + HAL_SPI_StateTypeDef tmp_state; + HAL_StatusTypeDef errorcode = HAL_OK; + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + /* Process locked */ + __HAL_LOCK(hspi); + + /* Init temporary variables */ + tmp_state = hspi->State; + tmp_mode = hspi->Init.Mode; + + if (!((tmp_state == HAL_SPI_STATE_READY) || \ + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + { + errorcode = HAL_BUSY; + goto error; + } + + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } + + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ + if (hspi->State != HAL_SPI_STATE_BUSY_RX) + { + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + } + + /* Set the transaction information */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + hspi->pRxBuffPtr = (uint8_t *)pRxData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /* Set the function for IT treatment */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + hspi->RxISR = SPI_2linesRxISR_16BIT; + hspi->TxISR = SPI_2linesTxISR_16BIT; + } + else + { + hspi->RxISR = SPI_2linesRxISR_8BIT; + hspi->TxISR = SPI_2linesTxISR_8BIT; + } + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Enable TXE, RXNE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + +error : + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; +} + +/** + * @brief Transmit an amount of data in non-blocking mode with DMA. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData pointer to data buffer + * @param Size amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef errorcode = HAL_OK; + + /* Check tx dma handle */ + assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + + /* Process Locked */ + __HAL_LOCK(hspi); + + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } + + if ((pData == NULL) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /* Init field not used in handle to zero */ + hspi->pRxBuffPtr = (uint8_t *)NULL; + hspi->TxISR = NULL; + hspi->RxISR = NULL; + hspi->RxXferSize = 0U; + hspi->RxXferCount = 0U; + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_TX(hspi); + } + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Set the SPI TxDMA Half transfer complete callback */ + hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt; + + /* Set the SPI TxDMA transfer complete callback */ + hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt; + + /* Set the DMA error callback */ + hspi->hdmatx->XferErrorCallback = SPI_DMAError; + + /* Set the DMA AbortCpltCallback */ + hspi->hdmatx->XferAbortCallback = NULL; + + /* Enable the Tx DMA Stream/Channel */ + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, + hspi->TxXferCount)) + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + errorcode = HAL_ERROR; + + hspi->State = HAL_SPI_STATE_READY; + goto error; + } + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Enable the SPI Error Interrupt Bit */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); + + /* Enable Tx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + +error : + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; +} + +/** + * @brief Receive an amount of data in non-blocking mode with DMA. + * @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData pointer to data buffer + * @note When the CRC feature is enabled the pData Length must be Size + 1. + * @param Size amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef errorcode = HAL_OK; + + /* Check rx dma handle */ + assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); + + if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + hspi->State = HAL_SPI_STATE_BUSY_RX; + + /* Check tx dma handle */ + assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); + + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size); + } + + /* Process Locked */ + __HAL_LOCK(hspi); + + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } + + if ((pData == NULL) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = (uint8_t *)pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->RxISR = NULL; + hspi->TxISR = NULL; + hspi->TxXferSize = 0U; + hspi->TxXferCount = 0U; + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_RX(hspi); + } + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Set the SPI RxDMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; + + /* Set the SPI Rx DMA transfer complete callback */ + hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; + + /* Set the DMA error callback */ + hspi->hdmarx->XferErrorCallback = SPI_DMAError; + + /* Set the DMA AbortCpltCallback */ + hspi->hdmarx->XferAbortCallback = NULL; + + /* Enable the Rx DMA Stream/Channel */ + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, + hspi->RxXferCount)) + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + errorcode = HAL_ERROR; + + hspi->State = HAL_SPI_STATE_READY; + goto error; + } + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Enable the SPI Error Interrupt Bit */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); + + /* Enable Rx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + +error: + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; +} + +/** + * @brief Transmit and Receive an amount of data in non-blocking mode with DMA. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData pointer to transmission data buffer + * @param pRxData pointer to reception data buffer + * @note When the CRC feature is enabled the pRxData Length must be Size + 1 + * @param Size amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) +{ + uint32_t tmp_mode; + HAL_SPI_StateTypeDef tmp_state; + HAL_StatusTypeDef errorcode = HAL_OK; + + /* Check rx & tx dma handles */ + assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); + assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + /* Process locked */ + __HAL_LOCK(hspi); + + /* Init temporary variables */ + tmp_state = hspi->State; + tmp_mode = hspi->Init.Mode; + + if (!((tmp_state == HAL_SPI_STATE_READY) || + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + { + errorcode = HAL_BUSY; + goto error; + } + + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } + + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ + if (hspi->State != HAL_SPI_STATE_BUSY_RX) + { + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + } + + /* Set the transaction information */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + hspi->pRxBuffPtr = (uint8_t *)pRxData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /* Init field not used in handle to zero */ + hspi->RxISR = NULL; + hspi->TxISR = NULL; + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */ + if (hspi->State == HAL_SPI_STATE_BUSY_RX) + { + /* Set the SPI Rx DMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; + hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; + } + else + { + /* Set the SPI Tx/Rx DMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt; + hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt; + } + + /* Set the DMA error callback */ + hspi->hdmarx->XferErrorCallback = SPI_DMAError; + + /* Set the DMA AbortCpltCallback */ + hspi->hdmarx->XferAbortCallback = NULL; + + /* Enable the Rx DMA Stream/Channel */ + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, + hspi->RxXferCount)) + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + errorcode = HAL_ERROR; + + hspi->State = HAL_SPI_STATE_READY; + goto error; + } + + /* Enable Rx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing + is performed in DMA reception complete callback */ + hspi->hdmatx->XferHalfCpltCallback = NULL; + hspi->hdmatx->XferCpltCallback = NULL; + hspi->hdmatx->XferErrorCallback = NULL; + hspi->hdmatx->XferAbortCallback = NULL; + + /* Enable the Tx DMA Stream/Channel */ + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, + hspi->TxXferCount)) + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + errorcode = HAL_ERROR; + + hspi->State = HAL_SPI_STATE_READY; + goto error; + } + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + /* Enable the SPI Error Interrupt Bit */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); + + /* Enable Tx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + +error : + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; +} + +/** + * @brief Abort ongoing transfer (blocking mode). + * @param hspi SPI handle. + * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx), + * started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable SPI Interrupts (depending of transfer direction) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) +{ + HAL_StatusTypeDef errorcode; + __IO uint32_t count; + __IO uint32_t resetcount; + + /* Initialized local variable */ + errorcode = HAL_OK; + resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + count = resetcount; + + /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE); + + /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)) + { + hspi->TxISR = SPI_AbortTx_ISR; + /* Wait HAL_SPI_STATE_ABORT state */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } while (hspi->State != HAL_SPI_STATE_ABORT); + /* Reset Timeout Counter */ + count = resetcount; + } + + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) + { + hspi->RxISR = SPI_AbortRx_ISR; + /* Wait HAL_SPI_STATE_ABORT state */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } while (hspi->State != HAL_SPI_STATE_ABORT); + /* Reset Timeout Counter */ + count = resetcount; + } + + /* Disable the SPI DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) + { + /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */ + if (hspi->hdmatx != NULL) + { + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */ + hspi->hdmatx->XferAbortCallback = NULL; + + /* Abort DMA Tx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Disable Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN)); + + /* Wait until TXE flag is set */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET); + } + } + + /* Disable the SPI DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)) + { + /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */ + if (hspi->hdmarx != NULL) + { + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */ + hspi->hdmarx->XferAbortCallback = NULL; + + /* Abort DMA Rx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Disable peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Disable Rx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN)); + } + } + /* Reset Tx and Rx transfer counters */ + hspi->RxXferCount = 0U; + hspi->TxXferCount = 0U; + + /* Check error during Abort procedure */ + if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT) + { + /* return HAL_Error in case of error during Abort procedure */ + errorcode = HAL_ERROR; + } + else + { + /* Reset errorCode */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + } + + /* Clear the Error flags in the SR register */ + __HAL_SPI_CLEAR_OVRFLAG(hspi); + __HAL_SPI_CLEAR_FREFLAG(hspi); + + /* Restore hspi->state to ready */ + hspi->State = HAL_SPI_STATE_READY; + + return errorcode; +} + +/** + * @brief Abort ongoing transfer (Interrupt mode). + * @param hspi SPI handle. + * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx), + * started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable SPI Interrupts (depending of transfer direction) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) +{ + HAL_StatusTypeDef errorcode; + uint32_t abortcplt ; + __IO uint32_t count; + __IO uint32_t resetcount; + + /* Initialized local variable */ + errorcode = HAL_OK; + abortcplt = 1U; + resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + count = resetcount; + + /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE); + + /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)) + { + hspi->TxISR = SPI_AbortTx_ISR; + /* Wait HAL_SPI_STATE_ABORT state */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } while (hspi->State != HAL_SPI_STATE_ABORT); + /* Reset Timeout Counter */ + count = resetcount; + } + + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) + { + hspi->RxISR = SPI_AbortRx_ISR; + /* Wait HAL_SPI_STATE_ABORT state */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } while (hspi->State != HAL_SPI_STATE_ABORT); + /* Reset Timeout Counter */ + count = resetcount; + } + + /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised + before any call to DMA Abort functions */ + /* DMA Tx Handle is valid */ + if (hspi->hdmatx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) + { + hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback; + } + else + { + hspi->hdmatx->XferAbortCallback = NULL; + } + } + /* DMA Rx Handle is valid */ + if (hspi->hdmarx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)) + { + hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback; + } + else + { + hspi->hdmarx->XferAbortCallback = NULL; + } + } + + /* Disable the SPI DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) + { + /* Abort the SPI DMA Tx Stream/Channel */ + if (hspi->hdmatx != NULL) + { + /* Abort DMA Tx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK) + { + hspi->hdmatx->XferAbortCallback = NULL; + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + else + { + abortcplt = 0U; + } + } + } + /* Disable the SPI DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)) + { + /* Abort the SPI DMA Rx Stream/Channel */ + if (hspi->hdmarx != NULL) + { + /* Abort DMA Rx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK) + { + hspi->hdmarx->XferAbortCallback = NULL; + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + else + { + abortcplt = 0U; + } + } + } + + if (abortcplt == 1U) + { + /* Reset Tx and Rx transfer counters */ + hspi->RxXferCount = 0U; + hspi->TxXferCount = 0U; + + /* Check error during Abort procedure */ + if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT) + { + /* return HAL_Error in case of error during Abort procedure */ + errorcode = HAL_ERROR; + } + else + { + /* Reset errorCode */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + } + + /* Clear the Error flags in the SR register */ + __HAL_SPI_CLEAR_OVRFLAG(hspi); + __HAL_SPI_CLEAR_FREFLAG(hspi); + + /* Restore hspi->State to Ready */ + hspi->State = HAL_SPI_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->AbortCpltCallback(hspi); +#else + HAL_SPI_AbortCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + + return errorcode; +} + +/** + * @brief Pause the DMA Transfer. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi) +{ + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Disable the SPI DMA Tx & Rx requests */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief Resume the DMA Transfer. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi) +{ + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Enable the SPI DMA Tx & Rx requests */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief Stop the DMA Transfer. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) +{ + HAL_StatusTypeDef errorcode = HAL_OK; + /* The Lock is not implemented on this API to allow the user application + to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback(): + when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated + and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback() + */ + + /* Abort the SPI DMA tx Stream/Channel */ + if (hspi->hdmatx != NULL) + { + if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + errorcode = HAL_ERROR; + } + } + /* Abort the SPI DMA rx Stream/Channel */ + if (hspi->hdmarx != NULL) + { + if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + errorcode = HAL_ERROR; + } + } + + /* Disable the SPI DMA Tx & Rx requests */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + hspi->State = HAL_SPI_STATE_READY; + return errorcode; +} + +/** + * @brief Handle SPI interrupt request. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval None + */ +void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) +{ + uint32_t itsource = hspi->Instance->CR2; + uint32_t itflag = hspi->Instance->SR; + + /* SPI in mode Receiver ----------------------------------------------------*/ + if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) && + (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET)) + { + hspi->RxISR(hspi); + return; + } + + /* SPI in mode Transmitter -------------------------------------------------*/ + if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET)) + { + hspi->TxISR(hspi); + return; + } + + /* SPI in Error Treatment --------------------------------------------------*/ + if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET) + || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET)) + { + /* SPI Overrun error interrupt occurred ----------------------------------*/ + if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET) + { + if (hspi->State != HAL_SPI_STATE_BUSY_TX) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR); + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + else + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + return; + } + } + + /* SPI Mode Fault error interrupt occurred -------------------------------*/ + if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF); + __HAL_SPI_CLEAR_MODFFLAG(hspi); + } + + /* SPI Frame error interrupt occurred ------------------------------------*/ + if (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE); + __HAL_SPI_CLEAR_FREFLAG(hspi); + } + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + /* Disable all interrupts */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR); + + hspi->State = HAL_SPI_STATE_READY; + /* Disable the SPI DMA requests if enabled */ + if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN))) + { + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN)); + + /* Abort the SPI DMA Rx channel */ + if (hspi->hdmarx != NULL) + { + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ + hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError; + if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + } + } + /* Abort the SPI DMA Tx channel */ + if (hspi->hdmatx != NULL) + { + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ + hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError; + if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + } + } + } + else + { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + } + return; + } +} + +/** + * @brief Tx Transfer completed callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxCpltCallback should be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_RxCpltCallback should be implemented in the user file + */ +} + +/** + * @brief Tx and Rx Transfer completed callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxRxCpltCallback should be implemented in the user file + */ +} + +/** + * @brief Tx Half Transfer completed callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxHalfCpltCallback should be implemented in the user file + */ +} + +/** + * @brief Rx Half Transfer completed callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file + */ +} + +/** + * @brief Tx and Rx Half Transfer callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file + */ +} + +/** + * @brief SPI error callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_ErrorCallback should be implemented in the user file + */ + /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes + and user can use HAL_SPI_GetError() API to check the latest error occurred + */ +} + +/** + * @brief SPI Abort Complete callback. + * @param hspi SPI handle. + * @retval None + */ +__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_AbortCpltCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief SPI control functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the SPI. + (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral + (+) HAL_SPI_GetError() check in run-time Errors occurring during communication +@endverbatim + * @{ + */ + +/** + * @brief Return the SPI handle state. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval SPI state + */ +HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) +{ + /* Return SPI handle state */ + return hspi->State; +} + +/** + * @brief Return the SPI error code. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval SPI error code in bitmap format + */ +uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) +{ + /* Return SPI ErrorCode */ + return hspi->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup SPI_Private_Functions + * @brief Private functions + * @{ + */ + +/** + * @brief DMA SPI transmit process complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + uint32_t tickstart; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* DMA Normal Mode */ + if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC) + { + /* Disable ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); + + /* Disable Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Clear overrun flag in 2 Lines communication mode because received data is not read */ + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + + hspi->TxXferCount = 0U; + hspi->State = HAL_SPI_STATE_READY; + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + return; + } + } + /* Call user Tx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxCpltCallback(hspi); +#else + HAL_SPI_TxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI receive process complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + uint32_t tickstart; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* DMA Normal Mode */ + if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC) + { + /* Disable ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); + +#if (USE_SPI_CRC != 0U) + /* CRC handling */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Wait until RXNE flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + /* Error on the CRC reception */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + } + /* Read CRC */ + READ_REG(hspi->Instance->DR); + } +#endif /* USE_SPI_CRC */ + + /* Check if we are in Master RX 2 line mode */ + if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + } + else + { + /* Normal case */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + } + + /* Check the end of the transaction */ + if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + } + + hspi->RxXferCount = 0U; + hspi->State = HAL_SPI_STATE_READY; + +#if (USE_SPI_CRC != 0U) + /* Check if CRC error occurred */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } +#endif /* USE_SPI_CRC */ + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + return; + } + } + /* Call user Rx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->RxCpltCallback(hspi); +#else + HAL_SPI_RxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI transmit receive process complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + uint32_t tickstart; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* DMA Normal Mode */ + if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC) + { + /* Disable ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); + +#if (USE_SPI_CRC != 0U) + /* CRC handling */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Wait the CRC data */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + } + /* Read CRC to Flush DR and RXNE flag */ + READ_REG(hspi->Instance->DR); + } +#endif /* USE_SPI_CRC */ + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Disable Rx/Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + + hspi->TxXferCount = 0U; + hspi->RxXferCount = 0U; + hspi->State = HAL_SPI_STATE_READY; + +#if (USE_SPI_CRC != 0U) + /* Check if CRC error occurred */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } +#endif /* USE_SPI_CRC */ + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + return; + } + } + /* Call user TxRx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxRxCpltCallback(hspi); +#else + HAL_SPI_TxRxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI half transmit process complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + + /* Call user Tx half complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxHalfCpltCallback(hspi); +#else + HAL_SPI_TxHalfCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI half receive process complete callback + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + + /* Call user Rx half complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->RxHalfCpltCallback(hspi); +#else + HAL_SPI_RxHalfCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI half transmit receive process complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + + /* Call user TxRx half complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxRxHalfCpltCallback(hspi); +#else + HAL_SPI_TxRxHalfCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI communication error callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAError(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + + /* Stop the disable DMA transfer on SPI side */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + hspi->State = HAL_SPI_STATE_READY; + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI communication abort callback, when initiated by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + * @retval None + */ +static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + hspi->RxXferCount = 0U; + hspi->TxXferCount = 0U; + + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI Tx communication abort callback, when initiated by user + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Rx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + __IO uint32_t count; + + hspi->hdmatx->XferAbortCallback = NULL; + count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + + /* Disable Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + + /* Wait until TXE flag is set */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET); + + /* Check if an Abort process is still ongoing */ + if (hspi->hdmarx != NULL) + { + if (hspi->hdmarx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */ + hspi->RxXferCount = 0U; + hspi->TxXferCount = 0U; + + /* Check no error during Abort procedure */ + if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT) + { + /* Reset errorCode */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + } + + /* Clear the Error flags in the SR register */ + __HAL_SPI_CLEAR_OVRFLAG(hspi); + __HAL_SPI_CLEAR_FREFLAG(hspi); + + /* Restore hspi->State to Ready */ + hspi->State = HAL_SPI_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->AbortCpltCallback(hspi); +#else + HAL_SPI_AbortCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI Rx communication abort callback, when initiated by user + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Tx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + + /* Disable SPI Peripheral */ + __HAL_SPI_DISABLE(hspi); + + hspi->hdmarx->XferAbortCallback = NULL; + + /* Disable Rx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + /* Check Busy flag */ + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + } + + /* Check if an Abort process is still ongoing */ + if (hspi->hdmatx != NULL) + { + if (hspi->hdmatx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */ + hspi->RxXferCount = 0U; + hspi->TxXferCount = 0U; + + /* Check no error during Abort procedure */ + if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT) + { + /* Reset errorCode */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + } + + /* Clear the Error flags in the SR register */ + __HAL_SPI_CLEAR_OVRFLAG(hspi); + __HAL_SPI_CLEAR_FREFLAG(hspi); + + /* Restore hspi->State to Ready */ + hspi->State = HAL_SPI_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->AbortCpltCallback(hspi); +#else + HAL_SPI_AbortCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) +{ + /* Receive data in 8bit mode */ + *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR); + hspi->pRxBuffPtr++; + hspi->RxXferCount--; + + /* Check end of the reception */ + if (hspi->RxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + hspi->RxISR = SPI_2linesRxISR_8BITCRC; + return; + } +#endif /* USE_SPI_CRC */ + + /* Disable RXNE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + if (hspi->TxXferCount == 0U) + { + SPI_CloseRxTx_ISR(hspi); + } + } +} + +#if (USE_SPI_CRC != 0U) +/** + * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) +{ + /* Read 8bit CRC to flush Data Regsiter */ + READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + + /* Disable RXNE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + if (hspi->TxXferCount == 0U) + { + SPI_CloseRxTx_ISR(hspi); + } +} +#endif /* USE_SPI_CRC */ + +/** + * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) +{ + *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + hspi->pTxBuffPtr++; + hspi->TxXferCount--; + + /* Check the end of the transmission */ + if (hspi->TxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Set CRC Next Bit to send CRC */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + /* Disable TXE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); + return; + } +#endif /* USE_SPI_CRC */ + + /* Disable TXE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); + + if (hspi->RxXferCount == 0U) + { + SPI_CloseRxTx_ISR(hspi); + } + } +} + +/** + * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) +{ + /* Receive data in 16 Bit mode */ + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR); + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + + if (hspi->RxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + hspi->RxISR = SPI_2linesRxISR_16BITCRC; + return; + } +#endif /* USE_SPI_CRC */ + + /* Disable RXNE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); + + if (hspi->TxXferCount == 0U) + { + SPI_CloseRxTx_ISR(hspi); + } + } +} + +#if (USE_SPI_CRC != 0U) +/** + * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) +{ + /* Read 16bit CRC to flush Data Regsiter */ + READ_REG(hspi->Instance->DR); + + /* Disable RXNE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); + + SPI_CloseRxTx_ISR(hspi); +} +#endif /* USE_SPI_CRC */ + +/** + * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) +{ + /* Transmit data in 16 Bit mode */ + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + + /* Enable CRC Transmission */ + if (hspi->TxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Set CRC Next Bit to send CRC */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + /* Disable TXE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); + return; + } +#endif /* USE_SPI_CRC */ + + /* Disable TXE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); + + if (hspi->RxXferCount == 0U) + { + SPI_CloseRxTx_ISR(hspi); + } + } +} + +#if (USE_SPI_CRC != 0U) +/** + * @brief Manage the CRC 8-bit receive in Interrupt context. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) +{ + /* Read 8bit CRC to flush Data Register */ + READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + + SPI_CloseRx_ISR(hspi); +} +#endif /* USE_SPI_CRC */ + +/** + * @brief Manage the receive 8-bit in Interrupt context. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi) +{ + *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR); + hspi->pRxBuffPtr++; + hspi->RxXferCount--; + +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + + if (hspi->RxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + hspi->RxISR = SPI_RxISR_8BITCRC; + return; + } +#endif /* USE_SPI_CRC */ + SPI_CloseRx_ISR(hspi); + } +} + +#if (USE_SPI_CRC != 0U) +/** + * @brief Manage the CRC 16-bit receive in Interrupt context. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) +{ + /* Read 16bit CRC to flush Data Register */ + READ_REG(hspi->Instance->DR); + + /* Disable RXNE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + SPI_CloseRx_ISR(hspi); +} +#endif /* USE_SPI_CRC */ + +/** + * @brief Manage the 16-bit receive in Interrupt context. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi) +{ + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR); + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + + if (hspi->RxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + hspi->RxISR = SPI_RxISR_16BITCRC; + return; + } +#endif /* USE_SPI_CRC */ + SPI_CloseRx_ISR(hspi); + } +} + +/** + * @brief Handle the data 8-bit transmit in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) +{ + *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + hspi->pTxBuffPtr++; + hspi->TxXferCount--; + + if (hspi->TxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Enable CRC Transmission */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + SPI_CloseTx_ISR(hspi); + } +} + +/** + * @brief Handle the data 16-bit transmit in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) +{ + /* Transmit data in 16 Bit mode */ + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + + if (hspi->TxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Enable CRC Transmission */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + SPI_CloseTx_ISR(hspi); + } +} + +/** + * @brief Handle SPI Communication Timeout. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param Flag SPI flag to check + * @param State flag state to check + * @param Timeout Timeout duration + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, + uint32_t Timeout, uint32_t Tickstart) +{ + while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Disable the SPI and reset the CRC: the CRC value should be cleared + on both master and slave sides in order to resynchronize the master + and slave for their respective CRC calculation */ + + /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + + if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + } + + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + hspi->State = HAL_SPI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + } + } + + return HAL_OK; +} + +/** + * @brief Handle the check of the RX transaction complete. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param Timeout Timeout duration + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) +{ + if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + } + + /* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */ + if (hspi->Init.Mode == SPI_MODE_MASTER) + { + if (hspi->Init.Direction != SPI_DIRECTION_2LINES_RXONLY) + { + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + } + else + { + /* Wait the RXNE reset */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout, Tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + } + } + else + { + /* Wait the RXNE reset */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout, Tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @brief Handle the check of the RXTX or TX transaction complete. + * @param hspi SPI handle + * @param Timeout Timeout duration + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) +{ + /* Timeout in µs */ + __IO uint32_t count = SPI_BSY_FLAG_WORKAROUND_TIMEOUT * (SystemCoreClock / 24U / 1000000U); + /* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */ + if (hspi->Init.Mode == SPI_MODE_MASTER) + { + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + } + else + { + /* Wait BSY flag during 1 Byte time transfer in case of Full-Duplex and Tx transfer + * If Timeout is reached, the transfer is considered as finish. + * User have to calculate the timeout value to fit with the time of 1 byte transfer. + * This time is directly link with the SPI clock from Master device. + */ + do + { + if (count == 0U) + { + break; + } + count--; + } while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_BSY) != RESET); + } + + return HAL_OK; +} + +/** + * @brief Handle the end of the RXTX transaction. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) +{ + uint32_t tickstart; + __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); + + /* Disable ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); + + /* Wait until TXE flag is set */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + break; + } + count--; + } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET); + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Clear overrun flag in 2 Lines communication mode because received is not read */ + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + +#if (USE_SPI_CRC != 0U) + /* Check if CRC error occurred */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + hspi->State = HAL_SPI_STATE_READY; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + else + { +#endif /* USE_SPI_CRC */ + if (hspi->ErrorCode == HAL_SPI_ERROR_NONE) + { + if (hspi->State == HAL_SPI_STATE_BUSY_RX) + { + hspi->State = HAL_SPI_STATE_READY; + /* Call user Rx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->RxCpltCallback(hspi); +#else + HAL_SPI_RxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + else + { + hspi->State = HAL_SPI_STATE_READY; + /* Call user TxRx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxRxCpltCallback(hspi); +#else + HAL_SPI_TxRxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + } + else + { + hspi->State = HAL_SPI_STATE_READY; + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } +#if (USE_SPI_CRC != 0U) + } +#endif /* USE_SPI_CRC */ +} + +/** + * @brief Handle the end of the RX transaction. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi) +{ + /* Disable RXNE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + /* Check the end of the transaction */ + if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Clear overrun flag in 2 Lines communication mode because received is not read */ + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + hspi->State = HAL_SPI_STATE_READY; + +#if (USE_SPI_CRC != 0U) + /* Check if CRC error occurred */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + else + { +#endif /* USE_SPI_CRC */ + if (hspi->ErrorCode == HAL_SPI_ERROR_NONE) + { + /* Call user Rx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->RxCpltCallback(hspi); +#else + HAL_SPI_RxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + else + { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } +#if (USE_SPI_CRC != 0U) + } +#endif /* USE_SPI_CRC */ +} + +/** + * @brief Handle the end of the TX transaction. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi) +{ + uint32_t tickstart; + __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* Wait until TXE flag is set */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + break; + } + count--; + } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET); + + /* Disable TXE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Clear overrun flag in 2 Lines communication mode because received is not read */ + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + + hspi->State = HAL_SPI_STATE_READY; + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + else + { + /* Call user Rx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxCpltCallback(hspi); +#else + HAL_SPI_TxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Handle abort a Rx transaction. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi) +{ + __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + + /* Wait until TXE flag is set */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET); + + /* Disable SPI Peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */ + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE)); + + /* Read CRC to flush Data Register */ + READ_REG(hspi->Instance->DR); + + hspi->State = HAL_SPI_STATE_ABORT; +} + +/** + * @brief Handle abort a Tx or Rx/Tx transaction. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) +{ + /* Disable TXEIE interrupt */ + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE)); + + /* Disable SPI Peripheral */ + __HAL_SPI_DISABLE(hspi); + + hspi->State = HAL_SPI_STATE_ABORT; +} + +/** + * @} + */ + +#endif /* HAL_SPI_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c new file mode 100644 index 0000000..eb98d57 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c @@ -0,0 +1,6654 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_tim.c + * @author MCD Application Team + * @brief TIM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Timer (TIM) peripheral: + * + TIM Time Base Initialization + * + TIM Time Base Start + * + TIM Time Base Start Interruption + * + TIM Time Base Start DMA + * + TIM Output Compare/PWM Initialization + * + TIM Output Compare/PWM Channel Configuration + * + TIM Output Compare/PWM Start + * + TIM Output Compare/PWM Start Interruption + * + TIM Output Compare/PWM Start DMA + * + TIM Input Capture Initialization + * + TIM Input Capture Channel Configuration + * + TIM Input Capture Start + * + TIM Input Capture Start Interruption + * + TIM Input Capture Start DMA + * + TIM One Pulse Initialization + * + TIM One Pulse Channel Configuration + * + TIM One Pulse Start + * + TIM Encoder Interface Initialization + * + TIM Encoder Interface Start + * + TIM Encoder Interface Start Interruption + * + TIM Encoder Interface Start DMA + * + Commutation Event configuration with Interruption and DMA + * + TIM OCRef clear configuration + * + TIM External Clock configuration + @verbatim + ============================================================================== + ##### TIMER Generic features ##### + ============================================================================== + [..] The Timer features include: + (#) 16-bit up, down, up/down auto-reload counter. + (#) 16-bit programmable prescaler allowing dividing (also on the fly) the + counter clock frequency either by any factor between 1 and 65536. + (#) Up to 4 independent channels for: + (++) Input Capture + (++) Output Compare + (++) PWM generation (Edge and Center-aligned Mode) + (++) One-pulse mode output + (#) Synchronization circuit to control the timer with external signals and to interconnect + several timers together. + (#) Supports incremental encoder for positioning purposes + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the TIM low level resources by implementing the following functions + depending on the selected feature: + (++) Time Base : HAL_TIM_Base_MspInit() + (++) Input Capture : HAL_TIM_IC_MspInit() + (++) Output Compare : HAL_TIM_OC_MspInit() + (++) PWM generation : HAL_TIM_PWM_MspInit() + (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit() + (++) Encoder mode output : HAL_TIM_Encoder_MspInit() + + (#) Initialize the TIM low level resources : + (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); + (##) TIM pins configuration + (+++) Enable the clock for the TIM GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + + (#) The external Clock can be configured, if needed (the default clock is the + internal clock from the APBx), using the following function: + HAL_TIM_ConfigClockSource, the clock configuration should be done before + any start function. + + (#) Configure the TIM in the desired functioning mode using one of the + Initialization function of this driver: + (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base + (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an + Output Compare signal. + (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a + PWM signal. + (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an + external signal. + (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer + in One Pulse Mode. + (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. + + (#) Activate the TIM peripheral using one of the start functions depending from the feature used: + (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT() + (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT() + (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT() + (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT() + (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT() + (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(). + + (#) The DMA Burst is managed with the two following functions: + HAL_TIM_DMABurst_WriteStart() + HAL_TIM_DMABurst_ReadStart() + + *** Callback registration *** + ============================================= + + [..] + The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function @ref HAL_TIM_RegisterCallback() to register a callback. + @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle, + the Callback ID and a pointer to the user callback function. + + [..] + Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default + weak function. + @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + + [..] + These functions allow to register/unregister following callbacks: + (+) Base_MspInitCallback : TIM Base Msp Init Callback. + (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback. + (+) IC_MspInitCallback : TIM IC Msp Init Callback. + (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback. + (+) OC_MspInitCallback : TIM OC Msp Init Callback. + (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback. + (+) PWM_MspInitCallback : TIM PWM Msp Init Callback. + (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback. + (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback. + (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback. + (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback. + (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback. + (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback. + (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback. + (+) PeriodElapsedCallback : TIM Period Elapsed Callback. + (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback. + (+) TriggerCallback : TIM Trigger Callback. + (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback. + (+) IC_CaptureCallback : TIM Input Capture Callback. + (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback. + (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback. + (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback. + (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback. + (+) ErrorCallback : TIM Error Callback. + (+) CommutationCallback : TIM Commutation Callback. + (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback. + (+) BreakCallback : TIM Break Callback. + + [..] +By default, after the Init and when the state is HAL_TIM_STATE_RESET +all interrupt callbacks are set to the corresponding weak functions: + examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback(). + + [..] + Exception done for MspInit and MspDeInit functions that are reset to the legacy weak + functionalities in the Init / DeInit only when these callbacks are null + (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit + keep and use the user MspInit / MspDeInit callbacks(registered beforehand) + + [..] + Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only. + Exception done MspInit / MspDeInit that can be registered / unregistered + in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state, + thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function. + + [..] + When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup TIM TIM + * @brief TIM HAL module driver + * @{ + */ + +#ifdef HAL_TIM_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup TIM_Private_Functions + * @{ + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource); +static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, + TIM_SlaveConfigTypeDef *sSlaveConfig); +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup TIM_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions + * @brief Time Base functions + * +@verbatim + ============================================================================== + ##### Time Base functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM base. + (+) De-initialize the TIM base. + (+) Start the Time Base. + (+) Stop the Time Base. + (+) Start the Time Base and enable interrupt. + (+) Stop the Time Base and disable interrupt. + (+) Start the Time Base and enable DMA transfer. + (+) Stop the Time Base and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Time base Unit according to the specified + * parameters in the TIM_HandleTypeDef and initialize the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->Base_MspInitCallback == NULL) + { + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Base_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Set the Time Base configuration */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM Base peripheral + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->Base_MspDeInitCallback == NULL) + { + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; + } + /* DeInit the low level hardware */ + htim->Base_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Base MSP. + * @param htim TIM Base handle + * @retval None + */ +__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Base_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Base MSP. + * @param htim TIM Base handle + * @retval None + */ +__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Base_MspDeInit could be implemented in the user file + */ +} + + +/** + * @brief Starts the TIM Base generation. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Change the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Base generation in interrupt mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Enable the TIM Update interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation in interrupt mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + /* Disable the TIM Update interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Base generation in DMA mode. + * @param htim TIM Base handle + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + + if (htim->State == HAL_TIM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->State == HAL_TIM_STATE_READY) + { + if ((pData == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK) + { + return HAL_ERROR; + } + + /* Enable the TIM Update DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation in DMA mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); + + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions + * @brief TIM Output Compare functions + * +@verbatim + ============================================================================== + ##### TIM Output Compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Output Compare. + (+) De-initialize the TIM Output Compare. + (+) Start the TIM Output Compare. + (+) Stop the TIM Output Compare. + (+) Start the TIM Output Compare and enable interrupt. + (+) Stop the TIM Output Compare and disable interrupt. + (+) Start the TIM Output Compare and enable DMA transfer. + (+) Stop the TIM Output Compare and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Output Compare according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() + * @param htim TIM Output Compare handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->OC_MspInitCallback == NULL) + { + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->OC_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OC_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the Output Compare */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM Output Compare handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->OC_MspDeInitCallback == NULL) + { + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; + } + /* DeInit the low level hardware */ + htim->OC_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OC_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Output Compare MSP. + * @param htim TIM Output Compare handle + * @retval None + */ +__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Output Compare MSP. + * @param htim TIM Output Compare handle + * @retval None + */ +__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Output Compare signal generation. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in interrupt mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + break; + } + + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation in interrupt mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + break; + } + + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in DMA mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + if (htim->State == HAL_TIM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->State == HAL_TIM_STATE_READY) + { + if ((pData == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + { + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + { + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + break; + } + + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation in DMA mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + break; + } + + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions + * @brief TIM PWM functions + * +@verbatim + ============================================================================== + ##### TIM PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM PWM. + (+) De-initialize the TIM PWM. + (+) Start the TIM PWM. + (+) Stop the TIM PWM. + (+) Start the TIM PWM and enable interrupt. + (+) Stop the TIM PWM and disable interrupt. + (+) Start the TIM PWM and enable DMA transfer. + (+) Stop the TIM PWM and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM PWM Time Base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() + * @param htim TIM PWM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->PWM_MspInitCallback == NULL) + { + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->PWM_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the PWM */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM PWM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->PWM_MspDeInitCallback == NULL) + { + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; + } + /* DeInit the low level hardware */ + htim->PWM_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM PWM MSP. + * @param htim TIM PWM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM PWM MSP. + * @param htim TIM PWM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the PWM signal generation. + * @param htim TIM handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the PWM signal generation in interrupt mode. + * @param htim TIM PWM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + break; + } + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation in interrupt mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + break; + } + + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM PWM signal generation in DMA mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + if (htim->State == HAL_TIM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->State == HAL_TIM_STATE_READY) + { + if ((pData == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + { + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Output Capture/Compare 3 request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + break; + } + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM PWM signal generation in DMA mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + break; + } + + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions + * @brief TIM Input Capture functions + * +@verbatim + ============================================================================== + ##### TIM Input Capture functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Input Capture. + (+) De-initialize the TIM Input Capture. + (+) Start the TIM Input Capture. + (+) Stop the TIM Input Capture. + (+) Start the TIM Input Capture and enable interrupt. + (+) Stop the TIM Input Capture and disable interrupt. + (+) Start the TIM Input Capture and enable DMA transfer. + (+) Stop the TIM Input Capture and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Input Capture Time base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init() + * @param htim TIM Input Capture handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->IC_MspInitCallback == NULL) + { + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->IC_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_IC_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the input capture */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM Input Capture handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->IC_MspDeInitCallback == NULL) + { + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; + } + /* DeInit the low level hardware */ + htim->IC_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_IC_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Input Capture MSP. + * @param htim TIM Input Capture handle + * @retval None + */ +__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Input Capture MSP. + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Input Capture measurement. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Input Capture measurement. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Input Capture measurement in interrupt mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + break; + } + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Input Capture measurement in interrupt mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + break; + } + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Input Capture measurement in DMA mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + if (htim->State == HAL_TIM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->State == HAL_TIM_STATE_READY) + { + if ((pData == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + break; + } + + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Input Capture measurement in DMA mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + break; + } + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions + * @brief TIM One Pulse functions + * +@verbatim + ============================================================================== + ##### TIM One Pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM One Pulse. + (+) De-initialize the TIM One Pulse. + (+) Start the TIM One Pulse. + (+) Stop the TIM One Pulse. + (+) Start the TIM One Pulse and enable interrupt. + (+) Stop the TIM One Pulse and disable interrupt. + (+) Start the TIM One Pulse and enable DMA transfer. + (+) Stop the TIM One Pulse and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM One Pulse Time Base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init() + * @param htim TIM One Pulse handle + * @param OnePulseMode Select the One pulse mode. + * This parameter can be one of the following values: + * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. + * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_OPM_MODE(OnePulseMode)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->OnePulse_MspInitCallback == NULL) + { + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->OnePulse_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OnePulse_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Configure the Time base in the One Pulse Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Reset the OPM Bit */ + htim->Instance->CR1 &= ~TIM_CR1_OPM; + + /* Configure the OPM Mode */ + htim->Instance->CR1 |= OnePulseMode; + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM One Pulse + * @param htim TIM One Pulse handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->OnePulse_MspDeInitCallback == NULL) + { + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; + } + /* DeInit the low level hardware */ + htim->OnePulse_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_OnePulse_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM One Pulse MSP. + * @param htim TIM One Pulse handle + * @retval None + */ +__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OnePulse_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM One Pulse MSP. + * @param htim TIM One Pulse handle + * @retval None + */ +__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM One Pulse signal generation. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Enable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + + No need to enable the counter, it's enabled automatically by hardware + (the counter starts in response to a stimulus and generate a pulse */ + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be disable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Disable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM One Pulse signal generation in interrupt mode. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Enable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + + No need to enable the counter, it's enabled automatically by hardware + (the counter starts in response to a stimulus and generate a pulse */ + + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation in interrupt mode. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + + /* Disable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions + * @brief TIM Encoder functions + * +@verbatim + ============================================================================== + ##### TIM Encoder functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Encoder. + (+) De-initialize the TIM Encoder. + (+) Start the TIM Encoder. + (+) Stop the TIM Encoder. + (+) Start the TIM Encoder and enable interrupt. + (+) Stop the TIM Encoder and disable interrupt. + (+) Start the TIM Encoder and enable DMA transfer. + (+) Stop the TIM Encoder and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Encoder Interface and initialize the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init() + * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together + * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource + * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa + * @param htim TIM Encoder Interface handle + * @param sConfig TIM Encoder Interface configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig) +{ + uint32_t tmpsmcr; + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); + assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); + assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); + assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->Encoder_MspInitCallback == NULL) + { + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Encoder_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_Encoder_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Reset the SMS and ECE bits */ + htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); + + /* Configure the Time base in the Encoder Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = htim->Instance->CCMR1; + + /* Get the TIMx CCER register value */ + tmpccer = htim->Instance->CCER; + + /* Set the encoder Mode */ + tmpsmcr |= sConfig->EncoderMode; + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); + tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); + + /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ + tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); + tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); + tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); + tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); + + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); + tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); + tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + /* Write to TIMx CCMR1 */ + htim->Instance->CCMR1 = tmpccmr1; + + /* Write to TIMx CCER */ + htim->Instance->CCER = tmpccer; + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + + +/** + * @brief DeInitializes the TIM Encoder interface + * @param htim TIM Encoder Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->Encoder_MspDeInitCallback == NULL) + { + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; + } + /* DeInit the low level hardware */ + htim->Encoder_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_Encoder_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Encoder Interface MSP. + * @param htim TIM Encoder Interface handle + * @retval None + */ +__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Encoder_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Encoder Interface MSP. + * @param htim TIM Encoder Interface handle + * @retval None + */ +__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Encoder_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Encoder Interface. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Enable the encoder interface channels */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + } + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; + } + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Encoder Interface in interrupt mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Enable the encoder interface channels */ + /* Enable the capture compare Interrupts 1 and/or 2 */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + } + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface in interrupt mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + if (Channel == TIM_CHANNEL_1) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 1 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + } + else if (Channel == TIM_CHANNEL_2) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 2 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + else + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 1 and 2 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Encoder Interface in DMA mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @param pData1 The destination Buffer address for IC1. + * @param pData2 The destination Buffer address for IC2. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, + uint32_t *pData2, uint16_t Length) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + if (htim->State == HAL_TIM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->State == HAL_TIM_STATE_READY) + { + if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + + case TIM_CHANNEL_ALL: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) + { + return HAL_ERROR; + } + + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + default: + break; + } + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface in DMA mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + if (Channel == TIM_CHANNEL_1) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 1 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + } + else if (Channel == TIM_CHANNEL_2) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 2 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + } + else + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 1 and 2 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ +/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management + * @brief TIM IRQ handler management + * +@verbatim + ============================================================================== + ##### IRQ handler management ##### + ============================================================================== + [..] + This section provides Timer IRQ handler function. + +@endverbatim + * @{ + */ +/** + * @brief This function handles TIM interrupts requests. + * @param htim TIM handle + * @retval None + */ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) +{ + /* Capture compare 1 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) + { + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + } + /* Capture compare 2 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 3 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 4 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* TIM Update event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else + HAL_TIM_PeriodElapsedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Break input event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->BreakCallback(htim); +#else + HAL_TIMEx_BreakCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Trigger detection event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else + HAL_TIM_TriggerCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM commutation event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationCallback(htim); +#else + HAL_TIMEx_CommutCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions + * @brief TIM Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. + (+) Configure External Clock source. + (+) Configure Complementary channels, break features and dead time. + (+) Configure Master and the Slave synchronization. + (+) Configure the DMA Burst Mode. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the TIM Output Compare Channels according to the specified + * parameters in the TIM_OC_InitTypeDef. + * @param htim TIM Output Compare handle + * @param sConfig TIM Output Compare configuration structure + * @param Channel TIM Channels to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, + TIM_OC_InitTypeDef *sConfig, + uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CHANNELS(Channel)); + assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 1 in Output Compare */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 2 in Output Compare */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 3 in Output Compare */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 4 in Output Compare */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + break; + } + + default: + break; + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Input Capture Channels according to the specified + * parameters in the TIM_IC_InitTypeDef. + * @param htim TIM IC handle + * @param sConfig TIM Input Capture configuration structure + * @param Channel TIM Channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); + assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + if (Channel == TIM_CHANNEL_1) + { + /* TI1 Configuration */ + TIM_TI1_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + + /* Set the IC1PSC value */ + htim->Instance->CCMR1 |= sConfig->ICPrescaler; + } + else if (Channel == TIM_CHANNEL_2) + { + /* TI2 Configuration */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_TI2_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC2PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + + /* Set the IC2PSC value */ + htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); + } + else if (Channel == TIM_CHANNEL_3) + { + /* TI3 Configuration */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + TIM_TI3_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC3PSC Bits */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; + + /* Set the IC3PSC value */ + htim->Instance->CCMR2 |= sConfig->ICPrescaler; + } + else + { + /* TI4 Configuration */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + TIM_TI4_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC4PSC Bits */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; + + /* Set the IC4PSC value */ + htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM PWM channels according to the specified + * parameters in the TIM_OC_InitTypeDef. + * @param htim TIM PWM handle + * @param sConfig TIM PWM configuration structure + * @param Channel TIM Channels to be configured + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, + TIM_OC_InitTypeDef *sConfig, + uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CHANNELS(Channel)); + assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Configure the Channel 1 in PWM mode */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel1 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; + htim->Instance->CCMR1 |= sConfig->OCFastMode; + break; + } + + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Configure the Channel 2 in PWM mode */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel2 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; + htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Configure the Channel 3 in PWM mode */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel3 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; + htim->Instance->CCMR2 |= sConfig->OCFastMode; + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Configure the Channel 4 in PWM mode */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel4 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; + htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; + break; + } + + default: + break; + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM One Pulse Channels according to the specified + * parameters in the TIM_OnePulse_InitTypeDef. + * @param htim TIM One Pulse handle + * @param sConfig TIM One Pulse configuration structure + * @param OutputChannel TIM output channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param InputChannel TIM input Channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @note To output a waveform with a minimum delay user can enable the fast + * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx + * output is forced in response to the edge detection on TIx input, + * without taking in account the comparison. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, + uint32_t OutputChannel, uint32_t InputChannel) +{ + TIM_OC_InitTypeDef temp1; + + /* Check the parameters */ + assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); + assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); + + if (OutputChannel != InputChannel) + { + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Extract the Output compare configuration from sConfig structure */ + temp1.OCMode = sConfig->OCMode; + temp1.Pulse = sConfig->Pulse; + temp1.OCPolarity = sConfig->OCPolarity; + temp1.OCNPolarity = sConfig->OCNPolarity; + temp1.OCIdleState = sConfig->OCIdleState; + temp1.OCNIdleState = sConfig->OCNIdleState; + + switch (OutputChannel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + TIM_OC1_SetConfig(htim->Instance, &temp1); + break; + } + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_OC2_SetConfig(htim->Instance, &temp1); + break; + } + default: + break; + } + + switch (InputChannel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI1FP1; + + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; + } + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); + + /* Reset the IC2PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI2FP2; + + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; + } + + default: + break; + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @note This function should be used only when BurstLength is equal to DMA data transfer length. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, + uint32_t *BurstBuffer, uint32_t BurstLength) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + + if (htim->State == HAL_TIM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->State == HAL_TIM_STATE_READY) + { + if ((BurstBuffer == NULL) && (BurstLength > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + case TIM_DMA_COM: + { + /* Set the DMA commutation callbacks */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + case TIM_DMA_TRIGGER: + { + /* Set the DMA trigger callbacks */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; + htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + default: + break; + } + /* configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength); + + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM DMA Burst mode + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) +{ + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + + /* Abort the DMA transfer (at least disable the DMA stream) */ + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + break; + } + case TIM_DMA_CC1: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + case TIM_DMA_CC2: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + case TIM_DMA_CC3: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + case TIM_DMA_CC4: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + case TIM_DMA_COM: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + break; + } + case TIM_DMA_TRIGGER: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + break; + } + default: + break; + } + + if (HAL_OK == status) + { + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + } + + /* Return function status */ + return status; +} + +/** + * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @note This function should be used only when BurstLength is equal to DMA data transfer length. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + + if (htim->State == HAL_TIM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->State == HAL_TIM_STATE_READY) + { + if ((BurstBuffer == NULL) && (BurstLength > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC2: + { + /* Set the DMA capture/compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC3: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC4: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + case TIM_DMA_COM: + { + /* Set the DMA commutation callbacks */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + case TIM_DMA_TRIGGER: + { + /* Set the DMA trigger callbacks */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; + htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + default: + break; + } + + /* configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength); + + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stop the DMA burst reading + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) +{ + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + + /* Abort the DMA transfer (at least disable the DMA stream) */ + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + break; + } + case TIM_DMA_CC1: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + case TIM_DMA_CC2: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + case TIM_DMA_CC3: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + case TIM_DMA_CC4: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + case TIM_DMA_COM: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + break; + } + case TIM_DMA_TRIGGER: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + break; + } + default: + break; + } + + if (HAL_OK == status) + { + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + } + + /* Return function status */ + return status; +} + +/** + * @brief Generate a software event + * @param htim TIM handle + * @param EventSource specifies the event source. + * This parameter can be one of the following values: + * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source + * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source + * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source + * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source + * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source + * @arg TIM_EVENTSOURCE_COM: Timer COM event source + * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source + * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source + * @note Basic timers can only generate an update event. + * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances. + * @note TIM_EVENTSOURCE_BREAK are relevant only for timer instances + * supporting a break input. + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_EVENT_SOURCE(EventSource)); + + /* Process Locked */ + __HAL_LOCK(htim); + + /* Change the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Set the event sources */ + htim->Instance->EGR = EventSource; + + /* Change the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Configures the OCRef clear feature + * @param htim TIM handle + * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that + * contains the OCREF clear feature and parameters for the TIM peripheral. + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, + TIM_ClearInputConfigTypeDef *sClearInputConfig, + uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + switch (sClearInputConfig->ClearInputSource) + { + case TIM_CLEARINPUTSOURCE_NONE: + { + /* Clear the OCREF clear selection bit and the the ETR Bits */ + CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); + break; + } + + case TIM_CLEARINPUTSOURCE_ETR: + { + /* Check the parameters */ + assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); + assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); + assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); + + /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */ + if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + TIM_ETR_SetConfig(htim->Instance, + sClearInputConfig->ClearInputPrescaler, + sClearInputConfig->ClearInputPolarity, + sClearInputConfig->ClearInputFilter); + break; + } + + default: + break; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 1 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + } + else + { + /* Disable the OCREF clear feature for Channel 1 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + } + break; + } + case TIM_CHANNEL_2: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 2 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + } + else + { + /* Disable the OCREF clear feature for Channel 2 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + } + break; + } + case TIM_CHANNEL_3: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 3 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + } + else + { + /* Disable the OCREF clear feature for Channel 3 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + } + break; + } + case TIM_CHANNEL_4: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 4 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + } + else + { + /* Disable the OCREF clear feature for Channel 4 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + } + break; + } + default: + break; + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the clock source to be used + * @param htim TIM handle + * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that + * contains the clock source information for the TIM peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig) +{ + uint32_t tmpsmcr; + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); + + /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ + tmpsmcr = htim->Instance->SMCR; + tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + htim->Instance->SMCR = tmpsmcr; + + switch (sClockSourceConfig->ClockSource) + { + case TIM_CLOCKSOURCE_INTERNAL: + { + assert_param(IS_TIM_INSTANCE(htim->Instance)); + break; + } + + case TIM_CLOCKSOURCE_ETRMODE1: + { + /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); + + /* Check ETR input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + + /* Select the External clock mode1 and the ETRF trigger */ + tmpsmcr = htim->Instance->SMCR; + tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + break; + } + + case TIM_CLOCKSOURCE_ETRMODE2: + { + /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance)); + + /* Check ETR input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + /* Enable the External clock mode2 */ + htim->Instance->SMCR |= TIM_SMCR_ECE; + break; + } + + case TIM_CLOCKSOURCE_TI1: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); + break; + } + + case TIM_CLOCKSOURCE_TI2: + { + /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI2 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI2_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); + break; + } + + case TIM_CLOCKSOURCE_TI1ED: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); + break; + } + + case TIM_CLOCKSOURCE_ITR0: + case TIM_CLOCKSOURCE_ITR1: + case TIM_CLOCKSOURCE_ITR2: + case TIM_CLOCKSOURCE_ITR3: + { + /* Check whether or not the timer instance supports internal trigger input */ + assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); + + TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); + break; + } + + default: + break; + } + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Selects the signal connected to the TI1 input: direct from CH1_input + * or a XOR combination between CH1_input, CH2_input & CH3_input + * @param htim TIM handle. + * @param TI1_Selection Indicate whether or not channel 1 is connected to the + * output of a XOR gate. + * This parameter can be one of the following values: + * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input + * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 + * pins are connected to the TI1 input (XOR combination) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) +{ + uint32_t tmpcr2; + + /* Check the parameters */ + assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TI1SELECTION(TI1_Selection)); + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + + /* Reset the TI1 selection */ + tmpcr2 &= ~TIM_CR2_TI1S; + + /* Set the TI1 selection */ + tmpcr2 |= TI1_Selection; + + /* Write to TIMxCR2 */ + htim->Instance->CR2 = tmpcr2; + + return HAL_OK; +} + +/** + * @brief Configures the TIM in Slave mode + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that + * contains the selected trigger (internal trigger input, filtered + * timer input or external trigger input) and the Slave mode + * (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); + assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + /* Disable Trigger Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); + + /* Disable Trigger DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIM in Slave mode in interrupt mode + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that + * contains the selected trigger (internal trigger input, filtered + * timer input or external trigger input) and the Slave mode + * (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, + TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); + assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + /* Enable Trigger Interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); + + /* Disable Trigger DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Read the captured value from Capture Compare unit + * @param htim TIM handle. + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval Captured value + */ +uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpreg = 0U; + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Return the capture 1 value */ + tmpreg = htim->Instance->CCR1; + + break; + } + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Return the capture 2 value */ + tmpreg = htim->Instance->CCR2; + + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Return the capture 3 value */ + tmpreg = htim->Instance->CCR3; + + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Return the capture 4 value */ + tmpreg = htim->Instance->CCR4; + + break; + } + + default: + break; + } + + return tmpreg; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions + * @brief TIM Callbacks functions + * +@verbatim + ============================================================================== + ##### TIM Callbacks functions ##### + ============================================================================== + [..] + This section provides TIM callback functions: + (+) TIM Period elapsed callback + (+) TIM Output Compare callback + (+) TIM Input capture callback + (+) TIM Trigger callback + (+) TIM Error callback + +@endverbatim + * @{ + */ + +/** + * @brief Period elapsed callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PeriodElapsedCallback could be implemented in the user file + */ +} + +/** + * @brief Period elapsed half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Output Compare callback in non-blocking mode + * @param htim TIM OC handle + * @retval None + */ +__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file + */ +} + +/** + * @brief Input Capture callback in non-blocking mode + * @param htim TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_CaptureCallback could be implemented in the user file + */ +} + +/** + * @brief Input Capture half complete callback in non-blocking mode + * @param htim TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief PWM Pulse finished callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file + */ +} + +/** + * @brief PWM Pulse finished half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Trigger detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_TriggerCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Trigger detection half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Timer error callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_ErrorCallback could be implemented in the user file + */ +} + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User TIM callback to be used instead of the weak predefined callback + * @param htim tim handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID + * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID + * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID + * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID + * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID + * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID + * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID + * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID + * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID + * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID + * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID + * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID + * @param pCallback pointer to the callback function + * @retval status + */ +HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, + pTIM_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(htim); + + if (htim->State == HAL_TIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = pCallback; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_CB_ID : + htim->PeriodElapsedCallback = pCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : + htim->PeriodElapsedHalfCpltCallback = pCallback; + break; + + case HAL_TIM_TRIGGER_CB_ID : + htim->TriggerCallback = pCallback; + break; + + case HAL_TIM_TRIGGER_HALF_CB_ID : + htim->TriggerHalfCpltCallback = pCallback; + break; + + case HAL_TIM_IC_CAPTURE_CB_ID : + htim->IC_CaptureCallback = pCallback; + break; + + case HAL_TIM_IC_CAPTURE_HALF_CB_ID : + htim->IC_CaptureHalfCpltCallback = pCallback; + break; + + case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : + htim->OC_DelayElapsedCallback = pCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : + htim->PWM_PulseFinishedCallback = pCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : + htim->PWM_PulseFinishedHalfCpltCallback = pCallback; + break; + + case HAL_TIM_ERROR_CB_ID : + htim->ErrorCallback = pCallback; + break; + + case HAL_TIM_COMMUTATION_CB_ID : + htim->CommutationCallback = pCallback; + break; + + case HAL_TIM_COMMUTATION_HALF_CB_ID : + htim->CommutationHalfCpltCallback = pCallback; + break; + + case HAL_TIM_BREAK_CB_ID : + htim->BreakCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (htim->State == HAL_TIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = pCallback; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Unregister a TIM callback + * TIM callback is redirected to the weak predefined callback + * @param htim tim handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID + * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID + * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID + * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID + * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID + * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID + * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID + * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID + * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID + * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID + * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID + * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(htim); + + if (htim->State == HAL_TIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */ + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */ + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */ + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */ + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */ + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */ + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */ + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */ + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */ + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */ + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */ + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */ + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */ + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */ + break; + + case HAL_TIM_PERIOD_ELAPSED_CB_ID : + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak Period Elapsed Callback */ + break; + + case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak Period Elapsed half complete Callback */ + break; + + case HAL_TIM_TRIGGER_CB_ID : + htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak Trigger Callback */ + break; + + case HAL_TIM_TRIGGER_HALF_CB_ID : + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak Trigger half complete Callback */ + break; + + case HAL_TIM_IC_CAPTURE_CB_ID : + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC Capture Callback */ + break; + + case HAL_TIM_IC_CAPTURE_HALF_CB_ID : + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC Capture half complete Callback */ + break; + + case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC Delay Elapsed Callback */ + break; + + case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM Pulse Finished Callback */ + break; + + case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */ + break; + + case HAL_TIM_ERROR_CB_ID : + htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak Error Callback */ + break; + + case HAL_TIM_COMMUTATION_CB_ID : + htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak Commutation Callback */ + break; + + case HAL_TIM_COMMUTATION_HALF_CB_ID : + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak Commutation half complete Callback */ + break; + + case HAL_TIM_BREAK_CB_ID : + htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak Break Callback */ + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (htim->State == HAL_TIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */ + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */ + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */ + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */ + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */ + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */ + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */ + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */ + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */ + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */ + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */ + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */ + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */ + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */ + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return status; +} +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions + * @brief TIM Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the TIM Base handle state. + * @param htim TIM Base handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM OC handle state. + * @param htim TIM Output Compare handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM PWM handle state. + * @param htim TIM handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Input Capture handle state. + * @param htim TIM IC handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM One Pulse Mode handle state. + * @param htim TIM OPM handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Encoder Mode handle state. + * @param htim TIM Encoder Interface handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_Functions TIM Private Functions + * @{ + */ + +/** + * @brief TIM DMA error callback + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMAError(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->ErrorCallback(htim); +#else + HAL_TIM_ErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Delay Pulse complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + htim->State = HAL_TIM_STATE_READY; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Delay Pulse half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + htim->State = HAL_TIM_STATE_READY; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedHalfCpltCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Capture complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + htim->State = HAL_TIM_STATE_READY; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Capture half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + htim->State = HAL_TIM_STATE_READY; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureHalfCpltCallback(htim); +#else + HAL_TIM_IC_CaptureHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Period Elapse complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else + HAL_TIM_PeriodElapsedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Period Elapse half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedHalfCpltCallback(htim); +#else + HAL_TIM_PeriodElapsedHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Trigger callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else + HAL_TIM_TriggerCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Trigger half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerHalfCpltCallback(htim); +#else + HAL_TIM_TriggerHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief Time Base configuration + * @param TIMx TIM peripheral + * @param Structure TIM Base configuration structure + * @retval None + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) +{ + uint32_t tmpcr1; + tmpcr1 = TIMx->CR1; + + /* Set TIM Time Base Unit parameters ---------------------------------------*/ + if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) + { + /* Select the Counter Mode */ + tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); + tmpcr1 |= Structure->CounterMode; + } + + if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) + { + /* Set the clock division */ + tmpcr1 &= ~TIM_CR1_CKD; + tmpcr1 |= (uint32_t)Structure->ClockDivision; + } + + /* Set the auto-reload preload */ + MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); + + TIMx->CR1 = tmpcr1; + + /* Set the Autoreload value */ + TIMx->ARR = (uint32_t)Structure->Period ; + + /* Set the Prescaler value */ + TIMx->PSC = Structure->Prescaler; + + if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) + { + /* Set the Repetition Counter value */ + TIMx->RCR = Structure->RepetitionCounter; + } + + /* Generate an update event to reload the Prescaler + and the repetition counter (only for advanced timer) value immediately */ + TIMx->EGR = TIM_EGR_UG; +} + +/** + * @brief Timer Output Compare 1 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The ouput configuration structure + * @retval None + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= ~TIM_CCER_CC1E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~TIM_CCMR1_OC1M; + tmpccmrx &= ~TIM_CCMR1_CC1S; + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC1P; + /* Set the Output Compare Polarity */ + tmpccer |= OC_Config->OCPolarity; + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) + { + /* Check parameters */ + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC1NP; + /* Set the Output N Polarity */ + tmpccer |= OC_Config->OCNPolarity; + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC1NE; + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS1; + tmpcr2 &= ~TIM_CR2_OIS1N; + /* Set the Output Idle state */ + tmpcr2 |= OC_Config->OCIdleState; + /* Set the Output N Idle state */ + tmpcr2 |= OC_Config->OCNIdleState; + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 2 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The ouput configuration structure + * @retval None + */ +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR1_OC2M; + tmpccmrx &= ~TIM_CCMR1_CC2S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC2P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 4U); + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC2NP; + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 4U); + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC2NE; + + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS2; + tmpcr2 &= ~TIM_CR2_OIS2N; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 2U); + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 2U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 3 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The ouput configuration structure + * @retval None + */ +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 3: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC3E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC3M; + tmpccmrx &= ~TIM_CCMR2_CC3S; + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC3P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 8U); + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC3NP; + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 8U); + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC3NE; + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS3; + tmpcr2 &= ~TIM_CR2_OIS3N; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 4U); + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 4U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 4 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The ouput configuration structure + * @retval None + */ +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= ~TIM_CCER_CC4E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC4M; + tmpccmrx &= ~TIM_CCMR2_CC4S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC4P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 12U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS4; + + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 6U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Slave Timer configuration function + * @param htim TIM handle + * @param sSlaveConfig Slave timer configuration + * @retval None + */ +static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, + TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + uint32_t tmpsmcr; + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Reset the Trigger Selection Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + /* Set the Input Trigger source */ + tmpsmcr |= sSlaveConfig->InputTrigger; + + /* Reset the slave mode Bits */ + tmpsmcr &= ~TIM_SMCR_SMS; + /* Set the slave mode */ + tmpsmcr |= sSlaveConfig->SlaveMode; + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + /* Configure the trigger prescaler, filter, and polarity */ + switch (sSlaveConfig->InputTrigger) + { + case TIM_TS_ETRF: + { + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + /* Configure the ETR Trigger source */ + TIM_ETR_SetConfig(htim->Instance, + sSlaveConfig->TriggerPrescaler, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_TI1F_ED: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + if(sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) + { + return HAL_ERROR; + } + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = htim->Instance->CCER; + htim->Instance->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = htim->Instance->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U); + + /* Write to TIMx CCMR1 and CCER registers */ + htim->Instance->CCMR1 = tmpccmr1; + htim->Instance->CCER = tmpccer; + break; + } + + case TIM_TS_TI1FP1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Configure TI1 Filter and Polarity */ + TIM_TI1_ConfigInputStage(htim->Instance, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_TI2FP2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Configure TI2 Filter and Polarity */ + TIM_TI2_ConfigInputStage(htim->Instance, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_ITR0: + case TIM_TS_ITR1: + case TIM_TS_ITR2: + case TIM_TS_ITR3: + { + /* Check the parameter */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + break; + } + + default: + break; + } + return HAL_OK; +} + +/** + * @brief Configure the TI1 as Input. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2. + * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 + * (on channel2 path) is used as the input signal. Therefore CCMR1 must be + * protected against un-initialized filter and polarity values. + */ +void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Select the Input */ + if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) + { + tmpccmr1 &= ~TIM_CCMR1_CC1S; + tmpccmr1 |= TIM_ICSelection; + } + else + { + tmpccmr1 |= TIM_CCMR1_CC1S_0; + } + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the Polarity and Filter for TI1. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = TIMx->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= (TIM_ICFilter << 4U); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + tmpccer |= TIM_ICPolarity; + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI2 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1. + * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 + * (on channel1 path) is used as the input signal. Therefore CCMR1 must be + * protected against un-initialized filter and polarity values. + */ +static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Select the Input */ + tmpccmr1 &= ~TIM_CCMR1_CC2S; + tmpccmr1 |= (TIM_ICSelection << 8U); + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the Polarity and Filter for TI2. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + tmpccmr1 |= (TIM_ICFilter << 12U); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= (TIM_ICPolarity << 4U); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI3 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4. + * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 + * (on channel1 path) is used as the input signal. Therefore CCMR2 must be + * protected against un-initialized filter and polarity values. + */ +static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr2; + uint32_t tmpccer; + + /* Disable the Channel 3: Reset the CC3E Bit */ + TIMx->CCER &= ~TIM_CCER_CC3E; + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + + /* Select the Input */ + tmpccmr2 &= ~TIM_CCMR2_CC3S; + tmpccmr2 |= TIM_ICSelection; + + /* Set the filter */ + tmpccmr2 &= ~TIM_CCMR2_IC3F; + tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); + + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); + tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI4 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3. + * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 + * (on channel1 path) is used as the input signal. Therefore CCMR2 must be + * protected against un-initialized filter and polarity values. + * @retval None + */ +static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr2; + uint32_t tmpccer; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= ~TIM_CCER_CC4E; + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + + /* Select the Input */ + tmpccmr2 &= ~TIM_CCMR2_CC4S; + tmpccmr2 |= (TIM_ICSelection << 8U); + + /* Set the filter */ + tmpccmr2 &= ~TIM_CCMR2_IC4F; + tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F); + + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); + tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer ; +} + +/** + * @brief Selects the Input Trigger source + * @param TIMx to select the TIM peripheral + * @param InputTriggerSource The Input Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal Trigger 0 + * @arg TIM_TS_ITR1: Internal Trigger 1 + * @arg TIM_TS_ITR2: Internal Trigger 2 + * @arg TIM_TS_ITR3: Internal Trigger 3 + * @arg TIM_TS_TI1F_ED: TI1 Edge Detector + * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 + * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 + * @arg TIM_TS_ETRF: External Trigger input + * @retval None + */ +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) +{ + uint32_t tmpsmcr; + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + /* Reset the TS Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + /* Set the Input Trigger source and the slave mode*/ + tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} +/** + * @brief Configures the TIMx External Trigger (ETR). + * @param TIMx to select the TIM peripheral + * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF. + * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2. + * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4. + * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active. + * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active. + * @param ExtTRGFilter External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) +{ + uint32_t tmpsmcr; + + tmpsmcr = TIMx->SMCR; + + /* Reset the ETR Bits */ + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel x. + * @param TIMx to select the TIM peripheral + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @param ChannelState specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. + * @retval None + */ +void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) +{ + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + assert_param(IS_TIM_CHANNELS(Channel)); + + tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ + + /* Reset the CCxE Bit */ + TIMx->CCER &= ~tmp; + + /* Set or reset the CCxE Bit */ + TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ +} + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief Reset interrupt callbacks to the legacy weak callbacks. + * @param htim pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @retval None + */ +void TIM_ResetCallback(TIM_HandleTypeDef *htim) +{ + /* Reset the TIM callback to the legacy weak callbacks */ + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak PeriodElapsedCallback */ + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak PeriodElapsedHalfCpltCallback */ + htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak TriggerCallback */ + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak TriggerHalfCpltCallback */ + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC_CaptureCallback */ + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC_CaptureHalfCpltCallback */ + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC_DelayElapsedCallback */ + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM_PulseFinishedCallback */ + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */ + htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak ErrorCallback */ + htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak CommutationCallback */ + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak CommutationHalfCpltCallback */ + htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak BreakCallback */ +} +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +#endif /* HAL_TIM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c new file mode 100644 index 0000000..99a13c0 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c @@ -0,0 +1,1978 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_tim_ex.c + * @author MCD Application Team + * @brief TIM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Timer Extended peripheral: + * + Time Hall Sensor Interface Initialization + * + Time Hall Sensor Interface Start + * + Time Complementary signal break and dead time configuration + * + Time Master and Slave synchronization configuration + * + Timer remapping capabilities configuration + @verbatim + ============================================================================== + ##### TIMER Extended features ##### + ============================================================================== + [..] + The Timer Extended features include: + (#) Complementary outputs with programmable dead-time for : + (++) Output Compare + (++) PWM generation (Edge and Center-aligned Mode) + (++) One-pulse mode output + (#) Synchronization circuit to control the timer with external signals and to + interconnect several timers together. + (#) Break input to put the timer output signals in reset state or in a known state. + (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for + positioning purposes + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the TIM low level resources by implementing the following functions + depending on the selected feature: + (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit() + + (#) Initialize the TIM low level resources : + (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); + (##) TIM pins configuration + (+++) Enable the clock for the TIM GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + + (#) The external Clock can be configured, if needed (the default clock is the + internal clock from the APBx), using the following function: + HAL_TIM_ConfigClockSource, the clock configuration should be done before + any start function. + + (#) Configure the TIM in the desired functioning mode using one of the + initialization function of this driver: + (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the + Timer Hall Sensor Interface and the commutation event with the corresponding + Interrupt and DMA request if needed (Note that One Timer is used to interface + with the Hall sensor Interface and another Timer should be used to use + the commutation event). + + (#) Activate the TIM peripheral using one of the start functions: + (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT() + (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT() + (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() + (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(). + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup TIMEx TIMEx + * @brief TIM Extended HAL module driver + * @{ + */ + +#ifdef HAL_TIM_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState); + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions + * @{ + */ + +/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions + * @brief Timer Hall Sensor functions + * +@verbatim + ============================================================================== + ##### Timer Hall Sensor functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure TIM HAL Sensor. + (+) De-initialize TIM HAL Sensor. + (+) Start the Hall Sensor Interface. + (+) Stop the Hall Sensor Interface. + (+) Start the Hall Sensor Interface and enable interrupts. + (+) Stop the Hall Sensor Interface and disable interrupts. + (+) Start the Hall Sensor Interface and enable DMA transfers. + (+) Stop the Hall Sensor Interface and disable DMA transfers. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle. + * @param htim TIM Hall Sensor Interface handle + * @param sConfig TIM Hall Sensor configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig) +{ + TIM_OC_InitTypeDef OC_Config; + + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy week callbacks */ + TIM_ResetCallback(htim); + + if (htim->HallSensor_MspInitCallback == NULL) + { + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->HallSensor_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIMEx_HallSensor_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Configure the Time base in the Encoder Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */ + TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + /* Set the IC1PSC value */ + htim->Instance->CCMR1 |= sConfig->IC1Prescaler; + + /* Enable the Hall sensor interface (XOR function of the three inputs) */ + htim->Instance->CR2 |= TIM_CR2_TI1S; + + /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI1F_ED; + + /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_RESET; + + /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/ + OC_Config.OCFastMode = TIM_OCFAST_DISABLE; + OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET; + OC_Config.OCMode = TIM_OCMODE_PWM2; + OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET; + OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH; + OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH; + OC_Config.Pulse = sConfig->Commutation_Delay; + + TIM_OC2_SetConfig(htim->Instance, &OC_Config); + + /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 + register to 101 */ + htim->Instance->CR2 &= ~TIM_CR2_MMS; + htim->Instance->CR2 |= TIM_TRGO_OC2REF; + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM Hall Sensor interface + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->HallSensor_MspDeInitCallback == NULL) + { + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; + } + /* DeInit the low level hardware */ + htim->HallSensor_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIMEx_HallSensor_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Hall Sensor MSP. + * @param htim TIM Hall Sensor Interface handle + * @retval None + */ +__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Hall Sensor MSP. + * @param htim TIM Hall Sensor Interface handle + * @retval None + */ +__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Hall Sensor Interface. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall sensor Interface. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1, 2 and 3 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Hall Sensor Interface in interrupt mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Enable the capture compare Interrupts 1 event */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall Sensor Interface in interrupt mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts event */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Hall Sensor Interface in DMA mode. + * @param htim TIM Hall Sensor Interface handle + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + if (htim->State == HAL_TIM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->State == HAL_TIM_STATE_READY) + { + if (((uint32_t)pData == 0U) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Set the DMA Input Capture 1 Callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream for Capture 1*/ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the capture compare 1 Interrupt */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall Sensor Interface in DMA mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + + /* Disable the capture compare Interrupts 1 event */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions + * @brief Timer Complementary Output Compare functions + * +@verbatim + ============================================================================== + ##### Timer Complementary Output Compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary Output Compare/PWM. + (+) Stop the Complementary Output Compare/PWM. + (+) Start the Complementary Output Compare/PWM and enable interrupts. + (+) Stop the Complementary Output Compare/PWM and disable interrupts. + (+) Start the Complementary Output Compare/PWM and enable DMA transfers. + (+) Stop the Complementary Output Compare/PWM and disable DMA transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the TIM Output Compare signal generation on the complementary + * output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation on the complementary + * output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in interrupt mode + * on the complementary output. + * @param htim TIM OC handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + + default: + break; + } + + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation in interrupt mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpccer; + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + default: + break; + } + + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in DMA mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + if (htim->State == HAL_TIM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->State == HAL_TIM_STATE_READY) + { + if (((uint32_t)pData == 0U) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + default: + break; + } + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation in DMA mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + default: + break; + } + + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions + * @brief Timer Complementary PWM functions + * +@verbatim + ============================================================================== + ##### Timer Complementary PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary PWM. + (+) Stop the Complementary PWM. + (+) Start the Complementary PWM and enable interrupts. + (+) Stop the Complementary PWM and disable interrupts. + (+) Start the Complementary PWM and enable DMA transfers. + (+) Stop the Complementary PWM and disable DMA transfers. + (+) Start the Complementary Input Capture measurement. + (+) Stop the Complementary Input Capture. + (+) Start the Complementary Input Capture and enable interrupts. + (+) Stop the Complementary Input Capture and disable interrupts. + (+) Start the Complementary Input Capture and enable DMA transfers. + (+) Stop the Complementary Input Capture and disable DMA transfers. + (+) Start the Complementary One Pulse generation. + (+) Stop the Complementary One Pulse. + (+) Start the Complementary One Pulse and enable interrupts. + (+) Stop the Complementary One Pulse and disable interrupts. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the PWM signal generation on the complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation on the complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the PWM signal generation in interrupt mode on the + * complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + default: + break; + } + + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation in interrupt mode on the + * complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpccer; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + default: + break; + } + + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM PWM signal generation in DMA mode on the + * complementary output + * @param htim TIM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + if (htim->State == HAL_TIM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->State == HAL_TIM_STATE_READY) + { + if (((uint32_t)pData == 0U) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + default: + break; + } + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM PWM signal generation in DMA mode on the complementary + * output + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + default: + break; + } + + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions + * @brief Timer Complementary One Pulse functions + * +@verbatim + ============================================================================== + ##### Timer Complementary One Pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary One Pulse generation. + (+) Stop the Complementary One Pulse. + (+) Start the Complementary One Pulse and enable interrupts. + (+) Stop the Complementary One Pulse and disable interrupts. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the TIM One Pulse signal generation on the complementary + * output. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Enable the complementary One Pulse output */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation on the complementary + * output. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Disable the complementary One Pulse output */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM One Pulse signal generation in interrupt mode on the + * complementary channel. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + + /* Enable the complementary One Pulse output */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation in interrupt mode on the + * complementary channel. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + + /* Disable the complementary One Pulse output */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure the commutation event in case of use of the Hall sensor interface. + (+) Configure Output channels for OC and PWM mode. + + (+) Configure Complementary channels, break features and dead time. + (+) Configure Master synchronization. + (+) Configure timer remapping capabilities. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the TIM commutation event sequence. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Disable Commutation Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); + + /* Disable Commutation DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configure the TIM commutation event sequence with interrupt. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Disable Commutation DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); + + /* Enable the Commutation Interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configure the TIM commutation event sequence with DMA. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Enable the Commutation DMA Request */ + /* Set the DMA Commutation Callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError; + + /* Disable Commutation Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); + + /* Enable the Commutation DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIM in master mode. + * @param htim TIM handle. + * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that + * contains the selected trigger output (TRGO) and the Master/Slave + * mode. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + TIM_MasterConfigTypeDef *sMasterConfig) +{ + uint32_t tmpcr2; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); + assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); + + /* Check input state */ + __HAL_LOCK(htim); + + /* Change the handler state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Reset the MMS Bits */ + tmpcr2 &= ~TIM_CR2_MMS; + /* Select the TRGO source */ + tmpcr2 |= sMasterConfig->MasterOutputTrigger; + + /* Update TIMx CR2 */ + htim->Instance->CR2 = tmpcr2; + + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + /* Reset the MSM Bit */ + tmpsmcr &= ~TIM_SMCR_MSM; + /* Set master mode */ + tmpsmcr |= sMasterConfig->MasterSlaveMode; + + /* Update TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + } + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State + * and the AOE(automatic output enable). + * @param htim TIM handle + * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that + * contains the BDTR Register configuration information for the TIM peripheral. + * @note Interrupts can be generated when an active level is detected on the + * break input, the break 2 input or the system break input. Break + * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, + TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) +{ + /* Keep this variable initialized to 0 as it is used to configure BDTR register */ + uint32_t tmpbdtr = 0U; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode)); + assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode)); + assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel)); + assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime)); + assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState)); + assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); + assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); + + /* Check input state */ + __HAL_LOCK(htim); + + /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + + /* Set the BDTR bits */ + MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); + MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); + MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); + + + /* Set TIMx_BDTR */ + htim->Instance->BDTR = tmpbdtr; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIMx Remapping input capabilities. + * @param htim TIM handle. + * @param Remap specifies the TIM remapping source. + * For TIM1, the parameter can have the following values: (**) + * @arg TIM_TIM1_TIM3_TRGO: TIM1 ITR2 is connected to TIM3 TRGO + * @arg TIM_TIM1_LPTIM: TIM1 ITR2 is connected to LPTIM1 output + * + * For TIM2, the parameter can have the following values: (**) + * @arg TIM_TIM2_TIM8_TRGO: TIM2 ITR1 is connected to TIM8 TRGO (*) + * @arg TIM_TIM2_ETH_PTP: TIM2 ITR1 is connected to PTP trigger output (*) + * @arg TIM_TIM2_USBFS_SOF: TIM2 ITR1 is connected to OTG FS SOF + * @arg TIM_TIM2_USBHS_SOF: TIM2 ITR1 is connected to OTG FS SOF + * + * For TIM5, the parameter can have the following values: + * @arg TIM_TIM5_GPIO: TIM5 TI4 is connected to GPIO + * @arg TIM_TIM5_LSI: TIM5 TI4 is connected to LSI + * @arg TIM_TIM5_LSE: TIM5 TI4 is connected to LSE + * @arg TIM_TIM5_RTC: TIM5 TI4 is connected to the RTC wakeup interrupt + * @arg TIM_TIM5_TIM3_TRGO: TIM5 ITR1 is connected to TIM3 TRGO (*) + * @arg TIM_TIM5_LPTIM: TIM5 ITR1 is connected to LPTIM1 output (*) + * + * For TIM9, the parameter can have the following values: (**) + * @arg TIM_TIM9_TIM3_TRGO: TIM9 ITR1 is connected to TIM3 TRGO + * @arg TIM_TIM9_LPTIM: TIM9 ITR1 is connected to LPTIM1 output + * + * For TIM11, the parameter can have the following values: + * @arg TIM_TIM11_GPIO: TIM11 TI1 is connected to GPIO + * @arg TIM_TIM11_HSE: TIM11 TI1 is connected to HSE_RTC clock + * @arg TIM_TIM11_SPDIFRX: TIM11 TI1 is connected to SPDIFRX_FRAME_SYNC (*) + * + * (*) Value not defined in all devices. \n + * (**) Register not available in all devices. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) +{ + __HAL_LOCK(htim); + + /* Check parameters */ + assert_param(IS_TIM_REMAP(htim->Instance, Remap)); + +#if defined(LPTIM_OR_TIM1_ITR2_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) + if ((Remap & LPTIM_REMAP_MASK) == LPTIM_REMAP_MASK) + { + /* Connect TIMx internal trigger to LPTIM1 output */ + __HAL_RCC_LPTIM1_CLK_ENABLE(); + MODIFY_REG(LPTIM1->OR, + (LPTIM_OR_TIM1_ITR2_RMP | LPTIM_OR_TIM5_ITR1_RMP | LPTIM_OR_TIM9_ITR1_RMP), + Remap & ~(LPTIM_REMAP_MASK)); + } + else + { + /* Set the Timer remapping configuration */ + WRITE_REG(htim->Instance->OR, Remap); + } +#else + /* Set the Timer remapping configuration */ + WRITE_REG(htim->Instance->OR, Remap); +#endif /* LPTIM_OR_TIM1_ITR2_RMP && LPTIM_OR_TIM5_ITR1_RMP && LPTIM_OR_TIM5_ITR1_RMP */ + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions + * @brief Extended Callbacks functions + * +@verbatim + ============================================================================== + ##### Extended Callbacks functions ##### + ============================================================================== + [..] + This section provides Extended TIM callback functions: + (+) Timer Commutation callback + (+) Timer Break callback + +@endverbatim + * @{ + */ + +/** + * @brief Hall commutation changed callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_CommutCallback could be implemented in the user file + */ +} +/** + * @brief Hall commutation changed half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Break detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_BreakCallback could be implemented in the user file + */ +} +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions + * @brief Extended Peripheral State functions + * +@verbatim + ============================================================================== + ##### Extended Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the TIM Hall Sensor interface handle state. + * @param htim TIM Hall Sensor handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Functions TIMEx Private Functions + * @{ + */ + +/** + * @brief TIM DMA Commutation callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationCallback(htim); +#else + HAL_TIMEx_CommutCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Commutation half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationHalfCpltCallback(htim); +#else + HAL_TIMEx_CommutHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + + +/** + * @brief Enables or disables the TIM Capture Compare Channel xN. + * @param TIMx to select the TIM peripheral + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @param ChannelNState specifies the TIM Channel CCxNE bit new state. + * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. + * @retval None + */ +static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState) +{ + uint32_t tmp; + + tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ + + /* Reset the CCxNE Bit */ + TIMx->CCER &= ~tmp; + + /* Set or reset the CCxNE Bit */ + TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ +} +/** + * @} + */ + +#endif /* HAL_TIM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c new file mode 100644 index 0000000..eaf4114 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c @@ -0,0 +1,3165 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_uart.c + * @author MCD Application Team + * @brief UART HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Errors functions + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The UART HAL driver can be used as follows: + + (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart). + (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API: + (##) Enable the USARTx interface clock. + (##) UART pins configuration: + (+++) Enable the clock for the UART GPIOs. + (+++) Configure these UART pins (TX as alternate function pull-up, RX as alternate function Input). + (##) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT() + and HAL_UART_Receive_IT() APIs): + (+++) Configure the USARTx interrupt priority. + (+++) Enable the NVIC USART IRQ handle. + (##) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA() + and HAL_UART_Receive_DMA() APIs): + (+++) Declare a DMA handle structure for the Tx/Rx stream. + (+++) Enable the DMAx interface clock. + (+++) Configure the declared DMA handle structure with the required + Tx/Rx parameters. + (+++) Configure the DMA Tx/Rx stream. + (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle. + (+++) Configure the priority and enable the NVIC for the transfer complete + interrupt on the DMA Tx/Rx stream. + (+++) Configure the USARTx interrupt priority and enable the NVIC USART IRQ handle + (used for last byte sending completion detection in DMA non circular mode) + + (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware + flow control and Mode(Receiver/Transmitter) in the huart Init structure. + + (#) For the UART asynchronous mode, initialize the UART registers by calling + the HAL_UART_Init() API. + + (#) For the UART Half duplex mode, initialize the UART registers by calling + the HAL_HalfDuplex_Init() API. + + (#) For the LIN mode, initialize the UART registers by calling the HAL_LIN_Init() API. + + (#) For the Multi-Processor mode, initialize the UART registers by calling + the HAL_MultiProcessor_Init() API. + + [..] + (@) The specific UART interrupts (Transmission complete interrupt, + RXNE interrupt and Error Interrupts) will be managed using the macros + __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit + and receive process. + + [..] + (@) These APIs (HAL_UART_Init() and HAL_HalfDuplex_Init()) configure also the + low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customized + HAL_UART_MspInit() API. + + ##### Callback registration ##### + ================================== + + [..] + The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function @ref HAL_UART_RegisterCallback() to register a user callback. + Function @ref HAL_UART_RegisterCallback() allows to register following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) MspInitCallback : UART MspInit. + (+) MspDeInitCallback : UART MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + [..] + Use function @ref HAL_UART_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. + @ref HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) MspInitCallback : UART MspInit. + (+) MspDeInitCallback : UART MspDeInit. + + [..] + By default, after the @ref HAL_UART_Init() and when the state is HAL_UART_STATE_RESET + all callbacks are set to the corresponding weak (surcharged) functions: + examples @ref HAL_UART_TxCpltCallback(), @ref HAL_UART_RxHalfCpltCallback(). + Exception done for MspInit and MspDeInit functions that are respectively + reset to the legacy weak (surcharged) functions in the @ref HAL_UART_Init() + and @ref HAL_UART_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the @ref HAL_UART_Init() and @ref HAL_UART_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user) + MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_UART_RegisterCallback() before calling @ref HAL_UART_DeInit() + or @ref HAL_UART_Init() function. + + [..] + When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available + and weak (surcharged) callbacks are used. + + [..] + Three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Send an amount of data in blocking mode using HAL_UART_Transmit() + (+) Receive an amount of data in blocking mode using HAL_UART_Receive() + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT() + (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_UART_TxCpltCallback + (+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT() + (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_UART_RxCpltCallback + (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_UART_ErrorCallback + + *** DMA mode IO operation *** + ============================== + [..] + (+) Send an amount of data in non blocking mode (DMA) using HAL_UART_Transmit_DMA() + (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback + (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_UART_TxCpltCallback + (+) Receive an amount of data in non blocking mode (DMA) using HAL_UART_Receive_DMA() + (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback + (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_UART_RxCpltCallback + (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_UART_ErrorCallback + (+) Pause the DMA Transfer using HAL_UART_DMAPause() + (+) Resume the DMA Transfer using HAL_UART_DMAResume() + (+) Stop the DMA Transfer using HAL_UART_DMAStop() + + *** UART HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in UART HAL driver. + + (+) __HAL_UART_ENABLE: Enable the UART peripheral + (+) __HAL_UART_DISABLE: Disable the UART peripheral + (+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not + (+) __HAL_UART_CLEAR_FLAG : Clear the specified UART pending flag + (+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt + (+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt + (+) __HAL_UART_GET_IT_SOURCE: Check whether the specified UART interrupt has occurred or not + + [..] + (@) You can refer to the UART HAL driver header file for more useful macros + + @endverbatim + [..] + (@) Additionnal remark: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + Depending on the frame length defined by the M bit (8-bits or 9-bits), + the possible UART frame formats are as listed in the following table: + +-------------------------------------------------------------+ + | M bit | PCE bit | UART frame | + |---------------------|---------------------------------------| + | 0 | 0 | | SB | 8 bit data | STB | | + |---------|-----------|---------------------------------------| + | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|-----------|---------------------------------------| + | 1 | 0 | | SB | 9 bit data | STB | | + |---------|-----------|---------------------------------------| + | 1 | 1 | | SB | 8 bit data | PB | STB | | + +-------------------------------------------------------------+ + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup UART UART + * @brief HAL UART module driver + * @{ + */ +#ifdef HAL_UART_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup UART_Private_Constants + * @{ + */ +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup UART_Private_Functions UART Private Functions + * @{ + */ + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +static void UART_EndTxTransfer(UART_HandleTypeDef *huart); +static void UART_EndRxTransfer(UART_HandleTypeDef *huart); +static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); +static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); +static void UART_DMAError(DMA_HandleTypeDef *hdma); +static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma); +static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart); +static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart); +static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart); +static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); +static void UART_SetConfig(UART_HandleTypeDef *huart); + +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @defgroup UART_Exported_Functions UART Exported Functions + * @{ + */ + +/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USARTx or the UARTy + in asynchronous mode. + (+) For the asynchronous mode only these parameters can be configured: + (++) Baud Rate + (++) Word Length + (++) Stop Bit + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + Depending on the frame length defined by the M bit (8-bits or 9-bits), + please refer to Reference manual for possible UART frame formats. + (++) Hardware flow control + (++) Receiver/transmitter modes + (++) Over Sampling Method + [..] + The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init() and HAL_MultiProcessor_Init() APIs + follow respectively the UART asynchronous, UART Half duplex, LIN and Multi-Processor configuration + procedures (details for the procedures are available in reference manual + (RM0430 for STM32F4X3xx MCUs and RM0402 for STM32F412xx MCUs + RM0383 for STM32F411xC/E MCUs and RM0401 for STM32F410xx MCUs + RM0090 for STM32F4X5xx/STM32F4X7xx/STM32F429xx/STM32F439xx MCUs + RM0390 for STM32F446xx MCUs and RM0386 for STM32F469xx/STM32F479xx MCUs)). + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the UART mode according to the specified parameters in + * the UART_InitTypeDef and create the associated handle. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE) + { + /* The hardware flow control is available only for USART1, USART2, USART3 and USART6. + Except for STM32F446xx devices, that is available for USART1, USART2, USART3, USART6, UART4 and UART5. + */ + assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance)); + assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl)); + } + else + { + assert_param(IS_UART_INSTANCE(huart->Instance)); + } + assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); + assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + UART_SetConfig(huart); + + /* In asynchronous mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + + /* Enable the peripheral */ + __HAL_UART_ENABLE(huart); + + /* Initialize the UART state */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Initializes the half-duplex mode according to the specified + * parameters in the UART_InitTypeDef and create the associated handle. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance)); + assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); + assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + UART_SetConfig(huart); + + /* In half-duplex mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN)); + + /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL); + + /* Enable the peripheral */ + __HAL_UART_ENABLE(huart); + + /* Initialize the UART state*/ + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Initializes the LIN mode according to the specified + * parameters in the UART_InitTypeDef and create the associated handle. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param BreakDetectLength Specifies the LIN break detection length. + * This parameter can be one of the following values: + * @arg UART_LINBREAKDETECTLENGTH_10B: 10-bit break detection + * @arg UART_LINBREAKDETECTLENGTH_11B: 11-bit break detection + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the LIN UART instance */ + assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); + + /* Check the Break detection length parameter */ + assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength)); + assert_param(IS_UART_LIN_WORD_LENGTH(huart->Init.WordLength)); + assert_param(IS_UART_LIN_OVERSAMPLING(huart->Init.OverSampling)); + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + UART_SetConfig(huart); + + /* In LIN mode, the following bits must be kept cleared: + - CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN)); + + /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ + SET_BIT(huart->Instance->CR2, USART_CR2_LINEN); + + /* Set the USART LIN Break detection length. */ + CLEAR_BIT(huart->Instance->CR2, USART_CR2_LBDL); + SET_BIT(huart->Instance->CR2, BreakDetectLength); + + /* Enable the peripheral */ + __HAL_UART_ENABLE(huart); + + /* Initialize the UART state*/ + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Initializes the Multi-Processor mode according to the specified + * parameters in the UART_InitTypeDef and create the associated handle. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param Address USART address + * @param WakeUpMethod specifies the USART wake-up method. + * This parameter can be one of the following values: + * @arg UART_WAKEUPMETHOD_IDLELINE: Wake-up by an idle line detection + * @arg UART_WAKEUPMETHOD_ADDRESSMARK: Wake-up by an address mark + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(huart->Instance)); + + /* Check the Address & wake up method parameters */ + assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod)); + assert_param(IS_UART_ADDRESS(Address)); + assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); + assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + UART_SetConfig(huart); + + /* In Multi-Processor mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register */ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + + /* Set the USART address node */ + CLEAR_BIT(huart->Instance->CR2, USART_CR2_ADD); + SET_BIT(huart->Instance->CR2, Address); + + /* Set the wake up method by setting the WAKE bit in the CR1 register */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_WAKE); + SET_BIT(huart->Instance->CR1, WakeUpMethod); + + /* Enable the peripheral */ + __HAL_UART_ENABLE(huart); + + /* Initialize the UART state */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the UART peripheral. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(huart->Instance)); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + if (huart->MspDeInitCallback == NULL) + { + huart->MspDeInitCallback = HAL_UART_MspDeInit; + } + /* DeInit the low level hardware */ + huart->MspDeInitCallback(huart); +#else + /* DeInit the low level hardware */ + HAL_UART_MspDeInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_RESET; + huart->RxState = HAL_UART_STATE_RESET; + + /* Process Unlock */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief UART MSP Init. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_MspInit could be implemented in the user file + */ +} + +/** + * @brief UART MSP DeInit. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User UART Callback + * To be used instead of the weak predefined callback + * @param huart uart handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(huart); + + if (huart->gState == HAL_UART_STATE_READY) + { + switch (CallbackID) + { + case HAL_UART_TX_HALFCOMPLETE_CB_ID : + huart->TxHalfCpltCallback = pCallback; + break; + + case HAL_UART_TX_COMPLETE_CB_ID : + huart->TxCpltCallback = pCallback; + break; + + case HAL_UART_RX_HALFCOMPLETE_CB_ID : + huart->RxHalfCpltCallback = pCallback; + break; + + case HAL_UART_RX_COMPLETE_CB_ID : + huart->RxCpltCallback = pCallback; + break; + + case HAL_UART_ERROR_CB_ID : + huart->ErrorCallback = pCallback; + break; + + case HAL_UART_ABORT_COMPLETE_CB_ID : + huart->AbortCpltCallback = pCallback; + break; + + case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : + huart->AbortTransmitCpltCallback = pCallback; + break; + + case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : + huart->AbortReceiveCpltCallback = pCallback; + break; + + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = pCallback; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (huart->gState == HAL_UART_STATE_RESET) + { + switch (CallbackID) + { + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = pCallback; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(huart); + + return status; +} + +/** + * @brief Unregister an UART Callback + * UART callaback is redirected to the weak predefined callback + * @param huart uart handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(huart); + + if (HAL_UART_STATE_READY == huart->gState) + { + switch (CallbackID) + { + case HAL_UART_TX_HALFCOMPLETE_CB_ID : + huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + break; + + case HAL_UART_TX_COMPLETE_CB_ID : + huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_UART_RX_HALFCOMPLETE_CB_ID : + huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + break; + + case HAL_UART_RX_COMPLETE_CB_ID : + huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + + case HAL_UART_ERROR_CB_ID : + huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_UART_ABORT_COMPLETE_CB_ID : + huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : + huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + break; + + case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : + huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ + break; + + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = HAL_UART_MspInit; /* Legacy weak MspInitCallback */ + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = HAL_UART_MspDeInit; /* Legacy weak MspDeInitCallback */ + break; + + default : + /* Update the error code */ + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_UART_STATE_RESET == huart->gState) + { + switch (CallbackID) + { + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = HAL_UART_MspInit; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = HAL_UART_MspDeInit; + break; + + default : + /* Update the error code */ + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(huart); + + return status; +} +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group2 IO operation functions + * @brief UART Transmit and Receive functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + This subsection provides a set of functions allowing to manage the UART asynchronous + and Half duplex data transfers. + + (#) There are two modes of transfer: + (+) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (+) Non-Blocking mode: The communication is performed using Interrupts + or DMA, these API's return the HAL status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks + will be executed respectively at the end of the transmit or receive process + The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected. + + (#) Blocking mode API's are : + (+) HAL_UART_Transmit() + (+) HAL_UART_Receive() + + (#) Non-Blocking mode API's with Interrupt are : + (+) HAL_UART_Transmit_IT() + (+) HAL_UART_Receive_IT() + (+) HAL_UART_IRQHandler() + + (#) Non-Blocking mode API's with DMA are : + (+) HAL_UART_Transmit_DMA() + (+) HAL_UART_Receive_DMA() + (+) HAL_UART_DMAPause() + (+) HAL_UART_DMAResume() + (+) HAL_UART_DMAStop() + + (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode: + (+) HAL_UART_TxHalfCpltCallback() + (+) HAL_UART_TxCpltCallback() + (+) HAL_UART_RxHalfCpltCallback() + (+) HAL_UART_RxCpltCallback() + (+) HAL_UART_ErrorCallback() + + (#) Non-Blocking mode transfers could be aborted using Abort API's : + (+) HAL_UART_Abort() + (+) HAL_UART_AbortTransmit() + (+) HAL_UART_AbortReceive() + (+) HAL_UART_Abort_IT() + (+) HAL_UART_AbortTransmit_IT() + (+) HAL_UART_AbortReceive_IT() + + (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided: + (+) HAL_UART_AbortCpltCallback() + (+) HAL_UART_AbortTransmitCpltCallback() + (+) HAL_UART_AbortReceiveCpltCallback() + + (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. + Errors are handled as follows : + (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, + and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side. + If user wants to abort it, Abort services should be called by user. + (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed. + + -@- In the Half duplex communication, it is forbidden to run the transmit + and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful. + +@endverbatim + * @{ + */ + +/** + * @brief Sends an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint16_t *tmp; + uint32_t tickstart = 0U; + + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_BUSY_TX; + + /* Init tickstart for timeout managment */ + tickstart = HAL_GetTick(); + + huart->TxXferSize = Size; + huart->TxXferCount = Size; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + while (huart->TxXferCount > 0U) + { + huart->TxXferCount--; + if (huart->Init.WordLength == UART_WORDLENGTH_9B) + { + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + tmp = (uint16_t *) pData; + huart->Instance->DR = (*tmp & (uint16_t)0x01FF); + if (huart->Init.Parity == UART_PARITY_NONE) + { + pData += 2U; + } + else + { + pData += 1U; + } + } + else + { + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + huart->Instance->DR = (*pData++ & (uint8_t)0xFF); + } + } + + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receives an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint16_t *tmp; + uint32_t tickstart = 0U; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + + /* Init tickstart for timeout managment */ + tickstart = HAL_GetTick(); + + huart->RxXferSize = Size; + huart->RxXferCount = Size; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + /* Check the remain data to be received */ + while (huart->RxXferCount > 0U) + { + huart->RxXferCount--; + if (huart->Init.WordLength == UART_WORDLENGTH_9B) + { + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + tmp = (uint16_t *) pData; + if (huart->Init.Parity == UART_PARITY_NONE) + { + *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); + pData += 2U; + } + else + { + *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF); + pData += 1U; + } + + } + else + { + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + if (huart->Init.Parity == UART_PARITY_NONE) + { + *pData++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); + } + else + { + *pData++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); + } + + } + } + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sends an amount of data in non blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->pTxBuffPtr = pData; + huart->TxXferSize = Size; + huart->TxXferCount = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_BUSY_TX; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + /* Enable the UART Transmit data register empty Interrupt */ + __HAL_UART_ENABLE_IT(huart, UART_IT_TXE); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receives an amount of data in non blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->pRxBuffPtr = pData; + huart->RxXferSize = Size; + huart->RxXferCount = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + /* Enable the UART Parity Error Interrupt */ + __HAL_UART_ENABLE_IT(huart, UART_IT_PE); + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_UART_ENABLE_IT(huart, UART_IT_ERR); + + /* Enable the UART Data Register not empty Interrupt */ + __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sends an amount of data in DMA mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + uint32_t *tmp; + + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->pTxBuffPtr = pData; + huart->TxXferSize = Size; + huart->TxXferCount = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_BUSY_TX; + + /* Set the UART DMA transfer complete callback */ + huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; + + /* Set the UART DMA Half transfer complete callback */ + huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; + + /* Set the DMA error callback */ + huart->hdmatx->XferErrorCallback = UART_DMAError; + + /* Set the DMA abort callback */ + huart->hdmatx->XferAbortCallback = NULL; + + /* Enable the UART transmit DMA stream */ + tmp = (uint32_t *)&pData; + HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t *)tmp, (uint32_t)&huart->Instance->DR, Size); + + /* Clear the TC flag in the SR register by writing 0 to it */ + __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC); + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the UART CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receives an amount of data in DMA mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @note When the UART parity is enabled (PCE = 1) the received data contains the parity bit. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + uint32_t *tmp; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->pRxBuffPtr = pData; + huart->RxXferSize = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + + /* Set the UART DMA transfer complete callback */ + huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; + + /* Set the UART DMA Half transfer complete callback */ + huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; + + /* Set the DMA error callback */ + huart->hdmarx->XferErrorCallback = UART_DMAError; + + /* Set the DMA abort callback */ + huart->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + tmp = (uint32_t *)&pData; + HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t *)tmp, Size); + + /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */ + __HAL_UART_CLEAR_OREFLAG(huart); + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + /* Enable the UART Parity Error Interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the UART CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Pauses the DMA Transfer. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) +{ + uint32_t dmarequest = 0x00U; + + /* Process Locked */ + __HAL_LOCK(huart); + + dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT); + if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest) + { + /* Disable the UART DMA Tx request */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + } + + dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); + if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest) + { + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the UART DMA Rx request */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Resumes the DMA Transfer. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) +{ + /* Process Locked */ + __HAL_LOCK(huart); + + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + /* Enable the UART DMA Tx request */ + SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); + } + + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + /* Clear the Overrun flag before resuming the Rx transfer*/ + __HAL_UART_CLEAR_OREFLAG(huart); + + /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */ + SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Enable the UART DMA Rx request */ + SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Stops the DMA Transfer. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) +{ + uint32_t dmarequest = 0x00U; + /* The Lock is not implemented on this API to allow the user application + to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback(): + when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated + and the correspond call back is executed HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() + */ + + /* Stop UART DMA Tx request if ongoing */ + dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT); + if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx stream */ + if (huart->hdmatx != NULL) + { + HAL_DMA_Abort(huart->hdmatx); + } + UART_EndTxTransfer(huart); + } + + /* Stop UART DMA Rx request if ongoing */ + dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); + if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx stream */ + if (huart->hdmarx != NULL) + { + HAL_DMA_Abort(huart->hdmarx); + } + UART_EndRxTransfer(huart); + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfers (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) +{ + /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the UART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx stream: use blocking DMA Abort API (no callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx stream: use blocking DMA Abort API (no callback) */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Reset Tx and Rx transfer counters */ + huart->TxXferCount = 0x00U; + huart->RxXferCount = 0x00U; + + /* Reset ErrorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Restore huart->RxState and huart->gState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->gState = HAL_UART_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Abort ongoing Transmit transfer (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) +{ + /* Disable TXEIE and TCIE interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + + /* Disable the UART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx stream : use blocking DMA Abort API (no callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Reset Tx transfer counter */ + huart->TxXferCount = 0x00U; + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx stream : use blocking DMA Abort API (no callback) */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Reset Rx transfer counter */ + huart->RxXferCount = 0x00U; + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfers (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) +{ + uint32_t AbortCplt = 0x01U; + + /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised + before any call to DMA Abort functions */ + /* DMA Tx Handle is valid */ + if (huart->hdmatx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback; + } + else + { + huart->hdmatx->XferAbortCallback = NULL; + } + } + /* DMA Rx Handle is valid */ + if (huart->hdmarx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback; + } + else + { + huart->hdmarx->XferAbortCallback = NULL; + } + } + + /* Disable the UART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + /* Disable DMA Tx at UART level */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx stream : use non blocking DMA Abort API (callback) */ + if (huart->hdmatx != NULL) + { + /* UART Tx DMA Abort callback has already been initialised : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) + { + huart->hdmatx->XferAbortCallback = NULL; + } + else + { + AbortCplt = 0x00U; + } + } + } + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx stream : use non blocking DMA Abort API (callback) */ + if (huart->hdmarx != NULL) + { + /* UART Rx DMA Abort callback has already been initialised : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + huart->hdmarx->XferAbortCallback = NULL; + AbortCplt = 0x01U; + } + else + { + AbortCplt = 0x00U; + } + } + } + + /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ + if (AbortCplt == 0x01U) + { + /* Reset Tx and Rx transfer counters */ + huart->TxXferCount = 0x00U; + huart->RxXferCount = 0x00U; + + /* Reset ErrorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing Transmit transfer (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) +{ + /* Disable TXEIE and TCIE interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + + /* Disable the UART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx stream : use blocking DMA Abort API (no callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) + { + /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */ + huart->hdmatx->XferAbortCallback(huart->hdmatx); + } + } + else + { + /* Reset Tx transfer counter */ + huart->TxXferCount = 0x00U; + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else + { + /* Reset Tx transfer counter */ + huart->TxXferCount = 0x00U; + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx stream : use blocking DMA Abort API (no callback) */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ + huart->hdmarx->XferAbortCallback(huart->hdmarx); + } + } + else + { + /* Reset Rx transfer counter */ + huart->RxXferCount = 0x00U; + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else + { + /* Reset Rx transfer counter */ + huart->RxXferCount = 0x00U; + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief This function handles UART interrupt request. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) +{ + uint32_t isrflags = READ_REG(huart->Instance->SR); + uint32_t cr1its = READ_REG(huart->Instance->CR1); + uint32_t cr3its = READ_REG(huart->Instance->CR3); + uint32_t errorflags = 0x00U; + uint32_t dmarequest = 0x00U; + + /* If no error occurs */ + errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE)); + if (errorflags == RESET) + { + /* UART in mode Receiver -------------------------------------------------*/ + if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) + { + UART_Receive_IT(huart); + return; + } + } + + /* If some errors occur */ + if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) + { + /* UART parity error interrupt occurred ----------------------------------*/ + if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) + { + huart->ErrorCode |= HAL_UART_ERROR_PE; + } + + /* UART noise error interrupt occurred -----------------------------------*/ + if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + { + huart->ErrorCode |= HAL_UART_ERROR_NE; + } + + /* UART frame error interrupt occurred -----------------------------------*/ + if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + { + huart->ErrorCode |= HAL_UART_ERROR_FE; + } + + /* UART Over-Run interrupt occurred --------------------------------------*/ + if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET))) + { + huart->ErrorCode |= HAL_UART_ERROR_ORE; + } + + /* Call UART Error Call back function if need be --------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + { + /* UART in mode Receiver -----------------------------------------------*/ + if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) + { + UART_Receive_IT(huart); + } + + /* If Overrun error occurs, or if any error occurs in DMA mode reception, + consider error as blocking */ + dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); + if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest) + { + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ + UART_EndRxTransfer(huart); + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx stream */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + huart->hdmarx->XferAbortCallback(huart->hdmarx); + } + } + else + { + /* Call user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else + { + /* Call user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + + huart->ErrorCode = HAL_UART_ERROR_NONE; + } + } + return; + } /* End if some error occurs */ + + /* UART in mode Transmitter ------------------------------------------------*/ + if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) + { + UART_Transmit_IT(huart); + return; + } + + /* UART in mode Transmitter end --------------------------------------------*/ + if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) + { + UART_EndTransmit_IT(huart); + return; + } +} + +/** + * @brief Tx Transfer completed callbacks. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Tx Half Transfer completed callbacks. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_TxHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callbacks. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_RxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Half Transfer completed callbacks. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_RxHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief UART error callbacks. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief UART Abort Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Receive Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions + * @brief UART control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the UART: + (+) HAL_LIN_SendBreak() API can be helpful to transmit the break character. + (+) HAL_MultiProcessor_EnterMuteMode() API can be helpful to enter the UART in mute mode. + (+) HAL_MultiProcessor_ExitMuteMode() API can be helpful to exit the UART mute mode by software. + (+) HAL_HalfDuplex_EnableTransmitter() API to enable the UART transmitter and disables the UART receiver in Half Duplex mode + (+) HAL_HalfDuplex_EnableReceiver() API to enable the UART receiver and disables the UART transmitter in Half Duplex mode + +@endverbatim + * @{ + */ + +/** + * @brief Transmits break characters. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) +{ + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(huart->Instance)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Send break characters */ + SET_BIT(huart->Instance->CR1, USART_CR1_SBK); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Enters the UART in mute mode. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) +{ + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(huart->Instance)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Enable the USART mute mode by setting the RWU bit in the CR1 register */ + SET_BIT(huart->Instance->CR1, USART_CR1_RWU); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Exits the UART mute mode: wake up software. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart) +{ + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(huart->Instance)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_RWU); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Enables the UART transmitter and disables the UART receiver. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) +{ + uint32_t tmpreg = 0x00U; + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /*-------------------------- USART CR1 Configuration -----------------------*/ + tmpreg = huart->Instance->CR1; + + /* Clear TE and RE bits */ + tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE)); + + /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */ + tmpreg |= (uint32_t)USART_CR1_TE; + + /* Write to USART CR1 */ + WRITE_REG(huart->Instance->CR1, (uint32_t)tmpreg); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Enables the UART receiver and disables the UART transmitter. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) +{ + uint32_t tmpreg = 0x00U; + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /*-------------------------- USART CR1 Configuration -----------------------*/ + tmpreg = huart->Instance->CR1; + + /* Clear TE and RE bits */ + tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE)); + + /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */ + tmpreg |= (uint32_t)USART_CR1_RE; + + /* Write to USART CR1 */ + WRITE_REG(huart->Instance->CR1, (uint32_t)tmpreg); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Errors functions + * @brief UART State and Errors functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Errors functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to return the State of + UART communication process, return Peripheral Errors occurred during communication + process + (+) HAL_UART_GetState() API can be helpful to check in run-time the state of the UART peripheral. + (+) HAL_UART_GetError() check in run-time errors that could be occurred during communication. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the UART state. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL state + */ +HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) +{ + uint32_t temp1 = 0x00U, temp2 = 0x00U; + temp1 = huart->gState; + temp2 = huart->RxState; + + return (HAL_UART_StateTypeDef)(temp1 | temp2); +} + +/** + * @brief Return the UART error code + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART. + * @retval UART Error Code + */ +uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) +{ + return huart->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup UART_Private_Functions UART Private Functions + * @{ + */ + +/** + * @brief Initialize the callbacks to their default values. + * @param huart UART handle. + * @retval none + */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart) +{ + /* Init the UART Callback settings */ + huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ + huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ + +} +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @brief DMA UART transmit process complete callback. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + /* DMA Normal mode*/ + if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U) + { + huart->TxXferCount = 0x00U; + + /* Disable the DMA transfer for transmit request by setting the DMAT bit + in the UART CR3 register */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Enable the UART Transmit Complete Interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + + } + /* DMA Circular mode */ + else + { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxCpltCallback(huart); +#else + /*Call legacy weak Tx complete callback*/ + HAL_UART_TxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA UART transmit process half complete callback + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxHalfCpltCallback(huart); +#else + /*Call legacy weak Tx complete callback*/ + HAL_UART_TxHalfCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART receive process complete callback. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + /* DMA Normal mode*/ + if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U) + { + huart->RxXferCount = 0U; + + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the DMA transfer for the receiver request by setting the DMAR bit + in the UART CR3 register */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + } +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART receive process half complete callback + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Half complete callback*/ + huart->RxHalfCpltCallback(huart); +#else + /*Call legacy weak Rx Half complete callback*/ + HAL_UART_RxHalfCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART communication error callback. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMAError(DMA_HandleTypeDef *hdma) +{ + uint32_t dmarequest = 0x00U; + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Stop UART DMA Tx request if ongoing */ + dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT); + if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest) + { + huart->TxXferCount = 0x00U; + UART_EndTxTransfer(huart); + } + + /* Stop UART DMA Rx request if ongoing */ + dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); + if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest) + { + huart->RxXferCount = 0x00U; + UART_EndRxTransfer(huart); + } + + huart->ErrorCode |= HAL_UART_ERROR_DMA; +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief This function handles UART Communication Timeout. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param Flag specifies the UART flag to check. + * @param Status The new Flag status (SET or RESET). + * @param Tickstart Tick start value + * @param Timeout Timeout duration + * @retval HAL status + */ +static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) +{ + /* Wait until flag is set */ + while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) + { + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + +/** + * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). + * @param huart UART handle. + * @retval None + */ +static void UART_EndTxTransfer(UART_HandleTypeDef *huart) +{ + /* Disable TXEIE and TCIE interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; +} + +/** + * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). + * @param huart UART handle. + * @retval None + */ +static void UART_EndRxTransfer(UART_HandleTypeDef *huart) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; +} + +/** + * @brief DMA UART communication abort callback, when initiated by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + huart->RxXferCount = 0x00U; + huart->TxXferCount = 0x00U; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART Tx communication abort callback, when initiated by user + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Rx DMA Handle. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + huart->hdmatx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (huart->hdmarx != NULL) + { + if (huart->hdmarx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + huart->TxXferCount = 0x00U; + huart->RxXferCount = 0x00U; + + /* Reset ErrorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART Rx communication abort callback, when initiated by user + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Tx DMA Handle. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + huart->hdmarx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (huart->hdmatx != NULL) + { + if (huart->hdmatx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + huart->TxXferCount = 0x00U; + huart->RxXferCount = 0x00U; + + /* Reset ErrorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART Tx communication abort callback, when initiated by user by a call to + * HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) + * (This callback is executed at end of DMA Tx Abort procedure following user abort request, + * and leads to user Tx Abort Complete callback execution). + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + huart->TxXferCount = 0x00U; + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART Rx communication abort callback, when initiated by user by a call to + * HAL_UART_AbortReceive_IT API (Abort only Rx transfer) + * (This callback is executed at end of DMA Rx Abort procedure following user abort request, + * and leads to user Rx Abort Complete callback execution). + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + huart->RxXferCount = 0x00U; + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief Sends an amount of data in non blocking mode. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) +{ + uint16_t *tmp; + + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + if (huart->Init.WordLength == UART_WORDLENGTH_9B) + { + tmp = (uint16_t *) huart->pTxBuffPtr; + huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); + if (huart->Init.Parity == UART_PARITY_NONE) + { + huart->pTxBuffPtr += 2U; + } + else + { + huart->pTxBuffPtr += 1U; + } + } + else + { + huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF); + } + + if (--huart->TxXferCount == 0U) + { + /* Disable the UART Transmit Complete Interrupt */ + __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); + + /* Enable the UART Transmit Complete Interrupt */ + __HAL_UART_ENABLE_IT(huart, UART_IT_TC); + } + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Wraps up transmission in non blocking mode. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) +{ + /* Disable the UART Transmit Complete Interrupt */ + __HAL_UART_DISABLE_IT(huart, UART_IT_TC); + + /* Tx process is ended, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxCpltCallback(huart); +#else + /*Call legacy weak Tx complete callback*/ + HAL_UART_TxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + + return HAL_OK; +} + +/** + * @brief Receives an amount of data in non blocking mode + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) +{ + uint16_t *tmp; + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + if (huart->Init.WordLength == UART_WORDLENGTH_9B) + { + tmp = (uint16_t *) huart->pRxBuffPtr; + if (huart->Init.Parity == UART_PARITY_NONE) + { + *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); + huart->pRxBuffPtr += 2U; + } + else + { + *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF); + huart->pRxBuffPtr += 1U; + } + } + else + { + if (huart->Init.Parity == UART_PARITY_NONE) + { + *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); + } + else + { + *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); + } + } + + if (--huart->RxXferCount == 0U) + { + /* Disable the UART Data Register not empty Interrupt */ + __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); + + /* Disable the UART Parity Error Interrupt */ + __HAL_UART_DISABLE_IT(huart, UART_IT_PE); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + + return HAL_OK; + } + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Configures the UART peripheral. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +static void UART_SetConfig(UART_HandleTypeDef *huart) +{ + uint32_t tmpreg; + uint32_t pclk; + + /* Check the parameters */ + assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate)); + assert_param(IS_UART_STOPBITS(huart->Init.StopBits)); + assert_param(IS_UART_PARITY(huart->Init.Parity)); + assert_param(IS_UART_MODE(huart->Init.Mode)); + + /*-------------------------- USART CR2 Configuration -----------------------*/ + /* Configure the UART Stop Bits: Set STOP[13:12] bits + according to huart->Init.StopBits value */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); + + /*-------------------------- USART CR1 Configuration -----------------------*/ + /* Configure the UART Word Length, Parity and mode: + Set the M bits according to huart->Init.WordLength value + Set PCE and PS bits according to huart->Init.Parity value + Set TE and RE bits according to huart->Init.Mode value + Set OVER8 bit according to huart->Init.OverSampling value */ + + tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; + MODIFY_REG(huart->Instance->CR1, + (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), + tmpreg); + + /*-------------------------- USART CR3 Configuration -----------------------*/ + /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ + MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); + + /* Check the Over Sampling */ + if (huart->Init.OverSampling == UART_OVERSAMPLING_8) + { + /*-------------------------- USART BRR Configuration ---------------------*/ +#if defined(USART6) && defined(UART9) && defined(UART10) + if ((huart->Instance == USART1) || (huart->Instance == USART6) || (huart->Instance == UART9) || (huart->Instance == UART10)) + { + pclk = HAL_RCC_GetPCLK2Freq(); + huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate); + } +#elif defined(USART6) + if ((huart->Instance == USART1) || (huart->Instance == USART6)) + { + pclk = HAL_RCC_GetPCLK2Freq(); + huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate); + } +#else + if (huart->Instance == USART1) + { + pclk = HAL_RCC_GetPCLK2Freq(); + huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate); + } +#endif /* USART6 */ + else + { + pclk = HAL_RCC_GetPCLK1Freq(); + huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate); + } + } + else + { + /*-------------------------- USART BRR Configuration ---------------------*/ +#if defined(USART6) && defined(UART9) && defined(UART10) + if ((huart->Instance == USART1) || (huart->Instance == USART6) || (huart->Instance == UART9) || (huart->Instance == UART10)) + { + pclk = HAL_RCC_GetPCLK2Freq(); + huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); + } +#elif defined(USART6) + if ((huart->Instance == USART1) || (huart->Instance == USART6)) + { + pclk = HAL_RCC_GetPCLK2Freq(); + huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); + } +#else + if (huart->Instance == USART1) + { + pclk = HAL_RCC_GetPCLK2Freq(); + huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); + } +#endif /* USART6 */ + else + { + pclk = HAL_RCC_GetPCLK1Freq(); + huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); + } + } +} + +/** + * @} + */ + +#endif /* HAL_UART_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c new file mode 100644 index 0000000..da8da4a --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c @@ -0,0 +1,2039 @@ +/** + ****************************************************************************** + * @file stm32f4xx_ll_usb.c + * @author MCD Application Team + * @brief USB Low Layer HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the USB Peripheral Controller: + * + Initialization/de-initialization functions + * + I/O operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure. + + (#) Call USB_CoreInit() API to initialize the USB Core peripheral. + + (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_LL_USB_DRIVER + * @{ + */ + +#if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx); + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup USB_LL_Exported_Functions USB Low Layer Exported Functions + * @{ + */ + +/** @defgroup USB_LL_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization/de-initialization functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the USB Core + * @param USBx USB Instance + * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains + * the configuration information for the specified USBx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) +{ + HAL_StatusTypeDef ret; + + if (cfg.phy_itface == USB_OTG_ULPI_PHY) + { + USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); + + /* Init The ULPI Interface */ + USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL); + + /* Select vbus source */ + USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI); + if (cfg.use_external_vbus == 1U) + { + USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD; + } + /* Reset after a PHY select */ + ret = USB_CoreReset(USBx); + } + else /* FS interface (embedded Phy) */ + { + /* Select FS Embedded PHY */ + USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; + + /* Reset after a PHY select */ + ret = USB_CoreReset(USBx); + + if (cfg.battery_charging_enable == 0U) + { + /* Activate the USB Transceiver */ + USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; + } + else + { + /* Deactivate the USB Transceiver */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); + } + } + + if (cfg.dma_enable == 1U) + { + USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2; + USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN; + } + + return ret; +} + + +/** + * @brief Set the USB turnaround time + * @param USBx USB Instance + * @param hclk: AHB clock frequency + * @retval USB turnaround time In PHY Clocks number + */ +HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, + uint32_t hclk, uint8_t speed) +{ + uint32_t UsbTrd; + + /* The USBTRD is configured according to the tables below, depending on AHB frequency + used by application. In the low AHB frequency range it is used to stretch enough the USB response + time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access + latency to the Data FIFO */ + if (speed == USBD_FS_SPEED) + { + if ((hclk >= 14200000U) && (hclk < 15000000U)) + { + /* hclk Clock Range between 14.2-15 MHz */ + UsbTrd = 0xFU; + } + else if ((hclk >= 15000000U) && (hclk < 16000000U)) + { + /* hclk Clock Range between 15-16 MHz */ + UsbTrd = 0xEU; + } + else if ((hclk >= 16000000U) && (hclk < 17200000U)) + { + /* hclk Clock Range between 16-17.2 MHz */ + UsbTrd = 0xDU; + } + else if ((hclk >= 17200000U) && (hclk < 18500000U)) + { + /* hclk Clock Range between 17.2-18.5 MHz */ + UsbTrd = 0xCU; + } + else if ((hclk >= 18500000U) && (hclk < 20000000U)) + { + /* hclk Clock Range between 18.5-20 MHz */ + UsbTrd = 0xBU; + } + else if ((hclk >= 20000000U) && (hclk < 21800000U)) + { + /* hclk Clock Range between 20-21.8 MHz */ + UsbTrd = 0xAU; + } + else if ((hclk >= 21800000U) && (hclk < 24000000U)) + { + /* hclk Clock Range between 21.8-24 MHz */ + UsbTrd = 0x9U; + } + else if ((hclk >= 24000000U) && (hclk < 27700000U)) + { + /* hclk Clock Range between 24-27.7 MHz */ + UsbTrd = 0x8U; + } + else if ((hclk >= 27700000U) && (hclk < 32000000U)) + { + /* hclk Clock Range between 27.7-32 MHz */ + UsbTrd = 0x7U; + } + else /* if(hclk >= 32000000) */ + { + /* hclk Clock Range between 32-200 MHz */ + UsbTrd = 0x6U; + } + } + else if (speed == USBD_HS_SPEED) + { + UsbTrd = USBD_HS_TRDT_VALUE; + } + else + { + UsbTrd = USBD_DEFAULT_TRDT_VALUE; + } + + USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT; + USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT); + + return HAL_OK; +} + +/** + * @brief USB_EnableGlobalInt + * Enables the controller's Global Int in the AHB Config reg + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx) +{ + USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT; + return HAL_OK; +} + +/** + * @brief USB_DisableGlobalInt + * Disable the controller's Global Int in the AHB Config reg + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) +{ + USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; + return HAL_OK; +} + +/** + * @brief USB_SetCurrentMode Set functional mode + * @param USBx Selected device + * @param mode current core mode + * This parameter can be one of these values: + * @arg USB_DEVICE_MODE Peripheral mode + * @arg USB_HOST_MODE Host mode + * @retval HAL status + */ +HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode) +{ + USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); + + if (mode == USB_HOST_MODE) + { + USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; + } + else if (mode == USB_DEVICE_MODE) + { + USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; + } + else + { + return HAL_ERROR; + } + HAL_Delay(50U); + + return HAL_OK; +} + +/** + * @brief USB_DevInit Initializes the USB_OTG controller registers + * for device mode + * @param USBx Selected device + * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains + * the configuration information for the specified USBx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) +{ + HAL_StatusTypeDef ret = HAL_OK; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t i; + + for (i = 0U; i < 15U; i++) + { + USBx->DIEPTXF[i] = 0U; + } + +#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) + /* VBUS Sensing setup */ + if (cfg.vbus_sensing_enable == 0U) + { + USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; + + /* Deactivate VBUS Sensing B */ + USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN; + + /* B-peripheral session valid override enable */ + USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; + USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; + } + else + { + /* Enable HW VBUS sensing */ + USBx->GCCFG |= USB_OTG_GCCFG_VBDEN; + } +#else + /* VBUS Sensing setup */ + if (cfg.vbus_sensing_enable == 0U) + { + /* + * Disable HW VBUS sensing. VBUS is internally considered to be always + * at VBUS-Valid level (5V). + */ + USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; + USBx->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS; + USBx->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN; + USBx->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN; + } + else + { + /* Enable HW VBUS sensing */ + USBx->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS; + USBx->GCCFG |= USB_OTG_GCCFG_VBUSBSEN; + } +#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ + + /* Restart the Phy Clock */ + USBx_PCGCCTL = 0U; + + /* Device mode configuration */ + USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80; + + if (cfg.phy_itface == USB_OTG_ULPI_PHY) + { + if (cfg.speed == USBD_HS_SPEED) + { + /* Set Core speed to High speed mode */ + (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH); + } + else + { + /* Set Core speed to Full speed mode */ + (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL); + } + } + else + { + /* Set Core speed to Full speed mode */ + (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL); + } + + /* Flush the FIFOs */ + if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ + { + ret = HAL_ERROR; + } + + if (USB_FlushRxFifo(USBx) != HAL_OK) + { + ret = HAL_ERROR; + } + + /* Clear all pending Device Interrupts */ + USBx_DEVICE->DIEPMSK = 0U; + USBx_DEVICE->DOEPMSK = 0U; + USBx_DEVICE->DAINTMSK = 0U; + + for (i = 0U; i < cfg.dev_endpoints; i++) + { + if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) + { + if (i == 0U) + { + USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK; + } + else + { + USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK; + } + } + else + { + USBx_INEP(i)->DIEPCTL = 0U; + } + + USBx_INEP(i)->DIEPTSIZ = 0U; + USBx_INEP(i)->DIEPINT = 0xFB7FU; + } + + for (i = 0U; i < cfg.dev_endpoints; i++) + { + if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + { + if (i == 0U) + { + USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK; + } + else + { + USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK; + } + } + else + { + USBx_OUTEP(i)->DOEPCTL = 0U; + } + + USBx_OUTEP(i)->DOEPTSIZ = 0U; + USBx_OUTEP(i)->DOEPINT = 0xFB7FU; + } + + USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM); + + /* Disable all interrupts. */ + USBx->GINTMSK = 0U; + + /* Clear any pending interrupts */ + USBx->GINTSTS = 0xBFFFFFFFU; + + /* Enable the common interrupts */ + if (cfg.dma_enable == 0U) + { + USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; + } + + /* Enable interrupts matching to the Device mode ONLY */ + USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST | + USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT | + USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM | + USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM; + + if (cfg.Sof_enable != 0U) + { + USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM; + } + + if (cfg.vbus_sensing_enable == 1U) + { + USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); + } + + return ret; +} + +/** + * @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO + * @param USBx Selected device + * @param num FIFO number + * This parameter can be a value from 1 to 15 + 15 means Flush all Tx FIFOs + * @retval HAL status + */ +HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) +{ + uint32_t count = 0U; + + USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6)); + + do + { + if (++count > 200000U) + { + return HAL_TIMEOUT; + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH); + + return HAL_OK; +} + +/** + * @brief USB_FlushRxFifo : Flush Rx FIFO + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t count = 0; + + USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; + + do + { + if (++count > 200000U) + { + return HAL_TIMEOUT; + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH); + + return HAL_OK; +} + +/** + * @brief USB_SetDevSpeed Initializes the DevSpd field of DCFG register + * depending the PHY type and the enumeration speed of the device. + * @param USBx Selected device + * @param speed device speed + * This parameter can be one of these values: + * @arg USB_OTG_SPEED_HIGH: High speed mode + * @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode + * @arg USB_OTG_SPEED_FULL: Full speed mode + * @retval Hal status + */ +HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + USBx_DEVICE->DCFG |= speed; + return HAL_OK; +} + +/** + * @brief USB_GetDevSpeed Return the Dev Speed + * @param USBx Selected device + * @retval speed device speed + * This parameter can be one of these values: + * @arg PCD_SPEED_HIGH: High speed mode + * @arg PCD_SPEED_FULL: Full speed mode + */ +uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint8_t speed; + uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD; + + if (DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ) + { + speed = USBD_HS_SPEED; + } + else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) || + (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ)) + { + speed = USBD_FS_SPEED; + } + else + { + speed = 0xFU; + } + + return speed; +} + +/** + * @brief Activate and configure an endpoint + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + if (ep->is_in == 1U) + { + USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)); + + if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U) + { + USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | (epnum << 22) | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DIEPCTL_USBAEP; + } + } + else + { + USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16); + + if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) + { + USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DOEPCTL_USBAEP; + } + } + return HAL_OK; +} + +/** + * @brief Activate and configure a dedicated endpoint + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + /* Read DEPCTLn register */ + if (ep->is_in == 1U) + { + if (((USBx_INEP(epnum)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0U) + { + USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | (epnum << 22) | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DIEPCTL_USBAEP; + } + + USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)); + } + else + { + if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) + { + USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | (epnum << 22) | + USB_OTG_DOEPCTL_USBAEP; + } + + USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16); + } + + return HAL_OK; +} + +/** + * @brief De-activate and de-initialize an endpoint + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + /* Read DEPCTLn register */ + if (ep->is_in == 1U) + { + if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS; + } + + USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); + USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP | + USB_OTG_DIEPCTL_MPSIZ | + USB_OTG_DIEPCTL_TXFNUM | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DIEPCTL_EPTYP); + } + else + { + if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS; + } + + USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); + USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP | + USB_OTG_DOEPCTL_MPSIZ | + USB_OTG_DOEPCTL_SD0PID_SEVNFRM | + USB_OTG_DOEPCTL_EPTYP); + } + + return HAL_OK; +} + +/** + * @brief De-activate and de-initialize a dedicated endpoint + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + /* Read DEPCTLn register */ + if (ep->is_in == 1U) + { + if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS; + } + + USBx_INEP(epnum)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP; + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); + } + else + { + if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS; + } + + USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP; + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); + } + + return HAL_OK; +} + +/** + * @brief USB_EPStartXfer : setup and starts a transfer over an EP + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @param dma USB dma enabled or disabled + * This parameter can be one of these values: + * 0 : DMA feature not used + * 1 : DMA feature used + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + uint16_t pktcnt; + + /* IN endpoint */ + if (ep->is_in == 1U) + { + /* Zero Length Packet? */ + if (ep->xfer_len == 0U) + { + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + } + else + { + /* Program the transfer size and packet count + * as follows: xfersize = N * maxpacket + + * short_packet pktcnt = N + (short_packet + * exist ? 1 : 0) + */ + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19)); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); + + if (ep->type == EP_TYPE_ISOC) + { + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29)); + } + } + + if (dma == 1U) + { + if ((uint32_t)ep->dma_addr != 0U) + { + USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr); + } + + if (ep->type == EP_TYPE_ISOC) + { + if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; + } + else + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; + } + } + + /* EP enable, IN data in FIFO */ + USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + } + else + { + /* EP enable, IN data in FIFO */ + USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + + if (ep->type != EP_TYPE_ISOC) + { + /* Enable the Tx FIFO Empty Interrupt for this EP */ + if (ep->xfer_len > 0U) + { + USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK); + } + } + else + { + if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; + } + else + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; + } + + (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len, dma); + } + } + } + else /* OUT endpoint */ + { + /* Program the transfer size and packet count as follows: + * pktcnt = N + * xfersize = N * maxpacket + */ + USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); + USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); + + if (ep->xfer_len == 0U) + { + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket); + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + } + else + { + pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); + USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19); + USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt); + } + + if (dma == 1U) + { + if ((uint32_t)ep->xfer_buff != 0U) + { + USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff); + } + } + + if (ep->type == EP_TYPE_ISOC) + { + if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM; + } + else + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; + } + } + /* EP enable */ + USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); + } + + return HAL_OK; +} + +/** + * @brief USB_EP0StartXfer : setup and starts a transfer over the EP 0 + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @param dma USB dma enabled or disabled + * This parameter can be one of these values: + * 0 : DMA feature not used + * 1 : DMA feature used + * @retval HAL status + */ +HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + /* IN endpoint */ + if (ep->is_in == 1U) + { + /* Zero Length Packet? */ + if (ep->xfer_len == 0U) + { + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + } + else + { + /* Program the transfer size and packet count + * as follows: xfersize = N * maxpacket + + * short_packet pktcnt = N + (short_packet + * exist ? 1 : 0) + */ + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + + if (ep->xfer_len > ep->maxpacket) + { + ep->xfer_len = ep->maxpacket; + } + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); + } + + if (dma == 1U) + { + if ((uint32_t)ep->dma_addr != 0U) + { + USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr); + } + + /* EP enable, IN data in FIFO */ + USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + } + else + { + /* EP enable, IN data in FIFO */ + USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + + /* Enable the Tx FIFO Empty Interrupt for this EP */ + if (ep->xfer_len > 0U) + { + USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK); + } + } + } + else /* OUT endpoint */ + { + /* Program the transfer size and packet count as follows: + * pktcnt = N + * xfersize = N * maxpacket + */ + USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); + USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); + + if (ep->xfer_len > 0U) + { + ep->xfer_len = ep->maxpacket; + } + + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket)); + + if (dma == 1U) + { + if ((uint32_t)ep->xfer_buff != 0U) + { + USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff); + } + } + + /* EP enable */ + USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); + } + + return HAL_OK; +} + +/** + * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated + * with the EP/channel + * @param USBx Selected device + * @param src pointer to source buffer + * @param ch_ep_num endpoint or host channel number + * @param len Number of bytes to write + * @param dma USB dma enabled or disabled + * This parameter can be one of these values: + * 0 : DMA feature not used + * 1 : DMA feature used + * @retval HAL status + */ +HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, + uint8_t ch_ep_num, uint16_t len, uint8_t dma) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t *pSrc = (uint32_t *)src; + uint32_t count32b, i; + + if (dma == 0U) + { + count32b = ((uint32_t)len + 3U) / 4U; + for (i = 0U; i < count32b; i++) + { + USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc); + pSrc++; + } + } + + return HAL_OK; +} + +/** + * @brief USB_ReadPacket : read a packet from the RX FIFO + * @param USBx Selected device + * @param dest source pointer + * @param len Number of bytes to read + * @retval pointer to destination buffer + */ +void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t *pDest = (uint32_t *)dest; + uint32_t i; + uint32_t count32b = ((uint32_t)len + 3U) / 4U; + + for (i = 0U; i < count32b; i++) + { + __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U)); + pDest++; + } + + return ((void *)pDest); +} + +/** + * @brief USB_EPSetStall : set a stall condition over an EP + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + if (ep->is_in == 1U) + { + if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U)) + { + USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); + } + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL; + } + else + { + if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U)) + { + USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); + } + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL; + } + + return HAL_OK; +} + +/** + * @brief USB_EPClearStall : Clear a stall condition over an EP + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + if (ep->is_in == 1U) + { + USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; + if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */ + } + } + else + { + USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; + if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */ + } + } + return HAL_OK; +} + +/** + * @brief USB_StopDevice : Stop the usb device mode + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx) +{ + HAL_StatusTypeDef ret; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t i; + + /* Clear Pending interrupt */ + for (i = 0U; i < 15U; i++) + { + USBx_INEP(i)->DIEPINT = 0xFB7FU; + USBx_OUTEP(i)->DOEPINT = 0xFB7FU; + } + + /* Clear interrupt masks */ + USBx_DEVICE->DIEPMSK = 0U; + USBx_DEVICE->DOEPMSK = 0U; + USBx_DEVICE->DAINTMSK = 0U; + + /* Flush the FIFO */ + ret = USB_FlushRxFifo(USBx); + if (ret != HAL_OK) + { + return ret; + } + + ret = USB_FlushTxFifo(USBx, 0x10U); + if (ret != HAL_OK) + { + return ret; + } + + return ret; +} + +/** + * @brief USB_SetDevAddress : Stop the usb device mode + * @param USBx Selected device + * @param address new device address to be assigned + * This parameter can be a value from 0 to 255 + * @retval HAL status + */ +HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD); + USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD; + + return HAL_OK; +} + +/** + * @brief USB_DevConnect : Connect the USB device by enabling Rpu + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + /* In case phy is stopped, ensure to ungate and restore the phy CLK */ + USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); + + USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS; + + return HAL_OK; +} + +/** + * @brief USB_DevDisconnect : Disconnect the USB device by disabling Rpu + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + /* In case phy is stopped, ensure to ungate and restore the phy CLK */ + USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); + + USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; + + return HAL_OK; +} + +/** + * @brief USB_ReadInterrupts: return the global USB interrupt status + * @param USBx Selected device + * @retval HAL status + */ +uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t tmpreg; + + tmpreg = USBx->GINTSTS; + tmpreg &= USBx->GINTMSK; + + return tmpreg; +} + +/** + * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status + * @param USBx Selected device + * @retval HAL status + */ +uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + + tmpreg = USBx_DEVICE->DAINT; + tmpreg &= USBx_DEVICE->DAINTMSK; + + return ((tmpreg & 0xffff0000U) >> 16); +} + +/** + * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status + * @param USBx Selected device + * @retval HAL status + */ +uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + + tmpreg = USBx_DEVICE->DAINT; + tmpreg &= USBx_DEVICE->DAINTMSK; + + return ((tmpreg & 0xFFFFU)); +} + +/** + * @brief Returns Device OUT EP Interrupt register + * @param USBx Selected device + * @param epnum endpoint number + * This parameter can be a value from 0 to 15 + * @retval Device OUT EP Interrupt register + */ +uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + + tmpreg = USBx_OUTEP((uint32_t)epnum)->DOEPINT; + tmpreg &= USBx_DEVICE->DOEPMSK; + + return tmpreg; +} + +/** + * @brief Returns Device IN EP Interrupt register + * @param USBx Selected device + * @param epnum endpoint number + * This parameter can be a value from 0 to 15 + * @retval Device IN EP Interrupt register + */ +uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg, msk, emp; + + msk = USBx_DEVICE->DIEPMSK; + emp = USBx_DEVICE->DIEPEMPMSK; + msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7; + tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk; + + return tmpreg; +} + +/** + * @brief USB_ClearInterrupts: clear a USB interrupt + * @param USBx Selected device + * @param interrupt flag + * @retval None + */ +void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) +{ + USBx->GINTSTS |= interrupt; +} + +/** + * @brief Returns USB core mode + * @param USBx Selected device + * @retval return core mode : Host or Device + * This parameter can be one of these values: + * 0 : Host + * 1 : Device + */ +uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx) +{ + return ((USBx->GINTSTS) & 0x1U); +} + +/** + * @brief Activate EP0 for Setup transactions + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + /* Set the MPS of the IN EP0 to 64 bytes */ + USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ; + + USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK; + + return HAL_OK; +} + +/** + * @brief Prepare the EP0 to start the first control setup + * @param USBx Selected device + * @param dma USB dma enabled or disabled + * This parameter can be one of these values: + * 0 : DMA feature not used + * 1 : DMA feature used + * @param psetup pointer to setup packet + * @retval HAL status + */ +HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U); + + if (gSNPSiD > USB_OTG_CORE_ID_300A) + { + if ((USBx_OUTEP(0U)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + { + return HAL_OK; + } + } + + USBx_OUTEP(0U)->DOEPTSIZ = 0U; + USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U); + USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT; + + if (dma == 1U) + { + USBx_OUTEP(0U)->DOEPDMA = (uint32_t)psetup; + /* EP enable */ + USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_USBAEP; + } + + return HAL_OK; +} + +/** + * @brief Reset the USB Core (needed after USB clock settings change) + * @param USBx Selected device + * @retval HAL status + */ +static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t count = 0U; + + /* Wait for AHB master IDLE state. */ + do + { + if (++count > 200000U) + { + return HAL_TIMEOUT; + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); + + /* Core Soft Reset */ + count = 0U; + USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; + + do + { + if (++count > 200000U) + { + return HAL_TIMEOUT; + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST); + + return HAL_OK; +} + +/** + * @brief USB_HostInit : Initializes the USB OTG controller registers + * for Host mode + * @param USBx Selected device + * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains + * the configuration information for the specified USBx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t i; + + /* Restart the Phy Clock */ + USBx_PCGCCTL = 0U; + +#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) + /* Disable HW VBUS sensing */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_VBDEN); +#else + /* + * Disable HW VBUS sensing. VBUS is internally considered to be always + * at VBUS-Valid level (5V). + */ + USBx->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS; + USBx->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN; + USBx->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN; +#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) + /* Disable Battery chargin detector */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN); +#endif /* defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ + + if ((USBx->CID & (0x1U << 8)) != 0U) + { + if (cfg.speed == USBH_FSLS_SPEED) + { + /* Force Device Enumeration to FS/LS mode only */ + USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS; + } + else + { + /* Set default Max speed support */ + USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS); + } + } + else + { + /* Set default Max speed support */ + USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS); + } + + /* Make sure the FIFOs are flushed. */ + (void)USB_FlushTxFifo(USBx, 0x10U); /* all Tx FIFOs */ + (void)USB_FlushRxFifo(USBx); + + /* Clear all pending HC Interrupts */ + for (i = 0U; i < cfg.Host_channels; i++) + { + USBx_HC(i)->HCINT = 0xFFFFFFFFU; + USBx_HC(i)->HCINTMSK = 0U; + } + + /* Enable VBUS driving */ + (void)USB_DriveVbus(USBx, 1U); + + HAL_Delay(200U); + + /* Disable all interrupts. */ + USBx->GINTMSK = 0U; + + /* Clear any pending interrupts */ + USBx->GINTSTS = 0xFFFFFFFFU; + + if ((USBx->CID & (0x1U << 8)) != 0U) + { + /* set Rx FIFO size */ + USBx->GRXFSIZ = 0x200U; + USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x100U << 16) & USB_OTG_NPTXFD) | 0x200U); + USBx->HPTXFSIZ = (uint32_t)(((0xE0U << 16) & USB_OTG_HPTXFSIZ_PTXFD) | 0x300U); + } + else + { + /* set Rx FIFO size */ + USBx->GRXFSIZ = 0x80U; + USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x60U << 16) & USB_OTG_NPTXFD) | 0x80U); + USBx->HPTXFSIZ = (uint32_t)(((0x40U << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0U); + } + + /* Enable the common interrupts */ + if (cfg.dma_enable == 0U) + { + USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; + } + + /* Enable interrupts matching to the Host mode ONLY */ + USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM | \ + USB_OTG_GINTMSK_SOFM | USB_OTG_GINTSTS_DISCINT | \ + USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM); + + return HAL_OK; +} + +/** + * @brief USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the + * HCFG register on the PHY type and set the right frame interval + * @param USBx Selected device + * @param freq clock frequency + * This parameter can be one of these values: + * HCFG_48_MHZ : Full Speed 48 MHz Clock + * HCFG_6_MHZ : Low Speed 6 MHz Clock + * @retval HAL status + */ +HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS); + USBx_HOST->HCFG |= (uint32_t)freq & USB_OTG_HCFG_FSLSPCS; + + if (freq == HCFG_48_MHZ) + { + USBx_HOST->HFIR = 48000U; + } + else if (freq == HCFG_6_MHZ) + { + USBx_HOST->HFIR = 6000U; + } + else + { + /* ... */ + } + + return HAL_OK; +} + +/** + * @brief USB_OTG_ResetPort : Reset Host Port + * @param USBx Selected device + * @retval HAL status + * @note (1)The application must wait at least 10 ms + * before clearing the reset bit. + */ +HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + __IO uint32_t hprt0 = 0U; + + hprt0 = USBx_HPRT0; + + hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | + USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); + + USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0); + HAL_Delay(100U); /* See Note #1 */ + USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0); + HAL_Delay(10U); + + return HAL_OK; +} + +/** + * @brief USB_DriveVbus : activate or de-activate vbus + * @param state VBUS state + * This parameter can be one of these values: + * 0 : Deactivate VBUS + * 1 : Activate VBUS + * @retval HAL status + */ +HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + __IO uint32_t hprt0 = 0U; + + hprt0 = USBx_HPRT0; + + hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | + USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); + + if (((hprt0 & USB_OTG_HPRT_PPWR) == 0U) && (state == 1U)) + { + USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0); + } + if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0U)) + { + USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0); + } + return HAL_OK; +} + +/** + * @brief Return Host Core speed + * @param USBx Selected device + * @retval speed : Host speed + * This parameter can be one of these values: + * @arg HCD_SPEED_HIGH: High speed mode + * @arg HCD_SPEED_FULL: Full speed mode + * @arg HCD_SPEED_LOW: Low speed mode + */ +uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + __IO uint32_t hprt0 = 0U; + + hprt0 = USBx_HPRT0; + return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17); +} + +/** + * @brief Return Host Current Frame number + * @param USBx Selected device + * @retval current frame number + */ +uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM); +} + +/** + * @brief Initialize a host channel + * @param USBx Selected device + * @param ch_num Channel number + * This parameter can be a value from 1 to 15 + * @param epnum Endpoint number + * This parameter can be a value from 1 to 15 + * @param dev_address Current device address + * This parameter can be a value from 0 to 255 + * @param speed Current device speed + * This parameter can be one of these values: + * @arg USB_OTG_SPEED_HIGH: High speed mode + * @arg USB_OTG_SPEED_FULL: Full speed mode + * @arg USB_OTG_SPEED_LOW: Low speed mode + * @param ep_type Endpoint Type + * This parameter can be one of these values: + * @arg EP_TYPE_CTRL: Control type + * @arg EP_TYPE_ISOC: Isochronous type + * @arg EP_TYPE_BULK: Bulk type + * @arg EP_TYPE_INTR: Interrupt type + * @param mps Max Packet Size + * This parameter can be a value from 0 to32K + * @retval HAL state + */ +HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, + uint8_t epnum, uint8_t dev_address, uint8_t speed, + uint8_t ep_type, uint16_t mps) +{ + HAL_StatusTypeDef ret = HAL_OK; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t HCcharEpDir, HCcharLowSpeed; + + /* Clear old interrupt conditions for this host channel. */ + USBx_HC((uint32_t)ch_num)->HCINT = 0xFFFFFFFFU; + + /* Enable channel interrupts required for this transfer. */ + switch (ep_type) + { + case EP_TYPE_CTRL: + case EP_TYPE_BULK: + USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | + USB_OTG_HCINTMSK_STALLM | + USB_OTG_HCINTMSK_TXERRM | + USB_OTG_HCINTMSK_DTERRM | + USB_OTG_HCINTMSK_AHBERR | + USB_OTG_HCINTMSK_NAKM; + + if ((epnum & 0x80U) == 0x80U) + { + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; + } + else + { + if ((USBx->CID & (0x1U << 8)) != 0U) + { + USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM); + } + } + break; + + case EP_TYPE_INTR: + USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | + USB_OTG_HCINTMSK_STALLM | + USB_OTG_HCINTMSK_TXERRM | + USB_OTG_HCINTMSK_DTERRM | + USB_OTG_HCINTMSK_NAKM | + USB_OTG_HCINTMSK_AHBERR | + USB_OTG_HCINTMSK_FRMORM; + + if ((epnum & 0x80U) == 0x80U) + { + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; + } + + break; + + case EP_TYPE_ISOC: + USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | + USB_OTG_HCINTMSK_ACKM | + USB_OTG_HCINTMSK_AHBERR | + USB_OTG_HCINTMSK_FRMORM; + + if ((epnum & 0x80U) == 0x80U) + { + USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM); + } + break; + + default: + ret = HAL_ERROR; + break; + } + + /* Enable the top level host channel interrupt. */ + USBx_HOST->HAINTMSK |= 1UL << (ch_num & 0xFU); + + /* Make sure host channel interrupts are enabled. */ + USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM; + + /* Program the HCCHAR register */ + if ((epnum & 0x80U) == 0x80U) + { + HCcharEpDir = (0x1U << 15) & USB_OTG_HCCHAR_EPDIR; + } + else + { + HCcharEpDir = 0U; + } + + if (speed == HPRT0_PRTSPD_LOW_SPEED) + { + HCcharLowSpeed = (0x1U << 17) & USB_OTG_HCCHAR_LSDEV; + } + else + { + HCcharLowSpeed = 0U; + } + + USBx_HC((uint32_t)ch_num)->HCCHAR = (((uint32_t)dev_address << 22) & USB_OTG_HCCHAR_DAD) | + ((((uint32_t)epnum & 0x7FU) << 11) & USB_OTG_HCCHAR_EPNUM) | + (((uint32_t)ep_type << 18) & USB_OTG_HCCHAR_EPTYP) | + ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | HCcharEpDir | HCcharLowSpeed; + + if (ep_type == EP_TYPE_INTR) + { + USBx_HC((uint32_t)ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ; + } + + return ret; +} + +/** + * @brief Start a transfer over a host channel + * @param USBx Selected device + * @param hc pointer to host channel structure + * @param dma USB dma enabled or disabled + * This parameter can be one of these values: + * 0 : DMA feature not used + * 1 : DMA feature used + * @retval HAL state + */ +HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t ch_num = (uint32_t)hc->ch_num; + static __IO uint32_t tmpreg = 0U; + uint8_t is_oddframe; + uint16_t len_words; + uint16_t num_packets; + uint16_t max_hc_pkt_count = 256U; + + if (((USBx->CID & (0x1U << 8)) != 0U) && (hc->speed == USBH_HS_SPEED)) + { + if ((dma == 0U) && (hc->do_ping == 1U)) + { + (void)USB_DoPing(USBx, hc->ch_num); + return HAL_OK; + } + else if (dma == 1U) + { + USBx_HC(ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM); + hc->do_ping = 0U; + } + else + { + /* ... */ + } + } + + /* Compute the expected number of packets associated to the transfer */ + if (hc->xfer_len > 0U) + { + num_packets = (uint16_t)((hc->xfer_len + hc->max_packet - 1U) / hc->max_packet); + + if (num_packets > max_hc_pkt_count) + { + num_packets = max_hc_pkt_count; + hc->xfer_len = (uint32_t)num_packets * hc->max_packet; + } + } + else + { + num_packets = 1U; + } + if (hc->ep_is_in != 0U) + { + hc->xfer_len = (uint32_t)num_packets * hc->max_packet; + } + + /* Initialize the HCTSIZn register */ + USBx_HC(ch_num)->HCTSIZ = (hc->xfer_len & USB_OTG_HCTSIZ_XFRSIZ) | + (((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) | + (((uint32_t)hc->data_pid << 29) & USB_OTG_HCTSIZ_DPID); + + if (dma != 0U) + { + /* xfer_buff MUST be 32-bits aligned */ + USBx_HC(ch_num)->HCDMA = (uint32_t)hc->xfer_buff; + } + + is_oddframe = (((uint32_t)USBx_HOST->HFNUM & 0x01U) != 0U) ? 0U : 1U; + USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM; + USBx_HC(ch_num)->HCCHAR |= (uint32_t)is_oddframe << 29; + + /* Set host channel enable */ + tmpreg = USBx_HC(ch_num)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + + /* make sure to set the correct ep direction */ + if (hc->ep_is_in != 0U) + { + tmpreg |= USB_OTG_HCCHAR_EPDIR; + } + else + { + tmpreg &= ~USB_OTG_HCCHAR_EPDIR; + } + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(ch_num)->HCCHAR = tmpreg; + + if (dma != 0U) /* dma mode */ + { + return HAL_OK; + } + + if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U)) + { + switch (hc->ep_type) + { + /* Non periodic transfer */ + case EP_TYPE_CTRL: + case EP_TYPE_BULK: + + len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); + + /* check if there is enough space in FIFO space */ + if (len_words > (USBx->HNPTXSTS & 0xFFFFU)) + { + /* need to process data in nptxfempty interrupt */ + USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM; + } + break; + + /* Periodic transfer */ + case EP_TYPE_INTR: + case EP_TYPE_ISOC: + len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); + /* check if there is enough space in FIFO space */ + if (len_words > (USBx_HOST->HPTXSTS & 0xFFFFU)) /* split the transfer */ + { + /* need to process data in ptxfempty interrupt */ + USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM; + } + break; + + default: + break; + } + + /* Write packet into the Tx FIFO. */ + (void)USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, (uint16_t)hc->xfer_len, 0); + } + + return HAL_OK; +} + +/** + * @brief Read all host channel interrupts status + * @param USBx Selected device + * @retval HAL state + */ +uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + return ((USBx_HOST->HAINT) & 0xFFFFU); +} + +/** + * @brief Halt a host channel + * @param USBx Selected device + * @param hc_num Host Channel number + * This parameter can be a value from 1 to 15 + * @retval HAL state + */ +HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t hcnum = (uint32_t)hc_num; + uint32_t count = 0U; + uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18; + + /* Check for space in the request queue to issue the halt. */ + if ((HcEpType == HCCHAR_CTRL) || (HcEpType == HCCHAR_BULK)) + { + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; + + if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U) + { + USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR; + do + { + if (++count > 1000U) + { + break; + } + } while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + } + else + { + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + } + } + else + { + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; + + if ((USBx_HOST->HPTXSTS & (0xFFU << 16)) == 0U) + { + USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR; + do + { + if (++count > 1000U) + { + break; + } + } while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + } + else + { + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + } + } + + return HAL_OK; +} + +/** + * @brief Initiate Do Ping protocol + * @param USBx Selected device + * @param hc_num Host Channel number + * This parameter can be a value from 1 to 15 + * @retval HAL state + */ +HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t chnum = (uint32_t)ch_num; + uint32_t num_packets = 1U; + uint32_t tmpreg; + + USBx_HC(chnum)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) | + USB_OTG_HCTSIZ_DOPING; + + /* Set host channel enable */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; + + return HAL_OK; +} + +/** + * @brief Stop Host Core + * @param USBx Selected device + * @retval HAL state + */ +HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t count = 0U; + uint32_t value; + uint32_t i; + + (void)USB_DisableGlobalInt(USBx); + + /* Flush FIFO */ + (void)USB_FlushTxFifo(USBx, 0x10U); + (void)USB_FlushRxFifo(USBx); + + /* Flush out any leftover queued requests. */ + for (i = 0U; i <= 15U; i++) + { + value = USBx_HC(i)->HCCHAR; + value |= USB_OTG_HCCHAR_CHDIS; + value &= ~USB_OTG_HCCHAR_CHENA; + value &= ~USB_OTG_HCCHAR_EPDIR; + USBx_HC(i)->HCCHAR = value; + } + + /* Halt all channels to put them into a known state. */ + for (i = 0U; i <= 15U; i++) + { + value = USBx_HC(i)->HCCHAR; + value |= USB_OTG_HCCHAR_CHDIS; + value |= USB_OTG_HCCHAR_CHENA; + value &= ~USB_OTG_HCCHAR_EPDIR; + USBx_HC(i)->HCCHAR = value; + + do + { + if (++count > 1000U) + { + break; + } + } while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + } + + /* Clear any pending Host interrupts */ + USBx_HOST->HAINT = 0xFFFFFFFFU; + USBx->GINTSTS = 0xFFFFFFFFU; + + (void)USB_EnableGlobalInt(USBx); + + return HAL_OK; +} + +/** + * @brief USB_ActivateRemoteWakeup active remote wakeup signalling + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) + { + /* active Remote wakeup signalling */ + USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG; + } + + return HAL_OK; +} + +/** + * @brief USB_DeActivateRemoteWakeup de-active remote wakeup signalling + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + /* active Remote wakeup signalling */ + USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG); + + return HAL_OK; +} +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + + +/** + * @} + */ + +/** + * @} + */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +#endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc/usbh_cdc.h b/Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc/usbh_cdc.h new file mode 100644 index 0000000..a23ea6a --- /dev/null +++ b/Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc/usbh_cdc.h @@ -0,0 +1,448 @@ +/** + ****************************************************************************** + * @file usbh_cdc.h + * @author MCD Application Team + * @brief This file contains all the prototypes for the usbh_cdc.c + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2015 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ + +/* Define to prevent recursive ----------------------------------------------*/ +#ifndef __USBH_CDC_H +#define __USBH_CDC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "usbh_core.h" + + +/** @addtogroup USBH_LIB +* @{ +*/ + +/** @addtogroup USBH_CLASS +* @{ +*/ + +/** @addtogroup USBH_CDC_CLASS +* @{ +*/ + +/** @defgroup USBH_CDC_CORE +* @brief This file is the Header file for usbh_core.c +* @{ +*/ + + + + +/*Communication Class codes*/ +#define USB_CDC_CLASS 0x02U +#define COMMUNICATION_INTERFACE_CLASS_CODE 0x02U + +/*Data Interface Class Codes*/ +#define DATA_INTERFACE_CLASS_CODE 0x0AU + +/*Communication sub class codes*/ +#define RESERVED 0x00U +#define DIRECT_LINE_CONTROL_MODEL 0x01U +#define ABSTRACT_CONTROL_MODEL 0x02U +#define TELEPHONE_CONTROL_MODEL 0x03U +#define MULTICHANNEL_CONTROL_MODEL 0x04U +#define CAPI_CONTROL_MODEL 0x05U +#define ETHERNET_NETWORKING_CONTROL_MODEL 0x06U +#define ATM_NETWORKING_CONTROL_MODEL 0x07U + + +/*Communication Interface Class Control Protocol Codes*/ +#define NO_CLASS_SPECIFIC_PROTOCOL_CODE 0x00U +#define COMMON_AT_COMMAND 0x01U +#define VENDOR_SPECIFIC 0xFFU + + +#define CS_INTERFACE 0x24U +#define CDC_PAGE_SIZE_64 0x40U + +/*Class-Specific Request Codes*/ +#define CDC_SEND_ENCAPSULATED_COMMAND 0x00U +#define CDC_GET_ENCAPSULATED_RESPONSE 0x01U +#define CDC_SET_COMM_FEATURE 0x02U +#define CDC_GET_COMM_FEATURE 0x03U +#define CDC_CLEAR_COMM_FEATURE 0x04U + +#define CDC_SET_AUX_LINE_STATE 0x10U +#define CDC_SET_HOOK_STATE 0x11U +#define CDC_PULSE_SETUP 0x12U +#define CDC_SEND_PULSE 0x13U +#define CDC_SET_PULSE_TIME 0x14U +#define CDC_RING_AUX_JACK 0x15U + +#define CDC_SET_LINE_CODING 0x20U +#define CDC_GET_LINE_CODING 0x21U +#define CDC_SET_CONTROL_LINE_STATE 0x22U +#define CDC_SEND_BREAK 0x23U + +#define CDC_SET_RINGER_PARMS 0x30U +#define CDC_GET_RINGER_PARMS 0x31U +#define CDC_SET_OPERATION_PARMS 0x32U +#define CDC_GET_OPERATION_PARMS 0x33U +#define CDC_SET_LINE_PARMS 0x34U +#define CDC_GET_LINE_PARMS 0x35U +#define CDC_DIAL_DIGITS 0x36U +#define CDC_SET_UNIT_PARAMETER 0x37U +#define CDC_GET_UNIT_PARAMETER 0x38U +#define CDC_CLEAR_UNIT_PARAMETER 0x39U +#define CDC_GET_PROFILE 0x3AU + +#define CDC_SET_ETHERNET_MULTICAST_FILTERS 0x40U +#define CDC_SET_ETHERNET_POWER_MANAGEMENT_PATTERN FILTER 0x41U +#define CDC_GET_ETHERNET_POWER_MANAGEMENT_PATTERN FILTER 0x42U +#define CDC_SET_ETHERNET_PACKET_FILTER 0x43U +#define CDC_GET_ETHERNET_STATISTIC 0x44U + +#define CDC_SET_ATM_DATA_FORMAT 0x50U +#define CDC_GET_ATM_DEVICE_STATISTICS 0x51U +#define CDC_SET_ATM_DEFAULT_VC 0x52U +#define CDC_GET_ATM_VC_STATISTICS 0x53U + + +/* wValue for SetControlLineState*/ +#define CDC_ACTIVATE_CARRIER_SIGNAL_RTS 0x0002U +#define CDC_DEACTIVATE_CARRIER_SIGNAL_RTS 0x0000U +#define CDC_ACTIVATE_SIGNAL_DTR 0x0001U +#define CDC_DEACTIVATE_SIGNAL_DTR 0x0000U + +#define LINE_CODING_STRUCTURE_SIZE 0x07U +/** + * @} + */ + +/** @defgroup USBH_CDC_CORE_Exported_Types +* @{ +*/ + +/* States for CDC State Machine */ +typedef enum +{ + CDC_IDLE = 0U, + CDC_SEND_DATA, + CDC_SEND_DATA_WAIT, + CDC_RECEIVE_DATA, + CDC_RECEIVE_DATA_WAIT, +} +CDC_DataStateTypeDef; + +typedef enum +{ + CDC_IDLE_STATE = 0U, + CDC_SET_LINE_CODING_STATE, + CDC_GET_LAST_LINE_CODING_STATE, + CDC_TRANSFER_DATA, + CDC_ERROR_STATE, +} +CDC_StateTypeDef; + + +/*Line coding structure*/ +typedef union _CDC_LineCodingStructure +{ + uint8_t Array[LINE_CODING_STRUCTURE_SIZE]; + + struct + { + + uint32_t dwDTERate; /*Data terminal rate, in bits per second*/ + uint8_t bCharFormat; /*Stop bits + 0 - 1 Stop bit + 1 - 1.5 Stop bits + 2 - 2 Stop bits*/ + uint8_t bParityType; /* Parity + 0 - None + 1 - Odd + 2 - Even + 3 - Mark + 4 - Space*/ + uint8_t bDataBits; /* Data bits (5, 6, 7, 8 or 16). */ + } b; +} +CDC_LineCodingTypeDef; + + + +/* Header Functional Descriptor +-------------------------------------------------------------------------------- +Offset| field | Size | Value | Description +------|---------------------|-------|------------|------------------------------ +0 | bFunctionLength | 1 | number | Size of this descriptor. +1 | bDescriptorType | 1 | Constant | CS_INTERFACE (0x24) +2 | bDescriptorSubtype | 1 | Constant | Identifier (ID) of functional + | | | | descriptor. +3 | bcdCDC | 2 | | + | | | Number | USB Class Definitions for + | | | | Communication Devices Specification + | | | | release number in binary-coded + | | | | decimal +------|---------------------|-------|------------|------------------------------ +*/ +typedef struct _FunctionalDescriptorHeader +{ + uint8_t bLength; /*Size of this descriptor.*/ + uint8_t bDescriptorType; /*CS_INTERFACE (0x24)*/ + uint8_t bDescriptorSubType; /* Header functional descriptor subtype as*/ + uint16_t bcdCDC; /* USB Class Definitions for Communication + Devices Specification release number in + binary-coded decimal. */ +} +CDC_HeaderFuncDesc_TypeDef; +/* Call Management Functional Descriptor +-------------------------------------------------------------------------------- +Offset| field | Size | Value | Description +------|---------------------|-------|------------|------------------------------ +0 | bFunctionLength | 1 | number | Size of this descriptor. +1 | bDescriptorType | 1 | Constant | CS_INTERFACE (0x24) +2 | bDescriptorSubtype | 1 | Constant | Call Management functional + | | | | descriptor subtype. +3 | bmCapabilities | 1 | Bitmap | The capabilities that this configuration + | | | | supports: + | | | | D7..D2: RESERVED (Reset to zero) + | | | | D1: 0 - Device sends/receives call + | | | | management information only over + | | | | the Communication Class + | | | | interface. + | | | | 1 - Device can send/receive call + | \ | | management information over a + | | | | Data Class interface. + | | | | D0: 0 - Device does not handle call + | | | | management itself. + | | | | 1 - Device handles call + | | | | management itself. + | | | | The previous bits, in combination, identify + | | | | which call management scenario is used. If bit + | | | | D0 is reset to 0, then the value of bit D1 is + | | | | ignored. In this case, bit D1 is reset to zero for + | | | | future compatibility. +4 | bDataInterface | 1 | Number | Interface number of Data Class interface + | | | | optionally used for call management. +------|---------------------|-------|------------|------------------------------ +*/ +typedef struct _CallMgmtFunctionalDescriptor +{ + uint8_t bLength; /*Size of this functional descriptor, in bytes.*/ + uint8_t bDescriptorType; /*CS_INTERFACE (0x24)*/ + uint8_t bDescriptorSubType; /* Call Management functional descriptor subtype*/ + uint8_t bmCapabilities; /* bmCapabilities: D0+D1 */ + uint8_t bDataInterface; /*bDataInterface: 1*/ +} +CDC_CallMgmtFuncDesc_TypeDef; +/* Abstract Control Management Functional Descriptor +-------------------------------------------------------------------------------- +Offset| field | Size | Value | Description +------|---------------------|-------|------------|------------------------------ +0 | bFunctionLength | 1 | number | Size of functional descriptor, in bytes. +1 | bDescriptorType | 1 | Constant | CS_INTERFACE (0x24) +2 | bDescriptorSubtype | 1 | Constant | Abstract Control Management + | | | | functional descriptor subtype. +3 | bmCapabilities | 1 | Bitmap | The capabilities that this configuration + | | | | supports ((A bit value of zero means that the + | | | | request is not supported.) ) + D7..D4: RESERVED (Reset to zero) + | | | | D3: 1 - Device supports the notification + | | | | Network_Connection. + | | | | D2: 1 - Device supports the request + | | | | Send_Break + | | | | D1: 1 - Device supports the request + | \ | | combination of Set_Line_Coding, + | | | | Set_Control_Line_State, Get_Line_Coding, and the + notification Serial_State. + | | | | D0: 1 - Device supports the request + | | | | combination of Set_Comm_Feature, + | | | | Clear_Comm_Feature, and Get_Comm_Feature. + | | | | The previous bits, in combination, identify + | | | | which requests/notifications are supported by + | | | | a Communication Class interface with the + | | | | SubClass code of Abstract Control Model. +------|---------------------|-------|------------|------------------------------ +*/ +typedef struct _AbstractCntrlMgmtFunctionalDescriptor +{ + uint8_t bLength; /*Size of this functional descriptor, in bytes.*/ + uint8_t bDescriptorType; /*CS_INTERFACE (0x24)*/ + uint8_t bDescriptorSubType; /* Abstract Control Management functional + descriptor subtype*/ + uint8_t bmCapabilities; /* The capabilities that this configuration supports */ +} +CDC_AbstCntrlMgmtFuncDesc_TypeDef; +/* Union Functional Descriptor +-------------------------------------------------------------------------------- +Offset| field | Size | Value | Description +------|---------------------|-------|------------|------------------------------ +0 | bFunctionLength | 1 | number | Size of this descriptor. +1 | bDescriptorType | 1 | Constant | CS_INTERFACE (0x24) +2 | bDescriptorSubtype | 1 | Constant | Union functional + | | | | descriptor subtype. +3 | bMasterInterface | 1 | Constant | The interface number of the + | | | | Communication or Data Class interface +4 | bSlaveInterface0 | 1 | Number | nterface number of first slave or associated + | | | | interface in the union. +------|---------------------|-------|------------|------------------------------ +*/ +typedef struct _UnionFunctionalDescriptor +{ + uint8_t bLength; /*Size of this functional descriptor, in bytes*/ + uint8_t bDescriptorType; /*CS_INTERFACE (0x24)*/ + uint8_t bDescriptorSubType; /* Union functional descriptor SubType*/ + uint8_t bMasterInterface; /* The interface number of the Communication or + Data Class interface,*/ + uint8_t bSlaveInterface0; /*Interface number of first slave*/ +} +CDC_UnionFuncDesc_TypeDef; + +typedef struct _USBH_CDCInterfaceDesc +{ + CDC_HeaderFuncDesc_TypeDef CDC_HeaderFuncDesc; + CDC_CallMgmtFuncDesc_TypeDef CDC_CallMgmtFuncDesc; + CDC_AbstCntrlMgmtFuncDesc_TypeDef CDC_AbstCntrlMgmtFuncDesc; + CDC_UnionFuncDesc_TypeDef CDC_UnionFuncDesc; +} +CDC_InterfaceDesc_Typedef; + + +/* Structure for CDC process */ +typedef struct +{ + uint8_t NotifPipe; + uint8_t NotifEp; + uint8_t buff[8]; + uint16_t NotifEpSize; +} +CDC_CommItfTypedef ; + +typedef struct +{ + uint8_t InPipe; + uint8_t OutPipe; + uint8_t OutEp; + uint8_t InEp; + uint8_t buff[8]; + uint16_t OutEpSize; + uint16_t InEpSize; +} +CDC_DataItfTypedef ; + +/* Structure for CDC process */ +typedef struct _CDC_Process +{ + CDC_CommItfTypedef CommItf; + CDC_DataItfTypedef DataItf; + uint8_t *pTxData; + uint8_t *pRxData; + uint32_t TxDataLength; + uint32_t RxDataLength; + CDC_InterfaceDesc_Typedef CDC_Desc; + CDC_LineCodingTypeDef LineCoding; + CDC_LineCodingTypeDef *pUserLineCoding; + CDC_StateTypeDef state; + CDC_DataStateTypeDef data_tx_state; + CDC_DataStateTypeDef data_rx_state; + uint8_t Rx_Poll; +} +CDC_HandleTypeDef; + +/** +* @} +*/ + +/** @defgroup USBH_CDC_CORE_Exported_Defines +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup USBH_CDC_CORE_Exported_Macros +* @{ +*/ +/** +* @} +*/ + +/** @defgroup USBH_CDC_CORE_Exported_Variables +* @{ +*/ +extern USBH_ClassTypeDef CDC_Class; +#define USBH_CDC_CLASS &CDC_Class + +/** +* @} +*/ + +/** @defgroup USBH_CDC_CORE_Exported_FunctionsPrototype +* @{ +*/ + +USBH_StatusTypeDef USBH_CDC_SetLineCoding(USBH_HandleTypeDef *phost, + CDC_LineCodingTypeDef *linecoding); + +USBH_StatusTypeDef USBH_CDC_GetLineCoding(USBH_HandleTypeDef *phost, + CDC_LineCodingTypeDef *linecoding); + +USBH_StatusTypeDef USBH_CDC_Transmit(USBH_HandleTypeDef *phost, + uint8_t *pbuff, + uint32_t length); + +USBH_StatusTypeDef USBH_CDC_Receive(USBH_HandleTypeDef *phost, + uint8_t *pbuff, + uint32_t length); + + +uint16_t USBH_CDC_GetLastReceivedDataSize(USBH_HandleTypeDef *phost); + +USBH_StatusTypeDef USBH_CDC_Stop(USBH_HandleTypeDef *phost); + +void USBH_CDC_LineCodingChanged(USBH_HandleTypeDef *phost); + +void USBH_CDC_TransmitCallback(USBH_HandleTypeDef *phost); + +void USBH_CDC_ReceiveCallback(USBH_HandleTypeDef *phost); + +/** +* @} +*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __USBH_CDC_H */ + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Src/usbh_cdc.c b/Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Src/usbh_cdc.c new file mode 100644 index 0000000..e32d00d --- /dev/null +++ b/Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Src/usbh_cdc.c @@ -0,0 +1,837 @@ +/** + ****************************************************************************** + * @file usbh_cdc.c + * @author MCD Application Team + * @brief This file is the CDC Layer Handlers for USB Host CDC class. + * + * @verbatim + * + * =================================================================== + * CDC Class Driver Description + * =================================================================== + * This driver manages the "Universal Serial Bus Class Definitions for Communications Devices + * Revision 1.2 November 16, 2007" and the sub-protocol specification of "Universal Serial Bus + * Communications Class Subclass Specification for PSTN Devices Revision 1.2 February 9, 2007" + * This driver implements the following aspects of the specification: + * - Device descriptor management + * - Configuration descriptor management + * - Enumeration as CDC device with 2 data endpoints (IN and OUT) and 1 command endpoint (IN) + * - Requests management (as described in section 6.2 in specification) + * - Abstract Control Model compliant + * - Union Functional collection (using 1 IN endpoint for control) + * - Data interface class + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2015 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ + +/* BSPDependencies +- "stm32xxxxx_{eval}{discovery}{nucleo_144}.c" +- "stm32xxxxx_{eval}{discovery}_io.c" +- "stm32xxxxx_{eval}{discovery}{adafruit}_sd.c" +- "stm32xxxxx_{eval}{discovery}{adafruit}_lcd.c" +- "stm32xxxxx_{eval}{discovery}_sdram.c" +EndBSPDependencies */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbh_cdc.h" + +/** @addtogroup USBH_LIB +* @{ +*/ + +/** @addtogroup USBH_CLASS +* @{ +*/ + +/** @addtogroup USBH_CDC_CLASS +* @{ +*/ + +/** @defgroup USBH_CDC_CORE +* @brief This file includes CDC Layer Handlers for USB Host CDC class. +* @{ +*/ + +/** @defgroup USBH_CDC_CORE_Private_TypesDefinitions +* @{ +*/ +/** +* @} +*/ + + +/** @defgroup USBH_CDC_CORE_Private_Defines +* @{ +*/ +#define USBH_CDC_BUFFER_SIZE 1024 +/** +* @} +*/ + + +/** @defgroup USBH_CDC_CORE_Private_Macros +* @{ +*/ +/** +* @} +*/ + + +/** @defgroup USBH_CDC_CORE_Private_Variables +* @{ +*/ +/** +* @} +*/ + + +/** @defgroup USBH_CDC_CORE_Private_FunctionPrototypes +* @{ +*/ + +static USBH_StatusTypeDef USBH_CDC_InterfaceInit(USBH_HandleTypeDef *phost); + +static USBH_StatusTypeDef USBH_CDC_InterfaceDeInit(USBH_HandleTypeDef *phost); + +static USBH_StatusTypeDef USBH_CDC_Process(USBH_HandleTypeDef *phost); + +static USBH_StatusTypeDef USBH_CDC_SOFProcess(USBH_HandleTypeDef *phost); + +static USBH_StatusTypeDef USBH_CDC_ClassRequest(USBH_HandleTypeDef *phost); + +static USBH_StatusTypeDef GetLineCoding(USBH_HandleTypeDef *phost, + CDC_LineCodingTypeDef *linecoding); + +static USBH_StatusTypeDef SetLineCoding(USBH_HandleTypeDef *phost, + CDC_LineCodingTypeDef *linecoding); + +static void CDC_ProcessTransmission(USBH_HandleTypeDef *phost); + +static void CDC_ProcessReception(USBH_HandleTypeDef *phost); + +USBH_ClassTypeDef CDC_Class = +{ + "CDC", + USB_CDC_CLASS, + USBH_CDC_InterfaceInit, + USBH_CDC_InterfaceDeInit, + USBH_CDC_ClassRequest, + USBH_CDC_Process, + USBH_CDC_SOFProcess, + NULL, +}; +/** +* @} +*/ + + +/** @defgroup USBH_CDC_CORE_Private_Functions +* @{ +*/ + +/** + * @brief USBH_CDC_InterfaceInit + * The function init the CDC class. + * @param phost: Host handle + * @retval USBH Status + */ +static USBH_StatusTypeDef USBH_CDC_InterfaceInit(USBH_HandleTypeDef *phost) +{ + + USBH_StatusTypeDef status; + uint8_t interface; + CDC_HandleTypeDef *CDC_Handle; + + interface = USBH_FindInterface(phost, COMMUNICATION_INTERFACE_CLASS_CODE, + ABSTRACT_CONTROL_MODEL, COMMON_AT_COMMAND); + + if ((interface == 0xFFU) || (interface >= USBH_MAX_NUM_INTERFACES)) /* No Valid Interface */ + { + USBH_DbgLog("Cannot Find the interface for Communication Interface Class.", phost->pActiveClass->Name); + return USBH_FAIL; + } + + status = USBH_SelectInterface(phost, interface); + + if (status != USBH_OK) + { + return USBH_FAIL; + } + + phost->pActiveClass->pData = (CDC_HandleTypeDef *)USBH_malloc(sizeof(CDC_HandleTypeDef)); + CDC_Handle = (CDC_HandleTypeDef *) phost->pActiveClass->pData; + + if (CDC_Handle == NULL) + { + USBH_DbgLog("Cannot allocate memory for CDC Handle"); + return USBH_FAIL; + } + + /* Initialize cdc handler */ + USBH_memset(CDC_Handle, 0, sizeof(CDC_HandleTypeDef)); + + /*Collect the notification endpoint address and length*/ + if (phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[0].bEndpointAddress & 0x80U) + { + CDC_Handle->CommItf.NotifEp = phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[0].bEndpointAddress; + CDC_Handle->CommItf.NotifEpSize = phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[0].wMaxPacketSize; + } + + /*Allocate the length for host channel number in*/ + CDC_Handle->CommItf.NotifPipe = USBH_AllocPipe(phost, CDC_Handle->CommItf.NotifEp); + + /* Open pipe for Notification endpoint */ + USBH_OpenPipe(phost, CDC_Handle->CommItf.NotifPipe, CDC_Handle->CommItf.NotifEp, + phost->device.address, phost->device.speed, USB_EP_TYPE_INTR, + CDC_Handle->CommItf.NotifEpSize); + + USBH_LL_SetToggle(phost, CDC_Handle->CommItf.NotifPipe, 0U); + + interface = USBH_FindInterface(phost, DATA_INTERFACE_CLASS_CODE, + RESERVED, NO_CLASS_SPECIFIC_PROTOCOL_CODE); + + if ((interface == 0xFFU) || (interface >= USBH_MAX_NUM_INTERFACES)) /* No Valid Interface */ + { + USBH_DbgLog("Cannot Find the interface for Data Interface Class.", phost->pActiveClass->Name); + return USBH_FAIL; + } + + /*Collect the class specific endpoint address and length*/ + if (phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[0].bEndpointAddress & 0x80U) + { + CDC_Handle->DataItf.InEp = phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[0].bEndpointAddress; + CDC_Handle->DataItf.InEpSize = phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[0].wMaxPacketSize; + } + else + { + CDC_Handle->DataItf.OutEp = phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[0].bEndpointAddress; + CDC_Handle->DataItf.OutEpSize = phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[0].wMaxPacketSize; + } + + if (phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[1].bEndpointAddress & 0x80U) + { + CDC_Handle->DataItf.InEp = phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[1].bEndpointAddress; + CDC_Handle->DataItf.InEpSize = phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[1].wMaxPacketSize; + } + else + { + CDC_Handle->DataItf.OutEp = phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[1].bEndpointAddress; + CDC_Handle->DataItf.OutEpSize = phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[1].wMaxPacketSize; + } + + /*Allocate the length for host channel number out*/ + CDC_Handle->DataItf.OutPipe = USBH_AllocPipe(phost, CDC_Handle->DataItf.OutEp); + + /*Allocate the length for host channel number in*/ + CDC_Handle->DataItf.InPipe = USBH_AllocPipe(phost, CDC_Handle->DataItf.InEp); + + /* Open channel for OUT endpoint */ + USBH_OpenPipe(phost, CDC_Handle->DataItf.OutPipe, CDC_Handle->DataItf.OutEp, + phost->device.address, phost->device.speed, USB_EP_TYPE_BULK, + CDC_Handle->DataItf.OutEpSize); + + /* Open channel for IN endpoint */ + USBH_OpenPipe(phost, CDC_Handle->DataItf.InPipe, CDC_Handle->DataItf.InEp, + phost->device.address, phost->device.speed, USB_EP_TYPE_BULK, + CDC_Handle->DataItf.InEpSize); + + CDC_Handle->state = CDC_IDLE_STATE; + + USBH_LL_SetToggle(phost, CDC_Handle->DataItf.OutPipe, 0U); + USBH_LL_SetToggle(phost, CDC_Handle->DataItf.InPipe, 0U); + + return USBH_OK; +} + + + +/** + * @brief USBH_CDC_InterfaceDeInit + * The function DeInit the Pipes used for the CDC class. + * @param phost: Host handle + * @retval USBH Status + */ +static USBH_StatusTypeDef USBH_CDC_InterfaceDeInit(USBH_HandleTypeDef *phost) +{ + CDC_HandleTypeDef *CDC_Handle = (CDC_HandleTypeDef *) phost->pActiveClass->pData; + + if (CDC_Handle->CommItf.NotifPipe) + { + USBH_ClosePipe(phost, CDC_Handle->CommItf.NotifPipe); + USBH_FreePipe(phost, CDC_Handle->CommItf.NotifPipe); + CDC_Handle->CommItf.NotifPipe = 0U; /* Reset the Channel as Free */ + } + + if (CDC_Handle->DataItf.InPipe) + { + USBH_ClosePipe(phost, CDC_Handle->DataItf.InPipe); + USBH_FreePipe(phost, CDC_Handle->DataItf.InPipe); + CDC_Handle->DataItf.InPipe = 0U; /* Reset the Channel as Free */ + } + + if (CDC_Handle->DataItf.OutPipe) + { + USBH_ClosePipe(phost, CDC_Handle->DataItf.OutPipe); + USBH_FreePipe(phost, CDC_Handle->DataItf.OutPipe); + CDC_Handle->DataItf.OutPipe = 0U; /* Reset the Channel as Free */ + } + + if (phost->pActiveClass->pData) + { + USBH_free(phost->pActiveClass->pData); + phost->pActiveClass->pData = 0U; + } + + return USBH_OK; +} + +/** + * @brief USBH_CDC_ClassRequest + * The function is responsible for handling Standard requests + * for CDC class. + * @param phost: Host handle + * @retval USBH Status + */ +static USBH_StatusTypeDef USBH_CDC_ClassRequest(USBH_HandleTypeDef *phost) +{ + USBH_StatusTypeDef status; + CDC_HandleTypeDef *CDC_Handle = (CDC_HandleTypeDef *) phost->pActiveClass->pData; + + /* Issue the get line coding request */ + status = GetLineCoding(phost, &CDC_Handle->LineCoding); + if (status == USBH_OK) + { + phost->pUser(phost, HOST_USER_CLASS_ACTIVE); + } + else if (status == USBH_NOT_SUPPORTED) + { + USBH_ErrLog("Control error: CDC: Device Get Line Coding configuration failed"); + } + else + { + /* .. */ + } + + return status; +} + + +/** + * @brief USBH_CDC_Process + * The function is for managing state machine for CDC data transfers + * @param phost: Host handle + * @retval USBH Status + */ +static USBH_StatusTypeDef USBH_CDC_Process(USBH_HandleTypeDef *phost) +{ + USBH_StatusTypeDef status = USBH_BUSY; + USBH_StatusTypeDef req_status = USBH_OK; + CDC_HandleTypeDef *CDC_Handle = (CDC_HandleTypeDef *) phost->pActiveClass->pData; + + switch (CDC_Handle->state) + { + + case CDC_IDLE_STATE: + status = USBH_OK; + break; + + case CDC_SET_LINE_CODING_STATE: + req_status = SetLineCoding(phost, CDC_Handle->pUserLineCoding); + + if (req_status == USBH_OK) + { + CDC_Handle->state = CDC_GET_LAST_LINE_CODING_STATE; + } + + else + { + if (req_status != USBH_BUSY) + { + CDC_Handle->state = CDC_ERROR_STATE; + } + } + break; + + + case CDC_GET_LAST_LINE_CODING_STATE: + req_status = GetLineCoding(phost, &(CDC_Handle->LineCoding)); + + if (req_status == USBH_OK) + { + CDC_Handle->state = CDC_IDLE_STATE; + + if ((CDC_Handle->LineCoding.b.bCharFormat == CDC_Handle->pUserLineCoding->b.bCharFormat) && + (CDC_Handle->LineCoding.b.bDataBits == CDC_Handle->pUserLineCoding->b.bDataBits) && + (CDC_Handle->LineCoding.b.bParityType == CDC_Handle->pUserLineCoding->b.bParityType) && + (CDC_Handle->LineCoding.b.dwDTERate == CDC_Handle->pUserLineCoding->b.dwDTERate)) + { + USBH_CDC_LineCodingChanged(phost); + } + } + else + { + if (req_status != USBH_BUSY) + { + CDC_Handle->state = CDC_ERROR_STATE; + } + } + break; + + case CDC_TRANSFER_DATA: + CDC_ProcessTransmission(phost); + CDC_ProcessReception(phost); + break; + + case CDC_ERROR_STATE: + req_status = USBH_ClrFeature(phost, 0x00U); + + if (req_status == USBH_OK) + { + /*Change the state to waiting*/ + CDC_Handle->state = CDC_IDLE_STATE; + } + break; + + default: + break; + + } + + return status; +} + +/** + * @brief USBH_CDC_SOFProcess + * The function is for managing SOF callback + * @param phost: Host handle + * @retval USBH Status + */ +static USBH_StatusTypeDef USBH_CDC_SOFProcess(USBH_HandleTypeDef *phost) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(phost); + + return USBH_OK; +} + + +/** + * @brief USBH_CDC_Stop + * Stop current CDC Transmission + * @param phost: Host handle + * @retval USBH Status + */ +USBH_StatusTypeDef USBH_CDC_Stop(USBH_HandleTypeDef *phost) +{ + CDC_HandleTypeDef *CDC_Handle = (CDC_HandleTypeDef *) phost->pActiveClass->pData; + + if (phost->gState == HOST_CLASS) + { + CDC_Handle->state = CDC_IDLE_STATE; + + USBH_ClosePipe(phost, CDC_Handle->CommItf.NotifPipe); + USBH_ClosePipe(phost, CDC_Handle->DataItf.InPipe); + USBH_ClosePipe(phost, CDC_Handle->DataItf.OutPipe); + } + return USBH_OK; +} +/** + * @brief This request allows the host to find out the currently + * configured line coding. + * @param pdev: Selected device + * @retval USBH_StatusTypeDef : USB ctl xfer status + */ +static USBH_StatusTypeDef GetLineCoding(USBH_HandleTypeDef *phost, CDC_LineCodingTypeDef *linecoding) +{ + + phost->Control.setup.b.bmRequestType = USB_D2H | USB_REQ_TYPE_CLASS | \ + USB_REQ_RECIPIENT_INTERFACE; + + phost->Control.setup.b.bRequest = CDC_GET_LINE_CODING; + phost->Control.setup.b.wValue.w = 0U; + phost->Control.setup.b.wIndex.w = 0U; + phost->Control.setup.b.wLength.w = LINE_CODING_STRUCTURE_SIZE; + + return USBH_CtlReq(phost, linecoding->Array, LINE_CODING_STRUCTURE_SIZE); +} + + +/** + * @brief This request allows the host to specify typical asynchronous + * line-character formatting properties + * This request applies to asynchronous byte stream data class interfaces + * and endpoints + * @param pdev: Selected device + * @retval USBH_StatusTypeDef : USB ctl xfer status + */ +static USBH_StatusTypeDef SetLineCoding(USBH_HandleTypeDef *phost, + CDC_LineCodingTypeDef *linecoding) +{ + phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_TYPE_CLASS | + USB_REQ_RECIPIENT_INTERFACE; + + phost->Control.setup.b.bRequest = CDC_SET_LINE_CODING; + phost->Control.setup.b.wValue.w = 0U; + + phost->Control.setup.b.wIndex.w = 0U; + + phost->Control.setup.b.wLength.w = LINE_CODING_STRUCTURE_SIZE; + + return USBH_CtlReq(phost, linecoding->Array, LINE_CODING_STRUCTURE_SIZE); +} + +/** +* @brief This function prepares the state before issuing the class specific commands +* @param None +* @retval None +*/ +USBH_StatusTypeDef USBH_CDC_SetLineCoding(USBH_HandleTypeDef *phost, + CDC_LineCodingTypeDef *linecoding) +{ + CDC_HandleTypeDef *CDC_Handle = (CDC_HandleTypeDef *) phost->pActiveClass->pData; + + if (phost->gState == HOST_CLASS) + { + CDC_Handle->state = CDC_SET_LINE_CODING_STATE; + CDC_Handle->pUserLineCoding = linecoding; + +#if (USBH_USE_OS == 1U) + phost->os_msg = (uint32_t)USBH_CLASS_EVENT; +#if (osCMSIS < 0x20000U) + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + } + + return USBH_OK; +} + +/** +* @brief This function prepares the state before issuing the class specific commands +* @param None +* @retval None +*/ +USBH_StatusTypeDef USBH_CDC_GetLineCoding(USBH_HandleTypeDef *phost, + CDC_LineCodingTypeDef *linecoding) +{ + CDC_HandleTypeDef *CDC_Handle = (CDC_HandleTypeDef *) phost->pActiveClass->pData; + + if ((phost->gState == HOST_CLASS) || (phost->gState == HOST_CLASS_REQUEST)) + { + *linecoding = CDC_Handle->LineCoding; + return USBH_OK; + } + else + { + return USBH_FAIL; + } +} + +/** + * @brief This function return last received data size + * @param None + * @retval None + */ +uint16_t USBH_CDC_GetLastReceivedDataSize(USBH_HandleTypeDef *phost) +{ + uint32_t dataSize; + CDC_HandleTypeDef *CDC_Handle = (CDC_HandleTypeDef *) phost->pActiveClass->pData; + + if (phost->gState == HOST_CLASS) + { + dataSize = USBH_LL_GetLastXferSize(phost, CDC_Handle->DataItf.InPipe); + } + else + { + dataSize = 0U; + } + + return (uint16_t)dataSize; +} + +/** + * @brief This function prepares the state before issuing the class specific commands + * @param None + * @retval None + */ +USBH_StatusTypeDef USBH_CDC_Transmit(USBH_HandleTypeDef *phost, uint8_t *pbuff, uint32_t length) +{ + USBH_StatusTypeDef Status = USBH_BUSY; + CDC_HandleTypeDef *CDC_Handle = (CDC_HandleTypeDef *) phost->pActiveClass->pData; + + if ((CDC_Handle->state == CDC_IDLE_STATE) || (CDC_Handle->state == CDC_TRANSFER_DATA)) + { + CDC_Handle->pTxData = pbuff; + CDC_Handle->TxDataLength = length; + CDC_Handle->state = CDC_TRANSFER_DATA; + CDC_Handle->data_tx_state = CDC_SEND_DATA; + Status = USBH_OK; + +#if (USBH_USE_OS == 1U) + phost->os_msg = (uint32_t)USBH_CLASS_EVENT; +#if (osCMSIS < 0x20000U) + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + } + return Status; +} + + +/** +* @brief This function prepares the state before issuing the class specific commands +* @param None +* @retval None +*/ +USBH_StatusTypeDef USBH_CDC_Receive(USBH_HandleTypeDef *phost, uint8_t *pbuff, uint32_t length) +{ + USBH_StatusTypeDef Status = USBH_BUSY; + CDC_HandleTypeDef *CDC_Handle = (CDC_HandleTypeDef *) phost->pActiveClass->pData; + + if ((CDC_Handle->state == CDC_IDLE_STATE) || (CDC_Handle->state == CDC_TRANSFER_DATA)) + { + CDC_Handle->pRxData = pbuff; + CDC_Handle->RxDataLength = length; + CDC_Handle->state = CDC_TRANSFER_DATA; + CDC_Handle->data_rx_state = CDC_RECEIVE_DATA; + Status = USBH_OK; + +#if (USBH_USE_OS == 1U) + phost->os_msg = (uint32_t)USBH_CLASS_EVENT; +#if (osCMSIS < 0x20000U) + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + } + return Status; +} + +/** +* @brief The function is responsible for sending data to the device +* @param pdev: Selected device +* @retval None +*/ +static void CDC_ProcessTransmission(USBH_HandleTypeDef *phost) +{ + CDC_HandleTypeDef *CDC_Handle = (CDC_HandleTypeDef *) phost->pActiveClass->pData; + USBH_URBStateTypeDef URB_Status = USBH_URB_IDLE; + + switch (CDC_Handle->data_tx_state) + { + case CDC_SEND_DATA: + if (CDC_Handle->TxDataLength > CDC_Handle->DataItf.OutEpSize) + { + USBH_BulkSendData(phost, + CDC_Handle->pTxData, + CDC_Handle->DataItf.OutEpSize, + CDC_Handle->DataItf.OutPipe, + 1U); + } + else + { + USBH_BulkSendData(phost, + CDC_Handle->pTxData, + (uint16_t)CDC_Handle->TxDataLength, + CDC_Handle->DataItf.OutPipe, + 1U); + } + + CDC_Handle->data_tx_state = CDC_SEND_DATA_WAIT; + break; + + case CDC_SEND_DATA_WAIT: + + URB_Status = USBH_LL_GetURBState(phost, CDC_Handle->DataItf.OutPipe); + + /* Check the status done for transmission */ + if (URB_Status == USBH_URB_DONE) + { + if (CDC_Handle->TxDataLength > CDC_Handle->DataItf.OutEpSize) + { + CDC_Handle->TxDataLength -= CDC_Handle->DataItf.OutEpSize; + CDC_Handle->pTxData += CDC_Handle->DataItf.OutEpSize; + } + else + { + CDC_Handle->TxDataLength = 0U; + } + + if (CDC_Handle->TxDataLength > 0U) + { + CDC_Handle->data_tx_state = CDC_SEND_DATA; + } + else + { + CDC_Handle->data_tx_state = CDC_IDLE; + USBH_CDC_TransmitCallback(phost); + } + +#if (USBH_USE_OS == 1U) + phost->os_msg = (uint32_t)USBH_CLASS_EVENT; +#if (osCMSIS < 0x20000U) + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + } + else + { + if (URB_Status == USBH_URB_NOTREADY) + { + CDC_Handle->data_tx_state = CDC_SEND_DATA; + +#if (USBH_USE_OS == 1U) + phost->os_msg = (uint32_t)USBH_CLASS_EVENT; +#if (osCMSIS < 0x20000U) + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + } + } + break; + + default: + break; + } +} +/** +* @brief This function responsible for reception of data from the device +* @param pdev: Selected device +* @retval None +*/ + +static void CDC_ProcessReception(USBH_HandleTypeDef *phost) +{ + CDC_HandleTypeDef *CDC_Handle = (CDC_HandleTypeDef *) phost->pActiveClass->pData; + USBH_URBStateTypeDef URB_Status = USBH_URB_IDLE; + uint32_t length; + + switch (CDC_Handle->data_rx_state) + { + + case CDC_RECEIVE_DATA: + + USBH_BulkReceiveData(phost, + CDC_Handle->pRxData, + CDC_Handle->DataItf.InEpSize, + CDC_Handle->DataItf.InPipe); + + CDC_Handle->data_rx_state = CDC_RECEIVE_DATA_WAIT; + + break; + + case CDC_RECEIVE_DATA_WAIT: + + URB_Status = USBH_LL_GetURBState(phost, CDC_Handle->DataItf.InPipe); + + /*Check the status done for reception*/ + if (URB_Status == USBH_URB_DONE) + { + length = USBH_LL_GetLastXferSize(phost, CDC_Handle->DataItf.InPipe); + + if (((CDC_Handle->RxDataLength - length) > 0U) && (length > CDC_Handle->DataItf.InEpSize)) + { + CDC_Handle->RxDataLength -= length ; + CDC_Handle->pRxData += length; + CDC_Handle->data_rx_state = CDC_RECEIVE_DATA; + } + else + { + CDC_Handle->data_rx_state = CDC_IDLE; + USBH_CDC_ReceiveCallback(phost); + } + +#if (USBH_USE_OS == 1U) + phost->os_msg = (uint32_t)USBH_CLASS_EVENT; +#if (osCMSIS < 0x20000U) + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + } + break; + + default: + break; + } +} + +/** +* @brief The function informs user that data have been received +* @param pdev: Selected device +* @retval None +*/ +__weak void USBH_CDC_TransmitCallback(USBH_HandleTypeDef *phost) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(phost); +} + +/** +* @brief The function informs user that data have been sent +* @param pdev: Selected device +* @retval None +*/ +__weak void USBH_CDC_ReceiveCallback(USBH_HandleTypeDef *phost) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(phost); +} + +/** +* @brief The function informs user that Settings have been changed +* @param pdev: Selected device +* @retval None +*/ +__weak void USBH_CDC_LineCodingChanged(USBH_HandleTypeDef *phost) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(phost); +} + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + + +/** +* @} +*/ + + +/** +* @} +*/ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_core.h b/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_core.h new file mode 100644 index 0000000..1be86e9 --- /dev/null +++ b/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_core.h @@ -0,0 +1,192 @@ +/** + ****************************************************************************** + * @file usbh_core.h + * @author MCD Application Team + * @brief Header file for usbh_core.c + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2015 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ +/* Define to prevent recursive ----------------------------------------------*/ +#ifndef __USBH_CORE_H +#define __USBH_CORE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "usbh_conf.h" +#include "usbh_def.h" +#include "usbh_ioreq.h" +#include "usbh_pipes.h" +#include "usbh_ctlreq.h" + +/** @addtogroup USBH_LIB + * @{ + */ + +/** @addtogroup USBH_LIB_CORE +* @{ +*/ + +/** @defgroup USBH_CORE + * @brief This file is the Header file for usbh_core.c + * @{ + */ + + +/** @defgroup USBH_CORE_Exported_Defines + * @{ + */ + +/** + * @} + */ +#define HOST_USER_SELECT_CONFIGURATION 0x01U +#define HOST_USER_CLASS_ACTIVE 0x02U +#define HOST_USER_CLASS_SELECTED 0x03U +#define HOST_USER_CONNECTION 0x04U +#define HOST_USER_DISCONNECTION 0x05U +#define HOST_USER_UNRECOVERED_ERROR 0x06U + + +/** + * @} + */ + + + +/** @defgroup USBH_CORE_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBH_CORE_Exported_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBH_CORE_Exported_FunctionsPrototype + * @{ + */ + + +USBH_StatusTypeDef USBH_Init(USBH_HandleTypeDef *phost, void (*pUsrFunc)(USBH_HandleTypeDef *phost, uint8_t id), uint8_t id); +USBH_StatusTypeDef USBH_DeInit(USBH_HandleTypeDef *phost); +USBH_StatusTypeDef USBH_RegisterClass(USBH_HandleTypeDef *phost, USBH_ClassTypeDef *pclass); +USBH_StatusTypeDef USBH_SelectInterface(USBH_HandleTypeDef *phost, uint8_t interface); +uint8_t USBH_FindInterface(USBH_HandleTypeDef *phost, + uint8_t Class, + uint8_t SubClass, + uint8_t Protocol); +uint8_t USBH_GetActiveClass(USBH_HandleTypeDef *phost); + +uint8_t USBH_FindInterfaceIndex(USBH_HandleTypeDef *phost, + uint8_t interface_number, + uint8_t alt_settings); + +uint8_t USBH_IsPortEnabled(USBH_HandleTypeDef *phost); + +USBH_StatusTypeDef USBH_Start(USBH_HandleTypeDef *phost); +USBH_StatusTypeDef USBH_Stop(USBH_HandleTypeDef *phost); +USBH_StatusTypeDef USBH_Process(USBH_HandleTypeDef *phost); +USBH_StatusTypeDef USBH_ReEnumerate(USBH_HandleTypeDef *phost); + +/* USBH Low Level Driver */ +USBH_StatusTypeDef USBH_LL_Init(USBH_HandleTypeDef *phost); +USBH_StatusTypeDef USBH_LL_DeInit(USBH_HandleTypeDef *phost); +USBH_StatusTypeDef USBH_LL_Start(USBH_HandleTypeDef *phost); +USBH_StatusTypeDef USBH_LL_Stop(USBH_HandleTypeDef *phost); + +USBH_StatusTypeDef USBH_LL_Connect(USBH_HandleTypeDef *phost); +USBH_StatusTypeDef USBH_LL_Disconnect(USBH_HandleTypeDef *phost); +USBH_SpeedTypeDef USBH_LL_GetSpeed(USBH_HandleTypeDef *phost); +USBH_StatusTypeDef USBH_LL_ResetPort(USBH_HandleTypeDef *phost); +uint32_t USBH_LL_GetLastXferSize(USBH_HandleTypeDef *phost, + uint8_t pipe); + +USBH_StatusTypeDef USBH_LL_DriverVBUS(USBH_HandleTypeDef *phost, + uint8_t state); + +USBH_StatusTypeDef USBH_LL_OpenPipe(USBH_HandleTypeDef *phost, + uint8_t pipe, + uint8_t epnum, + uint8_t dev_address, + uint8_t speed, + uint8_t ep_type, + uint16_t mps); + +USBH_StatusTypeDef USBH_LL_ClosePipe(USBH_HandleTypeDef *phost, + uint8_t pipe); + +USBH_StatusTypeDef USBH_LL_SubmitURB(USBH_HandleTypeDef *phost, + uint8_t pipe, + uint8_t direction, + uint8_t ep_type, + uint8_t token, + uint8_t *pbuff, + uint16_t length, + uint8_t do_ping); + +USBH_URBStateTypeDef USBH_LL_GetURBState(USBH_HandleTypeDef *phost, + uint8_t pipe); + +#if (USBH_USE_OS == 1U) +USBH_StatusTypeDef USBH_LL_NotifyURBChange(USBH_HandleTypeDef *phost); +#endif + +USBH_StatusTypeDef USBH_LL_SetToggle(USBH_HandleTypeDef *phost, + uint8_t pipe, uint8_t toggle); + +uint8_t USBH_LL_GetToggle(USBH_HandleTypeDef *phost, uint8_t pipe); + +void USBH_LL_PortDisabled(USBH_HandleTypeDef *phost); +void USBH_LL_PortEnabled(USBH_HandleTypeDef *phost); + +/* USBH Time base */ +void USBH_LL_SetTimer(USBH_HandleTypeDef *phost, uint32_t time); +void USBH_LL_IncTimer(USBH_HandleTypeDef *phost); + +void USBH_Delay(uint32_t Delay); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USBH_CORE_H */ +/** + * @} + */ + +/** + * @} + */ + +/** +* @} +*/ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + + + diff --git a/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_ctlreq.h b/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_ctlreq.h new file mode 100644 index 0000000..ca6ca6a --- /dev/null +++ b/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_ctlreq.h @@ -0,0 +1,141 @@ +/** + ****************************************************************************** + * @file usbh_ctlreq.h + * @author MCD Application Team + * @brief Header file for usbh_ctlreq.c + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2015 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ + +/* Define to prevent recursive ----------------------------------------------*/ +#ifndef __USBH_CTLREQ_H +#define __USBH_CTLREQ_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "usbh_core.h" + +/** @addtogroup USBH_LIB + * @{ + */ + +/** @addtogroup USBH_LIB_CORE +* @{ +*/ + +/** @defgroup USBH_CTLREQ + * @brief This file is the + * @{ + */ + + +/** @defgroup USBH_CTLREQ_Exported_Defines + * @{ + */ +/*Standard Feature Selector for clear feature command*/ +#define FEATURE_SELECTOR_ENDPOINT 0x00U +#define FEATURE_SELECTOR_DEVICE 0x01U +#define FEATURE_SELECTOR_REMOTEWAKEUP 0X01U + + +#define INTERFACE_DESC_TYPE 0x04U +#define ENDPOINT_DESC_TYPE 0x05U +#define INTERFACE_DESC_SIZE 0x09U + +/** + * @} + */ + + +/** @defgroup USBH_CTLREQ_Exported_Types + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBH_CTLREQ_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup USBH_CTLREQ_Exported_Variables + * @{ + */ +extern uint8_t USBH_CfgDesc[512]; +/** + * @} + */ + +/** @defgroup USBH_CTLREQ_Exported_FunctionsPrototype + * @{ + */ +USBH_StatusTypeDef USBH_CtlReq(USBH_HandleTypeDef *phost, uint8_t *buff, + uint16_t length); + +USBH_StatusTypeDef USBH_GetDescriptor(USBH_HandleTypeDef *phost, + uint8_t req_type, uint16_t value_idx, + uint8_t *buff, uint16_t length); + +USBH_StatusTypeDef USBH_Get_DevDesc(USBH_HandleTypeDef *phost, uint8_t length); + +USBH_StatusTypeDef USBH_Get_StringDesc(USBH_HandleTypeDef *phost, + uint8_t string_index, uint8_t *buff, + uint16_t length); + +USBH_StatusTypeDef USBH_SetCfg(USBH_HandleTypeDef *phost, uint16_t cfg_idx); + +USBH_StatusTypeDef USBH_Get_CfgDesc(USBH_HandleTypeDef *phost, uint16_t length); + +USBH_StatusTypeDef USBH_SetAddress(USBH_HandleTypeDef *phost, + uint8_t DeviceAddress); + +USBH_StatusTypeDef USBH_SetInterface(USBH_HandleTypeDef *phost, uint8_t ep_num, + uint8_t altSetting); + +USBH_StatusTypeDef USBH_SetFeature(USBH_HandleTypeDef *phost, uint8_t wValue); + +USBH_StatusTypeDef USBH_ClrFeature(USBH_HandleTypeDef *phost, uint8_t ep_num); + +USBH_DescHeader_t *USBH_GetNextDesc(uint8_t *pbuf, uint16_t *ptr); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USBH_CTLREQ_H */ + +/** + * @} + */ + +/** + * @} + */ + +/** +* @} +*/ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + + diff --git a/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_def.h b/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_def.h new file mode 100644 index 0000000..8ce334d --- /dev/null +++ b/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_def.h @@ -0,0 +1,500 @@ +/** + ****************************************************************************** + * @file usbh_def.h + * @author MCD Application Team + * @brief Definitions used in the USB host library + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2015 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ + +/* Define to prevent recursive ----------------------------------------------*/ +#ifndef USBH_DEF_H +#define USBH_DEF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "usbh_conf.h" + +/** @addtogroup USBH_LIB + * @{ + */ + +/** @addtogroup USBH_LIB_CORE +* @{ +*/ + +/** @defgroup USBH_DEF + * @brief This file is includes USB descriptors + * @{ + */ + +#ifndef NULL +#define NULL 0U +#endif + +#ifndef FALSE +#define FALSE 0U +#endif + +#ifndef TRUE +#define TRUE 1U +#endif + +#ifndef USBH_DEV_RESET_TIMEOUT +#define USBH_DEV_RESET_TIMEOUT 1000U +#endif + +#define ValBit(VAR,POS) (VAR & (1 << POS)) +#define SetBit(VAR,POS) (VAR |= (1 << POS)) +#define ClrBit(VAR,POS) (VAR &= ((1 << POS)^255)) + +#define LE16(addr) (((uint16_t)(addr)[0]) | \ + ((uint16_t)(((uint32_t)(addr)[1]) << 8))) + +#define LE24(addr) (((uint32_t)(addr)[0]) | \ + (((uint32_t)(addr)[1]) << 8) | \ + (((uint32_t)(addr)[2]) << 16)) + +#define LE32(addr) (((uint32_t)(addr)[0]) | \ + (((uint32_t)(addr)[1]) << 8) | \ + (((uint32_t)(addr)[2]) << 16) | \ + (((uint32_t)(addr)[3]) << 24)) + +#define LE64(addr) (((uint64_t)(addr)[0]) | \ + (((uint64_t)(addr)[1]) << 8) | \ + (((uint64_t)(addr)[2]) << 16) | \ + (((uint64_t)(addr)[3]) << 24) | \ + (((uint64_t)(addr)[4]) << 32) | \ + (((uint64_t)(addr)[5]) << 40) | \ + (((uint64_t)(addr)[6]) << 48) | \ + (((uint64_t)(addr)[7]) << 56)) + +#define LE16S(addr) ((int16_t)(LE16((addr)))) +#define LE24S(addr) ((int32_t)(LE24((addr)))) +#define LE32S(addr) ((int32_t)(LE32((addr)))) +#define LE64S(addr) ((int64_t)(LE64((addr)))) + + + +#define USB_LEN_DESC_HDR 0x02U +#define USB_LEN_DEV_DESC 0x12U +#define USB_LEN_CFG_DESC 0x09U +#define USB_LEN_IF_DESC 0x09U +#define USB_LEN_EP_DESC 0x07U +#define USB_LEN_OTG_DESC 0x03U +#define USB_LEN_SETUP_PKT 0x08U + +/* bmRequestType :D7 Data Phase Transfer Direction */ +#define USB_REQ_DIR_MASK 0x80U +#define USB_H2D 0x00U +#define USB_D2H 0x80U + +/* bmRequestType D6..5 Type */ +#define USB_REQ_TYPE_STANDARD 0x00U +#define USB_REQ_TYPE_CLASS 0x20U +#define USB_REQ_TYPE_VENDOR 0x40U +#define USB_REQ_TYPE_RESERVED 0x60U + +/* bmRequestType D4..0 Recipient */ +#define USB_REQ_RECIPIENT_DEVICE 0x00U +#define USB_REQ_RECIPIENT_INTERFACE 0x01U +#define USB_REQ_RECIPIENT_ENDPOINT 0x02U +#define USB_REQ_RECIPIENT_OTHER 0x03U + +/* Table 9-4. Standard Request Codes */ +/* bRequest , Value */ +#define USB_REQ_GET_STATUS 0x00U +#define USB_REQ_CLEAR_FEATURE 0x01U +#define USB_REQ_SET_FEATURE 0x03U +#define USB_REQ_SET_ADDRESS 0x05U +#define USB_REQ_GET_DESCRIPTOR 0x06U +#define USB_REQ_SET_DESCRIPTOR 0x07U +#define USB_REQ_GET_CONFIGURATION 0x08U +#define USB_REQ_SET_CONFIGURATION 0x09U +#define USB_REQ_GET_INTERFACE 0x0AU +#define USB_REQ_SET_INTERFACE 0x0BU +#define USB_REQ_SYNCH_FRAME 0x0CU + +/* Table 9-5. Descriptor Types of USB Specifications */ +#define USB_DESC_TYPE_DEVICE 0x01U +#define USB_DESC_TYPE_CONFIGURATION 0x02U +#define USB_DESC_TYPE_STRING 0x03U +#define USB_DESC_TYPE_INTERFACE 0x04U +#define USB_DESC_TYPE_ENDPOINT 0x05U +#define USB_DESC_TYPE_DEVICE_QUALIFIER 0x06U +#define USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION 0x07U +#define USB_DESC_TYPE_INTERFACE_POWER 0x08U +#define USB_DESC_TYPE_HID 0x21U +#define USB_DESC_TYPE_HID_REPORT 0x22U + + +#define USB_DEVICE_DESC_SIZE 0x12U +#define USB_CONFIGURATION_DESC_SIZE 0x09U +#define USB_HID_DESC_SIZE 0x09U +#define USB_INTERFACE_DESC_SIZE 0x09U +#define USB_ENDPOINT_DESC_SIZE 0x07U + +/* Descriptor Type and Descriptor Index */ +/* Use the following values when calling the function USBH_GetDescriptor */ +#define USB_DESC_DEVICE ((USB_DESC_TYPE_DEVICE << 8) & 0xFF00U) +#define USB_DESC_CONFIGURATION ((USB_DESC_TYPE_CONFIGURATION << 8) & 0xFF00U) +#define USB_DESC_STRING ((USB_DESC_TYPE_STRING << 8) & 0xFF00U) +#define USB_DESC_INTERFACE ((USB_DESC_TYPE_INTERFACE << 8) & 0xFF00U) +#define USB_DESC_ENDPOINT ((USB_DESC_TYPE_INTERFACE << 8) & 0xFF00U) +#define USB_DESC_DEVICE_QUALIFIER ((USB_DESC_TYPE_DEVICE_QUALIFIER << 8) & 0xFF00U) +#define USB_DESC_OTHER_SPEED_CONFIGURATION ((USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION << 8) & 0xFF00U) +#define USB_DESC_INTERFACE_POWER ((USB_DESC_TYPE_INTERFACE_POWER << 8) & 0xFF00U) +#define USB_DESC_HID_REPORT ((USB_DESC_TYPE_HID_REPORT << 8) & 0xFF00U) +#define USB_DESC_HID ((USB_DESC_TYPE_HID << 8) & 0xFF00U) + + +#define USB_EP_TYPE_CTRL 0x00U +#define USB_EP_TYPE_ISOC 0x01U +#define USB_EP_TYPE_BULK 0x02U +#define USB_EP_TYPE_INTR 0x03U + +#define USB_EP_DIR_OUT 0x00U +#define USB_EP_DIR_IN 0x80U +#define USB_EP_DIR_MSK 0x80U + +#ifndef USBH_MAX_PIPES_NBR +#define USBH_MAX_PIPES_NBR 15U +#endif /* USBH_MAX_PIPES_NBR */ + +#define USBH_DEVICE_ADDRESS_DEFAULT 0x00U +#define USBH_DEVICE_ADDRESS 0x01U + +#define USBH_MAX_ERROR_COUNT 0x02U + +#if (USBH_USE_OS == 1U) +#define MSGQUEUE_OBJECTS 0x10U +#endif + + +/** + * @} + */ + + +#define USBH_CONFIGURATION_DESCRIPTOR_SIZE (USB_CONFIGURATION_DESC_SIZE \ + + USB_INTERFACE_DESC_SIZE\ + + (USBH_MAX_NUM_ENDPOINTS * USB_ENDPOINT_DESC_SIZE)) + + +#define CONFIG_DESC_wTOTAL_LENGTH (ConfigurationDescriptorData.ConfigDescfield.\ + ConfigurationDescriptor.wTotalLength) + + +typedef union +{ + uint16_t w; + struct BW + { + uint8_t msb; + uint8_t lsb; + } + bw; +} +uint16_t_uint8_t; + + +typedef union _USB_Setup +{ + uint32_t d8[2]; + + struct _SetupPkt_Struc + { + uint8_t bmRequestType; + uint8_t bRequest; + uint16_t_uint8_t wValue; + uint16_t_uint8_t wIndex; + uint16_t_uint8_t wLength; + } b; +} +USB_Setup_TypeDef; + +typedef struct _DescHeader +{ + uint8_t bLength; + uint8_t bDescriptorType; +} +USBH_DescHeader_t; + +typedef struct _DeviceDescriptor +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bcdUSB; /* USB Specification Number which device complies too */ + uint8_t bDeviceClass; + uint8_t bDeviceSubClass; + uint8_t bDeviceProtocol; + /* If equal to Zero, each interface specifies its own class + code if equal to 0xFF, the class code is vendor specified. + Otherwise field is valid Class Code.*/ + uint8_t bMaxPacketSize; + uint16_t idVendor; /* Vendor ID (Assigned by USB Org) */ + uint16_t idProduct; /* Product ID (Assigned by Manufacturer) */ + uint16_t bcdDevice; /* Device Release Number */ + uint8_t iManufacturer; /* Index of Manufacturer String Descriptor */ + uint8_t iProduct; /* Index of Product String Descriptor */ + uint8_t iSerialNumber; /* Index of Serial Number String Descriptor */ + uint8_t bNumConfigurations; /* Number of Possible Configurations */ +} +USBH_DevDescTypeDef; + +typedef struct _EndpointDescriptor +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bEndpointAddress; /* indicates what endpoint this descriptor is describing */ + uint8_t bmAttributes; /* specifies the transfer type. */ + uint16_t wMaxPacketSize; /* Maximum Packet Size this endpoint is capable of sending or receiving */ + uint8_t bInterval; /* is used to specify the polling interval of certain transfers. */ +} +USBH_EpDescTypeDef; + +typedef struct _InterfaceDescriptor +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bInterfaceNumber; + uint8_t bAlternateSetting; /* Value used to select alternative setting */ + uint8_t bNumEndpoints; /* Number of Endpoints used for this interface */ + uint8_t bInterfaceClass; /* Class Code (Assigned by USB Org) */ + uint8_t bInterfaceSubClass; /* Subclass Code (Assigned by USB Org) */ + uint8_t bInterfaceProtocol; /* Protocol Code */ + uint8_t iInterface; /* Index of String Descriptor Describing this interface */ + USBH_EpDescTypeDef Ep_Desc[USBH_MAX_NUM_ENDPOINTS]; +} +USBH_InterfaceDescTypeDef; + + +typedef struct _ConfigurationDescriptor +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t wTotalLength; /* Total Length of Data Returned */ + uint8_t bNumInterfaces; /* Number of Interfaces */ + uint8_t bConfigurationValue; /* Value to use as an argument to select this configuration*/ + uint8_t iConfiguration; /*Index of String Descriptor Describing this configuration */ + uint8_t bmAttributes; /* D7 Bus Powered , D6 Self Powered, D5 Remote Wakeup , D4..0 Reserved (0)*/ + uint8_t bMaxPower; /*Maximum Power Consumption */ + USBH_InterfaceDescTypeDef Itf_Desc[USBH_MAX_NUM_INTERFACES]; +} +USBH_CfgDescTypeDef; + + +/* Following USB Host status */ +typedef enum +{ + USBH_OK = 0, + USBH_BUSY, + USBH_FAIL, + USBH_NOT_SUPPORTED, + USBH_UNRECOVERED_ERROR, + USBH_ERROR_SPEED_UNKNOWN, +} USBH_StatusTypeDef; + + +/** @defgroup USBH_CORE_Exported_Types + * @{ + */ + +typedef enum +{ + USBH_SPEED_HIGH = 0U, + USBH_SPEED_FULL = 1U, + USBH_SPEED_LOW = 2U, + +} USBH_SpeedTypeDef; + +/* Following states are used for gState */ +typedef enum +{ + HOST_IDLE = 0U, + HOST_DEV_WAIT_FOR_ATTACHMENT, + HOST_DEV_ATTACHED, + HOST_DEV_DISCONNECTED, + HOST_DETECT_DEVICE_SPEED, + HOST_ENUMERATION, + HOST_CLASS_REQUEST, + HOST_INPUT, + HOST_SET_CONFIGURATION, + HOST_SET_WAKEUP_FEATURE, + HOST_CHECK_CLASS, + HOST_CLASS, + HOST_SUSPENDED, + HOST_ABORT_STATE, +} HOST_StateTypeDef; + +/* Following states are used for EnumerationState */ +typedef enum +{ + ENUM_IDLE = 0U, + ENUM_GET_FULL_DEV_DESC, + ENUM_SET_ADDR, + ENUM_GET_CFG_DESC, + ENUM_GET_FULL_CFG_DESC, + ENUM_GET_MFC_STRING_DESC, + ENUM_GET_PRODUCT_STRING_DESC, + ENUM_GET_SERIALNUM_STRING_DESC, +} ENUM_StateTypeDef; + +/* Following states are used for CtrlXferStateMachine */ +typedef enum +{ + CTRL_IDLE = 0U, + CTRL_SETUP, + CTRL_SETUP_WAIT, + CTRL_DATA_IN, + CTRL_DATA_IN_WAIT, + CTRL_DATA_OUT, + CTRL_DATA_OUT_WAIT, + CTRL_STATUS_IN, + CTRL_STATUS_IN_WAIT, + CTRL_STATUS_OUT, + CTRL_STATUS_OUT_WAIT, + CTRL_ERROR, + CTRL_STALLED, + CTRL_COMPLETE +} CTRL_StateTypeDef; + + +/* Following states are used for RequestState */ +typedef enum +{ + CMD_IDLE = 0U, + CMD_SEND, + CMD_WAIT +} CMD_StateTypeDef; + +typedef enum +{ + USBH_URB_IDLE = 0U, + USBH_URB_DONE, + USBH_URB_NOTREADY, + USBH_URB_NYET, + USBH_URB_ERROR, + USBH_URB_STALL +} USBH_URBStateTypeDef; + +typedef enum +{ + USBH_PORT_EVENT = 1U, + USBH_URB_EVENT, + USBH_CONTROL_EVENT, + USBH_CLASS_EVENT, + USBH_STATE_CHANGED_EVENT, +} +USBH_OSEventTypeDef; + +/* Control request structure */ +typedef struct +{ + uint8_t pipe_in; + uint8_t pipe_out; + uint8_t pipe_size; + uint8_t *buff; + uint16_t length; + uint16_t timer; + USB_Setup_TypeDef setup; + CTRL_StateTypeDef state; + uint8_t errorcount; + +} USBH_CtrlTypeDef; + +/* Attached device structure */ +typedef struct +{ + uint8_t CfgDesc_Raw[USBH_MAX_SIZE_CONFIGURATION]; + uint8_t Data[USBH_MAX_DATA_BUFFER]; + uint8_t address; + uint8_t speed; + uint8_t EnumCnt; + uint8_t RstCnt; + __IO uint8_t is_connected; + __IO uint8_t is_disconnected; + __IO uint8_t is_ReEnumerated; + uint8_t PortEnabled; + uint8_t current_interface; + USBH_DevDescTypeDef DevDesc; + USBH_CfgDescTypeDef CfgDesc; +} USBH_DeviceTypeDef; + +struct _USBH_HandleTypeDef; + +/* USB Host Class structure */ +typedef struct +{ + const char *Name; + uint8_t ClassCode; + USBH_StatusTypeDef(*Init)(struct _USBH_HandleTypeDef *phost); + USBH_StatusTypeDef(*DeInit)(struct _USBH_HandleTypeDef *phost); + USBH_StatusTypeDef(*Requests)(struct _USBH_HandleTypeDef *phost); + USBH_StatusTypeDef(*BgndProcess)(struct _USBH_HandleTypeDef *phost); + USBH_StatusTypeDef(*SOFProcess)(struct _USBH_HandleTypeDef *phost); + void *pData; +} USBH_ClassTypeDef; + +/* USB Host handle structure */ +typedef struct _USBH_HandleTypeDef +{ + __IO HOST_StateTypeDef gState; /* Host State Machine Value */ + ENUM_StateTypeDef EnumState; /* Enumeration state Machine */ + CMD_StateTypeDef RequestState; + USBH_CtrlTypeDef Control; + USBH_DeviceTypeDef device; + USBH_ClassTypeDef *pClass[USBH_MAX_NUM_SUPPORTED_CLASS]; + USBH_ClassTypeDef *pActiveClass; + uint32_t ClassNumber; + uint32_t Pipes[16]; + __IO uint32_t Timer; + uint32_t Timeout; + uint8_t id; + void *pData; + void (* pUser)(struct _USBH_HandleTypeDef *pHandle, uint8_t id); + +#if (USBH_USE_OS == 1U) +#if osCMSIS < 0x20000 + osMessageQId os_event; + osThreadId thread; +#else + osMessageQueueId_t os_event; + osThreadId_t thread; +#endif + uint32_t os_msg; +#endif + +} USBH_HandleTypeDef; + + +#if defined ( __GNUC__ ) +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ +#ifndef __packed +#define __packed __attribute__((__packed__)) +#endif /* __packed */ +#endif /* __GNUC__ */ + +#ifdef __cplusplus +} +#endif + +#endif /* USBH_DEF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_ioreq.h b/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_ioreq.h new file mode 100644 index 0000000..8c13a20 --- /dev/null +++ b/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_ioreq.h @@ -0,0 +1,160 @@ +/** + ****************************************************************************** + * @file usbh_ioreq.h + * @author MCD Application Team + * @brief Header file for usbh_ioreq.c + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2015 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ + +/* Define to prevent recursive ----------------------------------------------*/ +#ifndef __USBH_IOREQ_H +#define __USBH_IOREQ_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "usbh_conf.h" +#include "usbh_core.h" + +/** @addtogroup USBH_LIB + * @{ + */ + +/** @addtogroup USBH_LIB_CORE +* @{ +*/ + +/** @defgroup USBH_IOREQ + * @brief This file is the header file for usbh_ioreq.c + * @{ + */ + + +/** @defgroup USBH_IOREQ_Exported_Defines + * @{ + */ + +#define USBH_PID_SETUP 0U +#define USBH_PID_DATA 1U + +#define USBH_EP_CONTROL 0U +#define USBH_EP_ISO 1U +#define USBH_EP_BULK 2U +#define USBH_EP_INTERRUPT 3U + +#define USBH_SETUP_PKT_SIZE 8U +/** + * @} + */ + + +/** @defgroup USBH_IOREQ_Exported_Types + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBH_IOREQ_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup USBH_IOREQ_Exported_Variables + * @{ + */ +/** + * @} + */ + +/** @defgroup USBH_IOREQ_Exported_FunctionsPrototype + * @{ + */ +USBH_StatusTypeDef USBH_CtlSendSetup(USBH_HandleTypeDef *phost, + uint8_t *buff, + uint8_t pipe_num); + +USBH_StatusTypeDef USBH_CtlSendData(USBH_HandleTypeDef *phost, + uint8_t *buff, + uint16_t length, + uint8_t pipe_num, + uint8_t do_ping); + +USBH_StatusTypeDef USBH_CtlReceiveData(USBH_HandleTypeDef *phost, + uint8_t *buff, + uint16_t length, + uint8_t pipe_num); + +USBH_StatusTypeDef USBH_BulkReceiveData(USBH_HandleTypeDef *phost, + uint8_t *buff, + uint16_t length, + uint8_t pipe_num); + +USBH_StatusTypeDef USBH_BulkSendData(USBH_HandleTypeDef *phost, + uint8_t *buff, + uint16_t length, + uint8_t pipe_num, + uint8_t do_ping); + +USBH_StatusTypeDef USBH_InterruptReceiveData(USBH_HandleTypeDef *phost, + uint8_t *buff, + uint8_t length, + uint8_t pipe_num); + +USBH_StatusTypeDef USBH_InterruptSendData(USBH_HandleTypeDef *phost, + uint8_t *buff, + uint8_t length, + uint8_t pipe_num); + + +USBH_StatusTypeDef USBH_IsocReceiveData(USBH_HandleTypeDef *phost, + uint8_t *buff, + uint32_t length, + uint8_t pipe_num); + + +USBH_StatusTypeDef USBH_IsocSendData(USBH_HandleTypeDef *phost, + uint8_t *buff, + uint32_t length, + uint8_t pipe_num); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USBH_IOREQ_H */ + +/** + * @} + */ + +/** + * @} + */ + +/** +* @} +*/ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + + diff --git a/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_pipes.h b/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_pipes.h new file mode 100644 index 0000000..ed2247e --- /dev/null +++ b/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_pipes.h @@ -0,0 +1,123 @@ +/** + ****************************************************************************** + * @file usbh_pipes.h + * @author MCD Application Team + * @brief Header file for usbh_pipes.c + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2015 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ + +/* Define to prevent recursive ----------------------------------------------*/ +#ifndef __USBH_PIPES_H +#define __USBH_PIPES_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "usbh_core.h" + +/** @addtogroup USBH_LIB + * @{ + */ + +/** @addtogroup USBH_LIB_CORE +* @{ +*/ + +/** @defgroup USBH_PIPES + * @brief This file is the header file for usbh_pipes.c + * @{ + */ + +/** @defgroup USBH_PIPES_Exported_Defines + * @{ + */ +/** + * @} + */ + +/** @defgroup USBH_PIPES_Exported_Types + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBH_PIPES_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup USBH_PIPES_Exported_Variables + * @{ + */ +/** + * @} + */ + +/** @defgroup USBH_PIPES_Exported_FunctionsPrototype + * @{ + */ + +USBH_StatusTypeDef USBH_OpenPipe(USBH_HandleTypeDef *phost, + uint8_t pipe_num, + uint8_t epnum, + uint8_t dev_address, + uint8_t speed, + uint8_t ep_type, + uint16_t mps); + +USBH_StatusTypeDef USBH_ClosePipe(USBH_HandleTypeDef *phost, + uint8_t pipe_num); + +uint8_t USBH_AllocPipe(USBH_HandleTypeDef *phost, + uint8_t ep_addr); + +USBH_StatusTypeDef USBH_FreePipe(USBH_HandleTypeDef *phost, + uint8_t idx); + + + + +/** + * @} + */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __USBH_PIPES_H */ + + +/** + * @} + */ + +/** + * @} + */ + +/** +* @} +*/ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + + diff --git a/Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_core.c b/Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_core.c new file mode 100644 index 0000000..76874c4 --- /dev/null +++ b/Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_core.c @@ -0,0 +1,1370 @@ +/** + ****************************************************************************** + * @file usbh_core.c + * @author MCD Application Team + * @brief This file implements the functions for the core state machine process + * the enumeration and the control transfer process + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2015 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbh_core.h" + + +/** @addtogroup USBH_LIB + * @{ + */ + +/** @addtogroup USBH_LIB_CORE + * @{ + */ + +/** @defgroup USBH_CORE + * @brief This file handles the basic enumeration when a device is connected + * to the host. + * @{ + */ + + +/** @defgroup USBH_CORE_Private_Defines + * @{ + */ +#define USBH_ADDRESS_DEFAULT 0x00U +#define USBH_ADDRESS_ASSIGNED 0x01U +#define USBH_MPS_DEFAULT 0x40U +/** + * @} + */ + +/** @defgroup USBH_CORE_Private_Macros + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBH_CORE_Private_Variables + * @{ + */ +#if (USBH_USE_OS == 1U) +#if (osCMSIS >= 0x20000U) +osThreadAttr_t USBH_Thread_Atrr; +#endif +#endif + + +/** + * @} + */ + + +/** @defgroup USBH_CORE_Private_Functions + * @{ + */ +static USBH_StatusTypeDef USBH_HandleEnum(USBH_HandleTypeDef *phost); +static void USBH_HandleSof(USBH_HandleTypeDef *phost); +static USBH_StatusTypeDef DeInitStateMachine(USBH_HandleTypeDef *phost); + +#if (USBH_USE_OS == 1U) +#if (osCMSIS < 0x20000U) +static void USBH_Process_OS(void const *argument); +#else +static void USBH_Process_OS(void *argument); +#endif +#endif + + +/** + * @brief HCD_Init + * Initialize the HOST Core. + * @param phost: Host Handle + * @param pUsrFunc: User Callback + * @retval USBH Status + */ +USBH_StatusTypeDef USBH_Init(USBH_HandleTypeDef *phost, + void (*pUsrFunc)(USBH_HandleTypeDef *phost, + uint8_t id), uint8_t id) +{ + /* Check whether the USB Host handle is valid */ + if (phost == NULL) + { + USBH_ErrLog("Invalid Host handle"); + return USBH_FAIL; + } + + /* Set DRiver ID */ + phost->id = id; + + /* Unlink class*/ + phost->pActiveClass = NULL; + phost->ClassNumber = 0U; + + /* Restore default states and prepare EP0 */ + DeInitStateMachine(phost); + + /* Restore default Device connection states */ + phost->device.PortEnabled = 0U; + phost->device.is_connected = 0U; + phost->device.is_disconnected = 0U; + phost->device.is_ReEnumerated = 0U; + + /* Assign User process */ + if (pUsrFunc != NULL) + { + phost->pUser = pUsrFunc; + } + +#if (USBH_USE_OS == 1U) +#if (osCMSIS < 0x20000U) + + /* Create USB Host Queue */ + osMessageQDef(USBH_Queue, MSGQUEUE_OBJECTS, uint16_t); + phost->os_event = osMessageCreate(osMessageQ(USBH_Queue), NULL); + + /* Create USB Host Task */ +#if defined (USBH_PROCESS_STACK_SIZE) + osThreadDef(USBH_Thread, USBH_Process_OS, USBH_PROCESS_PRIO, 0U, USBH_PROCESS_STACK_SIZE); +#else + osThreadDef(USBH_Thread, USBH_Process_OS, USBH_PROCESS_PRIO, 0U, 8U * configMINIMAL_STACK_SIZE); +#endif /* defined (USBH_PROCESS_STACK_SIZE) */ + + phost->thread = osThreadCreate(osThread(USBH_Thread), phost); + +#else + + /* Create USB Host Queue */ + phost->os_event = osMessageQueueNew(MSGQUEUE_OBJECTS, sizeof(uint32_t), NULL); + + /* Create USB Host Task */ + USBH_Thread_Atrr.name = "USBH_Queue"; + +#if defined (USBH_PROCESS_STACK_SIZE) + USBH_Thread_Atrr.stack_size = USBH_PROCESS_STACK_SIZE; +#else + USBH_Thread_Atrr.stack_size = (8U * configMINIMAL_STACK_SIZE); +#endif /* defined (USBH_PROCESS_STACK_SIZE) */ + + USBH_Thread_Atrr.priority = USBH_PROCESS_PRIO; + phost->thread = osThreadNew(USBH_Process_OS, phost, &USBH_Thread_Atrr); + +#endif /* (osCMSIS < 0x20000U) */ +#endif /* (USBH_USE_OS == 1U) */ + + /* Initialize low level driver */ + USBH_LL_Init(phost); + + return USBH_OK; +} + + +/** + * @brief HCD_Init + * De-Initialize the Host portion of the driver. + * @param phost: Host Handle + * @retval USBH Status + */ +USBH_StatusTypeDef USBH_DeInit(USBH_HandleTypeDef *phost) +{ + DeInitStateMachine(phost); + + /* Restore default Device connection states */ + phost->device.PortEnabled = 0U; + phost->device.is_connected = 0U; + phost->device.is_disconnected = 0U; + phost->device.is_ReEnumerated = 0U; + phost->device.RstCnt = 0U; + phost->device.EnumCnt = 0U; + + if (phost->pData != NULL) + { + USBH_LL_Stop(phost); + } + + return USBH_OK; +} + + +/** + * @brief DeInitStateMachine + * De-Initialize the Host state machine. + * @param phost: Host Handle + * @retval USBH Status + */ +static USBH_StatusTypeDef DeInitStateMachine(USBH_HandleTypeDef *phost) +{ + uint32_t i = 0U; + + /* Clear Pipes flags*/ + for (i = 0U; i < USBH_MAX_PIPES_NBR; i++) + { + phost->Pipes[i] = 0U; + } + + for (i = 0U; i < USBH_MAX_DATA_BUFFER; i++) + { + phost->device.Data[i] = 0U; + } + + phost->gState = HOST_IDLE; + phost->EnumState = ENUM_IDLE; + phost->RequestState = CMD_SEND; + phost->Timer = 0U; + + phost->Control.state = CTRL_SETUP; + phost->Control.pipe_size = USBH_MPS_DEFAULT; + phost->Control.errorcount = 0U; + + phost->device.address = USBH_ADDRESS_DEFAULT; + phost->device.speed = USBH_SPEED_FULL; + phost->device.RstCnt = 0U; + phost->device.EnumCnt = 0U; + + return USBH_OK; +} + + +/** + * @brief USBH_RegisterClass + * Link class driver to Host Core. + * @param phost : Host Handle + * @param pclass: Class handle + * @retval USBH Status + */ +USBH_StatusTypeDef USBH_RegisterClass(USBH_HandleTypeDef *phost, USBH_ClassTypeDef *pclass) +{ + USBH_StatusTypeDef status = USBH_OK; + + if (pclass != NULL) + { + if (phost->ClassNumber < USBH_MAX_NUM_SUPPORTED_CLASS) + { + /* link the class to the USB Host handle */ + phost->pClass[phost->ClassNumber++] = pclass; + status = USBH_OK; + } + else + { + USBH_ErrLog("Max Class Number reached"); + status = USBH_FAIL; + } + } + else + { + USBH_ErrLog("Invalid Class handle"); + status = USBH_FAIL; + } + + return status; +} + + +/** + * @brief USBH_SelectInterface + * Select current interface. + * @param phost: Host Handle + * @param interface: Interface number + * @retval USBH Status + */ +USBH_StatusTypeDef USBH_SelectInterface(USBH_HandleTypeDef *phost, uint8_t interface) +{ + USBH_StatusTypeDef status = USBH_OK; + + if (interface < phost->device.CfgDesc.bNumInterfaces) + { + phost->device.current_interface = interface; + USBH_UsrLog("Switching to Interface (#%d)", interface); + USBH_UsrLog("Class : %xh", phost->device.CfgDesc.Itf_Desc[interface].bInterfaceClass); + USBH_UsrLog("SubClass : %xh", phost->device.CfgDesc.Itf_Desc[interface].bInterfaceSubClass); + USBH_UsrLog("Protocol : %xh", phost->device.CfgDesc.Itf_Desc[interface].bInterfaceProtocol); + } + else + { + USBH_ErrLog("Cannot Select This Interface."); + status = USBH_FAIL; + } + + return status; +} + + +/** + * @brief USBH_GetActiveClass + * Return Device Class. + * @param phost: Host Handle + * @param interface: Interface index + * @retval Class Code + */ +uint8_t USBH_GetActiveClass(USBH_HandleTypeDef *phost) +{ + return (phost->device.CfgDesc.Itf_Desc[0].bInterfaceClass); +} + + +/** + * @brief USBH_FindInterface + * Find the interface index for a specific class. + * @param phost: Host Handle + * @param Class: Class code + * @param SubClass: SubClass code + * @param Protocol: Protocol code + * @retval interface index in the configuration structure + * @note : (1)interface index 0xFF means interface index not found + */ +uint8_t USBH_FindInterface(USBH_HandleTypeDef *phost, uint8_t Class, uint8_t SubClass, uint8_t Protocol) +{ + USBH_InterfaceDescTypeDef *pif; + USBH_CfgDescTypeDef *pcfg; + uint8_t if_ix = 0U; + + pif = (USBH_InterfaceDescTypeDef *)0; + pcfg = &phost->device.CfgDesc; + + while (if_ix < USBH_MAX_NUM_INTERFACES) + { + pif = &pcfg->Itf_Desc[if_ix]; + if (((pif->bInterfaceClass == Class) || (Class == 0xFFU)) && + ((pif->bInterfaceSubClass == SubClass) || (SubClass == 0xFFU)) && + ((pif->bInterfaceProtocol == Protocol) || (Protocol == 0xFFU))) + { + return if_ix; + } + if_ix++; + } + return 0xFFU; +} + + +/** + * @brief USBH_FindInterfaceIndex + * Find the interface index for a specific class interface and alternate setting number. + * @param phost: Host Handle + * @param interface_number: interface number + * @param alt_settings : alternate setting number + * @retval interface index in the configuration structure + * @note : (1)interface index 0xFF means interface index not found + */ +uint8_t USBH_FindInterfaceIndex(USBH_HandleTypeDef *phost, uint8_t interface_number, uint8_t alt_settings) +{ + USBH_InterfaceDescTypeDef *pif; + USBH_CfgDescTypeDef *pcfg; + uint8_t if_ix = 0U; + + pif = (USBH_InterfaceDescTypeDef *)0; + pcfg = &phost->device.CfgDesc; + + while (if_ix < USBH_MAX_NUM_INTERFACES) + { + pif = &pcfg->Itf_Desc[if_ix]; + if ((pif->bInterfaceNumber == interface_number) && (pif->bAlternateSetting == alt_settings)) + { + return if_ix; + } + if_ix++; + } + return 0xFFU; +} + + +/** + * @brief USBH_Start + * Start the USB Host Core. + * @param phost: Host Handle + * @retval USBH Status + */ +USBH_StatusTypeDef USBH_Start(USBH_HandleTypeDef *phost) +{ + /* Start the low level driver */ + USBH_LL_Start(phost); + + /* Activate VBUS on the port */ + USBH_LL_DriverVBUS(phost, TRUE); + + return USBH_OK; +} + + +/** + * @brief USBH_Stop + * Stop the USB Host Core. + * @param phost: Host Handle + * @retval USBH Status + */ +USBH_StatusTypeDef USBH_Stop(USBH_HandleTypeDef *phost) +{ + /* DeActivate VBUS on the port */ + USBH_LL_DriverVBUS(phost, FALSE); + + /* Stop and cleanup the low level driver */ + USBH_LL_Stop(phost); + + /* Free Control Pipes */ + USBH_FreePipe(phost, phost->Control.pipe_in); + USBH_FreePipe(phost, phost->Control.pipe_out); + + return USBH_OK; +} + + +/** + * @brief HCD_ReEnumerate + * Perform a new Enumeration phase. + * @param phost: Host Handle + * @retval USBH Status + */ +USBH_StatusTypeDef USBH_ReEnumerate(USBH_HandleTypeDef *phost) +{ + if (USBH_IsPortEnabled(phost)) + { + phost->device.is_ReEnumerated = 1U; + + /* Stop Host */ + USBH_Stop(phost); + + phost->device.is_disconnected = 1U; + } + +#if (USBH_USE_OS == 1U) + phost->os_msg = (uint32_t)USBH_PORT_EVENT; +#if (osCMSIS < 0x20000U) + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + + return USBH_OK; +} + + +/** + * @brief USBH_Process + * Background process of the USB Core. + * @param phost: Host Handle + * @retval USBH Status + */ +USBH_StatusTypeDef USBH_Process(USBH_HandleTypeDef *phost) +{ + __IO USBH_StatusTypeDef status = USBH_FAIL; + uint8_t idx = 0U; + + /* check for Host pending port disconnect event */ + if (phost->device.is_disconnected == 1U) + { + phost->gState = HOST_DEV_DISCONNECTED; + } + + switch (phost->gState) + { + case HOST_IDLE : + + if (phost->device.is_connected) + { + USBH_UsrLog("USB Device Connected"); + + /* Wait for 200 ms after connection */ + phost->gState = HOST_DEV_WAIT_FOR_ATTACHMENT; + USBH_Delay(200U); + USBH_LL_ResetPort(phost); + + /* Make sure to start with Default address */ + phost->device.address = USBH_ADDRESS_DEFAULT; + phost->Timeout = 0U; + +#if (USBH_USE_OS == 1U) + phost->os_msg = (uint32_t)USBH_PORT_EVENT; +#if (osCMSIS < 0x20000U) + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + } + break; + + case HOST_DEV_WAIT_FOR_ATTACHMENT: /* Wait for Port Enabled */ + + if (phost->device.PortEnabled == 1U) + { + USBH_UsrLog("USB Device Reset Completed"); + phost->device.RstCnt = 0U; + phost->gState = HOST_DEV_ATTACHED; + } + else + { + if (phost->Timeout > USBH_DEV_RESET_TIMEOUT) + { + phost->device.RstCnt++; + if (phost->device.RstCnt > 3U) + { + /* Buggy Device can't complete reset */ + USBH_UsrLog("USB Reset Failed, Please unplug the Device."); + phost->gState = HOST_ABORT_STATE; + } + else + { + phost->gState = HOST_IDLE; + } + } + else + { + phost->Timeout += 10U; + USBH_Delay(10U); + } + } +#if (USBH_USE_OS == 1U) + phost->os_msg = (uint32_t)USBH_PORT_EVENT; +#if (osCMSIS < 0x20000U) + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + break; + + case HOST_DEV_ATTACHED : + + if (phost->pUser != NULL) + { + phost->pUser(phost, HOST_USER_CONNECTION); + } + + /* Wait for 100 ms after Reset */ + USBH_Delay(100U); + + phost->device.speed = USBH_LL_GetSpeed(phost); + + phost->gState = HOST_ENUMERATION; + + phost->Control.pipe_out = USBH_AllocPipe(phost, 0x00U); + phost->Control.pipe_in = USBH_AllocPipe(phost, 0x80U); + + /* Open Control pipes */ + USBH_OpenPipe(phost, phost->Control.pipe_in, 0x80U, + phost->device.address, phost->device.speed, + USBH_EP_CONTROL, (uint16_t)phost->Control.pipe_size); + + /* Open Control pipes */ + USBH_OpenPipe(phost, phost->Control.pipe_out, 0x00U, + phost->device.address, phost->device.speed, + USBH_EP_CONTROL, (uint16_t)phost->Control.pipe_size); + +#if (USBH_USE_OS == 1U) + phost->os_msg = (uint32_t)USBH_PORT_EVENT; +#if (osCMSIS < 0x20000U) + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + break; + + case HOST_ENUMERATION: + /* Check for enumeration status */ + status = USBH_HandleEnum(phost); + if (status == USBH_OK) + { + /* The function shall return USBH_OK when full enumeration is complete */ + USBH_UsrLog("Enumeration done."); + + phost->device.current_interface = 0U; + + if (phost->device.DevDesc.bNumConfigurations == 1U) + { + USBH_UsrLog("This device has only 1 configuration."); + phost->gState = HOST_SET_CONFIGURATION; + } + else + { + phost->gState = HOST_INPUT; + } +#if (USBH_USE_OS == 1U) + phost->os_msg = (uint32_t)USBH_STATE_CHANGED_EVENT; +#if (osCMSIS < 0x20000U) + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + } + break; + + case HOST_INPUT: + { + /* user callback for end of device basic enumeration */ + if (phost->pUser != NULL) + { + phost->pUser(phost, HOST_USER_SELECT_CONFIGURATION); + phost->gState = HOST_SET_CONFIGURATION; + +#if (USBH_USE_OS == 1U) + phost->os_msg = (uint32_t)USBH_STATE_CHANGED_EVENT; +#if (osCMSIS < 0x20000U) + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + } + } + break; + + case HOST_SET_CONFIGURATION: + /* set configuration */ + if (USBH_SetCfg(phost, (uint16_t)phost->device.CfgDesc.bConfigurationValue) == USBH_OK) + { + phost->gState = HOST_SET_WAKEUP_FEATURE; + USBH_UsrLog("Default configuration set."); + } + +#if (USBH_USE_OS == 1U) + phost->os_msg = (uint32_t)USBH_PORT_EVENT; +#if (osCMSIS < 0x20000U) + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + break; + + case HOST_SET_WAKEUP_FEATURE: + + if ((phost->device.CfgDesc.bmAttributes) & (1U << 5)) + { + if (USBH_SetFeature(phost, FEATURE_SELECTOR_REMOTEWAKEUP) == USBH_OK) + { + USBH_UsrLog("Device remote wakeup enabled"); + phost->gState = HOST_CHECK_CLASS; + } + } + else + { + phost->gState = HOST_CHECK_CLASS; + } + +#if (USBH_USE_OS == 1U) + phost->os_msg = (uint32_t)USBH_PORT_EVENT; +#if (osCMSIS < 0x20000U) + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + break; + + case HOST_CHECK_CLASS: + + if (phost->ClassNumber == 0U) + { + USBH_UsrLog("No Class has been registered."); + } + else + { + phost->pActiveClass = NULL; + + for (idx = 0U; idx < USBH_MAX_NUM_SUPPORTED_CLASS; idx++) + { + if (phost->pClass[idx]->ClassCode == phost->device.CfgDesc.Itf_Desc[0].bInterfaceClass) + { + phost->pActiveClass = phost->pClass[idx]; + break; + } + } + + if (phost->pActiveClass != NULL) + { + if (phost->pActiveClass->Init(phost) == USBH_OK) + { + phost->gState = HOST_CLASS_REQUEST; + USBH_UsrLog("%s class started.", phost->pActiveClass->Name); + + /* Inform user that a class has been activated */ + phost->pUser(phost, HOST_USER_CLASS_SELECTED); + } + else + { + phost->gState = HOST_ABORT_STATE; + USBH_UsrLog("Device not supporting %s class.", phost->pActiveClass->Name); + } + } + else + { + phost->gState = HOST_ABORT_STATE; + USBH_UsrLog("No registered class for this device."); + } + } + +#if (USBH_USE_OS == 1U) + phost->os_msg = (uint32_t)USBH_STATE_CHANGED_EVENT; +#if (osCMSIS < 0x20000U) + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + break; + + case HOST_CLASS_REQUEST: + /* process class standard control requests state machine */ + if (phost->pActiveClass != NULL) + { + status = phost->pActiveClass->Requests(phost); + + if (status == USBH_OK) + { + phost->gState = HOST_CLASS; + } + else if (status == USBH_FAIL) + { + phost->gState = HOST_ABORT_STATE; + USBH_ErrLog("Device not responding Please Unplug."); + } + else + { + /* .. */ + } + } + else + { + phost->gState = HOST_ABORT_STATE; + USBH_ErrLog("Invalid Class Driver."); + } +#if (USBH_USE_OS == 1U) + phost->os_msg = (uint32_t)USBH_STATE_CHANGED_EVENT; +#if (osCMSIS < 0x20000U) + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + break; + + case HOST_CLASS: + /* process class state machine */ + if (phost->pActiveClass != NULL) + { + phost->pActiveClass->BgndProcess(phost); + } + break; + + case HOST_DEV_DISCONNECTED : + phost->device.is_disconnected = 0U; + + DeInitStateMachine(phost); + + /* Re-Initilaize Host for new Enumeration */ + if (phost->pActiveClass != NULL) + { + phost->pActiveClass->DeInit(phost); + phost->pActiveClass = NULL; + } + + if (phost->pUser != NULL) + { + phost->pUser(phost, HOST_USER_DISCONNECTION); + } + USBH_UsrLog("USB Device disconnected"); + + if (phost->device.is_ReEnumerated == 1U) + { + phost->device.is_ReEnumerated = 0U; + + /* Start the host and re-enable Vbus */ + USBH_Start(phost); + } + else + { + /* Device Disconnection Completed, start USB Driver */ + USBH_LL_Start(phost); + } + +#if (USBH_USE_OS == 1U) + phost->os_msg = (uint32_t)USBH_PORT_EVENT; +#if (osCMSIS < 0x20000U) + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + break; + + case HOST_ABORT_STATE: + default : + break; + } + return USBH_OK; +} + + +/** + * @brief USBH_HandleEnum + * This function includes the complete enumeration process + * @param phost: Host Handle + * @retval USBH_Status + */ +static USBH_StatusTypeDef USBH_HandleEnum(USBH_HandleTypeDef *phost) +{ + USBH_StatusTypeDef Status = USBH_BUSY; + USBH_StatusTypeDef ReqStatus = USBH_BUSY; + + switch (phost->EnumState) + { + case ENUM_IDLE: + /* Get Device Desc for only 1st 8 bytes : To get EP0 MaxPacketSize */ + ReqStatus = USBH_Get_DevDesc(phost, 8U); + if (ReqStatus == USBH_OK) + { + phost->Control.pipe_size = phost->device.DevDesc.bMaxPacketSize; + + phost->EnumState = ENUM_GET_FULL_DEV_DESC; + + /* modify control channels configuration for MaxPacket size */ + USBH_OpenPipe(phost, phost->Control.pipe_in, 0x80U, phost->device.address, + phost->device.speed, USBH_EP_CONTROL, + (uint16_t)phost->Control.pipe_size); + + /* Open Control pipes */ + USBH_OpenPipe(phost, phost->Control.pipe_out, 0x00U, phost->device.address, + phost->device.speed, USBH_EP_CONTROL, + (uint16_t)phost->Control.pipe_size); + } + else if (ReqStatus == USBH_NOT_SUPPORTED) + { + USBH_ErrLog("Control error: Get Device Descriptor request failed"); + phost->device.EnumCnt++; + if (phost->device.EnumCnt > 3U) + { + /* Buggy Device can't complete get device desc request */ + USBH_UsrLog("Control error, Device not Responding Please unplug the Device."); + phost->gState = HOST_ABORT_STATE; + } + else + { + /* free control pipes */ + USBH_FreePipe(phost, phost->Control.pipe_out); + USBH_FreePipe(phost, phost->Control.pipe_in); + + /* Reset the USB Device */ + phost->gState = HOST_IDLE; + } + } + else + { + /* .. */ + } + break; + + case ENUM_GET_FULL_DEV_DESC: + /* Get FULL Device Desc */ + ReqStatus = USBH_Get_DevDesc(phost, USB_DEVICE_DESC_SIZE); + if (ReqStatus == USBH_OK) + { + USBH_UsrLog("PID: %xh", phost->device.DevDesc.idProduct); + USBH_UsrLog("VID: %xh", phost->device.DevDesc.idVendor); + + phost->EnumState = ENUM_SET_ADDR; + } + else if (ReqStatus == USBH_NOT_SUPPORTED) + { + USBH_ErrLog("Control error: Get Full Device Descriptor request failed"); + phost->device.EnumCnt++; + if (phost->device.EnumCnt > 3U) + { + /* Buggy Device can't complete get device desc request */ + USBH_UsrLog("Control error, Device not Responding Please unplug the Device."); + phost->gState = HOST_ABORT_STATE; + } + else + { + /* Free control pipes */ + USBH_FreePipe(phost, phost->Control.pipe_out); + USBH_FreePipe(phost, phost->Control.pipe_in); + + /* Reset the USB Device */ + phost->EnumState = ENUM_IDLE; + phost->gState = HOST_IDLE; + } + } + else + { + /* .. */ + } + break; + + case ENUM_SET_ADDR: + /* set address */ + ReqStatus = USBH_SetAddress(phost, USBH_DEVICE_ADDRESS); + if (ReqStatus == USBH_OK) + { + USBH_Delay(2U); + phost->device.address = USBH_DEVICE_ADDRESS; + + /* user callback for device address assigned */ + USBH_UsrLog("Address (#%d) assigned.", phost->device.address); + phost->EnumState = ENUM_GET_CFG_DESC; + + /* modify control channels to update device address */ + USBH_OpenPipe(phost, phost->Control.pipe_in, 0x80U, phost->device.address, + phost->device.speed, USBH_EP_CONTROL, + (uint16_t)phost->Control.pipe_size); + + /* Open Control pipes */ + USBH_OpenPipe(phost, phost->Control.pipe_out, 0x00U, phost->device.address, + phost->device.speed, USBH_EP_CONTROL, + (uint16_t)phost->Control.pipe_size); + } + else if (ReqStatus == USBH_NOT_SUPPORTED) + { + USBH_ErrLog("Control error: Device Set Address request failed"); + + /* Buggy Device can't complete get device desc request */ + USBH_UsrLog("Control error, Device not Responding Please unplug the Device."); + phost->gState = HOST_ABORT_STATE; + phost->EnumState = ENUM_IDLE; + } + else + { + /* .. */ + } + break; + + case ENUM_GET_CFG_DESC: + /* get standard configuration descriptor */ + ReqStatus = USBH_Get_CfgDesc(phost, USB_CONFIGURATION_DESC_SIZE); + if (ReqStatus == USBH_OK) + { + phost->EnumState = ENUM_GET_FULL_CFG_DESC; + } + else if (ReqStatus == USBH_NOT_SUPPORTED) + { + USBH_ErrLog("Control error: Get Device configuration descriptor request failed"); + phost->device.EnumCnt++; + if (phost->device.EnumCnt > 3U) + { + /* Buggy Device can't complete get device desc request */ + USBH_UsrLog("Control error, Device not Responding Please unplug the Device."); + phost->gState = HOST_ABORT_STATE; + } + else + { + /* Free control pipes */ + USBH_FreePipe(phost, phost->Control.pipe_out); + USBH_FreePipe(phost, phost->Control.pipe_in); + + /* Reset the USB Device */ + phost->EnumState = ENUM_IDLE; + phost->gState = HOST_IDLE; + } + } + else + { + /* .. */ + } + break; + + case ENUM_GET_FULL_CFG_DESC: + /* get FULL config descriptor (config, interface, endpoints) */ + ReqStatus = USBH_Get_CfgDesc(phost, phost->device.CfgDesc.wTotalLength); + if (ReqStatus == USBH_OK) + { + phost->EnumState = ENUM_GET_MFC_STRING_DESC; + } + else if (ReqStatus == USBH_NOT_SUPPORTED) + { + USBH_ErrLog("Control error: Get Device configuration descriptor request failed"); + phost->device.EnumCnt++; + if (phost->device.EnumCnt > 3U) + { + /* Buggy Device can't complete get device desc request */ + USBH_UsrLog("Control error, Device not Responding Please unplug the Device."); + phost->gState = HOST_ABORT_STATE; + } + else + { + /* Free control pipes */ + USBH_FreePipe(phost, phost->Control.pipe_out); + USBH_FreePipe(phost, phost->Control.pipe_in); + + /* Reset the USB Device */ + phost->EnumState = ENUM_IDLE; + phost->gState = HOST_IDLE; + } + } + else + { + /* .. */ + } + break; + + case ENUM_GET_MFC_STRING_DESC: + if (phost->device.DevDesc.iManufacturer != 0U) + { + /* Check that Manufacturer String is available */ + ReqStatus = USBH_Get_StringDesc(phost, phost->device.DevDesc.iManufacturer, + phost->device.Data, 0xFFU); + if (ReqStatus == USBH_OK) + { + /* User callback for Manufacturing string */ + USBH_UsrLog("Manufacturer : %s", (char *)(void *)phost->device.Data); + phost->EnumState = ENUM_GET_PRODUCT_STRING_DESC; + +#if (USBH_USE_OS == 1U) + phost->os_msg = (uint32_t)USBH_STATE_CHANGED_EVENT; +#if (osCMSIS < 0x20000U) + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + } + else if (ReqStatus == USBH_NOT_SUPPORTED) + { + USBH_UsrLog("Manufacturer : N/A"); + phost->EnumState = ENUM_GET_PRODUCT_STRING_DESC; + +#if (USBH_USE_OS == 1U) + phost->os_msg = (uint32_t)USBH_STATE_CHANGED_EVENT; +#if (osCMSIS < 0x20000U) + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + } + else + { + /* .. */ + } + } + else + { + USBH_UsrLog("Manufacturer : N/A"); + phost->EnumState = ENUM_GET_PRODUCT_STRING_DESC; + +#if (USBH_USE_OS == 1U) + phost->os_msg = (uint32_t)USBH_STATE_CHANGED_EVENT; +#if (osCMSIS < 0x20000U) + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + } + break; + + case ENUM_GET_PRODUCT_STRING_DESC: + if (phost->device.DevDesc.iProduct != 0U) + { + /* Check that Product string is available */ + ReqStatus = USBH_Get_StringDesc(phost, phost->device.DevDesc.iProduct, + phost->device.Data, 0xFFU); + if (ReqStatus == USBH_OK) + { + /* User callback for Product string */ + USBH_UsrLog("Product : %s", (char *)(void *)phost->device.Data); + phost->EnumState = ENUM_GET_SERIALNUM_STRING_DESC; + } + else if (ReqStatus == USBH_NOT_SUPPORTED) + { + USBH_UsrLog("Product : N/A"); + phost->EnumState = ENUM_GET_SERIALNUM_STRING_DESC; + +#if (USBH_USE_OS == 1U) + phost->os_msg = (uint32_t)USBH_STATE_CHANGED_EVENT; +#if (osCMSIS < 0x20000U) + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + } + else + { + /* .. */ + } + } + else + { + USBH_UsrLog("Product : N/A"); + phost->EnumState = ENUM_GET_SERIALNUM_STRING_DESC; + +#if (USBH_USE_OS == 1U) + phost->os_msg = (uint32_t)USBH_STATE_CHANGED_EVENT; +#if (osCMSIS < 0x20000U) + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + } + break; + + case ENUM_GET_SERIALNUM_STRING_DESC: + if (phost->device.DevDesc.iSerialNumber != 0U) + { + /* Check that Serial number string is available */ + ReqStatus = USBH_Get_StringDesc(phost, phost->device.DevDesc.iSerialNumber, + phost->device.Data, 0xFFU); + if (ReqStatus == USBH_OK) + { + /* User callback for Serial number string */ + USBH_UsrLog("Serial Number : %s", (char *)(void *)phost->device.Data); + Status = USBH_OK; + } + else if (ReqStatus == USBH_NOT_SUPPORTED) + { + USBH_UsrLog("Serial Number : N/A"); + Status = USBH_OK; + } + else + { + /* .. */ + } + } + else + { + USBH_UsrLog("Serial Number : N/A"); + Status = USBH_OK; + } + break; + + default: + break; + } + return Status; +} + + +/** + * @brief USBH_LL_SetTimer + * Set the initial Host Timer tick + * @param phost: Host Handle + * @retval None + */ +void USBH_LL_SetTimer(USBH_HandleTypeDef *phost, uint32_t time) +{ + phost->Timer = time; +} + + +/** + * @brief USBH_LL_IncTimer + * Increment Host Timer tick + * @param phost: Host Handle + * @retval None + */ +void USBH_LL_IncTimer(USBH_HandleTypeDef *phost) +{ + phost->Timer++; + USBH_HandleSof(phost); +} + + +/** + * @brief USBH_HandleSof + * Call SOF process + * @param phost: Host Handle + * @retval None + */ +static void USBH_HandleSof(USBH_HandleTypeDef *phost) +{ + if ((phost->gState == HOST_CLASS) && (phost->pActiveClass != NULL)) + { + phost->pActiveClass->SOFProcess(phost); + } +} + + +/** + * @brief USBH_PortEnabled + * Port Enabled + * @param phost: Host Handle + * @retval None + */ +void USBH_LL_PortEnabled(USBH_HandleTypeDef *phost) +{ + phost->device.PortEnabled = 1U; + +#if (USBH_USE_OS == 1U) + phost->os_msg = (uint32_t)USBH_PORT_EVENT; +#if (osCMSIS < 0x20000U) + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + + return; +} + + +/** + * @brief USBH_LL_PortDisabled + * Port Disabled + * @param phost: Host Handle + * @retval None + */ +void USBH_LL_PortDisabled(USBH_HandleTypeDef *phost) +{ + phost->device.PortEnabled = 0U; + + return; +} + + +/** + * @brief HCD_IsPortEnabled + * Is Port Enabled + * @param phost: Host Handle + * @retval None + */ +uint8_t USBH_IsPortEnabled(USBH_HandleTypeDef *phost) +{ + return (phost->device.PortEnabled); +} + + +/** + * @brief USBH_LL_Connect + * Handle USB Host connexion event + * @param phost: Host Handle + * @retval USBH_Status + */ +USBH_StatusTypeDef USBH_LL_Connect(USBH_HandleTypeDef *phost) +{ + phost->device.is_connected = 1U; + phost->device.is_disconnected = 0U; + phost->device.is_ReEnumerated = 0U; + + +#if (USBH_USE_OS == 1U) + phost->os_msg = (uint32_t)USBH_PORT_EVENT; +#if (osCMSIS < 0x20000U) + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + + return USBH_OK; +} + + +/** + * @brief USBH_LL_Disconnect + * Handle USB Host disconnection event + * @param phost: Host Handle + * @retval USBH_Status + */ +USBH_StatusTypeDef USBH_LL_Disconnect(USBH_HandleTypeDef *phost) +{ + /* update device connection states */ + phost->device.is_disconnected = 1U; + phost->device.is_connected = 0U; + phost->device.PortEnabled = 0U; + + /* Stop Host */ + USBH_LL_Stop(phost); + + /* FRee Control Pipes */ + USBH_FreePipe(phost, phost->Control.pipe_in); + USBH_FreePipe(phost, phost->Control.pipe_out); +#if (USBH_USE_OS == 1U) + phost->os_msg = (uint32_t)USBH_PORT_EVENT; +#if (osCMSIS < 0x20000U) + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + + return USBH_OK; +} + + +#if (USBH_USE_OS == 1U) +/** + * @brief USB Host Thread task + * @param pvParameters not used + * @retval None + */ + +#if (osCMSIS < 0x20000U) +static void USBH_Process_OS(void const *argument) +{ + osEvent event; + + for (;;) + { + event = osMessageGet(((USBH_HandleTypeDef *)argument)->os_event, osWaitForever); + if (event.status == osEventMessage) + { + USBH_Process((USBH_HandleTypeDef *)argument); + } + } +} +#else +static void USBH_Process_OS(void *argument) +{ + osStatus_t status; + + for (;;) + { + status = osMessageQueueGet(((USBH_HandleTypeDef *)argument)->os_event, + &((USBH_HandleTypeDef *)argument)->os_msg, NULL, osWaitForever); + if (status == osOK) + { + USBH_Process((USBH_HandleTypeDef *)argument); + } + } +} +#endif /* (osCMSIS < 0x20000U) */ + + +/** +* @brief USBH_LL_NotifyURBChange +* Notify URB state Change +* @param phost: Host handle +* @retval USBH Status +*/ +USBH_StatusTypeDef USBH_LL_NotifyURBChange(USBH_HandleTypeDef *phost) +{ + phost->os_msg = (uint32_t)USBH_PORT_EVENT; + +#if (osCMSIS < 0x20000U) + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif + + return USBH_OK; +} +#endif +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ctlreq.c b/Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ctlreq.c new file mode 100644 index 0000000..13e777e --- /dev/null +++ b/Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ctlreq.c @@ -0,0 +1,1003 @@ +/** + ****************************************************************************** + * @file usbh_ctlreq.c + * @author MCD Application Team + * @brief This file implements the control requests for device enumeration + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2015 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbh_ctlreq.h" + +/** @addtogroup USBH_LIB +* @{ +*/ + +/** @addtogroup USBH_LIB_CORE +* @{ +*/ + +/** @defgroup USBH_CTLREQ +* @brief This file implements the standard requests for device enumeration +* @{ +*/ + + +/** @defgroup USBH_CTLREQ_Private_Defines +* @{ +*/ +/** +* @} +*/ + + +/** @defgroup USBH_CTLREQ_Private_TypesDefinitions +* @{ +*/ +/** +* @} +*/ + + + +/** @defgroup USBH_CTLREQ_Private_Macros +* @{ +*/ +/** +* @} +*/ + + +/** @defgroup USBH_CTLREQ_Private_Variables +* @{ +*/ +/** +* @} +*/ + +/** @defgroup USBH_CTLREQ_Private_FunctionPrototypes +* @{ +*/ +static USBH_StatusTypeDef USBH_HandleControl(USBH_HandleTypeDef *phost); + +static void USBH_ParseDevDesc(USBH_DevDescTypeDef *dev_desc, + uint8_t *buf, uint16_t length); + +static void USBH_ParseCfgDesc(USBH_CfgDescTypeDef *cfg_desc, + uint8_t *buf, uint16_t length); + +static void USBH_ParseEPDesc(USBH_EpDescTypeDef *ep_descriptor, uint8_t *buf); +static void USBH_ParseStringDesc(uint8_t *psrc, uint8_t *pdest, uint16_t length); +static void USBH_ParseInterfaceDesc(USBH_InterfaceDescTypeDef *if_descriptor, uint8_t *buf); + + +/** +* @} +*/ + + +/** @defgroup USBH_CTLREQ_Private_Functions +* @{ +*/ + + +/** + * @brief USBH_Get_DevDesc + * Issue Get Device Descriptor command to the device. Once the response + * received, it parses the device descriptor and updates the status. + * @param phost: Host Handle + * @param length: Length of the descriptor + * @retval USBH Status + */ +USBH_StatusTypeDef USBH_Get_DevDesc(USBH_HandleTypeDef *phost, uint8_t length) +{ + USBH_StatusTypeDef status; + + if ((status = USBH_GetDescriptor(phost, + USB_REQ_RECIPIENT_DEVICE | USB_REQ_TYPE_STANDARD, + USB_DESC_DEVICE, phost->device.Data, + (uint16_t)length)) == USBH_OK) + { + /* Commands successfully sent and Response Received */ + USBH_ParseDevDesc(&phost->device.DevDesc, phost->device.Data, + (uint16_t)length); + } + + return status; +} + + +/** + * @brief USBH_Get_CfgDesc + * Issues Configuration Descriptor to the device. Once the response + * received, it parses the configuration descriptor and updates the + * status. + * @param phost: Host Handle + * @param length: Length of the descriptor + * @retval USBH Status + */ +USBH_StatusTypeDef USBH_Get_CfgDesc(USBH_HandleTypeDef *phost, + uint16_t length) + +{ + USBH_StatusTypeDef status; + uint8_t *pData = phost->device.CfgDesc_Raw;; + + if ((status = USBH_GetDescriptor(phost, (USB_REQ_RECIPIENT_DEVICE | USB_REQ_TYPE_STANDARD), + USB_DESC_CONFIGURATION, pData, length)) == USBH_OK) + { + /* Commands successfully sent and Response Received */ + USBH_ParseCfgDesc(&phost->device.CfgDesc, pData, length); + } + + return status; +} + + +/** + * @brief USBH_Get_StringDesc + * Issues string Descriptor command to the device. Once the response + * received, it parses the string descriptor and updates the status. + * @param phost: Host Handle + * @param string_index: String index for the descriptor + * @param buff: Buffer address for the descriptor + * @param length: Length of the descriptor + * @retval USBH Status + */ +USBH_StatusTypeDef USBH_Get_StringDesc(USBH_HandleTypeDef *phost, + uint8_t string_index, uint8_t *buff, + uint16_t length) +{ + USBH_StatusTypeDef status; + + if ((status = USBH_GetDescriptor(phost, + USB_REQ_RECIPIENT_DEVICE | USB_REQ_TYPE_STANDARD, + USB_DESC_STRING | string_index, + phost->device.Data, length)) == USBH_OK) + { + /* Commands successfully sent and Response Received */ + USBH_ParseStringDesc(phost->device.Data, buff, length); + } + + return status; +} + + +/** + * @brief USBH_GetDescriptor + * Issues Descriptor command to the device. Once the response received, + * it parses the descriptor and updates the status. + * @param phost: Host Handle + * @param req_type: Descriptor type + * @param value_idx: Value for the GetDescriptr request + * @param buff: Buffer to store the descriptor + * @param length: Length of the descriptor + * @retval USBH Status + */ +USBH_StatusTypeDef USBH_GetDescriptor(USBH_HandleTypeDef *phost, + uint8_t req_type, + uint16_t value_idx, + uint8_t *buff, + uint16_t length) +{ + if (phost->RequestState == CMD_SEND) + { + phost->Control.setup.b.bmRequestType = USB_D2H | req_type; + phost->Control.setup.b.bRequest = USB_REQ_GET_DESCRIPTOR; + phost->Control.setup.b.wValue.w = value_idx; + + if ((value_idx & 0xff00U) == USB_DESC_STRING) + { + phost->Control.setup.b.wIndex.w = 0x0409U; + } + else + { + phost->Control.setup.b.wIndex.w = 0U; + } + phost->Control.setup.b.wLength.w = length; + } + + return USBH_CtlReq(phost, buff, length); +} + + +/** + * @brief USBH_SetAddress + * This command sets the address to the connected device + * @param phost: Host Handle + * @param DeviceAddress: Device address to assign + * @retval USBH Status + */ +USBH_StatusTypeDef USBH_SetAddress(USBH_HandleTypeDef *phost, + uint8_t DeviceAddress) +{ + if (phost->RequestState == CMD_SEND) + { + phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_DEVICE | \ + USB_REQ_TYPE_STANDARD; + + phost->Control.setup.b.bRequest = USB_REQ_SET_ADDRESS; + + phost->Control.setup.b.wValue.w = (uint16_t)DeviceAddress; + phost->Control.setup.b.wIndex.w = 0U; + phost->Control.setup.b.wLength.w = 0U; + } + + return USBH_CtlReq(phost, 0U, 0U); +} + + +/** + * @brief USBH_SetCfg + * The command sets the configuration value to the connected device + * @param phost: Host Handle + * @param cfg_idx: Configuration value + * @retval USBH Status + */ +USBH_StatusTypeDef USBH_SetCfg(USBH_HandleTypeDef *phost, uint16_t cfg_idx) +{ + if (phost->RequestState == CMD_SEND) + { + phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_DEVICE + | USB_REQ_TYPE_STANDARD; + + phost->Control.setup.b.bRequest = USB_REQ_SET_CONFIGURATION; + phost->Control.setup.b.wValue.w = cfg_idx; + phost->Control.setup.b.wIndex.w = 0U; + phost->Control.setup.b.wLength.w = 0U; + } + + return USBH_CtlReq(phost, 0U, 0U); +} + + +/** + * @brief USBH_SetInterface + * The command sets the Interface value to the connected device + * @param phost: Host Handle + * @param altSetting: Interface value + * @retval USBH Status + */ +USBH_StatusTypeDef USBH_SetInterface(USBH_HandleTypeDef *phost, uint8_t ep_num, + uint8_t altSetting) +{ + if (phost->RequestState == CMD_SEND) + { + phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_INTERFACE + | USB_REQ_TYPE_STANDARD; + + phost->Control.setup.b.bRequest = USB_REQ_SET_INTERFACE; + phost->Control.setup.b.wValue.w = altSetting; + phost->Control.setup.b.wIndex.w = ep_num; + phost->Control.setup.b.wLength.w = 0U; + } + + return USBH_CtlReq(phost, 0U, 0U); +} + + +/** + * @brief USBH_SetFeature + * The command sets the device features (remote wakeup feature,..) + * @param pdev: Selected device + * @param itf_idx + * @retval Status +*/ +USBH_StatusTypeDef USBH_SetFeature(USBH_HandleTypeDef *phost, uint8_t wValue) +{ + if (phost->RequestState == CMD_SEND) + { + phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_DEVICE + | USB_REQ_TYPE_STANDARD; + + phost->Control.setup.b.bRequest = USB_REQ_SET_FEATURE; + phost->Control.setup.b.wValue.w = wValue; + phost->Control.setup.b.wIndex.w = 0U; + phost->Control.setup.b.wLength.w = 0U; + } + + return USBH_CtlReq(phost, 0U, 0U); +} + + +/** + * @brief USBH_ClrFeature + * This request is used to clear or disable a specific feature. + * @param phost: Host Handle + * @param ep_num: endpoint number + * @param hc_num: Host channel number + * @retval USBH Status + */ +USBH_StatusTypeDef USBH_ClrFeature(USBH_HandleTypeDef *phost, uint8_t ep_num) +{ + if (phost->RequestState == CMD_SEND) + { + phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_ENDPOINT + | USB_REQ_TYPE_STANDARD; + + phost->Control.setup.b.bRequest = USB_REQ_CLEAR_FEATURE; + phost->Control.setup.b.wValue.w = FEATURE_SELECTOR_ENDPOINT; + phost->Control.setup.b.wIndex.w = ep_num; + phost->Control.setup.b.wLength.w = 0U; + } + return USBH_CtlReq(phost, 0U, 0U); +} + + +/** + * @brief USBH_ParseDevDesc + * This function Parses the device descriptor + * @param dev_desc: device_descriptor destination address + * @param buf: Buffer where the source descriptor is available + * @param length: Length of the descriptor + * @retval None + */ +static void USBH_ParseDevDesc(USBH_DevDescTypeDef *dev_desc, uint8_t *buf, + uint16_t length) +{ + dev_desc->bLength = *(uint8_t *)(buf + 0); + dev_desc->bDescriptorType = *(uint8_t *)(buf + 1); + dev_desc->bcdUSB = LE16(buf + 2); + dev_desc->bDeviceClass = *(uint8_t *)(buf + 4); + dev_desc->bDeviceSubClass = *(uint8_t *)(buf + 5); + dev_desc->bDeviceProtocol = *(uint8_t *)(buf + 6); + dev_desc->bMaxPacketSize = *(uint8_t *)(buf + 7); + + if (length > 8U) + { + /* For 1st time after device connection, Host may issue only 8 bytes for + Device Descriptor Length */ + dev_desc->idVendor = LE16(buf + 8); + dev_desc->idProduct = LE16(buf + 10); + dev_desc->bcdDevice = LE16(buf + 12); + dev_desc->iManufacturer = *(uint8_t *)(buf + 14); + dev_desc->iProduct = *(uint8_t *)(buf + 15); + dev_desc->iSerialNumber = *(uint8_t *)(buf + 16); + dev_desc->bNumConfigurations = *(uint8_t *)(buf + 17); + } +} + + +/** + * @brief USBH_ParseCfgDesc + * This function Parses the configuration descriptor + * @param cfg_desc: Configuration Descriptor address + * @param buf: Buffer where the source descriptor is available + * @param length: Length of the descriptor + * @retval None + */ +static void USBH_ParseCfgDesc(USBH_CfgDescTypeDef *cfg_desc, uint8_t *buf, + uint16_t length) +{ + USBH_InterfaceDescTypeDef *pif ; + USBH_EpDescTypeDef *pep; + USBH_DescHeader_t *pdesc = (USBH_DescHeader_t *)(void *)buf; + uint16_t ptr; + uint8_t if_ix = 0U; + uint8_t ep_ix = 0U; + + pdesc = (USBH_DescHeader_t *)(void *)buf; + + /* Parse configuration descriptor */ + cfg_desc->bLength = *(uint8_t *)(buf + 0); + cfg_desc->bDescriptorType = *(uint8_t *)(buf + 1); + cfg_desc->wTotalLength = LE16(buf + 2); + cfg_desc->bNumInterfaces = *(uint8_t *)(buf + 4); + cfg_desc->bConfigurationValue = *(uint8_t *)(buf + 5); + cfg_desc->iConfiguration = *(uint8_t *)(buf + 6); + cfg_desc->bmAttributes = *(uint8_t *)(buf + 7); + cfg_desc->bMaxPower = *(uint8_t *)(buf + 8); + + if (length > USB_CONFIGURATION_DESC_SIZE) + { + ptr = USB_LEN_CFG_DESC; + pif = (USBH_InterfaceDescTypeDef *)0; + + while ((if_ix < USBH_MAX_NUM_INTERFACES) && (ptr < cfg_desc->wTotalLength)) + { + pdesc = USBH_GetNextDesc((uint8_t *)(void *)pdesc, &ptr); + if (pdesc->bDescriptorType == USB_DESC_TYPE_INTERFACE) + { + pif = &cfg_desc->Itf_Desc[if_ix]; + USBH_ParseInterfaceDesc(pif, (uint8_t *)(void *)pdesc); + + ep_ix = 0U; + pep = (USBH_EpDescTypeDef *)0; + while ((ep_ix < pif->bNumEndpoints) && (ptr < cfg_desc->wTotalLength)) + { + pdesc = USBH_GetNextDesc((uint8_t *)(void *)pdesc, &ptr); + if (pdesc->bDescriptorType == USB_DESC_TYPE_ENDPOINT) + { + pep = &cfg_desc->Itf_Desc[if_ix].Ep_Desc[ep_ix]; + USBH_ParseEPDesc(pep, (uint8_t *)(void *)pdesc); + ep_ix++; + } + } + if_ix++; + } + } + } +} + + +/** + * @brief USBH_ParseInterfaceDesc + * This function Parses the interface descriptor + * @param if_descriptor : Interface descriptor destination + * @param buf: Buffer where the descriptor data is available + * @retval None + */ +static void USBH_ParseInterfaceDesc(USBH_InterfaceDescTypeDef *if_descriptor, + uint8_t *buf) +{ + if_descriptor->bLength = *(uint8_t *)(buf + 0); + if_descriptor->bDescriptorType = *(uint8_t *)(buf + 1); + if_descriptor->bInterfaceNumber = *(uint8_t *)(buf + 2); + if_descriptor->bAlternateSetting = *(uint8_t *)(buf + 3); + if_descriptor->bNumEndpoints = *(uint8_t *)(buf + 4); + if_descriptor->bInterfaceClass = *(uint8_t *)(buf + 5); + if_descriptor->bInterfaceSubClass = *(uint8_t *)(buf + 6); + if_descriptor->bInterfaceProtocol = *(uint8_t *)(buf + 7); + if_descriptor->iInterface = *(uint8_t *)(buf + 8); +} + + +/** + * @brief USBH_ParseEPDesc + * This function Parses the endpoint descriptor + * @param ep_descriptor: Endpoint descriptor destination address + * @param buf: Buffer where the parsed descriptor stored + * @retval None + */ +static void USBH_ParseEPDesc(USBH_EpDescTypeDef *ep_descriptor, + uint8_t *buf) +{ + ep_descriptor->bLength = *(uint8_t *)(buf + 0); + ep_descriptor->bDescriptorType = *(uint8_t *)(buf + 1); + ep_descriptor->bEndpointAddress = *(uint8_t *)(buf + 2); + ep_descriptor->bmAttributes = *(uint8_t *)(buf + 3); + ep_descriptor->wMaxPacketSize = LE16(buf + 4); + ep_descriptor->bInterval = *(uint8_t *)(buf + 6); +} + + +/** + * @brief USBH_ParseStringDesc + * This function Parses the string descriptor + * @param psrc: Source pointer containing the descriptor data + * @param pdest: Destination address pointer + * @param length: Length of the descriptor + * @retval None + */ +static void USBH_ParseStringDesc(uint8_t *psrc, uint8_t *pdest, uint16_t length) +{ + uint16_t strlength; + uint16_t idx; + + /* The UNICODE string descriptor is not NULL-terminated. The string length is + computed by substracting two from the value of the first byte of the descriptor. + */ + + /* Check which is lower size, the Size of string or the length of bytes read + from the device */ + + if (psrc[1] == USB_DESC_TYPE_STRING) + { + /* Make sure the Descriptor is String Type */ + + /* psrc[0] contains Size of Descriptor, subtract 2 to get the length of string */ + strlength = ((((uint16_t)psrc[0] - 2U) <= length) ? ((uint16_t)psrc[0] - 2U) : length); + + /* Adjust the offset ignoring the String Len and Descriptor type */ + psrc += 2U; + + for (idx = 0U; idx < strlength; idx += 2U) + { + /* Copy Only the string and ignore the UNICODE ID, hence add the src */ + *pdest = psrc[idx]; + pdest++; + } + *pdest = 0U; /* mark end of string */ + } +} + + +/** + * @brief USBH_GetNextDesc + * This function return the next descriptor header + * @param buf: Buffer where the cfg descriptor is available + * @param ptr: data pointer inside the cfg descriptor + * @retval next header + */ +USBH_DescHeader_t *USBH_GetNextDesc(uint8_t *pbuf, uint16_t *ptr) +{ + USBH_DescHeader_t *pnext; + + *ptr += ((USBH_DescHeader_t *)(void *)pbuf)->bLength; + pnext = (USBH_DescHeader_t *)(void *)((uint8_t *)(void *)pbuf + \ + ((USBH_DescHeader_t *)(void *)pbuf)->bLength); + + return (pnext); +} + + +/** + * @brief USBH_CtlReq + * USBH_CtlReq sends a control request and provide the status after + * completion of the request + * @param phost: Host Handle + * @param req: Setup Request Structure + * @param buff: data buffer address to store the response + * @param length: length of the response + * @retval USBH Status + */ +USBH_StatusTypeDef USBH_CtlReq(USBH_HandleTypeDef *phost, uint8_t *buff, + uint16_t length) +{ + USBH_StatusTypeDef status; + status = USBH_BUSY; + + switch (phost->RequestState) + { + case CMD_SEND: + /* Start a SETUP transfer */ + phost->Control.buff = buff; + phost->Control.length = length; + phost->Control.state = CTRL_SETUP; + phost->RequestState = CMD_WAIT; + status = USBH_BUSY; + +#if (USBH_USE_OS == 1U) + phost->os_msg = (uint32_t)USBH_CONTROL_EVENT; +#if (osCMSIS < 0x20000U) + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + break; + + case CMD_WAIT: + status = USBH_HandleControl(phost); + if ((status == USBH_OK) || (status == USBH_NOT_SUPPORTED)) + { + /* Transaction completed, move control state to idle */ + phost->RequestState = CMD_SEND; + phost->Control.state = CTRL_IDLE; + } + else if (status == USBH_FAIL) + { + /* Failure Mode */ + phost->RequestState = CMD_SEND; + } + else + { + /* .. */ + } +#if (USBH_USE_OS == 1U) + phost->os_msg = (uint32_t)USBH_CONTROL_EVENT; +#if (osCMSIS < 0x20000U) + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + break; + + default: + break; + } + return status; +} + + +/** + * @brief USBH_HandleControl + * Handles the USB control transfer state machine + * @param phost: Host Handle + * @retval USBH Status + */ +static USBH_StatusTypeDef USBH_HandleControl(USBH_HandleTypeDef *phost) +{ + uint8_t direction; + USBH_StatusTypeDef status = USBH_BUSY; + USBH_URBStateTypeDef URB_Status = USBH_URB_IDLE; + + switch (phost->Control.state) + { + case CTRL_SETUP: + /* send a SETUP packet */ + USBH_CtlSendSetup(phost, (uint8_t *)(void *)phost->Control.setup.d8, + phost->Control.pipe_out); + + phost->Control.state = CTRL_SETUP_WAIT; + break; + + case CTRL_SETUP_WAIT: + + URB_Status = USBH_LL_GetURBState(phost, phost->Control.pipe_out); + /* case SETUP packet sent successfully */ + if (URB_Status == USBH_URB_DONE) + { + direction = (phost->Control.setup.b.bmRequestType & USB_REQ_DIR_MASK); + + /* check if there is a data stage */ + if (phost->Control.setup.b.wLength.w != 0U) + { + if (direction == USB_D2H) + { + /* Data Direction is IN */ + phost->Control.state = CTRL_DATA_IN; + } + else + { + /* Data Direction is OUT */ + phost->Control.state = CTRL_DATA_OUT; + } + } + /* No DATA stage */ + else + { + /* If there is No Data Transfer Stage */ + if (direction == USB_D2H) + { + /* Data Direction is IN */ + phost->Control.state = CTRL_STATUS_OUT; + } + else + { + /* Data Direction is OUT */ + phost->Control.state = CTRL_STATUS_IN; + } + } + +#if (USBH_USE_OS == 1U) + phost->os_msg = (uint32_t)USBH_CONTROL_EVENT; +#if (osCMSIS < 0x20000U) + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + } + else + { + if ((URB_Status == USBH_URB_ERROR) || (URB_Status == USBH_URB_NOTREADY)) + { + phost->Control.state = CTRL_ERROR; + +#if (USBH_USE_OS == 1U) + phost->os_msg = (uint32_t)USBH_CONTROL_EVENT; +#if (osCMSIS < 0x20000U) + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + } + } + break; + + case CTRL_DATA_IN: + /* Issue an IN token */ + phost->Control.timer = (uint16_t)phost->Timer; + USBH_CtlReceiveData(phost, phost->Control.buff, phost->Control.length, + phost->Control.pipe_in); + + phost->Control.state = CTRL_DATA_IN_WAIT; + break; + + case CTRL_DATA_IN_WAIT: + + URB_Status = USBH_LL_GetURBState(phost, phost->Control.pipe_in); + + /* check is DATA packet transferred successfully */ + if (URB_Status == USBH_URB_DONE) + { + phost->Control.state = CTRL_STATUS_OUT; + +#if (USBH_USE_OS == 1U) + phost->os_msg = (uint32_t)USBH_CONTROL_EVENT; +#if (osCMSIS < 0x20000U) + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + } + + /* manage error cases*/ + if (URB_Status == USBH_URB_STALL) + { + /* In stall case, return to previous machine state*/ + status = USBH_NOT_SUPPORTED; + +#if (USBH_USE_OS == 1U) + phost->os_msg = (uint32_t)USBH_CONTROL_EVENT; +#if (osCMSIS < 0x20000U) + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + } + else + { + if (URB_Status == USBH_URB_ERROR) + { + /* Device error */ + phost->Control.state = CTRL_ERROR; + +#if (USBH_USE_OS == 1U) + phost->os_msg = (uint32_t)USBH_CONTROL_EVENT; +#if (osCMSIS < 0x20000U) + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + } + } + break; + + case CTRL_DATA_OUT: + + USBH_CtlSendData(phost, phost->Control.buff, phost->Control.length, + phost->Control.pipe_out, 1U); + + phost->Control.timer = (uint16_t)phost->Timer; + phost->Control.state = CTRL_DATA_OUT_WAIT; + break; + + case CTRL_DATA_OUT_WAIT: + + URB_Status = USBH_LL_GetURBState(phost, phost->Control.pipe_out); + + if (URB_Status == USBH_URB_DONE) + { + /* If the Setup Pkt is sent successful, then change the state */ + phost->Control.state = CTRL_STATUS_IN; + +#if (USBH_USE_OS == 1U) + phost->os_msg = (uint32_t)USBH_CONTROL_EVENT; +#if (osCMSIS < 0x20000U) + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + } + + /* handle error cases */ + else if (URB_Status == USBH_URB_STALL) + { + /* In stall case, return to previous machine state*/ + phost->Control.state = CTRL_STALLED; + status = USBH_NOT_SUPPORTED; + +#if (USBH_USE_OS == 1U) + phost->os_msg = (uint32_t)USBH_CONTROL_EVENT; +#if (osCMSIS < 0x20000U) + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + } + else if (URB_Status == USBH_URB_NOTREADY) + { + /* Nack received from device */ + phost->Control.state = CTRL_DATA_OUT; + +#if (USBH_USE_OS == 1U) + phost->os_msg = (uint32_t)USBH_CONTROL_EVENT; +#if (osCMSIS < 0x20000U) + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + } + else + { + if (URB_Status == USBH_URB_ERROR) + { + /* device error */ + phost->Control.state = CTRL_ERROR; + status = USBH_FAIL; + +#if (USBH_USE_OS == 1U) + phost->os_msg = (uint32_t)USBH_CONTROL_EVENT; +#if (osCMSIS < 0x20000U) + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + } + } + break; + + case CTRL_STATUS_IN: + /* Send 0 bytes out packet */ + USBH_CtlReceiveData(phost, 0U, 0U, phost->Control.pipe_in); + + phost->Control.timer = (uint16_t)phost->Timer; + phost->Control.state = CTRL_STATUS_IN_WAIT; + + break; + + case CTRL_STATUS_IN_WAIT: + + URB_Status = USBH_LL_GetURBState(phost, phost->Control.pipe_in); + + if (URB_Status == USBH_URB_DONE) + { + /* Control transfers completed, Exit the State Machine */ + phost->Control.state = CTRL_COMPLETE; + status = USBH_OK; + +#if (USBH_USE_OS == 1U) + phost->os_msg = (uint32_t)USBH_CONTROL_EVENT; +#if (osCMSIS < 0x20000U) + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + } + else if (URB_Status == USBH_URB_ERROR) + { + phost->Control.state = CTRL_ERROR; + +#if (USBH_USE_OS == 1U) + phost->os_msg = (uint32_t)USBH_CONTROL_EVENT; +#if (osCMSIS < 0x20000U) + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + } + else + { + if (URB_Status == USBH_URB_STALL) + { + /* Control transfers completed, Exit the State Machine */ + status = USBH_NOT_SUPPORTED; + +#if (USBH_USE_OS == 1U) + phost->os_msg = (uint32_t)USBH_CONTROL_EVENT; +#if (osCMSIS < 0x20000U) + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + } + } + break; + + case CTRL_STATUS_OUT: + USBH_CtlSendData(phost, 0U, 0U, phost->Control.pipe_out, 1U); + + phost->Control.timer = (uint16_t)phost->Timer; + phost->Control.state = CTRL_STATUS_OUT_WAIT; + break; + + case CTRL_STATUS_OUT_WAIT: + URB_Status = USBH_LL_GetURBState(phost, phost->Control.pipe_out); + if (URB_Status == USBH_URB_DONE) + { + status = USBH_OK; + phost->Control.state = CTRL_COMPLETE; + +#if (USBH_USE_OS == 1U) + phost->os_msg = (uint32_t)USBH_CONTROL_EVENT; +#if (osCMSIS < 0x20000U) + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + } + else if (URB_Status == USBH_URB_NOTREADY) + { + phost->Control.state = CTRL_STATUS_OUT; + +#if (USBH_USE_OS == 1U) + phost->os_msg = (uint32_t)USBH_CONTROL_EVENT; +#if (osCMSIS < 0x20000U) + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + } + else + { + if (URB_Status == USBH_URB_ERROR) + { + phost->Control.state = CTRL_ERROR; + +#if (USBH_USE_OS == 1U) + phost->os_msg = (uint32_t)USBH_CONTROL_EVENT; +#if (osCMSIS < 0x20000U) + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + } + } + break; + + case CTRL_ERROR: + /* + After a halt condition is encountered or an error is detected by the + host, a control endpoint is allowed to recover by accepting the next Setup + PID; i.e., recovery actions via some other pipe are not required for control + endpoints. For the Default Control Pipe, a device reset will ultimately be + required to clear the halt or error condition if the next Setup PID is not + accepted. + */ + if (++phost->Control.errorcount <= USBH_MAX_ERROR_COUNT) + { + /* Do the transmission again, starting from SETUP Packet */ + phost->Control.state = CTRL_SETUP; + phost->RequestState = CMD_SEND; + } + else + { + phost->pUser(phost, HOST_USER_UNRECOVERED_ERROR); + phost->Control.errorcount = 0U; + USBH_ErrLog("Control error: Device not responding"); + + /* Free control pipes */ + USBH_FreePipe(phost, phost->Control.pipe_out); + USBH_FreePipe(phost, phost->Control.pipe_in); + + phost->gState = HOST_IDLE; + status = USBH_FAIL; + } + break; + + default: + break; + } + + return status; +} + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + + + + diff --git a/Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ioreq.c b/Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ioreq.c new file mode 100644 index 0000000..46e9734 --- /dev/null +++ b/Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ioreq.c @@ -0,0 +1,350 @@ +/** + ****************************************************************************** + * @file usbh_ioreq.c + * @author MCD Application Team + * @brief This file handles the issuing of the USB transactions + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2015 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbh_ioreq.h" + +/** @addtogroup USBH_LIB + * @{ + */ + +/** @addtogroup USBH_LIB_CORE +* @{ +*/ + +/** @defgroup USBH_IOREQ + * @brief This file handles the standard protocol processing (USB v2.0) + * @{ + */ + + +/** @defgroup USBH_IOREQ_Private_Defines + * @{ + */ + +/** + * @} + */ + + +/** @defgroup USBH_IOREQ_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + + + +/** @defgroup USBH_IOREQ_Private_Macros + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBH_IOREQ_Private_Variables + * @{ + */ +/** + * @} + */ +/** @defgroup USBH_IOREQ_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + + +/** @defgroup USBH_IOREQ_Private_Functions + * @{ + */ + + + +/** + * @brief USBH_CtlSendSetup + * Sends the Setup Packet to the Device + * @param phost: Host Handle + * @param buff: Buffer pointer from which the Data will be send to Device + * @param pipe_num: Pipe Number + * @retval USBH Status + */ +USBH_StatusTypeDef USBH_CtlSendSetup(USBH_HandleTypeDef *phost, + uint8_t *buff, + uint8_t pipe_num) +{ + + USBH_LL_SubmitURB(phost, /* Driver handle */ + pipe_num, /* Pipe index */ + 0U, /* Direction : OUT */ + USBH_EP_CONTROL, /* EP type */ + USBH_PID_SETUP, /* Type setup */ + buff, /* data buffer */ + USBH_SETUP_PKT_SIZE, /* data length */ + 0U); + return USBH_OK; +} + + +/** + * @brief USBH_CtlSendData + * Sends a data Packet to the Device + * @param phost: Host Handle + * @param buff: Buffer pointer from which the Data will be sent to Device + * @param length: Length of the data to be sent + * @param pipe_num: Pipe Number + * @retval USBH Status + */ +USBH_StatusTypeDef USBH_CtlSendData(USBH_HandleTypeDef *phost, + uint8_t *buff, + uint16_t length, + uint8_t pipe_num, + uint8_t do_ping) +{ + if (phost->device.speed != USBH_SPEED_HIGH) + { + do_ping = 0U; + } + + USBH_LL_SubmitURB(phost, /* Driver handle */ + pipe_num, /* Pipe index */ + 0U, /* Direction : OUT */ + USBH_EP_CONTROL, /* EP type */ + USBH_PID_DATA, /* Type Data */ + buff, /* data buffer */ + length, /* data length */ + do_ping); /* do ping (HS Only)*/ + + return USBH_OK; +} + + +/** + * @brief USBH_CtlReceiveData + * Receives the Device Response to the Setup Packet + * @param phost: Host Handle + * @param buff: Buffer pointer in which the response needs to be copied + * @param length: Length of the data to be received + * @param pipe_num: Pipe Number + * @retval USBH Status. + */ +USBH_StatusTypeDef USBH_CtlReceiveData(USBH_HandleTypeDef *phost, + uint8_t *buff, + uint16_t length, + uint8_t pipe_num) +{ + USBH_LL_SubmitURB(phost, /* Driver handle */ + pipe_num, /* Pipe index */ + 1U, /* Direction : IN */ + USBH_EP_CONTROL, /* EP type */ + USBH_PID_DATA, /* Type Data */ + buff, /* data buffer */ + length, /* data length */ + 0U); + return USBH_OK; + +} + + +/** + * @brief USBH_BulkSendData + * Sends the Bulk Packet to the device + * @param phost: Host Handle + * @param buff: Buffer pointer from which the Data will be sent to Device + * @param length: Length of the data to be sent + * @param pipe_num: Pipe Number + * @retval USBH Status + */ +USBH_StatusTypeDef USBH_BulkSendData(USBH_HandleTypeDef *phost, + uint8_t *buff, + uint16_t length, + uint8_t pipe_num, + uint8_t do_ping) +{ + if (phost->device.speed != USBH_SPEED_HIGH) + { + do_ping = 0U; + } + + USBH_LL_SubmitURB(phost, /* Driver handle */ + pipe_num, /* Pipe index */ + 0U, /* Direction : IN */ + USBH_EP_BULK, /* EP type */ + USBH_PID_DATA, /* Type Data */ + buff, /* data buffer */ + length, /* data length */ + do_ping); /* do ping (HS Only)*/ + return USBH_OK; +} + + +/** + * @brief USBH_BulkReceiveData + * Receives IN bulk packet from device + * @param phost: Host Handle + * @param buff: Buffer pointer in which the received data packet to be copied + * @param length: Length of the data to be received + * @param pipe_num: Pipe Number + * @retval USBH Status. + */ +USBH_StatusTypeDef USBH_BulkReceiveData(USBH_HandleTypeDef *phost, + uint8_t *buff, + uint16_t length, + uint8_t pipe_num) +{ + USBH_LL_SubmitURB(phost, /* Driver handle */ + pipe_num, /* Pipe index */ + 1U, /* Direction : IN */ + USBH_EP_BULK, /* EP type */ + USBH_PID_DATA, /* Type Data */ + buff, /* data buffer */ + length, /* data length */ + 0U); + return USBH_OK; +} + + +/** + * @brief USBH_InterruptReceiveData + * Receives the Device Response to the Interrupt IN token + * @param phost: Host Handle + * @param buff: Buffer pointer in which the response needs to be copied + * @param length: Length of the data to be received + * @param pipe_num: Pipe Number + * @retval USBH Status. + */ +USBH_StatusTypeDef USBH_InterruptReceiveData(USBH_HandleTypeDef *phost, + uint8_t *buff, + uint8_t length, + uint8_t pipe_num) +{ + USBH_LL_SubmitURB(phost, /* Driver handle */ + pipe_num, /* Pipe index */ + 1U, /* Direction : IN */ + USBH_EP_INTERRUPT, /* EP type */ + USBH_PID_DATA, /* Type Data */ + buff, /* data buffer */ + (uint16_t)length, /* data length */ + 0U); + + return USBH_OK; +} + +/** + * @brief USBH_InterruptSendData + * Sends the data on Interrupt OUT Endpoint + * @param phost: Host Handle + * @param buff: Buffer pointer from where the data needs to be copied + * @param length: Length of the data to be sent + * @param pipe_num: Pipe Number + * @retval USBH Status. + */ +USBH_StatusTypeDef USBH_InterruptSendData(USBH_HandleTypeDef *phost, + uint8_t *buff, + uint8_t length, + uint8_t pipe_num) +{ + USBH_LL_SubmitURB(phost, /* Driver handle */ + pipe_num, /* Pipe index */ + 0U, /* Direction : OUT */ + USBH_EP_INTERRUPT, /* EP type */ + USBH_PID_DATA, /* Type Data */ + buff, /* data buffer */ + (uint16_t)length, /* data length */ + 0U); + + return USBH_OK; +} + +/** + * @brief USBH_IsocReceiveData + * Receives the Device Response to the Isochronous IN token + * @param phost: Host Handle + * @param buff: Buffer pointer in which the response needs to be copied + * @param length: Length of the data to be received + * @param pipe_num: Pipe Number + * @retval USBH Status. + */ +USBH_StatusTypeDef USBH_IsocReceiveData(USBH_HandleTypeDef *phost, + uint8_t *buff, + uint32_t length, + uint8_t pipe_num) +{ + USBH_LL_SubmitURB(phost, /* Driver handle */ + pipe_num, /* Pipe index */ + 1U, /* Direction : IN */ + USBH_EP_ISO, /* EP type */ + USBH_PID_DATA, /* Type Data */ + buff, /* data buffer */ + (uint16_t)length, /* data length */ + 0U); + + + return USBH_OK; +} + +/** + * @brief USBH_IsocSendData + * Sends the data on Isochronous OUT Endpoint + * @param phost: Host Handle + * @param buff: Buffer pointer from where the data needs to be copied + * @param length: Length of the data to be sent + * @param pipe_num: Pipe Number + * @retval USBH Status. + */ +USBH_StatusTypeDef USBH_IsocSendData(USBH_HandleTypeDef *phost, + uint8_t *buff, + uint32_t length, + uint8_t pipe_num) +{ + USBH_LL_SubmitURB(phost, /* Driver handle */ + pipe_num, /* Pipe index */ + 0U, /* Direction : OUT */ + USBH_EP_ISO, /* EP type */ + USBH_PID_DATA, /* Type Data */ + buff, /* data buffer */ + (uint16_t)length, /* data length */ + 0U); + + return USBH_OK; +} +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + + + diff --git a/Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_pipes.c b/Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_pipes.c new file mode 100644 index 0000000..60fe08b --- /dev/null +++ b/Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_pipes.c @@ -0,0 +1,188 @@ +/** + ****************************************************************************** + * @file usbh_pipes.c + * @author MCD Application Team + * @brief This file implements functions for opening and closing Pipes + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2015 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbh_pipes.h" + +/** @addtogroup USBH_LIB + * @{ + */ + +/** @addtogroup USBH_LIB_CORE +* @{ +*/ + +/** @defgroup USBH_PIPES + * @brief This file includes opening and closing Pipes + * @{ + */ + +/** @defgroup USBH_PIPES_Private_Defines + * @{ + */ +/** + * @} + */ + +/** @defgroup USBH_PIPES_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBH_PIPES_Private_Macros + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBH_PIPES_Private_Variables + * @{ + */ + +/** + * @} + */ + + +/** @defgroup USBH_PIPES_Private_Functions + * @{ + */ +static uint16_t USBH_GetFreePipe(USBH_HandleTypeDef *phost); + + +/** + * @brief USBH_Open_Pipe + * Open a pipe + * @param phost: Host Handle + * @param pipe_num: Pipe Number + * @param dev_address: USB Device address allocated to attached device + * @param speed : USB device speed (Full/Low) + * @param ep_type: end point type (Bulk/int/ctl) + * @param mps: max pkt size + * @retval USBH Status + */ +USBH_StatusTypeDef USBH_OpenPipe(USBH_HandleTypeDef *phost, uint8_t pipe_num, + uint8_t epnum, uint8_t dev_address, + uint8_t speed, uint8_t ep_type, uint16_t mps) +{ + USBH_LL_OpenPipe(phost, pipe_num, epnum, dev_address, speed, ep_type, mps); + + return USBH_OK; +} + + +/** + * @brief USBH_ClosePipe + * Close a pipe + * @param phost: Host Handle + * @param pipe_num: Pipe Number + * @retval USBH Status + */ +USBH_StatusTypeDef USBH_ClosePipe(USBH_HandleTypeDef *phost, uint8_t pipe_num) +{ + USBH_LL_ClosePipe(phost, pipe_num); + + return USBH_OK; +} + + +/** + * @brief USBH_Alloc_Pipe + * Allocate a new Pipe + * @param phost: Host Handle + * @param ep_addr: End point for which the Pipe to be allocated + * @retval Pipe number + */ +uint8_t USBH_AllocPipe(USBH_HandleTypeDef *phost, uint8_t ep_addr) +{ + uint16_t pipe; + + pipe = USBH_GetFreePipe(phost); + + if (pipe != 0xFFFFU) + { + phost->Pipes[pipe & 0xFU] = 0x8000U | ep_addr; + } + + return (uint8_t)pipe; +} + + +/** + * @brief USBH_Free_Pipe + * Free the USB Pipe + * @param phost: Host Handle + * @param idx: Pipe number to be freed + * @retval USBH Status + */ +USBH_StatusTypeDef USBH_FreePipe(USBH_HandleTypeDef *phost, uint8_t idx) +{ + if (idx < 11U) + { + phost->Pipes[idx] &= 0x7FFFU; + } + + return USBH_OK; +} + + +/** + * @brief USBH_GetFreePipe + * @param phost: Host Handle + * Get a free Pipe number for allocation to a device endpoint + * @retval idx: Free Pipe number + */ +static uint16_t USBH_GetFreePipe(USBH_HandleTypeDef *phost) +{ + uint8_t idx = 0U; + + for (idx = 0U ; idx < 11U ; idx++) + { + if ((phost->Pipes[idx] & 0x8000U) == 0U) + { + return (uint16_t)idx; + } + } + + return 0xFFFFU; +} +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + + diff --git a/Release/Core/Src/subdir.mk b/Release/Core/Src/subdir.mk new file mode 100644 index 0000000..c3c0430 --- /dev/null +++ b/Release/Core/Src/subdir.mk @@ -0,0 +1,49 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Core/Src/app.c \ +../Core/Src/main.c \ +../Core/Src/stm32f4xx_hal_msp.c \ +../Core/Src/stm32f4xx_it.c \ +../Core/Src/syscalls.c \ +../Core/Src/sysmem.c \ +../Core/Src/system_stm32f4xx.c + +C_DEPS += \ +./Core/Src/app.d \ +./Core/Src/main.d \ +./Core/Src/stm32f4xx_hal_msp.d \ +./Core/Src/stm32f4xx_it.d \ +./Core/Src/syscalls.d \ +./Core/Src/sysmem.d \ +./Core/Src/system_stm32f4xx.d + +OBJS += \ +./Core/Src/app.o \ +./Core/Src/main.o \ +./Core/Src/stm32f4xx_hal_msp.o \ +./Core/Src/stm32f4xx_it.o \ +./Core/Src/syscalls.o \ +./Core/Src/sysmem.o \ +./Core/Src/system_stm32f4xx.o + + +# Each subdirectory must supply rules for building sources it contributes +Core/Src/app.o: ../Core/Src/app.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F401xC -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/app.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Core/Src/main.o: ../Core/Src/main.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F401xC -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/main.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Core/Src/stm32f4xx_hal_msp.o: ../Core/Src/stm32f4xx_hal_msp.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F401xC -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/stm32f4xx_hal_msp.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Core/Src/stm32f4xx_it.o: ../Core/Src/stm32f4xx_it.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F401xC -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/stm32f4xx_it.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Core/Src/syscalls.o: ../Core/Src/syscalls.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F401xC -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/syscalls.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Core/Src/sysmem.o: ../Core/Src/sysmem.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F401xC -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/sysmem.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Core/Src/system_stm32f4xx.o: ../Core/Src/system_stm32f4xx.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F401xC -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/system_stm32f4xx.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + diff --git a/Release/Core/Startup/subdir.mk b/Release/Core/Startup/subdir.mk new file mode 100644 index 0000000..d8a4678 --- /dev/null +++ b/Release/Core/Startup/subdir.mk @@ -0,0 +1,19 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Core/Startup/startup_stm32f401vctx.s + +S_DEPS += \ +./Core/Startup/startup_stm32f401vctx.d + +OBJS += \ +./Core/Startup/startup_stm32f401vctx.o + + +# Each subdirectory must supply rules for building sources it contributes +Core/Startup/startup_stm32f401vctx.o: ../Core/Startup/startup_stm32f401vctx.s + arm-none-eabi-gcc -mcpu=cortex-m4 -c -x assembler-with-cpp -MMD -MP -MF"Core/Startup/startup_stm32f401vctx.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" "$<" + diff --git a/Release/Drivers/COMPASS_LEDS/subdir.mk b/Release/Drivers/COMPASS_LEDS/subdir.mk new file mode 100644 index 0000000..bef35c9 --- /dev/null +++ b/Release/Drivers/COMPASS_LEDS/subdir.mk @@ -0,0 +1,19 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/COMPASS_LEDS/COMPASS_LEDS.c + +C_DEPS += \ +./Drivers/COMPASS_LEDS/COMPASS_LEDS.d + +OBJS += \ +./Drivers/COMPASS_LEDS/COMPASS_LEDS.o + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/COMPASS_LEDS/COMPASS_LEDS.o: ../Drivers/COMPASS_LEDS/COMPASS_LEDS.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F401xC -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/COMPASS_LEDS/COMPASS_LEDS.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + diff --git a/Release/Drivers/LSM303DLHC/subdir.mk b/Release/Drivers/LSM303DLHC/subdir.mk new file mode 100644 index 0000000..b92a5fe --- /dev/null +++ b/Release/Drivers/LSM303DLHC/subdir.mk @@ -0,0 +1,19 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/LSM303DLHC/LSM303DLHC.c + +C_DEPS += \ +./Drivers/LSM303DLHC/LSM303DLHC.d + +OBJS += \ +./Drivers/LSM303DLHC/LSM303DLHC.o + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/LSM303DLHC/LSM303DLHC.o: ../Drivers/LSM303DLHC/LSM303DLHC.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F401xC -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/LSM303DLHC/LSM303DLHC.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + diff --git a/Release/Drivers/STM32F4xx_HAL_Driver/Src/subdir.mk b/Release/Drivers/STM32F4xx_HAL_Driver/Src/subdir.mk new file mode 100644 index 0000000..ca56ceb --- /dev/null +++ b/Release/Drivers/STM32F4xx_HAL_Driver/Src/subdir.mk @@ -0,0 +1,129 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c + +C_DEPS += \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.d + +OBJS += \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.o + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o: ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F401xC -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o: ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F401xC -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o: ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F401xC -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o: ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F401xC -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o: ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F401xC -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o: ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F401xC -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o: ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F401xC -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o: ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F401xC -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o: ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F401xC -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.o: ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F401xC -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.o: ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F401xC -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.o: ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F401xC -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.o: ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F401xC -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.o: ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F401xC -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o: ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F401xC -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o: ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F401xC -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o: ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F401xC -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o: ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F401xC -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.o: ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F401xC -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o: ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F401xC -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o: ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F401xC -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o: ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F401xC -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.o: ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F401xC -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + diff --git a/Release/Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Src/subdir.mk b/Release/Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Src/subdir.mk new file mode 100644 index 0000000..0af773b --- /dev/null +++ b/Release/Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Src/subdir.mk @@ -0,0 +1,19 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Src/usbh_cdc.c + +C_DEPS += \ +./Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Src/usbh_cdc.d + +OBJS += \ +./Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Src/usbh_cdc.o + + +# Each subdirectory must supply rules for building sources it contributes +Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Src/usbh_cdc.o: ../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Src/usbh_cdc.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F401xC -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Src/usbh_cdc.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + diff --git a/Release/Middlewares/ST/STM32_USB_Host_Library/Core/Src/subdir.mk b/Release/Middlewares/ST/STM32_USB_Host_Library/Core/Src/subdir.mk new file mode 100644 index 0000000..a17cada --- /dev/null +++ b/Release/Middlewares/ST/STM32_USB_Host_Library/Core/Src/subdir.mk @@ -0,0 +1,34 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_core.c \ +../Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ctlreq.c \ +../Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ioreq.c \ +../Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_pipes.c + +C_DEPS += \ +./Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_core.d \ +./Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ctlreq.d \ +./Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ioreq.d \ +./Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_pipes.d + +OBJS += \ +./Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_core.o \ +./Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ctlreq.o \ +./Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ioreq.o \ +./Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_pipes.o + + +# Each subdirectory must supply rules for building sources it contributes +Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_core.o: ../Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_core.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F401xC -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_core.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ctlreq.o: ../Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ctlreq.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F401xC -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ctlreq.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ioreq.o: ../Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ioreq.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F401xC -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ioreq.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_pipes.o: ../Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_pipes.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F401xC -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_pipes.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + diff --git a/Release/USB_HOST/App/subdir.mk b/Release/USB_HOST/App/subdir.mk new file mode 100644 index 0000000..12a7525 --- /dev/null +++ b/Release/USB_HOST/App/subdir.mk @@ -0,0 +1,19 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../USB_HOST/App/usb_host.c + +C_DEPS += \ +./USB_HOST/App/usb_host.d + +OBJS += \ +./USB_HOST/App/usb_host.o + + +# Each subdirectory must supply rules for building sources it contributes +USB_HOST/App/usb_host.o: ../USB_HOST/App/usb_host.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F401xC -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"USB_HOST/App/usb_host.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + diff --git a/Release/USB_HOST/Target/subdir.mk b/Release/USB_HOST/Target/subdir.mk new file mode 100644 index 0000000..d0a4818 --- /dev/null +++ b/Release/USB_HOST/Target/subdir.mk @@ -0,0 +1,24 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../USB_HOST/Target/usbh_conf.c \ +../USB_HOST/Target/usbh_platform.c + +C_DEPS += \ +./USB_HOST/Target/usbh_conf.d \ +./USB_HOST/Target/usbh_platform.d + +OBJS += \ +./USB_HOST/Target/usbh_conf.o \ +./USB_HOST/Target/usbh_platform.o + + +# Each subdirectory must supply rules for building sources it contributes +USB_HOST/Target/usbh_conf.o: ../USB_HOST/Target/usbh_conf.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F401xC -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"USB_HOST/Target/usbh_conf.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +USB_HOST/Target/usbh_platform.o: ../USB_HOST/Target/usbh_platform.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F401xC -c -I../USB_HOST/App -I../USB_HOST/Target -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Middlewares/ST/STM32_USB_Host_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/COMPASS_LEDS" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/LSM303DLHC" -I"D:/Users/Think/Programmation/STM32CUBEIDE/eCompass/Drivers/MY_TYPES" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"USB_HOST/Target/usbh_platform.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + diff --git a/Release/eCompass.bin b/Release/eCompass.bin new file mode 100644 index 0000000..8d85b13 Binary files /dev/null and b/Release/eCompass.bin differ diff --git a/Release/eCompass.list b/Release/eCompass.list new file mode 100644 index 0000000..787c329 --- /dev/null +++ b/Release/eCompass.list @@ -0,0 +1,15575 @@ + +eCompass.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .isr_vector 00000194 08000000 08000000 00010000 2**0 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 1 .text 00009790 080001a0 080001a0 000101a0 2**4 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 .rodata 00000420 08009930 08009930 00019930 2**3 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .ARM.extab 00000000 08009d50 08009d50 000201fc 2**0 + CONTENTS + 4 .ARM 00000008 08009d50 08009d50 00019d50 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 5 .preinit_array 00000000 08009d58 08009d58 000201fc 2**0 + CONTENTS, ALLOC, LOAD, DATA + 6 .init_array 00000004 08009d58 08009d58 00019d58 2**2 + CONTENTS, ALLOC, LOAD, DATA + 7 .fini_array 00000004 08009d5c 08009d5c 00019d5c 2**2 + CONTENTS, ALLOC, LOAD, DATA + 8 .data 000001fc 20000000 08009d60 00020000 2**2 + CONTENTS, ALLOC, LOAD, DATA + 9 .bss 000008b8 200001fc 08009f5c 000201fc 2**2 + ALLOC + 10 ._user_heap_stack 00000604 20000ab4 08009f5c 00020ab4 2**0 + ALLOC + 11 .ARM.attributes 00000030 00000000 00000000 000201fc 2**0 + CONTENTS, READONLY + 12 .comment 0000007b 00000000 00000000 0002022c 2**0 + CONTENTS, READONLY + 13 .debug_frame 000013a8 00000000 00000000 000202a8 2**2 + CONTENTS, READONLY, DEBUGGING + +Disassembly of section .text: + +080001a0 <__do_global_dtors_aux>: + 80001a0: b510 push {r4, lr} + 80001a2: 4c05 ldr r4, [pc, #20] ; (80001b8 <__do_global_dtors_aux+0x18>) + 80001a4: 7823 ldrb r3, [r4, #0] + 80001a6: b933 cbnz r3, 80001b6 <__do_global_dtors_aux+0x16> + 80001a8: 4b04 ldr r3, [pc, #16] ; (80001bc <__do_global_dtors_aux+0x1c>) + 80001aa: b113 cbz r3, 80001b2 <__do_global_dtors_aux+0x12> + 80001ac: 4804 ldr r0, [pc, #16] ; (80001c0 <__do_global_dtors_aux+0x20>) + 80001ae: f3af 8000 nop.w + 80001b2: 2301 movs r3, #1 + 80001b4: 7023 strb r3, [r4, #0] + 80001b6: bd10 pop {r4, pc} + 80001b8: 200001fc .word 0x200001fc + 80001bc: 00000000 .word 0x00000000 + 80001c0: 08009918 .word 0x08009918 + +080001c4 : + 80001c4: b508 push {r3, lr} + 80001c6: 4b03 ldr r3, [pc, #12] ; (80001d4 ) + 80001c8: b11b cbz r3, 80001d2 + 80001ca: 4903 ldr r1, [pc, #12] ; (80001d8 ) + 80001cc: 4803 ldr r0, [pc, #12] ; (80001dc ) + 80001ce: f3af 8000 nop.w + 80001d2: bd08 pop {r3, pc} + 80001d4: 00000000 .word 0x00000000 + 80001d8: 20000200 .word 0x20000200 + 80001dc: 08009918 .word 0x08009918 + +080001e0 : + 80001e0: 4603 mov r3, r0 + 80001e2: f813 2b01 ldrb.w r2, [r3], #1 + 80001e6: 2a00 cmp r2, #0 + 80001e8: d1fb bne.n 80001e2 + 80001ea: 1a18 subs r0, r3, r0 + 80001ec: 3801 subs r0, #1 + 80001ee: 4770 bx lr + +080001f0 : + 80001f0: f001 01ff and.w r1, r1, #255 ; 0xff + 80001f4: 2a10 cmp r2, #16 + 80001f6: db2b blt.n 8000250 + 80001f8: f010 0f07 tst.w r0, #7 + 80001fc: d008 beq.n 8000210 + 80001fe: f810 3b01 ldrb.w r3, [r0], #1 + 8000202: 3a01 subs r2, #1 + 8000204: 428b cmp r3, r1 + 8000206: d02d beq.n 8000264 + 8000208: f010 0f07 tst.w r0, #7 + 800020c: b342 cbz r2, 8000260 + 800020e: d1f6 bne.n 80001fe + 8000210: b4f0 push {r4, r5, r6, r7} + 8000212: ea41 2101 orr.w r1, r1, r1, lsl #8 + 8000216: ea41 4101 orr.w r1, r1, r1, lsl #16 + 800021a: f022 0407 bic.w r4, r2, #7 + 800021e: f07f 0700 mvns.w r7, #0 + 8000222: 2300 movs r3, #0 + 8000224: e8f0 5602 ldrd r5, r6, [r0], #8 + 8000228: 3c08 subs r4, #8 + 800022a: ea85 0501 eor.w r5, r5, r1 + 800022e: ea86 0601 eor.w r6, r6, r1 + 8000232: fa85 f547 uadd8 r5, r5, r7 + 8000236: faa3 f587 sel r5, r3, r7 + 800023a: fa86 f647 uadd8 r6, r6, r7 + 800023e: faa5 f687 sel r6, r5, r7 + 8000242: b98e cbnz r6, 8000268 + 8000244: d1ee bne.n 8000224 + 8000246: bcf0 pop {r4, r5, r6, r7} + 8000248: f001 01ff and.w r1, r1, #255 ; 0xff + 800024c: f002 0207 and.w r2, r2, #7 + 8000250: b132 cbz r2, 8000260 + 8000252: f810 3b01 ldrb.w r3, [r0], #1 + 8000256: 3a01 subs r2, #1 + 8000258: ea83 0301 eor.w r3, r3, r1 + 800025c: b113 cbz r3, 8000264 + 800025e: d1f8 bne.n 8000252 + 8000260: 2000 movs r0, #0 + 8000262: 4770 bx lr + 8000264: 3801 subs r0, #1 + 8000266: 4770 bx lr + 8000268: 2d00 cmp r5, #0 + 800026a: bf06 itte eq + 800026c: 4635 moveq r5, r6 + 800026e: 3803 subeq r0, #3 + 8000270: 3807 subne r0, #7 + 8000272: f015 0f01 tst.w r5, #1 + 8000276: d107 bne.n 8000288 + 8000278: 3001 adds r0, #1 + 800027a: f415 7f80 tst.w r5, #256 ; 0x100 + 800027e: bf02 ittt eq + 8000280: 3001 addeq r0, #1 + 8000282: f415 3fc0 tsteq.w r5, #98304 ; 0x18000 + 8000286: 3001 addeq r0, #1 + 8000288: bcf0 pop {r4, r5, r6, r7} + 800028a: 3801 subs r0, #1 + 800028c: 4770 bx lr + 800028e: bf00 nop + +08000290 <__aeabi_drsub>: + 8000290: f081 4100 eor.w r1, r1, #2147483648 ; 0x80000000 + 8000294: e002 b.n 800029c <__adddf3> + 8000296: bf00 nop + +08000298 <__aeabi_dsub>: + 8000298: f083 4300 eor.w r3, r3, #2147483648 ; 0x80000000 + +0800029c <__adddf3>: + 800029c: b530 push {r4, r5, lr} + 800029e: ea4f 0441 mov.w r4, r1, lsl #1 + 80002a2: ea4f 0543 mov.w r5, r3, lsl #1 + 80002a6: ea94 0f05 teq r4, r5 + 80002aa: bf08 it eq + 80002ac: ea90 0f02 teqeq r0, r2 + 80002b0: bf1f itttt ne + 80002b2: ea54 0c00 orrsne.w ip, r4, r0 + 80002b6: ea55 0c02 orrsne.w ip, r5, r2 + 80002ba: ea7f 5c64 mvnsne.w ip, r4, asr #21 + 80002be: ea7f 5c65 mvnsne.w ip, r5, asr #21 + 80002c2: f000 80e2 beq.w 800048a <__adddf3+0x1ee> + 80002c6: ea4f 5454 mov.w r4, r4, lsr #21 + 80002ca: ebd4 5555 rsbs r5, r4, r5, lsr #21 + 80002ce: bfb8 it lt + 80002d0: 426d neglt r5, r5 + 80002d2: dd0c ble.n 80002ee <__adddf3+0x52> + 80002d4: 442c add r4, r5 + 80002d6: ea80 0202 eor.w r2, r0, r2 + 80002da: ea81 0303 eor.w r3, r1, r3 + 80002de: ea82 0000 eor.w r0, r2, r0 + 80002e2: ea83 0101 eor.w r1, r3, r1 + 80002e6: ea80 0202 eor.w r2, r0, r2 + 80002ea: ea81 0303 eor.w r3, r1, r3 + 80002ee: 2d36 cmp r5, #54 ; 0x36 + 80002f0: bf88 it hi + 80002f2: bd30 pophi {r4, r5, pc} + 80002f4: f011 4f00 tst.w r1, #2147483648 ; 0x80000000 + 80002f8: ea4f 3101 mov.w r1, r1, lsl #12 + 80002fc: f44f 1c80 mov.w ip, #1048576 ; 0x100000 + 8000300: ea4c 3111 orr.w r1, ip, r1, lsr #12 + 8000304: d002 beq.n 800030c <__adddf3+0x70> + 8000306: 4240 negs r0, r0 + 8000308: eb61 0141 sbc.w r1, r1, r1, lsl #1 + 800030c: f013 4f00 tst.w r3, #2147483648 ; 0x80000000 + 8000310: ea4f 3303 mov.w r3, r3, lsl #12 + 8000314: ea4c 3313 orr.w r3, ip, r3, lsr #12 + 8000318: d002 beq.n 8000320 <__adddf3+0x84> + 800031a: 4252 negs r2, r2 + 800031c: eb63 0343 sbc.w r3, r3, r3, lsl #1 + 8000320: ea94 0f05 teq r4, r5 + 8000324: f000 80a7 beq.w 8000476 <__adddf3+0x1da> + 8000328: f1a4 0401 sub.w r4, r4, #1 + 800032c: f1d5 0e20 rsbs lr, r5, #32 + 8000330: db0d blt.n 800034e <__adddf3+0xb2> + 8000332: fa02 fc0e lsl.w ip, r2, lr + 8000336: fa22 f205 lsr.w r2, r2, r5 + 800033a: 1880 adds r0, r0, r2 + 800033c: f141 0100 adc.w r1, r1, #0 + 8000340: fa03 f20e lsl.w r2, r3, lr + 8000344: 1880 adds r0, r0, r2 + 8000346: fa43 f305 asr.w r3, r3, r5 + 800034a: 4159 adcs r1, r3 + 800034c: e00e b.n 800036c <__adddf3+0xd0> + 800034e: f1a5 0520 sub.w r5, r5, #32 + 8000352: f10e 0e20 add.w lr, lr, #32 + 8000356: 2a01 cmp r2, #1 + 8000358: fa03 fc0e lsl.w ip, r3, lr + 800035c: bf28 it cs + 800035e: f04c 0c02 orrcs.w ip, ip, #2 + 8000362: fa43 f305 asr.w r3, r3, r5 + 8000366: 18c0 adds r0, r0, r3 + 8000368: eb51 71e3 adcs.w r1, r1, r3, asr #31 + 800036c: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 + 8000370: d507 bpl.n 8000382 <__adddf3+0xe6> + 8000372: f04f 0e00 mov.w lr, #0 + 8000376: f1dc 0c00 rsbs ip, ip, #0 + 800037a: eb7e 0000 sbcs.w r0, lr, r0 + 800037e: eb6e 0101 sbc.w r1, lr, r1 + 8000382: f5b1 1f80 cmp.w r1, #1048576 ; 0x100000 + 8000386: d31b bcc.n 80003c0 <__adddf3+0x124> + 8000388: f5b1 1f00 cmp.w r1, #2097152 ; 0x200000 + 800038c: d30c bcc.n 80003a8 <__adddf3+0x10c> + 800038e: 0849 lsrs r1, r1, #1 + 8000390: ea5f 0030 movs.w r0, r0, rrx + 8000394: ea4f 0c3c mov.w ip, ip, rrx + 8000398: f104 0401 add.w r4, r4, #1 + 800039c: ea4f 5244 mov.w r2, r4, lsl #21 + 80003a0: f512 0f80 cmn.w r2, #4194304 ; 0x400000 + 80003a4: f080 809a bcs.w 80004dc <__adddf3+0x240> + 80003a8: f1bc 4f00 cmp.w ip, #2147483648 ; 0x80000000 + 80003ac: bf08 it eq + 80003ae: ea5f 0c50 movseq.w ip, r0, lsr #1 + 80003b2: f150 0000 adcs.w r0, r0, #0 + 80003b6: eb41 5104 adc.w r1, r1, r4, lsl #20 + 80003ba: ea41 0105 orr.w r1, r1, r5 + 80003be: bd30 pop {r4, r5, pc} + 80003c0: ea5f 0c4c movs.w ip, ip, lsl #1 + 80003c4: 4140 adcs r0, r0 + 80003c6: eb41 0101 adc.w r1, r1, r1 + 80003ca: f411 1f80 tst.w r1, #1048576 ; 0x100000 + 80003ce: f1a4 0401 sub.w r4, r4, #1 + 80003d2: d1e9 bne.n 80003a8 <__adddf3+0x10c> + 80003d4: f091 0f00 teq r1, #0 + 80003d8: bf04 itt eq + 80003da: 4601 moveq r1, r0 + 80003dc: 2000 moveq r0, #0 + 80003de: fab1 f381 clz r3, r1 + 80003e2: bf08 it eq + 80003e4: 3320 addeq r3, #32 + 80003e6: f1a3 030b sub.w r3, r3, #11 + 80003ea: f1b3 0220 subs.w r2, r3, #32 + 80003ee: da0c bge.n 800040a <__adddf3+0x16e> + 80003f0: 320c adds r2, #12 + 80003f2: dd08 ble.n 8000406 <__adddf3+0x16a> + 80003f4: f102 0c14 add.w ip, r2, #20 + 80003f8: f1c2 020c rsb r2, r2, #12 + 80003fc: fa01 f00c lsl.w r0, r1, ip + 8000400: fa21 f102 lsr.w r1, r1, r2 + 8000404: e00c b.n 8000420 <__adddf3+0x184> + 8000406: f102 0214 add.w r2, r2, #20 + 800040a: bfd8 it le + 800040c: f1c2 0c20 rsble ip, r2, #32 + 8000410: fa01 f102 lsl.w r1, r1, r2 + 8000414: fa20 fc0c lsr.w ip, r0, ip + 8000418: bfdc itt le + 800041a: ea41 010c orrle.w r1, r1, ip + 800041e: 4090 lslle r0, r2 + 8000420: 1ae4 subs r4, r4, r3 + 8000422: bfa2 ittt ge + 8000424: eb01 5104 addge.w r1, r1, r4, lsl #20 + 8000428: 4329 orrge r1, r5 + 800042a: bd30 popge {r4, r5, pc} + 800042c: ea6f 0404 mvn.w r4, r4 + 8000430: 3c1f subs r4, #31 + 8000432: da1c bge.n 800046e <__adddf3+0x1d2> + 8000434: 340c adds r4, #12 + 8000436: dc0e bgt.n 8000456 <__adddf3+0x1ba> + 8000438: f104 0414 add.w r4, r4, #20 + 800043c: f1c4 0220 rsb r2, r4, #32 + 8000440: fa20 f004 lsr.w r0, r0, r4 + 8000444: fa01 f302 lsl.w r3, r1, r2 + 8000448: ea40 0003 orr.w r0, r0, r3 + 800044c: fa21 f304 lsr.w r3, r1, r4 + 8000450: ea45 0103 orr.w r1, r5, r3 + 8000454: bd30 pop {r4, r5, pc} + 8000456: f1c4 040c rsb r4, r4, #12 + 800045a: f1c4 0220 rsb r2, r4, #32 + 800045e: fa20 f002 lsr.w r0, r0, r2 + 8000462: fa01 f304 lsl.w r3, r1, r4 + 8000466: ea40 0003 orr.w r0, r0, r3 + 800046a: 4629 mov r1, r5 + 800046c: bd30 pop {r4, r5, pc} + 800046e: fa21 f004 lsr.w r0, r1, r4 + 8000472: 4629 mov r1, r5 + 8000474: bd30 pop {r4, r5, pc} + 8000476: f094 0f00 teq r4, #0 + 800047a: f483 1380 eor.w r3, r3, #1048576 ; 0x100000 + 800047e: bf06 itte eq + 8000480: f481 1180 eoreq.w r1, r1, #1048576 ; 0x100000 + 8000484: 3401 addeq r4, #1 + 8000486: 3d01 subne r5, #1 + 8000488: e74e b.n 8000328 <__adddf3+0x8c> + 800048a: ea7f 5c64 mvns.w ip, r4, asr #21 + 800048e: bf18 it ne + 8000490: ea7f 5c65 mvnsne.w ip, r5, asr #21 + 8000494: d029 beq.n 80004ea <__adddf3+0x24e> + 8000496: ea94 0f05 teq r4, r5 + 800049a: bf08 it eq + 800049c: ea90 0f02 teqeq r0, r2 + 80004a0: d005 beq.n 80004ae <__adddf3+0x212> + 80004a2: ea54 0c00 orrs.w ip, r4, r0 + 80004a6: bf04 itt eq + 80004a8: 4619 moveq r1, r3 + 80004aa: 4610 moveq r0, r2 + 80004ac: bd30 pop {r4, r5, pc} + 80004ae: ea91 0f03 teq r1, r3 + 80004b2: bf1e ittt ne + 80004b4: 2100 movne r1, #0 + 80004b6: 2000 movne r0, #0 + 80004b8: bd30 popne {r4, r5, pc} + 80004ba: ea5f 5c54 movs.w ip, r4, lsr #21 + 80004be: d105 bne.n 80004cc <__adddf3+0x230> + 80004c0: 0040 lsls r0, r0, #1 + 80004c2: 4149 adcs r1, r1 + 80004c4: bf28 it cs + 80004c6: f041 4100 orrcs.w r1, r1, #2147483648 ; 0x80000000 + 80004ca: bd30 pop {r4, r5, pc} + 80004cc: f514 0480 adds.w r4, r4, #4194304 ; 0x400000 + 80004d0: bf3c itt cc + 80004d2: f501 1180 addcc.w r1, r1, #1048576 ; 0x100000 + 80004d6: bd30 popcc {r4, r5, pc} + 80004d8: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 + 80004dc: f045 41fe orr.w r1, r5, #2130706432 ; 0x7f000000 + 80004e0: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000 + 80004e4: f04f 0000 mov.w r0, #0 + 80004e8: bd30 pop {r4, r5, pc} + 80004ea: ea7f 5c64 mvns.w ip, r4, asr #21 + 80004ee: bf1a itte ne + 80004f0: 4619 movne r1, r3 + 80004f2: 4610 movne r0, r2 + 80004f4: ea7f 5c65 mvnseq.w ip, r5, asr #21 + 80004f8: bf1c itt ne + 80004fa: 460b movne r3, r1 + 80004fc: 4602 movne r2, r0 + 80004fe: ea50 3401 orrs.w r4, r0, r1, lsl #12 + 8000502: bf06 itte eq + 8000504: ea52 3503 orrseq.w r5, r2, r3, lsl #12 + 8000508: ea91 0f03 teqeq r1, r3 + 800050c: f441 2100 orrne.w r1, r1, #524288 ; 0x80000 + 8000510: bd30 pop {r4, r5, pc} + 8000512: bf00 nop + +08000514 <__aeabi_ui2d>: + 8000514: f090 0f00 teq r0, #0 + 8000518: bf04 itt eq + 800051a: 2100 moveq r1, #0 + 800051c: 4770 bxeq lr + 800051e: b530 push {r4, r5, lr} + 8000520: f44f 6480 mov.w r4, #1024 ; 0x400 + 8000524: f104 0432 add.w r4, r4, #50 ; 0x32 + 8000528: f04f 0500 mov.w r5, #0 + 800052c: f04f 0100 mov.w r1, #0 + 8000530: e750 b.n 80003d4 <__adddf3+0x138> + 8000532: bf00 nop + +08000534 <__aeabi_i2d>: + 8000534: f090 0f00 teq r0, #0 + 8000538: bf04 itt eq + 800053a: 2100 moveq r1, #0 + 800053c: 4770 bxeq lr + 800053e: b530 push {r4, r5, lr} + 8000540: f44f 6480 mov.w r4, #1024 ; 0x400 + 8000544: f104 0432 add.w r4, r4, #50 ; 0x32 + 8000548: f010 4500 ands.w r5, r0, #2147483648 ; 0x80000000 + 800054c: bf48 it mi + 800054e: 4240 negmi r0, r0 + 8000550: f04f 0100 mov.w r1, #0 + 8000554: e73e b.n 80003d4 <__adddf3+0x138> + 8000556: bf00 nop + +08000558 <__aeabi_f2d>: + 8000558: 0042 lsls r2, r0, #1 + 800055a: ea4f 01e2 mov.w r1, r2, asr #3 + 800055e: ea4f 0131 mov.w r1, r1, rrx + 8000562: ea4f 7002 mov.w r0, r2, lsl #28 + 8000566: bf1f itttt ne + 8000568: f012 437f andsne.w r3, r2, #4278190080 ; 0xff000000 + 800056c: f093 4f7f teqne r3, #4278190080 ; 0xff000000 + 8000570: f081 5160 eorne.w r1, r1, #939524096 ; 0x38000000 + 8000574: 4770 bxne lr + 8000576: f032 427f bics.w r2, r2, #4278190080 ; 0xff000000 + 800057a: bf08 it eq + 800057c: 4770 bxeq lr + 800057e: f093 4f7f teq r3, #4278190080 ; 0xff000000 + 8000582: bf04 itt eq + 8000584: f441 2100 orreq.w r1, r1, #524288 ; 0x80000 + 8000588: 4770 bxeq lr + 800058a: b530 push {r4, r5, lr} + 800058c: f44f 7460 mov.w r4, #896 ; 0x380 + 8000590: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 + 8000594: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000 + 8000598: e71c b.n 80003d4 <__adddf3+0x138> + 800059a: bf00 nop + +0800059c <__aeabi_ul2d>: + 800059c: ea50 0201 orrs.w r2, r0, r1 + 80005a0: bf08 it eq + 80005a2: 4770 bxeq lr + 80005a4: b530 push {r4, r5, lr} + 80005a6: f04f 0500 mov.w r5, #0 + 80005aa: e00a b.n 80005c2 <__aeabi_l2d+0x16> + +080005ac <__aeabi_l2d>: + 80005ac: ea50 0201 orrs.w r2, r0, r1 + 80005b0: bf08 it eq + 80005b2: 4770 bxeq lr + 80005b4: b530 push {r4, r5, lr} + 80005b6: f011 4500 ands.w r5, r1, #2147483648 ; 0x80000000 + 80005ba: d502 bpl.n 80005c2 <__aeabi_l2d+0x16> + 80005bc: 4240 negs r0, r0 + 80005be: eb61 0141 sbc.w r1, r1, r1, lsl #1 + 80005c2: f44f 6480 mov.w r4, #1024 ; 0x400 + 80005c6: f104 0432 add.w r4, r4, #50 ; 0x32 + 80005ca: ea5f 5c91 movs.w ip, r1, lsr #22 + 80005ce: f43f aed8 beq.w 8000382 <__adddf3+0xe6> + 80005d2: f04f 0203 mov.w r2, #3 + 80005d6: ea5f 0cdc movs.w ip, ip, lsr #3 + 80005da: bf18 it ne + 80005dc: 3203 addne r2, #3 + 80005de: ea5f 0cdc movs.w ip, ip, lsr #3 + 80005e2: bf18 it ne + 80005e4: 3203 addne r2, #3 + 80005e6: eb02 02dc add.w r2, r2, ip, lsr #3 + 80005ea: f1c2 0320 rsb r3, r2, #32 + 80005ee: fa00 fc03 lsl.w ip, r0, r3 + 80005f2: fa20 f002 lsr.w r0, r0, r2 + 80005f6: fa01 fe03 lsl.w lr, r1, r3 + 80005fa: ea40 000e orr.w r0, r0, lr + 80005fe: fa21 f102 lsr.w r1, r1, r2 + 8000602: 4414 add r4, r2 + 8000604: e6bd b.n 8000382 <__adddf3+0xe6> + 8000606: bf00 nop + +08000608 <__aeabi_dmul>: + 8000608: b570 push {r4, r5, r6, lr} + 800060a: f04f 0cff mov.w ip, #255 ; 0xff + 800060e: f44c 6ce0 orr.w ip, ip, #1792 ; 0x700 + 8000612: ea1c 5411 ands.w r4, ip, r1, lsr #20 + 8000616: bf1d ittte ne + 8000618: ea1c 5513 andsne.w r5, ip, r3, lsr #20 + 800061c: ea94 0f0c teqne r4, ip + 8000620: ea95 0f0c teqne r5, ip + 8000624: f000 f8de bleq 80007e4 <__aeabi_dmul+0x1dc> + 8000628: 442c add r4, r5 + 800062a: ea81 0603 eor.w r6, r1, r3 + 800062e: ea21 514c bic.w r1, r1, ip, lsl #21 + 8000632: ea23 534c bic.w r3, r3, ip, lsl #21 + 8000636: ea50 3501 orrs.w r5, r0, r1, lsl #12 + 800063a: bf18 it ne + 800063c: ea52 3503 orrsne.w r5, r2, r3, lsl #12 + 8000640: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 + 8000644: f443 1380 orr.w r3, r3, #1048576 ; 0x100000 + 8000648: d038 beq.n 80006bc <__aeabi_dmul+0xb4> + 800064a: fba0 ce02 umull ip, lr, r0, r2 + 800064e: f04f 0500 mov.w r5, #0 + 8000652: fbe1 e502 umlal lr, r5, r1, r2 + 8000656: f006 4200 and.w r2, r6, #2147483648 ; 0x80000000 + 800065a: fbe0 e503 umlal lr, r5, r0, r3 + 800065e: f04f 0600 mov.w r6, #0 + 8000662: fbe1 5603 umlal r5, r6, r1, r3 + 8000666: f09c 0f00 teq ip, #0 + 800066a: bf18 it ne + 800066c: f04e 0e01 orrne.w lr, lr, #1 + 8000670: f1a4 04ff sub.w r4, r4, #255 ; 0xff + 8000674: f5b6 7f00 cmp.w r6, #512 ; 0x200 + 8000678: f564 7440 sbc.w r4, r4, #768 ; 0x300 + 800067c: d204 bcs.n 8000688 <__aeabi_dmul+0x80> + 800067e: ea5f 0e4e movs.w lr, lr, lsl #1 + 8000682: 416d adcs r5, r5 + 8000684: eb46 0606 adc.w r6, r6, r6 + 8000688: ea42 21c6 orr.w r1, r2, r6, lsl #11 + 800068c: ea41 5155 orr.w r1, r1, r5, lsr #21 + 8000690: ea4f 20c5 mov.w r0, r5, lsl #11 + 8000694: ea40 505e orr.w r0, r0, lr, lsr #21 + 8000698: ea4f 2ece mov.w lr, lr, lsl #11 + 800069c: f1b4 0cfd subs.w ip, r4, #253 ; 0xfd + 80006a0: bf88 it hi + 80006a2: f5bc 6fe0 cmphi.w ip, #1792 ; 0x700 + 80006a6: d81e bhi.n 80006e6 <__aeabi_dmul+0xde> + 80006a8: f1be 4f00 cmp.w lr, #2147483648 ; 0x80000000 + 80006ac: bf08 it eq + 80006ae: ea5f 0e50 movseq.w lr, r0, lsr #1 + 80006b2: f150 0000 adcs.w r0, r0, #0 + 80006b6: eb41 5104 adc.w r1, r1, r4, lsl #20 + 80006ba: bd70 pop {r4, r5, r6, pc} + 80006bc: f006 4600 and.w r6, r6, #2147483648 ; 0x80000000 + 80006c0: ea46 0101 orr.w r1, r6, r1 + 80006c4: ea40 0002 orr.w r0, r0, r2 + 80006c8: ea81 0103 eor.w r1, r1, r3 + 80006cc: ebb4 045c subs.w r4, r4, ip, lsr #1 + 80006d0: bfc2 ittt gt + 80006d2: ebd4 050c rsbsgt r5, r4, ip + 80006d6: ea41 5104 orrgt.w r1, r1, r4, lsl #20 + 80006da: bd70 popgt {r4, r5, r6, pc} + 80006dc: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 + 80006e0: f04f 0e00 mov.w lr, #0 + 80006e4: 3c01 subs r4, #1 + 80006e6: f300 80ab bgt.w 8000840 <__aeabi_dmul+0x238> + 80006ea: f114 0f36 cmn.w r4, #54 ; 0x36 + 80006ee: bfde ittt le + 80006f0: 2000 movle r0, #0 + 80006f2: f001 4100 andle.w r1, r1, #2147483648 ; 0x80000000 + 80006f6: bd70 pople {r4, r5, r6, pc} + 80006f8: f1c4 0400 rsb r4, r4, #0 + 80006fc: 3c20 subs r4, #32 + 80006fe: da35 bge.n 800076c <__aeabi_dmul+0x164> + 8000700: 340c adds r4, #12 + 8000702: dc1b bgt.n 800073c <__aeabi_dmul+0x134> + 8000704: f104 0414 add.w r4, r4, #20 + 8000708: f1c4 0520 rsb r5, r4, #32 + 800070c: fa00 f305 lsl.w r3, r0, r5 + 8000710: fa20 f004 lsr.w r0, r0, r4 + 8000714: fa01 f205 lsl.w r2, r1, r5 + 8000718: ea40 0002 orr.w r0, r0, r2 + 800071c: f001 4200 and.w r2, r1, #2147483648 ; 0x80000000 + 8000720: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000 + 8000724: eb10 70d3 adds.w r0, r0, r3, lsr #31 + 8000728: fa21 f604 lsr.w r6, r1, r4 + 800072c: eb42 0106 adc.w r1, r2, r6 + 8000730: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 + 8000734: bf08 it eq + 8000736: ea20 70d3 biceq.w r0, r0, r3, lsr #31 + 800073a: bd70 pop {r4, r5, r6, pc} + 800073c: f1c4 040c rsb r4, r4, #12 + 8000740: f1c4 0520 rsb r5, r4, #32 + 8000744: fa00 f304 lsl.w r3, r0, r4 + 8000748: fa20 f005 lsr.w r0, r0, r5 + 800074c: fa01 f204 lsl.w r2, r1, r4 + 8000750: ea40 0002 orr.w r0, r0, r2 + 8000754: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 + 8000758: eb10 70d3 adds.w r0, r0, r3, lsr #31 + 800075c: f141 0100 adc.w r1, r1, #0 + 8000760: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 + 8000764: bf08 it eq + 8000766: ea20 70d3 biceq.w r0, r0, r3, lsr #31 + 800076a: bd70 pop {r4, r5, r6, pc} + 800076c: f1c4 0520 rsb r5, r4, #32 + 8000770: fa00 f205 lsl.w r2, r0, r5 + 8000774: ea4e 0e02 orr.w lr, lr, r2 + 8000778: fa20 f304 lsr.w r3, r0, r4 + 800077c: fa01 f205 lsl.w r2, r1, r5 + 8000780: ea43 0302 orr.w r3, r3, r2 + 8000784: fa21 f004 lsr.w r0, r1, r4 + 8000788: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 + 800078c: fa21 f204 lsr.w r2, r1, r4 + 8000790: ea20 0002 bic.w r0, r0, r2 + 8000794: eb00 70d3 add.w r0, r0, r3, lsr #31 + 8000798: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 + 800079c: bf08 it eq + 800079e: ea20 70d3 biceq.w r0, r0, r3, lsr #31 + 80007a2: bd70 pop {r4, r5, r6, pc} + 80007a4: f094 0f00 teq r4, #0 + 80007a8: d10f bne.n 80007ca <__aeabi_dmul+0x1c2> + 80007aa: f001 4600 and.w r6, r1, #2147483648 ; 0x80000000 + 80007ae: 0040 lsls r0, r0, #1 + 80007b0: eb41 0101 adc.w r1, r1, r1 + 80007b4: f411 1f80 tst.w r1, #1048576 ; 0x100000 + 80007b8: bf08 it eq + 80007ba: 3c01 subeq r4, #1 + 80007bc: d0f7 beq.n 80007ae <__aeabi_dmul+0x1a6> + 80007be: ea41 0106 orr.w r1, r1, r6 + 80007c2: f095 0f00 teq r5, #0 + 80007c6: bf18 it ne + 80007c8: 4770 bxne lr + 80007ca: f003 4600 and.w r6, r3, #2147483648 ; 0x80000000 + 80007ce: 0052 lsls r2, r2, #1 + 80007d0: eb43 0303 adc.w r3, r3, r3 + 80007d4: f413 1f80 tst.w r3, #1048576 ; 0x100000 + 80007d8: bf08 it eq + 80007da: 3d01 subeq r5, #1 + 80007dc: d0f7 beq.n 80007ce <__aeabi_dmul+0x1c6> + 80007de: ea43 0306 orr.w r3, r3, r6 + 80007e2: 4770 bx lr + 80007e4: ea94 0f0c teq r4, ip + 80007e8: ea0c 5513 and.w r5, ip, r3, lsr #20 + 80007ec: bf18 it ne + 80007ee: ea95 0f0c teqne r5, ip + 80007f2: d00c beq.n 800080e <__aeabi_dmul+0x206> + 80007f4: ea50 0641 orrs.w r6, r0, r1, lsl #1 + 80007f8: bf18 it ne + 80007fa: ea52 0643 orrsne.w r6, r2, r3, lsl #1 + 80007fe: d1d1 bne.n 80007a4 <__aeabi_dmul+0x19c> + 8000800: ea81 0103 eor.w r1, r1, r3 + 8000804: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 + 8000808: f04f 0000 mov.w r0, #0 + 800080c: bd70 pop {r4, r5, r6, pc} + 800080e: ea50 0641 orrs.w r6, r0, r1, lsl #1 + 8000812: bf06 itte eq + 8000814: 4610 moveq r0, r2 + 8000816: 4619 moveq r1, r3 + 8000818: ea52 0643 orrsne.w r6, r2, r3, lsl #1 + 800081c: d019 beq.n 8000852 <__aeabi_dmul+0x24a> + 800081e: ea94 0f0c teq r4, ip + 8000822: d102 bne.n 800082a <__aeabi_dmul+0x222> + 8000824: ea50 3601 orrs.w r6, r0, r1, lsl #12 + 8000828: d113 bne.n 8000852 <__aeabi_dmul+0x24a> + 800082a: ea95 0f0c teq r5, ip + 800082e: d105 bne.n 800083c <__aeabi_dmul+0x234> + 8000830: ea52 3603 orrs.w r6, r2, r3, lsl #12 + 8000834: bf1c itt ne + 8000836: 4610 movne r0, r2 + 8000838: 4619 movne r1, r3 + 800083a: d10a bne.n 8000852 <__aeabi_dmul+0x24a> + 800083c: ea81 0103 eor.w r1, r1, r3 + 8000840: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 + 8000844: f041 41fe orr.w r1, r1, #2130706432 ; 0x7f000000 + 8000848: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000 + 800084c: f04f 0000 mov.w r0, #0 + 8000850: bd70 pop {r4, r5, r6, pc} + 8000852: f041 41fe orr.w r1, r1, #2130706432 ; 0x7f000000 + 8000856: f441 0178 orr.w r1, r1, #16252928 ; 0xf80000 + 800085a: bd70 pop {r4, r5, r6, pc} + +0800085c <__aeabi_ddiv>: + 800085c: b570 push {r4, r5, r6, lr} + 800085e: f04f 0cff mov.w ip, #255 ; 0xff + 8000862: f44c 6ce0 orr.w ip, ip, #1792 ; 0x700 + 8000866: ea1c 5411 ands.w r4, ip, r1, lsr #20 + 800086a: bf1d ittte ne + 800086c: ea1c 5513 andsne.w r5, ip, r3, lsr #20 + 8000870: ea94 0f0c teqne r4, ip + 8000874: ea95 0f0c teqne r5, ip + 8000878: f000 f8a7 bleq 80009ca <__aeabi_ddiv+0x16e> + 800087c: eba4 0405 sub.w r4, r4, r5 + 8000880: ea81 0e03 eor.w lr, r1, r3 + 8000884: ea52 3503 orrs.w r5, r2, r3, lsl #12 + 8000888: ea4f 3101 mov.w r1, r1, lsl #12 + 800088c: f000 8088 beq.w 80009a0 <__aeabi_ddiv+0x144> + 8000890: ea4f 3303 mov.w r3, r3, lsl #12 + 8000894: f04f 5580 mov.w r5, #268435456 ; 0x10000000 + 8000898: ea45 1313 orr.w r3, r5, r3, lsr #4 + 800089c: ea43 6312 orr.w r3, r3, r2, lsr #24 + 80008a0: ea4f 2202 mov.w r2, r2, lsl #8 + 80008a4: ea45 1511 orr.w r5, r5, r1, lsr #4 + 80008a8: ea45 6510 orr.w r5, r5, r0, lsr #24 + 80008ac: ea4f 2600 mov.w r6, r0, lsl #8 + 80008b0: f00e 4100 and.w r1, lr, #2147483648 ; 0x80000000 + 80008b4: 429d cmp r5, r3 + 80008b6: bf08 it eq + 80008b8: 4296 cmpeq r6, r2 + 80008ba: f144 04fd adc.w r4, r4, #253 ; 0xfd + 80008be: f504 7440 add.w r4, r4, #768 ; 0x300 + 80008c2: d202 bcs.n 80008ca <__aeabi_ddiv+0x6e> + 80008c4: 085b lsrs r3, r3, #1 + 80008c6: ea4f 0232 mov.w r2, r2, rrx + 80008ca: 1ab6 subs r6, r6, r2 + 80008cc: eb65 0503 sbc.w r5, r5, r3 + 80008d0: 085b lsrs r3, r3, #1 + 80008d2: ea4f 0232 mov.w r2, r2, rrx + 80008d6: f44f 1080 mov.w r0, #1048576 ; 0x100000 + 80008da: f44f 2c00 mov.w ip, #524288 ; 0x80000 + 80008de: ebb6 0e02 subs.w lr, r6, r2 + 80008e2: eb75 0e03 sbcs.w lr, r5, r3 + 80008e6: bf22 ittt cs + 80008e8: 1ab6 subcs r6, r6, r2 + 80008ea: 4675 movcs r5, lr + 80008ec: ea40 000c orrcs.w r0, r0, ip + 80008f0: 085b lsrs r3, r3, #1 + 80008f2: ea4f 0232 mov.w r2, r2, rrx + 80008f6: ebb6 0e02 subs.w lr, r6, r2 + 80008fa: eb75 0e03 sbcs.w lr, r5, r3 + 80008fe: bf22 ittt cs + 8000900: 1ab6 subcs r6, r6, r2 + 8000902: 4675 movcs r5, lr + 8000904: ea40 005c orrcs.w r0, r0, ip, lsr #1 + 8000908: 085b lsrs r3, r3, #1 + 800090a: ea4f 0232 mov.w r2, r2, rrx + 800090e: ebb6 0e02 subs.w lr, r6, r2 + 8000912: eb75 0e03 sbcs.w lr, r5, r3 + 8000916: bf22 ittt cs + 8000918: 1ab6 subcs r6, r6, r2 + 800091a: 4675 movcs r5, lr + 800091c: ea40 009c orrcs.w r0, r0, ip, lsr #2 + 8000920: 085b lsrs r3, r3, #1 + 8000922: ea4f 0232 mov.w r2, r2, rrx + 8000926: ebb6 0e02 subs.w lr, r6, r2 + 800092a: eb75 0e03 sbcs.w lr, r5, r3 + 800092e: bf22 ittt cs + 8000930: 1ab6 subcs r6, r6, r2 + 8000932: 4675 movcs r5, lr + 8000934: ea40 00dc orrcs.w r0, r0, ip, lsr #3 + 8000938: ea55 0e06 orrs.w lr, r5, r6 + 800093c: d018 beq.n 8000970 <__aeabi_ddiv+0x114> + 800093e: ea4f 1505 mov.w r5, r5, lsl #4 + 8000942: ea45 7516 orr.w r5, r5, r6, lsr #28 + 8000946: ea4f 1606 mov.w r6, r6, lsl #4 + 800094a: ea4f 03c3 mov.w r3, r3, lsl #3 + 800094e: ea43 7352 orr.w r3, r3, r2, lsr #29 + 8000952: ea4f 02c2 mov.w r2, r2, lsl #3 + 8000956: ea5f 1c1c movs.w ip, ip, lsr #4 + 800095a: d1c0 bne.n 80008de <__aeabi_ddiv+0x82> + 800095c: f411 1f80 tst.w r1, #1048576 ; 0x100000 + 8000960: d10b bne.n 800097a <__aeabi_ddiv+0x11e> + 8000962: ea41 0100 orr.w r1, r1, r0 + 8000966: f04f 0000 mov.w r0, #0 + 800096a: f04f 4c00 mov.w ip, #2147483648 ; 0x80000000 + 800096e: e7b6 b.n 80008de <__aeabi_ddiv+0x82> + 8000970: f411 1f80 tst.w r1, #1048576 ; 0x100000 + 8000974: bf04 itt eq + 8000976: 4301 orreq r1, r0 + 8000978: 2000 moveq r0, #0 + 800097a: f1b4 0cfd subs.w ip, r4, #253 ; 0xfd + 800097e: bf88 it hi + 8000980: f5bc 6fe0 cmphi.w ip, #1792 ; 0x700 + 8000984: f63f aeaf bhi.w 80006e6 <__aeabi_dmul+0xde> + 8000988: ebb5 0c03 subs.w ip, r5, r3 + 800098c: bf04 itt eq + 800098e: ebb6 0c02 subseq.w ip, r6, r2 + 8000992: ea5f 0c50 movseq.w ip, r0, lsr #1 + 8000996: f150 0000 adcs.w r0, r0, #0 + 800099a: eb41 5104 adc.w r1, r1, r4, lsl #20 + 800099e: bd70 pop {r4, r5, r6, pc} + 80009a0: f00e 4e00 and.w lr, lr, #2147483648 ; 0x80000000 + 80009a4: ea4e 3111 orr.w r1, lr, r1, lsr #12 + 80009a8: eb14 045c adds.w r4, r4, ip, lsr #1 + 80009ac: bfc2 ittt gt + 80009ae: ebd4 050c rsbsgt r5, r4, ip + 80009b2: ea41 5104 orrgt.w r1, r1, r4, lsl #20 + 80009b6: bd70 popgt {r4, r5, r6, pc} + 80009b8: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 + 80009bc: f04f 0e00 mov.w lr, #0 + 80009c0: 3c01 subs r4, #1 + 80009c2: e690 b.n 80006e6 <__aeabi_dmul+0xde> + 80009c4: ea45 0e06 orr.w lr, r5, r6 + 80009c8: e68d b.n 80006e6 <__aeabi_dmul+0xde> + 80009ca: ea0c 5513 and.w r5, ip, r3, lsr #20 + 80009ce: ea94 0f0c teq r4, ip + 80009d2: bf08 it eq + 80009d4: ea95 0f0c teqeq r5, ip + 80009d8: f43f af3b beq.w 8000852 <__aeabi_dmul+0x24a> + 80009dc: ea94 0f0c teq r4, ip + 80009e0: d10a bne.n 80009f8 <__aeabi_ddiv+0x19c> + 80009e2: ea50 3401 orrs.w r4, r0, r1, lsl #12 + 80009e6: f47f af34 bne.w 8000852 <__aeabi_dmul+0x24a> + 80009ea: ea95 0f0c teq r5, ip + 80009ee: f47f af25 bne.w 800083c <__aeabi_dmul+0x234> + 80009f2: 4610 mov r0, r2 + 80009f4: 4619 mov r1, r3 + 80009f6: e72c b.n 8000852 <__aeabi_dmul+0x24a> + 80009f8: ea95 0f0c teq r5, ip + 80009fc: d106 bne.n 8000a0c <__aeabi_ddiv+0x1b0> + 80009fe: ea52 3503 orrs.w r5, r2, r3, lsl #12 + 8000a02: f43f aefd beq.w 8000800 <__aeabi_dmul+0x1f8> + 8000a06: 4610 mov r0, r2 + 8000a08: 4619 mov r1, r3 + 8000a0a: e722 b.n 8000852 <__aeabi_dmul+0x24a> + 8000a0c: ea50 0641 orrs.w r6, r0, r1, lsl #1 + 8000a10: bf18 it ne + 8000a12: ea52 0643 orrsne.w r6, r2, r3, lsl #1 + 8000a16: f47f aec5 bne.w 80007a4 <__aeabi_dmul+0x19c> + 8000a1a: ea50 0441 orrs.w r4, r0, r1, lsl #1 + 8000a1e: f47f af0d bne.w 800083c <__aeabi_dmul+0x234> + 8000a22: ea52 0543 orrs.w r5, r2, r3, lsl #1 + 8000a26: f47f aeeb bne.w 8000800 <__aeabi_dmul+0x1f8> + 8000a2a: e712 b.n 8000852 <__aeabi_dmul+0x24a> + +08000a2c <__gedf2>: + 8000a2c: f04f 3cff mov.w ip, #4294967295 + 8000a30: e006 b.n 8000a40 <__cmpdf2+0x4> + 8000a32: bf00 nop + +08000a34 <__ledf2>: + 8000a34: f04f 0c01 mov.w ip, #1 + 8000a38: e002 b.n 8000a40 <__cmpdf2+0x4> + 8000a3a: bf00 nop + +08000a3c <__cmpdf2>: + 8000a3c: f04f 0c01 mov.w ip, #1 + 8000a40: f84d cd04 str.w ip, [sp, #-4]! + 8000a44: ea4f 0c41 mov.w ip, r1, lsl #1 + 8000a48: ea7f 5c6c mvns.w ip, ip, asr #21 + 8000a4c: ea4f 0c43 mov.w ip, r3, lsl #1 + 8000a50: bf18 it ne + 8000a52: ea7f 5c6c mvnsne.w ip, ip, asr #21 + 8000a56: d01b beq.n 8000a90 <__cmpdf2+0x54> + 8000a58: b001 add sp, #4 + 8000a5a: ea50 0c41 orrs.w ip, r0, r1, lsl #1 + 8000a5e: bf0c ite eq + 8000a60: ea52 0c43 orrseq.w ip, r2, r3, lsl #1 + 8000a64: ea91 0f03 teqne r1, r3 + 8000a68: bf02 ittt eq + 8000a6a: ea90 0f02 teqeq r0, r2 + 8000a6e: 2000 moveq r0, #0 + 8000a70: 4770 bxeq lr + 8000a72: f110 0f00 cmn.w r0, #0 + 8000a76: ea91 0f03 teq r1, r3 + 8000a7a: bf58 it pl + 8000a7c: 4299 cmppl r1, r3 + 8000a7e: bf08 it eq + 8000a80: 4290 cmpeq r0, r2 + 8000a82: bf2c ite cs + 8000a84: 17d8 asrcs r0, r3, #31 + 8000a86: ea6f 70e3 mvncc.w r0, r3, asr #31 + 8000a8a: f040 0001 orr.w r0, r0, #1 + 8000a8e: 4770 bx lr + 8000a90: ea4f 0c41 mov.w ip, r1, lsl #1 + 8000a94: ea7f 5c6c mvns.w ip, ip, asr #21 + 8000a98: d102 bne.n 8000aa0 <__cmpdf2+0x64> + 8000a9a: ea50 3c01 orrs.w ip, r0, r1, lsl #12 + 8000a9e: d107 bne.n 8000ab0 <__cmpdf2+0x74> + 8000aa0: ea4f 0c43 mov.w ip, r3, lsl #1 + 8000aa4: ea7f 5c6c mvns.w ip, ip, asr #21 + 8000aa8: d1d6 bne.n 8000a58 <__cmpdf2+0x1c> + 8000aaa: ea52 3c03 orrs.w ip, r2, r3, lsl #12 + 8000aae: d0d3 beq.n 8000a58 <__cmpdf2+0x1c> + 8000ab0: f85d 0b04 ldr.w r0, [sp], #4 + 8000ab4: 4770 bx lr + 8000ab6: bf00 nop + +08000ab8 <__aeabi_cdrcmple>: + 8000ab8: 4684 mov ip, r0 + 8000aba: 4610 mov r0, r2 + 8000abc: 4662 mov r2, ip + 8000abe: 468c mov ip, r1 + 8000ac0: 4619 mov r1, r3 + 8000ac2: 4663 mov r3, ip + 8000ac4: e000 b.n 8000ac8 <__aeabi_cdcmpeq> + 8000ac6: bf00 nop + +08000ac8 <__aeabi_cdcmpeq>: + 8000ac8: b501 push {r0, lr} + 8000aca: f7ff ffb7 bl 8000a3c <__cmpdf2> + 8000ace: 2800 cmp r0, #0 + 8000ad0: bf48 it mi + 8000ad2: f110 0f00 cmnmi.w r0, #0 + 8000ad6: bd01 pop {r0, pc} + +08000ad8 <__aeabi_dcmpeq>: + 8000ad8: f84d ed08 str.w lr, [sp, #-8]! + 8000adc: f7ff fff4 bl 8000ac8 <__aeabi_cdcmpeq> + 8000ae0: bf0c ite eq + 8000ae2: 2001 moveq r0, #1 + 8000ae4: 2000 movne r0, #0 + 8000ae6: f85d fb08 ldr.w pc, [sp], #8 + 8000aea: bf00 nop + +08000aec <__aeabi_dcmplt>: + 8000aec: f84d ed08 str.w lr, [sp, #-8]! + 8000af0: f7ff ffea bl 8000ac8 <__aeabi_cdcmpeq> + 8000af4: bf34 ite cc + 8000af6: 2001 movcc r0, #1 + 8000af8: 2000 movcs r0, #0 + 8000afa: f85d fb08 ldr.w pc, [sp], #8 + 8000afe: bf00 nop + +08000b00 <__aeabi_dcmple>: + 8000b00: f84d ed08 str.w lr, [sp, #-8]! + 8000b04: f7ff ffe0 bl 8000ac8 <__aeabi_cdcmpeq> + 8000b08: bf94 ite ls + 8000b0a: 2001 movls r0, #1 + 8000b0c: 2000 movhi r0, #0 + 8000b0e: f85d fb08 ldr.w pc, [sp], #8 + 8000b12: bf00 nop + +08000b14 <__aeabi_dcmpge>: + 8000b14: f84d ed08 str.w lr, [sp, #-8]! + 8000b18: f7ff ffce bl 8000ab8 <__aeabi_cdrcmple> + 8000b1c: bf94 ite ls + 8000b1e: 2001 movls r0, #1 + 8000b20: 2000 movhi r0, #0 + 8000b22: f85d fb08 ldr.w pc, [sp], #8 + 8000b26: bf00 nop + +08000b28 <__aeabi_dcmpgt>: + 8000b28: f84d ed08 str.w lr, [sp, #-8]! + 8000b2c: f7ff ffc4 bl 8000ab8 <__aeabi_cdrcmple> + 8000b30: bf34 ite cc + 8000b32: 2001 movcc r0, #1 + 8000b34: 2000 movcs r0, #0 + 8000b36: f85d fb08 ldr.w pc, [sp], #8 + 8000b3a: bf00 nop + +08000b3c <__aeabi_dcmpun>: + 8000b3c: ea4f 0c41 mov.w ip, r1, lsl #1 + 8000b40: ea7f 5c6c mvns.w ip, ip, asr #21 + 8000b44: d102 bne.n 8000b4c <__aeabi_dcmpun+0x10> + 8000b46: ea50 3c01 orrs.w ip, r0, r1, lsl #12 + 8000b4a: d10a bne.n 8000b62 <__aeabi_dcmpun+0x26> + 8000b4c: ea4f 0c43 mov.w ip, r3, lsl #1 + 8000b50: ea7f 5c6c mvns.w ip, ip, asr #21 + 8000b54: d102 bne.n 8000b5c <__aeabi_dcmpun+0x20> + 8000b56: ea52 3c03 orrs.w ip, r2, r3, lsl #12 + 8000b5a: d102 bne.n 8000b62 <__aeabi_dcmpun+0x26> + 8000b5c: f04f 0000 mov.w r0, #0 + 8000b60: 4770 bx lr + 8000b62: f04f 0001 mov.w r0, #1 + 8000b66: 4770 bx lr + +08000b68 <__aeabi_d2iz>: + 8000b68: ea4f 0241 mov.w r2, r1, lsl #1 + 8000b6c: f512 1200 adds.w r2, r2, #2097152 ; 0x200000 + 8000b70: d215 bcs.n 8000b9e <__aeabi_d2iz+0x36> + 8000b72: d511 bpl.n 8000b98 <__aeabi_d2iz+0x30> + 8000b74: f46f 7378 mvn.w r3, #992 ; 0x3e0 + 8000b78: ebb3 5262 subs.w r2, r3, r2, asr #21 + 8000b7c: d912 bls.n 8000ba4 <__aeabi_d2iz+0x3c> + 8000b7e: ea4f 23c1 mov.w r3, r1, lsl #11 + 8000b82: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 + 8000b86: ea43 5350 orr.w r3, r3, r0, lsr #21 + 8000b8a: f011 4f00 tst.w r1, #2147483648 ; 0x80000000 + 8000b8e: fa23 f002 lsr.w r0, r3, r2 + 8000b92: bf18 it ne + 8000b94: 4240 negne r0, r0 + 8000b96: 4770 bx lr + 8000b98: f04f 0000 mov.w r0, #0 + 8000b9c: 4770 bx lr + 8000b9e: ea50 3001 orrs.w r0, r0, r1, lsl #12 + 8000ba2: d105 bne.n 8000bb0 <__aeabi_d2iz+0x48> + 8000ba4: f011 4000 ands.w r0, r1, #2147483648 ; 0x80000000 + 8000ba8: bf08 it eq + 8000baa: f06f 4000 mvneq.w r0, #2147483648 ; 0x80000000 + 8000bae: 4770 bx lr + 8000bb0: f04f 0000 mov.w r0, #0 + 8000bb4: 4770 bx lr + 8000bb6: bf00 nop + +08000bb8 <__aeabi_d2uiz>: + 8000bb8: 004a lsls r2, r1, #1 + 8000bba: d211 bcs.n 8000be0 <__aeabi_d2uiz+0x28> + 8000bbc: f512 1200 adds.w r2, r2, #2097152 ; 0x200000 + 8000bc0: d211 bcs.n 8000be6 <__aeabi_d2uiz+0x2e> + 8000bc2: d50d bpl.n 8000be0 <__aeabi_d2uiz+0x28> + 8000bc4: f46f 7378 mvn.w r3, #992 ; 0x3e0 + 8000bc8: ebb3 5262 subs.w r2, r3, r2, asr #21 + 8000bcc: d40e bmi.n 8000bec <__aeabi_d2uiz+0x34> + 8000bce: ea4f 23c1 mov.w r3, r1, lsl #11 + 8000bd2: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 + 8000bd6: ea43 5350 orr.w r3, r3, r0, lsr #21 + 8000bda: fa23 f002 lsr.w r0, r3, r2 + 8000bde: 4770 bx lr + 8000be0: f04f 0000 mov.w r0, #0 + 8000be4: 4770 bx lr + 8000be6: ea50 3001 orrs.w r0, r0, r1, lsl #12 + 8000bea: d102 bne.n 8000bf2 <__aeabi_d2uiz+0x3a> + 8000bec: f04f 30ff mov.w r0, #4294967295 + 8000bf0: 4770 bx lr + 8000bf2: f04f 0000 mov.w r0, #0 + 8000bf6: 4770 bx lr + +08000bf8 <__aeabi_d2f>: + 8000bf8: ea4f 0241 mov.w r2, r1, lsl #1 + 8000bfc: f1b2 43e0 subs.w r3, r2, #1879048192 ; 0x70000000 + 8000c00: bf24 itt cs + 8000c02: f5b3 1c00 subscs.w ip, r3, #2097152 ; 0x200000 + 8000c06: f1dc 5cfe rsbscs ip, ip, #532676608 ; 0x1fc00000 + 8000c0a: d90d bls.n 8000c28 <__aeabi_d2f+0x30> + 8000c0c: f001 4c00 and.w ip, r1, #2147483648 ; 0x80000000 + 8000c10: ea4f 02c0 mov.w r2, r0, lsl #3 + 8000c14: ea4c 7050 orr.w r0, ip, r0, lsr #29 + 8000c18: f1b2 4f00 cmp.w r2, #2147483648 ; 0x80000000 + 8000c1c: eb40 0083 adc.w r0, r0, r3, lsl #2 + 8000c20: bf08 it eq + 8000c22: f020 0001 biceq.w r0, r0, #1 + 8000c26: 4770 bx lr + 8000c28: f011 4f80 tst.w r1, #1073741824 ; 0x40000000 + 8000c2c: d121 bne.n 8000c72 <__aeabi_d2f+0x7a> + 8000c2e: f113 7238 adds.w r2, r3, #48234496 ; 0x2e00000 + 8000c32: bfbc itt lt + 8000c34: f001 4000 andlt.w r0, r1, #2147483648 ; 0x80000000 + 8000c38: 4770 bxlt lr + 8000c3a: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 + 8000c3e: ea4f 5252 mov.w r2, r2, lsr #21 + 8000c42: f1c2 0218 rsb r2, r2, #24 + 8000c46: f1c2 0c20 rsb ip, r2, #32 + 8000c4a: fa10 f30c lsls.w r3, r0, ip + 8000c4e: fa20 f002 lsr.w r0, r0, r2 + 8000c52: bf18 it ne + 8000c54: f040 0001 orrne.w r0, r0, #1 + 8000c58: ea4f 23c1 mov.w r3, r1, lsl #11 + 8000c5c: ea4f 23d3 mov.w r3, r3, lsr #11 + 8000c60: fa03 fc0c lsl.w ip, r3, ip + 8000c64: ea40 000c orr.w r0, r0, ip + 8000c68: fa23 f302 lsr.w r3, r3, r2 + 8000c6c: ea4f 0343 mov.w r3, r3, lsl #1 + 8000c70: e7cc b.n 8000c0c <__aeabi_d2f+0x14> + 8000c72: ea7f 5362 mvns.w r3, r2, asr #21 + 8000c76: d107 bne.n 8000c88 <__aeabi_d2f+0x90> + 8000c78: ea50 3301 orrs.w r3, r0, r1, lsl #12 + 8000c7c: bf1e ittt ne + 8000c7e: f04f 40fe movne.w r0, #2130706432 ; 0x7f000000 + 8000c82: f440 0040 orrne.w r0, r0, #12582912 ; 0xc00000 + 8000c86: 4770 bxne lr + 8000c88: f001 4000 and.w r0, r1, #2147483648 ; 0x80000000 + 8000c8c: f040 40fe orr.w r0, r0, #2130706432 ; 0x7f000000 + 8000c90: f440 0000 orr.w r0, r0, #8388608 ; 0x800000 + 8000c94: 4770 bx lr + 8000c96: bf00 nop + +08000c98 <__aeabi_uldivmod>: + 8000c98: b953 cbnz r3, 8000cb0 <__aeabi_uldivmod+0x18> + 8000c9a: b94a cbnz r2, 8000cb0 <__aeabi_uldivmod+0x18> + 8000c9c: 2900 cmp r1, #0 + 8000c9e: bf08 it eq + 8000ca0: 2800 cmpeq r0, #0 + 8000ca2: bf1c itt ne + 8000ca4: f04f 31ff movne.w r1, #4294967295 + 8000ca8: f04f 30ff movne.w r0, #4294967295 + 8000cac: f000 b972 b.w 8000f94 <__aeabi_idiv0> + 8000cb0: f1ad 0c08 sub.w ip, sp, #8 + 8000cb4: e96d ce04 strd ip, lr, [sp, #-16]! + 8000cb8: f000 f806 bl 8000cc8 <__udivmoddi4> + 8000cbc: f8dd e004 ldr.w lr, [sp, #4] + 8000cc0: e9dd 2302 ldrd r2, r3, [sp, #8] + 8000cc4: b004 add sp, #16 + 8000cc6: 4770 bx lr + +08000cc8 <__udivmoddi4>: + 8000cc8: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 8000ccc: 9e08 ldr r6, [sp, #32] + 8000cce: 4604 mov r4, r0 + 8000cd0: 4688 mov r8, r1 + 8000cd2: 2b00 cmp r3, #0 + 8000cd4: d14b bne.n 8000d6e <__udivmoddi4+0xa6> + 8000cd6: 428a cmp r2, r1 + 8000cd8: 4615 mov r5, r2 + 8000cda: d967 bls.n 8000dac <__udivmoddi4+0xe4> + 8000cdc: fab2 f282 clz r2, r2 + 8000ce0: b14a cbz r2, 8000cf6 <__udivmoddi4+0x2e> + 8000ce2: f1c2 0720 rsb r7, r2, #32 + 8000ce6: fa01 f302 lsl.w r3, r1, r2 + 8000cea: fa20 f707 lsr.w r7, r0, r7 + 8000cee: 4095 lsls r5, r2 + 8000cf0: ea47 0803 orr.w r8, r7, r3 + 8000cf4: 4094 lsls r4, r2 + 8000cf6: ea4f 4e15 mov.w lr, r5, lsr #16 + 8000cfa: 0c23 lsrs r3, r4, #16 + 8000cfc: fbb8 f7fe udiv r7, r8, lr + 8000d00: fa1f fc85 uxth.w ip, r5 + 8000d04: fb0e 8817 mls r8, lr, r7, r8 + 8000d08: ea43 4308 orr.w r3, r3, r8, lsl #16 + 8000d0c: fb07 f10c mul.w r1, r7, ip + 8000d10: 4299 cmp r1, r3 + 8000d12: d909 bls.n 8000d28 <__udivmoddi4+0x60> + 8000d14: 18eb adds r3, r5, r3 + 8000d16: f107 30ff add.w r0, r7, #4294967295 + 8000d1a: f080 811b bcs.w 8000f54 <__udivmoddi4+0x28c> + 8000d1e: 4299 cmp r1, r3 + 8000d20: f240 8118 bls.w 8000f54 <__udivmoddi4+0x28c> + 8000d24: 3f02 subs r7, #2 + 8000d26: 442b add r3, r5 + 8000d28: 1a5b subs r3, r3, r1 + 8000d2a: b2a4 uxth r4, r4 + 8000d2c: fbb3 f0fe udiv r0, r3, lr + 8000d30: fb0e 3310 mls r3, lr, r0, r3 + 8000d34: ea44 4403 orr.w r4, r4, r3, lsl #16 + 8000d38: fb00 fc0c mul.w ip, r0, ip + 8000d3c: 45a4 cmp ip, r4 + 8000d3e: d909 bls.n 8000d54 <__udivmoddi4+0x8c> + 8000d40: 192c adds r4, r5, r4 + 8000d42: f100 33ff add.w r3, r0, #4294967295 + 8000d46: f080 8107 bcs.w 8000f58 <__udivmoddi4+0x290> + 8000d4a: 45a4 cmp ip, r4 + 8000d4c: f240 8104 bls.w 8000f58 <__udivmoddi4+0x290> + 8000d50: 3802 subs r0, #2 + 8000d52: 442c add r4, r5 + 8000d54: ea40 4007 orr.w r0, r0, r7, lsl #16 + 8000d58: eba4 040c sub.w r4, r4, ip + 8000d5c: 2700 movs r7, #0 + 8000d5e: b11e cbz r6, 8000d68 <__udivmoddi4+0xa0> + 8000d60: 40d4 lsrs r4, r2 + 8000d62: 2300 movs r3, #0 + 8000d64: e9c6 4300 strd r4, r3, [r6] + 8000d68: 4639 mov r1, r7 + 8000d6a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 8000d6e: 428b cmp r3, r1 + 8000d70: d909 bls.n 8000d86 <__udivmoddi4+0xbe> + 8000d72: 2e00 cmp r6, #0 + 8000d74: f000 80eb beq.w 8000f4e <__udivmoddi4+0x286> + 8000d78: 2700 movs r7, #0 + 8000d7a: e9c6 0100 strd r0, r1, [r6] + 8000d7e: 4638 mov r0, r7 + 8000d80: 4639 mov r1, r7 + 8000d82: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 8000d86: fab3 f783 clz r7, r3 + 8000d8a: 2f00 cmp r7, #0 + 8000d8c: d147 bne.n 8000e1e <__udivmoddi4+0x156> + 8000d8e: 428b cmp r3, r1 + 8000d90: d302 bcc.n 8000d98 <__udivmoddi4+0xd0> + 8000d92: 4282 cmp r2, r0 + 8000d94: f200 80fa bhi.w 8000f8c <__udivmoddi4+0x2c4> + 8000d98: 1a84 subs r4, r0, r2 + 8000d9a: eb61 0303 sbc.w r3, r1, r3 + 8000d9e: 2001 movs r0, #1 + 8000da0: 4698 mov r8, r3 + 8000da2: 2e00 cmp r6, #0 + 8000da4: d0e0 beq.n 8000d68 <__udivmoddi4+0xa0> + 8000da6: e9c6 4800 strd r4, r8, [r6] + 8000daa: e7dd b.n 8000d68 <__udivmoddi4+0xa0> + 8000dac: b902 cbnz r2, 8000db0 <__udivmoddi4+0xe8> + 8000dae: deff udf #255 ; 0xff + 8000db0: fab2 f282 clz r2, r2 + 8000db4: 2a00 cmp r2, #0 + 8000db6: f040 808f bne.w 8000ed8 <__udivmoddi4+0x210> + 8000dba: 1b49 subs r1, r1, r5 + 8000dbc: ea4f 4e15 mov.w lr, r5, lsr #16 + 8000dc0: fa1f f885 uxth.w r8, r5 + 8000dc4: 2701 movs r7, #1 + 8000dc6: fbb1 fcfe udiv ip, r1, lr + 8000dca: 0c23 lsrs r3, r4, #16 + 8000dcc: fb0e 111c mls r1, lr, ip, r1 + 8000dd0: ea43 4301 orr.w r3, r3, r1, lsl #16 + 8000dd4: fb08 f10c mul.w r1, r8, ip + 8000dd8: 4299 cmp r1, r3 + 8000dda: d907 bls.n 8000dec <__udivmoddi4+0x124> + 8000ddc: 18eb adds r3, r5, r3 + 8000dde: f10c 30ff add.w r0, ip, #4294967295 + 8000de2: d202 bcs.n 8000dea <__udivmoddi4+0x122> + 8000de4: 4299 cmp r1, r3 + 8000de6: f200 80cd bhi.w 8000f84 <__udivmoddi4+0x2bc> + 8000dea: 4684 mov ip, r0 + 8000dec: 1a59 subs r1, r3, r1 + 8000dee: b2a3 uxth r3, r4 + 8000df0: fbb1 f0fe udiv r0, r1, lr + 8000df4: fb0e 1410 mls r4, lr, r0, r1 + 8000df8: ea43 4404 orr.w r4, r3, r4, lsl #16 + 8000dfc: fb08 f800 mul.w r8, r8, r0 + 8000e00: 45a0 cmp r8, r4 + 8000e02: d907 bls.n 8000e14 <__udivmoddi4+0x14c> + 8000e04: 192c adds r4, r5, r4 + 8000e06: f100 33ff add.w r3, r0, #4294967295 + 8000e0a: d202 bcs.n 8000e12 <__udivmoddi4+0x14a> + 8000e0c: 45a0 cmp r8, r4 + 8000e0e: f200 80b6 bhi.w 8000f7e <__udivmoddi4+0x2b6> + 8000e12: 4618 mov r0, r3 + 8000e14: eba4 0408 sub.w r4, r4, r8 + 8000e18: ea40 400c orr.w r0, r0, ip, lsl #16 + 8000e1c: e79f b.n 8000d5e <__udivmoddi4+0x96> + 8000e1e: f1c7 0c20 rsb ip, r7, #32 + 8000e22: 40bb lsls r3, r7 + 8000e24: fa22 fe0c lsr.w lr, r2, ip + 8000e28: ea4e 0e03 orr.w lr, lr, r3 + 8000e2c: fa01 f407 lsl.w r4, r1, r7 + 8000e30: fa20 f50c lsr.w r5, r0, ip + 8000e34: fa21 f30c lsr.w r3, r1, ip + 8000e38: ea4f 481e mov.w r8, lr, lsr #16 + 8000e3c: 4325 orrs r5, r4 + 8000e3e: fbb3 f9f8 udiv r9, r3, r8 + 8000e42: 0c2c lsrs r4, r5, #16 + 8000e44: fb08 3319 mls r3, r8, r9, r3 + 8000e48: fa1f fa8e uxth.w sl, lr + 8000e4c: ea44 4303 orr.w r3, r4, r3, lsl #16 + 8000e50: fb09 f40a mul.w r4, r9, sl + 8000e54: 429c cmp r4, r3 + 8000e56: fa02 f207 lsl.w r2, r2, r7 + 8000e5a: fa00 f107 lsl.w r1, r0, r7 + 8000e5e: d90b bls.n 8000e78 <__udivmoddi4+0x1b0> + 8000e60: eb1e 0303 adds.w r3, lr, r3 + 8000e64: f109 30ff add.w r0, r9, #4294967295 + 8000e68: f080 8087 bcs.w 8000f7a <__udivmoddi4+0x2b2> + 8000e6c: 429c cmp r4, r3 + 8000e6e: f240 8084 bls.w 8000f7a <__udivmoddi4+0x2b2> + 8000e72: f1a9 0902 sub.w r9, r9, #2 + 8000e76: 4473 add r3, lr + 8000e78: 1b1b subs r3, r3, r4 + 8000e7a: b2ad uxth r5, r5 + 8000e7c: fbb3 f0f8 udiv r0, r3, r8 + 8000e80: fb08 3310 mls r3, r8, r0, r3 + 8000e84: ea45 4403 orr.w r4, r5, r3, lsl #16 + 8000e88: fb00 fa0a mul.w sl, r0, sl + 8000e8c: 45a2 cmp sl, r4 + 8000e8e: d908 bls.n 8000ea2 <__udivmoddi4+0x1da> + 8000e90: eb1e 0404 adds.w r4, lr, r4 + 8000e94: f100 33ff add.w r3, r0, #4294967295 + 8000e98: d26b bcs.n 8000f72 <__udivmoddi4+0x2aa> + 8000e9a: 45a2 cmp sl, r4 + 8000e9c: d969 bls.n 8000f72 <__udivmoddi4+0x2aa> + 8000e9e: 3802 subs r0, #2 + 8000ea0: 4474 add r4, lr + 8000ea2: ea40 4009 orr.w r0, r0, r9, lsl #16 + 8000ea6: fba0 8902 umull r8, r9, r0, r2 + 8000eaa: eba4 040a sub.w r4, r4, sl + 8000eae: 454c cmp r4, r9 + 8000eb0: 46c2 mov sl, r8 + 8000eb2: 464b mov r3, r9 + 8000eb4: d354 bcc.n 8000f60 <__udivmoddi4+0x298> + 8000eb6: d051 beq.n 8000f5c <__udivmoddi4+0x294> + 8000eb8: 2e00 cmp r6, #0 + 8000eba: d069 beq.n 8000f90 <__udivmoddi4+0x2c8> + 8000ebc: ebb1 050a subs.w r5, r1, sl + 8000ec0: eb64 0403 sbc.w r4, r4, r3 + 8000ec4: fa04 fc0c lsl.w ip, r4, ip + 8000ec8: 40fd lsrs r5, r7 + 8000eca: 40fc lsrs r4, r7 + 8000ecc: ea4c 0505 orr.w r5, ip, r5 + 8000ed0: e9c6 5400 strd r5, r4, [r6] + 8000ed4: 2700 movs r7, #0 + 8000ed6: e747 b.n 8000d68 <__udivmoddi4+0xa0> + 8000ed8: f1c2 0320 rsb r3, r2, #32 + 8000edc: fa20 f703 lsr.w r7, r0, r3 + 8000ee0: 4095 lsls r5, r2 + 8000ee2: fa01 f002 lsl.w r0, r1, r2 + 8000ee6: fa21 f303 lsr.w r3, r1, r3 + 8000eea: ea4f 4e15 mov.w lr, r5, lsr #16 + 8000eee: 4338 orrs r0, r7 + 8000ef0: 0c01 lsrs r1, r0, #16 + 8000ef2: fbb3 f7fe udiv r7, r3, lr + 8000ef6: fa1f f885 uxth.w r8, r5 + 8000efa: fb0e 3317 mls r3, lr, r7, r3 + 8000efe: ea41 4103 orr.w r1, r1, r3, lsl #16 + 8000f02: fb07 f308 mul.w r3, r7, r8 + 8000f06: 428b cmp r3, r1 + 8000f08: fa04 f402 lsl.w r4, r4, r2 + 8000f0c: d907 bls.n 8000f1e <__udivmoddi4+0x256> + 8000f0e: 1869 adds r1, r5, r1 + 8000f10: f107 3cff add.w ip, r7, #4294967295 + 8000f14: d22f bcs.n 8000f76 <__udivmoddi4+0x2ae> + 8000f16: 428b cmp r3, r1 + 8000f18: d92d bls.n 8000f76 <__udivmoddi4+0x2ae> + 8000f1a: 3f02 subs r7, #2 + 8000f1c: 4429 add r1, r5 + 8000f1e: 1acb subs r3, r1, r3 + 8000f20: b281 uxth r1, r0 + 8000f22: fbb3 f0fe udiv r0, r3, lr + 8000f26: fb0e 3310 mls r3, lr, r0, r3 + 8000f2a: ea41 4103 orr.w r1, r1, r3, lsl #16 + 8000f2e: fb00 f308 mul.w r3, r0, r8 + 8000f32: 428b cmp r3, r1 + 8000f34: d907 bls.n 8000f46 <__udivmoddi4+0x27e> + 8000f36: 1869 adds r1, r5, r1 + 8000f38: f100 3cff add.w ip, r0, #4294967295 + 8000f3c: d217 bcs.n 8000f6e <__udivmoddi4+0x2a6> + 8000f3e: 428b cmp r3, r1 + 8000f40: d915 bls.n 8000f6e <__udivmoddi4+0x2a6> + 8000f42: 3802 subs r0, #2 + 8000f44: 4429 add r1, r5 + 8000f46: 1ac9 subs r1, r1, r3 + 8000f48: ea40 4707 orr.w r7, r0, r7, lsl #16 + 8000f4c: e73b b.n 8000dc6 <__udivmoddi4+0xfe> + 8000f4e: 4637 mov r7, r6 + 8000f50: 4630 mov r0, r6 + 8000f52: e709 b.n 8000d68 <__udivmoddi4+0xa0> + 8000f54: 4607 mov r7, r0 + 8000f56: e6e7 b.n 8000d28 <__udivmoddi4+0x60> + 8000f58: 4618 mov r0, r3 + 8000f5a: e6fb b.n 8000d54 <__udivmoddi4+0x8c> + 8000f5c: 4541 cmp r1, r8 + 8000f5e: d2ab bcs.n 8000eb8 <__udivmoddi4+0x1f0> + 8000f60: ebb8 0a02 subs.w sl, r8, r2 + 8000f64: eb69 020e sbc.w r2, r9, lr + 8000f68: 3801 subs r0, #1 + 8000f6a: 4613 mov r3, r2 + 8000f6c: e7a4 b.n 8000eb8 <__udivmoddi4+0x1f0> + 8000f6e: 4660 mov r0, ip + 8000f70: e7e9 b.n 8000f46 <__udivmoddi4+0x27e> + 8000f72: 4618 mov r0, r3 + 8000f74: e795 b.n 8000ea2 <__udivmoddi4+0x1da> + 8000f76: 4667 mov r7, ip + 8000f78: e7d1 b.n 8000f1e <__udivmoddi4+0x256> + 8000f7a: 4681 mov r9, r0 + 8000f7c: e77c b.n 8000e78 <__udivmoddi4+0x1b0> + 8000f7e: 3802 subs r0, #2 + 8000f80: 442c add r4, r5 + 8000f82: e747 b.n 8000e14 <__udivmoddi4+0x14c> + 8000f84: f1ac 0c02 sub.w ip, ip, #2 + 8000f88: 442b add r3, r5 + 8000f8a: e72f b.n 8000dec <__udivmoddi4+0x124> + 8000f8c: 4638 mov r0, r7 + 8000f8e: e708 b.n 8000da2 <__udivmoddi4+0xda> + 8000f90: 4637 mov r7, r6 + 8000f92: e6e9 b.n 8000d68 <__udivmoddi4+0xa0> + +08000f94 <__aeabi_idiv0>: + 8000f94: 4770 bx lr + 8000f96: bf00 nop + +08000f98 : + 8000f98: b510 push {r4, lr} + 8000f9a: 4816 ldr r0, [pc, #88] ; (8000ff4 ) + 8000f9c: f000 fc40 bl 8001820 + 8000fa0: 4915 ldr r1, [pc, #84] ; (8000ff8 ) + 8000fa2: 4816 ldr r0, [pc, #88] ; (8000ffc ) + 8000fa4: f000 fcca bl 800193c + 8000fa8: b910 cbnz r0, 8000fb0 + 8000faa: 4815 ldr r0, [pc, #84] ; (8001000 ) + 8000fac: f005 f9d8 bl 8006360 + 8000fb0: 2101 movs r1, #1 + 8000fb2: 4812 ldr r0, [pc, #72] ; (8000ffc ) + 8000fb4: f000 fccf bl 8001956 + 8000fb8: b910 cbnz r0, 8000fc0 + 8000fba: 4812 ldr r0, [pc, #72] ; (8001004 ) + 8000fbc: f005 f9d0 bl 8006360 + 8000fc0: 480e ldr r0, [pc, #56] ; (8000ffc ) + 8000fc2: f000 fda0 bl 8001b06 + 8000fc6: b910 cbnz r0, 8000fce + 8000fc8: 480f ldr r0, [pc, #60] ; (8001008 ) + 8000fca: f005 f9c9 bl 8006360 + 8000fce: 4c0f ldr r4, [pc, #60] ; (800100c ) + 8000fd0: 480a ldr r0, [pc, #40] ; (8000ffc ) + 8000fd2: 4621 mov r1, r4 + 8000fd4: f000 fcc6 bl 8001964 + 8000fd8: b920 cbnz r0, 8000fe4 + 8000fda: 480d ldr r0, [pc, #52] ; (8001010 ) + 8000fdc: e8bd 4010 ldmia.w sp!, {r4, lr} + 8000fe0: f005 b9be b.w 8006360 + 8000fe4: 78a3 ldrb r3, [r4, #2] + 8000fe6: 7862 ldrb r2, [r4, #1] + 8000fe8: 7821 ldrb r1, [r4, #0] + 8000fea: 480a ldr r0, [pc, #40] ; (8001014 ) + 8000fec: e8bd 4010 ldmia.w sp!, {r4, lr} + 8000ff0: f005 b942 b.w 8006278 + 8000ff4: 20000244 .word 0x20000244 + 8000ff8: 20000294 .word 0x20000294 + 8000ffc: 2000023c .word 0x2000023c + 8001000: 08009992 .word 0x08009992 + 8001004: 080099ab .word 0x080099ab + 8001008: 080099c9 .word 0x080099c9 + 800100c: 20000218 .word 0x20000218 + 8001010: 080099e1 .word 0x080099e1 + 8001014: 080099f8 .word 0x080099f8 + +08001018 : + 8001018: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} + 800101a: 4e3e ldr r6, [pc, #248] ; (8001114 ) + 800101c: 4d3e ldr r5, [pc, #248] ; (8001118 ) + 800101e: 4c3f ldr r4, [pc, #252] ; (800111c ) + 8001020: f000 fde4 bl 8001bec + 8001024: 6832 ldr r2, [r6, #0] + 8001026: 1a80 subs r0, r0, r2 + 8001028: 2864 cmp r0, #100 ; 0x64 + 800102a: d91b bls.n 8001064 + 800102c: a902 add r1, sp, #8 + 800102e: 2300 movs r3, #0 + 8001030: f841 3d04 str.w r3, [r1, #-4]! + 8001034: 2200 movs r2, #0 + 8001036: 483a ldr r0, [pc, #232] ; (8001120 ) + 8001038: f000 fcb4 bl 80019a4 + 800103c: 2800 cmp r0, #0 + 800103e: d155 bne.n 80010ec + 8001040: 4838 ldr r0, [pc, #224] ; (8001124 ) + 8001042: f005 f98d bl 8006360 + 8001046: 4f38 ldr r7, [pc, #224] ; (8001128 ) + 8001048: 4a33 ldr r2, [pc, #204] ; (8001118 ) + 800104a: 4934 ldr r1, [pc, #208] ; (800111c ) + 800104c: 4834 ldr r0, [pc, #208] ; (8001120 ) + 800104e: 463b mov r3, r7 + 8001050: f000 fcde bl 8001a10 + 8001054: 2800 cmp r0, #0 + 8001056: d152 bne.n 80010fe + 8001058: 4834 ldr r0, [pc, #208] ; (800112c ) + 800105a: f005 f981 bl 8006360 + 800105e: f000 fdc5 bl 8001bec + 8001062: 6030 str r0, [r6, #0] + 8001064: f9b4 2000 ldrsh.w r2, [r4] + 8001068: 2a00 cmp r2, #0 + 800106a: dd0b ble.n 8001084 + 800106c: f9b5 3000 ldrsh.w r3, [r5] + 8001070: 2b00 cmp r3, #0 + 8001072: bfb8 it lt + 8001074: 425b neglt r3, r3 + 8001076: 3b31 subs r3, #49 ; 0x31 + 8001078: 4293 cmp r3, r2 + 800107a: dc03 bgt.n 8001084 + 800107c: 2101 movs r1, #1 + 800107e: 482c ldr r0, [pc, #176] ; (8001130 ) + 8001080: f000 fc12 bl 80018a8 + 8001084: f9b4 2000 ldrsh.w r2, [r4] + 8001088: 2a00 cmp r2, #0 + 800108a: da0c bge.n 80010a6 + 800108c: f9b5 3000 ldrsh.w r3, [r5] + 8001090: 2b00 cmp r3, #0 + 8001092: bfb8 it lt + 8001094: 425b neglt r3, r3 + 8001096: 3b31 subs r3, #49 ; 0x31 + 8001098: 4252 negs r2, r2 + 800109a: 4293 cmp r3, r2 + 800109c: dc03 bgt.n 80010a6 + 800109e: 2102 movs r1, #2 + 80010a0: 4823 ldr r0, [pc, #140] ; (8001130 ) + 80010a2: f000 fc01 bl 80018a8 + 80010a6: f9b5 2000 ldrsh.w r2, [r5] + 80010aa: 2a00 cmp r2, #0 + 80010ac: dd0b ble.n 80010c6 + 80010ae: f9b4 3000 ldrsh.w r3, [r4] + 80010b2: 2b00 cmp r3, #0 + 80010b4: bfb8 it lt + 80010b6: 425b neglt r3, r3 + 80010b8: 3b31 subs r3, #49 ; 0x31 + 80010ba: 4293 cmp r3, r2 + 80010bc: dc03 bgt.n 80010c6 + 80010be: 2108 movs r1, #8 + 80010c0: 481b ldr r0, [pc, #108] ; (8001130 ) + 80010c2: f000 fbf1 bl 80018a8 + 80010c6: f9b5 2000 ldrsh.w r2, [r5] + 80010ca: 2a00 cmp r2, #0 + 80010cc: da0c bge.n 80010e8 + 80010ce: f9b4 3000 ldrsh.w r3, [r4] + 80010d2: 2b00 cmp r3, #0 + 80010d4: bfb8 it lt + 80010d6: 425b neglt r3, r3 + 80010d8: 3b31 subs r3, #49 ; 0x31 + 80010da: 4252 negs r2, r2 + 80010dc: 4293 cmp r3, r2 + 80010de: dc03 bgt.n 80010e8 + 80010e0: 2104 movs r1, #4 + 80010e2: 4813 ldr r0, [pc, #76] ; (8001130 ) + 80010e4: f000 fbe0 bl 80018a8 + 80010e8: b003 add sp, #12 + 80010ea: bdf0 pop {r4, r5, r6, r7, pc} + 80010ec: 9801 ldr r0, [sp, #4] + 80010ee: f7ff fa33 bl 8000558 <__aeabi_f2d> + 80010f2: 4602 mov r2, r0 + 80010f4: 460b mov r3, r1 + 80010f6: 480f ldr r0, [pc, #60] ; (8001134 ) + 80010f8: f005 f8be bl 8006278 + 80010fc: e7a3 b.n 8001046 + 80010fe: f9b7 3000 ldrsh.w r3, [r7] + 8001102: f9b5 2000 ldrsh.w r2, [r5] + 8001106: f9b4 1000 ldrsh.w r1, [r4] + 800110a: 480b ldr r0, [pc, #44] ; (8001138 ) + 800110c: f005 f8b4 bl 8006278 + 8001110: e7a5 b.n 800105e + 8001112: bf00 nop + 8001114: 2000021c .word 0x2000021c + 8001118: 20000222 .word 0x20000222 + 800111c: 20000220 .word 0x20000220 + 8001120: 2000023c .word 0x2000023c + 8001124: 08009930 .word 0x08009930 + 8001128: 20000224 .word 0x20000224 + 800112c: 0800995c .word 0x0800995c + 8001130: 20000244 .word 0x20000244 + 8001134: 0800994b .word 0x0800994b + 8001138: 08009979 .word 0x08009979 + +0800113c <__io_putchar>: + 800113c: b507 push {r0, r1, r2, lr} + 800113e: a902 add r1, sp, #8 + 8001140: f04f 33ff mov.w r3, #4294967295 + 8001144: f841 0d04 str.w r0, [r1, #-4]! + 8001148: 2201 movs r2, #1 + 800114a: 4803 ldr r0, [pc, #12] ; (8001158 <__io_putchar+0x1c>) + 800114c: f002 fd6e bl 8003c2c + 8001150: 9801 ldr r0, [sp, #4] + 8001152: b003 add sp, #12 + 8001154: f85d fb04 ldr.w pc, [sp], #4 + 8001158: 20000340 .word 0x20000340 + +0800115c : + 800115c: b530 push {r4, r5, lr} + 800115e: b099 sub sp, #100 ; 0x64 + 8001160: 2210 movs r2, #16 + 8001162: 2100 movs r1, #0 + 8001164: a80e add r0, sp, #56 ; 0x38 + 8001166: f004 f999 bl 800549c + 800116a: 2214 movs r2, #20 + 800116c: 2100 movs r1, #0 + 800116e: a802 add r0, sp, #8 + 8001170: f004 f994 bl 800549c + 8001174: 2214 movs r2, #20 + 8001176: 2100 movs r1, #0 + 8001178: a807 add r0, sp, #28 + 800117a: f004 f98f bl 800549c + 800117e: 2100 movs r1, #0 + 8001180: 4b25 ldr r3, [pc, #148] ; (8001218 ) + 8001182: 9100 str r1, [sp, #0] + 8001184: 6c1a ldr r2, [r3, #64] ; 0x40 + 8001186: f042 5280 orr.w r2, r2, #268435456 ; 0x10000000 + 800118a: 641a str r2, [r3, #64] ; 0x40 + 800118c: 6c1b ldr r3, [r3, #64] ; 0x40 + 800118e: 4a23 ldr r2, [pc, #140] ; (800121c ) + 8001190: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8001194: 9300 str r3, [sp, #0] + 8001196: 9b00 ldr r3, [sp, #0] + 8001198: 9101 str r1, [sp, #4] + 800119a: 6813 ldr r3, [r2, #0] + 800119c: f423 4340 bic.w r3, r3, #49152 ; 0xc000 + 80011a0: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 80011a4: 6013 str r3, [r2, #0] + 80011a6: 6813 ldr r3, [r2, #0] + 80011a8: f403 4340 and.w r3, r3, #49152 ; 0xc000 + 80011ac: 9301 str r3, [sp, #4] + 80011ae: 9b01 ldr r3, [sp, #4] + 80011b0: 2501 movs r5, #1 + 80011b2: f44f 3380 mov.w r3, #65536 ; 0x10000 + 80011b6: e9cd 530c strd r5, r3, [sp, #48] ; 0x30 + 80011ba: 2402 movs r4, #2 + 80011bc: f44f 0380 mov.w r3, #4194304 ; 0x400000 + 80011c0: e9cd 4312 strd r4, r3, [sp, #72] ; 0x48 + 80011c4: 2208 movs r2, #8 + 80011c6: f44f 73a8 mov.w r3, #336 ; 0x150 + 80011ca: e9cd 2314 strd r2, r3, [sp, #80] ; 0x50 + 80011ce: 2104 movs r1, #4 + 80011d0: 2307 movs r3, #7 + 80011d2: a80c add r0, sp, #48 ; 0x30 + 80011d4: e9cd 1316 strd r1, r3, [sp, #88] ; 0x58 + 80011d8: f002 f8ca bl 8003370 + 80011dc: b108 cbz r0, 80011e2 + 80011de: b672 cpsid i + 80011e0: e7fe b.n 80011e0 + 80011e2: 230f movs r3, #15 + 80011e4: e9cd 3402 strd r3, r4, [sp, #8] + 80011e8: f44f 5380 mov.w r3, #4096 ; 0x1000 + 80011ec: 9004 str r0, [sp, #16] + 80011ee: e9cd 3005 strd r3, r0, [sp, #20] + 80011f2: 4621 mov r1, r4 + 80011f4: a802 add r0, sp, #8 + 80011f6: f002 fa8f bl 8003718 + 80011fa: b108 cbz r0, 8001200 + 80011fc: b672 cpsid i + 80011fe: e7fe b.n 80011fe + 8001200: 23c0 movs r3, #192 ; 0xc0 + 8001202: a807 add r0, sp, #28 + 8001204: 9507 str r5, [sp, #28] + 8001206: e9cd 3408 strd r3, r4, [sp, #32] + 800120a: f002 fb3f bl 800388c + 800120e: b108 cbz r0, 8001214 + 8001210: b672 cpsid i + 8001212: e7fe b.n 8001212 + 8001214: b019 add sp, #100 ; 0x64 + 8001216: bd30 pop {r4, r5, pc} + 8001218: 40023800 .word 0x40023800 + 800121c: 40007000 .word 0x40007000 + +08001220
: + 8001220: b500 push {lr} + 8001222: b08d sub sp, #52 ; 0x34 + 8001224: f000 fcbc bl 8001ba0 + 8001228: f7ff ff98 bl 800115c + 800122c: 2214 movs r2, #20 + 800122e: 2100 movs r1, #0 + 8001230: a807 add r0, sp, #28 + 8001232: f004 f933 bl 800549c + 8001236: 2400 movs r4, #0 + 8001238: 4b7a ldr r3, [pc, #488] ; (8001424 ) + 800123a: 9401 str r4, [sp, #4] + 800123c: 6b1a ldr r2, [r3, #48] ; 0x30 + 800123e: 487a ldr r0, [pc, #488] ; (8001428 ) + 8001240: 4e7a ldr r6, [pc, #488] ; (800142c ) + 8001242: f042 0210 orr.w r2, r2, #16 + 8001246: 631a str r2, [r3, #48] ; 0x30 + 8001248: 6b1a ldr r2, [r3, #48] ; 0x30 + 800124a: f002 0210 and.w r2, r2, #16 + 800124e: 9201 str r2, [sp, #4] + 8001250: 9a01 ldr r2, [sp, #4] + 8001252: 9402 str r4, [sp, #8] + 8001254: 6b1a ldr r2, [r3, #48] ; 0x30 + 8001256: f042 0204 orr.w r2, r2, #4 + 800125a: 631a str r2, [r3, #48] ; 0x30 + 800125c: 6b1a ldr r2, [r3, #48] ; 0x30 + 800125e: f002 0204 and.w r2, r2, #4 + 8001262: 9202 str r2, [sp, #8] + 8001264: 9a02 ldr r2, [sp, #8] + 8001266: 9403 str r4, [sp, #12] + 8001268: 6b1a ldr r2, [r3, #48] ; 0x30 + 800126a: f042 0280 orr.w r2, r2, #128 ; 0x80 + 800126e: 631a str r2, [r3, #48] ; 0x30 + 8001270: 6b1a ldr r2, [r3, #48] ; 0x30 + 8001272: f002 0280 and.w r2, r2, #128 ; 0x80 + 8001276: 9203 str r2, [sp, #12] + 8001278: 9a03 ldr r2, [sp, #12] + 800127a: 9404 str r4, [sp, #16] + 800127c: 6b1a ldr r2, [r3, #48] ; 0x30 + 800127e: f042 0201 orr.w r2, r2, #1 + 8001282: 631a str r2, [r3, #48] ; 0x30 + 8001284: 6b1a ldr r2, [r3, #48] ; 0x30 + 8001286: f002 0201 and.w r2, r2, #1 + 800128a: 9204 str r2, [sp, #16] + 800128c: 9a04 ldr r2, [sp, #16] + 800128e: 9405 str r4, [sp, #20] + 8001290: 6b1a ldr r2, [r3, #48] ; 0x30 + 8001292: f042 0202 orr.w r2, r2, #2 + 8001296: 631a str r2, [r3, #48] ; 0x30 + 8001298: 6b1a ldr r2, [r3, #48] ; 0x30 + 800129a: f002 0202 and.w r2, r2, #2 + 800129e: 9205 str r2, [sp, #20] + 80012a0: 9a05 ldr r2, [sp, #20] + 80012a2: 9406 str r4, [sp, #24] + 80012a4: 6b1a ldr r2, [r3, #48] ; 0x30 + 80012a6: f042 0208 orr.w r2, r2, #8 + 80012aa: 631a str r2, [r3, #48] ; 0x30 + 80012ac: 6b1b ldr r3, [r3, #48] ; 0x30 + 80012ae: f003 0308 and.w r3, r3, #8 + 80012b2: 9306 str r3, [sp, #24] + 80012b4: 4622 mov r2, r4 + 80012b6: 2108 movs r1, #8 + 80012b8: 9b06 ldr r3, [sp, #24] + 80012ba: f000 fde9 bl 8001e90 + 80012be: 2201 movs r2, #1 + 80012c0: 4611 mov r1, r2 + 80012c2: 485b ldr r0, [pc, #364] ; (8001430 ) + 80012c4: f000 fde4 bl 8001e90 + 80012c8: 4622 mov r2, r4 + 80012ca: f24f 0110 movw r1, #61456 ; 0xf010 + 80012ce: 4859 ldr r0, [pc, #356] ; (8001434 ) + 80012d0: f000 fdde bl 8001e90 + 80012d4: 2304 movs r3, #4 + 80012d6: a907 add r1, sp, #28 + 80012d8: 4853 ldr r0, [pc, #332] ; (8001428 ) + 80012da: 9409 str r4, [sp, #36] ; 0x24 + 80012dc: 2501 movs r5, #1 + 80012de: e9cd 3407 strd r3, r4, [sp, #28] + 80012e2: f000 fd07 bl 8001cf4 + 80012e6: 2308 movs r3, #8 + 80012e8: a907 add r1, sp, #28 + 80012ea: 484f ldr r0, [pc, #316] ; (8001428 ) + 80012ec: e9cd 3507 strd r3, r5, [sp, #28] + 80012f0: e9cd 4409 strd r4, r4, [sp, #36] ; 0x24 + 80012f4: f000 fcfe bl 8001cf4 + 80012f8: 2332 movs r3, #50 ; 0x32 + 80012fa: a907 add r1, sp, #28 + 80012fc: 484a ldr r0, [pc, #296] ; (8001428 ) + 80012fe: 9409 str r4, [sp, #36] ; 0x24 + 8001300: e9cd 3607 strd r3, r6, [sp, #28] + 8001304: f000 fcf6 bl 8001cf4 + 8001308: a907 add r1, sp, #28 + 800130a: 4849 ldr r0, [pc, #292] ; (8001430 ) + 800130c: e9cd 5507 strd r5, r5, [sp, #28] + 8001310: e9cd 4409 strd r4, r4, [sp, #36] ; 0x24 + 8001314: f000 fcee bl 8001cf4 + 8001318: a907 add r1, sp, #28 + 800131a: 4847 ldr r0, [pc, #284] ; (8001438 ) + 800131c: 9409 str r4, [sp, #36] ; 0x24 + 800131e: e9cd 5607 strd r5, r6, [sp, #28] + 8001322: f000 fce7 bl 8001cf4 + 8001326: f24f 0310 movw r3, #61456 ; 0xf010 + 800132a: a907 add r1, sp, #28 + 800132c: 4841 ldr r0, [pc, #260] ; (8001434 ) + 800132e: e9cd 3507 strd r3, r5, [sp, #28] + 8001332: e9cd 4409 strd r4, r4, [sp, #36] ; 0x24 + 8001336: f000 fcdd bl 8001cf4 + 800133a: 2320 movs r3, #32 + 800133c: 483d ldr r0, [pc, #244] ; (8001434 ) + 800133e: 9409 str r4, [sp, #36] ; 0x24 + 8001340: a907 add r1, sp, #28 + 8001342: e9cd 3407 strd r3, r4, [sp, #28] + 8001346: 4d3d ldr r5, [pc, #244] ; (800143c ) + 8001348: f000 fcd4 bl 8001cf4 + 800134c: 483c ldr r0, [pc, #240] ; (8001440 ) + 800134e: 4b3d ldr r3, [pc, #244] ; (8001444 ) + 8001350: 6204 str r4, [r0, #32] + 8001352: e9c0 5300 strd r5, r3, [r0] + 8001356: f44f 4380 mov.w r3, #16384 ; 0x4000 + 800135a: e9c0 4402 strd r4, r4, [r0, #8] + 800135e: e9c0 3404 strd r3, r4, [r0, #16] + 8001362: e9c0 4406 strd r4, r4, [r0, #24] + 8001366: f001 fad1 bl 800290c + 800136a: b108 cbz r0, 8001370 + 800136c: b672 cpsid i + 800136e: e7fe b.n 800136e + 8001370: 4b35 ldr r3, [pc, #212] ; (8001448 ) + 8001372: 4a36 ldr r2, [pc, #216] ; (800144c ) + 8001374: 6118 str r0, [r3, #16] + 8001376: f44f 7400 mov.w r4, #512 ; 0x200 + 800137a: e9c3 2400 strd r2, r4, [r3] + 800137e: f44f 52fa mov.w r2, #8000 ; 0x1f40 + 8001382: e9c3 0002 strd r0, r0, [r3, #8] + 8001386: e9c3 2005 strd r2, r0, [r3, #20] + 800138a: e9c3 0007 strd r0, r0, [r3, #28] + 800138e: 4618 mov r0, r3 + 8001390: f001 fdb0 bl 8002ef4 + 8001394: b108 cbz r0, 800139a + 8001396: b672 cpsid i + 8001398: e7fe b.n 8001398 + 800139a: 4b2d ldr r3, [pc, #180] ; (8001450 ) + 800139c: 4a2d ldr r2, [pc, #180] ; (8001454 ) + 800139e: 611c str r4, [r3, #16] + 80013a0: e9c3 2400 strd r2, r4, [r3] + 80013a4: 4a2c ldr r2, [pc, #176] ; (8001458 ) + 80013a6: e9c3 0002 strd r0, r0, [r3, #8] + 80013aa: e9c3 2005 strd r2, r0, [r3, #20] + 80013ae: e9c3 0007 strd r0, r0, [r3, #28] + 80013b2: 4618 mov r0, r3 + 80013b4: f001 fd9e bl 8002ef4 + 80013b8: b108 cbz r0, 80013be + 80013ba: b672 cpsid i + 80013bc: e7fe b.n 80013bc + 80013be: 4b27 ldr r3, [pc, #156] ; (800145c ) + 80013c0: 4927 ldr r1, [pc, #156] ; (8001460 ) + 80013c2: 6298 str r0, [r3, #40] ; 0x28 + 80013c4: f44f 7282 mov.w r2, #260 ; 0x104 + 80013c8: e9c3 4006 strd r4, r0, [r3, #24] + 80013cc: e9c3 1200 strd r1, r2, [r3] + 80013d0: e9c3 0002 strd r0, r0, [r3, #8] + 80013d4: e9c3 0004 strd r0, r0, [r3, #16] + 80013d8: e9c3 0008 strd r0, r0, [r3, #32] + 80013dc: 220a movs r2, #10 + 80013de: 4618 mov r0, r3 + 80013e0: 62da str r2, [r3, #44] ; 0x2c + 80013e2: f002 fb1f bl 8003a24 + 80013e6: 4604 mov r4, r0 + 80013e8: b108 cbz r0, 80013ee + 80013ea: b672 cpsid i + 80013ec: e7fe b.n 80013ec + 80013ee: f003 fec7 bl 8005180 + 80013f2: 481c ldr r0, [pc, #112] ; (8001464 ) + 80013f4: 4b1c ldr r3, [pc, #112] ; (8001468 ) + 80013f6: 6104 str r4, [r0, #16] + 80013f8: f44f 32e1 mov.w r2, #115200 ; 0x1c200 + 80013fc: e9c0 3200 strd r3, r2, [r0] + 8001400: 220c movs r2, #12 + 8001402: e9c0 4402 strd r4, r4, [r0, #8] + 8001406: e9c0 2405 strd r2, r4, [r0, #20] + 800140a: 61c4 str r4, [r0, #28] + 800140c: f002 fbe0 bl 8003bd0 + 8001410: b108 cbz r0, 8001416 + 8001412: b672 cpsid i + 8001414: e7fe b.n 8001414 + 8001416: f7ff fdbf bl 8000f98 + 800141a: f003 fed1 bl 80051c0 + 800141e: f7ff fdfb bl 8001018 + 8001422: e7fa b.n 800141a + 8001424: 40023800 .word 0x40023800 + 8001428: 40021000 .word 0x40021000 + 800142c: 10120000 .word 0x10120000 + 8001430: 40020800 .word 0x40020800 + 8001434: 40020c00 .word 0x40020c00 + 8001438: 40020000 .word 0x40020000 + 800143c: 40005400 .word 0x40005400 + 8001440: 20000294 .word 0x20000294 + 8001444: 000186a0 .word 0x000186a0 + 8001448: 20000380 .word 0x20000380 + 800144c: 40003800 .word 0x40003800 + 8001450: 200003c8 .word 0x200003c8 + 8001454: 40003c00 .word 0x40003c00 + 8001458: 00017700 .word 0x00017700 + 800145c: 200002e8 .word 0x200002e8 + 8001460: 40013000 .word 0x40013000 + 8001464: 20000340 .word 0x20000340 + 8001468: 40004400 .word 0x40004400 + +0800146c : + 800146c: b672 cpsid i + 800146e: e7fe b.n 800146e + +08001470 : + 8001470: b082 sub sp, #8 + 8001472: 4b0d ldr r3, [pc, #52] ; (80014a8 ) + 8001474: 2100 movs r1, #0 + 8001476: 9100 str r1, [sp, #0] + 8001478: 6c5a ldr r2, [r3, #68] ; 0x44 + 800147a: f442 4280 orr.w r2, r2, #16384 ; 0x4000 + 800147e: 645a str r2, [r3, #68] ; 0x44 + 8001480: 6c5a ldr r2, [r3, #68] ; 0x44 + 8001482: f402 4280 and.w r2, r2, #16384 ; 0x4000 + 8001486: 9200 str r2, [sp, #0] + 8001488: 9a00 ldr r2, [sp, #0] + 800148a: 9101 str r1, [sp, #4] + 800148c: 6c1a ldr r2, [r3, #64] ; 0x40 + 800148e: f042 5280 orr.w r2, r2, #268435456 ; 0x10000000 + 8001492: 641a str r2, [r3, #64] ; 0x40 + 8001494: 6c1b ldr r3, [r3, #64] ; 0x40 + 8001496: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 800149a: 9301 str r3, [sp, #4] + 800149c: 9b01 ldr r3, [sp, #4] + 800149e: 2007 movs r0, #7 + 80014a0: b002 add sp, #8 + 80014a2: f000 bbbd b.w 8001c20 + 80014a6: bf00 nop + 80014a8: 40023800 .word 0x40023800 + +080014ac : + 80014ac: b530 push {r4, r5, lr} + 80014ae: 4604 mov r4, r0 + 80014b0: b089 sub sp, #36 ; 0x24 + 80014b2: 2214 movs r2, #20 + 80014b4: 2100 movs r1, #0 + 80014b6: a803 add r0, sp, #12 + 80014b8: f003 fff0 bl 800549c + 80014bc: 6822 ldr r2, [r4, #0] + 80014be: 4b14 ldr r3, [pc, #80] ; (8001510 ) + 80014c0: 429a cmp r2, r3 + 80014c2: d122 bne.n 800150a + 80014c4: 4c13 ldr r4, [pc, #76] ; (8001514 ) + 80014c6: 4814 ldr r0, [pc, #80] ; (8001518 ) + 80014c8: 2500 movs r5, #0 + 80014ca: 9501 str r5, [sp, #4] + 80014cc: 6b23 ldr r3, [r4, #48] ; 0x30 + 80014ce: f043 0302 orr.w r3, r3, #2 + 80014d2: 6323 str r3, [r4, #48] ; 0x30 + 80014d4: 6b23 ldr r3, [r4, #48] ; 0x30 + 80014d6: f003 0302 and.w r3, r3, #2 + 80014da: 9301 str r3, [sp, #4] + 80014dc: 9b01 ldr r3, [sp, #4] + 80014de: f44f 7210 mov.w r2, #576 ; 0x240 + 80014e2: 2312 movs r3, #18 + 80014e4: e9cd 2303 strd r2, r3, [sp, #12] + 80014e8: 2301 movs r3, #1 + 80014ea: 9305 str r3, [sp, #20] + 80014ec: a903 add r1, sp, #12 + 80014ee: 2304 movs r3, #4 + 80014f0: 9307 str r3, [sp, #28] + 80014f2: f000 fbff bl 8001cf4 + 80014f6: 9502 str r5, [sp, #8] + 80014f8: 6c23 ldr r3, [r4, #64] ; 0x40 + 80014fa: f443 1300 orr.w r3, r3, #2097152 ; 0x200000 + 80014fe: 6423 str r3, [r4, #64] ; 0x40 + 8001500: 6c23 ldr r3, [r4, #64] ; 0x40 + 8001502: f403 1300 and.w r3, r3, #2097152 ; 0x200000 + 8001506: 9302 str r3, [sp, #8] + 8001508: 9b02 ldr r3, [sp, #8] + 800150a: b009 add sp, #36 ; 0x24 + 800150c: bd30 pop {r4, r5, pc} + 800150e: bf00 nop + 8001510: 40005400 .word 0x40005400 + 8001514: 40023800 .word 0x40023800 + 8001518: 40020400 .word 0x40020400 + +0800151c : + 800151c: b570 push {r4, r5, r6, lr} + 800151e: 4604 mov r4, r0 + 8001520: b08c sub sp, #48 ; 0x30 + 8001522: 2214 movs r2, #20 + 8001524: 2100 movs r1, #0 + 8001526: a807 add r0, sp, #28 + 8001528: f003 ffb8 bl 800549c + 800152c: 6823 ldr r3, [r4, #0] + 800152e: 4a38 ldr r2, [pc, #224] ; (8001610 ) + 8001530: 4293 cmp r3, r2 + 8001532: d136 bne.n 80015a2 + 8001534: 4b37 ldr r3, [pc, #220] ; (8001614 ) + 8001536: 4838 ldr r0, [pc, #224] ; (8001618 ) + 8001538: 2400 movs r4, #0 + 800153a: 9401 str r4, [sp, #4] + 800153c: 6c1a ldr r2, [r3, #64] ; 0x40 + 800153e: f442 4280 orr.w r2, r2, #16384 ; 0x4000 + 8001542: 641a str r2, [r3, #64] ; 0x40 + 8001544: 6c1a ldr r2, [r3, #64] ; 0x40 + 8001546: f402 4280 and.w r2, r2, #16384 ; 0x4000 + 800154a: 9201 str r2, [sp, #4] + 800154c: 9a01 ldr r2, [sp, #4] + 800154e: 9402 str r4, [sp, #8] + 8001550: 6b1a ldr r2, [r3, #48] ; 0x30 + 8001552: f042 0204 orr.w r2, r2, #4 + 8001556: 631a str r2, [r3, #48] ; 0x30 + 8001558: 6b1a ldr r2, [r3, #48] ; 0x30 + 800155a: f002 0204 and.w r2, r2, #4 + 800155e: 9202 str r2, [sp, #8] + 8001560: 9a02 ldr r2, [sp, #8] + 8001562: 9403 str r4, [sp, #12] + 8001564: 6b1a ldr r2, [r3, #48] ; 0x30 + 8001566: f042 0202 orr.w r2, r2, #2 + 800156a: 631a str r2, [r3, #48] ; 0x30 + 800156c: 6b1b ldr r3, [r3, #48] ; 0x30 + 800156e: f003 0302 and.w r3, r3, #2 + 8001572: 9303 str r3, [sp, #12] + 8001574: 9b03 ldr r3, [sp, #12] + 8001576: 2602 movs r6, #2 + 8001578: 2308 movs r3, #8 + 800157a: 2505 movs r5, #5 + 800157c: a907 add r1, sp, #28 + 800157e: e9cd 3607 strd r3, r6, [sp, #28] + 8001582: 950b str r5, [sp, #44] ; 0x2c + 8001584: f000 fbb6 bl 8001cf4 + 8001588: f44f 53a0 mov.w r3, #5120 ; 0x1400 + 800158c: e9cd 3607 strd r3, r6, [sp, #28] + 8001590: e9cd 4409 strd r4, r4, [sp, #36] ; 0x24 + 8001594: 4821 ldr r0, [pc, #132] ; (800161c ) + 8001596: 950b str r5, [sp, #44] ; 0x2c + 8001598: a907 add r1, sp, #28 + 800159a: f000 fbab bl 8001cf4 + 800159e: b00c add sp, #48 ; 0x30 + 80015a0: bd70 pop {r4, r5, r6, pc} + 80015a2: 4a1f ldr r2, [pc, #124] ; (8001620 ) + 80015a4: 4293 cmp r3, r2 + 80015a6: d1fa bne.n 800159e + 80015a8: 4b1a ldr r3, [pc, #104] ; (8001614 ) + 80015aa: 481e ldr r0, [pc, #120] ; (8001624 ) + 80015ac: 2400 movs r4, #0 + 80015ae: 9404 str r4, [sp, #16] + 80015b0: 6c1a ldr r2, [r3, #64] ; 0x40 + 80015b2: f442 4200 orr.w r2, r2, #32768 ; 0x8000 + 80015b6: 641a str r2, [r3, #64] ; 0x40 + 80015b8: 6c1a ldr r2, [r3, #64] ; 0x40 + 80015ba: f402 4200 and.w r2, r2, #32768 ; 0x8000 + 80015be: 9204 str r2, [sp, #16] + 80015c0: 9a04 ldr r2, [sp, #16] + 80015c2: 9405 str r4, [sp, #20] + 80015c4: 6b1a ldr r2, [r3, #48] ; 0x30 + 80015c6: f042 0201 orr.w r2, r2, #1 + 80015ca: 631a str r2, [r3, #48] ; 0x30 + 80015cc: 6b1a ldr r2, [r3, #48] ; 0x30 + 80015ce: f002 0201 and.w r2, r2, #1 + 80015d2: 9205 str r2, [sp, #20] + 80015d4: 9a05 ldr r2, [sp, #20] + 80015d6: 9406 str r4, [sp, #24] + 80015d8: 6b1a ldr r2, [r3, #48] ; 0x30 + 80015da: f042 0204 orr.w r2, r2, #4 + 80015de: 631a str r2, [r3, #48] ; 0x30 + 80015e0: 6b1b ldr r3, [r3, #48] ; 0x30 + 80015e2: f003 0304 and.w r3, r3, #4 + 80015e6: 9306 str r3, [sp, #24] + 80015e8: 9b06 ldr r3, [sp, #24] + 80015ea: 2602 movs r6, #2 + 80015ec: 2310 movs r3, #16 + 80015ee: 2506 movs r5, #6 + 80015f0: a907 add r1, sp, #28 + 80015f2: e9cd 3607 strd r3, r6, [sp, #28] + 80015f6: 950b str r5, [sp, #44] ; 0x2c + 80015f8: f000 fb7c bl 8001cf4 + 80015fc: f44f 53a4 mov.w r3, #5248 ; 0x1480 + 8001600: e9cd 3607 strd r3, r6, [sp, #28] + 8001604: e9cd 4409 strd r4, r4, [sp, #36] ; 0x24 + 8001608: 950b str r5, [sp, #44] ; 0x2c + 800160a: a907 add r1, sp, #28 + 800160c: 4802 ldr r0, [pc, #8] ; (8001618 ) + 800160e: e7c4 b.n 800159a + 8001610: 40003800 .word 0x40003800 + 8001614: 40023800 .word 0x40023800 + 8001618: 40020800 .word 0x40020800 + 800161c: 40020400 .word 0x40020400 + 8001620: 40003c00 .word 0x40003c00 + 8001624: 40020000 .word 0x40020000 + +08001628 : + 8001628: b510 push {r4, lr} + 800162a: 4604 mov r4, r0 + 800162c: b088 sub sp, #32 + 800162e: 2214 movs r2, #20 + 8001630: 2100 movs r1, #0 + 8001632: a803 add r0, sp, #12 + 8001634: f003 ff32 bl 800549c + 8001638: 6822 ldr r2, [r4, #0] + 800163a: 4b14 ldr r3, [pc, #80] ; (800168c ) + 800163c: 429a cmp r2, r3 + 800163e: d122 bne.n 8001686 + 8001640: f503 3384 add.w r3, r3, #67584 ; 0x10800 + 8001644: 2100 movs r1, #0 + 8001646: 9101 str r1, [sp, #4] + 8001648: 6c5a ldr r2, [r3, #68] ; 0x44 + 800164a: 4811 ldr r0, [pc, #68] ; (8001690 ) + 800164c: f442 5280 orr.w r2, r2, #4096 ; 0x1000 + 8001650: 645a str r2, [r3, #68] ; 0x44 + 8001652: 6c5a ldr r2, [r3, #68] ; 0x44 + 8001654: f402 5280 and.w r2, r2, #4096 ; 0x1000 + 8001658: 9201 str r2, [sp, #4] + 800165a: 9a01 ldr r2, [sp, #4] + 800165c: 9102 str r1, [sp, #8] + 800165e: 6b1a ldr r2, [r3, #48] ; 0x30 + 8001660: f042 0201 orr.w r2, r2, #1 + 8001664: 631a str r2, [r3, #48] ; 0x30 + 8001666: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001668: f003 0301 and.w r3, r3, #1 + 800166c: 9302 str r3, [sp, #8] + 800166e: 9b02 ldr r3, [sp, #8] + 8001670: 22e0 movs r2, #224 ; 0xe0 + 8001672: 2302 movs r3, #2 + 8001674: 2103 movs r1, #3 + 8001676: e9cd 2303 strd r2, r3, [sp, #12] + 800167a: 2305 movs r3, #5 + 800167c: e9cd 1306 strd r1, r3, [sp, #24] + 8001680: a903 add r1, sp, #12 + 8001682: f000 fb37 bl 8001cf4 + 8001686: b008 add sp, #32 + 8001688: bd10 pop {r4, pc} + 800168a: bf00 nop + 800168c: 40013000 .word 0x40013000 + 8001690: 40020000 .word 0x40020000 + +08001694 : + 8001694: b510 push {r4, lr} + 8001696: 4604 mov r4, r0 + 8001698: b088 sub sp, #32 + 800169a: 2214 movs r2, #20 + 800169c: 2100 movs r1, #0 + 800169e: a803 add r0, sp, #12 + 80016a0: f003 fefc bl 800549c + 80016a4: 6822 ldr r2, [r4, #0] + 80016a6: 4b14 ldr r3, [pc, #80] ; (80016f8 ) + 80016a8: 429a cmp r2, r3 + 80016aa: d122 bne.n 80016f2 + 80016ac: f503 33fa add.w r3, r3, #128000 ; 0x1f400 + 80016b0: 2100 movs r1, #0 + 80016b2: 9101 str r1, [sp, #4] + 80016b4: 6c1a ldr r2, [r3, #64] ; 0x40 + 80016b6: 4811 ldr r0, [pc, #68] ; (80016fc ) + 80016b8: f442 3200 orr.w r2, r2, #131072 ; 0x20000 + 80016bc: 641a str r2, [r3, #64] ; 0x40 + 80016be: 6c1a ldr r2, [r3, #64] ; 0x40 + 80016c0: f402 3200 and.w r2, r2, #131072 ; 0x20000 + 80016c4: 9201 str r2, [sp, #4] + 80016c6: 9a01 ldr r2, [sp, #4] + 80016c8: 9102 str r1, [sp, #8] + 80016ca: 6b1a ldr r2, [r3, #48] ; 0x30 + 80016cc: f042 0201 orr.w r2, r2, #1 + 80016d0: 631a str r2, [r3, #48] ; 0x30 + 80016d2: 6b1b ldr r3, [r3, #48] ; 0x30 + 80016d4: f003 0301 and.w r3, r3, #1 + 80016d8: 9302 str r3, [sp, #8] + 80016da: 9b02 ldr r3, [sp, #8] + 80016dc: 220c movs r2, #12 + 80016de: 2302 movs r3, #2 + 80016e0: 2103 movs r1, #3 + 80016e2: e9cd 2303 strd r2, r3, [sp, #12] + 80016e6: 2307 movs r3, #7 + 80016e8: e9cd 1306 strd r1, r3, [sp, #24] + 80016ec: a903 add r1, sp, #12 + 80016ee: f000 fb01 bl 8001cf4 + 80016f2: b008 add sp, #32 + 80016f4: bd10 pop {r4, pc} + 80016f6: bf00 nop + 80016f8: 40004400 .word 0x40004400 + 80016fc: 40020000 .word 0x40020000 + +08001700 : + 8001700: e7fe b.n 8001700 + +08001702 : + 8001702: e7fe b.n 8001702 + +08001704 : + 8001704: e7fe b.n 8001704 + +08001706 : + 8001706: e7fe b.n 8001706 + +08001708 : + 8001708: e7fe b.n 8001708 + +0800170a : + 800170a: 4770 bx lr + +0800170c : + 800170c: 4770 bx lr + +0800170e : + 800170e: 4770 bx lr + +08001710 : + 8001710: f000 ba60 b.w 8001bd4 + +08001714 : + 8001714: 4801 ldr r0, [pc, #4] ; (800171c ) + 8001716: f000 bcb7 b.w 8002088 + 800171a: bf00 nop + 800171c: 200007ec .word 0x200007ec + +08001720 <_read>: + 8001720: b570 push {r4, r5, r6, lr} + 8001722: 460e mov r6, r1 + 8001724: 4615 mov r5, r2 + 8001726: 460c mov r4, r1 + 8001728: 1ba3 subs r3, r4, r6 + 800172a: 429d cmp r5, r3 + 800172c: dc01 bgt.n 8001732 <_read+0x12> + 800172e: 4628 mov r0, r5 + 8001730: bd70 pop {r4, r5, r6, pc} + 8001732: f3af 8000 nop.w + 8001736: f804 0b01 strb.w r0, [r4], #1 + 800173a: e7f5 b.n 8001728 <_read+0x8> + +0800173c <_write>: + 800173c: b570 push {r4, r5, r6, lr} + 800173e: 460e mov r6, r1 + 8001740: 4615 mov r5, r2 + 8001742: 460c mov r4, r1 + 8001744: 1ba3 subs r3, r4, r6 + 8001746: 429d cmp r5, r3 + 8001748: dc01 bgt.n 800174e <_write+0x12> + 800174a: 4628 mov r0, r5 + 800174c: bd70 pop {r4, r5, r6, pc} + 800174e: f814 0b01 ldrb.w r0, [r4], #1 + 8001752: f7ff fcf3 bl 800113c <__io_putchar> + 8001756: e7f5 b.n 8001744 <_write+0x8> + +08001758 <_close>: + 8001758: f04f 30ff mov.w r0, #4294967295 + 800175c: 4770 bx lr + +0800175e <_fstat>: + 800175e: f44f 5300 mov.w r3, #8192 ; 0x2000 + 8001762: 604b str r3, [r1, #4] + 8001764: 2000 movs r0, #0 + 8001766: 4770 bx lr + +08001768 <_isatty>: + 8001768: 2001 movs r0, #1 + 800176a: 4770 bx lr + +0800176c <_lseek>: + 800176c: 2000 movs r0, #0 + 800176e: 4770 bx lr + +08001770 <_sbrk>: + 8001770: 4b0b ldr r3, [pc, #44] ; (80017a0 <_sbrk+0x30>) + 8001772: 6819 ldr r1, [r3, #0] + 8001774: b510 push {r4, lr} + 8001776: 4602 mov r2, r0 + 8001778: b909 cbnz r1, 800177e <_sbrk+0xe> + 800177a: 490a ldr r1, [pc, #40] ; (80017a4 <_sbrk+0x34>) + 800177c: 6019 str r1, [r3, #0] + 800177e: 6818 ldr r0, [r3, #0] + 8001780: 4909 ldr r1, [pc, #36] ; (80017a8 <_sbrk+0x38>) + 8001782: 4c0a ldr r4, [pc, #40] ; (80017ac <_sbrk+0x3c>) + 8001784: 4402 add r2, r0 + 8001786: 1b09 subs r1, r1, r4 + 8001788: 428a cmp r2, r1 + 800178a: d906 bls.n 800179a <_sbrk+0x2a> + 800178c: f003 fe4c bl 8005428 <__errno> + 8001790: 230c movs r3, #12 + 8001792: 6003 str r3, [r0, #0] + 8001794: f04f 30ff mov.w r0, #4294967295 + 8001798: bd10 pop {r4, pc} + 800179a: 601a str r2, [r3, #0] + 800179c: e7fc b.n 8001798 <_sbrk+0x28> + 800179e: bf00 nop + 80017a0: 20000228 .word 0x20000228 + 80017a4: 20000ab8 .word 0x20000ab8 + 80017a8: 20010000 .word 0x20010000 + 80017ac: 00000400 .word 0x00000400 + +080017b0 : + 80017b0: 4b05 ldr r3, [pc, #20] ; (80017c8 ) + 80017b2: f8d3 2088 ldr.w r2, [r3, #136] ; 0x88 + 80017b6: f442 0270 orr.w r2, r2, #15728640 ; 0xf00000 + 80017ba: f8c3 2088 str.w r2, [r3, #136] ; 0x88 + 80017be: f04f 6200 mov.w r2, #134217728 ; 0x8000000 + 80017c2: 609a str r2, [r3, #8] + 80017c4: 4770 bx lr + 80017c6: bf00 nop + 80017c8: e000ed00 .word 0xe000ed00 + +080017cc : + 80017cc: f8df d034 ldr.w sp, [pc, #52] ; 8001804 + 80017d0: 2100 movs r1, #0 + 80017d2: e003 b.n 80017dc + +080017d4 : + 80017d4: 4b0c ldr r3, [pc, #48] ; (8001808 ) + 80017d6: 585b ldr r3, [r3, r1] + 80017d8: 5043 str r3, [r0, r1] + 80017da: 3104 adds r1, #4 + +080017dc : + 80017dc: 480b ldr r0, [pc, #44] ; (800180c ) + 80017de: 4b0c ldr r3, [pc, #48] ; (8001810 ) + 80017e0: 1842 adds r2, r0, r1 + 80017e2: 429a cmp r2, r3 + 80017e4: d3f6 bcc.n 80017d4 + 80017e6: 4a0b ldr r2, [pc, #44] ; (8001814 ) + 80017e8: e002 b.n 80017f0 + +080017ea : + 80017ea: 2300 movs r3, #0 + 80017ec: f842 3b04 str.w r3, [r2], #4 + +080017f0 : + 80017f0: 4b09 ldr r3, [pc, #36] ; (8001818 ) + 80017f2: 429a cmp r2, r3 + 80017f4: d3f9 bcc.n 80017ea + 80017f6: f7ff ffdb bl 80017b0 + 80017fa: f003 fe1b bl 8005434 <__libc_init_array> + 80017fe: f7ff fd0f bl 8001220
+ 8001802: 4770 bx lr + 8001804: 20010000 .word 0x20010000 + 8001808: 08009d60 .word 0x08009d60 + 800180c: 20000000 .word 0x20000000 + 8001810: 200001fc .word 0x200001fc + 8001814: 200001fc .word 0x200001fc + 8001818: 20000ab4 .word 0x20000ab4 + +0800181c : + 800181c: e7fe b.n 800181c + ... + +08001820 : + 8001820: b5f8 push {r3, r4, r5, r6, r7, lr} + 8001822: f44f 4300 mov.w r3, #32768 ; 0x8000 + 8001826: 6143 str r3, [r0, #20] + 8001828: f44f 5380 mov.w r3, #4096 ; 0x1000 + 800182c: 4d1d ldr r5, [pc, #116] ; (80018a4 ) + 800182e: 63c3 str r3, [r0, #60] ; 0x3c + 8001830: f44f 5300 mov.w r3, #8192 ; 0x2000 + 8001834: 2600 movs r6, #0 + 8001836: 2701 movs r7, #1 + 8001838: 6003 str r3, [r0, #0] + 800183a: f44f 4380 mov.w r3, #16384 ; 0x4000 + 800183e: 6283 str r3, [r0, #40] ; 0x28 + 8001840: 4604 mov r4, r0 + 8001842: 6187 str r7, [r0, #24] + 8001844: 6407 str r7, [r0, #64] ; 0x40 + 8001846: 6047 str r7, [r0, #4] + 8001848: 62c7 str r7, [r0, #44] ; 0x2c + 800184a: 6206 str r6, [r0, #32] + 800184c: 6486 str r6, [r0, #72] ; 0x48 + 800184e: 60c6 str r6, [r0, #12] + 8001850: 6346 str r6, [r0, #52] ; 0x34 + 8001852: f100 0114 add.w r1, r0, #20 + 8001856: 4628 mov r0, r5 + 8001858: f000 fa4c bl 8001cf4 + 800185c: f104 013c add.w r1, r4, #60 ; 0x3c + 8001860: 4628 mov r0, r5 + 8001862: f000 fa47 bl 8001cf4 + 8001866: 4621 mov r1, r4 + 8001868: 4628 mov r0, r5 + 800186a: f000 fa43 bl 8001cf4 + 800186e: f104 0128 add.w r1, r4, #40 ; 0x28 + 8001872: 4628 mov r0, r5 + 8001874: f000 fa3e bl 8001cf4 + 8001878: 4632 mov r2, r6 + 800187a: 8aa1 ldrh r1, [r4, #20] + 800187c: 4628 mov r0, r5 + 800187e: f000 fb07 bl 8001e90 + 8001882: 4632 mov r2, r6 + 8001884: 8fa1 ldrh r1, [r4, #60] ; 0x3c + 8001886: 4628 mov r0, r5 + 8001888: f000 fb02 bl 8001e90 + 800188c: 4632 mov r2, r6 + 800188e: 8821 ldrh r1, [r4, #0] + 8001890: 4628 mov r0, r5 + 8001892: f000 fafd bl 8001e90 + 8001896: 4628 mov r0, r5 + 8001898: 4632 mov r2, r6 + 800189a: 8d21 ldrh r1, [r4, #40] ; 0x28 + 800189c: f000 faf8 bl 8001e90 + 80018a0: 4638 mov r0, r7 + 80018a2: bdf8 pop {r3, r4, r5, r6, r7, pc} + 80018a4: 40020c00 .word 0x40020c00 + +080018a8 : + 80018a8: 3901 subs r1, #1 + 80018aa: b510 push {r4, lr} + 80018ac: 8a83 ldrh r3, [r0, #20] + 80018ae: 4604 mov r4, r0 + 80018b0: 2907 cmp r1, #7 + 80018b2: d83f bhi.n 8001934 + 80018b4: e8df f001 tbb [pc, r1] + 80018b8: 283e040b .word 0x283e040b + 80018bc: 1c3e3e3e .word 0x1c3e3e3e + 80018c0: 2201 movs r2, #1 + 80018c2: 4619 mov r1, r3 + 80018c4: 481c ldr r0, [pc, #112] ; (8001938 ) + 80018c6: f000 fae3 bl 8001e90 + 80018ca: 2200 movs r2, #0 + 80018cc: e016 b.n 80018fc + 80018ce: 4619 mov r1, r3 + 80018d0: 2200 movs r2, #0 + 80018d2: 4819 ldr r0, [pc, #100] ; (8001938 ) + 80018d4: f000 fadc bl 8001e90 + 80018d8: 2200 movs r2, #0 + 80018da: 8fa1 ldrh r1, [r4, #60] ; 0x3c + 80018dc: 4816 ldr r0, [pc, #88] ; (8001938 ) + 80018de: f000 fad7 bl 8001e90 + 80018e2: 2201 movs r2, #1 + 80018e4: 8821 ldrh r1, [r4, #0] + 80018e6: 4814 ldr r0, [pc, #80] ; (8001938 ) + 80018e8: f000 fad2 bl 8001e90 + 80018ec: 2200 movs r2, #0 + 80018ee: e01b b.n 8001928 + 80018f0: 2200 movs r2, #0 + 80018f2: 4619 mov r1, r3 + 80018f4: 4810 ldr r0, [pc, #64] ; (8001938 ) + 80018f6: f000 facb bl 8001e90 + 80018fa: 2201 movs r2, #1 + 80018fc: 8fa1 ldrh r1, [r4, #60] ; 0x3c + 80018fe: 480e ldr r0, [pc, #56] ; (8001938 ) + 8001900: f000 fac6 bl 8001e90 + 8001904: 2200 movs r2, #0 + 8001906: e7ed b.n 80018e4 + 8001908: 4619 mov r1, r3 + 800190a: 2200 movs r2, #0 + 800190c: 480a ldr r0, [pc, #40] ; (8001938 ) + 800190e: f000 fabf bl 8001e90 + 8001912: 2200 movs r2, #0 + 8001914: 8fa1 ldrh r1, [r4, #60] ; 0x3c + 8001916: 4808 ldr r0, [pc, #32] ; (8001938 ) + 8001918: f000 faba bl 8001e90 + 800191c: 2200 movs r2, #0 + 800191e: 8821 ldrh r1, [r4, #0] + 8001920: 4805 ldr r0, [pc, #20] ; (8001938 ) + 8001922: f000 fab5 bl 8001e90 + 8001926: 2201 movs r2, #1 + 8001928: 8d21 ldrh r1, [r4, #40] ; 0x28 + 800192a: 4803 ldr r0, [pc, #12] ; (8001938 ) + 800192c: f000 fab0 bl 8001e90 + 8001930: 2001 movs r0, #1 + 8001932: bd10 pop {r4, pc} + 8001934: 2200 movs r2, #0 + 8001936: e7c4 b.n 80018c2 + 8001938: 40020c00 .word 0x40020c00 + +0800193c : + 800193c: 2200 movs r2, #0 + 800193e: b148 cbz r0, 8001954 + 8001940: b139 cbz r1, 8001952 + 8001942: 7943 ldrb r3, [r0, #5] + 8001944: 6001 str r1, [r0, #0] + 8001946: f362 0300 bfi r3, r2, #0, #1 + 800194a: 7102 strb r2, [r0, #4] + 800194c: 7143 strb r3, [r0, #5] + 800194e: 2001 movs r0, #1 + 8001950: 4770 bx lr + 8001952: 4608 mov r0, r1 + 8001954: 4770 bx lr + +08001956 : + 8001956: b120 cbz r0, 8001962 + 8001958: 7943 ldrb r3, [r0, #5] + 800195a: f361 0300 bfi r3, r1, #0, #1 + 800195e: 7143 strb r3, [r0, #5] + 8001960: 2001 movs r0, #1 + 8001962: 4770 bx lr + +08001964 : + 8001964: b573 push {r0, r1, r4, r5, r6, lr} + 8001966: 460e mov r6, r1 + 8001968: 4604 mov r4, r0 + 800196a: b910 cbnz r0, 8001972 + 800196c: 2000 movs r0, #0 + 800196e: b002 add sp, #8 + 8001970: bd70 pop {r4, r5, r6, pc} + 8001972: f04f 35ff mov.w r5, #4294967295 + 8001976: 9500 str r5, [sp, #0] + 8001978: 2301 movs r3, #1 + 800197a: 4a09 ldr r2, [pc, #36] ; (80019a0 ) + 800197c: 6800 ldr r0, [r0, #0] + 800197e: 213c movs r1, #60 ; 0x3c + 8001980: f001 f870 bl 8002a64 + 8001984: 2800 cmp r0, #0 + 8001986: d1f1 bne.n 800196c + 8001988: 9500 str r5, [sp, #0] + 800198a: 2303 movs r3, #3 + 800198c: 4632 mov r2, r6 + 800198e: 213c movs r1, #60 ; 0x3c + 8001990: 6820 ldr r0, [r4, #0] + 8001992: f001 f93b bl 8002c0c + 8001996: fab0 f080 clz r0, r0 + 800199a: 0940 lsrs r0, r0, #5 + 800199c: e7e7 b.n 800196e + 800199e: bf00 nop + 80019a0: 08009a2a .word 0x08009a2a + +080019a4 : + 80019a4: b5f0 push {r4, r5, r6, r7, lr} + 80019a6: 460d mov r5, r1 + 80019a8: b085 sub sp, #20 + 80019aa: 4616 mov r6, r2 + 80019ac: 4604 mov r4, r0 + 80019ae: b910 cbnz r0, 80019b6 + 80019b0: 2000 movs r0, #0 + 80019b2: b005 add sp, #20 + 80019b4: bdf0 pop {r4, r5, r6, r7, pc} + 80019b6: f04f 37ff mov.w r7, #4294967295 + 80019ba: 9700 str r7, [sp, #0] + 80019bc: 2301 movs r3, #1 + 80019be: 4a13 ldr r2, [pc, #76] ; (8001a0c ) + 80019c0: 6800 ldr r0, [r0, #0] + 80019c2: 213c movs r1, #60 ; 0x3c + 80019c4: f001 f84e bl 8002a64 + 80019c8: 2800 cmp r0, #0 + 80019ca: d1f1 bne.n 80019b0 + 80019cc: 9700 str r7, [sp, #0] + 80019ce: 2302 movs r3, #2 + 80019d0: aa03 add r2, sp, #12 + 80019d2: 213c movs r1, #60 ; 0x3c + 80019d4: 6820 ldr r0, [r4, #0] + 80019d6: f001 f919 bl 8002c0c + 80019da: 2800 cmp r0, #0 + 80019dc: d1e8 bne.n 80019b0 + 80019de: f89d 300d ldrb.w r3, [sp, #13] + 80019e2: f88d 300e strb.w r3, [sp, #14] + 80019e6: f89d 300c ldrb.w r3, [sp, #12] + 80019ea: f88d 300f strb.w r3, [sp, #15] + 80019ee: b116 cbz r6, 80019f6 + 80019f0: f8bd 300e ldrh.w r3, [sp, #14] + 80019f4: 8033 strh r3, [r6, #0] + 80019f6: b13d cbz r5, 8001a08 + 80019f8: f9bd 300e ldrsh.w r3, [sp, #14] + 80019fc: ee07 3a90 vmov s15, r3 + 8001a00: eefa 7acc vcvt.f32.s32 s15, s15, #8 + 8001a04: edc5 7a00 vstr s15, [r5] + 8001a08: 2001 movs r0, #1 + 8001a0a: e7d2 b.n 80019b2 + 8001a0c: 08009a2c .word 0x08009a2c + +08001a10 : + 8001a10: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 8001a14: 460f mov r7, r1 + 8001a16: b086 sub sp, #24 + 8001a18: 4616 mov r6, r2 + 8001a1a: 461d mov r5, r3 + 8001a1c: 4604 mov r4, r0 + 8001a1e: b918 cbnz r0, 8001a28 + 8001a20: 2000 movs r0, #0 + 8001a22: b006 add sp, #24 + 8001a24: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 8001a28: f04f 38ff mov.w r8, #4294967295 + 8001a2c: f8cd 8000 str.w r8, [sp] + 8001a30: 2301 movs r3, #1 + 8001a32: 4a1b ldr r2, [pc, #108] ; (8001aa0 ) + 8001a34: 6800 ldr r0, [r0, #0] + 8001a36: 213c movs r1, #60 ; 0x3c + 8001a38: f001 f814 bl 8002a64 + 8001a3c: 2800 cmp r0, #0 + 8001a3e: d1ef bne.n 8001a20 + 8001a40: f8cd 8000 str.w r8, [sp] + 8001a44: 2308 movs r3, #8 + 8001a46: aa04 add r2, sp, #16 + 8001a48: 213c movs r1, #60 ; 0x3c + 8001a4a: 6820 ldr r0, [r4, #0] + 8001a4c: f001 f8de bl 8002c0c + 8001a50: 2800 cmp r0, #0 + 8001a52: d1e5 bne.n 8001a20 + 8001a54: f89d 3011 ldrb.w r3, [sp, #17] + 8001a58: f88d 300a strb.w r3, [sp, #10] + 8001a5c: f89d 3010 ldrb.w r3, [sp, #16] + 8001a60: f88d 300b strb.w r3, [sp, #11] + 8001a64: f89d 3013 ldrb.w r3, [sp, #19] + 8001a68: f88d 300e strb.w r3, [sp, #14] + 8001a6c: f89d 3012 ldrb.w r3, [sp, #18] + 8001a70: f88d 300f strb.w r3, [sp, #15] + 8001a74: f89d 3015 ldrb.w r3, [sp, #21] + 8001a78: f88d 300c strb.w r3, [sp, #12] + 8001a7c: f89d 3014 ldrb.w r3, [sp, #20] + 8001a80: f88d 300d strb.w r3, [sp, #13] + 8001a84: b117 cbz r7, 8001a8c + 8001a86: f8bd 300a ldrh.w r3, [sp, #10] + 8001a8a: 803b strh r3, [r7, #0] + 8001a8c: b116 cbz r6, 8001a94 + 8001a8e: f8bd 300c ldrh.w r3, [sp, #12] + 8001a92: 8033 strh r3, [r6, #0] + 8001a94: b115 cbz r5, 8001a9c + 8001a96: f8bd 300e ldrh.w r3, [sp, #14] + 8001a9a: 802b strh r3, [r5, #0] + 8001a9c: 2001 movs r0, #1 + 8001a9e: e7c0 b.n 8001a22 + 8001aa0: 08009a2b .word 0x08009a2b + +08001aa4 : + 8001aa4: b57f push {r0, r1, r2, r3, r4, r5, r6, lr} + 8001aa6: 4616 mov r6, r2 + 8001aa8: aa04 add r2, sp, #16 + 8001aaa: f04f 35ff mov.w r5, #4294967295 + 8001aae: f802 1d01 strb.w r1, [r2, #-1]! + 8001ab2: 9500 str r5, [sp, #0] + 8001ab4: 4604 mov r4, r0 + 8001ab6: 2301 movs r3, #1 + 8001ab8: 213c movs r1, #60 ; 0x3c + 8001aba: 6800 ldr r0, [r0, #0] + 8001abc: f000 ffd2 bl 8002a64 + 8001ac0: b958 cbnz r0, 8001ada + 8001ac2: 9500 str r5, [sp, #0] + 8001ac4: 2301 movs r3, #1 + 8001ac6: 4632 mov r2, r6 + 8001ac8: 213c movs r1, #60 ; 0x3c + 8001aca: 6820 ldr r0, [r4, #0] + 8001acc: f001 f89e bl 8002c0c + 8001ad0: fab0 f080 clz r0, r0 + 8001ad4: 0940 lsrs r0, r0, #5 + 8001ad6: b004 add sp, #16 + 8001ad8: bd70 pop {r4, r5, r6, pc} + 8001ada: 2000 movs r0, #0 + 8001adc: e7fb b.n 8001ad6 + +08001ade : + 8001ade: b51f push {r0, r1, r2, r3, r4, lr} + 8001ae0: f04f 33ff mov.w r3, #4294967295 + 8001ae4: 9300 str r3, [sp, #0] + 8001ae6: f88d 100c strb.w r1, [sp, #12] + 8001aea: f88d 200d strb.w r2, [sp, #13] + 8001aee: 2302 movs r3, #2 + 8001af0: aa03 add r2, sp, #12 + 8001af2: 213c movs r1, #60 ; 0x3c + 8001af4: 6800 ldr r0, [r0, #0] + 8001af6: f000 ffb5 bl 8002a64 + 8001afa: fab0 f080 clz r0, r0 + 8001afe: 0940 lsrs r0, r0, #5 + 8001b00: b005 add sp, #20 + 8001b02: f85d fb04 ldr.w pc, [sp], #4 + +08001b06 : + 8001b06: b537 push {r0, r1, r2, r4, r5, lr} + 8001b08: 4604 mov r4, r0 + 8001b0a: b910 cbnz r0, 8001b12 + 8001b0c: 2000 movs r0, #0 + 8001b0e: b003 add sp, #12 + 8001b10: bd30 pop {r4, r5, pc} + 8001b12: aa02 add r2, sp, #8 + 8001b14: 2500 movs r5, #0 + 8001b16: f802 5d01 strb.w r5, [r2, #-1]! + 8001b1a: 4629 mov r1, r5 + 8001b1c: f7ff ffc2 bl 8001aa4 + 8001b20: 2800 cmp r0, #0 + 8001b22: d0f3 beq.n 8001b0c + 8001b24: 7961 ldrb r1, [r4, #5] + 8001b26: f89d 2007 ldrb.w r2, [sp, #7] + 8001b2a: f011 0101 ands.w r1, r1, #1 + 8001b2e: d010 beq.n 8001b52 + 8001b30: f042 0280 orr.w r2, r2, #128 ; 0x80 + 8001b34: 4629 mov r1, r5 + 8001b36: 4620 mov r0, r4 + 8001b38: f7ff ffd1 bl 8001ade + 8001b3c: 2800 cmp r0, #0 + 8001b3e: d0e5 beq.n 8001b0c + 8001b40: 7922 ldrb r2, [r4, #4] + 8001b42: 2102 movs r1, #2 + 8001b44: 4620 mov r0, r4 + 8001b46: f7ff ffca bl 8001ade + 8001b4a: 3000 adds r0, #0 + 8001b4c: bf18 it ne + 8001b4e: 2001 movne r0, #1 + 8001b50: e7dd b.n 8001b0e + 8001b52: f002 027f and.w r2, r2, #127 ; 0x7f + 8001b56: e7ee b.n 8001b36 + +08001b58 : + 8001b58: b538 push {r3, r4, r5, lr} + 8001b5a: 4a0e ldr r2, [pc, #56] ; (8001b94 ) + 8001b5c: 4b0e ldr r3, [pc, #56] ; (8001b98 ) + 8001b5e: 4605 mov r5, r0 + 8001b60: 7818 ldrb r0, [r3, #0] + 8001b62: f44f 737a mov.w r3, #1000 ; 0x3e8 + 8001b66: fbb3 f3f0 udiv r3, r3, r0 + 8001b6a: 6810 ldr r0, [r2, #0] + 8001b6c: fbb0 f0f3 udiv r0, r0, r3 + 8001b70: f000 f8aa bl 8001cc8 + 8001b74: 4604 mov r4, r0 + 8001b76: b958 cbnz r0, 8001b90 + 8001b78: 2d0f cmp r5, #15 + 8001b7a: d809 bhi.n 8001b90 + 8001b7c: 4602 mov r2, r0 + 8001b7e: 4629 mov r1, r5 + 8001b80: f04f 30ff mov.w r0, #4294967295 + 8001b84: f000 f85e bl 8001c44 + 8001b88: 4b04 ldr r3, [pc, #16] ; (8001b9c ) + 8001b8a: 4620 mov r0, r4 + 8001b8c: 601d str r5, [r3, #0] + 8001b8e: bd38 pop {r3, r4, r5, pc} + 8001b90: 2001 movs r0, #1 + 8001b92: e7fc b.n 8001b8e + 8001b94: 20000000 .word 0x20000000 + 8001b98: 20000004 .word 0x20000004 + 8001b9c: 20000008 .word 0x20000008 + +08001ba0 : + 8001ba0: b508 push {r3, lr} + 8001ba2: 4b0b ldr r3, [pc, #44] ; (8001bd0 ) + 8001ba4: 681a ldr r2, [r3, #0] + 8001ba6: f442 7200 orr.w r2, r2, #512 ; 0x200 + 8001baa: 601a str r2, [r3, #0] + 8001bac: 681a ldr r2, [r3, #0] + 8001bae: f442 6280 orr.w r2, r2, #1024 ; 0x400 + 8001bb2: 601a str r2, [r3, #0] + 8001bb4: 681a ldr r2, [r3, #0] + 8001bb6: f442 7280 orr.w r2, r2, #256 ; 0x100 + 8001bba: 601a str r2, [r3, #0] + 8001bbc: 2003 movs r0, #3 + 8001bbe: f000 f82f bl 8001c20 + 8001bc2: 2000 movs r0, #0 + 8001bc4: f7ff ffc8 bl 8001b58 + 8001bc8: f7ff fc52 bl 8001470 + 8001bcc: 2000 movs r0, #0 + 8001bce: bd08 pop {r3, pc} + 8001bd0: 40023c00 .word 0x40023c00 + +08001bd4 : + 8001bd4: 4a03 ldr r2, [pc, #12] ; (8001be4 ) + 8001bd6: 4b04 ldr r3, [pc, #16] ; (8001be8 ) + 8001bd8: 6811 ldr r1, [r2, #0] + 8001bda: 781b ldrb r3, [r3, #0] + 8001bdc: 440b add r3, r1 + 8001bde: 6013 str r3, [r2, #0] + 8001be0: 4770 bx lr + 8001be2: bf00 nop + 8001be4: 20000410 .word 0x20000410 + 8001be8: 20000004 .word 0x20000004 + +08001bec : + 8001bec: 4b01 ldr r3, [pc, #4] ; (8001bf4 ) + 8001bee: 6818 ldr r0, [r3, #0] + 8001bf0: 4770 bx lr + 8001bf2: bf00 nop + 8001bf4: 20000410 .word 0x20000410 + +08001bf8 : + 8001bf8: b538 push {r3, r4, r5, lr} + 8001bfa: 4604 mov r4, r0 + 8001bfc: f7ff fff6 bl 8001bec + 8001c00: 1c63 adds r3, r4, #1 + 8001c02: bf1c itt ne + 8001c04: 4b05 ldrne r3, [pc, #20] ; (8001c1c ) + 8001c06: 781b ldrbne r3, [r3, #0] + 8001c08: 4605 mov r5, r0 + 8001c0a: bf18 it ne + 8001c0c: 18e4 addne r4, r4, r3 + 8001c0e: f7ff ffed bl 8001bec + 8001c12: 1b40 subs r0, r0, r5 + 8001c14: 42a0 cmp r0, r4 + 8001c16: d3fa bcc.n 8001c0e + 8001c18: bd38 pop {r3, r4, r5, pc} + 8001c1a: bf00 nop + 8001c1c: 20000004 .word 0x20000004 + +08001c20 : + 8001c20: 4a07 ldr r2, [pc, #28] ; (8001c40 ) + 8001c22: 68d3 ldr r3, [r2, #12] + 8001c24: f423 63e0 bic.w r3, r3, #1792 ; 0x700 + 8001c28: 041b lsls r3, r3, #16 + 8001c2a: 0c1b lsrs r3, r3, #16 + 8001c2c: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 + 8001c30: 0200 lsls r0, r0, #8 + 8001c32: f443 3300 orr.w r3, r3, #131072 ; 0x20000 + 8001c36: f400 60e0 and.w r0, r0, #1792 ; 0x700 + 8001c3a: 4303 orrs r3, r0 + 8001c3c: 60d3 str r3, [r2, #12] + 8001c3e: 4770 bx lr + 8001c40: e000ed00 .word 0xe000ed00 + +08001c44 : + 8001c44: 4b17 ldr r3, [pc, #92] ; (8001ca4 ) + 8001c46: b570 push {r4, r5, r6, lr} + 8001c48: 68dc ldr r4, [r3, #12] + 8001c4a: f3c4 2402 ubfx r4, r4, #8, #3 + 8001c4e: f1c4 0507 rsb r5, r4, #7 + 8001c52: 2d04 cmp r5, #4 + 8001c54: f104 0304 add.w r3, r4, #4 + 8001c58: bf28 it cs + 8001c5a: 2504 movcs r5, #4 + 8001c5c: f04f 36ff mov.w r6, #4294967295 + 8001c60: 2b06 cmp r3, #6 + 8001c62: fa06 f305 lsl.w r3, r6, r5 + 8001c66: bf8c ite hi + 8001c68: 3c03 subhi r4, #3 + 8001c6a: 2400 movls r4, #0 + 8001c6c: ea21 0303 bic.w r3, r1, r3 + 8001c70: 40a3 lsls r3, r4 + 8001c72: fa06 f404 lsl.w r4, r6, r4 + 8001c76: ea22 0404 bic.w r4, r2, r4 + 8001c7a: 2800 cmp r0, #0 + 8001c7c: ea43 0304 orr.w r3, r3, r4 + 8001c80: bfa8 it ge + 8001c82: f100 4060 addge.w r0, r0, #3758096384 ; 0xe0000000 + 8001c86: ea4f 1303 mov.w r3, r3, lsl #4 + 8001c8a: bfbc itt lt + 8001c8c: f000 000f andlt.w r0, r0, #15 + 8001c90: 4a05 ldrlt r2, [pc, #20] ; (8001ca8 ) + 8001c92: b2db uxtb r3, r3 + 8001c94: bfaa itet ge + 8001c96: f500 4061 addge.w r0, r0, #57600 ; 0xe100 + 8001c9a: 5413 strblt r3, [r2, r0] + 8001c9c: f880 3300 strbge.w r3, [r0, #768] ; 0x300 + 8001ca0: bd70 pop {r4, r5, r6, pc} + 8001ca2: bf00 nop + 8001ca4: e000ed00 .word 0xe000ed00 + 8001ca8: e000ed14 .word 0xe000ed14 + +08001cac : + 8001cac: 2800 cmp r0, #0 + 8001cae: db08 blt.n 8001cc2 + 8001cb0: 0942 lsrs r2, r0, #5 + 8001cb2: 2301 movs r3, #1 + 8001cb4: f000 001f and.w r0, r0, #31 + 8001cb8: fa03 f000 lsl.w r0, r3, r0 + 8001cbc: 4b01 ldr r3, [pc, #4] ; (8001cc4 ) + 8001cbe: f843 0022 str.w r0, [r3, r2, lsl #2] + 8001cc2: 4770 bx lr + 8001cc4: e000e100 .word 0xe000e100 + +08001cc8 : + 8001cc8: 3801 subs r0, #1 + 8001cca: f1b0 7f80 cmp.w r0, #16777216 ; 0x1000000 + 8001cce: d20a bcs.n 8001ce6 + 8001cd0: 4b06 ldr r3, [pc, #24] ; (8001cec ) + 8001cd2: 4a07 ldr r2, [pc, #28] ; (8001cf0 ) + 8001cd4: 6058 str r0, [r3, #4] + 8001cd6: 21f0 movs r1, #240 ; 0xf0 + 8001cd8: f882 1023 strb.w r1, [r2, #35] ; 0x23 + 8001cdc: 2000 movs r0, #0 + 8001cde: 2207 movs r2, #7 + 8001ce0: 6098 str r0, [r3, #8] + 8001ce2: 601a str r2, [r3, #0] + 8001ce4: 4770 bx lr + 8001ce6: 2001 movs r0, #1 + 8001ce8: 4770 bx lr + 8001cea: bf00 nop + 8001cec: e000e010 .word 0xe000e010 + 8001cf0: e000ed00 .word 0xe000ed00 + +08001cf4 : + 8001cf4: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 8001cf8: b085 sub sp, #20 + 8001cfa: 680b ldr r3, [r1, #0] + 8001cfc: f8df 818c ldr.w r8, [pc, #396] ; 8001e8c + 8001d00: 4a60 ldr r2, [pc, #384] ; (8001e84 ) + 8001d02: 9301 str r3, [sp, #4] + 8001d04: f04f 0901 mov.w r9, #1 + 8001d08: 2300 movs r3, #0 + 8001d0a: 9d01 ldr r5, [sp, #4] + 8001d0c: fa09 f403 lsl.w r4, r9, r3 + 8001d10: 4025 ands r5, r4 + 8001d12: 42ac cmp r4, r5 + 8001d14: f040 80a6 bne.w 8001e64 + 8001d18: 684c ldr r4, [r1, #4] + 8001d1a: f024 0c10 bic.w ip, r4, #16 + 8001d1e: ea4f 0e43 mov.w lr, r3, lsl #1 + 8001d22: 2603 movs r6, #3 + 8001d24: f10c 37ff add.w r7, ip, #4294967295 + 8001d28: fa06 f60e lsl.w r6, r6, lr + 8001d2c: 2f01 cmp r7, #1 + 8001d2e: ea6f 0606 mvn.w r6, r6 + 8001d32: d811 bhi.n 8001d58 + 8001d34: 6887 ldr r7, [r0, #8] + 8001d36: ea07 0a06 and.w sl, r7, r6 + 8001d3a: 68cf ldr r7, [r1, #12] + 8001d3c: fa07 f70e lsl.w r7, r7, lr + 8001d40: ea47 070a orr.w r7, r7, sl + 8001d44: 6087 str r7, [r0, #8] + 8001d46: 6847 ldr r7, [r0, #4] + 8001d48: ea27 0a05 bic.w sl, r7, r5 + 8001d4c: f3c4 1700 ubfx r7, r4, #4, #1 + 8001d50: 409f lsls r7, r3 + 8001d52: ea47 070a orr.w r7, r7, sl + 8001d56: 6047 str r7, [r0, #4] + 8001d58: 68c7 ldr r7, [r0, #12] + 8001d5a: ea07 0a06 and.w sl, r7, r6 + 8001d5e: 688f ldr r7, [r1, #8] + 8001d60: fa07 f70e lsl.w r7, r7, lr + 8001d64: ea47 070a orr.w r7, r7, sl + 8001d68: f1bc 0f02 cmp.w ip, #2 + 8001d6c: 60c7 str r7, [r0, #12] + 8001d6e: d116 bne.n 8001d9e + 8001d70: ea4f 0ad3 mov.w sl, r3, lsr #3 + 8001d74: eb00 0a8a add.w sl, r0, sl, lsl #2 + 8001d78: f003 0b07 and.w fp, r3, #7 + 8001d7c: f8da 7020 ldr.w r7, [sl, #32] + 8001d80: ea4f 0b8b mov.w fp, fp, lsl #2 + 8001d84: f04f 0c0f mov.w ip, #15 + 8001d88: fa0c fc0b lsl.w ip, ip, fp + 8001d8c: ea27 0c0c bic.w ip, r7, ip + 8001d90: 690f ldr r7, [r1, #16] + 8001d92: fa07 f70b lsl.w r7, r7, fp + 8001d96: ea47 070c orr.w r7, r7, ip + 8001d9a: f8ca 7020 str.w r7, [sl, #32] + 8001d9e: 6807 ldr r7, [r0, #0] + 8001da0: 403e ands r6, r7 + 8001da2: f004 0703 and.w r7, r4, #3 + 8001da6: fa07 fe0e lsl.w lr, r7, lr + 8001daa: ea4e 0606 orr.w r6, lr, r6 + 8001dae: 6006 str r6, [r0, #0] + 8001db0: 00e6 lsls r6, r4, #3 + 8001db2: d557 bpl.n 8001e64 + 8001db4: f04f 0b00 mov.w fp, #0 + 8001db8: f8cd b00c str.w fp, [sp, #12] + 8001dbc: f8d8 7044 ldr.w r7, [r8, #68] ; 0x44 + 8001dc0: 4e31 ldr r6, [pc, #196] ; (8001e88 ) + 8001dc2: f447 4780 orr.w r7, r7, #16384 ; 0x4000 + 8001dc6: f8c8 7044 str.w r7, [r8, #68] ; 0x44 + 8001dca: f8d8 7044 ldr.w r7, [r8, #68] ; 0x44 + 8001dce: f407 4780 and.w r7, r7, #16384 ; 0x4000 + 8001dd2: 9703 str r7, [sp, #12] + 8001dd4: 9f03 ldr r7, [sp, #12] + 8001dd6: f023 0703 bic.w r7, r3, #3 + 8001dda: f107 4780 add.w r7, r7, #1073741824 ; 0x40000000 + 8001dde: f507 379c add.w r7, r7, #79872 ; 0x13800 + 8001de2: f003 0e03 and.w lr, r3, #3 + 8001de6: f8d7 a008 ldr.w sl, [r7, #8] + 8001dea: ea4f 0e8e mov.w lr, lr, lsl #2 + 8001dee: f04f 0c0f mov.w ip, #15 + 8001df2: fa0c fc0e lsl.w ip, ip, lr + 8001df6: 42b0 cmp r0, r6 + 8001df8: ea2a 0c0c bic.w ip, sl, ip + 8001dfc: d039 beq.n 8001e72 + 8001dfe: f506 6680 add.w r6, r6, #1024 ; 0x400 + 8001e02: 42b0 cmp r0, r6 + 8001e04: d037 beq.n 8001e76 + 8001e06: f506 6680 add.w r6, r6, #1024 ; 0x400 + 8001e0a: 42b0 cmp r0, r6 + 8001e0c: d035 beq.n 8001e7a + 8001e0e: f506 6680 add.w r6, r6, #1024 ; 0x400 + 8001e12: 42b0 cmp r0, r6 + 8001e14: d033 beq.n 8001e7e + 8001e16: f506 6680 add.w r6, r6, #1024 ; 0x400 + 8001e1a: 42b0 cmp r0, r6 + 8001e1c: bf14 ite ne + 8001e1e: 2607 movne r6, #7 + 8001e20: 2604 moveq r6, #4 + 8001e22: fa06 f60e lsl.w r6, r6, lr + 8001e26: ea46 060c orr.w r6, r6, ip + 8001e2a: 60be str r6, [r7, #8] + 8001e2c: 6816 ldr r6, [r2, #0] + 8001e2e: 43ef mvns r7, r5 + 8001e30: f414 3f80 tst.w r4, #65536 ; 0x10000 + 8001e34: bf0c ite eq + 8001e36: 403e andeq r6, r7 + 8001e38: 432e orrne r6, r5 + 8001e3a: 6016 str r6, [r2, #0] + 8001e3c: 6856 ldr r6, [r2, #4] + 8001e3e: f414 3f00 tst.w r4, #131072 ; 0x20000 + 8001e42: bf0c ite eq + 8001e44: 403e andeq r6, r7 + 8001e46: 432e orrne r6, r5 + 8001e48: 6056 str r6, [r2, #4] + 8001e4a: 6896 ldr r6, [r2, #8] + 8001e4c: f414 1f80 tst.w r4, #1048576 ; 0x100000 + 8001e50: bf0c ite eq + 8001e52: 403e andeq r6, r7 + 8001e54: 432e orrne r6, r5 + 8001e56: 6096 str r6, [r2, #8] + 8001e58: 68d6 ldr r6, [r2, #12] + 8001e5a: 02a4 lsls r4, r4, #10 + 8001e5c: bf54 ite pl + 8001e5e: 403e andpl r6, r7 + 8001e60: 432e orrmi r6, r5 + 8001e62: 60d6 str r6, [r2, #12] + 8001e64: 3301 adds r3, #1 + 8001e66: 2b10 cmp r3, #16 + 8001e68: f47f af4f bne.w 8001d0a + 8001e6c: b005 add sp, #20 + 8001e6e: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 8001e72: 465e mov r6, fp + 8001e74: e7d5 b.n 8001e22 + 8001e76: 2601 movs r6, #1 + 8001e78: e7d3 b.n 8001e22 + 8001e7a: 2602 movs r6, #2 + 8001e7c: e7d1 b.n 8001e22 + 8001e7e: 2603 movs r6, #3 + 8001e80: e7cf b.n 8001e22 + 8001e82: bf00 nop + 8001e84: 40013c00 .word 0x40013c00 + 8001e88: 40020000 .word 0x40020000 + 8001e8c: 40023800 .word 0x40023800 + +08001e90 : + 8001e90: b10a cbz r2, 8001e96 + 8001e92: 6181 str r1, [r0, #24] + 8001e94: 4770 bx lr + 8001e96: 0409 lsls r1, r1, #16 + 8001e98: e7fb b.n 8001e92 + +08001e9a : + 8001e9a: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} + 8001e9e: 4604 mov r4, r0 + 8001ea0: f890 02b8 ldrb.w r0, [r0, #696] ; 0x2b8 + 8001ea4: f89d 7030 ldrb.w r7, [sp, #48] ; 0x30 + 8001ea8: f89d c034 ldrb.w ip, [sp, #52] ; 0x34 + 8001eac: f8bd e038 ldrh.w lr, [sp, #56] ; 0x38 + 8001eb0: 2801 cmp r0, #1 + 8001eb2: d027 beq.n 8001f04 + 8001eb4: 2028 movs r0, #40 ; 0x28 + 8001eb6: fb00 4001 mla r0, r0, r1, r4 + 8001eba: 2501 movs r5, #1 + 8001ebc: 2600 movs r6, #0 + 8001ebe: f012 0f80 tst.w r2, #128 ; 0x80 + 8001ec2: f884 52b8 strb.w r5, [r4, #696] ; 0x2b8 + 8001ec6: f002 097f and.w r9, r2, #127 ; 0x7f + 8001eca: bf08 it eq + 8001ecc: 4635 moveq r5, r6 + 8001ece: f880 603d strb.w r6, [r0, #61] ; 0x3d + 8001ed2: f880 3038 strb.w r3, [r0, #56] ; 0x38 + 8001ed6: f880 1039 strb.w r1, [r0, #57] ; 0x39 + 8001eda: f880 c03f strb.w ip, [r0, #63] ; 0x3f + 8001ede: f880 903a strb.w r9, [r0, #58] ; 0x3a + 8001ee2: f880 503b strb.w r5, [r0, #59] ; 0x3b + 8001ee6: f880 703c strb.w r7, [r0, #60] ; 0x3c + 8001eea: f8a0 e040 strh.w lr, [r0, #64] ; 0x40 + 8001eee: e9cd ce01 strd ip, lr, [sp, #4] + 8001ef2: 9700 str r7, [sp, #0] + 8001ef4: 6820 ldr r0, [r4, #0] + 8001ef6: f002 f897 bl 8004028 + 8001efa: f884 62b8 strb.w r6, [r4, #696] ; 0x2b8 + 8001efe: b004 add sp, #16 + 8001f00: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 8001f04: 2002 movs r0, #2 + 8001f06: e7fa b.n 8001efe + +08001f08 : + 8001f08: f890 32b8 ldrb.w r3, [r0, #696] ; 0x2b8 + 8001f0c: 2b01 cmp r3, #1 + 8001f0e: b510 push {r4, lr} + 8001f10: 4604 mov r4, r0 + 8001f12: d009 beq.n 8001f28 + 8001f14: 2301 movs r3, #1 + 8001f16: f880 32b8 strb.w r3, [r0, #696] ; 0x2b8 + 8001f1a: 6800 ldr r0, [r0, #0] + 8001f1c: f002 f90c bl 8004138 + 8001f20: 2000 movs r0, #0 + 8001f22: f884 02b8 strb.w r0, [r4, #696] ; 0x2b8 + 8001f26: bd10 pop {r4, pc} + 8001f28: 2002 movs r0, #2 + 8001f2a: e7fc b.n 8001f26 + +08001f2c : + 8001f2c: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 8001f30: 4607 mov r7, r0 + 8001f32: b08a sub sp, #40 ; 0x28 + 8001f34: 2800 cmp r0, #0 + 8001f36: d041 beq.n 8001fbc + 8001f38: f890 32b9 ldrb.w r3, [r0, #697] ; 0x2b9 + 8001f3c: 6804 ldr r4, [r0, #0] + 8001f3e: f003 02ff and.w r2, r3, #255 ; 0xff + 8001f42: b91b cbnz r3, 8001f4c + 8001f44: f880 22b8 strb.w r2, [r0, #696] ; 0x2b8 + 8001f48: f003 f940 bl 80051cc + 8001f4c: 2303 movs r3, #3 + 8001f4e: f887 32b9 strb.w r3, [r7, #697] ; 0x2b9 + 8001f52: 6be3 ldr r3, [r4, #60] ; 0x3c + 8001f54: 463c mov r4, r7 + 8001f56: f413 7380 ands.w r3, r3, #256 ; 0x100 + 8001f5a: f854 0b10 ldr.w r0, [r4], #16 + 8001f5e: bf08 it eq + 8001f60: 613b streq r3, [r7, #16] + 8001f62: f001 ff1d bl 8003da0 + 8001f66: cc0f ldmia r4!, {r0, r1, r2, r3} + 8001f68: 466d mov r5, sp + 8001f6a: c50f stmia r5!, {r0, r1, r2, r3} + 8001f6c: cc0f ldmia r4!, {r0, r1, r2, r3} + 8001f6e: c50f stmia r5!, {r0, r1, r2, r3} + 8001f70: e894 0003 ldmia.w r4, {r0, r1} + 8001f74: e885 0003 stmia.w r5, {r0, r1} + 8001f78: f107 0804 add.w r8, r7, #4 + 8001f7c: 463e mov r6, r7 + 8001f7e: e898 000e ldmia.w r8, {r1, r2, r3} + 8001f82: 6838 ldr r0, [r7, #0] + 8001f84: f001 fec6 bl 8003d14 + 8001f88: f856 0b10 ldr.w r0, [r6], #16 + 8001f8c: 2101 movs r1, #1 + 8001f8e: f001 ff0d bl 8003dac + 8001f92: ce0f ldmia r6!, {r0, r1, r2, r3} + 8001f94: 466d mov r5, sp + 8001f96: c50f stmia r5!, {r0, r1, r2, r3} + 8001f98: ce0f ldmia r6!, {r0, r1, r2, r3} + 8001f9a: c50f stmia r5!, {r0, r1, r2, r3} + 8001f9c: e894 0003 ldmia.w r4, {r0, r1} + 8001fa0: e885 0003 stmia.w r5, {r0, r1} + 8001fa4: e898 000e ldmia.w r8, {r1, r2, r3} + 8001fa8: 6838 ldr r0, [r7, #0] + 8001faa: f001 ffbd bl 8003f28 + 8001fae: 2301 movs r3, #1 + 8001fb0: f887 32b9 strb.w r3, [r7, #697] ; 0x2b9 + 8001fb4: 2000 movs r0, #0 + 8001fb6: b00a add sp, #40 ; 0x28 + 8001fb8: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 8001fbc: 2001 movs r0, #1 + 8001fbe: e7fa b.n 8001fb6 + +08001fc0 : + 8001fc0: b4f0 push {r4, r5, r6, r7} + 8001fc2: 2428 movs r4, #40 ; 0x28 + 8001fc4: fb04 0401 mla r4, r4, r1, r0 + 8001fc8: f89d 7010 ldrb.w r7, [sp, #16] + 8001fcc: 9e05 ldr r6, [sp, #20] + 8001fce: f8bd 5018 ldrh.w r5, [sp, #24] + 8001fd2: f89d c01c ldrb.w ip, [sp, #28] + 8001fd6: f884 203b strb.w r2, [r4, #59] ; 0x3b + 8001fda: f884 303f strb.w r3, [r4, #63] ; 0x3f + 8001fde: b97f cbnz r7, 8002000 + 8001fe0: 2703 movs r7, #3 + 8001fe2: 2b02 cmp r3, #2 + 8001fe4: f884 7042 strb.w r7, [r4, #66] ; 0x42 + 8001fe8: f884 c03d strb.w ip, [r4, #61] ; 0x3d + 8001fec: d02b beq.n 8002046 + 8001fee: 42bb cmp r3, r7 + 8001ff0: d029 beq.n 8002046 + 8001ff2: 2b01 cmp r3, #1 + 8001ff4: d131 bne.n 800205a + 8001ff6: 2328 movs r3, #40 ; 0x28 + 8001ff8: fb03 0301 mla r3, r3, r1, r0 + 8001ffc: 2200 movs r2, #0 + 8001ffe: e02a b.n 8002056 + 8002000: f04f 0c02 mov.w ip, #2 + 8002004: f884 c042 strb.w ip, [r4, #66] ; 0x42 + 8002008: 2b03 cmp r3, #3 + 800200a: d826 bhi.n 800205a + 800200c: a401 add r4, pc, #4 ; (adr r4, 8002014 ) + 800200e: f854 f023 ldr.w pc, [r4, r3, lsl #2] + 8002012: bf00 nop + 8002014: 08002025 .word 0x08002025 + 8002018: 08001ff7 .word 0x08001ff7 + 800201c: 08002047 .word 0x08002047 + 8002020: 08002047 .word 0x08002047 + 8002024: 2f01 cmp r7, #1 + 8002026: d118 bne.n 800205a + 8002028: b9ba cbnz r2, 800205a + 800202a: b925 cbnz r5, 8002036 + 800202c: 2328 movs r3, #40 ; 0x28 + 800202e: fb03 0301 mla r3, r3, r1, r0 + 8002032: f883 7051 strb.w r7, [r3, #81] ; 0x51 + 8002036: 2328 movs r3, #40 ; 0x28 + 8002038: fb03 0301 mla r3, r3, r1, r0 + 800203c: f893 2051 ldrb.w r2, [r3, #81] ; 0x51 + 8002040: b14a cbz r2, 8002056 + 8002042: 2202 movs r2, #2 + 8002044: e007 b.n 8002056 + 8002046: 2328 movs r3, #40 ; 0x28 + 8002048: fb03 0301 mla r3, r3, r1, r0 + 800204c: b9ca cbnz r2, 8002082 + 800204e: f893 4051 ldrb.w r4, [r3, #81] ; 0x51 + 8002052: 2c00 cmp r4, #0 + 8002054: d1f5 bne.n 8002042 + 8002056: f883 2042 strb.w r2, [r3, #66] ; 0x42 + 800205a: 2428 movs r4, #40 ; 0x28 + 800205c: fb04 0301 mla r3, r4, r1, r0 + 8002060: 2200 movs r2, #0 + 8002062: f883 1039 strb.w r1, [r3, #57] ; 0x39 + 8002066: 4619 mov r1, r3 + 8002068: e9c3 6511 strd r6, r5, [r3, #68] ; 0x44 + 800206c: f883 205c strb.w r2, [r3, #92] ; 0x5c + 8002070: 64da str r2, [r3, #76] ; 0x4c + 8002072: f883 205d strb.w r2, [r3, #93] ; 0x5d + 8002076: 3138 adds r1, #56 ; 0x38 + 8002078: 7c02 ldrb r2, [r0, #16] + 800207a: 6800 ldr r0, [r0, #0] + 800207c: bcf0 pop {r4, r5, r6, r7} + 800207e: f002 b8bf b.w 8004200 + 8002082: f893 2050 ldrb.w r2, [r3, #80] ; 0x50 + 8002086: e7db b.n 8002040 + +08002088 : + 8002088: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 800208c: 6806 ldr r6, [r0, #0] + 800208e: b085 sub sp, #20 + 8002090: 4605 mov r5, r0 + 8002092: 4630 mov r0, r6 + 8002094: f001 feea bl 8003e6c + 8002098: 2801 cmp r0, #1 + 800209a: f040 80e4 bne.w 8002266 + 800209e: 6828 ldr r0, [r5, #0] + 80020a0: f001 fee0 bl 8003e64 + 80020a4: 2800 cmp r0, #0 + 80020a6: f000 80de beq.w 8002266 + 80020aa: 6828 ldr r0, [r5, #0] + 80020ac: f001 feda bl 8003e64 + 80020b0: 0284 lsls r4, r0, #10 + 80020b2: bf48 it mi + 80020b4: 682b ldrmi r3, [r5, #0] + 80020b6: 6828 ldr r0, [r5, #0] + 80020b8: bf44 itt mi + 80020ba: f44f 1200 movmi.w r2, #2097152 ; 0x200000 + 80020be: 615a strmi r2, [r3, #20] + 80020c0: f001 fed0 bl 8003e64 + 80020c4: 02c0 lsls r0, r0, #11 + 80020c6: bf48 it mi + 80020c8: 682b ldrmi r3, [r5, #0] + 80020ca: 6828 ldr r0, [r5, #0] + 80020cc: bf44 itt mi + 80020ce: f44f 1280 movmi.w r2, #1048576 ; 0x100000 + 80020d2: 615a strmi r2, [r3, #20] + 80020d4: f001 fec6 bl 8003e64 + 80020d8: 0141 lsls r1, r0, #5 + 80020da: bf48 it mi + 80020dc: 682b ldrmi r3, [r5, #0] + 80020de: 6828 ldr r0, [r5, #0] + 80020e0: bf44 itt mi + 80020e2: f04f 6280 movmi.w r2, #67108864 ; 0x4000000 + 80020e6: 615a strmi r2, [r3, #20] + 80020e8: f001 febc bl 8003e64 + 80020ec: 0782 lsls r2, r0, #30 + 80020ee: bf48 it mi + 80020f0: 682b ldrmi r3, [r5, #0] + 80020f2: 6828 ldr r0, [r5, #0] + 80020f4: bf44 itt mi + 80020f6: 2202 movmi r2, #2 + 80020f8: 615a strmi r2, [r3, #20] + 80020fa: f001 feb3 bl 8003e64 + 80020fe: 0083 lsls r3, r0, #2 + 8002100: d50e bpl.n 8002120 + 8002102: 682b ldr r3, [r5, #0] + 8002104: f04f 5200 mov.w r2, #536870912 ; 0x20000000 + 8002108: 615a str r2, [r3, #20] + 800210a: f8d6 3440 ldr.w r3, [r6, #1088] ; 0x440 + 800210e: 07df lsls r7, r3, #31 + 8002110: d406 bmi.n 8002120 + 8002112: 4628 mov r0, r5 + 8002114: f003 f8ac bl 8005270 + 8002118: 2101 movs r1, #1 + 800211a: 6828 ldr r0, [r5, #0] + 800211c: f001 feaa bl 8003e74 + 8002120: 6828 ldr r0, [r5, #0] + 8002122: f001 fe9f bl 8003e64 + 8002126: 01c4 lsls r4, r0, #7 + 8002128: d53c bpl.n 80021a4 + 800212a: 682c ldr r4, [r5, #0] + 800212c: f8d4 3440 ldr.w r3, [r4, #1088] ; 0x440 + 8002130: 9302 str r3, [sp, #8] + 8002132: f8d4 3440 ldr.w r3, [r4, #1088] ; 0x440 + 8002136: 9303 str r3, [sp, #12] + 8002138: 9b03 ldr r3, [sp, #12] + 800213a: f023 032e bic.w r3, r3, #46 ; 0x2e + 800213e: 9303 str r3, [sp, #12] + 8002140: 9b02 ldr r3, [sp, #8] + 8002142: 0798 lsls r0, r3, #30 + 8002144: d509 bpl.n 800215a + 8002146: 9b02 ldr r3, [sp, #8] + 8002148: 07d9 lsls r1, r3, #31 + 800214a: d502 bpl.n 8002152 + 800214c: 4628 mov r0, r5 + 800214e: f003 f88b bl 8005268 + 8002152: 9b03 ldr r3, [sp, #12] + 8002154: f043 0302 orr.w r3, r3, #2 + 8002158: 9303 str r3, [sp, #12] + 800215a: 9b02 ldr r3, [sp, #8] + 800215c: 071a lsls r2, r3, #28 + 800215e: d517 bpl.n 8002190 + 8002160: 9b03 ldr r3, [sp, #12] + 8002162: f043 0308 orr.w r3, r3, #8 + 8002166: 9303 str r3, [sp, #12] + 8002168: 9b02 ldr r3, [sp, #8] + 800216a: 075b lsls r3, r3, #29 + 800216c: f140 8086 bpl.w 800227c + 8002170: 69a9 ldr r1, [r5, #24] + 8002172: 2902 cmp r1, #2 + 8002174: d17a bne.n 800226c + 8002176: 9b02 ldr r3, [sp, #8] + 8002178: 6828 ldr r0, [r5, #0] + 800217a: f403 23c0 and.w r3, r3, #393216 ; 0x60000 + 800217e: f5b3 2f80 cmp.w r3, #262144 ; 0x40000 + 8002182: bf18 it ne + 8002184: 2101 movne r1, #1 + 8002186: f001 fe75 bl 8003e74 + 800218a: 4628 mov r0, r5 + 800218c: f003 f875 bl 800527a + 8002190: 9b02 ldr r3, [sp, #8] + 8002192: 069f lsls r7, r3, #26 + 8002194: bf42 ittt mi + 8002196: 9b03 ldrmi r3, [sp, #12] + 8002198: f043 0320 orrmi.w r3, r3, #32 + 800219c: 9303 strmi r3, [sp, #12] + 800219e: 9b03 ldr r3, [sp, #12] + 80021a0: f8c4 3440 str.w r3, [r4, #1088] ; 0x440 + 80021a4: 6828 ldr r0, [r5, #0] + 80021a6: f001 fe5d bl 8003e64 + 80021aa: 0704 lsls r4, r0, #28 + 80021ac: d505 bpl.n 80021ba + 80021ae: 4628 mov r0, r5 + 80021b0: f003 f856 bl 8005260 + 80021b4: 682b ldr r3, [r5, #0] + 80021b6: 2208 movs r2, #8 + 80021b8: 615a str r2, [r3, #20] + 80021ba: 6828 ldr r0, [r5, #0] + 80021bc: f001 fe52 bl 8003e64 + 80021c0: 0180 lsls r0, r0, #6 + 80021c2: d512 bpl.n 80021ea + 80021c4: 6828 ldr r0, [r5, #0] + 80021c6: f001 ffb2 bl 800412e + 80021ca: f506 63a0 add.w r3, r6, #1280 ; 0x500 + 80021ce: 9000 str r0, [sp, #0] + 80021d0: f04f 0900 mov.w r9, #0 + 80021d4: 9301 str r3, [sp, #4] + 80021d6: 2728 movs r7, #40 ; 0x28 + 80021d8: f04f 0802 mov.w r8, #2 + 80021dc: 68ab ldr r3, [r5, #8] + 80021de: 6828 ldr r0, [r5, #0] + 80021e0: 454b cmp r3, r9 + 80021e2: d84f bhi.n 8002284 + 80021e4: f04f 7300 mov.w r3, #33554432 ; 0x2000000 + 80021e8: 6143 str r3, [r0, #20] + 80021ea: 6828 ldr r0, [r5, #0] + 80021ec: f001 fe3a bl 8003e64 + 80021f0: 06c3 lsls r3, r0, #27 + 80021f2: d538 bpl.n 8002266 + 80021f4: 682c ldr r4, [r5, #0] + 80021f6: 69a3 ldr r3, [r4, #24] + 80021f8: f023 0310 bic.w r3, r3, #16 + 80021fc: 61a3 str r3, [r4, #24] + 80021fe: 6a26 ldr r6, [r4, #32] + 8002200: f3c6 4243 ubfx r2, r6, #17, #4 + 8002204: 2a02 cmp r2, #2 + 8002206: d129 bne.n 800225c + 8002208: f3c6 180a ubfx r8, r6, #4, #11 + 800220c: f1b8 0f00 cmp.w r8, #0 + 8002210: d024 beq.n 800225c + 8002212: f006 060f and.w r6, r6, #15 + 8002216: 2728 movs r7, #40 ; 0x28 + 8002218: fb07 5706 mla r7, r7, r6, r5 + 800221c: 6c79 ldr r1, [r7, #68] ; 0x44 + 800221e: b1e9 cbz r1, 800225c + 8002220: 4642 mov r2, r8 + 8002222: 4620 mov r0, r4 + 8002224: f001 fe10 bl 8003e48 + 8002228: 6c7b ldr r3, [r7, #68] ; 0x44 + 800222a: 4443 add r3, r8 + 800222c: 647b str r3, [r7, #68] ; 0x44 + 800222e: 6cfb ldr r3, [r7, #76] ; 0x4c + 8002230: 4443 add r3, r8 + 8002232: 64fb str r3, [r7, #76] ; 0x4c + 8002234: f504 64a0 add.w r4, r4, #1280 ; 0x500 + 8002238: 0173 lsls r3, r6, #5 + 800223a: 18e2 adds r2, r4, r3 + 800223c: 6911 ldr r1, [r2, #16] + 800223e: 4ab1 ldr r2, [pc, #708] ; (8002504 ) + 8002240: 400a ands r2, r1 + 8002242: b15a cbz r2, 800225c + 8002244: 58e2 ldr r2, [r4, r3] + 8002246: f022 4280 bic.w r2, r2, #1073741824 ; 0x40000000 + 800224a: f042 4200 orr.w r2, r2, #2147483648 ; 0x80000000 + 800224e: 50e2 str r2, [r4, r3] + 8002250: f897 3050 ldrb.w r3, [r7, #80] ; 0x50 + 8002254: f083 0301 eor.w r3, r3, #1 + 8002258: f887 3050 strb.w r3, [r7, #80] ; 0x50 + 800225c: 682a ldr r2, [r5, #0] + 800225e: 6993 ldr r3, [r2, #24] + 8002260: f043 0310 orr.w r3, r3, #16 + 8002264: 6193 str r3, [r2, #24] + 8002266: b005 add sp, #20 + 8002268: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 800226c: 68eb ldr r3, [r5, #12] + 800226e: 2b01 cmp r3, #1 + 8002270: bf04 itt eq + 8002272: f64e 2260 movweq r2, #60000 ; 0xea60 + 8002276: f8c4 2404 streq.w r2, [r4, #1028] ; 0x404 + 800227a: e786 b.n 800218a + 800227c: 4628 mov r0, r5 + 800227e: f003 f800 bl 8005282 + 8002282: e785 b.n 8002190 + 8002284: 9a00 ldr r2, [sp, #0] + 8002286: f009 030f and.w r3, r9, #15 + 800228a: fa22 f303 lsr.w r3, r2, r3 + 800228e: 07d9 lsls r1, r3, #31 + 8002290: f140 8095 bpl.w 80023be + 8002294: ea4f 1349 mov.w r3, r9, lsl #5 + 8002298: 9a01 ldr r2, [sp, #4] + 800229a: fa5f f689 uxtb.w r6, r9 + 800229e: 58d1 ldr r1, [r2, r3] + 80022a0: f500 6ba0 add.w fp, r0, #1280 ; 0x500 + 80022a4: ea4f 1a46 mov.w sl, r6, lsl #5 + 80022a8: eb0b 040a add.w r4, fp, sl + 80022ac: f411 4f00 tst.w r1, #32768 ; 0x8000 + 80022b0: 68a1 ldr r1, [r4, #8] + 80022b2: f000 811d beq.w 80024f0 + 80022b6: 074a lsls r2, r1, #29 + 80022b8: d513 bpl.n 80022e2 + 80022ba: 2104 movs r1, #4 + 80022bc: 60a1 str r1, [r4, #8] + 80022be: 68e1 ldr r1, [r4, #12] + 80022c0: f041 0102 orr.w r1, r1, #2 + 80022c4: 60e1 str r1, [r4, #12] + 80022c6: 68a1 ldr r1, [r4, #8] + 80022c8: 0588 lsls r0, r1, #22 + 80022ca: d54a bpl.n 8002362 + 80022cc: 68e3 ldr r3, [r4, #12] + 80022ce: 6828 ldr r0, [r5, #0] + 80022d0: f043 0302 orr.w r3, r3, #2 + 80022d4: 60e3 str r3, [r4, #12] + 80022d6: 4631 mov r1, r6 + 80022d8: f001 ff2e bl 8004138 + 80022dc: f44f 7300 mov.w r3, #512 ; 0x200 + 80022e0: e0e6 b.n 80024b0 + 80022e2: 68a1 ldr r1, [r4, #8] + 80022e4: 05cb lsls r3, r1, #23 + 80022e6: d510 bpl.n 800230a + 80022e8: f44f 7180 mov.w r1, #256 ; 0x100 + 80022ec: 60a1 str r1, [r4, #8] + 80022ee: fb07 5106 mla r1, r7, r6, r5 + 80022f2: f04f 0c07 mov.w ip, #7 + 80022f6: f881 c05d strb.w ip, [r1, #93] ; 0x5d + 80022fa: 68e1 ldr r1, [r4, #12] + 80022fc: f041 0102 orr.w r1, r1, #2 + 8002300: 60e1 str r1, [r4, #12] + 8002302: 4631 mov r1, r6 + 8002304: f001 ff18 bl 8004138 + 8002308: e7dd b.n 80022c6 + 800230a: 68a1 ldr r1, [r4, #8] + 800230c: 0689 lsls r1, r1, #26 + 800230e: d502 bpl.n 8002316 + 8002310: 2120 movs r1, #32 + 8002312: 60a1 str r1, [r4, #8] + 8002314: e7d7 b.n 80022c6 + 8002316: 68a1 ldr r1, [r4, #8] + 8002318: 070a lsls r2, r1, #28 + 800231a: d50e bpl.n 800233a + 800231c: 68e1 ldr r1, [r4, #12] + 800231e: f041 0102 orr.w r1, r1, #2 + 8002322: 60e1 str r1, [r4, #12] + 8002324: fb07 5106 mla r1, r7, r6, r5 + 8002328: f04f 0c05 mov.w ip, #5 + 800232c: f881 c05d strb.w ip, [r1, #93] ; 0x5d + 8002330: 2110 movs r1, #16 + 8002332: 60a1 str r1, [r4, #8] + 8002334: 2108 movs r1, #8 + 8002336: 60a1 str r1, [r4, #8] + 8002338: e7e3 b.n 8002302 + 800233a: 68a1 ldr r1, [r4, #8] + 800233c: 054b lsls r3, r1, #21 + 800233e: d5c2 bpl.n 80022c6 + 8002340: 68e1 ldr r1, [r4, #12] + 8002342: f041 0102 orr.w r1, r1, #2 + 8002346: 60e1 str r1, [r4, #12] + 8002348: 4631 mov r1, r6 + 800234a: f001 fef5 bl 8004138 + 800234e: 2110 movs r1, #16 + 8002350: 60a1 str r1, [r4, #8] + 8002352: fb07 5106 mla r1, r7, r6, r5 + 8002356: 2008 movs r0, #8 + 8002358: f881 005d strb.w r0, [r1, #93] ; 0x5d + 800235c: f44f 6180 mov.w r1, #1024 ; 0x400 + 8002360: e7d7 b.n 8002312 + 8002362: 68a1 ldr r1, [r4, #8] + 8002364: 07c9 lsls r1, r1, #31 + 8002366: d548 bpl.n 80023fa + 8002368: 6929 ldr r1, [r5, #16] + 800236a: b149 cbz r1, 8002380 + 800236c: fb07 5c06 mla ip, r7, r6, r5 + 8002370: 6920 ldr r0, [r4, #16] + 8002372: f8dc 1048 ldr.w r1, [ip, #72] ; 0x48 + 8002376: f3c0 0012 ubfx r0, r0, #0, #19 + 800237a: 1a09 subs r1, r1, r0 + 800237c: f8cc 104c str.w r1, [ip, #76] ; 0x4c + 8002380: fb07 5106 mla r1, r7, r6, r5 + 8002384: 2301 movs r3, #1 + 8002386: 2000 movs r0, #0 + 8002388: f881 305d strb.w r3, [r1, #93] ; 0x5d + 800238c: 6588 str r0, [r1, #88] ; 0x58 + 800238e: 60a3 str r3, [r4, #8] + 8002390: f891 203f ldrb.w r2, [r1, #63] ; 0x3f + 8002394: f012 0ffd tst.w r2, #253 ; 0xfd + 8002398: d114 bne.n 80023c4 + 800239a: 68e3 ldr r3, [r4, #12] + 800239c: 6828 ldr r0, [r5, #0] + 800239e: f043 0302 orr.w r3, r3, #2 + 80023a2: 60e3 str r3, [r4, #12] + 80023a4: 4631 mov r1, r6 + 80023a6: f001 fec7 bl 8004138 + 80023aa: 2310 movs r3, #16 + 80023ac: 60a3 str r3, [r4, #8] + 80023ae: fb07 5606 mla r6, r7, r6, r5 + 80023b2: f896 3050 ldrb.w r3, [r6, #80] ; 0x50 + 80023b6: f083 0301 eor.w r3, r3, #1 + 80023ba: f886 3050 strb.w r3, [r6, #80] ; 0x50 + 80023be: f109 0901 add.w r9, r9, #1 + 80023c2: e70b b.n 80021dc + 80023c4: 2a03 cmp r2, #3 + 80023c6: d10d bne.n 80023e4 + 80023c8: f85b 000a ldr.w r0, [fp, sl] + 80023cc: f040 5000 orr.w r0, r0, #536870912 ; 0x20000000 + 80023d0: f84b 000a str.w r0, [fp, sl] + 80023d4: 461a mov r2, r3 + 80023d6: f881 305c strb.w r3, [r1, #92] ; 0x5c + 80023da: 4631 mov r1, r6 + 80023dc: 4628 mov r0, r5 + 80023de: f002 ff4b bl 8005278 + 80023e2: e7e4 b.n 80023ae + 80023e4: 2a01 cmp r2, #1 + 80023e6: d1e2 bne.n 80023ae + 80023e8: f891 3050 ldrb.w r3, [r1, #80] ; 0x50 + 80023ec: f881 205c strb.w r2, [r1, #92] ; 0x5c + 80023f0: f083 0301 eor.w r3, r3, #1 + 80023f4: f881 3050 strb.w r3, [r1, #80] ; 0x50 + 80023f8: e7ef b.n 80023da + 80023fa: 68a1 ldr r1, [r4, #8] + 80023fc: 078a lsls r2, r1, #30 + 80023fe: d542 bpl.n 8002486 + 8002400: 68e1 ldr r1, [r4, #12] + 8002402: fb07 5006 mla r0, r7, r6, r5 + 8002406: f021 0102 bic.w r1, r1, #2 + 800240a: 60e1 str r1, [r4, #12] + 800240c: f890 105d ldrb.w r1, [r0, #93] ; 0x5d + 8002410: 2901 cmp r1, #1 + 8002412: d102 bne.n 800241a + 8002414: f880 105c strb.w r1, [r0, #92] ; 0x5c + 8002418: e02a b.n 8002470 + 800241a: 2905 cmp r1, #5 + 800241c: d0fa beq.n 8002414 + 800241e: 2906 cmp r1, #6 + 8002420: d001 beq.n 8002426 + 8002422: 2908 cmp r1, #8 + 8002424: d10f bne.n 8002446 + 8002426: fb07 5106 mla r1, r7, r6, r5 + 800242a: 6d88 ldr r0, [r1, #88] ; 0x58 + 800242c: 3001 adds r0, #1 + 800242e: 2803 cmp r0, #3 + 8002430: 6588 str r0, [r1, #88] ; 0x58 + 8002432: bf81 itttt hi + 8002434: 2000 movhi r0, #0 + 8002436: 6588 strhi r0, [r1, #88] ; 0x58 + 8002438: 2004 movhi r0, #4 + 800243a: f881 005c strbhi.w r0, [r1, #92] ; 0x5c + 800243e: bf98 it ls + 8002440: f881 805c strbls.w r8, [r1, #92] ; 0x5c + 8002444: e003 b.n 800244e + 8002446: 2903 cmp r1, #3 + 8002448: d10a bne.n 8002460 + 800244a: f880 805c strb.w r8, [r0, #92] ; 0x5c + 800244e: f85b 100a ldr.w r1, [fp, sl] + 8002452: f021 4180 bic.w r1, r1, #1073741824 ; 0x40000000 + 8002456: f041 4100 orr.w r1, r1, #2147483648 ; 0x80000000 + 800245a: f84b 100a str.w r1, [fp, sl] + 800245e: e007 b.n 8002470 + 8002460: 2907 cmp r1, #7 + 8002462: d105 bne.n 8002470 + 8002464: 6d83 ldr r3, [r0, #88] ; 0x58 + 8002466: 3301 adds r3, #1 + 8002468: 6583 str r3, [r0, #88] ; 0x58 + 800246a: 2304 movs r3, #4 + 800246c: f880 305c strb.w r3, [r0, #92] ; 0x5c + 8002470: fb07 5306 mla r3, r7, r6, r5 + 8002474: f8c4 8008 str.w r8, [r4, #8] + 8002478: f893 205c ldrb.w r2, [r3, #92] ; 0x5c + 800247c: 4631 mov r1, r6 + 800247e: 4628 mov r0, r5 + 8002480: f002 fefa bl 8005278 + 8002484: e79b b.n 80023be + 8002486: 68a1 ldr r1, [r4, #8] + 8002488: 6828 ldr r0, [r5, #0] + 800248a: f011 0180 ands.w r1, r1, #128 ; 0x80 + 800248e: d011 beq.n 80024b4 + 8002490: 68e3 ldr r3, [r4, #12] + 8002492: fb07 5206 mla r2, r7, r6, r5 + 8002496: f043 0302 orr.w r3, r3, #2 + 800249a: 60e3 str r3, [r4, #12] + 800249c: 6d93 ldr r3, [r2, #88] ; 0x58 + 800249e: 3301 adds r3, #1 + 80024a0: 6593 str r3, [r2, #88] ; 0x58 + 80024a2: 2306 movs r3, #6 + 80024a4: f882 305d strb.w r3, [r2, #93] ; 0x5d + 80024a8: 4631 mov r1, r6 + 80024aa: f001 fe45 bl 8004138 + 80024ae: 2380 movs r3, #128 ; 0x80 + 80024b0: 60a3 str r3, [r4, #8] + 80024b2: e784 b.n 80023be + 80024b4: 68a3 ldr r3, [r4, #8] + 80024b6: 06db lsls r3, r3, #27 + 80024b8: d581 bpl.n 80023be + 80024ba: fb07 5206 mla r2, r7, r6, r5 + 80024be: f892 303f ldrb.w r3, [r2, #63] ; 0x3f + 80024c2: 2b03 cmp r3, #3 + 80024c4: d109 bne.n 80024da + 80024c6: 6591 str r1, [r2, #88] ; 0x58 + 80024c8: 68e3 ldr r3, [r4, #12] + 80024ca: f043 0302 orr.w r3, r3, #2 + 80024ce: 60e3 str r3, [r4, #12] + 80024d0: 4631 mov r1, r6 + 80024d2: f001 fe31 bl 8004138 + 80024d6: 2310 movs r3, #16 + 80024d8: e7ea b.n 80024b0 + 80024da: f013 03fd ands.w r3, r3, #253 ; 0xfd + 80024de: d1fa bne.n 80024d6 + 80024e0: 6593 str r3, [r2, #88] ; 0x58 + 80024e2: 692b ldr r3, [r5, #16] + 80024e4: 2b00 cmp r3, #0 + 80024e6: d1f6 bne.n 80024d6 + 80024e8: 2303 movs r3, #3 + 80024ea: f882 305d strb.w r3, [r2, #93] ; 0x5d + 80024ee: e7eb b.n 80024c8 + 80024f0: f011 0c04 ands.w ip, r1, #4 + 80024f4: d008 beq.n 8002508 + 80024f6: 2304 movs r3, #4 + 80024f8: 60a3 str r3, [r4, #8] + 80024fa: 68e3 ldr r3, [r4, #12] + 80024fc: f043 0302 orr.w r3, r3, #2 + 8002500: 60e3 str r3, [r4, #12] + 8002502: e75c b.n 80023be + 8002504: 1ff80000 .word 0x1ff80000 + 8002508: 68a1 ldr r1, [r4, #8] + 800250a: f011 0120 ands.w r1, r1, #32 + 800250e: d014 beq.n 800253a + 8002510: 2320 movs r3, #32 + 8002512: 60a3 str r3, [r4, #8] + 8002514: fb07 5306 mla r3, r7, r6, r5 + 8002518: f893 203d ldrb.w r2, [r3, #61] ; 0x3d + 800251c: 2a01 cmp r2, #1 + 800251e: f47f af4e bne.w 80023be + 8002522: f883 c03d strb.w ip, [r3, #61] ; 0x3d + 8002526: f883 805c strb.w r8, [r3, #92] ; 0x5c + 800252a: 68e3 ldr r3, [r4, #12] + 800252c: f043 0302 orr.w r3, r3, #2 + 8002530: 60e3 str r3, [r4, #12] + 8002532: 4631 mov r1, r6 + 8002534: f001 fe00 bl 8004138 + 8002538: e741 b.n 80023be + 800253a: 68a3 ldr r3, [r4, #8] + 800253c: 065a lsls r2, r3, #25 + 800253e: d511 bpl.n 8002564 + 8002540: fb07 5306 mla r3, r7, r6, r5 + 8002544: 2204 movs r2, #4 + 8002546: f883 205d strb.w r2, [r3, #93] ; 0x5d + 800254a: 2201 movs r2, #1 + 800254c: f883 203d strb.w r2, [r3, #61] ; 0x3d + 8002550: 6599 str r1, [r3, #88] ; 0x58 + 8002552: 68e3 ldr r3, [r4, #12] + 8002554: f043 0302 orr.w r3, r3, #2 + 8002558: 60e3 str r3, [r4, #12] + 800255a: 4631 mov r1, r6 + 800255c: f001 fdec bl 8004138 + 8002560: 2340 movs r3, #64 ; 0x40 + 8002562: e7a5 b.n 80024b0 + 8002564: 68a1 ldr r1, [r4, #8] + 8002566: f411 7100 ands.w r1, r1, #512 ; 0x200 + 800256a: d005 beq.n 8002578 + 800256c: 68e3 ldr r3, [r4, #12] + 800256e: f043 0302 orr.w r3, r3, #2 + 8002572: 60e3 str r3, [r4, #12] + 8002574: 4631 mov r1, r6 + 8002576: e6af b.n 80022d8 + 8002578: 68a3 ldr r3, [r4, #8] + 800257a: 07db lsls r3, r3, #31 + 800257c: d50f bpl.n 800259e + 800257e: 68e2 ldr r2, [r4, #12] + 8002580: fb07 5a06 mla sl, r7, r6, r5 + 8002584: f042 0202 orr.w r2, r2, #2 + 8002588: f8ca 1058 str.w r1, [sl, #88] ; 0x58 + 800258c: 60e2 str r2, [r4, #12] + 800258e: 4631 mov r1, r6 + 8002590: f001 fdd2 bl 8004138 + 8002594: 2201 movs r2, #1 + 8002596: 60a2 str r2, [r4, #8] + 8002598: f88a 205d strb.w r2, [sl, #93] ; 0x5d + 800259c: e70f b.n 80023be + 800259e: 68a1 ldr r1, [r4, #8] + 80025a0: 0709 lsls r1, r1, #28 + 80025a2: d50e bpl.n 80025c2 + 80025a4: 2308 movs r3, #8 + 80025a6: 60a3 str r3, [r4, #8] + 80025a8: 68e3 ldr r3, [r4, #12] + 80025aa: f043 0302 orr.w r3, r3, #2 + 80025ae: 60e3 str r3, [r4, #12] + 80025b0: 4631 mov r1, r6 + 80025b2: f001 fdc1 bl 8004138 + 80025b6: fb07 5606 mla r6, r7, r6, r5 + 80025ba: 2305 movs r3, #5 + 80025bc: f886 305d strb.w r3, [r6, #93] ; 0x5d + 80025c0: e6fd b.n 80023be + 80025c2: 68a1 ldr r1, [r4, #8] + 80025c4: 06ca lsls r2, r1, #27 + 80025c6: d514 bpl.n 80025f2 + 80025c8: fb07 5306 mla r3, r7, r6, r5 + 80025cc: 2200 movs r2, #0 + 80025ce: 659a str r2, [r3, #88] ; 0x58 + 80025d0: 2203 movs r2, #3 + 80025d2: f883 205d strb.w r2, [r3, #93] ; 0x5d + 80025d6: f893 203d ldrb.w r2, [r3, #61] ; 0x3d + 80025da: 2a00 cmp r2, #0 + 80025dc: f47f af74 bne.w 80024c8 + 80025e0: f893 203c ldrb.w r2, [r3, #60] ; 0x3c + 80025e4: 2a00 cmp r2, #0 + 80025e6: f47f af6f bne.w 80024c8 + 80025ea: 2201 movs r2, #1 + 80025ec: f883 203d strb.w r2, [r3, #61] ; 0x3d + 80025f0: e76a b.n 80024c8 + 80025f2: 68a1 ldr r1, [r4, #8] + 80025f4: 060b lsls r3, r1, #24 + 80025f6: d50c bpl.n 8002612 + 80025f8: 68e3 ldr r3, [r4, #12] + 80025fa: f043 0302 orr.w r3, r3, #2 + 80025fe: 60e3 str r3, [r4, #12] + 8002600: 4631 mov r1, r6 + 8002602: fb07 5606 mla r6, r7, r6, r5 + 8002606: f001 fd97 bl 8004138 + 800260a: 2306 movs r3, #6 + 800260c: f886 305d strb.w r3, [r6, #93] ; 0x5d + 8002610: e74d b.n 80024ae + 8002612: 68a1 ldr r1, [r4, #8] + 8002614: 0549 lsls r1, r1, #21 + 8002616: d50f bpl.n 8002638 + 8002618: 68e3 ldr r3, [r4, #12] + 800261a: f043 0302 orr.w r3, r3, #2 + 800261e: 60e3 str r3, [r4, #12] + 8002620: 4631 mov r1, r6 + 8002622: f001 fd89 bl 8004138 + 8002626: 2310 movs r3, #16 + 8002628: 60a3 str r3, [r4, #8] + 800262a: f44f 6380 mov.w r3, #1024 ; 0x400 + 800262e: 60a3 str r3, [r4, #8] + 8002630: fb07 5606 mla r6, r7, r6, r5 + 8002634: 2308 movs r3, #8 + 8002636: e7c1 b.n 80025bc + 8002638: 68a1 ldr r1, [r4, #8] + 800263a: 078a lsls r2, r1, #30 + 800263c: f57f aebf bpl.w 80023be + 8002640: 68e1 ldr r1, [r4, #12] + 8002642: fb07 5006 mla r0, r7, r6, r5 + 8002646: f021 0102 bic.w r1, r1, #2 + 800264a: 60e1 str r1, [r4, #12] + 800264c: f890 105d ldrb.w r1, [r0, #93] ; 0x5d + 8002650: 2901 cmp r1, #1 + 8002652: d10e bne.n 8002672 + 8002654: f890 303f ldrb.w r3, [r0, #63] ; 0x3f + 8002658: f880 105c strb.w r1, [r0, #92] ; 0x5c + 800265c: 3b02 subs r3, #2 + 800265e: 2b01 cmp r3, #1 + 8002660: f63f af06 bhi.w 8002470 + 8002664: f890 3051 ldrb.w r3, [r0, #81] ; 0x51 + 8002668: f083 0301 eor.w r3, r3, #1 + 800266c: f880 3051 strb.w r3, [r0, #81] ; 0x51 + 8002670: e6fe b.n 8002470 + 8002672: 2903 cmp r1, #3 + 8002674: d102 bne.n 800267c + 8002676: f880 805c strb.w r8, [r0, #92] ; 0x5c + 800267a: e6f9 b.n 8002470 + 800267c: 2904 cmp r1, #4 + 800267e: d0fa beq.n 8002676 + 8002680: 2905 cmp r1, #5 + 8002682: f43f aec7 beq.w 8002414 + 8002686: 2906 cmp r1, #6 + 8002688: f43f aecd beq.w 8002426 + 800268c: 2908 cmp r1, #8 + 800268e: f47f aeef bne.w 8002470 + 8002692: e6c8 b.n 8002426 + +08002694 : + 8002694: b538 push {r3, r4, r5, lr} + 8002696: f890 32b8 ldrb.w r3, [r0, #696] ; 0x2b8 + 800269a: 2b01 cmp r3, #1 + 800269c: 4604 mov r4, r0 + 800269e: d00d beq.n 80026bc + 80026a0: 2501 movs r5, #1 + 80026a2: f880 52b8 strb.w r5, [r0, #696] ; 0x2b8 + 80026a6: 6800 ldr r0, [r0, #0] + 80026a8: f001 fb74 bl 8003d94 + 80026ac: 4629 mov r1, r5 + 80026ae: 6820 ldr r0, [r4, #0] + 80026b0: f001 fc1a bl 8003ee8 + 80026b4: 2000 movs r0, #0 + 80026b6: f884 02b8 strb.w r0, [r4, #696] ; 0x2b8 + 80026ba: bd38 pop {r3, r4, r5, pc} + 80026bc: 2002 movs r0, #2 + 80026be: e7fc b.n 80026ba + +080026c0 : + 80026c0: f890 32b8 ldrb.w r3, [r0, #696] ; 0x2b8 + 80026c4: 2b01 cmp r3, #1 + 80026c6: b510 push {r4, lr} + 80026c8: 4604 mov r4, r0 + 80026ca: d009 beq.n 80026e0 + 80026cc: 2301 movs r3, #1 + 80026ce: f880 32b8 strb.w r3, [r0, #696] ; 0x2b8 + 80026d2: 6800 ldr r0, [r0, #0] + 80026d4: f001 fe40 bl 8004358 + 80026d8: 2000 movs r0, #0 + 80026da: f884 02b8 strb.w r0, [r4, #696] ; 0x2b8 + 80026de: bd10 pop {r4, pc} + 80026e0: 2002 movs r0, #2 + 80026e2: e7fc b.n 80026de + +080026e4 : + 80026e4: 6800 ldr r0, [r0, #0] + 80026e6: f001 bbe1 b.w 8003eac + +080026ea : + 80026ea: 2328 movs r3, #40 ; 0x28 + 80026ec: fb03 0101 mla r1, r3, r1, r0 + 80026f0: f891 005c ldrb.w r0, [r1, #92] ; 0x5c + 80026f4: 4770 bx lr + +080026f6 : + 80026f6: 2328 movs r3, #40 ; 0x28 + 80026f8: fb03 0101 mla r1, r3, r1, r0 + 80026fc: 6cc8 ldr r0, [r1, #76] ; 0x4c + 80026fe: 4770 bx lr + +08002700 : + 8002700: 6800 ldr r0, [r0, #0] + 8002702: f001 bc8c b.w 800401e + +08002706 : + 8002706: 6800 ldr r0, [r0, #0] + 8002708: f001 bc7e b.w 8004008 + +0800270c : + 800270c: 6801 ldr r1, [r0, #0] + 800270e: 694b ldr r3, [r1, #20] + 8002710: f413 6380 ands.w r3, r3, #1024 ; 0x400 + 8002714: f04f 0200 mov.w r2, #0 + 8002718: d010 beq.n 800273c + 800271a: f46f 6380 mvn.w r3, #1024 ; 0x400 + 800271e: 614b str r3, [r1, #20] + 8002720: 2320 movs r3, #32 + 8002722: 6302 str r2, [r0, #48] ; 0x30 + 8002724: f880 303d strb.w r3, [r0, #61] ; 0x3d + 8002728: f880 203e strb.w r2, [r0, #62] ; 0x3e + 800272c: 6c03 ldr r3, [r0, #64] ; 0x40 + 800272e: f880 203c strb.w r2, [r0, #60] ; 0x3c + 8002732: f043 0304 orr.w r3, r3, #4 + 8002736: 6403 str r3, [r0, #64] ; 0x40 + 8002738: 2001 movs r0, #1 + 800273a: 4770 bx lr + 800273c: 4618 mov r0, r3 + 800273e: 4770 bx lr + +08002740 : + 8002740: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 8002744: 4604 mov r4, r0 + 8002746: 4616 mov r6, r2 + 8002748: 4698 mov r8, r3 + 800274a: b28f uxth r7, r1 + 800274c: 6825 ldr r5, [r4, #0] + 800274e: 6968 ldr r0, [r5, #20] + 8002750: ea37 0000 bics.w r0, r7, r0 + 8002754: d017 beq.n 8002786 + 8002756: 696b ldr r3, [r5, #20] + 8002758: 055a lsls r2, r3, #21 + 800275a: d516 bpl.n 800278a + 800275c: 682b ldr r3, [r5, #0] + 800275e: f443 7300 orr.w r3, r3, #512 ; 0x200 + 8002762: 602b str r3, [r5, #0] + 8002764: f46f 6380 mvn.w r3, #1024 ; 0x400 + 8002768: 616b str r3, [r5, #20] + 800276a: 2220 movs r2, #32 + 800276c: 2300 movs r3, #0 + 800276e: 6323 str r3, [r4, #48] ; 0x30 + 8002770: f884 203d strb.w r2, [r4, #61] ; 0x3d + 8002774: f884 303e strb.w r3, [r4, #62] ; 0x3e + 8002778: 6c22 ldr r2, [r4, #64] ; 0x40 + 800277a: f042 0204 orr.w r2, r2, #4 + 800277e: 6422 str r2, [r4, #64] ; 0x40 + 8002780: f884 303c strb.w r3, [r4, #60] ; 0x3c + 8002784: 2001 movs r0, #1 + 8002786: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 800278a: 1c73 adds r3, r6, #1 + 800278c: d0df beq.n 800274e + 800278e: f7ff fa2d bl 8001bec + 8002792: eba0 0008 sub.w r0, r0, r8 + 8002796: 42b0 cmp r0, r6 + 8002798: d801 bhi.n 800279e + 800279a: 2e00 cmp r6, #0 + 800279c: d1d6 bne.n 800274c + 800279e: 2300 movs r3, #0 + 80027a0: 2220 movs r2, #32 + 80027a2: 6323 str r3, [r4, #48] ; 0x30 + 80027a4: f884 203d strb.w r2, [r4, #61] ; 0x3d + 80027a8: f884 303e strb.w r3, [r4, #62] ; 0x3e + 80027ac: 6c22 ldr r2, [r4, #64] ; 0x40 + 80027ae: f042 0220 orr.w r2, r2, #32 + 80027b2: e7e4 b.n 800277e + +080027b4 : + 80027b4: b570 push {r4, r5, r6, lr} + 80027b6: 4604 mov r4, r0 + 80027b8: 460d mov r5, r1 + 80027ba: 4616 mov r6, r2 + 80027bc: 6823 ldr r3, [r4, #0] + 80027be: 695b ldr r3, [r3, #20] + 80027c0: 075b lsls r3, r3, #29 + 80027c2: d501 bpl.n 80027c8 + 80027c4: 2000 movs r0, #0 + 80027c6: bd70 pop {r4, r5, r6, pc} + 80027c8: 4620 mov r0, r4 + 80027ca: f7ff ff9f bl 800270c + 80027ce: b9a8 cbnz r0, 80027fc + 80027d0: 1c6a adds r2, r5, #1 + 80027d2: d0f3 beq.n 80027bc + 80027d4: f7ff fa0a bl 8001bec + 80027d8: 1b80 subs r0, r0, r6 + 80027da: 42a8 cmp r0, r5 + 80027dc: d801 bhi.n 80027e2 + 80027de: 2d00 cmp r5, #0 + 80027e0: d1ec bne.n 80027bc + 80027e2: 2300 movs r3, #0 + 80027e4: 2220 movs r2, #32 + 80027e6: 6323 str r3, [r4, #48] ; 0x30 + 80027e8: f884 203d strb.w r2, [r4, #61] ; 0x3d + 80027ec: f884 303e strb.w r3, [r4, #62] ; 0x3e + 80027f0: 6c22 ldr r2, [r4, #64] ; 0x40 + 80027f2: f884 303c strb.w r3, [r4, #60] ; 0x3c + 80027f6: f042 0220 orr.w r2, r2, #32 + 80027fa: 6422 str r2, [r4, #64] ; 0x40 + 80027fc: 2001 movs r0, #1 + 80027fe: e7e2 b.n 80027c6 + +08002800 : + 8002800: b570 push {r4, r5, r6, lr} + 8002802: 4604 mov r4, r0 + 8002804: 460d mov r5, r1 + 8002806: 4616 mov r6, r2 + 8002808: 6820 ldr r0, [r4, #0] + 800280a: 6943 ldr r3, [r0, #20] + 800280c: f013 0340 ands.w r3, r3, #64 ; 0x40 + 8002810: d001 beq.n 8002816 + 8002812: 2000 movs r0, #0 + 8002814: e010 b.n 8002838 + 8002816: 6942 ldr r2, [r0, #20] + 8002818: 06d2 lsls r2, r2, #27 + 800281a: d50e bpl.n 800283a + 800281c: f06f 0210 mvn.w r2, #16 + 8002820: 6142 str r2, [r0, #20] + 8002822: 2220 movs r2, #32 + 8002824: 6323 str r3, [r4, #48] ; 0x30 + 8002826: f884 203d strb.w r2, [r4, #61] ; 0x3d + 800282a: f884 303e strb.w r3, [r4, #62] ; 0x3e + 800282e: 6c22 ldr r2, [r4, #64] ; 0x40 + 8002830: 6422 str r2, [r4, #64] ; 0x40 + 8002832: f884 303c strb.w r3, [r4, #60] ; 0x3c + 8002836: 2001 movs r0, #1 + 8002838: bd70 pop {r4, r5, r6, pc} + 800283a: f7ff f9d7 bl 8001bec + 800283e: 1b80 subs r0, r0, r6 + 8002840: 42a8 cmp r0, r5 + 8002842: d801 bhi.n 8002848 + 8002844: 2d00 cmp r5, #0 + 8002846: d1df bne.n 8002808 + 8002848: 2300 movs r3, #0 + 800284a: 2220 movs r2, #32 + 800284c: 6323 str r3, [r4, #48] ; 0x30 + 800284e: f884 203d strb.w r2, [r4, #61] ; 0x3d + 8002852: f884 303e strb.w r3, [r4, #62] ; 0x3e + 8002856: 6c22 ldr r2, [r4, #64] ; 0x40 + 8002858: f042 0220 orr.w r2, r2, #32 + 800285c: e7e8 b.n 8002830 + +0800285e : + 800285e: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} + 8002862: 9e08 ldr r6, [sp, #32] + 8002864: 4604 mov r4, r0 + 8002866: 4690 mov r8, r2 + 8002868: 461f mov r7, r3 + 800286a: ea4f 4911 mov.w r9, r1, lsr #16 + 800286e: b28d uxth r5, r1 + 8002870: 6821 ldr r1, [r4, #0] + 8002872: f1b9 0f01 cmp.w r9, #1 + 8002876: bf0c ite eq + 8002878: 694b ldreq r3, [r1, #20] + 800287a: 698b ldrne r3, [r1, #24] + 800287c: ea35 0303 bics.w r3, r5, r3 + 8002880: bf0c ite eq + 8002882: 2301 moveq r3, #1 + 8002884: 2300 movne r3, #0 + 8002886: 4598 cmp r8, r3 + 8002888: d001 beq.n 800288e + 800288a: 2000 movs r0, #0 + 800288c: e016 b.n 80028bc + 800288e: 1c7b adds r3, r7, #1 + 8002890: d0ef beq.n 8002872 + 8002892: f7ff f9ab bl 8001bec + 8002896: 1b80 subs r0, r0, r6 + 8002898: 42b8 cmp r0, r7 + 800289a: d801 bhi.n 80028a0 + 800289c: 2f00 cmp r7, #0 + 800289e: d1e7 bne.n 8002870 + 80028a0: 2300 movs r3, #0 + 80028a2: 2220 movs r2, #32 + 80028a4: 6323 str r3, [r4, #48] ; 0x30 + 80028a6: f884 203d strb.w r2, [r4, #61] ; 0x3d + 80028aa: f884 303e strb.w r3, [r4, #62] ; 0x3e + 80028ae: 6c22 ldr r2, [r4, #64] ; 0x40 + 80028b0: f884 303c strb.w r3, [r4, #60] ; 0x3c + 80028b4: f042 0220 orr.w r2, r2, #32 + 80028b8: 6422 str r2, [r4, #64] ; 0x40 + 80028ba: 2001 movs r0, #1 + 80028bc: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} + +080028c0 : + 80028c0: b570 push {r4, r5, r6, lr} + 80028c2: 4604 mov r4, r0 + 80028c4: 460d mov r5, r1 + 80028c6: 4616 mov r6, r2 + 80028c8: 6823 ldr r3, [r4, #0] + 80028ca: 695b ldr r3, [r3, #20] + 80028cc: 061b lsls r3, r3, #24 + 80028ce: d501 bpl.n 80028d4 + 80028d0: 2000 movs r0, #0 + 80028d2: bd70 pop {r4, r5, r6, pc} + 80028d4: 4620 mov r0, r4 + 80028d6: f7ff ff19 bl 800270c + 80028da: b9a8 cbnz r0, 8002908 + 80028dc: 1c6a adds r2, r5, #1 + 80028de: d0f3 beq.n 80028c8 + 80028e0: f7ff f984 bl 8001bec + 80028e4: 1b80 subs r0, r0, r6 + 80028e6: 42a8 cmp r0, r5 + 80028e8: d801 bhi.n 80028ee + 80028ea: 2d00 cmp r5, #0 + 80028ec: d1ec bne.n 80028c8 + 80028ee: 2300 movs r3, #0 + 80028f0: 2220 movs r2, #32 + 80028f2: 6323 str r3, [r4, #48] ; 0x30 + 80028f4: f884 203d strb.w r2, [r4, #61] ; 0x3d + 80028f8: f884 303e strb.w r3, [r4, #62] ; 0x3e + 80028fc: 6c22 ldr r2, [r4, #64] ; 0x40 + 80028fe: f884 303c strb.w r3, [r4, #60] ; 0x3c + 8002902: f042 0220 orr.w r2, r2, #32 + 8002906: 6422 str r2, [r4, #64] ; 0x40 + 8002908: 2001 movs r0, #1 + 800290a: e7e2 b.n 80028d2 + +0800290c : + 800290c: b570 push {r4, r5, r6, lr} + 800290e: 4604 mov r4, r0 + 8002910: b908 cbnz r0, 8002916 + 8002912: 2001 movs r0, #1 + 8002914: bd70 pop {r4, r5, r6, pc} + 8002916: f890 303d ldrb.w r3, [r0, #61] ; 0x3d + 800291a: f003 02ff and.w r2, r3, #255 ; 0xff + 800291e: b91b cbnz r3, 8002928 + 8002920: f880 203c strb.w r2, [r0, #60] ; 0x3c + 8002924: f7fe fdc2 bl 80014ac + 8002928: 2324 movs r3, #36 ; 0x24 + 800292a: f884 303d strb.w r3, [r4, #61] ; 0x3d + 800292e: 6823 ldr r3, [r4, #0] + 8002930: 681a ldr r2, [r3, #0] + 8002932: f022 0201 bic.w r2, r2, #1 + 8002936: 601a str r2, [r3, #0] + 8002938: 681a ldr r2, [r3, #0] + 800293a: f442 4200 orr.w r2, r2, #32768 ; 0x8000 + 800293e: 601a str r2, [r3, #0] + 8002940: 681a ldr r2, [r3, #0] + 8002942: f422 4200 bic.w r2, r2, #32768 ; 0x8000 + 8002946: 601a str r2, [r3, #0] + 8002948: f000 ff80 bl 800384c + 800294c: 6863 ldr r3, [r4, #4] + 800294e: 4a41 ldr r2, [pc, #260] ; (8002a54 ) + 8002950: 4293 cmp r3, r2 + 8002952: d84d bhi.n 80029f0 + 8002954: 4a40 ldr r2, [pc, #256] ; (8002a58 ) + 8002956: 4290 cmp r0, r2 + 8002958: d9db bls.n 8002912 + 800295a: 6822 ldr r2, [r4, #0] + 800295c: 493f ldr r1, [pc, #252] ; (8002a5c ) + 800295e: 6855 ldr r5, [r2, #4] + 8002960: fbb0 f1f1 udiv r1, r0, r1 + 8002964: f025 053f bic.w r5, r5, #63 ; 0x3f + 8002968: 430d orrs r5, r1 + 800296a: 6055 str r5, [r2, #4] + 800296c: 6a15 ldr r5, [r2, #32] + 800296e: f025 053f bic.w r5, r5, #63 ; 0x3f + 8002972: 3101 adds r1, #1 + 8002974: 4329 orrs r1, r5 + 8002976: 6211 str r1, [r2, #32] + 8002978: 69d1 ldr r1, [r2, #28] + 800297a: 4d36 ldr r5, [pc, #216] ; (8002a54 ) + 800297c: f421 414f bic.w r1, r1, #52992 ; 0xcf00 + 8002980: 42ab cmp r3, r5 + 8002982: f021 01ff bic.w r1, r1, #255 ; 0xff + 8002986: f100 30ff add.w r0, r0, #4294967295 + 800298a: d848 bhi.n 8002a1e + 800298c: 005b lsls r3, r3, #1 + 800298e: fbb0 f0f3 udiv r0, r0, r3 + 8002992: 1c43 adds r3, r0, #1 + 8002994: f3c3 030b ubfx r3, r3, #0, #12 + 8002998: 2b04 cmp r3, #4 + 800299a: bf38 it cc + 800299c: 2304 movcc r3, #4 + 800299e: 430b orrs r3, r1 + 80029a0: 61d3 str r3, [r2, #28] + 80029a2: e9d4 3007 ldrd r3, r0, [r4, #28] + 80029a6: 6811 ldr r1, [r2, #0] + 80029a8: 4303 orrs r3, r0 + 80029aa: f021 01c0 bic.w r1, r1, #192 ; 0xc0 + 80029ae: 430b orrs r3, r1 + 80029b0: 6013 str r3, [r2, #0] + 80029b2: 6891 ldr r1, [r2, #8] + 80029b4: e9d4 0303 ldrd r0, r3, [r4, #12] + 80029b8: f421 4103 bic.w r1, r1, #33536 ; 0x8300 + 80029bc: 4303 orrs r3, r0 + 80029be: f021 01ff bic.w r1, r1, #255 ; 0xff + 80029c2: 430b orrs r3, r1 + 80029c4: 6093 str r3, [r2, #8] + 80029c6: e9d4 3005 ldrd r3, r0, [r4, #20] + 80029ca: 68d1 ldr r1, [r2, #12] + 80029cc: 4303 orrs r3, r0 + 80029ce: f021 01ff bic.w r1, r1, #255 ; 0xff + 80029d2: 430b orrs r3, r1 + 80029d4: 60d3 str r3, [r2, #12] + 80029d6: 6813 ldr r3, [r2, #0] + 80029d8: f043 0301 orr.w r3, r3, #1 + 80029dc: 6013 str r3, [r2, #0] + 80029de: 2000 movs r0, #0 + 80029e0: 2320 movs r3, #32 + 80029e2: 6420 str r0, [r4, #64] ; 0x40 + 80029e4: f884 303d strb.w r3, [r4, #61] ; 0x3d + 80029e8: 6320 str r0, [r4, #48] ; 0x30 + 80029ea: f884 003e strb.w r0, [r4, #62] ; 0x3e + 80029ee: e791 b.n 8002914 + 80029f0: 4a1b ldr r2, [pc, #108] ; (8002a60 ) + 80029f2: 4290 cmp r0, r2 + 80029f4: d98d bls.n 8002912 + 80029f6: 6822 ldr r2, [r4, #0] + 80029f8: 4e18 ldr r6, [pc, #96] ; (8002a5c ) + 80029fa: 6855 ldr r5, [r2, #4] + 80029fc: fbb0 f6f6 udiv r6, r0, r6 + 8002a00: f025 053f bic.w r5, r5, #63 ; 0x3f + 8002a04: 4335 orrs r5, r6 + 8002a06: 6055 str r5, [r2, #4] + 8002a08: 6a15 ldr r5, [r2, #32] + 8002a0a: f44f 7196 mov.w r1, #300 ; 0x12c + 8002a0e: 4371 muls r1, r6 + 8002a10: f025 053f bic.w r5, r5, #63 ; 0x3f + 8002a14: f44f 767a mov.w r6, #1000 ; 0x3e8 + 8002a18: fbb1 f1f6 udiv r1, r1, r6 + 8002a1c: e7a9 b.n 8002972 + 8002a1e: 68a5 ldr r5, [r4, #8] + 8002a20: b955 cbnz r5, 8002a38 + 8002a22: eb03 0343 add.w r3, r3, r3, lsl #1 + 8002a26: fbb0 f0f3 udiv r0, r0, r3 + 8002a2a: 1c43 adds r3, r0, #1 + 8002a2c: f3c3 030b ubfx r3, r3, #0, #12 + 8002a30: b16b cbz r3, 8002a4e + 8002a32: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 8002a36: e7b2 b.n 800299e + 8002a38: 2519 movs r5, #25 + 8002a3a: 436b muls r3, r5 + 8002a3c: fbb0 f0f3 udiv r0, r0, r3 + 8002a40: 1c43 adds r3, r0, #1 + 8002a42: f3c3 030b ubfx r3, r3, #0, #12 + 8002a46: b113 cbz r3, 8002a4e + 8002a48: f443 4340 orr.w r3, r3, #49152 ; 0xc000 + 8002a4c: e7a7 b.n 800299e + 8002a4e: 2301 movs r3, #1 + 8002a50: e7a5 b.n 800299e + 8002a52: bf00 nop + 8002a54: 000186a0 .word 0x000186a0 + 8002a58: 001e847f .word 0x001e847f + 8002a5c: 000f4240 .word 0x000f4240 + 8002a60: 003d08ff .word 0x003d08ff + +08002a64 : + 8002a64: e92d 41ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, lr} + 8002a68: 4604 mov r4, r0 + 8002a6a: 461f mov r7, r3 + 8002a6c: 460d mov r5, r1 + 8002a6e: 4690 mov r8, r2 + 8002a70: f7ff f8bc bl 8001bec + 8002a74: f894 303d ldrb.w r3, [r4, #61] ; 0x3d + 8002a78: 2b20 cmp r3, #32 + 8002a7a: 4606 mov r6, r0 + 8002a7c: d004 beq.n 8002a88 + 8002a7e: 2502 movs r5, #2 + 8002a80: 4628 mov r0, r5 + 8002a82: b004 add sp, #16 + 8002a84: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 8002a88: 9000 str r0, [sp, #0] + 8002a8a: 2319 movs r3, #25 + 8002a8c: 2201 movs r2, #1 + 8002a8e: 495b ldr r1, [pc, #364] ; (8002bfc ) + 8002a90: 4620 mov r0, r4 + 8002a92: f7ff fee4 bl 800285e + 8002a96: 2800 cmp r0, #0 + 8002a98: d1f1 bne.n 8002a7e + 8002a9a: f894 303c ldrb.w r3, [r4, #60] ; 0x3c + 8002a9e: 2b01 cmp r3, #1 + 8002aa0: d0ed beq.n 8002a7e + 8002aa2: 2301 movs r3, #1 + 8002aa4: f884 303c strb.w r3, [r4, #60] ; 0x3c + 8002aa8: 6823 ldr r3, [r4, #0] + 8002aaa: 681a ldr r2, [r3, #0] + 8002aac: 07d2 lsls r2, r2, #31 + 8002aae: bf5e ittt pl + 8002ab0: 681a ldrpl r2, [r3, #0] + 8002ab2: f042 0201 orrpl.w r2, r2, #1 + 8002ab6: 601a strpl r2, [r3, #0] + 8002ab8: 681a ldr r2, [r3, #0] + 8002aba: f422 6200 bic.w r2, r2, #2048 ; 0x800 + 8002abe: 601a str r2, [r3, #0] + 8002ac0: 2221 movs r2, #33 ; 0x21 + 8002ac2: f884 203d strb.w r2, [r4, #61] ; 0x3d + 8002ac6: 2210 movs r2, #16 + 8002ac8: f884 203e strb.w r2, [r4, #62] ; 0x3e + 8002acc: 2200 movs r2, #0 + 8002ace: 6422 str r2, [r4, #64] ; 0x40 + 8002ad0: 8567 strh r7, [r4, #42] ; 0x2a + 8002ad2: 8d62 ldrh r2, [r4, #42] ; 0x2a + 8002ad4: 8522 strh r2, [r4, #40] ; 0x28 + 8002ad6: 4a4a ldr r2, [pc, #296] ; (8002c00 ) + 8002ad8: 62e2 str r2, [r4, #44] ; 0x2c + 8002ada: 6ae2 ldr r2, [r4, #44] ; 0x2c + 8002adc: f8c4 8024 str.w r8, [r4, #36] ; 0x24 + 8002ae0: 2a08 cmp r2, #8 + 8002ae2: d004 beq.n 8002aee + 8002ae4: 2a01 cmp r2, #1 + 8002ae6: d002 beq.n 8002aee + 8002ae8: f512 3f80 cmn.w r2, #65536 ; 0x10000 + 8002aec: d104 bne.n 8002af8 + 8002aee: 681a ldr r2, [r3, #0] + 8002af0: f442 7280 orr.w r2, r2, #256 ; 0x100 + 8002af4: 601a str r2, [r3, #0] + 8002af6: e002 b.n 8002afe + 8002af8: 6b22 ldr r2, [r4, #48] ; 0x30 + 8002afa: 2a12 cmp r2, #18 + 8002afc: d0f7 beq.n 8002aee + 8002afe: 2200 movs r2, #0 + 8002b00: 9600 str r6, [sp, #0] + 8002b02: 9b0a ldr r3, [sp, #40] ; 0x28 + 8002b04: f04f 1101 mov.w r1, #65537 ; 0x10001 + 8002b08: 4620 mov r0, r4 + 8002b0a: f7ff fea8 bl 800285e + 8002b0e: 6822 ldr r2, [r4, #0] + 8002b10: b138 cbz r0, 8002b22 + 8002b12: 6813 ldr r3, [r2, #0] + 8002b14: 05db lsls r3, r3, #23 + 8002b16: bf44 itt mi + 8002b18: f44f 7300 movmi.w r3, #512 ; 0x200 + 8002b1c: 6423 strmi r3, [r4, #64] ; 0x40 + 8002b1e: 2501 movs r5, #1 + 8002b20: e7ae b.n 8002a80 + 8002b22: 6923 ldr r3, [r4, #16] + 8002b24: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 + 8002b28: d121 bne.n 8002b6e + 8002b2a: f005 05fe and.w r5, r5, #254 ; 0xfe + 8002b2e: 6115 str r5, [r2, #16] + 8002b30: 4633 mov r3, r6 + 8002b32: 9a0a ldr r2, [sp, #40] ; 0x28 + 8002b34: 4933 ldr r1, [pc, #204] ; (8002c04 ) + 8002b36: 4620 mov r0, r4 + 8002b38: f7ff fe02 bl 8002740 + 8002b3c: 4605 mov r5, r0 + 8002b3e: 2800 cmp r0, #0 + 8002b40: d1ed bne.n 8002b1e + 8002b42: 6823 ldr r3, [r4, #0] + 8002b44: 9003 str r0, [sp, #12] + 8002b46: 695a ldr r2, [r3, #20] + 8002b48: 9203 str r2, [sp, #12] + 8002b4a: 699b ldr r3, [r3, #24] + 8002b4c: 9303 str r3, [sp, #12] + 8002b4e: 9b03 ldr r3, [sp, #12] + 8002b50: 8d23 ldrh r3, [r4, #40] ; 0x28 + 8002b52: b9f3 cbnz r3, 8002b92 + 8002b54: 6821 ldr r1, [r4, #0] + 8002b56: 680a ldr r2, [r1, #0] + 8002b58: f442 7200 orr.w r2, r2, #512 ; 0x200 + 8002b5c: 600a str r2, [r1, #0] + 8002b5e: 2220 movs r2, #32 + 8002b60: f884 203d strb.w r2, [r4, #61] ; 0x3d + 8002b64: f884 303c strb.w r3, [r4, #60] ; 0x3c + 8002b68: f884 303e strb.w r3, [r4, #62] ; 0x3e + 8002b6c: e788 b.n 8002a80 + 8002b6e: 11eb asrs r3, r5, #7 + 8002b70: f003 0306 and.w r3, r3, #6 + 8002b74: f043 03f0 orr.w r3, r3, #240 ; 0xf0 + 8002b78: 6113 str r3, [r2, #16] + 8002b7a: 4923 ldr r1, [pc, #140] ; (8002c08 ) + 8002b7c: 9a0a ldr r2, [sp, #40] ; 0x28 + 8002b7e: 4633 mov r3, r6 + 8002b80: 4620 mov r0, r4 + 8002b82: f7ff fddd bl 8002740 + 8002b86: 2800 cmp r0, #0 + 8002b88: d1c9 bne.n 8002b1e + 8002b8a: 6823 ldr r3, [r4, #0] + 8002b8c: b2ed uxtb r5, r5 + 8002b8e: 611d str r5, [r3, #16] + 8002b90: e7ce b.n 8002b30 + 8002b92: 4632 mov r2, r6 + 8002b94: 990a ldr r1, [sp, #40] ; 0x28 + 8002b96: 4620 mov r0, r4 + 8002b98: f7ff fe92 bl 80028c0 + 8002b9c: b140 cbz r0, 8002bb0 + 8002b9e: 6c23 ldr r3, [r4, #64] ; 0x40 + 8002ba0: 2b04 cmp r3, #4 + 8002ba2: d1bc bne.n 8002b1e + 8002ba4: 6822 ldr r2, [r4, #0] + 8002ba6: 6813 ldr r3, [r2, #0] + 8002ba8: f443 7300 orr.w r3, r3, #512 ; 0x200 + 8002bac: 6013 str r3, [r2, #0] + 8002bae: e7b6 b.n 8002b1e + 8002bb0: 6a63 ldr r3, [r4, #36] ; 0x24 + 8002bb2: 6820 ldr r0, [r4, #0] + 8002bb4: 461a mov r2, r3 + 8002bb6: f812 1b01 ldrb.w r1, [r2], #1 + 8002bba: 6101 str r1, [r0, #16] + 8002bbc: 6262 str r2, [r4, #36] ; 0x24 + 8002bbe: 8d62 ldrh r2, [r4, #42] ; 0x2a + 8002bc0: 3a01 subs r2, #1 + 8002bc2: b292 uxth r2, r2 + 8002bc4: 8562 strh r2, [r4, #42] ; 0x2a + 8002bc6: 8d22 ldrh r2, [r4, #40] ; 0x28 + 8002bc8: 6947 ldr r7, [r0, #20] + 8002bca: 1e51 subs r1, r2, #1 + 8002bcc: b289 uxth r1, r1 + 8002bce: 077f lsls r7, r7, #29 + 8002bd0: 8521 strh r1, [r4, #40] ; 0x28 + 8002bd2: d50a bpl.n 8002bea + 8002bd4: b149 cbz r1, 8002bea + 8002bd6: 7859 ldrb r1, [r3, #1] + 8002bd8: 6101 str r1, [r0, #16] + 8002bda: 3302 adds r3, #2 + 8002bdc: 6263 str r3, [r4, #36] ; 0x24 + 8002bde: 8d63 ldrh r3, [r4, #42] ; 0x2a + 8002be0: 3b01 subs r3, #1 + 8002be2: b29b uxth r3, r3 + 8002be4: 3a02 subs r2, #2 + 8002be6: 8563 strh r3, [r4, #42] ; 0x2a + 8002be8: 8522 strh r2, [r4, #40] ; 0x28 + 8002bea: 4632 mov r2, r6 + 8002bec: 990a ldr r1, [sp, #40] ; 0x28 + 8002bee: 4620 mov r0, r4 + 8002bf0: f7ff fde0 bl 80027b4 + 8002bf4: 2800 cmp r0, #0 + 8002bf6: d0ab beq.n 8002b50 + 8002bf8: e7d1 b.n 8002b9e + 8002bfa: bf00 nop + 8002bfc: 00100002 .word 0x00100002 + 8002c00: ffff0000 .word 0xffff0000 + 8002c04: 00010002 .word 0x00010002 + 8002c08: 00010008 .word 0x00010008 + +08002c0c : + 8002c0c: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} + 8002c10: 4604 mov r4, r0 + 8002c12: b089 sub sp, #36 ; 0x24 + 8002c14: 4698 mov r8, r3 + 8002c16: 460e mov r6, r1 + 8002c18: 4691 mov r9, r2 + 8002c1a: 9f10 ldr r7, [sp, #64] ; 0x40 + 8002c1c: f7fe ffe6 bl 8001bec + 8002c20: f894 303d ldrb.w r3, [r4, #61] ; 0x3d + 8002c24: 2b20 cmp r3, #32 + 8002c26: 4605 mov r5, r0 + 8002c28: d004 beq.n 8002c34 + 8002c2a: 2602 movs r6, #2 + 8002c2c: 4630 mov r0, r6 + 8002c2e: b009 add sp, #36 ; 0x24 + 8002c30: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} + 8002c34: 9000 str r0, [sp, #0] + 8002c36: 2319 movs r3, #25 + 8002c38: 2201 movs r2, #1 + 8002c3a: 499b ldr r1, [pc, #620] ; (8002ea8 ) + 8002c3c: 4620 mov r0, r4 + 8002c3e: f7ff fe0e bl 800285e + 8002c42: 2800 cmp r0, #0 + 8002c44: d1f1 bne.n 8002c2a + 8002c46: f894 303c ldrb.w r3, [r4, #60] ; 0x3c + 8002c4a: 2b01 cmp r3, #1 + 8002c4c: d0ed beq.n 8002c2a + 8002c4e: 2301 movs r3, #1 + 8002c50: f884 303c strb.w r3, [r4, #60] ; 0x3c + 8002c54: 6823 ldr r3, [r4, #0] + 8002c56: 681a ldr r2, [r3, #0] + 8002c58: 07d2 lsls r2, r2, #31 + 8002c5a: bf5e ittt pl + 8002c5c: 681a ldrpl r2, [r3, #0] + 8002c5e: f042 0201 orrpl.w r2, r2, #1 + 8002c62: 601a strpl r2, [r3, #0] + 8002c64: 681a ldr r2, [r3, #0] + 8002c66: f422 6200 bic.w r2, r2, #2048 ; 0x800 + 8002c6a: 601a str r2, [r3, #0] + 8002c6c: 2222 movs r2, #34 ; 0x22 + 8002c6e: f884 203d strb.w r2, [r4, #61] ; 0x3d + 8002c72: 2210 movs r2, #16 + 8002c74: f884 203e strb.w r2, [r4, #62] ; 0x3e + 8002c78: 2200 movs r2, #0 + 8002c7a: 6422 str r2, [r4, #64] ; 0x40 + 8002c7c: f8a4 802a strh.w r8, [r4, #42] ; 0x2a + 8002c80: 8d62 ldrh r2, [r4, #42] ; 0x2a + 8002c82: 8522 strh r2, [r4, #40] ; 0x28 + 8002c84: 4a89 ldr r2, [pc, #548] ; (8002eac ) + 8002c86: 62e2 str r2, [r4, #44] ; 0x2c + 8002c88: 6ae2 ldr r2, [r4, #44] ; 0x2c + 8002c8a: 6819 ldr r1, [r3, #0] + 8002c8c: f8c4 9024 str.w r9, [r4, #36] ; 0x24 + 8002c90: f441 6180 orr.w r1, r1, #1024 ; 0x400 + 8002c94: 2a08 cmp r2, #8 + 8002c96: 6019 str r1, [r3, #0] + 8002c98: d004 beq.n 8002ca4 + 8002c9a: 2a01 cmp r2, #1 + 8002c9c: d002 beq.n 8002ca4 + 8002c9e: f512 3f80 cmn.w r2, #65536 ; 0x10000 + 8002ca2: d104 bne.n 8002cae + 8002ca4: 681a ldr r2, [r3, #0] + 8002ca6: f442 7280 orr.w r2, r2, #256 ; 0x100 + 8002caa: 601a str r2, [r3, #0] + 8002cac: e002 b.n 8002cb4 + 8002cae: 6b22 ldr r2, [r4, #48] ; 0x30 + 8002cb0: 2a11 cmp r2, #17 + 8002cb2: d0f7 beq.n 8002ca4 + 8002cb4: 463b mov r3, r7 + 8002cb6: 9500 str r5, [sp, #0] + 8002cb8: 2200 movs r2, #0 + 8002cba: f04f 1101 mov.w r1, #65537 ; 0x10001 + 8002cbe: 4620 mov r0, r4 + 8002cc0: f7ff fdcd bl 800285e + 8002cc4: 6823 ldr r3, [r4, #0] + 8002cc6: b138 cbz r0, 8002cd8 + 8002cc8: 681b ldr r3, [r3, #0] + 8002cca: 05d8 lsls r0, r3, #23 + 8002ccc: bf44 itt mi + 8002cce: f44f 7300 movmi.w r3, #512 ; 0x200 + 8002cd2: 6423 strmi r3, [r4, #64] ; 0x40 + 8002cd4: 2601 movs r6, #1 + 8002cd6: e7a9 b.n 8002c2c + 8002cd8: 6922 ldr r2, [r4, #16] + 8002cda: f5b2 4f80 cmp.w r2, #16384 ; 0x4000 + 8002cde: d123 bne.n 8002d28 + 8002ce0: f046 0601 orr.w r6, r6, #1 + 8002ce4: b2f6 uxtb r6, r6 + 8002ce6: 611e str r6, [r3, #16] + 8002ce8: 462b mov r3, r5 + 8002cea: 463a mov r2, r7 + 8002cec: 4970 ldr r1, [pc, #448] ; (8002eb0 ) + 8002cee: 4620 mov r0, r4 + 8002cf0: f7ff fd26 bl 8002740 + 8002cf4: 4606 mov r6, r0 + 8002cf6: 2800 cmp r0, #0 + 8002cf8: d1ec bne.n 8002cd4 + 8002cfa: 8d22 ldrh r2, [r4, #40] ; 0x28 + 8002cfc: 6823 ldr r3, [r4, #0] + 8002cfe: 2a00 cmp r2, #0 + 8002d00: d147 bne.n 8002d92 + 8002d02: 9003 str r0, [sp, #12] + 8002d04: 695a ldr r2, [r3, #20] + 8002d06: 9203 str r2, [sp, #12] + 8002d08: 699a ldr r2, [r3, #24] + 8002d0a: 9203 str r2, [sp, #12] + 8002d0c: 9a03 ldr r2, [sp, #12] + 8002d0e: 681a ldr r2, [r3, #0] + 8002d10: f442 7200 orr.w r2, r2, #512 ; 0x200 + 8002d14: 601a str r2, [r3, #0] + 8002d16: 2320 movs r3, #32 + 8002d18: f884 303d strb.w r3, [r4, #61] ; 0x3d + 8002d1c: 2300 movs r3, #0 + 8002d1e: f884 303e strb.w r3, [r4, #62] ; 0x3e + 8002d22: f884 303c strb.w r3, [r4, #60] ; 0x3c + 8002d26: e781 b.n 8002c2c + 8002d28: ea4f 18e6 mov.w r8, r6, asr #7 + 8002d2c: f008 0806 and.w r8, r8, #6 + 8002d30: f048 02f0 orr.w r2, r8, #240 ; 0xf0 + 8002d34: 611a str r2, [r3, #16] + 8002d36: 495f ldr r1, [pc, #380] ; (8002eb4 ) + 8002d38: 462b mov r3, r5 + 8002d3a: 463a mov r2, r7 + 8002d3c: 4620 mov r0, r4 + 8002d3e: f7ff fcff bl 8002740 + 8002d42: 2800 cmp r0, #0 + 8002d44: d1c6 bne.n 8002cd4 + 8002d46: 6823 ldr r3, [r4, #0] + 8002d48: 4959 ldr r1, [pc, #356] ; (8002eb0 ) + 8002d4a: b2f6 uxtb r6, r6 + 8002d4c: 611e str r6, [r3, #16] + 8002d4e: 463a mov r2, r7 + 8002d50: 462b mov r3, r5 + 8002d52: 4620 mov r0, r4 + 8002d54: f7ff fcf4 bl 8002740 + 8002d58: 4602 mov r2, r0 + 8002d5a: 2800 cmp r0, #0 + 8002d5c: d1ba bne.n 8002cd4 + 8002d5e: 6823 ldr r3, [r4, #0] + 8002d60: 9007 str r0, [sp, #28] + 8002d62: 6959 ldr r1, [r3, #20] + 8002d64: 9107 str r1, [sp, #28] + 8002d66: 6999 ldr r1, [r3, #24] + 8002d68: 9107 str r1, [sp, #28] + 8002d6a: 9907 ldr r1, [sp, #28] + 8002d6c: 6819 ldr r1, [r3, #0] + 8002d6e: f441 7180 orr.w r1, r1, #256 ; 0x100 + 8002d72: 6019 str r1, [r3, #0] + 8002d74: 4620 mov r0, r4 + 8002d76: 9500 str r5, [sp, #0] + 8002d78: 463b mov r3, r7 + 8002d7a: f04f 1101 mov.w r1, #65537 ; 0x10001 + 8002d7e: f7ff fd6e bl 800285e + 8002d82: 6822 ldr r2, [r4, #0] + 8002d84: b108 cbz r0, 8002d8a + 8002d86: 6813 ldr r3, [r2, #0] + 8002d88: e79f b.n 8002cca + 8002d8a: f048 03f1 orr.w r3, r8, #241 ; 0xf1 + 8002d8e: 6113 str r3, [r2, #16] + 8002d90: e7aa b.n 8002ce8 + 8002d92: 2a01 cmp r2, #1 + 8002d94: d12c bne.n 8002df0 + 8002d96: 681a ldr r2, [r3, #0] + 8002d98: f422 6280 bic.w r2, r2, #1024 ; 0x400 + 8002d9c: 601a str r2, [r3, #0] + 8002d9e: 9004 str r0, [sp, #16] + 8002da0: 695a ldr r2, [r3, #20] + 8002da2: 9204 str r2, [sp, #16] + 8002da4: 699a ldr r2, [r3, #24] + 8002da6: 9204 str r2, [sp, #16] + 8002da8: 9a04 ldr r2, [sp, #16] + 8002daa: 681a ldr r2, [r3, #0] + 8002dac: f442 7200 orr.w r2, r2, #512 ; 0x200 + 8002db0: 601a str r2, [r3, #0] + 8002db2: f8df 8104 ldr.w r8, [pc, #260] ; 8002eb8 + 8002db6: 8d23 ldrh r3, [r4, #40] ; 0x28 + 8002db8: 2b00 cmp r3, #0 + 8002dba: d0ac beq.n 8002d16 + 8002dbc: 2b03 cmp r3, #3 + 8002dbe: d87d bhi.n 8002ebc + 8002dc0: 2b01 cmp r3, #1 + 8002dc2: d130 bne.n 8002e26 + 8002dc4: 462a mov r2, r5 + 8002dc6: 4639 mov r1, r7 + 8002dc8: 4620 mov r0, r4 + 8002dca: f7ff fd19 bl 8002800 + 8002dce: 2800 cmp r0, #0 + 8002dd0: d180 bne.n 8002cd4 + 8002dd2: 6823 ldr r3, [r4, #0] + 8002dd4: 691a ldr r2, [r3, #16] + 8002dd6: 6a63 ldr r3, [r4, #36] ; 0x24 + 8002dd8: 701a strb r2, [r3, #0] + 8002dda: 6a63 ldr r3, [r4, #36] ; 0x24 + 8002ddc: 3301 adds r3, #1 + 8002dde: 6263 str r3, [r4, #36] ; 0x24 + 8002de0: 8d23 ldrh r3, [r4, #40] ; 0x28 + 8002de2: 3b01 subs r3, #1 + 8002de4: 8523 strh r3, [r4, #40] ; 0x28 + 8002de6: 8d63 ldrh r3, [r4, #42] ; 0x2a + 8002de8: 3b01 subs r3, #1 + 8002dea: b29b uxth r3, r3 + 8002dec: 8563 strh r3, [r4, #42] ; 0x2a + 8002dee: e7e2 b.n 8002db6 + 8002df0: 2a02 cmp r2, #2 + 8002df2: 681a ldr r2, [r3, #0] + 8002df4: d10d bne.n 8002e12 + 8002df6: f422 6280 bic.w r2, r2, #1024 ; 0x400 + 8002dfa: 601a str r2, [r3, #0] + 8002dfc: 681a ldr r2, [r3, #0] + 8002dfe: f442 6200 orr.w r2, r2, #2048 ; 0x800 + 8002e02: 601a str r2, [r3, #0] + 8002e04: 9005 str r0, [sp, #20] + 8002e06: 695a ldr r2, [r3, #20] + 8002e08: 9205 str r2, [sp, #20] + 8002e0a: 699b ldr r3, [r3, #24] + 8002e0c: 9305 str r3, [sp, #20] + 8002e0e: 9b05 ldr r3, [sp, #20] + 8002e10: e7cf b.n 8002db2 + 8002e12: f442 6280 orr.w r2, r2, #1024 ; 0x400 + 8002e16: 601a str r2, [r3, #0] + 8002e18: 9006 str r0, [sp, #24] + 8002e1a: 695a ldr r2, [r3, #20] + 8002e1c: 9206 str r2, [sp, #24] + 8002e1e: 699b ldr r3, [r3, #24] + 8002e20: 9306 str r3, [sp, #24] + 8002e22: 9b06 ldr r3, [sp, #24] + 8002e24: e7c5 b.n 8002db2 + 8002e26: 2b02 cmp r3, #2 + 8002e28: 9500 str r5, [sp, #0] + 8002e2a: 463b mov r3, r7 + 8002e2c: f04f 0200 mov.w r2, #0 + 8002e30: 4641 mov r1, r8 + 8002e32: 4620 mov r0, r4 + 8002e34: d11a bne.n 8002e6c + 8002e36: f7ff fd12 bl 800285e + 8002e3a: 2800 cmp r0, #0 + 8002e3c: f47f af4a bne.w 8002cd4 + 8002e40: 6823 ldr r3, [r4, #0] + 8002e42: 681a ldr r2, [r3, #0] + 8002e44: f442 7200 orr.w r2, r2, #512 ; 0x200 + 8002e48: 601a str r2, [r3, #0] + 8002e4a: 691a ldr r2, [r3, #16] + 8002e4c: 6a63 ldr r3, [r4, #36] ; 0x24 + 8002e4e: 701a strb r2, [r3, #0] + 8002e50: 6a62 ldr r2, [r4, #36] ; 0x24 + 8002e52: 1c53 adds r3, r2, #1 + 8002e54: 6263 str r3, [r4, #36] ; 0x24 + 8002e56: 8d23 ldrh r3, [r4, #40] ; 0x28 + 8002e58: 3b01 subs r3, #1 + 8002e5a: 8523 strh r3, [r4, #40] ; 0x28 + 8002e5c: 8d63 ldrh r3, [r4, #42] ; 0x2a + 8002e5e: 3b01 subs r3, #1 + 8002e60: b29b uxth r3, r3 + 8002e62: 8563 strh r3, [r4, #42] ; 0x2a + 8002e64: 6823 ldr r3, [r4, #0] + 8002e66: 691b ldr r3, [r3, #16] + 8002e68: 7053 strb r3, [r2, #1] + 8002e6a: e7b6 b.n 8002dda + 8002e6c: f7ff fcf7 bl 800285e + 8002e70: 4602 mov r2, r0 + 8002e72: 2800 cmp r0, #0 + 8002e74: f47f af2e bne.w 8002cd4 + 8002e78: 6823 ldr r3, [r4, #0] + 8002e7a: 6819 ldr r1, [r3, #0] + 8002e7c: f421 6180 bic.w r1, r1, #1024 ; 0x400 + 8002e80: 6019 str r1, [r3, #0] + 8002e82: 6919 ldr r1, [r3, #16] + 8002e84: 6a63 ldr r3, [r4, #36] ; 0x24 + 8002e86: 7019 strb r1, [r3, #0] + 8002e88: 6a63 ldr r3, [r4, #36] ; 0x24 + 8002e8a: 9500 str r5, [sp, #0] + 8002e8c: 3301 adds r3, #1 + 8002e8e: 6263 str r3, [r4, #36] ; 0x24 + 8002e90: 8d23 ldrh r3, [r4, #40] ; 0x28 + 8002e92: 3b01 subs r3, #1 + 8002e94: 8523 strh r3, [r4, #40] ; 0x28 + 8002e96: 8d63 ldrh r3, [r4, #42] ; 0x2a + 8002e98: 3b01 subs r3, #1 + 8002e9a: b29b uxth r3, r3 + 8002e9c: 8563 strh r3, [r4, #42] ; 0x2a + 8002e9e: 4641 mov r1, r8 + 8002ea0: 463b mov r3, r7 + 8002ea2: 4620 mov r0, r4 + 8002ea4: e7c7 b.n 8002e36 + 8002ea6: bf00 nop + 8002ea8: 00100002 .word 0x00100002 + 8002eac: ffff0000 .word 0xffff0000 + 8002eb0: 00010002 .word 0x00010002 + 8002eb4: 00010008 .word 0x00010008 + 8002eb8: 00010004 .word 0x00010004 + 8002ebc: 462a mov r2, r5 + 8002ebe: 4639 mov r1, r7 + 8002ec0: 4620 mov r0, r4 + 8002ec2: f7ff fc9d bl 8002800 + 8002ec6: 2800 cmp r0, #0 + 8002ec8: f47f af04 bne.w 8002cd4 + 8002ecc: 6823 ldr r3, [r4, #0] + 8002ece: 691a ldr r2, [r3, #16] + 8002ed0: 6a63 ldr r3, [r4, #36] ; 0x24 + 8002ed2: 701a strb r2, [r3, #0] + 8002ed4: 6a62 ldr r2, [r4, #36] ; 0x24 + 8002ed6: 1c53 adds r3, r2, #1 + 8002ed8: 6263 str r3, [r4, #36] ; 0x24 + 8002eda: 8d23 ldrh r3, [r4, #40] ; 0x28 + 8002edc: 3b01 subs r3, #1 + 8002ede: 8523 strh r3, [r4, #40] ; 0x28 + 8002ee0: 8d63 ldrh r3, [r4, #42] ; 0x2a + 8002ee2: 3b01 subs r3, #1 + 8002ee4: b29b uxth r3, r3 + 8002ee6: 8563 strh r3, [r4, #42] ; 0x2a + 8002ee8: 6823 ldr r3, [r4, #0] + 8002eea: 6959 ldr r1, [r3, #20] + 8002eec: 0749 lsls r1, r1, #29 + 8002eee: f57f af62 bpl.w 8002db6 + 8002ef2: e7b8 b.n 8002e66 + +08002ef4 : + 8002ef4: b5f8 push {r3, r4, r5, r6, r7, lr} + 8002ef6: 4604 mov r4, r0 + 8002ef8: 2800 cmp r0, #0 + 8002efa: d041 beq.n 8002f80 + 8002efc: f890 3041 ldrb.w r3, [r0, #65] ; 0x41 + 8002f00: f003 02ff and.w r2, r3, #255 ; 0xff + 8002f04: b92b cbnz r3, 8002f12 + 8002f06: 4b42 ldr r3, [pc, #264] ; (8003010 ) + 8002f08: f880 2040 strb.w r2, [r0, #64] ; 0x40 + 8002f0c: 6343 str r3, [r0, #52] ; 0x34 + 8002f0e: f7fe fb05 bl 800151c + 8002f12: 2102 movs r1, #2 + 8002f14: 6822 ldr r2, [r4, #0] + 8002f16: f884 1041 strb.w r1, [r4, #65] ; 0x41 + 8002f1a: 69d3 ldr r3, [r2, #28] + 8002f1c: f423 637b bic.w r3, r3, #4016 ; 0xfb0 + 8002f20: f023 030f bic.w r3, r3, #15 + 8002f24: 61d3 str r3, [r2, #28] + 8002f26: 6963 ldr r3, [r4, #20] + 8002f28: 6211 str r1, [r2, #32] + 8002f2a: 428b cmp r3, r1 + 8002f2c: d031 beq.n 8002f92 + 8002f2e: 68e3 ldr r3, [r4, #12] + 8002f30: 2b00 cmp r3, #0 + 8002f32: 68a3 ldr r3, [r4, #8] + 8002f34: bf14 ite ne + 8002f36: 2520 movne r5, #32 + 8002f38: 2510 moveq r5, #16 + 8002f3a: 2001 movs r0, #1 + 8002f3c: 2b20 cmp r3, #32 + 8002f3e: bf98 it ls + 8002f40: 006d lslls r5, r5, #1 + 8002f42: f000 fd41 bl 80039c8 + 8002f46: 6923 ldr r3, [r4, #16] + 8002f48: 6961 ldr r1, [r4, #20] + 8002f4a: f5b3 7f00 cmp.w r3, #512 ; 0x200 + 8002f4e: d11b bne.n 8002f88 + 8002f50: 68e3 ldr r3, [r4, #12] + 8002f52: 220a movs r2, #10 + 8002f54: b1b3 cbz r3, 8002f84 + 8002f56: 00ab lsls r3, r5, #2 + 8002f58: fbb0 f3f3 udiv r3, r0, r3 + 8002f5c: 4353 muls r3, r2 + 8002f5e: 220a movs r2, #10 + 8002f60: fbb3 f3f1 udiv r3, r3, r1 + 8002f64: 3305 adds r3, #5 + 8002f66: fbb3 f3f2 udiv r3, r3, r2 + 8002f6a: f003 0201 and.w r2, r3, #1 + 8002f6e: 0212 lsls r2, r2, #8 + 8002f70: 085b lsrs r3, r3, #1 + 8002f72: 1e99 subs r1, r3, #2 + 8002f74: 29fd cmp r1, #253 ; 0xfd + 8002f76: d90e bls.n 8002f96 + 8002f78: 6c63 ldr r3, [r4, #68] ; 0x44 + 8002f7a: f043 0310 orr.w r3, r3, #16 + 8002f7e: 6463 str r3, [r4, #68] ; 0x44 + 8002f80: 2001 movs r0, #1 + 8002f82: e044 b.n 800300e + 8002f84: 00eb lsls r3, r5, #3 + 8002f86: e7e7 b.n 8002f58 + 8002f88: 230a movs r3, #10 + 8002f8a: fbb0 f0f5 udiv r0, r0, r5 + 8002f8e: 4343 muls r3, r0 + 8002f90: e7e5 b.n 8002f5e + 8002f92: 2200 movs r2, #0 + 8002f94: e7ed b.n 8002f72 + 8002f96: 4313 orrs r3, r2 + 8002f98: 6922 ldr r2, [r4, #16] + 8002f9a: 6821 ldr r1, [r4, #0] + 8002f9c: 68e5 ldr r5, [r4, #12] + 8002f9e: 69a0 ldr r0, [r4, #24] + 8002fa0: f8df c07c ldr.w ip, [pc, #124] ; 8003020 + 8002fa4: 4313 orrs r3, r2 + 8002fa6: 620b str r3, [r1, #32] + 8002fa8: e9d4 6301 ldrd r6, r3, [r4, #4] + 8002fac: ea46 0203 orr.w r2, r6, r3 + 8002fb0: 69cf ldr r7, [r1, #28] + 8002fb2: f442 6200 orr.w r2, r2, #2048 ; 0x800 + 8002fb6: 432a orrs r2, r5 + 8002fb8: 4302 orrs r2, r0 + 8002fba: ea07 070c and.w r7, r7, ip + 8002fbe: 433a orrs r2, r7 + 8002fc0: 61ca str r2, [r1, #28] + 8002fc2: 6a22 ldr r2, [r4, #32] + 8002fc4: 2a01 cmp r2, #1 + 8002fc6: d11d bne.n 8003004 + 8002fc8: 4a12 ldr r2, [pc, #72] ; (8003014 ) + 8002fca: 6362 str r2, [r4, #52] ; 0x34 + 8002fcc: 4f12 ldr r7, [pc, #72] ; (8003018 ) + 8002fce: 4a13 ldr r2, [pc, #76] ; (800301c ) + 8002fd0: 42b9 cmp r1, r7 + 8002fd2: bf18 it ne + 8002fd4: f04f 2240 movne.w r2, #1073758208 ; 0x40004000 + 8002fd8: 432b orrs r3, r5 + 8002fda: 69d1 ldr r1, [r2, #28] + 8002fdc: ea01 010c and.w r1, r1, ip + 8002fe0: 61d1 str r1, [r2, #28] + 8002fe2: 2102 movs r1, #2 + 8002fe4: 6211 str r1, [r2, #32] + 8002fe6: 69d7 ldr r7, [r2, #28] + 8002fe8: f443 6300 orr.w r3, r3, #2048 ; 0x800 + 8002fec: 4303 orrs r3, r0 + 8002fee: f436 7100 bics.w r1, r6, #512 ; 0x200 + 8002ff2: ea43 0307 orr.w r3, r3, r7 + 8002ff6: bf14 ite ne + 8002ff8: 2100 movne r1, #0 + 8002ffa: f44f 7180 moveq.w r1, #256 ; 0x100 + 8002ffe: b29b uxth r3, r3 + 8003000: 430b orrs r3, r1 + 8003002: 61d3 str r3, [r2, #28] + 8003004: 2000 movs r0, #0 + 8003006: 2301 movs r3, #1 + 8003008: 6460 str r0, [r4, #68] ; 0x44 + 800300a: f884 3041 strb.w r3, [r4, #65] ; 0x41 + 800300e: bdf8 pop {r3, r4, r5, r6, r7, pc} + 8003010: 0800302b .word 0x0800302b + 8003014: 08003129 .word 0x08003129 + 8003018: 40003800 .word 0x40003800 + 800301c: 40003400 .word 0x40003400 + 8003020: fffff040 .word 0xfffff040 + +08003024 : + 8003024: 4770 bx lr + +08003026 : + 8003026: 4770 bx lr + +08003028 : + 8003028: 4770 bx lr + +0800302a : + 800302a: b51f push {r0, r1, r2, r3, r4, lr} + 800302c: 6803 ldr r3, [r0, #0] + 800302e: 689a ldr r2, [r3, #8] + 8003030: 9201 str r2, [sp, #4] + 8003032: f890 2041 ldrb.w r2, [r0, #65] ; 0x41 + 8003036: 2a04 cmp r2, #4 + 8003038: 4604 mov r4, r0 + 800303a: d136 bne.n 80030aa + 800303c: 9a01 ldr r2, [sp, #4] + 800303e: 07d1 lsls r1, r2, #31 + 8003040: d517 bpl.n 8003072 + 8003042: 685a ldr r2, [r3, #4] + 8003044: 0652 lsls r2, r2, #25 + 8003046: d514 bpl.n 8003072 + 8003048: 6ac2 ldr r2, [r0, #44] ; 0x2c + 800304a: 68d9 ldr r1, [r3, #12] + 800304c: f822 1b02 strh.w r1, [r2], #2 + 8003050: 62c2 str r2, [r0, #44] ; 0x2c + 8003052: 8e42 ldrh r2, [r0, #50] ; 0x32 + 8003054: 3a01 subs r2, #1 + 8003056: b292 uxth r2, r2 + 8003058: 8642 strh r2, [r0, #50] ; 0x32 + 800305a: 8e42 ldrh r2, [r0, #50] ; 0x32 + 800305c: b292 uxth r2, r2 + 800305e: b942 cbnz r2, 8003072 + 8003060: 685a ldr r2, [r3, #4] + 8003062: f022 0260 bic.w r2, r2, #96 ; 0x60 + 8003066: 605a str r2, [r3, #4] + 8003068: 2301 movs r3, #1 + 800306a: f880 3041 strb.w r3, [r0, #65] ; 0x41 + 800306e: f7ff ffda bl 8003026 + 8003072: 9b01 ldr r3, [sp, #4] + 8003074: 0659 lsls r1, r3, #25 + 8003076: d518 bpl.n 80030aa + 8003078: 6823 ldr r3, [r4, #0] + 800307a: 685a ldr r2, [r3, #4] + 800307c: 0692 lsls r2, r2, #26 + 800307e: d514 bpl.n 80030aa + 8003080: 685a ldr r2, [r3, #4] + 8003082: f022 0260 bic.w r2, r2, #96 ; 0x60 + 8003086: 605a str r2, [r3, #4] + 8003088: 2200 movs r2, #0 + 800308a: 9202 str r2, [sp, #8] + 800308c: 68da ldr r2, [r3, #12] + 800308e: 9202 str r2, [sp, #8] + 8003090: 689b ldr r3, [r3, #8] + 8003092: 9302 str r3, [sp, #8] + 8003094: 9b02 ldr r3, [sp, #8] + 8003096: 2301 movs r3, #1 + 8003098: f884 3041 strb.w r3, [r4, #65] ; 0x41 + 800309c: 6c63 ldr r3, [r4, #68] ; 0x44 + 800309e: f043 0302 orr.w r3, r3, #2 + 80030a2: 6463 str r3, [r4, #68] ; 0x44 + 80030a4: 4620 mov r0, r4 + 80030a6: f7ff ffbf bl 8003028 + 80030aa: f894 3041 ldrb.w r3, [r4, #65] ; 0x41 + 80030ae: 2b03 cmp r3, #3 + 80030b0: d136 bne.n 8003120 + 80030b2: 9b01 ldr r3, [sp, #4] + 80030b4: 079b lsls r3, r3, #30 + 80030b6: d519 bpl.n 80030ec + 80030b8: 6822 ldr r2, [r4, #0] + 80030ba: 6853 ldr r3, [r2, #4] + 80030bc: 0618 lsls r0, r3, #24 + 80030be: d515 bpl.n 80030ec + 80030c0: 6a63 ldr r3, [r4, #36] ; 0x24 + 80030c2: f833 1b02 ldrh.w r1, [r3], #2 + 80030c6: 60d1 str r1, [r2, #12] + 80030c8: 6263 str r3, [r4, #36] ; 0x24 + 80030ca: 8d63 ldrh r3, [r4, #42] ; 0x2a + 80030cc: 3b01 subs r3, #1 + 80030ce: b29b uxth r3, r3 + 80030d0: 8563 strh r3, [r4, #42] ; 0x2a + 80030d2: 8d63 ldrh r3, [r4, #42] ; 0x2a + 80030d4: b29b uxth r3, r3 + 80030d6: b94b cbnz r3, 80030ec + 80030d8: 6853 ldr r3, [r2, #4] + 80030da: f023 03a0 bic.w r3, r3, #160 ; 0xa0 + 80030de: 6053 str r3, [r2, #4] + 80030e0: 2301 movs r3, #1 + 80030e2: f884 3041 strb.w r3, [r4, #65] ; 0x41 + 80030e6: 4620 mov r0, r4 + 80030e8: f7ff ff9c bl 8003024 + 80030ec: 9b01 ldr r3, [sp, #4] + 80030ee: 0719 lsls r1, r3, #28 + 80030f0: d516 bpl.n 8003120 + 80030f2: 6823 ldr r3, [r4, #0] + 80030f4: 685a ldr r2, [r3, #4] + 80030f6: 0692 lsls r2, r2, #26 + 80030f8: d512 bpl.n 8003120 + 80030fa: 685a ldr r2, [r3, #4] + 80030fc: f022 02a0 bic.w r2, r2, #160 ; 0xa0 + 8003100: 605a str r2, [r3, #4] + 8003102: 2200 movs r2, #0 + 8003104: 9203 str r2, [sp, #12] + 8003106: 689b ldr r3, [r3, #8] + 8003108: 9303 str r3, [sp, #12] + 800310a: 9b03 ldr r3, [sp, #12] + 800310c: 2301 movs r3, #1 + 800310e: f884 3041 strb.w r3, [r4, #65] ; 0x41 + 8003112: 6c63 ldr r3, [r4, #68] ; 0x44 + 8003114: f043 0304 orr.w r3, r3, #4 + 8003118: 6463 str r3, [r4, #68] ; 0x44 + 800311a: 4620 mov r0, r4 + 800311c: f7ff ff84 bl 8003028 + 8003120: b004 add sp, #16 + 8003122: bd10 pop {r4, pc} + +08003124 : + 8003124: 4770 bx lr + ... + +08003128 : + 8003128: b510 push {r4, lr} + 800312a: 6802 ldr r2, [r0, #0] + 800312c: 498e ldr r1, [pc, #568] ; (8003368 ) + 800312e: 6893 ldr r3, [r2, #8] + 8003130: b086 sub sp, #24 + 8003132: 4604 mov r4, r0 + 8003134: 9300 str r3, [sp, #0] + 8003136: 4b8d ldr r3, [pc, #564] ; (800336c ) + 8003138: 428a cmp r2, r1 + 800313a: bf18 it ne + 800313c: f04f 2340 movne.w r3, #1073758208 ; 0x40004000 + 8003140: 6899 ldr r1, [r3, #8] + 8003142: 9101 str r1, [sp, #4] + 8003144: 6851 ldr r1, [r2, #4] + 8003146: 9102 str r1, [sp, #8] + 8003148: 6859 ldr r1, [r3, #4] + 800314a: 9103 str r1, [sp, #12] + 800314c: 6841 ldr r1, [r0, #4] + 800314e: f431 7100 bics.w r1, r1, #512 ; 0x200 + 8003152: f040 8093 bne.w 800327c + 8003156: 9b00 ldr r3, [sp, #0] + 8003158: 0799 lsls r1, r3, #30 + 800315a: d51a bpl.n 8003192 + 800315c: 9b02 ldr r3, [sp, #8] + 800315e: 061b lsls r3, r3, #24 + 8003160: d517 bpl.n 8003192 + 8003162: 6a43 ldr r3, [r0, #36] ; 0x24 + 8003164: 1c99 adds r1, r3, #2 + 8003166: 881b ldrh r3, [r3, #0] + 8003168: 6241 str r1, [r0, #36] ; 0x24 + 800316a: 60d3 str r3, [r2, #12] + 800316c: 8d43 ldrh r3, [r0, #42] ; 0x2a + 800316e: 3b01 subs r3, #1 + 8003170: b29b uxth r3, r3 + 8003172: 8543 strh r3, [r0, #42] ; 0x2a + 8003174: 8d43 ldrh r3, [r0, #42] ; 0x2a + 8003176: b29b uxth r3, r3 + 8003178: b95b cbnz r3, 8003192 + 800317a: 6853 ldr r3, [r2, #4] + 800317c: f023 03a0 bic.w r3, r3, #160 ; 0xa0 + 8003180: 6053 str r3, [r2, #4] + 8003182: 8e43 ldrh r3, [r0, #50] ; 0x32 + 8003184: b29b uxth r3, r3 + 8003186: b923 cbnz r3, 8003192 + 8003188: 2301 movs r3, #1 + 800318a: f880 3041 strb.w r3, [r0, #65] ; 0x41 + 800318e: f7ff ffc9 bl 8003124 + 8003192: 9b01 ldr r3, [sp, #4] + 8003194: 07d8 lsls r0, r3, #31 + 8003196: d522 bpl.n 80031de + 8003198: 9b03 ldr r3, [sp, #12] + 800319a: 0659 lsls r1, r3, #25 + 800319c: d51f bpl.n 80031de + 800319e: 6821 ldr r1, [r4, #0] + 80031a0: 4a71 ldr r2, [pc, #452] ; (8003368 ) + 80031a2: 4b72 ldr r3, [pc, #456] ; (800336c ) + 80031a4: 4291 cmp r1, r2 + 80031a6: bf18 it ne + 80031a8: f04f 2340 movne.w r3, #1073758208 ; 0x40004000 + 80031ac: 6ae2 ldr r2, [r4, #44] ; 0x2c + 80031ae: 68d9 ldr r1, [r3, #12] + 80031b0: 1c90 adds r0, r2, #2 + 80031b2: 62e0 str r0, [r4, #44] ; 0x2c + 80031b4: 8011 strh r1, [r2, #0] + 80031b6: 8e62 ldrh r2, [r4, #50] ; 0x32 + 80031b8: 3a01 subs r2, #1 + 80031ba: b292 uxth r2, r2 + 80031bc: 8662 strh r2, [r4, #50] ; 0x32 + 80031be: 8e62 ldrh r2, [r4, #50] ; 0x32 + 80031c0: b292 uxth r2, r2 + 80031c2: b962 cbnz r2, 80031de + 80031c4: 685a ldr r2, [r3, #4] + 80031c6: f022 0260 bic.w r2, r2, #96 ; 0x60 + 80031ca: 605a str r2, [r3, #4] + 80031cc: 8d63 ldrh r3, [r4, #42] ; 0x2a + 80031ce: b29b uxth r3, r3 + 80031d0: b92b cbnz r3, 80031de + 80031d2: 2301 movs r3, #1 + 80031d4: f884 3041 strb.w r3, [r4, #65] ; 0x41 + 80031d8: 4620 mov r0, r4 + 80031da: f7ff ffa3 bl 8003124 + 80031de: 9b01 ldr r3, [sp, #4] + 80031e0: 065a lsls r2, r3, #25 + 80031e2: d522 bpl.n 800322a + 80031e4: 9b03 ldr r3, [sp, #12] + 80031e6: 069b lsls r3, r3, #26 + 80031e8: d51f bpl.n 800322a + 80031ea: 6823 ldr r3, [r4, #0] + 80031ec: 495e ldr r1, [pc, #376] ; (8003368 ) + 80031ee: 4a5f ldr r2, [pc, #380] ; (800336c ) + 80031f0: 428b cmp r3, r1 + 80031f2: bf18 it ne + 80031f4: f04f 2240 movne.w r2, #1073758208 ; 0x40004000 + 80031f8: 4620 mov r0, r4 + 80031fa: 6851 ldr r1, [r2, #4] + 80031fc: f021 0160 bic.w r1, r1, #96 ; 0x60 + 8003200: 6051 str r1, [r2, #4] + 8003202: 685a ldr r2, [r3, #4] + 8003204: f022 02a0 bic.w r2, r2, #160 ; 0xa0 + 8003208: 605a str r2, [r3, #4] + 800320a: 2200 movs r2, #0 + 800320c: 9204 str r2, [sp, #16] + 800320e: 68da ldr r2, [r3, #12] + 8003210: 9204 str r2, [sp, #16] + 8003212: 689b ldr r3, [r3, #8] + 8003214: 9304 str r3, [sp, #16] + 8003216: 9b04 ldr r3, [sp, #16] + 8003218: 2301 movs r3, #1 + 800321a: f884 3041 strb.w r3, [r4, #65] ; 0x41 + 800321e: 6c63 ldr r3, [r4, #68] ; 0x44 + 8003220: f043 0302 orr.w r3, r3, #2 + 8003224: 6463 str r3, [r4, #68] ; 0x44 + 8003226: f7ff feff bl 8003028 + 800322a: 9b00 ldr r3, [sp, #0] + 800322c: 0718 lsls r0, r3, #28 + 800322e: f140 8098 bpl.w 8003362 + 8003232: 9b02 ldr r3, [sp, #8] + 8003234: 0699 lsls r1, r3, #26 + 8003236: f140 8094 bpl.w 8003362 + 800323a: 6823 ldr r3, [r4, #0] + 800323c: 494a ldr r1, [pc, #296] ; (8003368 ) + 800323e: 685a ldr r2, [r3, #4] + 8003240: f022 02a0 bic.w r2, r2, #160 ; 0xa0 + 8003244: 605a str r2, [r3, #4] + 8003246: 4a49 ldr r2, [pc, #292] ; (800336c ) + 8003248: 428b cmp r3, r1 + 800324a: bf18 it ne + 800324c: f04f 2240 movne.w r2, #1073758208 ; 0x40004000 + 8003250: 6851 ldr r1, [r2, #4] + 8003252: f021 0160 bic.w r1, r1, #96 ; 0x60 + 8003256: 6051 str r1, [r2, #4] + 8003258: 2200 movs r2, #0 + 800325a: 9205 str r2, [sp, #20] + 800325c: 689b ldr r3, [r3, #8] + 800325e: 9305 str r3, [sp, #20] + 8003260: 9b05 ldr r3, [sp, #20] + 8003262: 2301 movs r3, #1 + 8003264: f884 3041 strb.w r3, [r4, #65] ; 0x41 + 8003268: 6c63 ldr r3, [r4, #68] ; 0x44 + 800326a: 4620 mov r0, r4 + 800326c: f043 0304 orr.w r3, r3, #4 + 8003270: 6463 str r3, [r4, #68] ; 0x44 + 8003272: b006 add sp, #24 + 8003274: e8bd 4010 ldmia.w sp!, {r4, lr} + 8003278: f7ff bed6 b.w 8003028 + 800327c: 9a01 ldr r2, [sp, #4] + 800327e: 0792 lsls r2, r2, #30 + 8003280: d51a bpl.n 80032b8 + 8003282: 9a03 ldr r2, [sp, #12] + 8003284: 0611 lsls r1, r2, #24 + 8003286: d517 bpl.n 80032b8 + 8003288: 6a42 ldr r2, [r0, #36] ; 0x24 + 800328a: 1c91 adds r1, r2, #2 + 800328c: 8812 ldrh r2, [r2, #0] + 800328e: 6241 str r1, [r0, #36] ; 0x24 + 8003290: 60da str r2, [r3, #12] + 8003292: 8d42 ldrh r2, [r0, #42] ; 0x2a + 8003294: 3a01 subs r2, #1 + 8003296: b292 uxth r2, r2 + 8003298: 8542 strh r2, [r0, #42] ; 0x2a + 800329a: 8d42 ldrh r2, [r0, #42] ; 0x2a + 800329c: b292 uxth r2, r2 + 800329e: b95a cbnz r2, 80032b8 + 80032a0: 685a ldr r2, [r3, #4] + 80032a2: f022 02a0 bic.w r2, r2, #160 ; 0xa0 + 80032a6: 605a str r2, [r3, #4] + 80032a8: 8e43 ldrh r3, [r0, #50] ; 0x32 + 80032aa: b29b uxth r3, r3 + 80032ac: b923 cbnz r3, 80032b8 + 80032ae: 2301 movs r3, #1 + 80032b0: f880 3041 strb.w r3, [r0, #65] ; 0x41 + 80032b4: f7ff ff36 bl 8003124 + 80032b8: 9b00 ldr r3, [sp, #0] + 80032ba: 07da lsls r2, r3, #31 + 80032bc: d51c bpl.n 80032f8 + 80032be: 9b02 ldr r3, [sp, #8] + 80032c0: 065b lsls r3, r3, #25 + 80032c2: d519 bpl.n 80032f8 + 80032c4: 6ae3 ldr r3, [r4, #44] ; 0x2c + 80032c6: 6822 ldr r2, [r4, #0] + 80032c8: 1c98 adds r0, r3, #2 + 80032ca: 68d1 ldr r1, [r2, #12] + 80032cc: 62e0 str r0, [r4, #44] ; 0x2c + 80032ce: 8019 strh r1, [r3, #0] + 80032d0: 8e63 ldrh r3, [r4, #50] ; 0x32 + 80032d2: 3b01 subs r3, #1 + 80032d4: b29b uxth r3, r3 + 80032d6: 8663 strh r3, [r4, #50] ; 0x32 + 80032d8: 8e63 ldrh r3, [r4, #50] ; 0x32 + 80032da: b29b uxth r3, r3 + 80032dc: b963 cbnz r3, 80032f8 + 80032de: 6853 ldr r3, [r2, #4] + 80032e0: f023 0360 bic.w r3, r3, #96 ; 0x60 + 80032e4: 6053 str r3, [r2, #4] + 80032e6: 8d63 ldrh r3, [r4, #42] ; 0x2a + 80032e8: b29b uxth r3, r3 + 80032ea: b92b cbnz r3, 80032f8 + 80032ec: 2301 movs r3, #1 + 80032ee: f884 3041 strb.w r3, [r4, #65] ; 0x41 + 80032f2: 4620 mov r0, r4 + 80032f4: f7ff ff16 bl 8003124 + 80032f8: 9b00 ldr r3, [sp, #0] + 80032fa: 0658 lsls r0, r3, #25 + 80032fc: d51b bpl.n 8003336 + 80032fe: 9b02 ldr r3, [sp, #8] + 8003300: 0699 lsls r1, r3, #26 + 8003302: d518 bpl.n 8003336 + 8003304: 6822 ldr r2, [r4, #0] + 8003306: 4918 ldr r1, [pc, #96] ; (8003368 ) + 8003308: 6853 ldr r3, [r2, #4] + 800330a: f023 0360 bic.w r3, r3, #96 ; 0x60 + 800330e: 6053 str r3, [r2, #4] + 8003310: 4b16 ldr r3, [pc, #88] ; (800336c ) + 8003312: 428a cmp r2, r1 + 8003314: bf18 it ne + 8003316: f04f 2340 movne.w r3, #1073758208 ; 0x40004000 + 800331a: 4620 mov r0, r4 + 800331c: 685a ldr r2, [r3, #4] + 800331e: f022 02a0 bic.w r2, r2, #160 ; 0xa0 + 8003322: 605a str r2, [r3, #4] + 8003324: 2301 movs r3, #1 + 8003326: f884 3041 strb.w r3, [r4, #65] ; 0x41 + 800332a: 6c63 ldr r3, [r4, #68] ; 0x44 + 800332c: f043 0302 orr.w r3, r3, #2 + 8003330: 6463 str r3, [r4, #68] ; 0x44 + 8003332: f7ff fe79 bl 8003028 + 8003336: 9b01 ldr r3, [sp, #4] + 8003338: 071a lsls r2, r3, #28 + 800333a: d512 bpl.n 8003362 + 800333c: 9b03 ldr r3, [sp, #12] + 800333e: 069b lsls r3, r3, #26 + 8003340: d50f bpl.n 8003362 + 8003342: 6822 ldr r2, [r4, #0] + 8003344: 4908 ldr r1, [pc, #32] ; (8003368 ) + 8003346: 4b09 ldr r3, [pc, #36] ; (800336c ) + 8003348: 428a cmp r2, r1 + 800334a: bf18 it ne + 800334c: f04f 2340 movne.w r3, #1073758208 ; 0x40004000 + 8003350: 6859 ldr r1, [r3, #4] + 8003352: f021 01a0 bic.w r1, r1, #160 ; 0xa0 + 8003356: 6059 str r1, [r3, #4] + 8003358: 6853 ldr r3, [r2, #4] + 800335a: f023 0360 bic.w r3, r3, #96 ; 0x60 + 800335e: 6053 str r3, [r2, #4] + 8003360: e77f b.n 8003262 + 8003362: b006 add sp, #24 + 8003364: bd10 pop {r4, pc} + 8003366: bf00 nop + 8003368: 40003800 .word 0x40003800 + 800336c: 40003400 .word 0x40003400 + +08003370 : + 8003370: e92d 41f3 stmdb sp!, {r0, r1, r4, r5, r6, r7, r8, lr} + 8003374: 4604 mov r4, r0 + 8003376: b908 cbnz r0, 800337c + 8003378: 2001 movs r0, #1 + 800337a: e03f b.n 80033fc + 800337c: 6803 ldr r3, [r0, #0] + 800337e: 07dd lsls r5, r3, #31 + 8003380: d410 bmi.n 80033a4 + 8003382: 6823 ldr r3, [r4, #0] + 8003384: 0798 lsls r0, r3, #30 + 8003386: d45a bmi.n 800343e + 8003388: 6823 ldr r3, [r4, #0] + 800338a: 071a lsls r2, r3, #28 + 800338c: f100 809c bmi.w 80034c8 + 8003390: 6823 ldr r3, [r4, #0] + 8003392: 075b lsls r3, r3, #29 + 8003394: f100 80ba bmi.w 800350c + 8003398: 69a0 ldr r0, [r4, #24] + 800339a: 2800 cmp r0, #0 + 800339c: f040 811b bne.w 80035d6 + 80033a0: 2000 movs r0, #0 + 80033a2: e02b b.n 80033fc + 80033a4: 4ba7 ldr r3, [pc, #668] ; (8003644 ) + 80033a6: 689a ldr r2, [r3, #8] + 80033a8: f002 020c and.w r2, r2, #12 + 80033ac: 2a04 cmp r2, #4 + 80033ae: d007 beq.n 80033c0 + 80033b0: 689a ldr r2, [r3, #8] + 80033b2: f002 020c and.w r2, r2, #12 + 80033b6: 2a08 cmp r2, #8 + 80033b8: d10a bne.n 80033d0 + 80033ba: 685b ldr r3, [r3, #4] + 80033bc: 0259 lsls r1, r3, #9 + 80033be: d507 bpl.n 80033d0 + 80033c0: 4ba0 ldr r3, [pc, #640] ; (8003644 ) + 80033c2: 681b ldr r3, [r3, #0] + 80033c4: 039a lsls r2, r3, #14 + 80033c6: d5dc bpl.n 8003382 + 80033c8: 6863 ldr r3, [r4, #4] + 80033ca: 2b00 cmp r3, #0 + 80033cc: d1d9 bne.n 8003382 + 80033ce: e7d3 b.n 8003378 + 80033d0: 6863 ldr r3, [r4, #4] + 80033d2: 4d9c ldr r5, [pc, #624] ; (8003644 ) + 80033d4: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 80033d8: d113 bne.n 8003402 + 80033da: 682b ldr r3, [r5, #0] + 80033dc: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 80033e0: 602b str r3, [r5, #0] + 80033e2: f7fe fc03 bl 8001bec + 80033e6: 4d97 ldr r5, [pc, #604] ; (8003644 ) + 80033e8: 4606 mov r6, r0 + 80033ea: 682b ldr r3, [r5, #0] + 80033ec: 039b lsls r3, r3, #14 + 80033ee: d4c8 bmi.n 8003382 + 80033f0: f7fe fbfc bl 8001bec + 80033f4: 1b80 subs r0, r0, r6 + 80033f6: 2864 cmp r0, #100 ; 0x64 + 80033f8: d9f7 bls.n 80033ea + 80033fa: 2003 movs r0, #3 + 80033fc: b002 add sp, #8 + 80033fe: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 8003402: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 + 8003406: d104 bne.n 8003412 + 8003408: 682b ldr r3, [r5, #0] + 800340a: f443 2380 orr.w r3, r3, #262144 ; 0x40000 + 800340e: 602b str r3, [r5, #0] + 8003410: e7e3 b.n 80033da + 8003412: 682a ldr r2, [r5, #0] + 8003414: f422 3280 bic.w r2, r2, #65536 ; 0x10000 + 8003418: 602a str r2, [r5, #0] + 800341a: 682a ldr r2, [r5, #0] + 800341c: f422 2280 bic.w r2, r2, #262144 ; 0x40000 + 8003420: 602a str r2, [r5, #0] + 8003422: 2b00 cmp r3, #0 + 8003424: d1dd bne.n 80033e2 + 8003426: f7fe fbe1 bl 8001bec + 800342a: 4606 mov r6, r0 + 800342c: 682b ldr r3, [r5, #0] + 800342e: 039f lsls r7, r3, #14 + 8003430: d5a7 bpl.n 8003382 + 8003432: f7fe fbdb bl 8001bec + 8003436: 1b80 subs r0, r0, r6 + 8003438: 2864 cmp r0, #100 ; 0x64 + 800343a: d9f7 bls.n 800342c + 800343c: e7dd b.n 80033fa + 800343e: 4b81 ldr r3, [pc, #516] ; (8003644 ) + 8003440: 689a ldr r2, [r3, #8] + 8003442: f012 0f0c tst.w r2, #12 + 8003446: d007 beq.n 8003458 + 8003448: 689a ldr r2, [r3, #8] + 800344a: f002 020c and.w r2, r2, #12 + 800344e: 2a08 cmp r2, #8 + 8003450: d111 bne.n 8003476 + 8003452: 685b ldr r3, [r3, #4] + 8003454: 025e lsls r6, r3, #9 + 8003456: d40e bmi.n 8003476 + 8003458: 4b7a ldr r3, [pc, #488] ; (8003644 ) + 800345a: 681a ldr r2, [r3, #0] + 800345c: 0795 lsls r5, r2, #30 + 800345e: d502 bpl.n 8003466 + 8003460: 68e2 ldr r2, [r4, #12] + 8003462: 2a01 cmp r2, #1 + 8003464: d188 bne.n 8003378 + 8003466: 681a ldr r2, [r3, #0] + 8003468: 6921 ldr r1, [r4, #16] + 800346a: f022 02f8 bic.w r2, r2, #248 ; 0xf8 + 800346e: ea42 02c1 orr.w r2, r2, r1, lsl #3 + 8003472: 601a str r2, [r3, #0] + 8003474: e788 b.n 8003388 + 8003476: 68e2 ldr r2, [r4, #12] + 8003478: 4b73 ldr r3, [pc, #460] ; (8003648 ) + 800347a: b1b2 cbz r2, 80034aa + 800347c: 2201 movs r2, #1 + 800347e: 601a str r2, [r3, #0] + 8003480: f7fe fbb4 bl 8001bec + 8003484: 4d6f ldr r5, [pc, #444] ; (8003644 ) + 8003486: 4606 mov r6, r0 + 8003488: 682b ldr r3, [r5, #0] + 800348a: 0798 lsls r0, r3, #30 + 800348c: d507 bpl.n 800349e + 800348e: 682b ldr r3, [r5, #0] + 8003490: 6922 ldr r2, [r4, #16] + 8003492: f023 03f8 bic.w r3, r3, #248 ; 0xf8 + 8003496: ea43 03c2 orr.w r3, r3, r2, lsl #3 + 800349a: 602b str r3, [r5, #0] + 800349c: e774 b.n 8003388 + 800349e: f7fe fba5 bl 8001bec + 80034a2: 1b80 subs r0, r0, r6 + 80034a4: 2802 cmp r0, #2 + 80034a6: d9ef bls.n 8003488 + 80034a8: e7a7 b.n 80033fa + 80034aa: 601a str r2, [r3, #0] + 80034ac: f7fe fb9e bl 8001bec + 80034b0: 4d64 ldr r5, [pc, #400] ; (8003644 ) + 80034b2: 4606 mov r6, r0 + 80034b4: 682b ldr r3, [r5, #0] + 80034b6: 0799 lsls r1, r3, #30 + 80034b8: f57f af66 bpl.w 8003388 + 80034bc: f7fe fb96 bl 8001bec + 80034c0: 1b80 subs r0, r0, r6 + 80034c2: 2802 cmp r0, #2 + 80034c4: d9f6 bls.n 80034b4 + 80034c6: e798 b.n 80033fa + 80034c8: 6962 ldr r2, [r4, #20] + 80034ca: 4b60 ldr r3, [pc, #384] ; (800364c ) + 80034cc: b17a cbz r2, 80034ee + 80034ce: 2201 movs r2, #1 + 80034d0: 601a str r2, [r3, #0] + 80034d2: f7fe fb8b bl 8001bec + 80034d6: 4d5b ldr r5, [pc, #364] ; (8003644 ) + 80034d8: 4606 mov r6, r0 + 80034da: 6f6b ldr r3, [r5, #116] ; 0x74 + 80034dc: 079f lsls r7, r3, #30 + 80034de: f53f af57 bmi.w 8003390 + 80034e2: f7fe fb83 bl 8001bec + 80034e6: 1b80 subs r0, r0, r6 + 80034e8: 2802 cmp r0, #2 + 80034ea: d9f6 bls.n 80034da + 80034ec: e785 b.n 80033fa + 80034ee: 601a str r2, [r3, #0] + 80034f0: f7fe fb7c bl 8001bec + 80034f4: 4d53 ldr r5, [pc, #332] ; (8003644 ) + 80034f6: 4606 mov r6, r0 + 80034f8: 6f6b ldr r3, [r5, #116] ; 0x74 + 80034fa: 0798 lsls r0, r3, #30 + 80034fc: f57f af48 bpl.w 8003390 + 8003500: f7fe fb74 bl 8001bec + 8003504: 1b80 subs r0, r0, r6 + 8003506: 2802 cmp r0, #2 + 8003508: d9f6 bls.n 80034f8 + 800350a: e776 b.n 80033fa + 800350c: 4b4d ldr r3, [pc, #308] ; (8003644 ) + 800350e: 6c1a ldr r2, [r3, #64] ; 0x40 + 8003510: f012 5280 ands.w r2, r2, #268435456 ; 0x10000000 + 8003514: d128 bne.n 8003568 + 8003516: 9201 str r2, [sp, #4] + 8003518: 6c1a ldr r2, [r3, #64] ; 0x40 + 800351a: f042 5280 orr.w r2, r2, #268435456 ; 0x10000000 + 800351e: 641a str r2, [r3, #64] ; 0x40 + 8003520: 6c1b ldr r3, [r3, #64] ; 0x40 + 8003522: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8003526: 9301 str r3, [sp, #4] + 8003528: 9b01 ldr r3, [sp, #4] + 800352a: 2601 movs r6, #1 + 800352c: 4d48 ldr r5, [pc, #288] ; (8003650 ) + 800352e: 682b ldr r3, [r5, #0] + 8003530: 05d9 lsls r1, r3, #23 + 8003532: d51b bpl.n 800356c + 8003534: 68a3 ldr r3, [r4, #8] + 8003536: 4d43 ldr r5, [pc, #268] ; (8003644 ) + 8003538: 2b01 cmp r3, #1 + 800353a: d127 bne.n 800358c + 800353c: 6f2b ldr r3, [r5, #112] ; 0x70 + 800353e: f043 0301 orr.w r3, r3, #1 + 8003542: 672b str r3, [r5, #112] ; 0x70 + 8003544: f7fe fb52 bl 8001bec + 8003548: 4d3e ldr r5, [pc, #248] ; (8003644 ) + 800354a: 4607 mov r7, r0 + 800354c: f241 3888 movw r8, #5000 ; 0x1388 + 8003550: 6f2b ldr r3, [r5, #112] ; 0x70 + 8003552: 079b lsls r3, r3, #30 + 8003554: d539 bpl.n 80035ca + 8003556: 2e00 cmp r6, #0 + 8003558: f43f af1e beq.w 8003398 + 800355c: 4a39 ldr r2, [pc, #228] ; (8003644 ) + 800355e: 6c13 ldr r3, [r2, #64] ; 0x40 + 8003560: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 + 8003564: 6413 str r3, [r2, #64] ; 0x40 + 8003566: e717 b.n 8003398 + 8003568: 2600 movs r6, #0 + 800356a: e7df b.n 800352c + 800356c: 682b ldr r3, [r5, #0] + 800356e: f443 7380 orr.w r3, r3, #256 ; 0x100 + 8003572: 602b str r3, [r5, #0] + 8003574: f7fe fb3a bl 8001bec + 8003578: 4607 mov r7, r0 + 800357a: 682b ldr r3, [r5, #0] + 800357c: 05da lsls r2, r3, #23 + 800357e: d4d9 bmi.n 8003534 + 8003580: f7fe fb34 bl 8001bec + 8003584: 1bc0 subs r0, r0, r7 + 8003586: 2802 cmp r0, #2 + 8003588: d9f7 bls.n 800357a + 800358a: e736 b.n 80033fa + 800358c: 2b05 cmp r3, #5 + 800358e: d104 bne.n 800359a + 8003590: 6f2b ldr r3, [r5, #112] ; 0x70 + 8003592: f043 0304 orr.w r3, r3, #4 + 8003596: 672b str r3, [r5, #112] ; 0x70 + 8003598: e7d0 b.n 800353c + 800359a: 6f2a ldr r2, [r5, #112] ; 0x70 + 800359c: f022 0201 bic.w r2, r2, #1 + 80035a0: 672a str r2, [r5, #112] ; 0x70 + 80035a2: 6f2a ldr r2, [r5, #112] ; 0x70 + 80035a4: f022 0204 bic.w r2, r2, #4 + 80035a8: 672a str r2, [r5, #112] ; 0x70 + 80035aa: 2b00 cmp r3, #0 + 80035ac: d1ca bne.n 8003544 + 80035ae: f7fe fb1d bl 8001bec + 80035b2: f241 3888 movw r8, #5000 ; 0x1388 + 80035b6: 4607 mov r7, r0 + 80035b8: 6f2b ldr r3, [r5, #112] ; 0x70 + 80035ba: 0798 lsls r0, r3, #30 + 80035bc: d5cb bpl.n 8003556 + 80035be: f7fe fb15 bl 8001bec + 80035c2: 1bc0 subs r0, r0, r7 + 80035c4: 4540 cmp r0, r8 + 80035c6: d9f7 bls.n 80035b8 + 80035c8: e717 b.n 80033fa + 80035ca: f7fe fb0f bl 8001bec + 80035ce: 1bc0 subs r0, r0, r7 + 80035d0: 4540 cmp r0, r8 + 80035d2: d9bd bls.n 8003550 + 80035d4: e711 b.n 80033fa + 80035d6: 4d1b ldr r5, [pc, #108] ; (8003644 ) + 80035d8: 68ab ldr r3, [r5, #8] + 80035da: f003 030c and.w r3, r3, #12 + 80035de: 2b08 cmp r3, #8 + 80035e0: d047 beq.n 8003672 + 80035e2: 4e1c ldr r6, [pc, #112] ; (8003654 ) + 80035e4: 2300 movs r3, #0 + 80035e6: 2802 cmp r0, #2 + 80035e8: 6033 str r3, [r6, #0] + 80035ea: d135 bne.n 8003658 + 80035ec: f7fe fafe bl 8001bec + 80035f0: 4607 mov r7, r0 + 80035f2: 682b ldr r3, [r5, #0] + 80035f4: 0199 lsls r1, r3, #6 + 80035f6: d41e bmi.n 8003636 + 80035f8: e9d4 3207 ldrd r3, r2, [r4, #28] + 80035fc: 4313 orrs r3, r2 + 80035fe: 6a62 ldr r2, [r4, #36] ; 0x24 + 8003600: ea43 1382 orr.w r3, r3, r2, lsl #6 + 8003604: 6ae2 ldr r2, [r4, #44] ; 0x2c + 8003606: ea43 6302 orr.w r3, r3, r2, lsl #24 + 800360a: 6aa2 ldr r2, [r4, #40] ; 0x28 + 800360c: 4c0d ldr r4, [pc, #52] ; (8003644 ) + 800360e: 0852 lsrs r2, r2, #1 + 8003610: 3a01 subs r2, #1 + 8003612: ea43 4302 orr.w r3, r3, r2, lsl #16 + 8003616: 606b str r3, [r5, #4] + 8003618: 2301 movs r3, #1 + 800361a: 6033 str r3, [r6, #0] + 800361c: f7fe fae6 bl 8001bec + 8003620: 4605 mov r5, r0 + 8003622: 6823 ldr r3, [r4, #0] + 8003624: 019a lsls r2, r3, #6 + 8003626: f53f aebb bmi.w 80033a0 + 800362a: f7fe fadf bl 8001bec + 800362e: 1b40 subs r0, r0, r5 + 8003630: 2802 cmp r0, #2 + 8003632: d9f6 bls.n 8003622 + 8003634: e6e1 b.n 80033fa + 8003636: f7fe fad9 bl 8001bec + 800363a: 1bc0 subs r0, r0, r7 + 800363c: 2802 cmp r0, #2 + 800363e: d9d8 bls.n 80035f2 + 8003640: e6db b.n 80033fa + 8003642: bf00 nop + 8003644: 40023800 .word 0x40023800 + 8003648: 42470000 .word 0x42470000 + 800364c: 42470e80 .word 0x42470e80 + 8003650: 40007000 .word 0x40007000 + 8003654: 42470060 .word 0x42470060 + 8003658: f7fe fac8 bl 8001bec + 800365c: 4604 mov r4, r0 + 800365e: 682b ldr r3, [r5, #0] + 8003660: 019b lsls r3, r3, #6 + 8003662: f57f ae9d bpl.w 80033a0 + 8003666: f7fe fac1 bl 8001bec + 800366a: 1b00 subs r0, r0, r4 + 800366c: 2802 cmp r0, #2 + 800366e: d9f6 bls.n 800365e + 8003670: e6c3 b.n 80033fa + 8003672: 2801 cmp r0, #1 + 8003674: f43f aec2 beq.w 80033fc + 8003678: 6868 ldr r0, [r5, #4] + 800367a: 69e3 ldr r3, [r4, #28] + 800367c: f400 0280 and.w r2, r0, #4194304 ; 0x400000 + 8003680: 429a cmp r2, r3 + 8003682: f47f ae79 bne.w 8003378 + 8003686: 6a22 ldr r2, [r4, #32] + 8003688: f000 033f and.w r3, r0, #63 ; 0x3f + 800368c: 4293 cmp r3, r2 + 800368e: f47f ae73 bne.w 8003378 + 8003692: 6a62 ldr r2, [r4, #36] ; 0x24 + 8003694: f647 73c0 movw r3, #32704 ; 0x7fc0 + 8003698: 4003 ands r3, r0 + 800369a: 4293 cmp r3, r2 + 800369c: f47f ae6c bne.w 8003378 + 80036a0: 6aa2 ldr r2, [r4, #40] ; 0x28 + 80036a2: f400 3340 and.w r3, r0, #196608 ; 0x30000 + 80036a6: 4293 cmp r3, r2 + 80036a8: f47f ae66 bne.w 8003378 + 80036ac: 6ae3 ldr r3, [r4, #44] ; 0x2c + 80036ae: f000 6070 and.w r0, r0, #251658240 ; 0xf000000 + 80036b2: 1ac0 subs r0, r0, r3 + 80036b4: bf18 it ne + 80036b6: 2001 movne r0, #1 + 80036b8: e6a0 b.n 80033fc + 80036ba: bf00 nop + +080036bc : + 80036bc: 4913 ldr r1, [pc, #76] ; (800370c ) + 80036be: b508 push {r3, lr} + 80036c0: 688b ldr r3, [r1, #8] + 80036c2: f003 030c and.w r3, r3, #12 + 80036c6: 2b04 cmp r3, #4 + 80036c8: d003 beq.n 80036d2 + 80036ca: 2b08 cmp r3, #8 + 80036cc: d003 beq.n 80036d6 + 80036ce: 4810 ldr r0, [pc, #64] ; (8003710 ) + 80036d0: e000 b.n 80036d4 + 80036d2: 4810 ldr r0, [pc, #64] ; (8003714 ) + 80036d4: bd08 pop {r3, pc} + 80036d6: 684a ldr r2, [r1, #4] + 80036d8: 684b ldr r3, [r1, #4] + 80036da: 6849 ldr r1, [r1, #4] + 80036dc: f413 0380 ands.w r3, r3, #4194304 ; 0x400000 + 80036e0: bf14 ite ne + 80036e2: 480c ldrne r0, [pc, #48] ; (8003714 ) + 80036e4: 480a ldreq r0, [pc, #40] ; (8003710 ) + 80036e6: f3c1 1188 ubfx r1, r1, #6, #9 + 80036ea: bf18 it ne + 80036ec: 2300 movne r3, #0 + 80036ee: f002 023f and.w r2, r2, #63 ; 0x3f + 80036f2: fba1 0100 umull r0, r1, r1, r0 + 80036f6: f7fd facf bl 8000c98 <__aeabi_uldivmod> + 80036fa: 4b04 ldr r3, [pc, #16] ; (800370c ) + 80036fc: 685b ldr r3, [r3, #4] + 80036fe: f3c3 4301 ubfx r3, r3, #16, #2 + 8003702: 3301 adds r3, #1 + 8003704: 005b lsls r3, r3, #1 + 8003706: fbb0 f0f3 udiv r0, r0, r3 + 800370a: e7e3 b.n 80036d4 + 800370c: 40023800 .word 0x40023800 + 8003710: 00f42400 .word 0x00f42400 + 8003714: 007a1200 .word 0x007a1200 + +08003718 : + 8003718: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 800371c: 460d mov r5, r1 + 800371e: 4604 mov r4, r0 + 8003720: b910 cbnz r0, 8003728 + 8003722: 2001 movs r0, #1 + 8003724: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 8003728: 4b43 ldr r3, [pc, #268] ; (8003838 ) + 800372a: 681a ldr r2, [r3, #0] + 800372c: f002 020f and.w r2, r2, #15 + 8003730: 428a cmp r2, r1 + 8003732: d328 bcc.n 8003786 + 8003734: 6821 ldr r1, [r4, #0] + 8003736: 078f lsls r7, r1, #30 + 8003738: d42d bmi.n 8003796 + 800373a: 07c8 lsls r0, r1, #31 + 800373c: d440 bmi.n 80037c0 + 800373e: 4b3e ldr r3, [pc, #248] ; (8003838 ) + 8003740: 681a ldr r2, [r3, #0] + 8003742: f002 020f and.w r2, r2, #15 + 8003746: 42aa cmp r2, r5 + 8003748: d865 bhi.n 8003816 + 800374a: 6822 ldr r2, [r4, #0] + 800374c: 0751 lsls r1, r2, #29 + 800374e: d46b bmi.n 8003828 + 8003750: 0713 lsls r3, r2, #28 + 8003752: d507 bpl.n 8003764 + 8003754: 4a39 ldr r2, [pc, #228] ; (800383c ) + 8003756: 6921 ldr r1, [r4, #16] + 8003758: 6893 ldr r3, [r2, #8] + 800375a: f423 4360 bic.w r3, r3, #57344 ; 0xe000 + 800375e: ea43 03c1 orr.w r3, r3, r1, lsl #3 + 8003762: 6093 str r3, [r2, #8] + 8003764: f7ff ffaa bl 80036bc + 8003768: 4b34 ldr r3, [pc, #208] ; (800383c ) + 800376a: 4a35 ldr r2, [pc, #212] ; (8003840 ) + 800376c: 689b ldr r3, [r3, #8] + 800376e: f3c3 1303 ubfx r3, r3, #4, #4 + 8003772: 5cd3 ldrb r3, [r2, r3] + 8003774: 40d8 lsrs r0, r3 + 8003776: 4b33 ldr r3, [pc, #204] ; (8003844 ) + 8003778: 6018 str r0, [r3, #0] + 800377a: 4b33 ldr r3, [pc, #204] ; (8003848 ) + 800377c: 6818 ldr r0, [r3, #0] + 800377e: f7fe f9eb bl 8001b58 + 8003782: 2000 movs r0, #0 + 8003784: e7ce b.n 8003724 + 8003786: b2ca uxtb r2, r1 + 8003788: 701a strb r2, [r3, #0] + 800378a: 681b ldr r3, [r3, #0] + 800378c: f003 030f and.w r3, r3, #15 + 8003790: 428b cmp r3, r1 + 8003792: d1c6 bne.n 8003722 + 8003794: e7ce b.n 8003734 + 8003796: 4b29 ldr r3, [pc, #164] ; (800383c ) + 8003798: f011 0f04 tst.w r1, #4 + 800379c: bf1e ittt ne + 800379e: 689a ldrne r2, [r3, #8] + 80037a0: f442 52e0 orrne.w r2, r2, #7168 ; 0x1c00 + 80037a4: 609a strne r2, [r3, #8] + 80037a6: 070e lsls r6, r1, #28 + 80037a8: bf42 ittt mi + 80037aa: 689a ldrmi r2, [r3, #8] + 80037ac: f442 4260 orrmi.w r2, r2, #57344 ; 0xe000 + 80037b0: 609a strmi r2, [r3, #8] + 80037b2: 689a ldr r2, [r3, #8] + 80037b4: 68a0 ldr r0, [r4, #8] + 80037b6: f022 02f0 bic.w r2, r2, #240 ; 0xf0 + 80037ba: 4302 orrs r2, r0 + 80037bc: 609a str r2, [r3, #8] + 80037be: e7bc b.n 800373a + 80037c0: 6862 ldr r2, [r4, #4] + 80037c2: 4b1e ldr r3, [pc, #120] ; (800383c ) + 80037c4: 2a01 cmp r2, #1 + 80037c6: d11c bne.n 8003802 + 80037c8: 681b ldr r3, [r3, #0] + 80037ca: f413 3f00 tst.w r3, #131072 ; 0x20000 + 80037ce: d0a8 beq.n 8003722 + 80037d0: 4e1a ldr r6, [pc, #104] ; (800383c ) + 80037d2: 68b3 ldr r3, [r6, #8] + 80037d4: f023 0303 bic.w r3, r3, #3 + 80037d8: 4313 orrs r3, r2 + 80037da: 60b3 str r3, [r6, #8] + 80037dc: f7fe fa06 bl 8001bec + 80037e0: f241 3888 movw r8, #5000 ; 0x1388 + 80037e4: 4607 mov r7, r0 + 80037e6: 68b3 ldr r3, [r6, #8] + 80037e8: 6862 ldr r2, [r4, #4] + 80037ea: f003 030c and.w r3, r3, #12 + 80037ee: ebb3 0f82 cmp.w r3, r2, lsl #2 + 80037f2: d0a4 beq.n 800373e + 80037f4: f7fe f9fa bl 8001bec + 80037f8: 1bc0 subs r0, r0, r7 + 80037fa: 4540 cmp r0, r8 + 80037fc: d9f3 bls.n 80037e6 + 80037fe: 2003 movs r0, #3 + 8003800: e790 b.n 8003724 + 8003802: 1e91 subs r1, r2, #2 + 8003804: 2901 cmp r1, #1 + 8003806: 681b ldr r3, [r3, #0] + 8003808: d802 bhi.n 8003810 + 800380a: f013 7f00 tst.w r3, #33554432 ; 0x2000000 + 800380e: e7de b.n 80037ce + 8003810: f013 0f02 tst.w r3, #2 + 8003814: e7db b.n 80037ce + 8003816: b2ea uxtb r2, r5 + 8003818: 701a strb r2, [r3, #0] + 800381a: 681b ldr r3, [r3, #0] + 800381c: f003 030f and.w r3, r3, #15 + 8003820: 42ab cmp r3, r5 + 8003822: f47f af7e bne.w 8003722 + 8003826: e790 b.n 800374a + 8003828: 4904 ldr r1, [pc, #16] ; (800383c ) + 800382a: 68e0 ldr r0, [r4, #12] + 800382c: 688b ldr r3, [r1, #8] + 800382e: f423 53e0 bic.w r3, r3, #7168 ; 0x1c00 + 8003832: 4303 orrs r3, r0 + 8003834: 608b str r3, [r1, #8] + 8003836: e78b b.n 8003750 + 8003838: 40023c00 .word 0x40023c00 + 800383c: 40023800 .word 0x40023800 + 8003840: 08009a12 .word 0x08009a12 + 8003844: 20000000 .word 0x20000000 + 8003848: 20000008 .word 0x20000008 + +0800384c : + 800384c: 4b04 ldr r3, [pc, #16] ; (8003860 ) + 800384e: 4a05 ldr r2, [pc, #20] ; (8003864 ) + 8003850: 689b ldr r3, [r3, #8] + 8003852: f3c3 2382 ubfx r3, r3, #10, #3 + 8003856: 5cd3 ldrb r3, [r2, r3] + 8003858: 4a03 ldr r2, [pc, #12] ; (8003868 ) + 800385a: 6810 ldr r0, [r2, #0] + 800385c: 40d8 lsrs r0, r3 + 800385e: 4770 bx lr + 8003860: 40023800 .word 0x40023800 + 8003864: 08009a22 .word 0x08009a22 + 8003868: 20000000 .word 0x20000000 + +0800386c : + 800386c: 4b04 ldr r3, [pc, #16] ; (8003880 ) + 800386e: 4a05 ldr r2, [pc, #20] ; (8003884 ) + 8003870: 689b ldr r3, [r3, #8] + 8003872: f3c3 3342 ubfx r3, r3, #13, #3 + 8003876: 5cd3 ldrb r3, [r2, r3] + 8003878: 4a03 ldr r2, [pc, #12] ; (8003888 ) + 800387a: 6810 ldr r0, [r2, #0] + 800387c: 40d8 lsrs r0, r3 + 800387e: 4770 bx lr + 8003880: 40023800 .word 0x40023800 + 8003884: 08009a22 .word 0x08009a22 + 8003888: 20000000 .word 0x20000000 + +0800388c : + 800388c: 6803 ldr r3, [r0, #0] + 800388e: f013 0f05 tst.w r3, #5 + 8003892: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} + 8003894: 4604 mov r4, r0 + 8003896: d13c bne.n 8003912 + 8003898: 6823 ldr r3, [r4, #0] + 800389a: 079a lsls r2, r3, #30 + 800389c: d530 bpl.n 8003900 + 800389e: 2300 movs r3, #0 + 80038a0: 9301 str r3, [sp, #4] + 80038a2: 4b44 ldr r3, [pc, #272] ; (80039b4 ) + 80038a4: 4d44 ldr r5, [pc, #272] ; (80039b8 ) + 80038a6: 6c1a ldr r2, [r3, #64] ; 0x40 + 80038a8: f042 5280 orr.w r2, r2, #268435456 ; 0x10000000 + 80038ac: 641a str r2, [r3, #64] ; 0x40 + 80038ae: 6c1b ldr r3, [r3, #64] ; 0x40 + 80038b0: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 80038b4: 9301 str r3, [sp, #4] + 80038b6: 9b01 ldr r3, [sp, #4] + 80038b8: 682b ldr r3, [r5, #0] + 80038ba: f443 7380 orr.w r3, r3, #256 ; 0x100 + 80038be: 602b str r3, [r5, #0] + 80038c0: f7fe f994 bl 8001bec + 80038c4: 4606 mov r6, r0 + 80038c6: 682b ldr r3, [r5, #0] + 80038c8: 05d9 lsls r1, r3, #23 + 80038ca: d54a bpl.n 8003962 + 80038cc: 4d39 ldr r5, [pc, #228] ; (80039b4 ) + 80038ce: 6f2b ldr r3, [r5, #112] ; 0x70 + 80038d0: f413 7340 ands.w r3, r3, #768 ; 0x300 + 80038d4: d14b bne.n 800396e + 80038d6: 68e3 ldr r3, [r4, #12] + 80038d8: f403 7240 and.w r2, r3, #768 ; 0x300 + 80038dc: f5b2 7f40 cmp.w r2, #768 ; 0x300 + 80038e0: 4a34 ldr r2, [pc, #208] ; (80039b4 ) + 80038e2: d163 bne.n 80039ac + 80038e4: 6891 ldr r1, [r2, #8] + 80038e6: f023 4070 bic.w r0, r3, #4026531840 ; 0xf0000000 + 80038ea: f421 11f8 bic.w r1, r1, #2031616 ; 0x1f0000 + 80038ee: f420 7040 bic.w r0, r0, #768 ; 0x300 + 80038f2: 4301 orrs r1, r0 + 80038f4: 6091 str r1, [r2, #8] + 80038f6: 6f11 ldr r1, [r2, #112] ; 0x70 + 80038f8: f3c3 030b ubfx r3, r3, #0, #12 + 80038fc: 430b orrs r3, r1 + 80038fe: 6713 str r3, [r2, #112] ; 0x70 + 8003900: 6820 ldr r0, [r4, #0] + 8003902: f010 0008 ands.w r0, r0, #8 + 8003906: bf1f itttt ne + 8003908: 4b2c ldrne r3, [pc, #176] ; (80039bc ) + 800390a: 7c22 ldrbne r2, [r4, #16] + 800390c: 601a strne r2, [r3, #0] + 800390e: 2000 movne r0, #0 + 8003910: e025 b.n 800395e + 8003912: 4d2b ldr r5, [pc, #172] ; (80039c0 ) + 8003914: 4e27 ldr r6, [pc, #156] ; (80039b4 ) + 8003916: 2300 movs r3, #0 + 8003918: 602b str r3, [r5, #0] + 800391a: f7fe f967 bl 8001bec + 800391e: 4607 mov r7, r0 + 8003920: 6833 ldr r3, [r6, #0] + 8003922: 011b lsls r3, r3, #4 + 8003924: d415 bmi.n 8003952 + 8003926: e9d4 2301 ldrd r2, r3, [r4, #4] + 800392a: 071b lsls r3, r3, #28 + 800392c: ea43 1382 orr.w r3, r3, r2, lsl #6 + 8003930: f8c6 3084 str.w r3, [r6, #132] ; 0x84 + 8003934: 2301 movs r3, #1 + 8003936: 602b str r3, [r5, #0] + 8003938: f7fe f958 bl 8001bec + 800393c: 4d1d ldr r5, [pc, #116] ; (80039b4 ) + 800393e: 4606 mov r6, r0 + 8003940: 682b ldr r3, [r5, #0] + 8003942: 0118 lsls r0, r3, #4 + 8003944: d4a8 bmi.n 8003898 + 8003946: f7fe f951 bl 8001bec + 800394a: 1b80 subs r0, r0, r6 + 800394c: 2802 cmp r0, #2 + 800394e: d9f7 bls.n 8003940 + 8003950: e004 b.n 800395c + 8003952: f7fe f94b bl 8001bec + 8003956: 1bc0 subs r0, r0, r7 + 8003958: 2802 cmp r0, #2 + 800395a: d9e1 bls.n 8003920 + 800395c: 2003 movs r0, #3 + 800395e: b003 add sp, #12 + 8003960: bdf0 pop {r4, r5, r6, r7, pc} + 8003962: f7fe f943 bl 8001bec + 8003966: 1b80 subs r0, r0, r6 + 8003968: 2802 cmp r0, #2 + 800396a: d9ac bls.n 80038c6 + 800396c: e7f6 b.n 800395c + 800396e: 68e2 ldr r2, [r4, #12] + 8003970: f402 7240 and.w r2, r2, #768 ; 0x300 + 8003974: 4293 cmp r3, r2 + 8003976: d0ae beq.n 80038d6 + 8003978: 6f2b ldr r3, [r5, #112] ; 0x70 + 800397a: 4a12 ldr r2, [pc, #72] ; (80039c4 ) + 800397c: 2101 movs r1, #1 + 800397e: 6011 str r1, [r2, #0] + 8003980: f423 7340 bic.w r3, r3, #768 ; 0x300 + 8003984: 2100 movs r1, #0 + 8003986: 6011 str r1, [r2, #0] + 8003988: 672b str r3, [r5, #112] ; 0x70 + 800398a: 6f2b ldr r3, [r5, #112] ; 0x70 + 800398c: 07da lsls r2, r3, #31 + 800398e: d5a2 bpl.n 80038d6 + 8003990: f7fe f92c bl 8001bec + 8003994: f241 3788 movw r7, #5000 ; 0x1388 + 8003998: 4606 mov r6, r0 + 800399a: 6f2b ldr r3, [r5, #112] ; 0x70 + 800399c: 079b lsls r3, r3, #30 + 800399e: d49a bmi.n 80038d6 + 80039a0: f7fe f924 bl 8001bec + 80039a4: 1b80 subs r0, r0, r6 + 80039a6: 42b8 cmp r0, r7 + 80039a8: d9f7 bls.n 800399a + 80039aa: e7d7 b.n 800395c + 80039ac: 6891 ldr r1, [r2, #8] + 80039ae: f421 11f8 bic.w r1, r1, #2031616 ; 0x1f0000 + 80039b2: e79f b.n 80038f4 + 80039b4: 40023800 .word 0x40023800 + 80039b8: 40007000 .word 0x40007000 + 80039bc: 424711e0 .word 0x424711e0 + 80039c0: 42470068 .word 0x42470068 + 80039c4: 42470e40 .word 0x42470e40 + +080039c8 : + 80039c8: 2801 cmp r0, #1 + 80039ca: d120 bne.n 8003a0e + 80039cc: 4b11 ldr r3, [pc, #68] ; (8003a14 ) + 80039ce: 689a ldr r2, [r3, #8] + 80039d0: f412 0200 ands.w r2, r2, #8388608 ; 0x800000 + 80039d4: d004 beq.n 80039e0 + 80039d6: 2a01 cmp r2, #1 + 80039d8: 480f ldr r0, [pc, #60] ; (8003a18 ) + 80039da: bf18 it ne + 80039dc: 2000 movne r0, #0 + 80039de: 4770 bx lr + 80039e0: 685a ldr r2, [r3, #4] + 80039e2: 490c ldr r1, [pc, #48] ; (8003a14 ) + 80039e4: 6858 ldr r0, [r3, #4] + 80039e6: 0253 lsls r3, r2, #9 + 80039e8: f8d1 2084 ldr.w r2, [r1, #132] ; 0x84 + 80039ec: bf4c ite mi + 80039ee: 4b0b ldrmi r3, [pc, #44] ; (8003a1c ) + 80039f0: 4b0b ldrpl r3, [pc, #44] ; (8003a20 ) + 80039f2: f000 003f and.w r0, r0, #63 ; 0x3f + 80039f6: fbb3 f3f0 udiv r3, r3, r0 + 80039fa: f8d1 0084 ldr.w r0, [r1, #132] ; 0x84 + 80039fe: f3c2 1288 ubfx r2, r2, #6, #9 + 8003a02: 4353 muls r3, r2 + 8003a04: f3c0 7002 ubfx r0, r0, #28, #3 + 8003a08: fbb3 f0f0 udiv r0, r3, r0 + 8003a0c: 4770 bx lr + 8003a0e: 2000 movs r0, #0 + 8003a10: 4770 bx lr + 8003a12: bf00 nop + 8003a14: 40023800 .word 0x40023800 + 8003a18: 00bb8000 .word 0x00bb8000 + 8003a1c: 007a1200 .word 0x007a1200 + 8003a20: 00f42400 .word 0x00f42400 + +08003a24 : + 8003a24: b510 push {r4, lr} + 8003a26: 4604 mov r4, r0 + 8003a28: 2800 cmp r0, #0 + 8003a2a: d036 beq.n 8003a9a + 8003a2c: 2300 movs r3, #0 + 8003a2e: 6283 str r3, [r0, #40] ; 0x28 + 8003a30: f890 3051 ldrb.w r3, [r0, #81] ; 0x51 + 8003a34: f003 02ff and.w r2, r3, #255 ; 0xff + 8003a38: b91b cbnz r3, 8003a42 + 8003a3a: f880 2050 strb.w r2, [r0, #80] ; 0x50 + 8003a3e: f7fd fdf3 bl 8001628 + 8003a42: 6821 ldr r1, [r4, #0] + 8003a44: 69a2 ldr r2, [r4, #24] + 8003a46: 2302 movs r3, #2 + 8003a48: f884 3051 strb.w r3, [r4, #81] ; 0x51 + 8003a4c: 680b ldr r3, [r1, #0] + 8003a4e: f023 0340 bic.w r3, r3, #64 ; 0x40 + 8003a52: 600b str r3, [r1, #0] + 8003a54: e9d4 3001 ldrd r3, r0, [r4, #4] + 8003a58: 4303 orrs r3, r0 + 8003a5a: 68e0 ldr r0, [r4, #12] + 8003a5c: 4303 orrs r3, r0 + 8003a5e: 6920 ldr r0, [r4, #16] + 8003a60: 4303 orrs r3, r0 + 8003a62: 6960 ldr r0, [r4, #20] + 8003a64: 4303 orrs r3, r0 + 8003a66: 69e0 ldr r0, [r4, #28] + 8003a68: 4303 orrs r3, r0 + 8003a6a: 6a20 ldr r0, [r4, #32] + 8003a6c: 4303 orrs r3, r0 + 8003a6e: 6aa0 ldr r0, [r4, #40] ; 0x28 + 8003a70: 4303 orrs r3, r0 + 8003a72: f402 7000 and.w r0, r2, #512 ; 0x200 + 8003a76: 4303 orrs r3, r0 + 8003a78: 600b str r3, [r1, #0] + 8003a7a: 0c12 lsrs r2, r2, #16 + 8003a7c: 6a63 ldr r3, [r4, #36] ; 0x24 + 8003a7e: f002 0204 and.w r2, r2, #4 + 8003a82: 431a orrs r2, r3 + 8003a84: 604a str r2, [r1, #4] + 8003a86: 69cb ldr r3, [r1, #28] + 8003a88: f423 6300 bic.w r3, r3, #2048 ; 0x800 + 8003a8c: 61cb str r3, [r1, #28] + 8003a8e: 2000 movs r0, #0 + 8003a90: 2301 movs r3, #1 + 8003a92: 6560 str r0, [r4, #84] ; 0x54 + 8003a94: f884 3051 strb.w r3, [r4, #81] ; 0x51 + 8003a98: bd10 pop {r4, pc} + 8003a9a: 2001 movs r0, #1 + 8003a9c: e7fc b.n 8003a98 + ... + +08003aa0 : + 8003aa0: 6803 ldr r3, [r0, #0] + 8003aa2: 68c1 ldr r1, [r0, #12] + 8003aa4: 691a ldr r2, [r3, #16] + 8003aa6: b570 push {r4, r5, r6, lr} + 8003aa8: f422 5240 bic.w r2, r2, #12288 ; 0x3000 + 8003aac: 4604 mov r4, r0 + 8003aae: 430a orrs r2, r1 + 8003ab0: 611a str r2, [r3, #16] + 8003ab2: 6925 ldr r5, [r4, #16] + 8003ab4: 68a2 ldr r2, [r4, #8] + 8003ab6: 68d9 ldr r1, [r3, #12] + 8003ab8: 69c0 ldr r0, [r0, #28] + 8003aba: 432a orrs r2, r5 + 8003abc: 6965 ldr r5, [r4, #20] + 8003abe: f421 4116 bic.w r1, r1, #38400 ; 0x9600 + 8003ac2: 432a orrs r2, r5 + 8003ac4: f021 010c bic.w r1, r1, #12 + 8003ac8: 4302 orrs r2, r0 + 8003aca: 430a orrs r2, r1 + 8003acc: 60da str r2, [r3, #12] + 8003ace: 695a ldr r2, [r3, #20] + 8003ad0: 69a1 ldr r1, [r4, #24] + 8003ad2: f422 7240 bic.w r2, r2, #768 ; 0x300 + 8003ad6: 430a orrs r2, r1 + 8003ad8: f5b0 4f00 cmp.w r0, #32768 ; 0x8000 + 8003adc: 615a str r2, [r3, #20] + 8003ade: 4a26 ldr r2, [pc, #152] ; (8003b78 ) + 8003ae0: d129 bne.n 8003b36 + 8003ae2: 4293 cmp r3, r2 + 8003ae4: d003 beq.n 8003aee + 8003ae6: f502 6280 add.w r2, r2, #1024 ; 0x400 + 8003aea: 4293 cmp r3, r2 + 8003aec: d120 bne.n 8003b30 + 8003aee: f7ff febd bl 800386c + 8003af2: 6862 ldr r2, [r4, #4] + 8003af4: 2600 movs r6, #0 + 8003af6: 1892 adds r2, r2, r2 + 8003af8: f04f 0119 mov.w r1, #25 + 8003afc: eb46 0306 adc.w r3, r6, r6 + 8003b00: fba0 0101 umull r0, r1, r0, r1 + 8003b04: f7fd f8c8 bl 8000c98 <__aeabi_uldivmod> + 8003b08: 2164 movs r1, #100 ; 0x64 + 8003b0a: fbb0 f5f1 udiv r5, r0, r1 + 8003b0e: fb01 0315 mls r3, r1, r5, r0 + 8003b12: 00db lsls r3, r3, #3 + 8003b14: 3332 adds r3, #50 ; 0x32 + 8003b16: fbb3 f3f1 udiv r3, r3, r1 + 8003b1a: f003 0207 and.w r2, r3, #7 + 8003b1e: 005b lsls r3, r3, #1 + 8003b20: 6821 ldr r1, [r4, #0] + 8003b22: eb02 1205 add.w r2, r2, r5, lsl #4 + 8003b26: f403 73f8 and.w r3, r3, #496 ; 0x1f0 + 8003b2a: 4413 add r3, r2 + 8003b2c: 608b str r3, [r1, #8] + 8003b2e: bd70 pop {r4, r5, r6, pc} + 8003b30: f7ff fe8c bl 800384c + 8003b34: e7dd b.n 8003af2 + 8003b36: 4293 cmp r3, r2 + 8003b38: d002 beq.n 8003b40 + 8003b3a: 4a10 ldr r2, [pc, #64] ; (8003b7c ) + 8003b3c: 4293 cmp r3, r2 + 8003b3e: d117 bne.n 8003b70 + 8003b40: f7ff fe94 bl 800386c + 8003b44: 6863 ldr r3, [r4, #4] + 8003b46: 2119 movs r1, #25 + 8003b48: 009a lsls r2, r3, #2 + 8003b4a: fba0 0101 umull r0, r1, r0, r1 + 8003b4e: 0f9b lsrs r3, r3, #30 + 8003b50: f7fd f8a2 bl 8000c98 <__aeabi_uldivmod> + 8003b54: 2264 movs r2, #100 ; 0x64 + 8003b56: fbb0 f1f2 udiv r1, r0, r2 + 8003b5a: fb02 0311 mls r3, r2, r1, r0 + 8003b5e: 6824 ldr r4, [r4, #0] + 8003b60: 011b lsls r3, r3, #4 + 8003b62: 3332 adds r3, #50 ; 0x32 + 8003b64: fbb3 f3f2 udiv r3, r3, r2 + 8003b68: eb03 1301 add.w r3, r3, r1, lsl #4 + 8003b6c: 60a3 str r3, [r4, #8] + 8003b6e: e7de b.n 8003b2e + 8003b70: f7ff fe6c bl 800384c + 8003b74: e7e6 b.n 8003b44 + 8003b76: bf00 nop + 8003b78: 40011000 .word 0x40011000 + 8003b7c: 40011400 .word 0x40011400 + +08003b80 : + 8003b80: b5f8 push {r3, r4, r5, r6, r7, lr} + 8003b82: 4604 mov r4, r0 + 8003b84: 460e mov r6, r1 + 8003b86: 4617 mov r7, r2 + 8003b88: 461d mov r5, r3 + 8003b8a: 6821 ldr r1, [r4, #0] + 8003b8c: 680b ldr r3, [r1, #0] + 8003b8e: ea36 0303 bics.w r3, r6, r3 + 8003b92: d101 bne.n 8003b98 + 8003b94: 2000 movs r0, #0 + 8003b96: e014 b.n 8003bc2 + 8003b98: 1c6b adds r3, r5, #1 + 8003b9a: d0f7 beq.n 8003b8c + 8003b9c: b995 cbnz r5, 8003bc4 + 8003b9e: 6823 ldr r3, [r4, #0] + 8003ba0: 68da ldr r2, [r3, #12] + 8003ba2: f422 72d0 bic.w r2, r2, #416 ; 0x1a0 + 8003ba6: 60da str r2, [r3, #12] + 8003ba8: 695a ldr r2, [r3, #20] + 8003baa: f022 0201 bic.w r2, r2, #1 + 8003bae: 615a str r2, [r3, #20] + 8003bb0: 2320 movs r3, #32 + 8003bb2: f884 3039 strb.w r3, [r4, #57] ; 0x39 + 8003bb6: f884 303a strb.w r3, [r4, #58] ; 0x3a + 8003bba: 2300 movs r3, #0 + 8003bbc: f884 3038 strb.w r3, [r4, #56] ; 0x38 + 8003bc0: 2003 movs r0, #3 + 8003bc2: bdf8 pop {r3, r4, r5, r6, r7, pc} + 8003bc4: f7fe f812 bl 8001bec + 8003bc8: 1bc0 subs r0, r0, r7 + 8003bca: 4285 cmp r5, r0 + 8003bcc: d2dd bcs.n 8003b8a + 8003bce: e7e6 b.n 8003b9e + +08003bd0 : + 8003bd0: b510 push {r4, lr} + 8003bd2: 4604 mov r4, r0 + 8003bd4: b340 cbz r0, 8003c28 + 8003bd6: f890 3039 ldrb.w r3, [r0, #57] ; 0x39 + 8003bda: f003 02ff and.w r2, r3, #255 ; 0xff + 8003bde: b91b cbnz r3, 8003be8 + 8003be0: f880 2038 strb.w r2, [r0, #56] ; 0x38 + 8003be4: f7fd fd56 bl 8001694 + 8003be8: 6822 ldr r2, [r4, #0] + 8003bea: 2324 movs r3, #36 ; 0x24 + 8003bec: f884 3039 strb.w r3, [r4, #57] ; 0x39 + 8003bf0: 68d3 ldr r3, [r2, #12] + 8003bf2: f423 5300 bic.w r3, r3, #8192 ; 0x2000 + 8003bf6: 60d3 str r3, [r2, #12] + 8003bf8: 4620 mov r0, r4 + 8003bfa: f7ff ff51 bl 8003aa0 + 8003bfe: 6823 ldr r3, [r4, #0] + 8003c00: 691a ldr r2, [r3, #16] + 8003c02: f422 4290 bic.w r2, r2, #18432 ; 0x4800 + 8003c06: 611a str r2, [r3, #16] + 8003c08: 695a ldr r2, [r3, #20] + 8003c0a: f022 022a bic.w r2, r2, #42 ; 0x2a + 8003c0e: 615a str r2, [r3, #20] + 8003c10: 68da ldr r2, [r3, #12] + 8003c12: f442 5200 orr.w r2, r2, #8192 ; 0x2000 + 8003c16: 60da str r2, [r3, #12] + 8003c18: 2000 movs r0, #0 + 8003c1a: 2320 movs r3, #32 + 8003c1c: 63e0 str r0, [r4, #60] ; 0x3c + 8003c1e: f884 3039 strb.w r3, [r4, #57] ; 0x39 + 8003c22: f884 303a strb.w r3, [r4, #58] ; 0x3a + 8003c26: bd10 pop {r4, pc} + 8003c28: 2001 movs r0, #1 + 8003c2a: e7fc b.n 8003c26 + +08003c2c : + 8003c2c: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} + 8003c30: 461f mov r7, r3 + 8003c32: f890 3039 ldrb.w r3, [r0, #57] ; 0x39 + 8003c36: 2b20 cmp r3, #32 + 8003c38: 4604 mov r4, r0 + 8003c3a: 460d mov r5, r1 + 8003c3c: 4690 mov r8, r2 + 8003c3e: d14f bne.n 8003ce0 + 8003c40: 2900 cmp r1, #0 + 8003c42: d04b beq.n 8003cdc + 8003c44: 2a00 cmp r2, #0 + 8003c46: d049 beq.n 8003cdc + 8003c48: f890 3038 ldrb.w r3, [r0, #56] ; 0x38 + 8003c4c: 2b01 cmp r3, #1 + 8003c4e: d047 beq.n 8003ce0 + 8003c50: 2301 movs r3, #1 + 8003c52: f880 3038 strb.w r3, [r0, #56] ; 0x38 + 8003c56: f04f 0900 mov.w r9, #0 + 8003c5a: 2321 movs r3, #33 ; 0x21 + 8003c5c: f8c0 903c str.w r9, [r0, #60] ; 0x3c + 8003c60: f880 3039 strb.w r3, [r0, #57] ; 0x39 + 8003c64: f7fd ffc2 bl 8001bec + 8003c68: f8a4 8024 strh.w r8, [r4, #36] ; 0x24 + 8003c6c: 4606 mov r6, r0 + 8003c6e: f8a4 8026 strh.w r8, [r4, #38] ; 0x26 + 8003c72: f884 9038 strb.w r9, [r4, #56] ; 0x38 + 8003c76: 8ce3 ldrh r3, [r4, #38] ; 0x26 + 8003c78: b29b uxth r3, r3 + 8003c7a: b953 cbnz r3, 8003c92 + 8003c7c: 463b mov r3, r7 + 8003c7e: 4632 mov r2, r6 + 8003c80: 2140 movs r1, #64 ; 0x40 + 8003c82: 4620 mov r0, r4 + 8003c84: f7ff ff7c bl 8003b80 + 8003c88: b998 cbnz r0, 8003cb2 + 8003c8a: 2320 movs r3, #32 + 8003c8c: f884 3039 strb.w r3, [r4, #57] ; 0x39 + 8003c90: e010 b.n 8003cb4 + 8003c92: 8ce3 ldrh r3, [r4, #38] ; 0x26 + 8003c94: 3b01 subs r3, #1 + 8003c96: b29b uxth r3, r3 + 8003c98: 84e3 strh r3, [r4, #38] ; 0x26 + 8003c9a: 68a3 ldr r3, [r4, #8] + 8003c9c: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 + 8003ca0: 4632 mov r2, r6 + 8003ca2: 463b mov r3, r7 + 8003ca4: f04f 0180 mov.w r1, #128 ; 0x80 + 8003ca8: 4620 mov r0, r4 + 8003caa: d10e bne.n 8003cca + 8003cac: f7ff ff68 bl 8003b80 + 8003cb0: b110 cbz r0, 8003cb8 + 8003cb2: 2003 movs r0, #3 + 8003cb4: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} + 8003cb8: 882b ldrh r3, [r5, #0] + 8003cba: 6822 ldr r2, [r4, #0] + 8003cbc: f3c3 0308 ubfx r3, r3, #0, #9 + 8003cc0: 6053 str r3, [r2, #4] + 8003cc2: 6923 ldr r3, [r4, #16] + 8003cc4: b943 cbnz r3, 8003cd8 + 8003cc6: 3502 adds r5, #2 + 8003cc8: e7d5 b.n 8003c76 + 8003cca: f7ff ff59 bl 8003b80 + 8003cce: 2800 cmp r0, #0 + 8003cd0: d1ef bne.n 8003cb2 + 8003cd2: 6823 ldr r3, [r4, #0] + 8003cd4: 782a ldrb r2, [r5, #0] + 8003cd6: 605a str r2, [r3, #4] + 8003cd8: 3501 adds r5, #1 + 8003cda: e7cc b.n 8003c76 + 8003cdc: 2001 movs r0, #1 + 8003cde: e7e9 b.n 8003cb4 + 8003ce0: 2002 movs r0, #2 + 8003ce2: e7e7 b.n 8003cb4 + +08003ce4 : + 8003ce4: 4b0a ldr r3, [pc, #40] ; (8003d10 ) + 8003ce6: 3b01 subs r3, #1 + 8003ce8: d00f beq.n 8003d0a + 8003cea: 6902 ldr r2, [r0, #16] + 8003cec: 2a00 cmp r2, #0 + 8003cee: dafa bge.n 8003ce6 + 8003cf0: 6903 ldr r3, [r0, #16] + 8003cf2: 4a07 ldr r2, [pc, #28] ; (8003d10 ) + 8003cf4: f043 0301 orr.w r3, r3, #1 + 8003cf8: 6103 str r3, [r0, #16] + 8003cfa: 3a01 subs r2, #1 + 8003cfc: d005 beq.n 8003d0a + 8003cfe: 6903 ldr r3, [r0, #16] + 8003d00: f013 0301 ands.w r3, r3, #1 + 8003d04: d1f9 bne.n 8003cfa + 8003d06: 4618 mov r0, r3 + 8003d08: 4770 bx lr + 8003d0a: 2003 movs r0, #3 + 8003d0c: 4770 bx lr + 8003d0e: bf00 nop + 8003d10: 00030d41 .word 0x00030d41 + +08003d14 : + 8003d14: b084 sub sp, #16 + 8003d16: b538 push {r3, r4, r5, lr} + 8003d18: ad05 add r5, sp, #20 + 8003d1a: e885 000e stmia.w r5, {r1, r2, r3} + 8003d1e: 9b0a ldr r3, [sp, #40] ; 0x28 + 8003d20: 2b01 cmp r3, #1 + 8003d22: 4604 mov r4, r0 + 8003d24: d125 bne.n 8003d72 + 8003d26: 6b83 ldr r3, [r0, #56] ; 0x38 + 8003d28: f423 3380 bic.w r3, r3, #65536 ; 0x10000 + 8003d2c: 6383 str r3, [r0, #56] ; 0x38 + 8003d2e: 68c3 ldr r3, [r0, #12] + 8003d30: f423 0384 bic.w r3, r3, #4325376 ; 0x420000 + 8003d34: f023 0340 bic.w r3, r3, #64 ; 0x40 + 8003d38: 60c3 str r3, [r0, #12] + 8003d3a: 68c3 ldr r3, [r0, #12] + 8003d3c: f423 1340 bic.w r3, r3, #3145728 ; 0x300000 + 8003d40: 60c3 str r3, [r0, #12] + 8003d42: 9b11 ldr r3, [sp, #68] ; 0x44 + 8003d44: 2b01 cmp r3, #1 + 8003d46: bf02 ittt eq + 8003d48: 68c3 ldreq r3, [r0, #12] + 8003d4a: f443 1380 orreq.w r3, r3, #1048576 ; 0x100000 + 8003d4e: 60c3 streq r3, [r0, #12] + 8003d50: f7ff ffc8 bl 8003ce4 + 8003d54: 9b08 ldr r3, [sp, #32] + 8003d56: 2b01 cmp r3, #1 + 8003d58: d107 bne.n 8003d6a + 8003d5a: 68a3 ldr r3, [r4, #8] + 8003d5c: f043 0306 orr.w r3, r3, #6 + 8003d60: 60a3 str r3, [r4, #8] + 8003d62: 68a3 ldr r3, [r4, #8] + 8003d64: f043 0320 orr.w r3, r3, #32 + 8003d68: 60a3 str r3, [r4, #8] + 8003d6a: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} + 8003d6e: b004 add sp, #16 + 8003d70: 4770 bx lr + 8003d72: 68c3 ldr r3, [r0, #12] + 8003d74: f043 0340 orr.w r3, r3, #64 ; 0x40 + 8003d78: 60c3 str r3, [r0, #12] + 8003d7a: f7ff ffb3 bl 8003ce4 + 8003d7e: 9b0e ldr r3, [sp, #56] ; 0x38 + 8003d80: b923 cbnz r3, 8003d8c + 8003d82: 6ba3 ldr r3, [r4, #56] ; 0x38 + 8003d84: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 8003d88: 63a3 str r3, [r4, #56] ; 0x38 + 8003d8a: e7e3 b.n 8003d54 + 8003d8c: 6ba3 ldr r3, [r4, #56] ; 0x38 + 8003d8e: f423 3380 bic.w r3, r3, #65536 ; 0x10000 + 8003d92: e7f9 b.n 8003d88 + +08003d94 : + 8003d94: 6883 ldr r3, [r0, #8] + 8003d96: f043 0301 orr.w r3, r3, #1 + 8003d9a: 6083 str r3, [r0, #8] + 8003d9c: 2000 movs r0, #0 + 8003d9e: 4770 bx lr + +08003da0 : + 8003da0: 6883 ldr r3, [r0, #8] + 8003da2: f023 0301 bic.w r3, r3, #1 + 8003da6: 6083 str r3, [r0, #8] + 8003da8: 2000 movs r0, #0 + 8003daa: 4770 bx lr + +08003dac : + 8003dac: b508 push {r3, lr} + 8003dae: 68c3 ldr r3, [r0, #12] + 8003db0: 2901 cmp r1, #1 + 8003db2: f023 43c0 bic.w r3, r3, #1610612736 ; 0x60000000 + 8003db6: 60c3 str r3, [r0, #12] + 8003db8: d108 bne.n 8003dcc + 8003dba: 68c3 ldr r3, [r0, #12] + 8003dbc: f043 5300 orr.w r3, r3, #536870912 ; 0x20000000 + 8003dc0: 60c3 str r3, [r0, #12] + 8003dc2: 2032 movs r0, #50 ; 0x32 + 8003dc4: f7fd ff18 bl 8001bf8 + 8003dc8: 2000 movs r0, #0 + 8003dca: bd08 pop {r3, pc} + 8003dcc: b919 cbnz r1, 8003dd6 + 8003dce: 68c3 ldr r3, [r0, #12] + 8003dd0: f043 4380 orr.w r3, r3, #1073741824 ; 0x40000000 + 8003dd4: e7f4 b.n 8003dc0 + 8003dd6: 2001 movs r0, #1 + 8003dd8: e7f7 b.n 8003dca + ... + +08003ddc : + 8003ddc: 0189 lsls r1, r1, #6 + 8003dde: f041 0120 orr.w r1, r1, #32 + 8003de2: 4a06 ldr r2, [pc, #24] ; (8003dfc ) + 8003de4: 6101 str r1, [r0, #16] + 8003de6: 3a01 subs r2, #1 + 8003de8: d005 beq.n 8003df6 + 8003dea: 6903 ldr r3, [r0, #16] + 8003dec: f013 0320 ands.w r3, r3, #32 + 8003df0: d1f9 bne.n 8003de6 + 8003df2: 4618 mov r0, r3 + 8003df4: 4770 bx lr + 8003df6: 2003 movs r0, #3 + 8003df8: 4770 bx lr + 8003dfa: bf00 nop + 8003dfc: 00030d41 .word 0x00030d41 + +08003e00 : + 8003e00: 2310 movs r3, #16 + 8003e02: 4a06 ldr r2, [pc, #24] ; (8003e1c ) + 8003e04: 6103 str r3, [r0, #16] + 8003e06: 3a01 subs r2, #1 + 8003e08: d005 beq.n 8003e16 + 8003e0a: 6903 ldr r3, [r0, #16] + 8003e0c: f013 0310 ands.w r3, r3, #16 + 8003e10: d1f9 bne.n 8003e06 + 8003e12: 4618 mov r0, r3 + 8003e14: 4770 bx lr + 8003e16: 2003 movs r0, #3 + 8003e18: 4770 bx lr + 8003e1a: bf00 nop + 8003e1c: 00030d41 .word 0x00030d41 + +08003e20 : + 8003e20: b510 push {r4, lr} + 8003e22: f89d 4008 ldrb.w r4, [sp, #8] + 8003e26: b94c cbnz r4, 8003e3c + 8003e28: 3303 adds r3, #3 + 8003e2a: eb00 3002 add.w r0, r0, r2, lsl #12 + 8003e2e: 089b lsrs r3, r3, #2 + 8003e30: f500 5080 add.w r0, r0, #4096 ; 0x1000 + 8003e34: eb01 0383 add.w r3, r1, r3, lsl #2 + 8003e38: 4299 cmp r1, r3 + 8003e3a: d101 bne.n 8003e40 + 8003e3c: 2000 movs r0, #0 + 8003e3e: bd10 pop {r4, pc} + 8003e40: f851 2b04 ldr.w r2, [r1], #4 + 8003e44: 6002 str r2, [r0, #0] + 8003e46: e7f7 b.n 8003e38 + +08003e48 : + 8003e48: 3203 adds r2, #3 + 8003e4a: 0892 lsrs r2, r2, #2 + 8003e4c: eb01 0282 add.w r2, r1, r2, lsl #2 + 8003e50: f500 5080 add.w r0, r0, #4096 ; 0x1000 + 8003e54: 4291 cmp r1, r2 + 8003e56: d101 bne.n 8003e5c + 8003e58: 4608 mov r0, r1 + 8003e5a: 4770 bx lr + 8003e5c: 6803 ldr r3, [r0, #0] + 8003e5e: f841 3b04 str.w r3, [r1], #4 + 8003e62: e7f7 b.n 8003e54 + +08003e64 : + 8003e64: 6942 ldr r2, [r0, #20] + 8003e66: 6980 ldr r0, [r0, #24] + 8003e68: 4010 ands r0, r2 + 8003e6a: 4770 bx lr + +08003e6c : + 8003e6c: 6940 ldr r0, [r0, #20] + 8003e6e: f000 0001 and.w r0, r0, #1 + 8003e72: 4770 bx lr + +08003e74 : + 8003e74: f8d0 3400 ldr.w r3, [r0, #1024] ; 0x400 + 8003e78: f023 0303 bic.w r3, r3, #3 + 8003e7c: b510 push {r4, lr} + 8003e7e: f8c0 3400 str.w r3, [r0, #1024] ; 0x400 + 8003e82: f8d0 4400 ldr.w r4, [r0, #1024] ; 0x400 + 8003e86: f001 0303 and.w r3, r1, #3 + 8003e8a: 4323 orrs r3, r4 + 8003e8c: 2901 cmp r1, #1 + 8003e8e: f500 6280 add.w r2, r0, #1024 ; 0x400 + 8003e92: f8c0 3400 str.w r3, [r0, #1024] ; 0x400 + 8003e96: d104 bne.n 8003ea2 + 8003e98: f64b 3380 movw r3, #48000 ; 0xbb80 + 8003e9c: 6053 str r3, [r2, #4] + 8003e9e: 2000 movs r0, #0 + 8003ea0: bd10 pop {r4, pc} + 8003ea2: 2902 cmp r1, #2 + 8003ea4: d1fb bne.n 8003e9e + 8003ea6: f241 7370 movw r3, #6000 ; 0x1770 + 8003eaa: e7f7 b.n 8003e9c + +08003eac : + 8003eac: b537 push {r0, r1, r2, r4, r5, lr} + 8003eae: 2500 movs r5, #0 + 8003eb0: 9501 str r5, [sp, #4] + 8003eb2: f8d0 3440 ldr.w r3, [r0, #1088] ; 0x440 + 8003eb6: 9301 str r3, [sp, #4] + 8003eb8: 9b01 ldr r3, [sp, #4] + 8003eba: f023 032e bic.w r3, r3, #46 ; 0x2e + 8003ebe: 9301 str r3, [sp, #4] + 8003ec0: 9b01 ldr r3, [sp, #4] + 8003ec2: f443 7380 orr.w r3, r3, #256 ; 0x100 + 8003ec6: 4604 mov r4, r0 + 8003ec8: f8c0 3440 str.w r3, [r0, #1088] ; 0x440 + 8003ecc: 2064 movs r0, #100 ; 0x64 + 8003ece: f7fd fe93 bl 8001bf8 + 8003ed2: 9b01 ldr r3, [sp, #4] + 8003ed4: f423 7380 bic.w r3, r3, #256 ; 0x100 + 8003ed8: f8c4 3440 str.w r3, [r4, #1088] ; 0x440 + 8003edc: 200a movs r0, #10 + 8003ede: f7fd fe8b bl 8001bf8 + 8003ee2: 4628 mov r0, r5 + 8003ee4: b003 add sp, #12 + 8003ee6: bd30 pop {r4, r5, pc} + +08003ee8 : + 8003ee8: b082 sub sp, #8 + 8003eea: 2300 movs r3, #0 + 8003eec: 9301 str r3, [sp, #4] + 8003eee: f8d0 3440 ldr.w r3, [r0, #1088] ; 0x440 + 8003ef2: 9301 str r3, [sp, #4] + 8003ef4: 9b01 ldr r3, [sp, #4] + 8003ef6: f023 032e bic.w r3, r3, #46 ; 0x2e + 8003efa: 9301 str r3, [sp, #4] + 8003efc: 9b01 ldr r3, [sp, #4] + 8003efe: 04da lsls r2, r3, #19 + 8003f00: d406 bmi.n 8003f10 + 8003f02: 2901 cmp r1, #1 + 8003f04: bf02 ittt eq + 8003f06: 9b01 ldreq r3, [sp, #4] + 8003f08: f443 5380 orreq.w r3, r3, #4096 ; 0x1000 + 8003f0c: f8c0 3440 streq.w r3, [r0, #1088] ; 0x440 + 8003f10: 9b01 ldr r3, [sp, #4] + 8003f12: 04db lsls r3, r3, #19 + 8003f14: d505 bpl.n 8003f22 + 8003f16: b921 cbnz r1, 8003f22 + 8003f18: 9b01 ldr r3, [sp, #4] + 8003f1a: f423 5380 bic.w r3, r3, #4096 ; 0x1000 + 8003f1e: f8c0 3440 str.w r3, [r0, #1088] ; 0x440 + 8003f22: 2000 movs r0, #0 + 8003f24: b002 add sp, #8 + 8003f26: 4770 bx lr + +08003f28 : + 8003f28: b084 sub sp, #16 + 8003f2a: b538 push {r3, r4, r5, lr} + 8003f2c: 4604 mov r4, r0 + 8003f2e: a805 add r0, sp, #20 + 8003f30: e880 000e stmia.w r0, {r1, r2, r3} + 8003f34: 2300 movs r3, #0 + 8003f36: f8c4 3e00 str.w r3, [r4, #3584] ; 0xe00 + 8003f3a: 6ba3 ldr r3, [r4, #56] ; 0x38 + 8003f3c: f443 1300 orr.w r3, r3, #2097152 ; 0x200000 + 8003f40: 63a3 str r3, [r4, #56] ; 0x38 + 8003f42: 6ba3 ldr r3, [r4, #56] ; 0x38 + 8003f44: f423 2300 bic.w r3, r3, #524288 ; 0x80000 + 8003f48: 63a3 str r3, [r4, #56] ; 0x38 + 8003f4a: 6ba3 ldr r3, [r4, #56] ; 0x38 + 8003f4c: f423 2380 bic.w r3, r3, #262144 ; 0x40000 + 8003f50: 63a3 str r3, [r4, #56] ; 0x38 + 8003f52: 6be3 ldr r3, [r4, #60] ; 0x3c + 8003f54: 05da lsls r2, r3, #23 + 8003f56: d53f bpl.n 8003fd8 + 8003f58: 9b07 ldr r3, [sp, #28] + 8003f5a: 2b01 cmp r3, #1 + 8003f5c: f8d4 3400 ldr.w r3, [r4, #1024] ; 0x400 + 8003f60: d13c bne.n 8003fdc + 8003f62: f043 0304 orr.w r3, r3, #4 + 8003f66: f8c4 3400 str.w r3, [r4, #1024] ; 0x400 + 8003f6a: 2110 movs r1, #16 + 8003f6c: 4620 mov r0, r4 + 8003f6e: f7ff ff35 bl 8003ddc + 8003f72: 4620 mov r0, r4 + 8003f74: f7ff ff44 bl 8003e00 + 8003f78: 2300 movs r3, #0 + 8003f7a: 9906 ldr r1, [sp, #24] + 8003f7c: f504 62a0 add.w r2, r4, #1280 ; 0x500 + 8003f80: f04f 30ff mov.w r0, #4294967295 + 8003f84: 461d mov r5, r3 + 8003f86: 4299 cmp r1, r3 + 8003f88: d12b bne.n 8003fe2 + 8003f8a: 2101 movs r1, #1 + 8003f8c: 4620 mov r0, r4 + 8003f8e: f7ff ffab bl 8003ee8 + 8003f92: 20c8 movs r0, #200 ; 0xc8 + 8003f94: f7fd fe30 bl 8001bf8 + 8003f98: 2300 movs r3, #0 + 8003f9a: 61a3 str r3, [r4, #24] + 8003f9c: f04f 33ff mov.w r3, #4294967295 + 8003fa0: 6163 str r3, [r4, #20] + 8003fa2: 6be3 ldr r3, [r4, #60] ; 0x3c + 8003fa4: 05db lsls r3, r3, #23 + 8003fa6: d521 bpl.n 8003fec + 8003fa8: f44f 7300 mov.w r3, #512 ; 0x200 + 8003fac: 6263 str r3, [r4, #36] ; 0x24 + 8003fae: f103 7380 add.w r3, r3, #16777216 ; 0x1000000 + 8003fb2: 62a3 str r3, [r4, #40] ; 0x28 + 8003fb4: 4b11 ldr r3, [pc, #68] ; (8003ffc ) + 8003fb6: f8c4 3100 str.w r3, [r4, #256] ; 0x100 + 8003fba: 9b08 ldr r3, [sp, #32] + 8003fbc: b91b cbnz r3, 8003fc6 + 8003fbe: 69a3 ldr r3, [r4, #24] + 8003fc0: f043 0310 orr.w r3, r3, #16 + 8003fc4: 61a3 str r3, [r4, #24] + 8003fc6: 69a2 ldr r2, [r4, #24] + 8003fc8: 4b0d ldr r3, [pc, #52] ; (8004000 ) + 8003fca: 4313 orrs r3, r2 + 8003fcc: 61a3 str r3, [r4, #24] + 8003fce: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} + 8003fd2: 2000 movs r0, #0 + 8003fd4: b004 add sp, #16 + 8003fd6: 4770 bx lr + 8003fd8: f8d4 3400 ldr.w r3, [r4, #1024] ; 0x400 + 8003fdc: f023 0304 bic.w r3, r3, #4 + 8003fe0: e7c1 b.n 8003f66 + 8003fe2: 6090 str r0, [r2, #8] + 8003fe4: 3301 adds r3, #1 + 8003fe6: 60d5 str r5, [r2, #12] + 8003fe8: 3220 adds r2, #32 + 8003fea: e7cc b.n 8003f86 + 8003fec: 2380 movs r3, #128 ; 0x80 + 8003fee: 6263 str r3, [r4, #36] ; 0x24 + 8003ff0: f503 03c0 add.w r3, r3, #6291456 ; 0x600000 + 8003ff4: 62a3 str r3, [r4, #40] ; 0x28 + 8003ff6: 4b03 ldr r3, [pc, #12] ; (8004004 ) + 8003ff8: e7dd b.n 8003fb6 + 8003ffa: bf00 nop + 8003ffc: 00e00300 .word 0x00e00300 + 8004000: a3200008 .word 0xa3200008 + 8004004: 004000e0 .word 0x004000e0 + +08004008 : + 8004008: b082 sub sp, #8 + 800400a: 2300 movs r3, #0 + 800400c: 9301 str r3, [sp, #4] + 800400e: f8d0 3440 ldr.w r3, [r0, #1088] ; 0x440 + 8004012: 9301 str r3, [sp, #4] + 8004014: 9801 ldr r0, [sp, #4] + 8004016: f3c0 4041 ubfx r0, r0, #17, #2 + 800401a: b002 add sp, #8 + 800401c: 4770 bx lr + +0800401e : + 800401e: f500 6080 add.w r0, r0, #1024 ; 0x400 + 8004022: 6880 ldr r0, [r0, #8] + 8004024: b280 uxth r0, r0 + 8004026: 4770 bx lr + +08004028 : + 8004028: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 800402c: eb00 1741 add.w r7, r0, r1, lsl #5 + 8004030: f507 64a0 add.w r4, r7, #1280 ; 0x500 + 8004034: f89d 601c ldrb.w r6, [sp, #28] + 8004038: 4605 mov r5, r0 + 800403a: f04f 30ff mov.w r0, #4294967295 + 800403e: 60a0 str r0, [r4, #8] + 8004040: fa4f f882 sxtb.w r8, r2 + 8004044: f505 6e80 add.w lr, r5, #1024 ; 0x400 + 8004048: f001 0c0f and.w ip, r1, #15 + 800404c: 2e03 cmp r6, #3 + 800404e: d86c bhi.n 800412a + 8004050: e8df f006 tbb [pc, r6] + 8004054: 4c026102 .word 0x4c026102 + 8004058: f240 419d movw r1, #1181 ; 0x49d + 800405c: f1b8 0f00 cmp.w r8, #0 + 8004060: 60e1 str r1, [r4, #12] + 8004062: da03 bge.n 800406c + 8004064: 68e1 ldr r1, [r4, #12] + 8004066: f441 7180 orr.w r1, r1, #256 ; 0x100 + 800406a: e005 b.n 8004078 + 800406c: 6be9 ldr r1, [r5, #60] ; 0x3c + 800406e: 05c9 lsls r1, r1, #23 + 8004070: d542 bpl.n 80040f8 + 8004072: 68e1 ldr r1, [r4, #12] + 8004074: f041 0160 orr.w r1, r1, #96 ; 0x60 + 8004078: 60e1 str r1, [r4, #12] + 800407a: 2000 movs r0, #0 + 800407c: f8de 4018 ldr.w r4, [lr, #24] + 8004080: 2101 movs r1, #1 + 8004082: fa01 f10c lsl.w r1, r1, ip + 8004086: 4321 orrs r1, r4 + 8004088: f8ce 1018 str.w r1, [lr, #24] + 800408c: 69a9 ldr r1, [r5, #24] + 800408e: f1b8 0f00 cmp.w r8, #0 + 8004092: f041 7100 orr.w r1, r1, #33554432 ; 0x2000000 + 8004096: 61a9 str r1, [r5, #24] + 8004098: bfac ite ge + 800409a: 2400 movge r4, #0 + 800409c: f44f 4400 movlt.w r4, #32768 ; 0x8000 + 80040a0: f8bd 5020 ldrh.w r5, [sp, #32] + 80040a4: f89d 1018 ldrb.w r1, [sp, #24] + 80040a8: 059b lsls r3, r3, #22 + 80040aa: f003 53fe and.w r3, r3, #532676608 ; 0x1fc00000 + 80040ae: f3c5 050a ubfx r5, r5, #0, #11 + 80040b2: 02d2 lsls r2, r2, #11 + 80040b4: f402 42f0 and.w r2, r2, #30720 ; 0x7800 + 80040b8: 432b orrs r3, r5 + 80040ba: 4313 orrs r3, r2 + 80040bc: 04b2 lsls r2, r6, #18 + 80040be: f402 2240 and.w r2, r2, #786432 ; 0xc0000 + 80040c2: 2902 cmp r1, #2 + 80040c4: ea43 0302 orr.w r3, r3, r2 + 80040c8: bf14 ite ne + 80040ca: 2100 movne r1, #0 + 80040cc: f44f 3100 moveq.w r1, #131072 ; 0x20000 + 80040d0: 4323 orrs r3, r4 + 80040d2: 430b orrs r3, r1 + 80040d4: 2e03 cmp r6, #3 + 80040d6: f8c7 3500 str.w r3, [r7, #1280] ; 0x500 + 80040da: d105 bne.n 80040e8 + 80040dc: f8d7 3500 ldr.w r3, [r7, #1280] ; 0x500 + 80040e0: f043 5300 orr.w r3, r3, #536870912 ; 0x20000000 + 80040e4: f8c7 3500 str.w r3, [r7, #1280] ; 0x500 + 80040e8: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 80040ec: f240 619d movw r1, #1693 ; 0x69d + 80040f0: f1b8 0f00 cmp.w r8, #0 + 80040f4: 60e1 str r1, [r4, #12] + 80040f6: dbb5 blt.n 8004064 + 80040f8: f8de 0018 ldr.w r0, [lr, #24] + 80040fc: 2101 movs r1, #1 + 80040fe: fa01 f10c lsl.w r1, r1, ip + 8004102: 4301 orrs r1, r0 + 8004104: f8ce 1018 str.w r1, [lr, #24] + 8004108: 69a9 ldr r1, [r5, #24] + 800410a: 2000 movs r0, #0 + 800410c: f041 7100 orr.w r1, r1, #33554432 ; 0x2000000 + 8004110: 61a9 str r1, [r5, #24] + 8004112: 4604 mov r4, r0 + 8004114: e7c4 b.n 80040a0 + 8004116: f240 2125 movw r1, #549 ; 0x225 + 800411a: f1b8 0f00 cmp.w r8, #0 + 800411e: 60e1 str r1, [r4, #12] + 8004120: daea bge.n 80040f8 + 8004122: 68e1 ldr r1, [r4, #12] + 8004124: f441 71c0 orr.w r1, r1, #384 ; 0x180 + 8004128: e7a6 b.n 8004078 + 800412a: 2001 movs r0, #1 + 800412c: e7a6 b.n 800407c + +0800412e : + 800412e: f500 6080 add.w r0, r0, #1024 ; 0x400 + 8004132: 6940 ldr r0, [r0, #20] + 8004134: b280 uxth r0, r0 + 8004136: 4770 bx lr + +08004138 : + 8004138: eb00 1141 add.w r1, r0, r1, lsl #5 + 800413c: f501 62a0 add.w r2, r1, #1280 ; 0x500 + 8004140: f8d1 3500 ldr.w r3, [r1, #1280] ; 0x500 + 8004144: f413 2f80 tst.w r3, #262144 ; 0x40000 + 8004148: f8d1 3500 ldr.w r3, [r1, #1280] ; 0x500 + 800414c: f043 4380 orr.w r3, r3, #1073741824 ; 0x40000000 + 8004150: f8c1 3500 str.w r3, [r1, #1280] ; 0x500 + 8004154: d11e bne.n 8004194 + 8004156: 6ac3 ldr r3, [r0, #44] ; 0x2c + 8004158: f413 0f7f tst.w r3, #16711680 ; 0xff0000 + 800415c: f8d1 3500 ldr.w r3, [r1, #1280] ; 0x500 + 8004160: d137 bne.n 80041d2 + 8004162: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000 + 8004166: f8c1 3500 str.w r3, [r1, #1280] ; 0x500 + 800416a: f8d1 3500 ldr.w r3, [r1, #1280] ; 0x500 + 800416e: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 + 8004172: f8c1 3500 str.w r3, [r1, #1280] ; 0x500 + 8004176: f8d1 3500 ldr.w r3, [r1, #1280] ; 0x500 + 800417a: f423 4300 bic.w r3, r3, #32768 ; 0x8000 + 800417e: f8c1 3500 str.w r3, [r1, #1280] ; 0x500 + 8004182: f240 33e9 movw r3, #1001 ; 0x3e9 + 8004186: 3b01 subs r3, #1 + 8004188: d002 beq.n 8004190 + 800418a: 6811 ldr r1, [r2, #0] + 800418c: 2900 cmp r1, #0 + 800418e: dbfa blt.n 8004186 + 8004190: 2000 movs r0, #0 + 8004192: 4770 bx lr + 8004194: f8d0 3410 ldr.w r3, [r0, #1040] ; 0x410 + 8004198: f413 0f7f tst.w r3, #16711680 ; 0xff0000 + 800419c: f8d1 3500 ldr.w r3, [r1, #1280] ; 0x500 + 80041a0: d117 bne.n 80041d2 + 80041a2: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000 + 80041a6: f8c1 3500 str.w r3, [r1, #1280] ; 0x500 + 80041aa: f8d1 3500 ldr.w r3, [r1, #1280] ; 0x500 + 80041ae: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 + 80041b2: f8c1 3500 str.w r3, [r1, #1280] ; 0x500 + 80041b6: f8d1 3500 ldr.w r3, [r1, #1280] ; 0x500 + 80041ba: f423 4300 bic.w r3, r3, #32768 ; 0x8000 + 80041be: f8c1 3500 str.w r3, [r1, #1280] ; 0x500 + 80041c2: f240 33e9 movw r3, #1001 ; 0x3e9 + 80041c6: 3b01 subs r3, #1 + 80041c8: d0e2 beq.n 8004190 + 80041ca: 6811 ldr r1, [r2, #0] + 80041cc: 2900 cmp r1, #0 + 80041ce: dbfa blt.n 80041c6 + 80041d0: e7de b.n 8004190 + 80041d2: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 + 80041d6: f8c1 3500 str.w r3, [r1, #1280] ; 0x500 + 80041da: e7d9 b.n 8004190 + +080041dc : + 80041dc: eb00 1141 add.w r1, r0, r1, lsl #5 + 80041e0: 4a06 ldr r2, [pc, #24] ; (80041fc ) + 80041e2: f8c1 2510 str.w r2, [r1, #1296] ; 0x510 + 80041e6: f8d1 3500 ldr.w r3, [r1, #1280] ; 0x500 + 80041ea: f023 4380 bic.w r3, r3, #1073741824 ; 0x40000000 + 80041ee: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 + 80041f2: f8c1 3500 str.w r3, [r1, #1280] ; 0x500 + 80041f6: 2000 movs r0, #0 + 80041f8: 4770 bx lr + 80041fa: bf00 nop + 80041fc: 80080000 .word 0x80080000 + +08004200 : + 8004200: e92d 41f3 stmdb sp!, {r0, r1, r4, r5, r6, r7, r8, lr} + 8004204: 6bc3 ldr r3, [r0, #60] ; 0x3c + 8004206: 05db lsls r3, r3, #23 + 8004208: 4616 mov r6, r2 + 800420a: 4604 mov r4, r0 + 800420c: 784a ldrb r2, [r1, #1] + 800420e: d517 bpl.n 8004240 + 8004210: 790d ldrb r5, [r1, #4] + 8004212: b9ad cbnz r5, 8004240 + 8004214: b94e cbnz r6, 800422a + 8004216: 794b ldrb r3, [r1, #5] + 8004218: 2b01 cmp r3, #1 + 800421a: d111 bne.n 8004240 + 800421c: 4611 mov r1, r2 + 800421e: f7ff ffdd bl 80041dc + 8004222: 2000 movs r0, #0 + 8004224: b002 add sp, #8 + 8004226: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 800422a: 2e01 cmp r6, #1 + 800422c: d108 bne.n 8004240 + 800422e: eb00 1342 add.w r3, r0, r2, lsl #5 + 8004232: f8d3 050c ldr.w r0, [r3, #1292] ; 0x50c + 8004236: f020 0060 bic.w r0, r0, #96 ; 0x60 + 800423a: f8c3 050c str.w r0, [r3, #1292] ; 0x50c + 800423e: 714d strb r5, [r1, #5] + 8004240: 6908 ldr r0, [r1, #16] + 8004242: 2800 cmp r0, #0 + 8004244: d062 beq.n 800430c + 8004246: 890b ldrh r3, [r1, #8] + 8004248: 3801 subs r0, #1 + 800424a: 4418 add r0, r3 + 800424c: fbb0 f0f3 udiv r0, r0, r3 + 8004250: b280 uxth r0, r0 + 8004252: f5b0 7f80 cmp.w r0, #256 ; 0x100 + 8004256: d903 bls.n 8004260 + 8004258: 021b lsls r3, r3, #8 + 800425a: 610b str r3, [r1, #16] + 800425c: f44f 7080 mov.w r0, #256 ; 0x100 + 8004260: 78cf ldrb r7, [r1, #3] + 8004262: b117 cbz r7, 800426a + 8004264: 890b ldrh r3, [r1, #8] + 8004266: 4343 muls r3, r0 + 8004268: 610b str r3, [r1, #16] + 800426a: f891 c00a ldrb.w ip, [r1, #10] + 800426e: 690b ldr r3, [r1, #16] + 8004270: ea4f 7c4c mov.w ip, ip, lsl #29 + 8004274: f00c 4cc0 and.w ip, ip, #1610612736 ; 0x60000000 + 8004278: f3c3 0812 ubfx r8, r3, #0, #19 + 800427c: eb04 1542 add.w r5, r4, r2, lsl #5 + 8004280: ea4c 0c08 orr.w ip, ip, r8 + 8004284: ea4c 40c0 orr.w r0, ip, r0, lsl #19 + 8004288: f8c5 0510 str.w r0, [r5, #1296] ; 0x510 + 800428c: b116 cbz r6, 8004294 + 800428e: 68c8 ldr r0, [r1, #12] + 8004290: f8c5 0514 str.w r0, [r5, #1300] ; 0x514 + 8004294: f504 6c80 add.w ip, r4, #1024 ; 0x400 + 8004298: f8dc 0008 ldr.w r0, [ip, #8] + 800429c: f8d5 e500 ldr.w lr, [r5, #1280] ; 0x500 + 80042a0: f02e 5e00 bic.w lr, lr, #536870912 ; 0x20000000 + 80042a4: f8c5 e500 str.w lr, [r5, #1280] ; 0x500 + 80042a8: 43c0 mvns r0, r0 + 80042aa: f8d5 e500 ldr.w lr, [r5, #1280] ; 0x500 + 80042ae: 0740 lsls r0, r0, #29 + 80042b0: f000 5000 and.w r0, r0, #536870912 ; 0x20000000 + 80042b4: ea40 000e orr.w r0, r0, lr + 80042b8: f8c5 0500 str.w r0, [r5, #1280] ; 0x500 + 80042bc: 4825 ldr r0, [pc, #148] ; (8004354 ) + 80042be: f8d5 e500 ldr.w lr, [r5, #1280] ; 0x500 + 80042c2: f8c0 e000 str.w lr, [r0] + 80042c6: f8d0 e000 ldr.w lr, [r0] + 80042ca: f02e 4e80 bic.w lr, lr, #1073741824 ; 0x40000000 + 80042ce: f8c0 e000 str.w lr, [r0] + 80042d2: f8d0 e000 ldr.w lr, [r0] + 80042d6: b1df cbz r7, 8004310 + 80042d8: f44e 4e00 orr.w lr, lr, #32768 ; 0x8000 + 80042dc: f8c0 e000 str.w lr, [r0] + 80042e0: f8d0 e000 ldr.w lr, [r0] + 80042e4: f04e 4e00 orr.w lr, lr, #2147483648 ; 0x80000000 + 80042e8: f8c0 e000 str.w lr, [r0] + 80042ec: 6800 ldr r0, [r0, #0] + 80042ee: f8c5 0500 str.w r0, [r5, #1280] ; 0x500 + 80042f2: 2e00 cmp r6, #0 + 80042f4: d195 bne.n 8004222 + 80042f6: 2f00 cmp r7, #0 + 80042f8: d193 bne.n 8004222 + 80042fa: 2b00 cmp r3, #0 + 80042fc: d091 beq.n 8004222 + 80042fe: 79c8 ldrb r0, [r1, #7] + 8004300: 2803 cmp r0, #3 + 8004302: d813 bhi.n 800432c + 8004304: e8df f000 tbb [pc, r0] + 8004308: 1a071a07 .word 0x1a071a07 + 800430c: 2001 movs r0, #1 + 800430e: e7a7 b.n 8004260 + 8004310: f42e 4e00 bic.w lr, lr, #32768 ; 0x8000 + 8004314: e7e2 b.n 80042dc + 8004316: 6ae5 ldr r5, [r4, #44] ; 0x2c + 8004318: 1cd8 adds r0, r3, #3 + 800431a: b2ad uxth r5, r5 + 800431c: f3c0 008f ubfx r0, r0, #2, #16 + 8004320: 4285 cmp r5, r0 + 8004322: d203 bcs.n 800432c + 8004324: 69a0 ldr r0, [r4, #24] + 8004326: f040 0020 orr.w r0, r0, #32 + 800432a: 61a0 str r0, [r4, #24] + 800432c: 2000 movs r0, #0 + 800432e: 9000 str r0, [sp, #0] + 8004330: b29b uxth r3, r3 + 8004332: 68c9 ldr r1, [r1, #12] + 8004334: 4620 mov r0, r4 + 8004336: f7ff fd73 bl 8003e20 + 800433a: e772 b.n 8004222 + 800433c: f8dc 5010 ldr.w r5, [ip, #16] + 8004340: 1cd8 adds r0, r3, #3 + 8004342: b2ad uxth r5, r5 + 8004344: f3c0 008f ubfx r0, r0, #2, #16 + 8004348: 4285 cmp r5, r0 + 800434a: d2ef bcs.n 800432c + 800434c: 69a0 ldr r0, [r4, #24] + 800434e: f040 6080 orr.w r0, r0, #67108864 ; 0x4000000 + 8004352: e7ea b.n 800432a + 8004354: 2000022c .word 0x2000022c + +08004358 : + 8004358: 6883 ldr r3, [r0, #8] + 800435a: f023 0301 bic.w r3, r3, #1 + 800435e: b510 push {r4, lr} + 8004360: 2110 movs r1, #16 + 8004362: 4604 mov r4, r0 + 8004364: 6083 str r3, [r0, #8] + 8004366: f7ff fd39 bl 8003ddc + 800436a: 4620 mov r0, r4 + 800436c: f7ff fd48 bl 8003e00 + 8004370: f504 63a0 add.w r3, r4, #1280 ; 0x500 + 8004374: f504 60e0 add.w r0, r4, #1792 ; 0x700 + 8004378: 461a mov r2, r3 + 800437a: 6811 ldr r1, [r2, #0] + 800437c: f021 2180 bic.w r1, r1, #2147516416 ; 0x80008000 + 8004380: f041 4180 orr.w r1, r1, #1073741824 ; 0x40000000 + 8004384: f842 1b20 str.w r1, [r2], #32 + 8004388: 4282 cmp r2, r0 + 800438a: d1f6 bne.n 800437a + 800438c: 2000 movs r0, #0 + 800438e: 6819 ldr r1, [r3, #0] + 8004390: f421 4100 bic.w r1, r1, #32768 ; 0x8000 + 8004394: f041 4140 orr.w r1, r1, #3221225472 ; 0xc0000000 + 8004398: 6019 str r1, [r3, #0] + 800439a: 3001 adds r0, #1 + 800439c: f5b0 7f7a cmp.w r0, #1000 ; 0x3e8 + 80043a0: d802 bhi.n 80043a8 + 80043a2: 6819 ldr r1, [r3, #0] + 80043a4: 2900 cmp r1, #0 + 80043a6: dbf8 blt.n 800439a + 80043a8: 3320 adds r3, #32 + 80043aa: 429a cmp r2, r3 + 80043ac: d1ef bne.n 800438e + 80043ae: f04f 33ff mov.w r3, #4294967295 + 80043b2: f8c4 3414 str.w r3, [r4, #1044] ; 0x414 + 80043b6: 6163 str r3, [r4, #20] + 80043b8: 68a3 ldr r3, [r4, #8] + 80043ba: f043 0301 orr.w r3, r3, #1 + 80043be: 60a3 str r3, [r4, #8] + 80043c0: 2000 movs r0, #0 + 80043c2: bd10 pop {r4, pc} + +080043c4 : + 80043c4: 2000 movs r0, #0 + 80043c6: 4770 bx lr + +080043c8 : + 80043c8: b538 push {r3, r4, r5, lr} + 80043ca: f8d0 337c ldr.w r3, [r0, #892] ; 0x37c + 80043ce: 69dc ldr r4, [r3, #28] + 80043d0: 7821 ldrb r1, [r4, #0] + 80043d2: 4605 mov r5, r0 + 80043d4: b139 cbz r1, 80043e6 + 80043d6: f000 fe97 bl 8005108 + 80043da: 7821 ldrb r1, [r4, #0] + 80043dc: 4628 mov r0, r5 + 80043de: f000 feb0 bl 8005142 + 80043e2: 2300 movs r3, #0 + 80043e4: 7023 strb r3, [r4, #0] + 80043e6: 7b21 ldrb r1, [r4, #12] + 80043e8: b141 cbz r1, 80043fc + 80043ea: 4628 mov r0, r5 + 80043ec: f000 fe8c bl 8005108 + 80043f0: 7b21 ldrb r1, [r4, #12] + 80043f2: 4628 mov r0, r5 + 80043f4: f000 fea5 bl 8005142 + 80043f8: 2300 movs r3, #0 + 80043fa: 7323 strb r3, [r4, #12] + 80043fc: 7b61 ldrb r1, [r4, #13] + 80043fe: b141 cbz r1, 8004412 + 8004400: 4628 mov r0, r5 + 8004402: f000 fe81 bl 8005108 + 8004406: 7b61 ldrb r1, [r4, #13] + 8004408: 4628 mov r0, r5 + 800440a: f000 fe9a bl 8005142 + 800440e: 2300 movs r3, #0 + 8004410: 7363 strb r3, [r4, #13] + 8004412: f8d5 337c ldr.w r3, [r5, #892] ; 0x37c + 8004416: 69d8 ldr r0, [r3, #28] + 8004418: b128 cbz r0, 8004426 + 800441a: f001 f837 bl 800548c + 800441e: f8d5 337c ldr.w r3, [r5, #892] ; 0x37c + 8004422: 2200 movs r2, #0 + 8004424: 61da str r2, [r3, #28] + 8004426: 2000 movs r0, #0 + 8004428: bd38 pop {r3, r4, r5, pc} + +0800442a : + 800442a: e92d 41ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, lr} + 800442e: 2202 movs r2, #2 + 8004430: 2301 movs r3, #1 + 8004432: 4611 mov r1, r2 + 8004434: 4605 mov r5, r0 + 8004436: f000 f9bc bl 80047b2 + 800443a: 2801 cmp r0, #1 + 800443c: 4606 mov r6, r0 + 800443e: d904 bls.n 800444a + 8004440: 2702 movs r7, #2 + 8004442: 4638 mov r0, r7 + 8004444: b004 add sp, #16 + 8004446: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 800444a: 4601 mov r1, r0 + 800444c: 4628 mov r0, r5 + 800444e: f000 f9a7 bl 80047a0 + 8004452: 4607 mov r7, r0 + 8004454: 2800 cmp r0, #0 + 8004456: d1f3 bne.n 8004440 + 8004458: 2050 movs r0, #80 ; 0x50 + 800445a: f8d5 837c ldr.w r8, [r5, #892] ; 0x37c + 800445e: f001 f80d bl 800547c + 8004462: 4604 mov r4, r0 + 8004464: f8c8 001c str.w r0, [r8, #28] + 8004468: 2800 cmp r0, #0 + 800446a: d0e9 beq.n 8004440 + 800446c: 2250 movs r2, #80 ; 0x50 + 800446e: 4639 mov r1, r7 + 8004470: f001 f814 bl 800549c + 8004474: 231a movs r3, #26 + 8004476: fb03 5606 mla r6, r3, r6, r5 + 800447a: 4628 mov r0, r5 + 800447c: f896 334e ldrb.w r3, [r6, #846] ; 0x34e + 8004480: 061a lsls r2, r3, #24 + 8004482: bf48 it mi + 8004484: 7063 strbmi r3, [r4, #1] + 8004486: 7861 ldrb r1, [r4, #1] + 8004488: bf44 itt mi + 800448a: f8b6 3350 ldrhmi.w r3, [r6, #848] ; 0x350 + 800448e: 8163 strhmi r3, [r4, #10] + 8004490: f000 fe3f bl 8005112 + 8004494: 4601 mov r1, r0 + 8004496: 7020 strb r0, [r4, #0] + 8004498: 8960 ldrh r0, [r4, #10] + 800449a: 9002 str r0, [sp, #8] + 800449c: 2003 movs r0, #3 + 800449e: 9001 str r0, [sp, #4] + 80044a0: f895 031d ldrb.w r0, [r5, #797] ; 0x31d + 80044a4: f895 331c ldrb.w r3, [r5, #796] ; 0x31c + 80044a8: 7862 ldrb r2, [r4, #1] + 80044aa: 9000 str r0, [sp, #0] + 80044ac: 4628 mov r0, r5 + 80044ae: f000 fe1c bl 80050ea + 80044b2: 2200 movs r2, #0 + 80044b4: 7821 ldrb r1, [r4, #0] + 80044b6: 4628 mov r0, r5 + 80044b8: f000 ff9b bl 80053f2 + 80044bc: 2300 movs r3, #0 + 80044be: 461a mov r2, r3 + 80044c0: 210a movs r1, #10 + 80044c2: 4628 mov r0, r5 + 80044c4: f000 f975 bl 80047b2 + 80044c8: 2801 cmp r0, #1 + 80044ca: d8b9 bhi.n 8004440 + 80044cc: 231a movs r3, #26 + 80044ce: fb03 5100 mla r1, r3, r0, r5 + 80044d2: fb03 5000 mla r0, r3, r0, r5 + 80044d6: f891 234e ldrb.w r2, [r1, #846] ; 0x34e + 80044da: f890 3356 ldrb.w r3, [r0, #854] ; 0x356 + 80044de: f8b1 1350 ldrh.w r1, [r1, #848] ; 0x350 + 80044e2: 0616 lsls r6, r2, #24 + 80044e4: bf53 iteet pl + 80044e6: 73a2 strbpl r2, [r4, #14] + 80044e8: 73e2 strbmi r2, [r4, #15] + 80044ea: 8361 strhmi r1, [r4, #26] + 80044ec: 8321 strhpl r1, [r4, #24] + 80044ee: 0619 lsls r1, r3, #24 + 80044f0: bf58 it pl + 80044f2: 73a3 strbpl r3, [r4, #14] + 80044f4: f8b0 2358 ldrh.w r2, [r0, #856] ; 0x358 + 80044f8: 7ba1 ldrb r1, [r4, #14] + 80044fa: bf48 it mi + 80044fc: 73e3 strbmi r3, [r4, #15] + 80044fe: 4628 mov r0, r5 + 8004500: bf4c ite mi + 8004502: 8362 strhmi r2, [r4, #26] + 8004504: 8322 strhpl r2, [r4, #24] + 8004506: f000 fe04 bl 8005112 + 800450a: 7be1 ldrb r1, [r4, #15] + 800450c: 7360 strb r0, [r4, #13] + 800450e: 4628 mov r0, r5 + 8004510: f000 fdff bl 8005112 + 8004514: 7320 strb r0, [r4, #12] + 8004516: 8b20 ldrh r0, [r4, #24] + 8004518: 9002 str r0, [sp, #8] + 800451a: 2602 movs r6, #2 + 800451c: f895 031d ldrb.w r0, [r5, #797] ; 0x31d + 8004520: f895 331c ldrb.w r3, [r5, #796] ; 0x31c + 8004524: 7ba2 ldrb r2, [r4, #14] + 8004526: 7b61 ldrb r1, [r4, #13] + 8004528: 9601 str r6, [sp, #4] + 800452a: 9000 str r0, [sp, #0] + 800452c: 4628 mov r0, r5 + 800452e: f000 fddc bl 80050ea + 8004532: 8b60 ldrh r0, [r4, #26] + 8004534: f895 331c ldrb.w r3, [r5, #796] ; 0x31c + 8004538: 7be2 ldrb r2, [r4, #15] + 800453a: 7b21 ldrb r1, [r4, #12] + 800453c: e9cd 6001 strd r6, r0, [sp, #4] + 8004540: f895 031d ldrb.w r0, [r5, #797] ; 0x31d + 8004544: 9000 str r0, [sp, #0] + 8004546: 2600 movs r6, #0 + 8004548: 4628 mov r0, r5 + 800454a: f000 fdce bl 80050ea + 800454e: 4632 mov r2, r6 + 8004550: 7b61 ldrb r1, [r4, #13] + 8004552: f884 604c strb.w r6, [r4, #76] ; 0x4c + 8004556: 4628 mov r0, r5 + 8004558: f000 ff4b bl 80053f2 + 800455c: 4632 mov r2, r6 + 800455e: 7b21 ldrb r1, [r4, #12] + 8004560: 4628 mov r0, r5 + 8004562: f000 ff46 bl 80053f2 + 8004566: e76c b.n 8004442 + +08004568 : + 8004568: b538 push {r3, r4, r5, lr} + 800456a: f8d0 337c ldr.w r3, [r0, #892] ; 0x37c + 800456e: 69d9 ldr r1, [r3, #28] + 8004570: f242 12a1 movw r2, #8609 ; 0x21a1 + 8004574: f44f 23e0 mov.w r3, #458752 ; 0x70000 + 8004578: e9c0 2304 strd r2, r3, [r0, #16] + 800457c: 3140 adds r1, #64 ; 0x40 + 800457e: 2207 movs r2, #7 + 8004580: 4604 mov r4, r0 + 8004582: f000 fb43 bl 8004c0c + 8004586: 4605 mov r5, r0 + 8004588: b920 cbnz r0, 8004594 + 800458a: f8d4 33d4 ldr.w r3, [r4, #980] ; 0x3d4 + 800458e: 2102 movs r1, #2 + 8004590: 4620 mov r0, r4 + 8004592: 4798 blx r3 + 8004594: 4628 mov r0, r5 + 8004596: bd38 pop {r3, r4, r5, pc} + +08004598 : + 8004598: 4770 bx lr + +0800459a : + 800459a: 4770 bx lr + +0800459c : + 800459c: 4770 bx lr + +0800459e : + 800459e: f8d0 337c ldr.w r3, [r0, #892] ; 0x37c + 80045a2: b573 push {r0, r1, r4, r5, r6, lr} + 80045a4: 69dc ldr r4, [r3, #28] + 80045a6: f894 304c ldrb.w r3, [r4, #76] ; 0x4c + 80045aa: 4605 mov r5, r0 + 80045ac: 2b04 cmp r3, #4 + 80045ae: d813 bhi.n 80045d8 + 80045b0: e8df f003 tbb [pc, r3] + 80045b4: 381503a6 .word 0x381503a6 + 80045b8: 9d .byte 0x9d + 80045b9: 00 .byte 0x00 + 80045ba: f242 0021 movw r0, #8225 ; 0x2021 + 80045be: f44f 23e0 mov.w r3, #458752 ; 0x70000 + 80045c2: 6ca1 ldr r1, [r4, #72] ; 0x48 + 80045c4: 2207 movs r2, #7 + 80045c6: e9c5 0304 strd r0, r3, [r5, #16] + 80045ca: 4628 mov r0, r5 + 80045cc: f000 fb1e bl 8004c0c + 80045d0: bb20 cbnz r0, 800461c + 80045d2: 2302 movs r3, #2 + 80045d4: f884 304c strb.w r3, [r4, #76] ; 0x4c + 80045d8: 2001 movs r0, #1 + 80045da: b002 add sp, #8 + 80045dc: bd70 pop {r4, r5, r6, pc} + 80045de: f242 12a1 movw r2, #8609 ; 0x21a1 + 80045e2: f44f 23e0 mov.w r3, #458752 ; 0x70000 + 80045e6: e9c0 2304 strd r2, r3, [r0, #16] + 80045ea: f104 0140 add.w r1, r4, #64 ; 0x40 + 80045ee: 2207 movs r2, #7 + 80045f0: f000 fb0c bl 8004c0c + 80045f4: b990 cbnz r0, 800461c + 80045f6: e9d4 3111 ldrd r3, r1, [r4, #68] ; 0x44 + 80045fa: f023 427f bic.w r2, r3, #4278190080 ; 0xff000000 + 80045fe: 684b ldr r3, [r1, #4] + 8004600: f884 004c strb.w r0, [r4, #76] ; 0x4c + 8004604: f023 437f bic.w r3, r3, #4278190080 ; 0xff000000 + 8004608: 429a cmp r2, r3 + 800460a: d1e5 bne.n 80045d8 + 800460c: 6c22 ldr r2, [r4, #64] ; 0x40 + 800460e: 680b ldr r3, [r1, #0] + 8004610: 429a cmp r2, r3 + 8004612: d1e1 bne.n 80045d8 + 8004614: 4628 mov r0, r5 + 8004616: f7ff ffc1 bl 800459c + 800461a: e7dd b.n 80045d8 + 800461c: 2801 cmp r0, #1 + 800461e: d0db beq.n 80045d8 + 8004620: 2304 movs r3, #4 + 8004622: e7d7 b.n 80045d4 + 8004624: f894 004d ldrb.w r0, [r4, #77] ; 0x4d + 8004628: 2801 cmp r0, #1 + 800462a: d021 beq.n 8004670 + 800462c: 2802 cmp r0, #2 + 800462e: d02e beq.n 800468e + 8004630: f8d5 337c ldr.w r3, [r5, #892] ; 0x37c + 8004634: 69de ldr r6, [r3, #28] + 8004636: f896 304e ldrb.w r3, [r6, #78] ; 0x4e + 800463a: 2b03 cmp r3, #3 + 800463c: d046 beq.n 80046cc + 800463e: 2b04 cmp r3, #4 + 8004640: d1ca bne.n 80045d8 + 8004642: 7b31 ldrb r1, [r6, #12] + 8004644: 4628 mov r0, r5 + 8004646: f000 fec3 bl 80053d0 + 800464a: 2801 cmp r0, #1 + 800464c: d1c4 bne.n 80045d8 + 800464e: 7b31 ldrb r1, [r6, #12] + 8004650: 4628 mov r0, r5 + 8004652: f000 fe79 bl 8005348 + 8004656: 6ab3 ldr r3, [r6, #40] ; 0x28 + 8004658: 4298 cmp r0, r3 + 800465a: d041 beq.n 80046e0 + 800465c: 8b72 ldrh r2, [r6, #26] + 800465e: 4290 cmp r0, r2 + 8004660: d93e bls.n 80046e0 + 8004662: 1a1b subs r3, r3, r0 + 8004664: 62b3 str r3, [r6, #40] ; 0x28 + 8004666: 6a33 ldr r3, [r6, #32] + 8004668: 4418 add r0, r3 + 800466a: 6230 str r0, [r6, #32] + 800466c: 2303 movs r3, #3 + 800466e: e034 b.n 80046da + 8004670: 6a66 ldr r6, [r4, #36] ; 0x24 + 8004672: 8b22 ldrh r2, [r4, #24] + 8004674: 7b63 ldrb r3, [r4, #13] + 8004676: 69e1 ldr r1, [r4, #28] + 8004678: 9000 str r0, [sp, #0] + 800467a: 4296 cmp r6, r2 + 800467c: bf98 it ls + 800467e: b2b2 uxthls r2, r6 + 8004680: 4628 mov r0, r5 + 8004682: f000 fd0b bl 800509c + 8004686: 2302 movs r3, #2 + 8004688: f884 304d strb.w r3, [r4, #77] ; 0x4d + 800468c: e7d0 b.n 8004630 + 800468e: 7b61 ldrb r1, [r4, #13] + 8004690: 4628 mov r0, r5 + 8004692: f000 fe9d bl 80053d0 + 8004696: 2801 cmp r0, #1 + 8004698: d115 bne.n 80046c6 + 800469a: 6a63 ldr r3, [r4, #36] ; 0x24 + 800469c: 8b22 ldrh r2, [r4, #24] + 800469e: 4293 cmp r3, r2 + 80046a0: bf83 ittte hi + 80046a2: 1a9b subhi r3, r3, r2 + 80046a4: 6263 strhi r3, [r4, #36] ; 0x24 + 80046a6: 69e3 ldrhi r3, [r4, #28] + 80046a8: 2300 movls r3, #0 + 80046aa: bf8a itet hi + 80046ac: 189b addhi r3, r3, r2 + 80046ae: 6263 strls r3, [r4, #36] ; 0x24 + 80046b0: 61e3 strhi r3, [r4, #28] + 80046b2: 6a63 ldr r3, [r4, #36] ; 0x24 + 80046b4: b10b cbz r3, 80046ba + 80046b6: 2301 movs r3, #1 + 80046b8: e7e6 b.n 8004688 + 80046ba: f884 304d strb.w r3, [r4, #77] ; 0x4d + 80046be: 4628 mov r0, r5 + 80046c0: f7ff ff6a bl 8004598 + 80046c4: e7b4 b.n 8004630 + 80046c6: 2802 cmp r0, #2 + 80046c8: d1b2 bne.n 8004630 + 80046ca: e7f4 b.n 80046b6 + 80046cc: 7b33 ldrb r3, [r6, #12] + 80046ce: 8b72 ldrh r2, [r6, #26] + 80046d0: 6a31 ldr r1, [r6, #32] + 80046d2: 4628 mov r0, r5 + 80046d4: f000 fcf9 bl 80050ca + 80046d8: 2304 movs r3, #4 + 80046da: f886 304e strb.w r3, [r6, #78] ; 0x4e + 80046de: e77b b.n 80045d8 + 80046e0: 2300 movs r3, #0 + 80046e2: f886 304e strb.w r3, [r6, #78] ; 0x4e + 80046e6: 4628 mov r0, r5 + 80046e8: f7ff ff57 bl 800459a + 80046ec: e774 b.n 80045d8 + 80046ee: 2100 movs r1, #0 + 80046f0: f000 fc8f bl 8005012 + 80046f4: 2800 cmp r0, #0 + 80046f6: f47f af6f bne.w 80045d8 + 80046fa: f884 004c strb.w r0, [r4, #76] ; 0x4c + 80046fe: e76b b.n 80045d8 + 8004700: 2000 movs r0, #0 + 8004702: e76a b.n 80045da + +08004704 : + 8004704: f500 7361 add.w r3, r0, #900 ; 0x384 + 8004708: f500 7270 add.w r2, r0, #960 ; 0x3c0 + 800470c: 2100 movs r1, #0 + 800470e: f843 1b04 str.w r1, [r3], #4 + 8004712: 4293 cmp r3, r2 + 8004714: d1fb bne.n 800470e + 8004716: f500 728e add.w r2, r0, #284 ; 0x11c + 800471a: f500 7147 add.w r1, r0, #796 ; 0x31c + 800471e: 2300 movs r3, #0 + 8004720: f802 3b01 strb.w r3, [r2], #1 + 8004724: 4291 cmp r1, r2 + 8004726: d1fb bne.n 8004720 + 8004728: 2201 movs r2, #1 + 800472a: 7003 strb r3, [r0, #0] + 800472c: 7043 strb r3, [r0, #1] + 800472e: 7082 strb r2, [r0, #2] + 8004730: f8c0 33c4 str.w r3, [r0, #964] ; 0x3c4 + 8004734: 7602 strb r2, [r0, #24] + 8004736: 7643 strb r3, [r0, #25] + 8004738: 2240 movs r2, #64 ; 0x40 + 800473a: f44f 7380 mov.w r3, #256 ; 0x100 + 800473e: 7182 strb r2, [r0, #6] + 8004740: f8c0 331c str.w r3, [r0, #796] ; 0x31c + 8004744: 2000 movs r0, #0 + 8004746: 4770 bx lr + +08004748 : + 8004748: b570 push {r4, r5, r6, lr} + 800474a: 460e mov r6, r1 + 800474c: 4604 mov r4, r0 + 800474e: b1c0 cbz r0, 8004782 + 8004750: 2500 movs r5, #0 + 8004752: f880 23cc strb.w r2, [r0, #972] ; 0x3cc + 8004756: f8c0 537c str.w r5, [r0, #892] ; 0x37c + 800475a: f8c0 5380 str.w r5, [r0, #896] ; 0x380 + 800475e: f7ff ffd1 bl 8004704 + 8004762: f884 5320 strb.w r5, [r4, #800] ; 0x320 + 8004766: f884 5323 strb.w r5, [r4, #803] ; 0x323 + 800476a: f884 5321 strb.w r5, [r4, #801] ; 0x321 + 800476e: f884 5322 strb.w r5, [r4, #802] ; 0x322 + 8004772: b10e cbz r6, 8004778 + 8004774: f8c4 63d4 str.w r6, [r4, #980] ; 0x3d4 + 8004778: 4620 mov r0, r4 + 800477a: f000 fd87 bl 800528c + 800477e: 2000 movs r0, #0 + 8004780: bd70 pop {r4, r5, r6, pc} + 8004782: 2002 movs r0, #2 + 8004784: e7fc b.n 8004780 + +08004786 : + 8004786: b149 cbz r1, 800479c + 8004788: f8d0 3380 ldr.w r3, [r0, #896] ; 0x380 + 800478c: b933 cbnz r3, 800479c + 800478e: 2201 movs r2, #1 + 8004790: f8c0 2380 str.w r2, [r0, #896] ; 0x380 + 8004794: f8c0 1378 str.w r1, [r0, #888] ; 0x378 + 8004798: 4618 mov r0, r3 + 800479a: 4770 bx lr + 800479c: 2002 movs r0, #2 + 800479e: 4770 bx lr + +080047a0 : + 80047a0: f890 333c ldrb.w r3, [r0, #828] ; 0x33c + 80047a4: 428b cmp r3, r1 + 80047a6: bf86 itte hi + 80047a8: f880 1324 strbhi.w r1, [r0, #804] ; 0x324 + 80047ac: 2000 movhi r0, #0 + 80047ae: 2002 movls r0, #2 + 80047b0: 4770 bx lr + +080047b2 : + 80047b2: b570 push {r4, r5, r6, lr} + 80047b4: 2400 movs r4, #0 + 80047b6: f890 6347 ldrb.w r6, [r0, #839] ; 0x347 + 80047ba: 428e cmp r6, r1 + 80047bc: b2e5 uxtb r5, r4 + 80047be: d001 beq.n 80047c4 + 80047c0: 29ff cmp r1, #255 ; 0xff + 80047c2: d10b bne.n 80047dc + 80047c4: f890 6348 ldrb.w r6, [r0, #840] ; 0x348 + 80047c8: 4296 cmp r6, r2 + 80047ca: d001 beq.n 80047d0 + 80047cc: 2aff cmp r2, #255 ; 0xff + 80047ce: d105 bne.n 80047dc + 80047d0: f890 6349 ldrb.w r6, [r0, #841] ; 0x349 + 80047d4: 429e cmp r6, r3 + 80047d6: d004 beq.n 80047e2 + 80047d8: 2bff cmp r3, #255 ; 0xff + 80047da: d002 beq.n 80047e2 + 80047dc: 301a adds r0, #26 + 80047de: b114 cbz r4, 80047e6 + 80047e0: 25ff movs r5, #255 ; 0xff + 80047e2: 4628 mov r0, r5 + 80047e4: bd70 pop {r4, r5, r6, pc} + 80047e6: 2401 movs r4, #1 + 80047e8: e7e5 b.n 80047b6 + +080047ea : + 80047ea: b510 push {r4, lr} + 80047ec: 4604 mov r4, r0 + 80047ee: f000 fd73 bl 80052d8 + 80047f2: 2101 movs r1, #1 + 80047f4: 4620 mov r0, r4 + 80047f6: f000 fdef bl 80053d8 + 80047fa: 2000 movs r0, #0 + 80047fc: bd10 pop {r4, pc} + +080047fe : + 80047fe: b570 push {r4, r5, r6, lr} + 8004800: b086 sub sp, #24 + 8004802: 2302 movs r3, #2 + 8004804: f88d 3017 strb.w r3, [sp, #23] + 8004808: f890 3321 ldrb.w r3, [r0, #801] ; 0x321 + 800480c: 2b01 cmp r3, #1 + 800480e: bf04 itt eq + 8004810: 2303 moveq r3, #3 + 8004812: 7003 strbeq r3, [r0, #0] + 8004814: 7803 ldrb r3, [r0, #0] + 8004816: 4604 mov r4, r0 + 8004818: 2b0b cmp r3, #11 + 800481a: d81d bhi.n 8004858 + 800481c: e8df f013 tbh [pc, r3, lsl #1] + 8004820: 001f000c .word 0x001f000c + 8004824: 019b0041 .word 0x019b0041 + 8004828: 0076001c .word 0x0076001c + 800482c: 013f017f .word 0x013f017f + 8004830: 01500147 .word 0x01500147 + 8004834: 0193015c .word 0x0193015c + 8004838: f890 3320 ldrb.w r3, [r0, #800] ; 0x320 + 800483c: b163 cbz r3, 8004858 + 800483e: 2301 movs r3, #1 + 8004840: 7003 strb r3, [r0, #0] + 8004842: 20c8 movs r0, #200 ; 0xc8 + 8004844: f000 fde4 bl 8005410 + 8004848: 4620 mov r0, r4 + 800484a: f000 fd6f bl 800532c + 800484e: 2300 movs r3, #0 + 8004850: f884 331c strb.w r3, [r4, #796] ; 0x31c + 8004854: f8c4 33c8 str.w r3, [r4, #968] ; 0x3c8 + 8004858: 2000 movs r0, #0 + 800485a: b006 add sp, #24 + 800485c: bd70 pop {r4, r5, r6, pc} + 800485e: f890 3323 ldrb.w r3, [r0, #803] ; 0x323 + 8004862: 2b01 cmp r3, #1 + 8004864: d105 bne.n 8004872 + 8004866: 2300 movs r3, #0 + 8004868: f880 331f strb.w r3, [r0, #799] ; 0x31f + 800486c: 2302 movs r3, #2 + 800486e: 7023 strb r3, [r4, #0] + 8004870: e7f2 b.n 8004858 + 8004872: f8d0 33c8 ldr.w r3, [r0, #968] ; 0x3c8 + 8004876: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 + 800487a: d90b bls.n 8004894 + 800487c: f890 331f ldrb.w r3, [r0, #799] ; 0x31f + 8004880: 3301 adds r3, #1 + 8004882: b2db uxtb r3, r3 + 8004884: 2b03 cmp r3, #3 + 8004886: f880 331f strb.w r3, [r0, #799] ; 0x31f + 800488a: d901 bls.n 8004890 + 800488c: 230d movs r3, #13 + 800488e: e7ee b.n 800486e + 8004890: 2300 movs r3, #0 + 8004892: e7ec b.n 800486e + 8004894: 330a adds r3, #10 + 8004896: f8c0 33c8 str.w r3, [r0, #968] ; 0x3c8 + 800489a: 200a movs r0, #10 + 800489c: f000 fdb8 bl 8005410 + 80048a0: e7da b.n 8004858 + 80048a2: f8d0 33d4 ldr.w r3, [r0, #980] ; 0x3d4 + 80048a6: b10b cbz r3, 80048ac + 80048a8: 2104 movs r1, #4 + 80048aa: 4798 blx r3 + 80048ac: 2064 movs r0, #100 ; 0x64 + 80048ae: f000 fdaf bl 8005410 + 80048b2: 4620 mov r0, r4 + 80048b4: f000 fd2c bl 8005310 + 80048b8: 2305 movs r3, #5 + 80048ba: 7023 strb r3, [r4, #0] + 80048bc: f884 031d strb.w r0, [r4, #797] ; 0x31d + 80048c0: 2100 movs r1, #0 + 80048c2: 4620 mov r0, r4 + 80048c4: f000 fc25 bl 8005112 + 80048c8: 2180 movs r1, #128 ; 0x80 + 80048ca: 7160 strb r0, [r4, #5] + 80048cc: 4620 mov r0, r4 + 80048ce: f000 fc20 bl 8005112 + 80048d2: 79a2 ldrb r2, [r4, #6] + 80048d4: 9202 str r2, [sp, #8] + 80048d6: 2500 movs r5, #0 + 80048d8: f894 231d ldrb.w r2, [r4, #797] ; 0x31d + 80048dc: 7120 strb r0, [r4, #4] + 80048de: 4601 mov r1, r0 + 80048e0: f894 331c ldrb.w r3, [r4, #796] ; 0x31c + 80048e4: 9200 str r2, [sp, #0] + 80048e6: 9501 str r5, [sp, #4] + 80048e8: 2280 movs r2, #128 ; 0x80 + 80048ea: 4620 mov r0, r4 + 80048ec: f000 fbfd bl 80050ea + 80048f0: 79a2 ldrb r2, [r4, #6] + 80048f2: f894 331c ldrb.w r3, [r4, #796] ; 0x31c + 80048f6: 7961 ldrb r1, [r4, #5] + 80048f8: e9cd 5201 strd r5, r2, [sp, #4] + 80048fc: f894 231d ldrb.w r2, [r4, #797] ; 0x31d + 8004900: 9200 str r2, [sp, #0] + 8004902: 4620 mov r0, r4 + 8004904: 462a mov r2, r5 + 8004906: f000 fbf0 bl 80050ea + 800490a: e7a5 b.n 8004858 + 800490c: 7843 ldrb r3, [r0, #1] + 800490e: 2b07 cmp r3, #7 + 8004910: d82b bhi.n 800496a + 8004912: e8df f003 tbb [pc, r3] + 8004916: 4104 .short 0x4104 + 8004918: 866a6448 .word 0x866a6448 + 800491c: a294 .short 0xa294 + 800491e: 2108 movs r1, #8 + 8004920: f000 fa54 bl 8004dcc + 8004924: 4606 mov r6, r0 + 8004926: b9f0 cbnz r0, 8004966 + 8004928: f894 232d ldrb.w r2, [r4, #813] ; 0x32d + 800492c: 71a2 strb r2, [r4, #6] + 800492e: 2501 movs r5, #1 + 8004930: e9cd 0201 strd r0, r2, [sp, #4] + 8004934: f894 331c ldrb.w r3, [r4, #796] ; 0x31c + 8004938: f894 231d ldrb.w r2, [r4, #797] ; 0x31d + 800493c: 7921 ldrb r1, [r4, #4] + 800493e: 7065 strb r5, [r4, #1] + 8004940: 9200 str r2, [sp, #0] + 8004942: 2280 movs r2, #128 ; 0x80 + 8004944: 4620 mov r0, r4 + 8004946: f000 fbd0 bl 80050ea + 800494a: 79a2 ldrb r2, [r4, #6] + 800494c: f894 331c ldrb.w r3, [r4, #796] ; 0x31c + 8004950: 7961 ldrb r1, [r4, #5] + 8004952: e9cd 6201 strd r6, r2, [sp, #4] + 8004956: f894 231d ldrb.w r2, [r4, #797] ; 0x31d + 800495a: 9200 str r2, [sp, #0] + 800495c: 4620 mov r0, r4 + 800495e: 4632 mov r2, r6 + 8004960: f000 fbc3 bl 80050ea + 8004964: e001 b.n 800496a + 8004966: 2803 cmp r0, #3 + 8004968: d001 beq.n 800496e + 800496a: 2301 movs r3, #1 + 800496c: e079 b.n 8004a62 + 800496e: f894 331e ldrb.w r3, [r4, #798] ; 0x31e + 8004972: 3301 adds r3, #1 + 8004974: b2db uxtb r3, r3 + 8004976: 2b03 cmp r3, #3 + 8004978: f884 331e strb.w r3, [r4, #798] ; 0x31e + 800497c: d901 bls.n 8004982 + 800497e: 230d movs r3, #13 + 8004980: e008 b.n 8004994 + 8004982: 7961 ldrb r1, [r4, #5] + 8004984: 4620 mov r0, r4 + 8004986: f000 fbdc bl 8005142 + 800498a: 7921 ldrb r1, [r4, #4] + 800498c: 4620 mov r0, r4 + 800498e: f000 fbd8 bl 8005142 + 8004992: 2300 movs r3, #0 + 8004994: 7023 strb r3, [r4, #0] + 8004996: e7e8 b.n 800496a + 8004998: 2112 movs r1, #18 + 800499a: f000 fa17 bl 8004dcc + 800499e: bb58 cbnz r0, 80049f8 + 80049a0: 2302 movs r3, #2 + 80049a2: 7063 strb r3, [r4, #1] + 80049a4: e7e1 b.n 800496a + 80049a6: 2101 movs r1, #1 + 80049a8: f000 fb0c bl 8004fc4 + 80049ac: 4606 mov r6, r0 + 80049ae: b980 cbnz r0, 80049d2 + 80049b0: 2002 movs r0, #2 + 80049b2: f000 fd2d bl 8005410 + 80049b6: 2303 movs r3, #3 + 80049b8: 7063 strb r3, [r4, #1] + 80049ba: 79a3 ldrb r3, [r4, #6] + 80049bc: 7921 ldrb r1, [r4, #4] + 80049be: 2501 movs r5, #1 + 80049c0: e9cd 6301 strd r6, r3, [sp, #4] + 80049c4: f894 331d ldrb.w r3, [r4, #797] ; 0x31d + 80049c8: 9300 str r3, [sp, #0] + 80049ca: f884 531c strb.w r5, [r4, #796] ; 0x31c + 80049ce: 462b mov r3, r5 + 80049d0: e7b7 b.n 8004942 + 80049d2: 2803 cmp r0, #3 + 80049d4: d1c9 bne.n 800496a + 80049d6: 230d movs r3, #13 + 80049d8: 7023 strb r3, [r4, #0] + 80049da: 2300 movs r3, #0 + 80049dc: e7e1 b.n 80049a2 + 80049de: 2109 movs r1, #9 + 80049e0: f000 fa3c bl 8004e5c + 80049e4: b940 cbnz r0, 80049f8 + 80049e6: 2304 movs r3, #4 + 80049e8: e7db b.n 80049a2 + 80049ea: f8b0 133a ldrh.w r1, [r0, #826] ; 0x33a + 80049ee: f000 fa35 bl 8004e5c + 80049f2: b908 cbnz r0, 80049f8 + 80049f4: 2305 movs r3, #5 + 80049f6: e7d4 b.n 80049a2 + 80049f8: 2803 cmp r0, #3 + 80049fa: d1b6 bne.n 800496a + 80049fc: f894 331e ldrb.w r3, [r4, #798] ; 0x31e + 8004a00: 3301 adds r3, #1 + 8004a02: b2db uxtb r3, r3 + 8004a04: 2b03 cmp r3, #3 + 8004a06: f884 331e strb.w r3, [r4, #798] ; 0x31e + 8004a0a: d8b8 bhi.n 800497e + 8004a0c: 7961 ldrb r1, [r4, #5] + 8004a0e: 4620 mov r0, r4 + 8004a10: f000 fb97 bl 8005142 + 8004a14: 7921 ldrb r1, [r4, #4] + 8004a16: 4620 mov r0, r4 + 8004a18: f000 fb93 bl 8005142 + 8004a1c: 2300 movs r3, #0 + 8004a1e: 7063 strb r3, [r4, #1] + 8004a20: e7b8 b.n 8004994 + 8004a22: f890 1334 ldrb.w r1, [r0, #820] ; 0x334 + 8004a26: b129 cbz r1, 8004a34 + 8004a28: 23ff movs r3, #255 ; 0xff + 8004a2a: f500 728e add.w r2, r0, #284 ; 0x11c + 8004a2e: f000 faa2 bl 8004f76 + 8004a32: b908 cbnz r0, 8004a38 + 8004a34: 2306 movs r3, #6 + 8004a36: e7b4 b.n 80049a2 + 8004a38: 2803 cmp r0, #3 + 8004a3a: d196 bne.n 800496a + 8004a3c: e7fa b.n 8004a34 + 8004a3e: f890 1335 ldrb.w r1, [r0, #821] ; 0x335 + 8004a42: b129 cbz r1, 8004a50 + 8004a44: 23ff movs r3, #255 ; 0xff + 8004a46: f500 728e add.w r2, r0, #284 ; 0x11c + 8004a4a: f000 fa94 bl 8004f76 + 8004a4e: b908 cbnz r0, 8004a54 + 8004a50: 2307 movs r3, #7 + 8004a52: e7a6 b.n 80049a2 + 8004a54: 2803 cmp r0, #3 + 8004a56: d188 bne.n 800496a + 8004a58: e7fa b.n 8004a50 + 8004a5a: f890 1336 ldrb.w r1, [r0, #822] ; 0x336 + 8004a5e: b989 cbnz r1, 8004a84 + 8004a60: 2300 movs r3, #0 + 8004a62: f88d 3017 strb.w r3, [sp, #23] + 8004a66: f89d 3017 ldrb.w r3, [sp, #23] + 8004a6a: f003 02ff and.w r2, r3, #255 ; 0xff + 8004a6e: 2b00 cmp r3, #0 + 8004a70: f47f aef2 bne.w 8004858 + 8004a74: f894 3337 ldrb.w r3, [r4, #823] ; 0x337 + 8004a78: f884 2324 strb.w r2, [r4, #804] ; 0x324 + 8004a7c: 2b01 cmp r3, #1 + 8004a7e: d10c bne.n 8004a9a + 8004a80: 2308 movs r3, #8 + 8004a82: e6f4 b.n 800486e + 8004a84: 23ff movs r3, #255 ; 0xff + 8004a86: f500 728e add.w r2, r0, #284 ; 0x11c + 8004a8a: f000 fa74 bl 8004f76 + 8004a8e: 2800 cmp r0, #0 + 8004a90: d0e6 beq.n 8004a60 + 8004a92: 1ec3 subs r3, r0, #3 + 8004a94: bf18 it ne + 8004a96: 2301 movne r3, #1 + 8004a98: e7e3 b.n 8004a62 + 8004a9a: 2307 movs r3, #7 + 8004a9c: e6e7 b.n 800486e + 8004a9e: f8d0 33d4 ldr.w r3, [r0, #980] ; 0x3d4 + 8004aa2: 2b00 cmp r3, #0 + 8004aa4: f43f aed8 beq.w 8004858 + 8004aa8: 2101 movs r1, #1 + 8004aaa: 4798 blx r3 + 8004aac: e7e8 b.n 8004a80 + 8004aae: f890 133d ldrb.w r1, [r0, #829] ; 0x33d + 8004ab2: f000 fa94 bl 8004fde + 8004ab6: 2800 cmp r0, #0 + 8004ab8: f47f aece bne.w 8004858 + 8004abc: 2309 movs r3, #9 + 8004abe: e6d6 b.n 800486e + 8004ac0: f890 333f ldrb.w r3, [r0, #831] ; 0x33f + 8004ac4: 069b lsls r3, r3, #26 + 8004ac6: d505 bpl.n 8004ad4 + 8004ac8: 2101 movs r1, #1 + 8004aca: f000 fa95 bl 8004ff8 + 8004ace: 2800 cmp r0, #0 + 8004ad0: f47f aec2 bne.w 8004858 + 8004ad4: 230a movs r3, #10 + 8004ad6: e6ca b.n 800486e + 8004ad8: f8d0 3380 ldr.w r3, [r0, #896] ; 0x380 + 8004adc: 2b00 cmp r3, #0 + 8004ade: f43f aebb beq.w 8004858 + 8004ae2: 2300 movs r3, #0 + 8004ae4: f8c0 337c str.w r3, [r0, #892] ; 0x37c + 8004ae8: f8d0 3378 ldr.w r3, [r0, #888] ; 0x378 + 8004aec: f890 2347 ldrb.w r2, [r0, #839] ; 0x347 + 8004af0: 7919 ldrb r1, [r3, #4] + 8004af2: 4291 cmp r1, r2 + 8004af4: bf08 it eq + 8004af6: f8c0 337c streq.w r3, [r0, #892] ; 0x37c + 8004afa: f8d0 337c ldr.w r3, [r0, #892] ; 0x37c + 8004afe: 2b00 cmp r3, #0 + 8004b00: f43f aec4 beq.w 800488c + 8004b04: 689b ldr r3, [r3, #8] + 8004b06: 4798 blx r3 + 8004b08: 2800 cmp r0, #0 + 8004b0a: f47f aebf bne.w 800488c + 8004b0e: 2306 movs r3, #6 + 8004b10: 7023 strb r3, [r4, #0] + 8004b12: 2103 movs r1, #3 + 8004b14: f8d4 33d4 ldr.w r3, [r4, #980] ; 0x3d4 + 8004b18: 4620 mov r0, r4 + 8004b1a: 4798 blx r3 + 8004b1c: e69c b.n 8004858 + 8004b1e: f8d0 337c ldr.w r3, [r0, #892] ; 0x37c + 8004b22: 2b00 cmp r3, #0 + 8004b24: f43f aeb2 beq.w 800488c + 8004b28: 691b ldr r3, [r3, #16] + 8004b2a: 4798 blx r3 + 8004b2c: f88d 0017 strb.w r0, [sp, #23] + 8004b30: f89d 3017 ldrb.w r3, [sp, #23] + 8004b34: b90b cbnz r3, 8004b3a + 8004b36: 230b movs r3, #11 + 8004b38: e699 b.n 800486e + 8004b3a: f89d 3017 ldrb.w r3, [sp, #23] + 8004b3e: 2b02 cmp r3, #2 + 8004b40: f47f ae8a bne.w 8004858 + 8004b44: e6a2 b.n 800488c + 8004b46: f8d0 337c ldr.w r3, [r0, #892] ; 0x37c + 8004b4a: 2b00 cmp r3, #0 + 8004b4c: f43f ae84 beq.w 8004858 + 8004b50: 695b ldr r3, [r3, #20] + 8004b52: 4798 blx r3 + 8004b54: e680 b.n 8004858 + 8004b56: 2500 movs r5, #0 + 8004b58: f880 5321 strb.w r5, [r0, #801] ; 0x321 + 8004b5c: f7ff fdd2 bl 8004704 + 8004b60: f8d4 337c ldr.w r3, [r4, #892] ; 0x37c + 8004b64: b123 cbz r3, 8004b70 + 8004b66: 68db ldr r3, [r3, #12] + 8004b68: 4620 mov r0, r4 + 8004b6a: 4798 blx r3 + 8004b6c: f8c4 537c str.w r5, [r4, #892] ; 0x37c + 8004b70: f8d4 33d4 ldr.w r3, [r4, #980] ; 0x3d4 + 8004b74: b113 cbz r3, 8004b7c + 8004b76: 2105 movs r1, #5 + 8004b78: 4620 mov r0, r4 + 8004b7a: 4798 blx r3 + 8004b7c: f894 3322 ldrb.w r3, [r4, #802] ; 0x322 + 8004b80: 2b01 cmp r3, #1 + 8004b82: d106 bne.n 8004b92 + 8004b84: 2300 movs r3, #0 + 8004b86: f884 3322 strb.w r3, [r4, #802] ; 0x322 + 8004b8a: 4620 mov r0, r4 + 8004b8c: f7ff fe2d bl 80047ea + 8004b90: e662 b.n 8004858 + 8004b92: 4620 mov r0, r4 + 8004b94: f000 fba0 bl 80052d8 + 8004b98: e65e b.n 8004858 + +08004b9a : + 8004b9a: f8c0 13c4 str.w r1, [r0, #964] ; 0x3c4 + 8004b9e: 4770 bx lr + +08004ba0 : + 8004ba0: f8d0 23c4 ldr.w r2, [r0, #964] ; 0x3c4 + 8004ba4: 3201 adds r2, #1 + 8004ba6: f8c0 23c4 str.w r2, [r0, #964] ; 0x3c4 + 8004baa: 7802 ldrb r2, [r0, #0] + 8004bac: 2a0b cmp r2, #11 + 8004bae: d104 bne.n 8004bba + 8004bb0: f8d0 337c ldr.w r3, [r0, #892] ; 0x37c + 8004bb4: b10b cbz r3, 8004bba + 8004bb6: 699b ldr r3, [r3, #24] + 8004bb8: 4718 bx r3 + 8004bba: 4770 bx lr + +08004bbc : + 8004bbc: 2301 movs r3, #1 + 8004bbe: f880 3323 strb.w r3, [r0, #803] ; 0x323 + 8004bc2: 4770 bx lr + +08004bc4 : + 8004bc4: 2300 movs r3, #0 + 8004bc6: f880 3323 strb.w r3, [r0, #803] ; 0x323 + 8004bca: 4770 bx lr + +08004bcc : + 8004bcc: 2301 movs r3, #1 + 8004bce: f880 3320 strb.w r3, [r0, #800] ; 0x320 + 8004bd2: 2300 movs r3, #0 + 8004bd4: f880 3321 strb.w r3, [r0, #801] ; 0x321 + 8004bd8: f880 3322 strb.w r3, [r0, #802] ; 0x322 + 8004bdc: 4618 mov r0, r3 + 8004bde: 4770 bx lr + +08004be0 : + 8004be0: b538 push {r3, r4, r5, lr} + 8004be2: 4604 mov r4, r0 + 8004be4: 2301 movs r3, #1 + 8004be6: 2500 movs r5, #0 + 8004be8: f880 3321 strb.w r3, [r0, #801] ; 0x321 + 8004bec: f880 5323 strb.w r5, [r0, #803] ; 0x323 + 8004bf0: f880 5320 strb.w r5, [r0, #800] ; 0x320 + 8004bf4: f000 fb7e bl 80052f4 + 8004bf8: 7921 ldrb r1, [r4, #4] + 8004bfa: 4620 mov r0, r4 + 8004bfc: f000 faa1 bl 8005142 + 8004c00: 7961 ldrb r1, [r4, #5] + 8004c02: 4620 mov r0, r4 + 8004c04: f000 fa9d bl 8005142 + 8004c08: 4628 mov r0, r5 + 8004c0a: bd38 pop {r3, r4, r5, pc} + +08004c0c : + 8004c0c: b537 push {r0, r1, r2, r4, r5, lr} + 8004c0e: 4604 mov r4, r0 + 8004c10: 7880 ldrb r0, [r0, #2] + 8004c12: 2801 cmp r0, #1 + 8004c14: d003 beq.n 8004c1e + 8004c16: 2802 cmp r0, #2 + 8004c18: d008 beq.n 8004c2c + 8004c1a: 2001 movs r0, #1 + 8004c1c: e004 b.n 8004c28 + 8004c1e: 2302 movs r3, #2 + 8004c20: 60a1 str r1, [r4, #8] + 8004c22: 81a2 strh r2, [r4, #12] + 8004c24: 7620 strb r0, [r4, #24] + 8004c26: 70a3 strb r3, [r4, #2] + 8004c28: b003 add sp, #12 + 8004c2a: bd30 pop {r4, r5, pc} + 8004c2c: 7e23 ldrb r3, [r4, #24] + 8004c2e: 3b01 subs r3, #1 + 8004c30: 2101 movs r1, #1 + 8004c32: 2b0a cmp r3, #10 + 8004c34: d8f1 bhi.n 8004c1a + 8004c36: e8df f003 tbb [pc, r3] + 8004c3a: 0f06 .short 0x0f06 + 8004c3c: 4d41372c .word 0x4d41372c + 8004c40: 897d6f64 .word 0x897d6f64 + 8004c44: 92 .byte 0x92 + 8004c45: 00 .byte 0x00 + 8004c46: 7962 ldrb r2, [r4, #5] + 8004c48: f104 0110 add.w r1, r4, #16 + 8004c4c: 4620 mov r0, r4 + 8004c4e: f000 f9ed bl 800502c + 8004c52: 2302 movs r3, #2 + 8004c54: 7623 strb r3, [r4, #24] + 8004c56: e7e0 b.n 8004c1a + 8004c58: 7961 ldrb r1, [r4, #5] + 8004c5a: 4620 mov r0, r4 + 8004c5c: f000 fbb8 bl 80053d0 + 8004c60: 2801 cmp r0, #1 + 8004c62: d110 bne.n 8004c86 + 8004c64: 8ae2 ldrh r2, [r4, #22] + 8004c66: f994 3010 ldrsb.w r3, [r4, #16] + 8004c6a: b132 cbz r2, 8004c7a + 8004c6c: 2b00 cmp r3, #0 + 8004c6e: da02 bge.n 8004c76 + 8004c70: 2303 movs r3, #3 + 8004c72: 7623 strb r3, [r4, #24] + 8004c74: e7d8 b.n 8004c28 + 8004c76: 2305 movs r3, #5 + 8004c78: e7ec b.n 8004c54 + 8004c7a: 2b00 cmp r3, #0 + 8004c7c: da01 bge.n 8004c82 + 8004c7e: 2309 movs r3, #9 + 8004c80: e7e8 b.n 8004c54 + 8004c82: 2307 movs r3, #7 + 8004c84: e7e6 b.n 8004c54 + 8004c86: 2804 cmp r0, #4 + 8004c88: d001 beq.n 8004c8e + 8004c8a: 2802 cmp r0, #2 + 8004c8c: d1c5 bne.n 8004c1a + 8004c8e: 230b movs r3, #11 + 8004c90: e7e0 b.n 8004c54 + 8004c92: f8d4 33c4 ldr.w r3, [r4, #964] ; 0x3c4 + 8004c96: 81e3 strh r3, [r4, #14] + 8004c98: 89a2 ldrh r2, [r4, #12] + 8004c9a: 7923 ldrb r3, [r4, #4] + 8004c9c: 68a1 ldr r1, [r4, #8] + 8004c9e: 4620 mov r0, r4 + 8004ca0: f000 f9ec bl 800507c + 8004ca4: 2304 movs r3, #4 + 8004ca6: e7d5 b.n 8004c54 + 8004ca8: 7921 ldrb r1, [r4, #4] + 8004caa: 4620 mov r0, r4 + 8004cac: f000 fb90 bl 80053d0 + 8004cb0: 2801 cmp r0, #1 + 8004cb2: d0e4 beq.n 8004c7e + 8004cb4: 2805 cmp r0, #5 + 8004cb6: d015 beq.n 8004ce4 + 8004cb8: 2804 cmp r0, #4 + 8004cba: e7e7 b.n 8004c8c + 8004cbc: 7963 ldrb r3, [r4, #5] + 8004cbe: 9100 str r1, [sp, #0] + 8004cc0: 89a2 ldrh r2, [r4, #12] + 8004cc2: 68a1 ldr r1, [r4, #8] + 8004cc4: 4620 mov r0, r4 + 8004cc6: f000 f9c2 bl 800504e + 8004cca: f8d4 33c4 ldr.w r3, [r4, #964] ; 0x3c4 + 8004cce: 81e3 strh r3, [r4, #14] + 8004cd0: 2306 movs r3, #6 + 8004cd2: e7bf b.n 8004c54 + 8004cd4: 7961 ldrb r1, [r4, #5] + 8004cd6: 4620 mov r0, r4 + 8004cd8: f000 fb7a bl 80053d0 + 8004cdc: 2801 cmp r0, #1 + 8004cde: d0d0 beq.n 8004c82 + 8004ce0: 2805 cmp r0, #5 + 8004ce2: d104 bne.n 8004cee + 8004ce4: 2003 movs r0, #3 + 8004ce6: 2301 movs r3, #1 + 8004ce8: 70a3 strb r3, [r4, #2] + 8004cea: 2300 movs r3, #0 + 8004cec: e7c1 b.n 8004c72 + 8004cee: 2802 cmp r0, #2 + 8004cf0: d0c1 beq.n 8004c76 + 8004cf2: 2804 cmp r0, #4 + 8004cf4: d191 bne.n 8004c1a + 8004cf6: 230b movs r3, #11 + 8004cf8: 7623 strb r3, [r4, #24] + 8004cfa: 2301 movs r3, #1 + 8004cfc: 70a3 strb r3, [r4, #2] + 8004cfe: 2002 movs r0, #2 + 8004d00: e792 b.n 8004c28 + 8004d02: 2200 movs r2, #0 + 8004d04: 7923 ldrb r3, [r4, #4] + 8004d06: 4611 mov r1, r2 + 8004d08: 4620 mov r0, r4 + 8004d0a: f000 f9b7 bl 800507c + 8004d0e: f8d4 33c4 ldr.w r3, [r4, #964] ; 0x3c4 + 8004d12: 81e3 strh r3, [r4, #14] + 8004d14: 2308 movs r3, #8 + 8004d16: e79d b.n 8004c54 + 8004d18: 7921 ldrb r1, [r4, #4] + 8004d1a: 4620 mov r0, r4 + 8004d1c: f000 fb58 bl 80053d0 + 8004d20: 2801 cmp r0, #1 + 8004d22: d101 bne.n 8004d28 + 8004d24: 2000 movs r0, #0 + 8004d26: e7de b.n 8004ce6 + 8004d28: 2804 cmp r0, #4 + 8004d2a: d0b0 beq.n 8004c8e + 8004d2c: 2805 cmp r0, #5 + 8004d2e: f47f af74 bne.w 8004c1a + 8004d32: e7d7 b.n 8004ce4 + 8004d34: 2200 movs r2, #0 + 8004d36: 7963 ldrb r3, [r4, #5] + 8004d38: 9100 str r1, [sp, #0] + 8004d3a: 4620 mov r0, r4 + 8004d3c: 4611 mov r1, r2 + 8004d3e: f000 f986 bl 800504e + 8004d42: f8d4 33c4 ldr.w r3, [r4, #964] ; 0x3c4 + 8004d46: 81e3 strh r3, [r4, #14] + 8004d48: 230a movs r3, #10 + 8004d4a: e783 b.n 8004c54 + 8004d4c: 7961 ldrb r1, [r4, #5] + 8004d4e: 4620 mov r0, r4 + 8004d50: f000 fb3e bl 80053d0 + 8004d54: 2801 cmp r0, #1 + 8004d56: d0e5 beq.n 8004d24 + 8004d58: 2802 cmp r0, #2 + 8004d5a: d1ad bne.n 8004cb8 + 8004d5c: e78f b.n 8004c7e + 8004d5e: 7e63 ldrb r3, [r4, #25] + 8004d60: 3301 adds r3, #1 + 8004d62: b2db uxtb r3, r3 + 8004d64: 2b02 cmp r3, #2 + 8004d66: 7663 strb r3, [r4, #25] + 8004d68: d803 bhi.n 8004d72 + 8004d6a: 2001 movs r0, #1 + 8004d6c: 7620 strb r0, [r4, #24] + 8004d6e: 70a0 strb r0, [r4, #2] + 8004d70: e75a b.n 8004c28 + 8004d72: f8d4 33d4 ldr.w r3, [r4, #980] ; 0x3d4 + 8004d76: 2106 movs r1, #6 + 8004d78: 4620 mov r0, r4 + 8004d7a: 2500 movs r5, #0 + 8004d7c: 4798 blx r3 + 8004d7e: 7961 ldrb r1, [r4, #5] + 8004d80: 7665 strb r5, [r4, #25] + 8004d82: 4620 mov r0, r4 + 8004d84: f000 f9dd bl 8005142 + 8004d88: 7921 ldrb r1, [r4, #4] + 8004d8a: 4620 mov r0, r4 + 8004d8c: f000 f9d9 bl 8005142 + 8004d90: 7025 strb r5, [r4, #0] + 8004d92: e7b2 b.n 8004cfa + +08004d94 : + 8004d94: b430 push {r4, r5} + 8004d96: 7884 ldrb r4, [r0, #2] + 8004d98: f8bd 5008 ldrh.w r5, [sp, #8] + 8004d9c: 2c01 cmp r4, #1 + 8004d9e: d110 bne.n 8004dc2 + 8004da0: f061 047f orn r4, r1, #127 ; 0x7f + 8004da4: 7404 strb r4, [r0, #16] + 8004da6: f402 447f and.w r4, r2, #65280 ; 0xff00 + 8004daa: f5b4 7f40 cmp.w r4, #768 ; 0x300 + 8004dae: 8242 strh r2, [r0, #18] + 8004db0: f04f 0106 mov.w r1, #6 + 8004db4: bf0c ite eq + 8004db6: f240 4209 movweq r2, #1033 ; 0x409 + 8004dba: 2200 movne r2, #0 + 8004dbc: 7441 strb r1, [r0, #17] + 8004dbe: 8282 strh r2, [r0, #20] + 8004dc0: 82c5 strh r5, [r0, #22] + 8004dc2: 462a mov r2, r5 + 8004dc4: 4619 mov r1, r3 + 8004dc6: bc30 pop {r4, r5} + 8004dc8: f7ff bf20 b.w 8004c0c + +08004dcc : + 8004dcc: b537 push {r0, r1, r2, r4, r5, lr} + 8004dce: f500 738e add.w r3, r0, #284 ; 0x11c + 8004dd2: 460d mov r5, r1 + 8004dd4: 9100 str r1, [sp, #0] + 8004dd6: f44f 7280 mov.w r2, #256 ; 0x100 + 8004dda: 2100 movs r1, #0 + 8004ddc: 4604 mov r4, r0 + 8004dde: f7ff ffd9 bl 8004d94 + 8004de2: bbc8 cbnz r0, 8004e58 + 8004de4: f894 311c ldrb.w r3, [r4, #284] ; 0x11c + 8004de8: f884 3326 strb.w r3, [r4, #806] ; 0x326 + 8004dec: f894 311d ldrb.w r3, [r4, #285] ; 0x11d + 8004df0: f884 3327 strb.w r3, [r4, #807] ; 0x327 + 8004df4: f8b4 311e ldrh.w r3, [r4, #286] ; 0x11e + 8004df8: f8a4 3328 strh.w r3, [r4, #808] ; 0x328 + 8004dfc: f894 3120 ldrb.w r3, [r4, #288] ; 0x120 + 8004e00: f884 332a strb.w r3, [r4, #810] ; 0x32a + 8004e04: f894 3121 ldrb.w r3, [r4, #289] ; 0x121 + 8004e08: f884 332b strb.w r3, [r4, #811] ; 0x32b + 8004e0c: f894 3122 ldrb.w r3, [r4, #290] ; 0x122 + 8004e10: f884 332c strb.w r3, [r4, #812] ; 0x32c + 8004e14: 2d08 cmp r5, #8 + 8004e16: f894 3123 ldrb.w r3, [r4, #291] ; 0x123 + 8004e1a: f884 332d strb.w r3, [r4, #813] ; 0x32d + 8004e1e: d91b bls.n 8004e58 + 8004e20: f8b4 3124 ldrh.w r3, [r4, #292] ; 0x124 + 8004e24: f8a4 332e strh.w r3, [r4, #814] ; 0x32e + 8004e28: f8b4 3126 ldrh.w r3, [r4, #294] ; 0x126 + 8004e2c: f8a4 3330 strh.w r3, [r4, #816] ; 0x330 + 8004e30: f8b4 3128 ldrh.w r3, [r4, #296] ; 0x128 + 8004e34: f8a4 3332 strh.w r3, [r4, #818] ; 0x332 + 8004e38: f894 312a ldrb.w r3, [r4, #298] ; 0x12a + 8004e3c: f884 3334 strb.w r3, [r4, #820] ; 0x334 + 8004e40: f894 312b ldrb.w r3, [r4, #299] ; 0x12b + 8004e44: f884 3335 strb.w r3, [r4, #821] ; 0x335 + 8004e48: f894 312c ldrb.w r3, [r4, #300] ; 0x12c + 8004e4c: f884 3336 strb.w r3, [r4, #822] ; 0x336 + 8004e50: f894 312d ldrb.w r3, [r4, #301] ; 0x12d + 8004e54: f884 3337 strb.w r3, [r4, #823] ; 0x337 + 8004e58: b003 add sp, #12 + 8004e5a: bd30 pop {r4, r5, pc} + +08004e5c : + 8004e5c: e92d 43f7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr} + 8004e60: f100 041c add.w r4, r0, #28 + 8004e64: 460e mov r6, r1 + 8004e66: 9100 str r1, [sp, #0] + 8004e68: 4623 mov r3, r4 + 8004e6a: f44f 7200 mov.w r2, #512 ; 0x200 + 8004e6e: 2100 movs r1, #0 + 8004e70: 4605 mov r5, r0 + 8004e72: f7ff ff8f bl 8004d94 + 8004e76: bb40 cbnz r0, 8004eca + 8004e78: 7f2b ldrb r3, [r5, #28] + 8004e7a: f885 3338 strb.w r3, [r5, #824] ; 0x338 + 8004e7e: 7f6b ldrb r3, [r5, #29] + 8004e80: f885 3339 strb.w r3, [r5, #825] ; 0x339 + 8004e84: f895 3020 ldrb.w r3, [r5, #32] + 8004e88: f885 333c strb.w r3, [r5, #828] ; 0x33c + 8004e8c: f895 3021 ldrb.w r3, [r5, #33] ; 0x21 + 8004e90: f885 333d strb.w r3, [r5, #829] ; 0x33d + 8004e94: f895 3022 ldrb.w r3, [r5, #34] ; 0x22 + 8004e98: f885 333e strb.w r3, [r5, #830] ; 0x33e + 8004e9c: f895 3023 ldrb.w r3, [r5, #35] ; 0x23 + 8004ea0: f8b5 c01e ldrh.w ip, [r5, #30] + 8004ea4: f885 333f strb.w r3, [r5, #831] ; 0x33f + 8004ea8: 2e09 cmp r6, #9 + 8004eaa: f895 3024 ldrb.w r3, [r5, #36] ; 0x24 + 8004eae: f8a5 c33a strh.w ip, [r5, #826] ; 0x33a + 8004eb2: f885 3340 strb.w r3, [r5, #832] ; 0x340 + 8004eb6: d908 bls.n 8004eca + 8004eb8: 462b mov r3, r5 + 8004eba: 4607 mov r7, r0 + 8004ebc: 2209 movs r2, #9 + 8004ebe: f04f 0e1a mov.w lr, #26 + 8004ec2: 2f02 cmp r7, #2 + 8004ec4: d001 beq.n 8004eca + 8004ec6: 4594 cmp ip, r2 + 8004ec8: d802 bhi.n 8004ed0 + 8004eca: b003 add sp, #12 + 8004ecc: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} + 8004ed0: 7821 ldrb r1, [r4, #0] + 8004ed2: 440c add r4, r1 + 8004ed4: 440a add r2, r1 + 8004ed6: 7861 ldrb r1, [r4, #1] + 8004ed8: 2904 cmp r1, #4 + 8004eda: b292 uxth r2, r2 + 8004edc: d1f1 bne.n 8004ec2 + 8004ede: 7821 ldrb r1, [r4, #0] + 8004ee0: f883 1342 strb.w r1, [r3, #834] ; 0x342 + 8004ee4: 7861 ldrb r1, [r4, #1] + 8004ee6: f883 1343 strb.w r1, [r3, #835] ; 0x343 + 8004eea: 78a1 ldrb r1, [r4, #2] + 8004eec: f883 1344 strb.w r1, [r3, #836] ; 0x344 + 8004ef0: 78e1 ldrb r1, [r4, #3] + 8004ef2: f883 1345 strb.w r1, [r3, #837] ; 0x345 + 8004ef6: 7921 ldrb r1, [r4, #4] + 8004ef8: f883 1346 strb.w r1, [r3, #838] ; 0x346 + 8004efc: 7961 ldrb r1, [r4, #5] + 8004efe: f883 1347 strb.w r1, [r3, #839] ; 0x347 + 8004f02: 79a1 ldrb r1, [r4, #6] + 8004f04: f883 1348 strb.w r1, [r3, #840] ; 0x348 + 8004f08: 79e1 ldrb r1, [r4, #7] + 8004f0a: f883 1349 strb.w r1, [r3, #841] ; 0x349 + 8004f0e: 7a21 ldrb r1, [r4, #8] + 8004f10: f883 134a strb.w r1, [r3, #842] ; 0x34a + 8004f14: fb0e f807 mul.w r8, lr, r7 + 8004f18: 2100 movs r1, #0 + 8004f1a: f893 6346 ldrb.w r6, [r3, #838] ; 0x346 + 8004f1e: 428e cmp r6, r1 + 8004f20: d901 bls.n 8004f26 + 8004f22: 4594 cmp ip, r2 + 8004f24: d802 bhi.n 8004f2c + 8004f26: 3701 adds r7, #1 + 8004f28: 331a adds r3, #26 + 8004f2a: e7ca b.n 8004ec2 + 8004f2c: 7826 ldrb r6, [r4, #0] + 8004f2e: 4434 add r4, r6 + 8004f30: 4432 add r2, r6 + 8004f32: 7866 ldrb r6, [r4, #1] + 8004f34: 2e05 cmp r6, #5 + 8004f36: b292 uxth r2, r2 + 8004f38: d1ef bne.n 8004f1a + 8004f3a: 1c4e adds r6, r1, #1 + 8004f3c: eb08 01c6 add.w r1, r8, r6, lsl #3 + 8004f40: 4429 add r1, r5 + 8004f42: f894 9000 ldrb.w r9, [r4] + 8004f46: f881 9344 strb.w r9, [r1, #836] ; 0x344 + 8004f4a: f894 9001 ldrb.w r9, [r4, #1] + 8004f4e: f881 9345 strb.w r9, [r1, #837] ; 0x345 + 8004f52: f894 9002 ldrb.w r9, [r4, #2] + 8004f56: f881 9346 strb.w r9, [r1, #838] ; 0x346 + 8004f5a: f894 9003 ldrb.w r9, [r4, #3] + 8004f5e: f881 9347 strb.w r9, [r1, #839] ; 0x347 + 8004f62: f8b4 9004 ldrh.w r9, [r4, #4] + 8004f66: f8a1 9348 strh.w r9, [r1, #840] ; 0x348 + 8004f6a: f894 9006 ldrb.w r9, [r4, #6] + 8004f6e: f881 934a strb.w r9, [r1, #842] ; 0x34a + 8004f72: b2f1 uxtb r1, r6 + 8004f74: e7d1 b.n 8004f1a + +08004f76 : + 8004f76: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} + 8004f78: f500 758e add.w r5, r0, #284 ; 0x11c + 8004f7c: 4614 mov r4, r2 + 8004f7e: 461f mov r7, r3 + 8004f80: 9300 str r3, [sp, #0] + 8004f82: f441 7240 orr.w r2, r1, #768 ; 0x300 + 8004f86: 462b mov r3, r5 + 8004f88: 2100 movs r1, #0 + 8004f8a: 4606 mov r6, r0 + 8004f8c: f7ff ff02 bl 8004d94 + 8004f90: b978 cbnz r0, 8004fb2 + 8004f92: f896 311d ldrb.w r3, [r6, #285] ; 0x11d + 8004f96: 2b03 cmp r3, #3 + 8004f98: d10b bne.n 8004fb2 + 8004f9a: f896 311c ldrb.w r3, [r6, #284] ; 0x11c + 8004f9e: 3b02 subs r3, #2 + 8004fa0: 42bb cmp r3, r7 + 8004fa2: bf28 it cs + 8004fa4: 463b movcs r3, r7 + 8004fa6: b29b uxth r3, r3 + 8004fa8: 4602 mov r2, r0 + 8004faa: 4293 cmp r3, r2 + 8004fac: d803 bhi.n 8004fb6 + 8004fae: 2300 movs r3, #0 + 8004fb0: 7023 strb r3, [r4, #0] + 8004fb2: b003 add sp, #12 + 8004fb4: bdf0 pop {r4, r5, r6, r7, pc} + 8004fb6: 18a9 adds r1, r5, r2 + 8004fb8: 3202 adds r2, #2 + 8004fba: 7889 ldrb r1, [r1, #2] + 8004fbc: f804 1b01 strb.w r1, [r4], #1 + 8004fc0: b292 uxth r2, r2 + 8004fc2: e7f2 b.n 8004faa + +08004fc4 : + 8004fc4: 7883 ldrb r3, [r0, #2] + 8004fc6: 2b01 cmp r3, #1 + 8004fc8: d105 bne.n 8004fd6 + 8004fca: f44f 63a0 mov.w r3, #1280 ; 0x500 + 8004fce: 8203 strh r3, [r0, #16] + 8004fd0: 2300 movs r3, #0 + 8004fd2: 8241 strh r1, [r0, #18] + 8004fd4: 6143 str r3, [r0, #20] + 8004fd6: 2200 movs r2, #0 + 8004fd8: 4611 mov r1, r2 + 8004fda: f7ff be17 b.w 8004c0c + +08004fde : + 8004fde: 7883 ldrb r3, [r0, #2] + 8004fe0: 2b01 cmp r3, #1 + 8004fe2: d105 bne.n 8004ff0 + 8004fe4: f44f 6310 mov.w r3, #2304 ; 0x900 + 8004fe8: 8203 strh r3, [r0, #16] + 8004fea: 2300 movs r3, #0 + 8004fec: 8241 strh r1, [r0, #18] + 8004fee: 6143 str r3, [r0, #20] + 8004ff0: 2200 movs r2, #0 + 8004ff2: 4611 mov r1, r2 + 8004ff4: f7ff be0a b.w 8004c0c + +08004ff8 : + 8004ff8: 7883 ldrb r3, [r0, #2] + 8004ffa: 2b01 cmp r3, #1 + 8004ffc: d105 bne.n 800500a + 8004ffe: f44f 7340 mov.w r3, #768 ; 0x300 + 8005002: 8203 strh r3, [r0, #16] + 8005004: 2300 movs r3, #0 + 8005006: 8241 strh r1, [r0, #18] + 8005008: 6143 str r3, [r0, #20] + 800500a: 2200 movs r2, #0 + 800500c: 4611 mov r1, r2 + 800500e: f7ff bdfd b.w 8004c0c + +08005012 : + 8005012: 7883 ldrb r3, [r0, #2] + 8005014: 2b01 cmp r3, #1 + 8005016: d105 bne.n 8005024 + 8005018: f44f 7381 mov.w r3, #258 ; 0x102 + 800501c: 6103 str r3, [r0, #16] + 800501e: 2300 movs r3, #0 + 8005020: 8281 strh r1, [r0, #20] + 8005022: 82c3 strh r3, [r0, #22] + 8005024: 2200 movs r2, #0 + 8005026: 4611 mov r1, r2 + 8005028: f7ff bdf0 b.w 8004c0c + +0800502c : + 800502c: b530 push {r4, r5, lr} + 800502e: 2308 movs r3, #8 + 8005030: b085 sub sp, #20 + 8005032: 2400 movs r4, #0 + 8005034: 4615 mov r5, r2 + 8005036: e9cd 3402 strd r3, r4, [sp, #8] + 800503a: e9cd 4100 strd r4, r1, [sp] + 800503e: 4623 mov r3, r4 + 8005040: 4622 mov r2, r4 + 8005042: 4629 mov r1, r5 + 8005044: f000 f9aa bl 800539c + 8005048: 4620 mov r0, r4 + 800504a: b005 add sp, #20 + 800504c: bd30 pop {r4, r5, pc} + +0800504e : + 800504e: b530 push {r4, r5, lr} + 8005050: b085 sub sp, #20 + 8005052: f890 531d ldrb.w r5, [r0, #797] ; 0x31d + 8005056: 9101 str r1, [sp, #4] + 8005058: 461c mov r4, r3 + 800505a: 2d00 cmp r5, #0 + 800505c: f89d 3020 ldrb.w r3, [sp, #32] + 8005060: bf18 it ne + 8005062: 2300 movne r3, #0 + 8005064: e9cd 2302 strd r2, r3, [sp, #8] + 8005068: 2301 movs r3, #1 + 800506a: 9300 str r3, [sp, #0] + 800506c: 2300 movs r3, #0 + 800506e: 461a mov r2, r3 + 8005070: 4621 mov r1, r4 + 8005072: f000 f993 bl 800539c + 8005076: 2000 movs r0, #0 + 8005078: b005 add sp, #20 + 800507a: bd30 pop {r4, r5, pc} + +0800507c : + 800507c: b530 push {r4, r5, lr} + 800507e: 2400 movs r4, #0 + 8005080: b085 sub sp, #20 + 8005082: 461d mov r5, r3 + 8005084: e9cd 2402 strd r2, r4, [sp, #8] + 8005088: 2201 movs r2, #1 + 800508a: 9101 str r1, [sp, #4] + 800508c: 9200 str r2, [sp, #0] + 800508e: 4623 mov r3, r4 + 8005090: 4629 mov r1, r5 + 8005092: f000 f983 bl 800539c + 8005096: 4620 mov r0, r4 + 8005098: b005 add sp, #20 + 800509a: bd30 pop {r4, r5, pc} + +0800509c : + 800509c: b530 push {r4, r5, lr} + 800509e: b085 sub sp, #20 + 80050a0: f890 531d ldrb.w r5, [r0, #797] ; 0x31d + 80050a4: 9101 str r1, [sp, #4] + 80050a6: 461c mov r4, r3 + 80050a8: 2d00 cmp r5, #0 + 80050aa: f89d 3020 ldrb.w r3, [sp, #32] + 80050ae: bf18 it ne + 80050b0: 2300 movne r3, #0 + 80050b2: e9cd 2302 strd r2, r3, [sp, #8] + 80050b6: 2301 movs r3, #1 + 80050b8: 9300 str r3, [sp, #0] + 80050ba: 2200 movs r2, #0 + 80050bc: 2302 movs r3, #2 + 80050be: 4621 mov r1, r4 + 80050c0: f000 f96c bl 800539c + 80050c4: 2000 movs r0, #0 + 80050c6: b005 add sp, #20 + 80050c8: bd30 pop {r4, r5, pc} + +080050ca : + 80050ca: b530 push {r4, r5, lr} + 80050cc: 2400 movs r4, #0 + 80050ce: b085 sub sp, #20 + 80050d0: 461d mov r5, r3 + 80050d2: e9cd 2402 strd r2, r4, [sp, #8] + 80050d6: 2201 movs r2, #1 + 80050d8: 9101 str r1, [sp, #4] + 80050da: 9200 str r2, [sp, #0] + 80050dc: 2302 movs r3, #2 + 80050de: 4629 mov r1, r5 + 80050e0: f000 f95c bl 800539c + 80050e4: 4620 mov r0, r4 + 80050e6: b005 add sp, #20 + 80050e8: bd30 pop {r4, r5, pc} + +080050ea : + 80050ea: b51f push {r0, r1, r2, r3, r4, lr} + 80050ec: f8bd 4020 ldrh.w r4, [sp, #32] + 80050f0: 9402 str r4, [sp, #8] + 80050f2: f89d 401c ldrb.w r4, [sp, #28] + 80050f6: 9401 str r4, [sp, #4] + 80050f8: f89d 4018 ldrb.w r4, [sp, #24] + 80050fc: 9400 str r4, [sp, #0] + 80050fe: f000 f927 bl 8005350 + 8005102: 2000 movs r0, #0 + 8005104: b004 add sp, #16 + 8005106: bd10 pop {r4, pc} + +08005108 : + 8005108: b508 push {r3, lr} + 800510a: f000 f939 bl 8005380 + 800510e: 2000 movs r0, #0 + 8005110: bd08 pop {r3, pc} + +08005112 : + 8005112: b530 push {r4, r5, lr} + 8005114: 2300 movs r3, #0 + 8005116: f500 7461 add.w r4, r0, #900 ; 0x384 + 800511a: f854 5b04 ldr.w r5, [r4], #4 + 800511e: 042d lsls r5, r5, #16 + 8005120: b2da uxtb r2, r3 + 8005122: d408 bmi.n 8005136 + 8005124: eb00 0083 add.w r0, r0, r3, lsl #2 + 8005128: f441 4100 orr.w r1, r1, #32768 ; 0x8000 + 800512c: b292 uxth r2, r2 + 800512e: f8c0 1384 str.w r1, [r0, #900] ; 0x384 + 8005132: b2d0 uxtb r0, r2 + 8005134: bd30 pop {r4, r5, pc} + 8005136: 3301 adds r3, #1 + 8005138: 2b0b cmp r3, #11 + 800513a: d1ee bne.n 800511a + 800513c: f64f 72ff movw r2, #65535 ; 0xffff + 8005140: e7f7 b.n 8005132 + +08005142 : + 8005142: 290a cmp r1, #10 + 8005144: bf9f itttt ls + 8005146: eb00 0081 addls.w r0, r0, r1, lsl #2 + 800514a: f8d0 3384 ldrls.w r3, [r0, #900] ; 0x384 + 800514e: f3c3 030e ubfxls r3, r3, #0, #15 + 8005152: f8c0 3384 strls.w r3, [r0, #900] ; 0x384 + 8005156: 2000 movs r0, #0 + 8005158: 4770 bx lr + ... + +0800515c : + 800515c: 2904 cmp r1, #4 + 800515e: d00a beq.n 8005176 + 8005160: 2905 cmp r1, #5 + 8005162: d004 beq.n 800516e + 8005164: 2902 cmp r1, #2 + 8005166: d105 bne.n 8005174 + 8005168: 4b04 ldr r3, [pc, #16] ; (800517c ) + 800516a: 7019 strb r1, [r3, #0] + 800516c: 4770 bx lr + 800516e: 4b03 ldr r3, [pc, #12] ; (800517c ) + 8005170: 2203 movs r2, #3 + 8005172: 701a strb r2, [r3, #0] + 8005174: 4770 bx lr + 8005176: 4b01 ldr r3, [pc, #4] ; (800517c ) + 8005178: 2201 movs r2, #1 + 800517a: e7fa b.n 8005172 + 800517c: 20000230 .word 0x20000230 + +08005180 : + 8005180: b508 push {r3, lr} + 8005182: 2201 movs r2, #1 + 8005184: 490b ldr r1, [pc, #44] ; (80051b4 ) + 8005186: 480c ldr r0, [pc, #48] ; (80051b8 ) + 8005188: f7ff fade bl 8004748 + 800518c: b108 cbz r0, 8005192 + 800518e: f7fc f96d bl 800146c + 8005192: 490a ldr r1, [pc, #40] ; (80051bc ) + 8005194: 4808 ldr r0, [pc, #32] ; (80051b8 ) + 8005196: f7ff faf6 bl 8004786 + 800519a: b108 cbz r0, 80051a0 + 800519c: f7fc f966 bl 800146c + 80051a0: 4805 ldr r0, [pc, #20] ; (80051b8 ) + 80051a2: f7ff fb22 bl 80047ea + 80051a6: b118 cbz r0, 80051b0 + 80051a8: e8bd 4008 ldmia.w sp!, {r3, lr} + 80051ac: f7fc b95e b.w 800146c + 80051b0: bd08 pop {r3, pc} + 80051b2: bf00 nop + 80051b4: 0800515d .word 0x0800515d + 80051b8: 20000414 .word 0x20000414 + 80051bc: 2000000c .word 0x2000000c + +080051c0 : + 80051c0: 4801 ldr r0, [pc, #4] ; (80051c8 ) + 80051c2: f7ff bb1c b.w 80047fe + 80051c6: bf00 nop + 80051c8: 20000414 .word 0x20000414 + +080051cc : + 80051cc: b530 push {r4, r5, lr} + 80051ce: 4604 mov r4, r0 + 80051d0: b089 sub sp, #36 ; 0x24 + 80051d2: 2214 movs r2, #20 + 80051d4: 2100 movs r1, #0 + 80051d6: a803 add r0, sp, #12 + 80051d8: f000 f960 bl 800549c + 80051dc: 6823 ldr r3, [r4, #0] + 80051de: f1b3 4fa0 cmp.w r3, #1342177280 ; 0x50000000 + 80051e2: d136 bne.n 8005252 + 80051e4: 4c1c ldr r4, [pc, #112] ; (8005258 ) + 80051e6: 481d ldr r0, [pc, #116] ; (800525c ) + 80051e8: 2500 movs r5, #0 + 80051ea: 9501 str r5, [sp, #4] + 80051ec: 6b23 ldr r3, [r4, #48] ; 0x30 + 80051ee: f043 0301 orr.w r3, r3, #1 + 80051f2: 6323 str r3, [r4, #48] ; 0x30 + 80051f4: 6b23 ldr r3, [r4, #48] ; 0x30 + 80051f6: f003 0301 and.w r3, r3, #1 + 80051fa: 9301 str r3, [sp, #4] + 80051fc: 9b01 ldr r3, [sp, #4] + 80051fe: a903 add r1, sp, #12 + 8005200: f44f 7300 mov.w r3, #512 ; 0x200 + 8005204: 9303 str r3, [sp, #12] + 8005206: f7fc fd75 bl 8001cf4 + 800520a: f44f 52e0 mov.w r2, #7168 ; 0x1c00 + 800520e: 2302 movs r3, #2 + 8005210: e9cd 2303 strd r2, r3, [sp, #12] + 8005214: 2103 movs r1, #3 + 8005216: 230a movs r3, #10 + 8005218: e9cd 1306 strd r1, r3, [sp, #24] + 800521c: 480f ldr r0, [pc, #60] ; (800525c ) + 800521e: 9505 str r5, [sp, #20] + 8005220: a903 add r1, sp, #12 + 8005222: f7fc fd67 bl 8001cf4 + 8005226: 6b63 ldr r3, [r4, #52] ; 0x34 + 8005228: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800522c: 6363 str r3, [r4, #52] ; 0x34 + 800522e: 9502 str r5, [sp, #8] + 8005230: 6c63 ldr r3, [r4, #68] ; 0x44 + 8005232: f443 4380 orr.w r3, r3, #16384 ; 0x4000 + 8005236: 6463 str r3, [r4, #68] ; 0x44 + 8005238: 6c63 ldr r3, [r4, #68] ; 0x44 + 800523a: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 800523e: 9302 str r3, [sp, #8] + 8005240: 2043 movs r0, #67 ; 0x43 + 8005242: 462a mov r2, r5 + 8005244: 4629 mov r1, r5 + 8005246: 9b02 ldr r3, [sp, #8] + 8005248: f7fc fcfc bl 8001c44 + 800524c: 2043 movs r0, #67 ; 0x43 + 800524e: f7fc fd2d bl 8001cac + 8005252: b009 add sp, #36 ; 0x24 + 8005254: bd30 pop {r4, r5, pc} + 8005256: bf00 nop + 8005258: 40023800 .word 0x40023800 + 800525c: 40020000 .word 0x40020000 + +08005260 : + 8005260: f8d0 02c0 ldr.w r0, [r0, #704] ; 0x2c0 + 8005264: f7ff bc9c b.w 8004ba0 + +08005268 : + 8005268: f8d0 02c0 ldr.w r0, [r0, #704] ; 0x2c0 + 800526c: f7ff bcae b.w 8004bcc + +08005270 : + 8005270: f8d0 02c0 ldr.w r0, [r0, #704] ; 0x2c0 + 8005274: f7ff bcb4 b.w 8004be0 + +08005278 : + 8005278: 4770 bx lr + +0800527a : + 800527a: f8d0 02c0 ldr.w r0, [r0, #704] ; 0x2c0 + 800527e: f7ff bc9d b.w 8004bbc + +08005282 : + 8005282: f8d0 02c0 ldr.w r0, [r0, #704] ; 0x2c0 + 8005286: f7ff bc9d b.w 8004bc4 + ... + +0800528c : + 800528c: b510 push {r4, lr} + 800528e: f890 33cc ldrb.w r3, [r0, #972] ; 0x3cc + 8005292: 2b01 cmp r3, #1 + 8005294: 4604 mov r4, r0 + 8005296: d11b bne.n 80052d0 + 8005298: 480e ldr r0, [pc, #56] ; (80052d4 ) + 800529a: f8c4 03d0 str.w r0, [r4, #976] ; 0x3d0 + 800529e: f04f 42a0 mov.w r2, #1342177280 ; 0x50000000 + 80052a2: 6002 str r2, [r0, #0] + 80052a4: 2208 movs r2, #8 + 80052a6: e9c0 2302 strd r2, r3, [r0, #8] + 80052aa: 2300 movs r3, #0 + 80052ac: 2202 movs r2, #2 + 80052ae: f8c0 42c0 str.w r4, [r0, #704] ; 0x2c0 + 80052b2: 6103 str r3, [r0, #16] + 80052b4: e9c0 2306 strd r2, r3, [r0, #24] + 80052b8: f7fc fe38 bl 8001f2c + 80052bc: b108 cbz r0, 80052c2 + 80052be: f7fc f8d5 bl 800146c + 80052c2: 4804 ldr r0, [pc, #16] ; (80052d4 ) + 80052c4: f7fd fa1c bl 8002700 + 80052c8: 4601 mov r1, r0 + 80052ca: 4620 mov r0, r4 + 80052cc: f7ff fc65 bl 8004b9a + 80052d0: 2000 movs r0, #0 + 80052d2: bd10 pop {r4, pc} + 80052d4: 200007ec .word 0x200007ec + +080052d8 : + 80052d8: b508 push {r3, lr} + 80052da: f8d0 03d0 ldr.w r0, [r0, #976] ; 0x3d0 + 80052de: f7fd f9d9 bl 8002694 + 80052e2: 2803 cmp r0, #3 + 80052e4: bf96 itet ls + 80052e6: 4b02 ldrls r3, [pc, #8] ; (80052f0 ) + 80052e8: 2002 movhi r0, #2 + 80052ea: 5c18 ldrbls r0, [r3, r0] + 80052ec: bd08 pop {r3, pc} + 80052ee: bf00 nop + 80052f0: 08009a34 .word 0x08009a34 + +080052f4 : + 80052f4: b508 push {r3, lr} + 80052f6: f8d0 03d0 ldr.w r0, [r0, #976] ; 0x3d0 + 80052fa: f7fd f9e1 bl 80026c0 + 80052fe: 2803 cmp r0, #3 + 8005300: bf96 itet ls + 8005302: 4b02 ldrls r3, [pc, #8] ; (800530c ) + 8005304: 2002 movhi r0, #2 + 8005306: 5c18 ldrbls r0, [r3, r0] + 8005308: bd08 pop {r3, pc} + 800530a: bf00 nop + 800530c: 08009a34 .word 0x08009a34 + +08005310 : + 8005310: b508 push {r3, lr} + 8005312: f8d0 03d0 ldr.w r0, [r0, #976] ; 0x3d0 + 8005316: f7fd f9f6 bl 8002706 + 800531a: 2802 cmp r0, #2 + 800531c: bf96 itet ls + 800531e: 4b02 ldrls r3, [pc, #8] ; (8005328 ) + 8005320: 2001 movhi r0, #1 + 8005322: 5c18 ldrbls r0, [r3, r0] + 8005324: bd08 pop {r3, pc} + 8005326: bf00 nop + 8005328: 08009a31 .word 0x08009a31 + +0800532c : + 800532c: b508 push {r3, lr} + 800532e: f8d0 03d0 ldr.w r0, [r0, #976] ; 0x3d0 + 8005332: f7fd f9d7 bl 80026e4 + 8005336: 2803 cmp r0, #3 + 8005338: bf96 itet ls + 800533a: 4b02 ldrls r3, [pc, #8] ; (8005344 ) + 800533c: 2002 movhi r0, #2 + 800533e: 5c18 ldrbls r0, [r3, r0] + 8005340: bd08 pop {r3, pc} + 8005342: bf00 nop + 8005344: 08009a34 .word 0x08009a34 + +08005348 : + 8005348: f8d0 03d0 ldr.w r0, [r0, #976] ; 0x3d0 + 800534c: f7fd b9d3 b.w 80026f6 + +08005350 : + 8005350: b51f push {r0, r1, r2, r3, r4, lr} + 8005352: f8bd 4020 ldrh.w r4, [sp, #32] + 8005356: 9402 str r4, [sp, #8] + 8005358: f89d 401c ldrb.w r4, [sp, #28] + 800535c: 9401 str r4, [sp, #4] + 800535e: f89d 4018 ldrb.w r4, [sp, #24] + 8005362: 9400 str r4, [sp, #0] + 8005364: f8d0 03d0 ldr.w r0, [r0, #976] ; 0x3d0 + 8005368: f7fc fd97 bl 8001e9a + 800536c: 2803 cmp r0, #3 + 800536e: bf9a itte ls + 8005370: 4b02 ldrls r3, [pc, #8] ; (800537c ) + 8005372: 5c18 ldrbls r0, [r3, r0] + 8005374: 2002 movhi r0, #2 + 8005376: b004 add sp, #16 + 8005378: bd10 pop {r4, pc} + 800537a: bf00 nop + 800537c: 08009a34 .word 0x08009a34 + +08005380 : + 8005380: b508 push {r3, lr} + 8005382: f8d0 03d0 ldr.w r0, [r0, #976] ; 0x3d0 + 8005386: f7fc fdbf bl 8001f08 + 800538a: 2803 cmp r0, #3 + 800538c: bf96 itet ls + 800538e: 4b02 ldrls r3, [pc, #8] ; (8005398 ) + 8005390: 2002 movhi r0, #2 + 8005392: 5c18 ldrbls r0, [r3, r0] + 8005394: bd08 pop {r3, pc} + 8005396: bf00 nop + 8005398: 08009a34 .word 0x08009a34 + +0800539c : + 800539c: b51f push {r0, r1, r2, r3, r4, lr} + 800539e: f89d 4024 ldrb.w r4, [sp, #36] ; 0x24 + 80053a2: 9403 str r4, [sp, #12] + 80053a4: f8bd 4020 ldrh.w r4, [sp, #32] + 80053a8: 9402 str r4, [sp, #8] + 80053aa: 9c07 ldr r4, [sp, #28] + 80053ac: 9401 str r4, [sp, #4] + 80053ae: f89d 4018 ldrb.w r4, [sp, #24] + 80053b2: 9400 str r4, [sp, #0] + 80053b4: f8d0 03d0 ldr.w r0, [r0, #976] ; 0x3d0 + 80053b8: f7fc fe02 bl 8001fc0 + 80053bc: 2803 cmp r0, #3 + 80053be: bf9a itte ls + 80053c0: 4b02 ldrls r3, [pc, #8] ; (80053cc ) + 80053c2: 5c18 ldrbls r0, [r3, r0] + 80053c4: 2002 movhi r0, #2 + 80053c6: b004 add sp, #16 + 80053c8: bd10 pop {r4, pc} + 80053ca: bf00 nop + 80053cc: 08009a34 .word 0x08009a34 + +080053d0 : + 80053d0: f8d0 03d0 ldr.w r0, [r0, #976] ; 0x3d0 + 80053d4: f7fd b989 b.w 80026ea + +080053d8 : + 80053d8: b508 push {r3, lr} + 80053da: f890 33cc ldrb.w r3, [r0, #972] ; 0x3cc + 80053de: 2b01 cmp r3, #1 + 80053e0: d102 bne.n 80053e8 + 80053e2: 4608 mov r0, r1 + 80053e4: f000 f816 bl 8005414 + 80053e8: 20c8 movs r0, #200 ; 0xc8 + 80053ea: f7fc fc05 bl 8001bf8 + 80053ee: 2000 movs r0, #0 + 80053f0: bd08 pop {r3, pc} + +080053f2 : + 80053f2: f8d0 03d0 ldr.w r0, [r0, #976] ; 0x3d0 + 80053f6: 2328 movs r3, #40 ; 0x28 + 80053f8: fb03 0101 mla r1, r3, r1, r0 + 80053fc: f891 303b ldrb.w r3, [r1, #59] ; 0x3b + 8005400: b11b cbz r3, 800540a + 8005402: f881 2050 strb.w r2, [r1, #80] ; 0x50 + 8005406: 2000 movs r0, #0 + 8005408: 4770 bx lr + 800540a: f881 2051 strb.w r2, [r1, #81] ; 0x51 + 800540e: e7fa b.n 8005406 + +08005410 : + 8005410: f7fc bbf2 b.w 8001bf8 + +08005414 : + 8005414: fab0 f280 clz r2, r0 + 8005418: 0952 lsrs r2, r2, #5 + 800541a: 2101 movs r1, #1 + 800541c: 4801 ldr r0, [pc, #4] ; (8005424 ) + 800541e: f7fc bd37 b.w 8001e90 + 8005422: bf00 nop + 8005424: 40020800 .word 0x40020800 + +08005428 <__errno>: + 8005428: 4b01 ldr r3, [pc, #4] ; (8005430 <__errno+0x8>) + 800542a: 6818 ldr r0, [r3, #0] + 800542c: 4770 bx lr + 800542e: bf00 nop + 8005430: 2000002c .word 0x2000002c + +08005434 <__libc_init_array>: + 8005434: b570 push {r4, r5, r6, lr} + 8005436: 4e0d ldr r6, [pc, #52] ; (800546c <__libc_init_array+0x38>) + 8005438: 4c0d ldr r4, [pc, #52] ; (8005470 <__libc_init_array+0x3c>) + 800543a: 1ba4 subs r4, r4, r6 + 800543c: 10a4 asrs r4, r4, #2 + 800543e: 2500 movs r5, #0 + 8005440: 42a5 cmp r5, r4 + 8005442: d109 bne.n 8005458 <__libc_init_array+0x24> + 8005444: 4e0b ldr r6, [pc, #44] ; (8005474 <__libc_init_array+0x40>) + 8005446: 4c0c ldr r4, [pc, #48] ; (8005478 <__libc_init_array+0x44>) + 8005448: f004 fa66 bl 8009918 <_init> + 800544c: 1ba4 subs r4, r4, r6 + 800544e: 10a4 asrs r4, r4, #2 + 8005450: 2500 movs r5, #0 + 8005452: 42a5 cmp r5, r4 + 8005454: d105 bne.n 8005462 <__libc_init_array+0x2e> + 8005456: bd70 pop {r4, r5, r6, pc} + 8005458: f856 3025 ldr.w r3, [r6, r5, lsl #2] + 800545c: 4798 blx r3 + 800545e: 3501 adds r5, #1 + 8005460: e7ee b.n 8005440 <__libc_init_array+0xc> + 8005462: f856 3025 ldr.w r3, [r6, r5, lsl #2] + 8005466: 4798 blx r3 + 8005468: 3501 adds r5, #1 + 800546a: e7f2 b.n 8005452 <__libc_init_array+0x1e> + 800546c: 08009d58 .word 0x08009d58 + 8005470: 08009d58 .word 0x08009d58 + 8005474: 08009d58 .word 0x08009d58 + 8005478: 08009d5c .word 0x08009d5c + +0800547c : + 800547c: 4b02 ldr r3, [pc, #8] ; (8005488 ) + 800547e: 4601 mov r1, r0 + 8005480: 6818 ldr r0, [r3, #0] + 8005482: f000 b861 b.w 8005548 <_malloc_r> + 8005486: bf00 nop + 8005488: 2000002c .word 0x2000002c + +0800548c : + 800548c: 4b02 ldr r3, [pc, #8] ; (8005498 ) + 800548e: 4601 mov r1, r0 + 8005490: 6818 ldr r0, [r3, #0] + 8005492: f000 b80b b.w 80054ac <_free_r> + 8005496: bf00 nop + 8005498: 2000002c .word 0x2000002c + +0800549c : + 800549c: 4402 add r2, r0 + 800549e: 4603 mov r3, r0 + 80054a0: 4293 cmp r3, r2 + 80054a2: d100 bne.n 80054a6 + 80054a4: 4770 bx lr + 80054a6: f803 1b01 strb.w r1, [r3], #1 + 80054aa: e7f9 b.n 80054a0 + +080054ac <_free_r>: + 80054ac: b538 push {r3, r4, r5, lr} + 80054ae: 4605 mov r5, r0 + 80054b0: 2900 cmp r1, #0 + 80054b2: d045 beq.n 8005540 <_free_r+0x94> + 80054b4: f851 3c04 ldr.w r3, [r1, #-4] + 80054b8: 1f0c subs r4, r1, #4 + 80054ba: 2b00 cmp r3, #0 + 80054bc: bfb8 it lt + 80054be: 18e4 addlt r4, r4, r3 + 80054c0: f003 fa77 bl 80089b2 <__malloc_lock> + 80054c4: 4a1f ldr r2, [pc, #124] ; (8005544 <_free_r+0x98>) + 80054c6: 6813 ldr r3, [r2, #0] + 80054c8: 4610 mov r0, r2 + 80054ca: b933 cbnz r3, 80054da <_free_r+0x2e> + 80054cc: 6063 str r3, [r4, #4] + 80054ce: 6014 str r4, [r2, #0] + 80054d0: 4628 mov r0, r5 + 80054d2: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} + 80054d6: f003 ba6d b.w 80089b4 <__malloc_unlock> + 80054da: 42a3 cmp r3, r4 + 80054dc: d90c bls.n 80054f8 <_free_r+0x4c> + 80054de: 6821 ldr r1, [r4, #0] + 80054e0: 1862 adds r2, r4, r1 + 80054e2: 4293 cmp r3, r2 + 80054e4: bf04 itt eq + 80054e6: 681a ldreq r2, [r3, #0] + 80054e8: 685b ldreq r3, [r3, #4] + 80054ea: 6063 str r3, [r4, #4] + 80054ec: bf04 itt eq + 80054ee: 1852 addeq r2, r2, r1 + 80054f0: 6022 streq r2, [r4, #0] + 80054f2: 6004 str r4, [r0, #0] + 80054f4: e7ec b.n 80054d0 <_free_r+0x24> + 80054f6: 4613 mov r3, r2 + 80054f8: 685a ldr r2, [r3, #4] + 80054fa: b10a cbz r2, 8005500 <_free_r+0x54> + 80054fc: 42a2 cmp r2, r4 + 80054fe: d9fa bls.n 80054f6 <_free_r+0x4a> + 8005500: 6819 ldr r1, [r3, #0] + 8005502: 1858 adds r0, r3, r1 + 8005504: 42a0 cmp r0, r4 + 8005506: d10b bne.n 8005520 <_free_r+0x74> + 8005508: 6820 ldr r0, [r4, #0] + 800550a: 4401 add r1, r0 + 800550c: 1858 adds r0, r3, r1 + 800550e: 4282 cmp r2, r0 + 8005510: 6019 str r1, [r3, #0] + 8005512: d1dd bne.n 80054d0 <_free_r+0x24> + 8005514: 6810 ldr r0, [r2, #0] + 8005516: 6852 ldr r2, [r2, #4] + 8005518: 605a str r2, [r3, #4] + 800551a: 4401 add r1, r0 + 800551c: 6019 str r1, [r3, #0] + 800551e: e7d7 b.n 80054d0 <_free_r+0x24> + 8005520: d902 bls.n 8005528 <_free_r+0x7c> + 8005522: 230c movs r3, #12 + 8005524: 602b str r3, [r5, #0] + 8005526: e7d3 b.n 80054d0 <_free_r+0x24> + 8005528: 6820 ldr r0, [r4, #0] + 800552a: 1821 adds r1, r4, r0 + 800552c: 428a cmp r2, r1 + 800552e: bf04 itt eq + 8005530: 6811 ldreq r1, [r2, #0] + 8005532: 6852 ldreq r2, [r2, #4] + 8005534: 6062 str r2, [r4, #4] + 8005536: bf04 itt eq + 8005538: 1809 addeq r1, r1, r0 + 800553a: 6021 streq r1, [r4, #0] + 800553c: 605c str r4, [r3, #4] + 800553e: e7c7 b.n 80054d0 <_free_r+0x24> + 8005540: bd38 pop {r3, r4, r5, pc} + 8005542: bf00 nop + 8005544: 20000234 .word 0x20000234 + +08005548 <_malloc_r>: + 8005548: b570 push {r4, r5, r6, lr} + 800554a: 1ccd adds r5, r1, #3 + 800554c: f025 0503 bic.w r5, r5, #3 + 8005550: 3508 adds r5, #8 + 8005552: 2d0c cmp r5, #12 + 8005554: bf38 it cc + 8005556: 250c movcc r5, #12 + 8005558: 2d00 cmp r5, #0 + 800555a: 4606 mov r6, r0 + 800555c: db01 blt.n 8005562 <_malloc_r+0x1a> + 800555e: 42a9 cmp r1, r5 + 8005560: d903 bls.n 800556a <_malloc_r+0x22> + 8005562: 230c movs r3, #12 + 8005564: 6033 str r3, [r6, #0] + 8005566: 2000 movs r0, #0 + 8005568: bd70 pop {r4, r5, r6, pc} + 800556a: f003 fa22 bl 80089b2 <__malloc_lock> + 800556e: 4a21 ldr r2, [pc, #132] ; (80055f4 <_malloc_r+0xac>) + 8005570: 6814 ldr r4, [r2, #0] + 8005572: 4621 mov r1, r4 + 8005574: b991 cbnz r1, 800559c <_malloc_r+0x54> + 8005576: 4c20 ldr r4, [pc, #128] ; (80055f8 <_malloc_r+0xb0>) + 8005578: 6823 ldr r3, [r4, #0] + 800557a: b91b cbnz r3, 8005584 <_malloc_r+0x3c> + 800557c: 4630 mov r0, r6 + 800557e: f000 fef7 bl 8006370 <_sbrk_r> + 8005582: 6020 str r0, [r4, #0] + 8005584: 4629 mov r1, r5 + 8005586: 4630 mov r0, r6 + 8005588: f000 fef2 bl 8006370 <_sbrk_r> + 800558c: 1c43 adds r3, r0, #1 + 800558e: d124 bne.n 80055da <_malloc_r+0x92> + 8005590: 230c movs r3, #12 + 8005592: 6033 str r3, [r6, #0] + 8005594: 4630 mov r0, r6 + 8005596: f003 fa0d bl 80089b4 <__malloc_unlock> + 800559a: e7e4 b.n 8005566 <_malloc_r+0x1e> + 800559c: 680b ldr r3, [r1, #0] + 800559e: 1b5b subs r3, r3, r5 + 80055a0: d418 bmi.n 80055d4 <_malloc_r+0x8c> + 80055a2: 2b0b cmp r3, #11 + 80055a4: d90f bls.n 80055c6 <_malloc_r+0x7e> + 80055a6: 600b str r3, [r1, #0] + 80055a8: 50cd str r5, [r1, r3] + 80055aa: 18cc adds r4, r1, r3 + 80055ac: 4630 mov r0, r6 + 80055ae: f003 fa01 bl 80089b4 <__malloc_unlock> + 80055b2: f104 000b add.w r0, r4, #11 + 80055b6: 1d23 adds r3, r4, #4 + 80055b8: f020 0007 bic.w r0, r0, #7 + 80055bc: 1ac3 subs r3, r0, r3 + 80055be: d0d3 beq.n 8005568 <_malloc_r+0x20> + 80055c0: 425a negs r2, r3 + 80055c2: 50e2 str r2, [r4, r3] + 80055c4: e7d0 b.n 8005568 <_malloc_r+0x20> + 80055c6: 428c cmp r4, r1 + 80055c8: 684b ldr r3, [r1, #4] + 80055ca: bf16 itet ne + 80055cc: 6063 strne r3, [r4, #4] + 80055ce: 6013 streq r3, [r2, #0] + 80055d0: 460c movne r4, r1 + 80055d2: e7eb b.n 80055ac <_malloc_r+0x64> + 80055d4: 460c mov r4, r1 + 80055d6: 6849 ldr r1, [r1, #4] + 80055d8: e7cc b.n 8005574 <_malloc_r+0x2c> + 80055da: 1cc4 adds r4, r0, #3 + 80055dc: f024 0403 bic.w r4, r4, #3 + 80055e0: 42a0 cmp r0, r4 + 80055e2: d005 beq.n 80055f0 <_malloc_r+0xa8> + 80055e4: 1a21 subs r1, r4, r0 + 80055e6: 4630 mov r0, r6 + 80055e8: f000 fec2 bl 8006370 <_sbrk_r> + 80055ec: 3001 adds r0, #1 + 80055ee: d0cf beq.n 8005590 <_malloc_r+0x48> + 80055f0: 6025 str r5, [r4, #0] + 80055f2: e7db b.n 80055ac <_malloc_r+0x64> + 80055f4: 20000234 .word 0x20000234 + 80055f8: 20000238 .word 0x20000238 + +080055fc <__cvt>: + 80055fc: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} + 8005600: ec55 4b10 vmov r4, r5, d0 + 8005604: 9f0d ldr r7, [sp, #52] ; 0x34 + 8005606: f8dd a030 ldr.w sl, [sp, #48] ; 0x30 + 800560a: 2d00 cmp r5, #0 + 800560c: 460e mov r6, r1 + 800560e: 4691 mov r9, r2 + 8005610: 4619 mov r1, r3 + 8005612: bfb8 it lt + 8005614: 4622 movlt r2, r4 + 8005616: 462b mov r3, r5 + 8005618: f027 0720 bic.w r7, r7, #32 + 800561c: bfbb ittet lt + 800561e: f105 4300 addlt.w r3, r5, #2147483648 ; 0x80000000 + 8005622: 461d movlt r5, r3 + 8005624: 2300 movge r3, #0 + 8005626: 232d movlt r3, #45 ; 0x2d + 8005628: bfb8 it lt + 800562a: 4614 movlt r4, r2 + 800562c: 2f46 cmp r7, #70 ; 0x46 + 800562e: 700b strb r3, [r1, #0] + 8005630: d004 beq.n 800563c <__cvt+0x40> + 8005632: 2f45 cmp r7, #69 ; 0x45 + 8005634: d100 bne.n 8005638 <__cvt+0x3c> + 8005636: 3601 adds r6, #1 + 8005638: 2102 movs r1, #2 + 800563a: e000 b.n 800563e <__cvt+0x42> + 800563c: 2103 movs r1, #3 + 800563e: ab03 add r3, sp, #12 + 8005640: 9301 str r3, [sp, #4] + 8005642: ab02 add r3, sp, #8 + 8005644: 9300 str r3, [sp, #0] + 8005646: 4632 mov r2, r6 + 8005648: 4653 mov r3, sl + 800564a: ec45 4b10 vmov d0, r4, r5 + 800564e: f001 fec3 bl 80073d8 <_dtoa_r> + 8005652: 2f47 cmp r7, #71 ; 0x47 + 8005654: 4680 mov r8, r0 + 8005656: d102 bne.n 800565e <__cvt+0x62> + 8005658: f019 0f01 tst.w r9, #1 + 800565c: d026 beq.n 80056ac <__cvt+0xb0> + 800565e: 2f46 cmp r7, #70 ; 0x46 + 8005660: eb08 0906 add.w r9, r8, r6 + 8005664: d111 bne.n 800568a <__cvt+0x8e> + 8005666: f898 3000 ldrb.w r3, [r8] + 800566a: 2b30 cmp r3, #48 ; 0x30 + 800566c: d10a bne.n 8005684 <__cvt+0x88> + 800566e: 2200 movs r2, #0 + 8005670: 2300 movs r3, #0 + 8005672: 4620 mov r0, r4 + 8005674: 4629 mov r1, r5 + 8005676: f7fb fa2f bl 8000ad8 <__aeabi_dcmpeq> + 800567a: b918 cbnz r0, 8005684 <__cvt+0x88> + 800567c: f1c6 0601 rsb r6, r6, #1 + 8005680: f8ca 6000 str.w r6, [sl] + 8005684: f8da 3000 ldr.w r3, [sl] + 8005688: 4499 add r9, r3 + 800568a: 2200 movs r2, #0 + 800568c: 2300 movs r3, #0 + 800568e: 4620 mov r0, r4 + 8005690: 4629 mov r1, r5 + 8005692: f7fb fa21 bl 8000ad8 <__aeabi_dcmpeq> + 8005696: b938 cbnz r0, 80056a8 <__cvt+0xac> + 8005698: 2230 movs r2, #48 ; 0x30 + 800569a: 9b03 ldr r3, [sp, #12] + 800569c: 454b cmp r3, r9 + 800569e: d205 bcs.n 80056ac <__cvt+0xb0> + 80056a0: 1c59 adds r1, r3, #1 + 80056a2: 9103 str r1, [sp, #12] + 80056a4: 701a strb r2, [r3, #0] + 80056a6: e7f8 b.n 800569a <__cvt+0x9e> + 80056a8: f8cd 900c str.w r9, [sp, #12] + 80056ac: 9b03 ldr r3, [sp, #12] + 80056ae: 9a0e ldr r2, [sp, #56] ; 0x38 + 80056b0: eba3 0308 sub.w r3, r3, r8 + 80056b4: 4640 mov r0, r8 + 80056b6: 6013 str r3, [r2, #0] + 80056b8: b004 add sp, #16 + 80056ba: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + +080056be <__exponent>: + 80056be: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} + 80056c0: 2900 cmp r1, #0 + 80056c2: 4604 mov r4, r0 + 80056c4: bfba itte lt + 80056c6: 4249 neglt r1, r1 + 80056c8: 232d movlt r3, #45 ; 0x2d + 80056ca: 232b movge r3, #43 ; 0x2b + 80056cc: 2909 cmp r1, #9 + 80056ce: f804 2b02 strb.w r2, [r4], #2 + 80056d2: 7043 strb r3, [r0, #1] + 80056d4: dd20 ble.n 8005718 <__exponent+0x5a> + 80056d6: f10d 0307 add.w r3, sp, #7 + 80056da: 461f mov r7, r3 + 80056dc: 260a movs r6, #10 + 80056de: fb91 f5f6 sdiv r5, r1, r6 + 80056e2: fb06 1115 mls r1, r6, r5, r1 + 80056e6: 3130 adds r1, #48 ; 0x30 + 80056e8: 2d09 cmp r5, #9 + 80056ea: f803 1c01 strb.w r1, [r3, #-1] + 80056ee: f103 32ff add.w r2, r3, #4294967295 + 80056f2: 4629 mov r1, r5 + 80056f4: dc09 bgt.n 800570a <__exponent+0x4c> + 80056f6: 3130 adds r1, #48 ; 0x30 + 80056f8: 3b02 subs r3, #2 + 80056fa: f802 1c01 strb.w r1, [r2, #-1] + 80056fe: 42bb cmp r3, r7 + 8005700: 4622 mov r2, r4 + 8005702: d304 bcc.n 800570e <__exponent+0x50> + 8005704: 1a10 subs r0, r2, r0 + 8005706: b003 add sp, #12 + 8005708: bdf0 pop {r4, r5, r6, r7, pc} + 800570a: 4613 mov r3, r2 + 800570c: e7e7 b.n 80056de <__exponent+0x20> + 800570e: f813 2b01 ldrb.w r2, [r3], #1 + 8005712: f804 2b01 strb.w r2, [r4], #1 + 8005716: e7f2 b.n 80056fe <__exponent+0x40> + 8005718: 2330 movs r3, #48 ; 0x30 + 800571a: 4419 add r1, r3 + 800571c: 7083 strb r3, [r0, #2] + 800571e: 1d02 adds r2, r0, #4 + 8005720: 70c1 strb r1, [r0, #3] + 8005722: e7ef b.n 8005704 <__exponent+0x46> + +08005724 <_printf_float>: + 8005724: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 8005728: b08d sub sp, #52 ; 0x34 + 800572a: 460c mov r4, r1 + 800572c: f8dd 8058 ldr.w r8, [sp, #88] ; 0x58 + 8005730: 4616 mov r6, r2 + 8005732: 461f mov r7, r3 + 8005734: 4605 mov r5, r0 + 8005736: f003 f8ad bl 8008894 <_localeconv_r> + 800573a: 6803 ldr r3, [r0, #0] + 800573c: 9304 str r3, [sp, #16] + 800573e: 4618 mov r0, r3 + 8005740: f7fa fd4e bl 80001e0 + 8005744: 2300 movs r3, #0 + 8005746: 930a str r3, [sp, #40] ; 0x28 + 8005748: f8d8 3000 ldr.w r3, [r8] + 800574c: 9005 str r0, [sp, #20] + 800574e: 3307 adds r3, #7 + 8005750: f023 0307 bic.w r3, r3, #7 + 8005754: f103 0208 add.w r2, r3, #8 + 8005758: f894 a018 ldrb.w sl, [r4, #24] + 800575c: f8d4 b000 ldr.w fp, [r4] + 8005760: f8c8 2000 str.w r2, [r8] + 8005764: e9d3 2300 ldrd r2, r3, [r3] + 8005768: e9c4 2312 strd r2, r3, [r4, #72] ; 0x48 + 800576c: e9d4 8912 ldrd r8, r9, [r4, #72] ; 0x48 + 8005770: f029 4300 bic.w r3, r9, #2147483648 ; 0x80000000 + 8005774: 9307 str r3, [sp, #28] + 8005776: f8cd 8018 str.w r8, [sp, #24] + 800577a: f04f 32ff mov.w r2, #4294967295 + 800577e: 4ba7 ldr r3, [pc, #668] ; (8005a1c <_printf_float+0x2f8>) + 8005780: e9dd 0106 ldrd r0, r1, [sp, #24] + 8005784: f7fb f9da bl 8000b3c <__aeabi_dcmpun> + 8005788: bb70 cbnz r0, 80057e8 <_printf_float+0xc4> + 800578a: f04f 32ff mov.w r2, #4294967295 + 800578e: 4ba3 ldr r3, [pc, #652] ; (8005a1c <_printf_float+0x2f8>) + 8005790: e9dd 0106 ldrd r0, r1, [sp, #24] + 8005794: f7fb f9b4 bl 8000b00 <__aeabi_dcmple> + 8005798: bb30 cbnz r0, 80057e8 <_printf_float+0xc4> + 800579a: 2200 movs r2, #0 + 800579c: 2300 movs r3, #0 + 800579e: 4640 mov r0, r8 + 80057a0: 4649 mov r1, r9 + 80057a2: f7fb f9a3 bl 8000aec <__aeabi_dcmplt> + 80057a6: b110 cbz r0, 80057ae <_printf_float+0x8a> + 80057a8: 232d movs r3, #45 ; 0x2d + 80057aa: f884 3043 strb.w r3, [r4, #67] ; 0x43 + 80057ae: 4a9c ldr r2, [pc, #624] ; (8005a20 <_printf_float+0x2fc>) + 80057b0: 4b9c ldr r3, [pc, #624] ; (8005a24 <_printf_float+0x300>) + 80057b2: f1ba 0f47 cmp.w sl, #71 ; 0x47 + 80057b6: bf8c ite hi + 80057b8: 4690 movhi r8, r2 + 80057ba: 4698 movls r8, r3 + 80057bc: 2303 movs r3, #3 + 80057be: f02b 0204 bic.w r2, fp, #4 + 80057c2: 6123 str r3, [r4, #16] + 80057c4: 6022 str r2, [r4, #0] + 80057c6: f04f 0900 mov.w r9, #0 + 80057ca: 9700 str r7, [sp, #0] + 80057cc: 4633 mov r3, r6 + 80057ce: aa0b add r2, sp, #44 ; 0x2c + 80057d0: 4621 mov r1, r4 + 80057d2: 4628 mov r0, r5 + 80057d4: f000 f9e6 bl 8005ba4 <_printf_common> + 80057d8: 3001 adds r0, #1 + 80057da: f040 808d bne.w 80058f8 <_printf_float+0x1d4> + 80057de: f04f 30ff mov.w r0, #4294967295 + 80057e2: b00d add sp, #52 ; 0x34 + 80057e4: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 80057e8: 4642 mov r2, r8 + 80057ea: 464b mov r3, r9 + 80057ec: 4640 mov r0, r8 + 80057ee: 4649 mov r1, r9 + 80057f0: f7fb f9a4 bl 8000b3c <__aeabi_dcmpun> + 80057f4: b110 cbz r0, 80057fc <_printf_float+0xd8> + 80057f6: 4a8c ldr r2, [pc, #560] ; (8005a28 <_printf_float+0x304>) + 80057f8: 4b8c ldr r3, [pc, #560] ; (8005a2c <_printf_float+0x308>) + 80057fa: e7da b.n 80057b2 <_printf_float+0x8e> + 80057fc: 6861 ldr r1, [r4, #4] + 80057fe: 1c4b adds r3, r1, #1 + 8005800: f44b 6280 orr.w r2, fp, #1024 ; 0x400 + 8005804: a80a add r0, sp, #40 ; 0x28 + 8005806: d13e bne.n 8005886 <_printf_float+0x162> + 8005808: 2306 movs r3, #6 + 800580a: 6063 str r3, [r4, #4] + 800580c: 2300 movs r3, #0 + 800580e: e9cd 0302 strd r0, r3, [sp, #8] + 8005812: ab09 add r3, sp, #36 ; 0x24 + 8005814: 9300 str r3, [sp, #0] + 8005816: ec49 8b10 vmov d0, r8, r9 + 800581a: f10d 0323 add.w r3, sp, #35 ; 0x23 + 800581e: 6022 str r2, [r4, #0] + 8005820: f8cd a004 str.w sl, [sp, #4] + 8005824: 6861 ldr r1, [r4, #4] + 8005826: 4628 mov r0, r5 + 8005828: f7ff fee8 bl 80055fc <__cvt> + 800582c: f00a 03df and.w r3, sl, #223 ; 0xdf + 8005830: 2b47 cmp r3, #71 ; 0x47 + 8005832: 4680 mov r8, r0 + 8005834: d109 bne.n 800584a <_printf_float+0x126> + 8005836: 9b09 ldr r3, [sp, #36] ; 0x24 + 8005838: 1cd8 adds r0, r3, #3 + 800583a: db02 blt.n 8005842 <_printf_float+0x11e> + 800583c: 6862 ldr r2, [r4, #4] + 800583e: 4293 cmp r3, r2 + 8005840: dd47 ble.n 80058d2 <_printf_float+0x1ae> + 8005842: f1aa 0a02 sub.w sl, sl, #2 + 8005846: fa5f fa8a uxtb.w sl, sl + 800584a: f1ba 0f65 cmp.w sl, #101 ; 0x65 + 800584e: 9909 ldr r1, [sp, #36] ; 0x24 + 8005850: d824 bhi.n 800589c <_printf_float+0x178> + 8005852: 3901 subs r1, #1 + 8005854: 4652 mov r2, sl + 8005856: f104 0050 add.w r0, r4, #80 ; 0x50 + 800585a: 9109 str r1, [sp, #36] ; 0x24 + 800585c: f7ff ff2f bl 80056be <__exponent> + 8005860: 9a0a ldr r2, [sp, #40] ; 0x28 + 8005862: 1813 adds r3, r2, r0 + 8005864: 2a01 cmp r2, #1 + 8005866: 4681 mov r9, r0 + 8005868: 6123 str r3, [r4, #16] + 800586a: dc02 bgt.n 8005872 <_printf_float+0x14e> + 800586c: 6822 ldr r2, [r4, #0] + 800586e: 07d1 lsls r1, r2, #31 + 8005870: d501 bpl.n 8005876 <_printf_float+0x152> + 8005872: 3301 adds r3, #1 + 8005874: 6123 str r3, [r4, #16] + 8005876: f89d 3023 ldrb.w r3, [sp, #35] ; 0x23 + 800587a: 2b00 cmp r3, #0 + 800587c: d0a5 beq.n 80057ca <_printf_float+0xa6> + 800587e: 232d movs r3, #45 ; 0x2d + 8005880: f884 3043 strb.w r3, [r4, #67] ; 0x43 + 8005884: e7a1 b.n 80057ca <_printf_float+0xa6> + 8005886: f1ba 0f67 cmp.w sl, #103 ; 0x67 + 800588a: f000 8177 beq.w 8005b7c <_printf_float+0x458> + 800588e: f1ba 0f47 cmp.w sl, #71 ; 0x47 + 8005892: d1bb bne.n 800580c <_printf_float+0xe8> + 8005894: 2900 cmp r1, #0 + 8005896: d1b9 bne.n 800580c <_printf_float+0xe8> + 8005898: 2301 movs r3, #1 + 800589a: e7b6 b.n 800580a <_printf_float+0xe6> + 800589c: f1ba 0f66 cmp.w sl, #102 ; 0x66 + 80058a0: d119 bne.n 80058d6 <_printf_float+0x1b2> + 80058a2: 2900 cmp r1, #0 + 80058a4: 6863 ldr r3, [r4, #4] + 80058a6: dd0c ble.n 80058c2 <_printf_float+0x19e> + 80058a8: 6121 str r1, [r4, #16] + 80058aa: b913 cbnz r3, 80058b2 <_printf_float+0x18e> + 80058ac: 6822 ldr r2, [r4, #0] + 80058ae: 07d2 lsls r2, r2, #31 + 80058b0: d502 bpl.n 80058b8 <_printf_float+0x194> + 80058b2: 3301 adds r3, #1 + 80058b4: 440b add r3, r1 + 80058b6: 6123 str r3, [r4, #16] + 80058b8: 9b09 ldr r3, [sp, #36] ; 0x24 + 80058ba: 65a3 str r3, [r4, #88] ; 0x58 + 80058bc: f04f 0900 mov.w r9, #0 + 80058c0: e7d9 b.n 8005876 <_printf_float+0x152> + 80058c2: b913 cbnz r3, 80058ca <_printf_float+0x1a6> + 80058c4: 6822 ldr r2, [r4, #0] + 80058c6: 07d0 lsls r0, r2, #31 + 80058c8: d501 bpl.n 80058ce <_printf_float+0x1aa> + 80058ca: 3302 adds r3, #2 + 80058cc: e7f3 b.n 80058b6 <_printf_float+0x192> + 80058ce: 2301 movs r3, #1 + 80058d0: e7f1 b.n 80058b6 <_printf_float+0x192> + 80058d2: f04f 0a67 mov.w sl, #103 ; 0x67 + 80058d6: e9dd 3209 ldrd r3, r2, [sp, #36] ; 0x24 + 80058da: 4293 cmp r3, r2 + 80058dc: db05 blt.n 80058ea <_printf_float+0x1c6> + 80058de: 6822 ldr r2, [r4, #0] + 80058e0: 6123 str r3, [r4, #16] + 80058e2: 07d1 lsls r1, r2, #31 + 80058e4: d5e8 bpl.n 80058b8 <_printf_float+0x194> + 80058e6: 3301 adds r3, #1 + 80058e8: e7e5 b.n 80058b6 <_printf_float+0x192> + 80058ea: 2b00 cmp r3, #0 + 80058ec: bfd4 ite le + 80058ee: f1c3 0302 rsble r3, r3, #2 + 80058f2: 2301 movgt r3, #1 + 80058f4: 4413 add r3, r2 + 80058f6: e7de b.n 80058b6 <_printf_float+0x192> + 80058f8: 6823 ldr r3, [r4, #0] + 80058fa: 055a lsls r2, r3, #21 + 80058fc: d407 bmi.n 800590e <_printf_float+0x1ea> + 80058fe: 6923 ldr r3, [r4, #16] + 8005900: 4642 mov r2, r8 + 8005902: 4631 mov r1, r6 + 8005904: 4628 mov r0, r5 + 8005906: 47b8 blx r7 + 8005908: 3001 adds r0, #1 + 800590a: d12b bne.n 8005964 <_printf_float+0x240> + 800590c: e767 b.n 80057de <_printf_float+0xba> + 800590e: f1ba 0f65 cmp.w sl, #101 ; 0x65 + 8005912: f240 80dc bls.w 8005ace <_printf_float+0x3aa> + 8005916: 2200 movs r2, #0 + 8005918: 2300 movs r3, #0 + 800591a: e9d4 0112 ldrd r0, r1, [r4, #72] ; 0x48 + 800591e: f7fb f8db bl 8000ad8 <__aeabi_dcmpeq> + 8005922: 2800 cmp r0, #0 + 8005924: d033 beq.n 800598e <_printf_float+0x26a> + 8005926: 2301 movs r3, #1 + 8005928: 4a41 ldr r2, [pc, #260] ; (8005a30 <_printf_float+0x30c>) + 800592a: 4631 mov r1, r6 + 800592c: 4628 mov r0, r5 + 800592e: 47b8 blx r7 + 8005930: 3001 adds r0, #1 + 8005932: f43f af54 beq.w 80057de <_printf_float+0xba> + 8005936: e9dd 2309 ldrd r2, r3, [sp, #36] ; 0x24 + 800593a: 429a cmp r2, r3 + 800593c: db02 blt.n 8005944 <_printf_float+0x220> + 800593e: 6823 ldr r3, [r4, #0] + 8005940: 07d8 lsls r0, r3, #31 + 8005942: d50f bpl.n 8005964 <_printf_float+0x240> + 8005944: e9dd 2304 ldrd r2, r3, [sp, #16] + 8005948: 4631 mov r1, r6 + 800594a: 4628 mov r0, r5 + 800594c: 47b8 blx r7 + 800594e: 3001 adds r0, #1 + 8005950: f43f af45 beq.w 80057de <_printf_float+0xba> + 8005954: f04f 0800 mov.w r8, #0 + 8005958: f104 091a add.w r9, r4, #26 + 800595c: 9b0a ldr r3, [sp, #40] ; 0x28 + 800595e: 3b01 subs r3, #1 + 8005960: 4543 cmp r3, r8 + 8005962: dc09 bgt.n 8005978 <_printf_float+0x254> + 8005964: 6823 ldr r3, [r4, #0] + 8005966: 079b lsls r3, r3, #30 + 8005968: f100 8103 bmi.w 8005b72 <_printf_float+0x44e> + 800596c: 68e0 ldr r0, [r4, #12] + 800596e: 9b0b ldr r3, [sp, #44] ; 0x2c + 8005970: 4298 cmp r0, r3 + 8005972: bfb8 it lt + 8005974: 4618 movlt r0, r3 + 8005976: e734 b.n 80057e2 <_printf_float+0xbe> + 8005978: 2301 movs r3, #1 + 800597a: 464a mov r2, r9 + 800597c: 4631 mov r1, r6 + 800597e: 4628 mov r0, r5 + 8005980: 47b8 blx r7 + 8005982: 3001 adds r0, #1 + 8005984: f43f af2b beq.w 80057de <_printf_float+0xba> + 8005988: f108 0801 add.w r8, r8, #1 + 800598c: e7e6 b.n 800595c <_printf_float+0x238> + 800598e: 9b09 ldr r3, [sp, #36] ; 0x24 + 8005990: 2b00 cmp r3, #0 + 8005992: dc2b bgt.n 80059ec <_printf_float+0x2c8> + 8005994: 2301 movs r3, #1 + 8005996: 4a26 ldr r2, [pc, #152] ; (8005a30 <_printf_float+0x30c>) + 8005998: 4631 mov r1, r6 + 800599a: 4628 mov r0, r5 + 800599c: 47b8 blx r7 + 800599e: 3001 adds r0, #1 + 80059a0: f43f af1d beq.w 80057de <_printf_float+0xba> + 80059a4: 9b09 ldr r3, [sp, #36] ; 0x24 + 80059a6: b923 cbnz r3, 80059b2 <_printf_float+0x28e> + 80059a8: 9b0a ldr r3, [sp, #40] ; 0x28 + 80059aa: b913 cbnz r3, 80059b2 <_printf_float+0x28e> + 80059ac: 6823 ldr r3, [r4, #0] + 80059ae: 07d9 lsls r1, r3, #31 + 80059b0: d5d8 bpl.n 8005964 <_printf_float+0x240> + 80059b2: e9dd 2304 ldrd r2, r3, [sp, #16] + 80059b6: 4631 mov r1, r6 + 80059b8: 4628 mov r0, r5 + 80059ba: 47b8 blx r7 + 80059bc: 3001 adds r0, #1 + 80059be: f43f af0e beq.w 80057de <_printf_float+0xba> + 80059c2: f04f 0900 mov.w r9, #0 + 80059c6: f104 0a1a add.w sl, r4, #26 + 80059ca: 9b09 ldr r3, [sp, #36] ; 0x24 + 80059cc: 425b negs r3, r3 + 80059ce: 454b cmp r3, r9 + 80059d0: dc01 bgt.n 80059d6 <_printf_float+0x2b2> + 80059d2: 9b0a ldr r3, [sp, #40] ; 0x28 + 80059d4: e794 b.n 8005900 <_printf_float+0x1dc> + 80059d6: 2301 movs r3, #1 + 80059d8: 4652 mov r2, sl + 80059da: 4631 mov r1, r6 + 80059dc: 4628 mov r0, r5 + 80059de: 47b8 blx r7 + 80059e0: 3001 adds r0, #1 + 80059e2: f43f aefc beq.w 80057de <_printf_float+0xba> + 80059e6: f109 0901 add.w r9, r9, #1 + 80059ea: e7ee b.n 80059ca <_printf_float+0x2a6> + 80059ec: 9a0a ldr r2, [sp, #40] ; 0x28 + 80059ee: 6da3 ldr r3, [r4, #88] ; 0x58 + 80059f0: 429a cmp r2, r3 + 80059f2: bfa8 it ge + 80059f4: 461a movge r2, r3 + 80059f6: 2a00 cmp r2, #0 + 80059f8: 4691 mov r9, r2 + 80059fa: dd07 ble.n 8005a0c <_printf_float+0x2e8> + 80059fc: 4613 mov r3, r2 + 80059fe: 4631 mov r1, r6 + 8005a00: 4642 mov r2, r8 + 8005a02: 4628 mov r0, r5 + 8005a04: 47b8 blx r7 + 8005a06: 3001 adds r0, #1 + 8005a08: f43f aee9 beq.w 80057de <_printf_float+0xba> + 8005a0c: f104 031a add.w r3, r4, #26 + 8005a10: f04f 0b00 mov.w fp, #0 + 8005a14: ea29 79e9 bic.w r9, r9, r9, asr #31 + 8005a18: 9306 str r3, [sp, #24] + 8005a1a: e015 b.n 8005a48 <_printf_float+0x324> + 8005a1c: 7fefffff .word 0x7fefffff + 8005a20: 08009a40 .word 0x08009a40 + 8005a24: 08009a3c .word 0x08009a3c + 8005a28: 08009a48 .word 0x08009a48 + 8005a2c: 08009a44 .word 0x08009a44 + 8005a30: 08009a4c .word 0x08009a4c + 8005a34: 2301 movs r3, #1 + 8005a36: 9a06 ldr r2, [sp, #24] + 8005a38: 4631 mov r1, r6 + 8005a3a: 4628 mov r0, r5 + 8005a3c: 47b8 blx r7 + 8005a3e: 3001 adds r0, #1 + 8005a40: f43f aecd beq.w 80057de <_printf_float+0xba> + 8005a44: f10b 0b01 add.w fp, fp, #1 + 8005a48: f8d4 a058 ldr.w sl, [r4, #88] ; 0x58 + 8005a4c: ebaa 0309 sub.w r3, sl, r9 + 8005a50: 455b cmp r3, fp + 8005a52: dcef bgt.n 8005a34 <_printf_float+0x310> + 8005a54: e9dd 2309 ldrd r2, r3, [sp, #36] ; 0x24 + 8005a58: 429a cmp r2, r3 + 8005a5a: 44d0 add r8, sl + 8005a5c: db15 blt.n 8005a8a <_printf_float+0x366> + 8005a5e: 6823 ldr r3, [r4, #0] + 8005a60: 07da lsls r2, r3, #31 + 8005a62: d412 bmi.n 8005a8a <_printf_float+0x366> + 8005a64: 9b0a ldr r3, [sp, #40] ; 0x28 + 8005a66: 9909 ldr r1, [sp, #36] ; 0x24 + 8005a68: eba3 020a sub.w r2, r3, sl + 8005a6c: eba3 0a01 sub.w sl, r3, r1 + 8005a70: 4592 cmp sl, r2 + 8005a72: bfa8 it ge + 8005a74: 4692 movge sl, r2 + 8005a76: f1ba 0f00 cmp.w sl, #0 + 8005a7a: dc0e bgt.n 8005a9a <_printf_float+0x376> + 8005a7c: f04f 0800 mov.w r8, #0 + 8005a80: ea2a 7aea bic.w sl, sl, sl, asr #31 + 8005a84: f104 091a add.w r9, r4, #26 + 8005a88: e019 b.n 8005abe <_printf_float+0x39a> + 8005a8a: e9dd 2304 ldrd r2, r3, [sp, #16] + 8005a8e: 4631 mov r1, r6 + 8005a90: 4628 mov r0, r5 + 8005a92: 47b8 blx r7 + 8005a94: 3001 adds r0, #1 + 8005a96: d1e5 bne.n 8005a64 <_printf_float+0x340> + 8005a98: e6a1 b.n 80057de <_printf_float+0xba> + 8005a9a: 4653 mov r3, sl + 8005a9c: 4642 mov r2, r8 + 8005a9e: 4631 mov r1, r6 + 8005aa0: 4628 mov r0, r5 + 8005aa2: 47b8 blx r7 + 8005aa4: 3001 adds r0, #1 + 8005aa6: d1e9 bne.n 8005a7c <_printf_float+0x358> + 8005aa8: e699 b.n 80057de <_printf_float+0xba> + 8005aaa: 2301 movs r3, #1 + 8005aac: 464a mov r2, r9 + 8005aae: 4631 mov r1, r6 + 8005ab0: 4628 mov r0, r5 + 8005ab2: 47b8 blx r7 + 8005ab4: 3001 adds r0, #1 + 8005ab6: f43f ae92 beq.w 80057de <_printf_float+0xba> + 8005aba: f108 0801 add.w r8, r8, #1 + 8005abe: e9dd 2309 ldrd r2, r3, [sp, #36] ; 0x24 + 8005ac2: 1a9b subs r3, r3, r2 + 8005ac4: eba3 030a sub.w r3, r3, sl + 8005ac8: 4543 cmp r3, r8 + 8005aca: dcee bgt.n 8005aaa <_printf_float+0x386> + 8005acc: e74a b.n 8005964 <_printf_float+0x240> + 8005ace: 9a0a ldr r2, [sp, #40] ; 0x28 + 8005ad0: 2a01 cmp r2, #1 + 8005ad2: dc01 bgt.n 8005ad8 <_printf_float+0x3b4> + 8005ad4: 07db lsls r3, r3, #31 + 8005ad6: d53a bpl.n 8005b4e <_printf_float+0x42a> + 8005ad8: 2301 movs r3, #1 + 8005ada: 4642 mov r2, r8 + 8005adc: 4631 mov r1, r6 + 8005ade: 4628 mov r0, r5 + 8005ae0: 47b8 blx r7 + 8005ae2: 3001 adds r0, #1 + 8005ae4: f43f ae7b beq.w 80057de <_printf_float+0xba> + 8005ae8: e9dd 2304 ldrd r2, r3, [sp, #16] + 8005aec: 4631 mov r1, r6 + 8005aee: 4628 mov r0, r5 + 8005af0: 47b8 blx r7 + 8005af2: 3001 adds r0, #1 + 8005af4: f108 0801 add.w r8, r8, #1 + 8005af8: f43f ae71 beq.w 80057de <_printf_float+0xba> + 8005afc: 9b0a ldr r3, [sp, #40] ; 0x28 + 8005afe: 2200 movs r2, #0 + 8005b00: f103 3aff add.w sl, r3, #4294967295 + 8005b04: e9d4 0112 ldrd r0, r1, [r4, #72] ; 0x48 + 8005b08: 2300 movs r3, #0 + 8005b0a: f7fa ffe5 bl 8000ad8 <__aeabi_dcmpeq> + 8005b0e: b9c8 cbnz r0, 8005b44 <_printf_float+0x420> + 8005b10: 4653 mov r3, sl + 8005b12: 4642 mov r2, r8 + 8005b14: 4631 mov r1, r6 + 8005b16: 4628 mov r0, r5 + 8005b18: 47b8 blx r7 + 8005b1a: 3001 adds r0, #1 + 8005b1c: d10e bne.n 8005b3c <_printf_float+0x418> + 8005b1e: e65e b.n 80057de <_printf_float+0xba> + 8005b20: 2301 movs r3, #1 + 8005b22: 4652 mov r2, sl + 8005b24: 4631 mov r1, r6 + 8005b26: 4628 mov r0, r5 + 8005b28: 47b8 blx r7 + 8005b2a: 3001 adds r0, #1 + 8005b2c: f43f ae57 beq.w 80057de <_printf_float+0xba> + 8005b30: f108 0801 add.w r8, r8, #1 + 8005b34: 9b0a ldr r3, [sp, #40] ; 0x28 + 8005b36: 3b01 subs r3, #1 + 8005b38: 4543 cmp r3, r8 + 8005b3a: dcf1 bgt.n 8005b20 <_printf_float+0x3fc> + 8005b3c: 464b mov r3, r9 + 8005b3e: f104 0250 add.w r2, r4, #80 ; 0x50 + 8005b42: e6de b.n 8005902 <_printf_float+0x1de> + 8005b44: f04f 0800 mov.w r8, #0 + 8005b48: f104 0a1a add.w sl, r4, #26 + 8005b4c: e7f2 b.n 8005b34 <_printf_float+0x410> + 8005b4e: 2301 movs r3, #1 + 8005b50: e7df b.n 8005b12 <_printf_float+0x3ee> + 8005b52: 2301 movs r3, #1 + 8005b54: 464a mov r2, r9 + 8005b56: 4631 mov r1, r6 + 8005b58: 4628 mov r0, r5 + 8005b5a: 47b8 blx r7 + 8005b5c: 3001 adds r0, #1 + 8005b5e: f43f ae3e beq.w 80057de <_printf_float+0xba> + 8005b62: f108 0801 add.w r8, r8, #1 + 8005b66: 68e3 ldr r3, [r4, #12] + 8005b68: 9a0b ldr r2, [sp, #44] ; 0x2c + 8005b6a: 1a9b subs r3, r3, r2 + 8005b6c: 4543 cmp r3, r8 + 8005b6e: dcf0 bgt.n 8005b52 <_printf_float+0x42e> + 8005b70: e6fc b.n 800596c <_printf_float+0x248> + 8005b72: f04f 0800 mov.w r8, #0 + 8005b76: f104 0919 add.w r9, r4, #25 + 8005b7a: e7f4 b.n 8005b66 <_printf_float+0x442> + 8005b7c: 2900 cmp r1, #0 + 8005b7e: f43f ae8b beq.w 8005898 <_printf_float+0x174> + 8005b82: 2300 movs r3, #0 + 8005b84: e9cd 0302 strd r0, r3, [sp, #8] + 8005b88: ab09 add r3, sp, #36 ; 0x24 + 8005b8a: 9300 str r3, [sp, #0] + 8005b8c: ec49 8b10 vmov d0, r8, r9 + 8005b90: 6022 str r2, [r4, #0] + 8005b92: f8cd a004 str.w sl, [sp, #4] + 8005b96: f10d 0323 add.w r3, sp, #35 ; 0x23 + 8005b9a: 4628 mov r0, r5 + 8005b9c: f7ff fd2e bl 80055fc <__cvt> + 8005ba0: 4680 mov r8, r0 + 8005ba2: e648 b.n 8005836 <_printf_float+0x112> + +08005ba4 <_printf_common>: + 8005ba4: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 8005ba8: 4691 mov r9, r2 + 8005baa: 461f mov r7, r3 + 8005bac: 688a ldr r2, [r1, #8] + 8005bae: 690b ldr r3, [r1, #16] + 8005bb0: f8dd 8020 ldr.w r8, [sp, #32] + 8005bb4: 4293 cmp r3, r2 + 8005bb6: bfb8 it lt + 8005bb8: 4613 movlt r3, r2 + 8005bba: f8c9 3000 str.w r3, [r9] + 8005bbe: f891 2043 ldrb.w r2, [r1, #67] ; 0x43 + 8005bc2: 4606 mov r6, r0 + 8005bc4: 460c mov r4, r1 + 8005bc6: b112 cbz r2, 8005bce <_printf_common+0x2a> + 8005bc8: 3301 adds r3, #1 + 8005bca: f8c9 3000 str.w r3, [r9] + 8005bce: 6823 ldr r3, [r4, #0] + 8005bd0: 0699 lsls r1, r3, #26 + 8005bd2: bf42 ittt mi + 8005bd4: f8d9 3000 ldrmi.w r3, [r9] + 8005bd8: 3302 addmi r3, #2 + 8005bda: f8c9 3000 strmi.w r3, [r9] + 8005bde: 6825 ldr r5, [r4, #0] + 8005be0: f015 0506 ands.w r5, r5, #6 + 8005be4: d107 bne.n 8005bf6 <_printf_common+0x52> + 8005be6: f104 0a19 add.w sl, r4, #25 + 8005bea: 68e3 ldr r3, [r4, #12] + 8005bec: f8d9 2000 ldr.w r2, [r9] + 8005bf0: 1a9b subs r3, r3, r2 + 8005bf2: 42ab cmp r3, r5 + 8005bf4: dc28 bgt.n 8005c48 <_printf_common+0xa4> + 8005bf6: f894 3043 ldrb.w r3, [r4, #67] ; 0x43 + 8005bfa: 6822 ldr r2, [r4, #0] + 8005bfc: 3300 adds r3, #0 + 8005bfe: bf18 it ne + 8005c00: 2301 movne r3, #1 + 8005c02: 0692 lsls r2, r2, #26 + 8005c04: d42d bmi.n 8005c62 <_printf_common+0xbe> + 8005c06: f104 0243 add.w r2, r4, #67 ; 0x43 + 8005c0a: 4639 mov r1, r7 + 8005c0c: 4630 mov r0, r6 + 8005c0e: 47c0 blx r8 + 8005c10: 3001 adds r0, #1 + 8005c12: d020 beq.n 8005c56 <_printf_common+0xb2> + 8005c14: 6823 ldr r3, [r4, #0] + 8005c16: 68e5 ldr r5, [r4, #12] + 8005c18: f8d9 2000 ldr.w r2, [r9] + 8005c1c: f003 0306 and.w r3, r3, #6 + 8005c20: 2b04 cmp r3, #4 + 8005c22: bf08 it eq + 8005c24: 1aad subeq r5, r5, r2 + 8005c26: 68a3 ldr r3, [r4, #8] + 8005c28: 6922 ldr r2, [r4, #16] + 8005c2a: bf0c ite eq + 8005c2c: ea25 75e5 biceq.w r5, r5, r5, asr #31 + 8005c30: 2500 movne r5, #0 + 8005c32: 4293 cmp r3, r2 + 8005c34: bfc4 itt gt + 8005c36: 1a9b subgt r3, r3, r2 + 8005c38: 18ed addgt r5, r5, r3 + 8005c3a: f04f 0900 mov.w r9, #0 + 8005c3e: 341a adds r4, #26 + 8005c40: 454d cmp r5, r9 + 8005c42: d11a bne.n 8005c7a <_printf_common+0xd6> + 8005c44: 2000 movs r0, #0 + 8005c46: e008 b.n 8005c5a <_printf_common+0xb6> + 8005c48: 2301 movs r3, #1 + 8005c4a: 4652 mov r2, sl + 8005c4c: 4639 mov r1, r7 + 8005c4e: 4630 mov r0, r6 + 8005c50: 47c0 blx r8 + 8005c52: 3001 adds r0, #1 + 8005c54: d103 bne.n 8005c5e <_printf_common+0xba> + 8005c56: f04f 30ff mov.w r0, #4294967295 + 8005c5a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 8005c5e: 3501 adds r5, #1 + 8005c60: e7c3 b.n 8005bea <_printf_common+0x46> + 8005c62: 18e1 adds r1, r4, r3 + 8005c64: 1c5a adds r2, r3, #1 + 8005c66: 2030 movs r0, #48 ; 0x30 + 8005c68: f881 0043 strb.w r0, [r1, #67] ; 0x43 + 8005c6c: 4422 add r2, r4 + 8005c6e: f894 1045 ldrb.w r1, [r4, #69] ; 0x45 + 8005c72: f882 1043 strb.w r1, [r2, #67] ; 0x43 + 8005c76: 3302 adds r3, #2 + 8005c78: e7c5 b.n 8005c06 <_printf_common+0x62> + 8005c7a: 2301 movs r3, #1 + 8005c7c: 4622 mov r2, r4 + 8005c7e: 4639 mov r1, r7 + 8005c80: 4630 mov r0, r6 + 8005c82: 47c0 blx r8 + 8005c84: 3001 adds r0, #1 + 8005c86: d0e6 beq.n 8005c56 <_printf_common+0xb2> + 8005c88: f109 0901 add.w r9, r9, #1 + 8005c8c: e7d8 b.n 8005c40 <_printf_common+0x9c> + ... + +08005c90 <_printf_i>: + 8005c90: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} + 8005c94: f101 0c43 add.w ip, r1, #67 ; 0x43 + 8005c98: 460c mov r4, r1 + 8005c9a: 7e09 ldrb r1, [r1, #24] + 8005c9c: b085 sub sp, #20 + 8005c9e: 296e cmp r1, #110 ; 0x6e + 8005ca0: 4617 mov r7, r2 + 8005ca2: 4606 mov r6, r0 + 8005ca4: 4698 mov r8, r3 + 8005ca6: 9a0c ldr r2, [sp, #48] ; 0x30 + 8005ca8: f000 80b3 beq.w 8005e12 <_printf_i+0x182> + 8005cac: d822 bhi.n 8005cf4 <_printf_i+0x64> + 8005cae: 2963 cmp r1, #99 ; 0x63 + 8005cb0: d036 beq.n 8005d20 <_printf_i+0x90> + 8005cb2: d80a bhi.n 8005cca <_printf_i+0x3a> + 8005cb4: 2900 cmp r1, #0 + 8005cb6: f000 80b9 beq.w 8005e2c <_printf_i+0x19c> + 8005cba: 2958 cmp r1, #88 ; 0x58 + 8005cbc: f000 8083 beq.w 8005dc6 <_printf_i+0x136> + 8005cc0: f104 0542 add.w r5, r4, #66 ; 0x42 + 8005cc4: f884 1042 strb.w r1, [r4, #66] ; 0x42 + 8005cc8: e032 b.n 8005d30 <_printf_i+0xa0> + 8005cca: 2964 cmp r1, #100 ; 0x64 + 8005ccc: d001 beq.n 8005cd2 <_printf_i+0x42> + 8005cce: 2969 cmp r1, #105 ; 0x69 + 8005cd0: d1f6 bne.n 8005cc0 <_printf_i+0x30> + 8005cd2: 6820 ldr r0, [r4, #0] + 8005cd4: 6813 ldr r3, [r2, #0] + 8005cd6: 0605 lsls r5, r0, #24 + 8005cd8: f103 0104 add.w r1, r3, #4 + 8005cdc: d52a bpl.n 8005d34 <_printf_i+0xa4> + 8005cde: 681b ldr r3, [r3, #0] + 8005ce0: 6011 str r1, [r2, #0] + 8005ce2: 2b00 cmp r3, #0 + 8005ce4: da03 bge.n 8005cee <_printf_i+0x5e> + 8005ce6: 222d movs r2, #45 ; 0x2d + 8005ce8: 425b negs r3, r3 + 8005cea: f884 2043 strb.w r2, [r4, #67] ; 0x43 + 8005cee: 486f ldr r0, [pc, #444] ; (8005eac <_printf_i+0x21c>) + 8005cf0: 220a movs r2, #10 + 8005cf2: e039 b.n 8005d68 <_printf_i+0xd8> + 8005cf4: 2973 cmp r1, #115 ; 0x73 + 8005cf6: f000 809d beq.w 8005e34 <_printf_i+0x1a4> + 8005cfa: d808 bhi.n 8005d0e <_printf_i+0x7e> + 8005cfc: 296f cmp r1, #111 ; 0x6f + 8005cfe: d020 beq.n 8005d42 <_printf_i+0xb2> + 8005d00: 2970 cmp r1, #112 ; 0x70 + 8005d02: d1dd bne.n 8005cc0 <_printf_i+0x30> + 8005d04: 6823 ldr r3, [r4, #0] + 8005d06: f043 0320 orr.w r3, r3, #32 + 8005d0a: 6023 str r3, [r4, #0] + 8005d0c: e003 b.n 8005d16 <_printf_i+0x86> + 8005d0e: 2975 cmp r1, #117 ; 0x75 + 8005d10: d017 beq.n 8005d42 <_printf_i+0xb2> + 8005d12: 2978 cmp r1, #120 ; 0x78 + 8005d14: d1d4 bne.n 8005cc0 <_printf_i+0x30> + 8005d16: 2378 movs r3, #120 ; 0x78 + 8005d18: f884 3045 strb.w r3, [r4, #69] ; 0x45 + 8005d1c: 4864 ldr r0, [pc, #400] ; (8005eb0 <_printf_i+0x220>) + 8005d1e: e055 b.n 8005dcc <_printf_i+0x13c> + 8005d20: 6813 ldr r3, [r2, #0] + 8005d22: 1d19 adds r1, r3, #4 + 8005d24: 681b ldr r3, [r3, #0] + 8005d26: 6011 str r1, [r2, #0] + 8005d28: f104 0542 add.w r5, r4, #66 ; 0x42 + 8005d2c: f884 3042 strb.w r3, [r4, #66] ; 0x42 + 8005d30: 2301 movs r3, #1 + 8005d32: e08c b.n 8005e4e <_printf_i+0x1be> + 8005d34: 681b ldr r3, [r3, #0] + 8005d36: 6011 str r1, [r2, #0] + 8005d38: f010 0f40 tst.w r0, #64 ; 0x40 + 8005d3c: bf18 it ne + 8005d3e: b21b sxthne r3, r3 + 8005d40: e7cf b.n 8005ce2 <_printf_i+0x52> + 8005d42: 6813 ldr r3, [r2, #0] + 8005d44: 6825 ldr r5, [r4, #0] + 8005d46: 1d18 adds r0, r3, #4 + 8005d48: 6010 str r0, [r2, #0] + 8005d4a: 0628 lsls r0, r5, #24 + 8005d4c: d501 bpl.n 8005d52 <_printf_i+0xc2> + 8005d4e: 681b ldr r3, [r3, #0] + 8005d50: e002 b.n 8005d58 <_printf_i+0xc8> + 8005d52: 0668 lsls r0, r5, #25 + 8005d54: d5fb bpl.n 8005d4e <_printf_i+0xbe> + 8005d56: 881b ldrh r3, [r3, #0] + 8005d58: 4854 ldr r0, [pc, #336] ; (8005eac <_printf_i+0x21c>) + 8005d5a: 296f cmp r1, #111 ; 0x6f + 8005d5c: bf14 ite ne + 8005d5e: 220a movne r2, #10 + 8005d60: 2208 moveq r2, #8 + 8005d62: 2100 movs r1, #0 + 8005d64: f884 1043 strb.w r1, [r4, #67] ; 0x43 + 8005d68: 6865 ldr r5, [r4, #4] + 8005d6a: 60a5 str r5, [r4, #8] + 8005d6c: 2d00 cmp r5, #0 + 8005d6e: f2c0 8095 blt.w 8005e9c <_printf_i+0x20c> + 8005d72: 6821 ldr r1, [r4, #0] + 8005d74: f021 0104 bic.w r1, r1, #4 + 8005d78: 6021 str r1, [r4, #0] + 8005d7a: 2b00 cmp r3, #0 + 8005d7c: d13d bne.n 8005dfa <_printf_i+0x16a> + 8005d7e: 2d00 cmp r5, #0 + 8005d80: f040 808e bne.w 8005ea0 <_printf_i+0x210> + 8005d84: 4665 mov r5, ip + 8005d86: 2a08 cmp r2, #8 + 8005d88: d10b bne.n 8005da2 <_printf_i+0x112> + 8005d8a: 6823 ldr r3, [r4, #0] + 8005d8c: 07db lsls r3, r3, #31 + 8005d8e: d508 bpl.n 8005da2 <_printf_i+0x112> + 8005d90: 6923 ldr r3, [r4, #16] + 8005d92: 6862 ldr r2, [r4, #4] + 8005d94: 429a cmp r2, r3 + 8005d96: bfde ittt le + 8005d98: 2330 movle r3, #48 ; 0x30 + 8005d9a: f805 3c01 strble.w r3, [r5, #-1] + 8005d9e: f105 35ff addle.w r5, r5, #4294967295 + 8005da2: ebac 0305 sub.w r3, ip, r5 + 8005da6: 6123 str r3, [r4, #16] + 8005da8: f8cd 8000 str.w r8, [sp] + 8005dac: 463b mov r3, r7 + 8005dae: aa03 add r2, sp, #12 + 8005db0: 4621 mov r1, r4 + 8005db2: 4630 mov r0, r6 + 8005db4: f7ff fef6 bl 8005ba4 <_printf_common> + 8005db8: 3001 adds r0, #1 + 8005dba: d14d bne.n 8005e58 <_printf_i+0x1c8> + 8005dbc: f04f 30ff mov.w r0, #4294967295 + 8005dc0: b005 add sp, #20 + 8005dc2: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} + 8005dc6: 4839 ldr r0, [pc, #228] ; (8005eac <_printf_i+0x21c>) + 8005dc8: f884 1045 strb.w r1, [r4, #69] ; 0x45 + 8005dcc: 6813 ldr r3, [r2, #0] + 8005dce: 6821 ldr r1, [r4, #0] + 8005dd0: 1d1d adds r5, r3, #4 + 8005dd2: 681b ldr r3, [r3, #0] + 8005dd4: 6015 str r5, [r2, #0] + 8005dd6: 060a lsls r2, r1, #24 + 8005dd8: d50b bpl.n 8005df2 <_printf_i+0x162> + 8005dda: 07ca lsls r2, r1, #31 + 8005ddc: bf44 itt mi + 8005dde: f041 0120 orrmi.w r1, r1, #32 + 8005de2: 6021 strmi r1, [r4, #0] + 8005de4: b91b cbnz r3, 8005dee <_printf_i+0x15e> + 8005de6: 6822 ldr r2, [r4, #0] + 8005de8: f022 0220 bic.w r2, r2, #32 + 8005dec: 6022 str r2, [r4, #0] + 8005dee: 2210 movs r2, #16 + 8005df0: e7b7 b.n 8005d62 <_printf_i+0xd2> + 8005df2: 064d lsls r5, r1, #25 + 8005df4: bf48 it mi + 8005df6: b29b uxthmi r3, r3 + 8005df8: e7ef b.n 8005dda <_printf_i+0x14a> + 8005dfa: 4665 mov r5, ip + 8005dfc: fbb3 f1f2 udiv r1, r3, r2 + 8005e00: fb02 3311 mls r3, r2, r1, r3 + 8005e04: 5cc3 ldrb r3, [r0, r3] + 8005e06: f805 3d01 strb.w r3, [r5, #-1]! + 8005e0a: 460b mov r3, r1 + 8005e0c: 2900 cmp r1, #0 + 8005e0e: d1f5 bne.n 8005dfc <_printf_i+0x16c> + 8005e10: e7b9 b.n 8005d86 <_printf_i+0xf6> + 8005e12: 6813 ldr r3, [r2, #0] + 8005e14: 6825 ldr r5, [r4, #0] + 8005e16: 6961 ldr r1, [r4, #20] + 8005e18: 1d18 adds r0, r3, #4 + 8005e1a: 6010 str r0, [r2, #0] + 8005e1c: 0628 lsls r0, r5, #24 + 8005e1e: 681b ldr r3, [r3, #0] + 8005e20: d501 bpl.n 8005e26 <_printf_i+0x196> + 8005e22: 6019 str r1, [r3, #0] + 8005e24: e002 b.n 8005e2c <_printf_i+0x19c> + 8005e26: 066a lsls r2, r5, #25 + 8005e28: d5fb bpl.n 8005e22 <_printf_i+0x192> + 8005e2a: 8019 strh r1, [r3, #0] + 8005e2c: 2300 movs r3, #0 + 8005e2e: 6123 str r3, [r4, #16] + 8005e30: 4665 mov r5, ip + 8005e32: e7b9 b.n 8005da8 <_printf_i+0x118> + 8005e34: 6813 ldr r3, [r2, #0] + 8005e36: 1d19 adds r1, r3, #4 + 8005e38: 6011 str r1, [r2, #0] + 8005e3a: 681d ldr r5, [r3, #0] + 8005e3c: 6862 ldr r2, [r4, #4] + 8005e3e: 2100 movs r1, #0 + 8005e40: 4628 mov r0, r5 + 8005e42: f7fa f9d5 bl 80001f0 + 8005e46: b108 cbz r0, 8005e4c <_printf_i+0x1bc> + 8005e48: 1b40 subs r0, r0, r5 + 8005e4a: 6060 str r0, [r4, #4] + 8005e4c: 6863 ldr r3, [r4, #4] + 8005e4e: 6123 str r3, [r4, #16] + 8005e50: 2300 movs r3, #0 + 8005e52: f884 3043 strb.w r3, [r4, #67] ; 0x43 + 8005e56: e7a7 b.n 8005da8 <_printf_i+0x118> + 8005e58: 6923 ldr r3, [r4, #16] + 8005e5a: 462a mov r2, r5 + 8005e5c: 4639 mov r1, r7 + 8005e5e: 4630 mov r0, r6 + 8005e60: 47c0 blx r8 + 8005e62: 3001 adds r0, #1 + 8005e64: d0aa beq.n 8005dbc <_printf_i+0x12c> + 8005e66: 6823 ldr r3, [r4, #0] + 8005e68: 079b lsls r3, r3, #30 + 8005e6a: d413 bmi.n 8005e94 <_printf_i+0x204> + 8005e6c: 68e0 ldr r0, [r4, #12] + 8005e6e: 9b03 ldr r3, [sp, #12] + 8005e70: 4298 cmp r0, r3 + 8005e72: bfb8 it lt + 8005e74: 4618 movlt r0, r3 + 8005e76: e7a3 b.n 8005dc0 <_printf_i+0x130> + 8005e78: 2301 movs r3, #1 + 8005e7a: 464a mov r2, r9 + 8005e7c: 4639 mov r1, r7 + 8005e7e: 4630 mov r0, r6 + 8005e80: 47c0 blx r8 + 8005e82: 3001 adds r0, #1 + 8005e84: d09a beq.n 8005dbc <_printf_i+0x12c> + 8005e86: 3501 adds r5, #1 + 8005e88: 68e3 ldr r3, [r4, #12] + 8005e8a: 9a03 ldr r2, [sp, #12] + 8005e8c: 1a9b subs r3, r3, r2 + 8005e8e: 42ab cmp r3, r5 + 8005e90: dcf2 bgt.n 8005e78 <_printf_i+0x1e8> + 8005e92: e7eb b.n 8005e6c <_printf_i+0x1dc> + 8005e94: 2500 movs r5, #0 + 8005e96: f104 0919 add.w r9, r4, #25 + 8005e9a: e7f5 b.n 8005e88 <_printf_i+0x1f8> + 8005e9c: 2b00 cmp r3, #0 + 8005e9e: d1ac bne.n 8005dfa <_printf_i+0x16a> + 8005ea0: 7803 ldrb r3, [r0, #0] + 8005ea2: f884 3042 strb.w r3, [r4, #66] ; 0x42 + 8005ea6: f104 0542 add.w r5, r4, #66 ; 0x42 + 8005eaa: e76c b.n 8005d86 <_printf_i+0xf6> + 8005eac: 08009a4e .word 0x08009a4e + 8005eb0: 08009a5f .word 0x08009a5f + +08005eb4 <_scanf_float>: + 8005eb4: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 8005eb8: 469a mov sl, r3 + 8005eba: 688b ldr r3, [r1, #8] + 8005ebc: 4616 mov r6, r2 + 8005ebe: 1e5a subs r2, r3, #1 + 8005ec0: f5b2 7fae cmp.w r2, #348 ; 0x15c + 8005ec4: b087 sub sp, #28 + 8005ec6: bf83 ittte hi + 8005ec8: f46f 72ae mvnhi.w r2, #348 ; 0x15c + 8005ecc: 189b addhi r3, r3, r2 + 8005ece: 9301 strhi r3, [sp, #4] + 8005ed0: 2300 movls r3, #0 + 8005ed2: bf86 itte hi + 8005ed4: f240 135d movwhi r3, #349 ; 0x15d + 8005ed8: 608b strhi r3, [r1, #8] + 8005eda: 9301 strls r3, [sp, #4] + 8005edc: 680b ldr r3, [r1, #0] + 8005ede: 4688 mov r8, r1 + 8005ee0: f04f 0b00 mov.w fp, #0 + 8005ee4: f443 63f0 orr.w r3, r3, #1920 ; 0x780 + 8005ee8: f848 3b1c str.w r3, [r8], #28 + 8005eec: e9cd bb03 strd fp, fp, [sp, #12] + 8005ef0: 4607 mov r7, r0 + 8005ef2: 460c mov r4, r1 + 8005ef4: 4645 mov r5, r8 + 8005ef6: 465a mov r2, fp + 8005ef8: 46d9 mov r9, fp + 8005efa: f8cd b008 str.w fp, [sp, #8] + 8005efe: 68a1 ldr r1, [r4, #8] + 8005f00: b181 cbz r1, 8005f24 <_scanf_float+0x70> + 8005f02: 6833 ldr r3, [r6, #0] + 8005f04: 781b ldrb r3, [r3, #0] + 8005f06: 2b49 cmp r3, #73 ; 0x49 + 8005f08: d071 beq.n 8005fee <_scanf_float+0x13a> + 8005f0a: d84d bhi.n 8005fa8 <_scanf_float+0xf4> + 8005f0c: 2b39 cmp r3, #57 ; 0x39 + 8005f0e: d840 bhi.n 8005f92 <_scanf_float+0xde> + 8005f10: 2b31 cmp r3, #49 ; 0x31 + 8005f12: f080 8088 bcs.w 8006026 <_scanf_float+0x172> + 8005f16: 2b2d cmp r3, #45 ; 0x2d + 8005f18: f000 8090 beq.w 800603c <_scanf_float+0x188> + 8005f1c: d815 bhi.n 8005f4a <_scanf_float+0x96> + 8005f1e: 2b2b cmp r3, #43 ; 0x2b + 8005f20: f000 808c beq.w 800603c <_scanf_float+0x188> + 8005f24: f1b9 0f00 cmp.w r9, #0 + 8005f28: d003 beq.n 8005f32 <_scanf_float+0x7e> + 8005f2a: 6823 ldr r3, [r4, #0] + 8005f2c: f423 7380 bic.w r3, r3, #256 ; 0x100 + 8005f30: 6023 str r3, [r4, #0] + 8005f32: 3a01 subs r2, #1 + 8005f34: 2a01 cmp r2, #1 + 8005f36: f200 80ea bhi.w 800610e <_scanf_float+0x25a> + 8005f3a: 4545 cmp r5, r8 + 8005f3c: f200 80dc bhi.w 80060f8 <_scanf_float+0x244> + 8005f40: 2601 movs r6, #1 + 8005f42: 4630 mov r0, r6 + 8005f44: b007 add sp, #28 + 8005f46: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 8005f4a: 2b2e cmp r3, #46 ; 0x2e + 8005f4c: f000 809f beq.w 800608e <_scanf_float+0x1da> + 8005f50: 2b30 cmp r3, #48 ; 0x30 + 8005f52: d1e7 bne.n 8005f24 <_scanf_float+0x70> + 8005f54: 6820 ldr r0, [r4, #0] + 8005f56: f410 7f80 tst.w r0, #256 ; 0x100 + 8005f5a: d064 beq.n 8006026 <_scanf_float+0x172> + 8005f5c: 9b01 ldr r3, [sp, #4] + 8005f5e: f020 0080 bic.w r0, r0, #128 ; 0x80 + 8005f62: 6020 str r0, [r4, #0] + 8005f64: f109 0901 add.w r9, r9, #1 + 8005f68: b11b cbz r3, 8005f72 <_scanf_float+0xbe> + 8005f6a: 3b01 subs r3, #1 + 8005f6c: 3101 adds r1, #1 + 8005f6e: 9301 str r3, [sp, #4] + 8005f70: 60a1 str r1, [r4, #8] + 8005f72: 68a3 ldr r3, [r4, #8] + 8005f74: 3b01 subs r3, #1 + 8005f76: 60a3 str r3, [r4, #8] + 8005f78: 6923 ldr r3, [r4, #16] + 8005f7a: 3301 adds r3, #1 + 8005f7c: 6123 str r3, [r4, #16] + 8005f7e: 6873 ldr r3, [r6, #4] + 8005f80: 3b01 subs r3, #1 + 8005f82: 2b00 cmp r3, #0 + 8005f84: 6073 str r3, [r6, #4] + 8005f86: f340 80ac ble.w 80060e2 <_scanf_float+0x22e> + 8005f8a: 6833 ldr r3, [r6, #0] + 8005f8c: 3301 adds r3, #1 + 8005f8e: 6033 str r3, [r6, #0] + 8005f90: e7b5 b.n 8005efe <_scanf_float+0x4a> + 8005f92: 2b45 cmp r3, #69 ; 0x45 + 8005f94: f000 8085 beq.w 80060a2 <_scanf_float+0x1ee> + 8005f98: 2b46 cmp r3, #70 ; 0x46 + 8005f9a: d06a beq.n 8006072 <_scanf_float+0x1be> + 8005f9c: 2b41 cmp r3, #65 ; 0x41 + 8005f9e: d1c1 bne.n 8005f24 <_scanf_float+0x70> + 8005fa0: 2a01 cmp r2, #1 + 8005fa2: d1bf bne.n 8005f24 <_scanf_float+0x70> + 8005fa4: 2202 movs r2, #2 + 8005fa6: e046 b.n 8006036 <_scanf_float+0x182> + 8005fa8: 2b65 cmp r3, #101 ; 0x65 + 8005faa: d07a beq.n 80060a2 <_scanf_float+0x1ee> + 8005fac: d818 bhi.n 8005fe0 <_scanf_float+0x12c> + 8005fae: 2b54 cmp r3, #84 ; 0x54 + 8005fb0: d066 beq.n 8006080 <_scanf_float+0x1cc> + 8005fb2: d811 bhi.n 8005fd8 <_scanf_float+0x124> + 8005fb4: 2b4e cmp r3, #78 ; 0x4e + 8005fb6: d1b5 bne.n 8005f24 <_scanf_float+0x70> + 8005fb8: 2a00 cmp r2, #0 + 8005fba: d146 bne.n 800604a <_scanf_float+0x196> + 8005fbc: f1b9 0f00 cmp.w r9, #0 + 8005fc0: d145 bne.n 800604e <_scanf_float+0x19a> + 8005fc2: 6821 ldr r1, [r4, #0] + 8005fc4: f401 60e0 and.w r0, r1, #1792 ; 0x700 + 8005fc8: f5b0 6fe0 cmp.w r0, #1792 ; 0x700 + 8005fcc: d13f bne.n 800604e <_scanf_float+0x19a> + 8005fce: f421 61f0 bic.w r1, r1, #1920 ; 0x780 + 8005fd2: 6021 str r1, [r4, #0] + 8005fd4: 2201 movs r2, #1 + 8005fd6: e02e b.n 8006036 <_scanf_float+0x182> + 8005fd8: 2b59 cmp r3, #89 ; 0x59 + 8005fda: d01e beq.n 800601a <_scanf_float+0x166> + 8005fdc: 2b61 cmp r3, #97 ; 0x61 + 8005fde: e7de b.n 8005f9e <_scanf_float+0xea> + 8005fe0: 2b6e cmp r3, #110 ; 0x6e + 8005fe2: d0e9 beq.n 8005fb8 <_scanf_float+0x104> + 8005fe4: d815 bhi.n 8006012 <_scanf_float+0x15e> + 8005fe6: 2b66 cmp r3, #102 ; 0x66 + 8005fe8: d043 beq.n 8006072 <_scanf_float+0x1be> + 8005fea: 2b69 cmp r3, #105 ; 0x69 + 8005fec: d19a bne.n 8005f24 <_scanf_float+0x70> + 8005fee: f1bb 0f00 cmp.w fp, #0 + 8005ff2: d138 bne.n 8006066 <_scanf_float+0x1b2> + 8005ff4: f1b9 0f00 cmp.w r9, #0 + 8005ff8: d197 bne.n 8005f2a <_scanf_float+0x76> + 8005ffa: 6821 ldr r1, [r4, #0] + 8005ffc: f401 60e0 and.w r0, r1, #1792 ; 0x700 + 8006000: f5b0 6fe0 cmp.w r0, #1792 ; 0x700 + 8006004: d195 bne.n 8005f32 <_scanf_float+0x7e> + 8006006: f421 61f0 bic.w r1, r1, #1920 ; 0x780 + 800600a: 6021 str r1, [r4, #0] + 800600c: f04f 0b01 mov.w fp, #1 + 8006010: e011 b.n 8006036 <_scanf_float+0x182> + 8006012: 2b74 cmp r3, #116 ; 0x74 + 8006014: d034 beq.n 8006080 <_scanf_float+0x1cc> + 8006016: 2b79 cmp r3, #121 ; 0x79 + 8006018: d184 bne.n 8005f24 <_scanf_float+0x70> + 800601a: f1bb 0f07 cmp.w fp, #7 + 800601e: d181 bne.n 8005f24 <_scanf_float+0x70> + 8006020: f04f 0b08 mov.w fp, #8 + 8006024: e007 b.n 8006036 <_scanf_float+0x182> + 8006026: eb12 0f0b cmn.w r2, fp + 800602a: f47f af7b bne.w 8005f24 <_scanf_float+0x70> + 800602e: 6821 ldr r1, [r4, #0] + 8006030: f421 71c0 bic.w r1, r1, #384 ; 0x180 + 8006034: 6021 str r1, [r4, #0] + 8006036: 702b strb r3, [r5, #0] + 8006038: 3501 adds r5, #1 + 800603a: e79a b.n 8005f72 <_scanf_float+0xbe> + 800603c: 6821 ldr r1, [r4, #0] + 800603e: 0608 lsls r0, r1, #24 + 8006040: f57f af70 bpl.w 8005f24 <_scanf_float+0x70> + 8006044: f021 0180 bic.w r1, r1, #128 ; 0x80 + 8006048: e7f4 b.n 8006034 <_scanf_float+0x180> + 800604a: 2a02 cmp r2, #2 + 800604c: d047 beq.n 80060de <_scanf_float+0x22a> + 800604e: f1bb 0f01 cmp.w fp, #1 + 8006052: d003 beq.n 800605c <_scanf_float+0x1a8> + 8006054: f1bb 0f04 cmp.w fp, #4 + 8006058: f47f af64 bne.w 8005f24 <_scanf_float+0x70> + 800605c: f10b 0b01 add.w fp, fp, #1 + 8006060: fa5f fb8b uxtb.w fp, fp + 8006064: e7e7 b.n 8006036 <_scanf_float+0x182> + 8006066: f1bb 0f03 cmp.w fp, #3 + 800606a: d0f7 beq.n 800605c <_scanf_float+0x1a8> + 800606c: f1bb 0f05 cmp.w fp, #5 + 8006070: e7f2 b.n 8006058 <_scanf_float+0x1a4> + 8006072: f1bb 0f02 cmp.w fp, #2 + 8006076: f47f af55 bne.w 8005f24 <_scanf_float+0x70> + 800607a: f04f 0b03 mov.w fp, #3 + 800607e: e7da b.n 8006036 <_scanf_float+0x182> + 8006080: f1bb 0f06 cmp.w fp, #6 + 8006084: f47f af4e bne.w 8005f24 <_scanf_float+0x70> + 8006088: f04f 0b07 mov.w fp, #7 + 800608c: e7d3 b.n 8006036 <_scanf_float+0x182> + 800608e: 6821 ldr r1, [r4, #0] + 8006090: 0588 lsls r0, r1, #22 + 8006092: f57f af47 bpl.w 8005f24 <_scanf_float+0x70> + 8006096: f421 7120 bic.w r1, r1, #640 ; 0x280 + 800609a: 6021 str r1, [r4, #0] + 800609c: f8cd 9008 str.w r9, [sp, #8] + 80060a0: e7c9 b.n 8006036 <_scanf_float+0x182> + 80060a2: 6821 ldr r1, [r4, #0] + 80060a4: f401 60a0 and.w r0, r1, #1280 ; 0x500 + 80060a8: f5b0 6f80 cmp.w r0, #1024 ; 0x400 + 80060ac: d006 beq.n 80060bc <_scanf_float+0x208> + 80060ae: 0548 lsls r0, r1, #21 + 80060b0: f57f af38 bpl.w 8005f24 <_scanf_float+0x70> + 80060b4: f1b9 0f00 cmp.w r9, #0 + 80060b8: f43f af3b beq.w 8005f32 <_scanf_float+0x7e> + 80060bc: 0588 lsls r0, r1, #22 + 80060be: bf58 it pl + 80060c0: 9802 ldrpl r0, [sp, #8] + 80060c2: f421 61f0 bic.w r1, r1, #1920 ; 0x780 + 80060c6: bf58 it pl + 80060c8: eba9 0000 subpl.w r0, r9, r0 + 80060cc: f441 71c0 orr.w r1, r1, #384 ; 0x180 + 80060d0: bf58 it pl + 80060d2: e9cd 0503 strdpl r0, r5, [sp, #12] + 80060d6: 6021 str r1, [r4, #0] + 80060d8: f04f 0900 mov.w r9, #0 + 80060dc: e7ab b.n 8006036 <_scanf_float+0x182> + 80060de: 2203 movs r2, #3 + 80060e0: e7a9 b.n 8006036 <_scanf_float+0x182> + 80060e2: f8d4 3180 ldr.w r3, [r4, #384] ; 0x180 + 80060e6: 9205 str r2, [sp, #20] + 80060e8: 4631 mov r1, r6 + 80060ea: 4638 mov r0, r7 + 80060ec: 4798 blx r3 + 80060ee: 9a05 ldr r2, [sp, #20] + 80060f0: 2800 cmp r0, #0 + 80060f2: f43f af04 beq.w 8005efe <_scanf_float+0x4a> + 80060f6: e715 b.n 8005f24 <_scanf_float+0x70> + 80060f8: f8d4 317c ldr.w r3, [r4, #380] ; 0x17c + 80060fc: f815 1d01 ldrb.w r1, [r5, #-1]! + 8006100: 4632 mov r2, r6 + 8006102: 4638 mov r0, r7 + 8006104: 4798 blx r3 + 8006106: 6923 ldr r3, [r4, #16] + 8006108: 3b01 subs r3, #1 + 800610a: 6123 str r3, [r4, #16] + 800610c: e715 b.n 8005f3a <_scanf_float+0x86> + 800610e: f10b 33ff add.w r3, fp, #4294967295 + 8006112: 2b06 cmp r3, #6 + 8006114: d80a bhi.n 800612c <_scanf_float+0x278> + 8006116: f1bb 0f02 cmp.w fp, #2 + 800611a: d968 bls.n 80061ee <_scanf_float+0x33a> + 800611c: f1ab 0b03 sub.w fp, fp, #3 + 8006120: fa5f fb8b uxtb.w fp, fp + 8006124: eba5 0b0b sub.w fp, r5, fp + 8006128: 455d cmp r5, fp + 800612a: d14b bne.n 80061c4 <_scanf_float+0x310> + 800612c: 6823 ldr r3, [r4, #0] + 800612e: 05da lsls r2, r3, #23 + 8006130: d51f bpl.n 8006172 <_scanf_float+0x2be> + 8006132: 055b lsls r3, r3, #21 + 8006134: d468 bmi.n 8006208 <_scanf_float+0x354> + 8006136: f815 1c01 ldrb.w r1, [r5, #-1] + 800613a: 6923 ldr r3, [r4, #16] + 800613c: 2965 cmp r1, #101 ; 0x65 + 800613e: f103 33ff add.w r3, r3, #4294967295 + 8006142: f105 3bff add.w fp, r5, #4294967295 + 8006146: 6123 str r3, [r4, #16] + 8006148: d00d beq.n 8006166 <_scanf_float+0x2b2> + 800614a: 2945 cmp r1, #69 ; 0x45 + 800614c: d00b beq.n 8006166 <_scanf_float+0x2b2> + 800614e: f8d4 317c ldr.w r3, [r4, #380] ; 0x17c + 8006152: 4632 mov r2, r6 + 8006154: 4638 mov r0, r7 + 8006156: 4798 blx r3 + 8006158: 6923 ldr r3, [r4, #16] + 800615a: f815 1c02 ldrb.w r1, [r5, #-2] + 800615e: 3b01 subs r3, #1 + 8006160: f1a5 0b02 sub.w fp, r5, #2 + 8006164: 6123 str r3, [r4, #16] + 8006166: f8d4 317c ldr.w r3, [r4, #380] ; 0x17c + 800616a: 4632 mov r2, r6 + 800616c: 4638 mov r0, r7 + 800616e: 4798 blx r3 + 8006170: 465d mov r5, fp + 8006172: 6826 ldr r6, [r4, #0] + 8006174: f016 0610 ands.w r6, r6, #16 + 8006178: d17a bne.n 8006270 <_scanf_float+0x3bc> + 800617a: 702e strb r6, [r5, #0] + 800617c: 6823 ldr r3, [r4, #0] + 800617e: f403 63c0 and.w r3, r3, #1536 ; 0x600 + 8006182: f5b3 6f80 cmp.w r3, #1024 ; 0x400 + 8006186: d142 bne.n 800620e <_scanf_float+0x35a> + 8006188: 9b02 ldr r3, [sp, #8] + 800618a: eba9 0303 sub.w r3, r9, r3 + 800618e: 425a negs r2, r3 + 8006190: 2b00 cmp r3, #0 + 8006192: d149 bne.n 8006228 <_scanf_float+0x374> + 8006194: 2200 movs r2, #0 + 8006196: 4641 mov r1, r8 + 8006198: 4638 mov r0, r7 + 800619a: f000 ff31 bl 8007000 <_strtod_r> + 800619e: 6825 ldr r5, [r4, #0] + 80061a0: f8da 3000 ldr.w r3, [sl] + 80061a4: f015 0f02 tst.w r5, #2 + 80061a8: f103 0204 add.w r2, r3, #4 + 80061ac: ec59 8b10 vmov r8, r9, d0 + 80061b0: f8ca 2000 str.w r2, [sl] + 80061b4: d043 beq.n 800623e <_scanf_float+0x38a> + 80061b6: 681b ldr r3, [r3, #0] + 80061b8: e9c3 8900 strd r8, r9, [r3] + 80061bc: 68e3 ldr r3, [r4, #12] + 80061be: 3301 adds r3, #1 + 80061c0: 60e3 str r3, [r4, #12] + 80061c2: e6be b.n 8005f42 <_scanf_float+0x8e> + 80061c4: f8d4 317c ldr.w r3, [r4, #380] ; 0x17c + 80061c8: f815 1d01 ldrb.w r1, [r5, #-1]! + 80061cc: 4632 mov r2, r6 + 80061ce: 4638 mov r0, r7 + 80061d0: 4798 blx r3 + 80061d2: 6923 ldr r3, [r4, #16] + 80061d4: 3b01 subs r3, #1 + 80061d6: 6123 str r3, [r4, #16] + 80061d8: e7a6 b.n 8006128 <_scanf_float+0x274> + 80061da: f8d4 317c ldr.w r3, [r4, #380] ; 0x17c + 80061de: f815 1d01 ldrb.w r1, [r5, #-1]! + 80061e2: 4632 mov r2, r6 + 80061e4: 4638 mov r0, r7 + 80061e6: 4798 blx r3 + 80061e8: 6923 ldr r3, [r4, #16] + 80061ea: 3b01 subs r3, #1 + 80061ec: 6123 str r3, [r4, #16] + 80061ee: 4545 cmp r5, r8 + 80061f0: d8f3 bhi.n 80061da <_scanf_float+0x326> + 80061f2: e6a5 b.n 8005f40 <_scanf_float+0x8c> + 80061f4: f8d4 317c ldr.w r3, [r4, #380] ; 0x17c + 80061f8: f815 1d01 ldrb.w r1, [r5, #-1]! + 80061fc: 4632 mov r2, r6 + 80061fe: 4638 mov r0, r7 + 8006200: 4798 blx r3 + 8006202: 6923 ldr r3, [r4, #16] + 8006204: 3b01 subs r3, #1 + 8006206: 6123 str r3, [r4, #16] + 8006208: 4545 cmp r5, r8 + 800620a: d8f3 bhi.n 80061f4 <_scanf_float+0x340> + 800620c: e698 b.n 8005f40 <_scanf_float+0x8c> + 800620e: 9b03 ldr r3, [sp, #12] + 8006210: 2b00 cmp r3, #0 + 8006212: d0bf beq.n 8006194 <_scanf_float+0x2e0> + 8006214: 9904 ldr r1, [sp, #16] + 8006216: 230a movs r3, #10 + 8006218: 4632 mov r2, r6 + 800621a: 3101 adds r1, #1 + 800621c: 4638 mov r0, r7 + 800621e: f000 ff7b bl 8007118 <_strtol_r> + 8006222: 9b03 ldr r3, [sp, #12] + 8006224: 9d04 ldr r5, [sp, #16] + 8006226: 1ac2 subs r2, r0, r3 + 8006228: f204 136f addw r3, r4, #367 ; 0x16f + 800622c: 429d cmp r5, r3 + 800622e: bf28 it cs + 8006230: f504 75b7 addcs.w r5, r4, #366 ; 0x16e + 8006234: 490f ldr r1, [pc, #60] ; (8006274 <_scanf_float+0x3c0>) + 8006236: 4628 mov r0, r5 + 8006238: f000 f8b0 bl 800639c + 800623c: e7aa b.n 8006194 <_scanf_float+0x2e0> + 800623e: f015 0504 ands.w r5, r5, #4 + 8006242: d1b8 bne.n 80061b6 <_scanf_float+0x302> + 8006244: 681f ldr r7, [r3, #0] + 8006246: ee10 2a10 vmov r2, s0 + 800624a: 464b mov r3, r9 + 800624c: ee10 0a10 vmov r0, s0 + 8006250: 4649 mov r1, r9 + 8006252: f7fa fc73 bl 8000b3c <__aeabi_dcmpun> + 8006256: b128 cbz r0, 8006264 <_scanf_float+0x3b0> + 8006258: 4628 mov r0, r5 + 800625a: f000 f899 bl 8006390 + 800625e: ed87 0a00 vstr s0, [r7] + 8006262: e7ab b.n 80061bc <_scanf_float+0x308> + 8006264: 4640 mov r0, r8 + 8006266: 4649 mov r1, r9 + 8006268: f7fa fcc6 bl 8000bf8 <__aeabi_d2f> + 800626c: 6038 str r0, [r7, #0] + 800626e: e7a5 b.n 80061bc <_scanf_float+0x308> + 8006270: 2600 movs r6, #0 + 8006272: e666 b.n 8005f42 <_scanf_float+0x8e> + 8006274: 08009a70 .word 0x08009a70 + +08006278 : + 8006278: b40f push {r0, r1, r2, r3} + 800627a: 4b0a ldr r3, [pc, #40] ; (80062a4 ) + 800627c: b513 push {r0, r1, r4, lr} + 800627e: 681c ldr r4, [r3, #0] + 8006280: b124 cbz r4, 800628c + 8006282: 69a3 ldr r3, [r4, #24] + 8006284: b913 cbnz r3, 800628c + 8006286: 4620 mov r0, r4 + 8006288: f001 ff4e bl 8008128 <__sinit> + 800628c: ab05 add r3, sp, #20 + 800628e: 9a04 ldr r2, [sp, #16] + 8006290: 68a1 ldr r1, [r4, #8] + 8006292: 9301 str r3, [sp, #4] + 8006294: 4620 mov r0, r4 + 8006296: f003 f917 bl 80094c8 <_vfiprintf_r> + 800629a: b002 add sp, #8 + 800629c: e8bd 4010 ldmia.w sp!, {r4, lr} + 80062a0: b004 add sp, #16 + 80062a2: 4770 bx lr + 80062a4: 2000002c .word 0x2000002c + +080062a8 <_puts_r>: + 80062a8: b570 push {r4, r5, r6, lr} + 80062aa: 460e mov r6, r1 + 80062ac: 4605 mov r5, r0 + 80062ae: b118 cbz r0, 80062b8 <_puts_r+0x10> + 80062b0: 6983 ldr r3, [r0, #24] + 80062b2: b90b cbnz r3, 80062b8 <_puts_r+0x10> + 80062b4: f001 ff38 bl 8008128 <__sinit> + 80062b8: 69ab ldr r3, [r5, #24] + 80062ba: 68ac ldr r4, [r5, #8] + 80062bc: b913 cbnz r3, 80062c4 <_puts_r+0x1c> + 80062be: 4628 mov r0, r5 + 80062c0: f001 ff32 bl 8008128 <__sinit> + 80062c4: 4b23 ldr r3, [pc, #140] ; (8006354 <_puts_r+0xac>) + 80062c6: 429c cmp r4, r3 + 80062c8: d117 bne.n 80062fa <_puts_r+0x52> + 80062ca: 686c ldr r4, [r5, #4] + 80062cc: 89a3 ldrh r3, [r4, #12] + 80062ce: 071b lsls r3, r3, #28 + 80062d0: d51d bpl.n 800630e <_puts_r+0x66> + 80062d2: 6923 ldr r3, [r4, #16] + 80062d4: b1db cbz r3, 800630e <_puts_r+0x66> + 80062d6: 3e01 subs r6, #1 + 80062d8: 68a3 ldr r3, [r4, #8] + 80062da: f816 1f01 ldrb.w r1, [r6, #1]! + 80062de: 3b01 subs r3, #1 + 80062e0: 60a3 str r3, [r4, #8] + 80062e2: b9e9 cbnz r1, 8006320 <_puts_r+0x78> + 80062e4: 2b00 cmp r3, #0 + 80062e6: da2e bge.n 8006346 <_puts_r+0x9e> + 80062e8: 4622 mov r2, r4 + 80062ea: 210a movs r1, #10 + 80062ec: 4628 mov r0, r5 + 80062ee: f000 ff25 bl 800713c <__swbuf_r> + 80062f2: 3001 adds r0, #1 + 80062f4: d011 beq.n 800631a <_puts_r+0x72> + 80062f6: 200a movs r0, #10 + 80062f8: e011 b.n 800631e <_puts_r+0x76> + 80062fa: 4b17 ldr r3, [pc, #92] ; (8006358 <_puts_r+0xb0>) + 80062fc: 429c cmp r4, r3 + 80062fe: d101 bne.n 8006304 <_puts_r+0x5c> + 8006300: 68ac ldr r4, [r5, #8] + 8006302: e7e3 b.n 80062cc <_puts_r+0x24> + 8006304: 4b15 ldr r3, [pc, #84] ; (800635c <_puts_r+0xb4>) + 8006306: 429c cmp r4, r3 + 8006308: bf08 it eq + 800630a: 68ec ldreq r4, [r5, #12] + 800630c: e7de b.n 80062cc <_puts_r+0x24> + 800630e: 4621 mov r1, r4 + 8006310: 4628 mov r0, r5 + 8006312: f000 ff65 bl 80071e0 <__swsetup_r> + 8006316: 2800 cmp r0, #0 + 8006318: d0dd beq.n 80062d6 <_puts_r+0x2e> + 800631a: f04f 30ff mov.w r0, #4294967295 + 800631e: bd70 pop {r4, r5, r6, pc} + 8006320: 2b00 cmp r3, #0 + 8006322: da04 bge.n 800632e <_puts_r+0x86> + 8006324: 69a2 ldr r2, [r4, #24] + 8006326: 429a cmp r2, r3 + 8006328: dc06 bgt.n 8006338 <_puts_r+0x90> + 800632a: 290a cmp r1, #10 + 800632c: d004 beq.n 8006338 <_puts_r+0x90> + 800632e: 6823 ldr r3, [r4, #0] + 8006330: 1c5a adds r2, r3, #1 + 8006332: 6022 str r2, [r4, #0] + 8006334: 7019 strb r1, [r3, #0] + 8006336: e7cf b.n 80062d8 <_puts_r+0x30> + 8006338: 4622 mov r2, r4 + 800633a: 4628 mov r0, r5 + 800633c: f000 fefe bl 800713c <__swbuf_r> + 8006340: 3001 adds r0, #1 + 8006342: d1c9 bne.n 80062d8 <_puts_r+0x30> + 8006344: e7e9 b.n 800631a <_puts_r+0x72> + 8006346: 6823 ldr r3, [r4, #0] + 8006348: 200a movs r0, #10 + 800634a: 1c5a adds r2, r3, #1 + 800634c: 6022 str r2, [r4, #0] + 800634e: 7018 strb r0, [r3, #0] + 8006350: e7e5 b.n 800631e <_puts_r+0x76> + 8006352: bf00 nop + 8006354: 08009af8 .word 0x08009af8 + 8006358: 08009b18 .word 0x08009b18 + 800635c: 08009ad8 .word 0x08009ad8 + +08006360 : + 8006360: 4b02 ldr r3, [pc, #8] ; (800636c ) + 8006362: 4601 mov r1, r0 + 8006364: 6818 ldr r0, [r3, #0] + 8006366: f7ff bf9f b.w 80062a8 <_puts_r> + 800636a: bf00 nop + 800636c: 2000002c .word 0x2000002c + +08006370 <_sbrk_r>: + 8006370: b538 push {r3, r4, r5, lr} + 8006372: 4c06 ldr r4, [pc, #24] ; (800638c <_sbrk_r+0x1c>) + 8006374: 2300 movs r3, #0 + 8006376: 4605 mov r5, r0 + 8006378: 4608 mov r0, r1 + 800637a: 6023 str r3, [r4, #0] + 800637c: f7fb f9f8 bl 8001770 <_sbrk> + 8006380: 1c43 adds r3, r0, #1 + 8006382: d102 bne.n 800638a <_sbrk_r+0x1a> + 8006384: 6823 ldr r3, [r4, #0] + 8006386: b103 cbz r3, 800638a <_sbrk_r+0x1a> + 8006388: 602b str r3, [r5, #0] + 800638a: bd38 pop {r3, r4, r5, pc} + 800638c: 20000ab0 .word 0x20000ab0 + +08006390 : + 8006390: ed9f 0a01 vldr s0, [pc, #4] ; 8006398 + 8006394: 4770 bx lr + 8006396: bf00 nop + 8006398: 7fc00000 .word 0x7fc00000 + +0800639c : + 800639c: b40e push {r1, r2, r3} + 800639e: b500 push {lr} + 80063a0: b09c sub sp, #112 ; 0x70 + 80063a2: ab1d add r3, sp, #116 ; 0x74 + 80063a4: 9002 str r0, [sp, #8] + 80063a6: 9006 str r0, [sp, #24] + 80063a8: f06f 4100 mvn.w r1, #2147483648 ; 0x80000000 + 80063ac: 4809 ldr r0, [pc, #36] ; (80063d4 ) + 80063ae: 9107 str r1, [sp, #28] + 80063b0: 9104 str r1, [sp, #16] + 80063b2: 4909 ldr r1, [pc, #36] ; (80063d8 ) + 80063b4: f853 2b04 ldr.w r2, [r3], #4 + 80063b8: 9105 str r1, [sp, #20] + 80063ba: 6800 ldr r0, [r0, #0] + 80063bc: 9301 str r3, [sp, #4] + 80063be: a902 add r1, sp, #8 + 80063c0: f002 ff60 bl 8009284 <_svfiprintf_r> + 80063c4: 9b02 ldr r3, [sp, #8] + 80063c6: 2200 movs r2, #0 + 80063c8: 701a strb r2, [r3, #0] + 80063ca: b01c add sp, #112 ; 0x70 + 80063cc: f85d eb04 ldr.w lr, [sp], #4 + 80063d0: b003 add sp, #12 + 80063d2: 4770 bx lr + 80063d4: 2000002c .word 0x2000002c + 80063d8: ffff0208 .word 0xffff0208 + +080063dc : + 80063dc: b570 push {r4, r5, r6, lr} + 80063de: 4604 mov r4, r0 + 80063e0: 460d mov r5, r1 + 80063e2: ec45 4b10 vmov d0, r4, r5 + 80063e6: 4616 mov r6, r2 + 80063e8: f002 fdb0 bl 8008f4c <__ulp> + 80063ec: ec51 0b10 vmov r0, r1, d0 + 80063f0: b17e cbz r6, 8006412 + 80063f2: f3c5 530a ubfx r3, r5, #20, #11 + 80063f6: f1c3 036b rsb r3, r3, #107 ; 0x6b + 80063fa: 2b00 cmp r3, #0 + 80063fc: dd09 ble.n 8006412 + 80063fe: 051b lsls r3, r3, #20 + 8006400: f103 557f add.w r5, r3, #1069547520 ; 0x3fc00000 + 8006404: 2400 movs r4, #0 + 8006406: f505 1540 add.w r5, r5, #3145728 ; 0x300000 + 800640a: 4622 mov r2, r4 + 800640c: 462b mov r3, r5 + 800640e: f7fa f8fb bl 8000608 <__aeabi_dmul> + 8006412: bd70 pop {r4, r5, r6, pc} + 8006414: 0000 movs r0, r0 + ... + +08006418 <_strtod_l>: + 8006418: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 800641c: 461f mov r7, r3 + 800641e: b0a1 sub sp, #132 ; 0x84 + 8006420: 2300 movs r3, #0 + 8006422: 4681 mov r9, r0 + 8006424: 4638 mov r0, r7 + 8006426: 460e mov r6, r1 + 8006428: 9217 str r2, [sp, #92] ; 0x5c + 800642a: 931c str r3, [sp, #112] ; 0x70 + 800642c: f002 fa2f bl 800888e <__localeconv_l> + 8006430: 4680 mov r8, r0 + 8006432: 6800 ldr r0, [r0, #0] + 8006434: f7f9 fed4 bl 80001e0 + 8006438: f04f 0a00 mov.w sl, #0 + 800643c: 4604 mov r4, r0 + 800643e: f04f 0b00 mov.w fp, #0 + 8006442: 961b str r6, [sp, #108] ; 0x6c + 8006444: 9b1b ldr r3, [sp, #108] ; 0x6c + 8006446: 781a ldrb r2, [r3, #0] + 8006448: 2a0d cmp r2, #13 + 800644a: d832 bhi.n 80064b2 <_strtod_l+0x9a> + 800644c: 2a09 cmp r2, #9 + 800644e: d236 bcs.n 80064be <_strtod_l+0xa6> + 8006450: 2a00 cmp r2, #0 + 8006452: d03e beq.n 80064d2 <_strtod_l+0xba> + 8006454: 2300 movs r3, #0 + 8006456: 930d str r3, [sp, #52] ; 0x34 + 8006458: 9d1b ldr r5, [sp, #108] ; 0x6c + 800645a: 782b ldrb r3, [r5, #0] + 800645c: 2b30 cmp r3, #48 ; 0x30 + 800645e: f040 80ac bne.w 80065ba <_strtod_l+0x1a2> + 8006462: 786b ldrb r3, [r5, #1] + 8006464: 2b58 cmp r3, #88 ; 0x58 + 8006466: d001 beq.n 800646c <_strtod_l+0x54> + 8006468: 2b78 cmp r3, #120 ; 0x78 + 800646a: d167 bne.n 800653c <_strtod_l+0x124> + 800646c: 9b0d ldr r3, [sp, #52] ; 0x34 + 800646e: 9301 str r3, [sp, #4] + 8006470: ab1c add r3, sp, #112 ; 0x70 + 8006472: 9300 str r3, [sp, #0] + 8006474: 9702 str r7, [sp, #8] + 8006476: ab1d add r3, sp, #116 ; 0x74 + 8006478: 4a88 ldr r2, [pc, #544] ; (800669c <_strtod_l+0x284>) + 800647a: a91b add r1, sp, #108 ; 0x6c + 800647c: 4648 mov r0, r9 + 800647e: f001 ff2c bl 80082da <__gethex> + 8006482: f010 0407 ands.w r4, r0, #7 + 8006486: 4606 mov r6, r0 + 8006488: d005 beq.n 8006496 <_strtod_l+0x7e> + 800648a: 2c06 cmp r4, #6 + 800648c: d12b bne.n 80064e6 <_strtod_l+0xce> + 800648e: 3501 adds r5, #1 + 8006490: 2300 movs r3, #0 + 8006492: 951b str r5, [sp, #108] ; 0x6c + 8006494: 930d str r3, [sp, #52] ; 0x34 + 8006496: 9b17 ldr r3, [sp, #92] ; 0x5c + 8006498: 2b00 cmp r3, #0 + 800649a: f040 859a bne.w 8006fd2 <_strtod_l+0xbba> + 800649e: 9b0d ldr r3, [sp, #52] ; 0x34 + 80064a0: b1e3 cbz r3, 80064dc <_strtod_l+0xc4> + 80064a2: 4652 mov r2, sl + 80064a4: f10b 4300 add.w r3, fp, #2147483648 ; 0x80000000 + 80064a8: ec43 2b10 vmov d0, r2, r3 + 80064ac: b021 add sp, #132 ; 0x84 + 80064ae: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 80064b2: 2a2b cmp r2, #43 ; 0x2b + 80064b4: d015 beq.n 80064e2 <_strtod_l+0xca> + 80064b6: 2a2d cmp r2, #45 ; 0x2d + 80064b8: d004 beq.n 80064c4 <_strtod_l+0xac> + 80064ba: 2a20 cmp r2, #32 + 80064bc: d1ca bne.n 8006454 <_strtod_l+0x3c> + 80064be: 3301 adds r3, #1 + 80064c0: 931b str r3, [sp, #108] ; 0x6c + 80064c2: e7bf b.n 8006444 <_strtod_l+0x2c> + 80064c4: 2201 movs r2, #1 + 80064c6: 920d str r2, [sp, #52] ; 0x34 + 80064c8: 1c5a adds r2, r3, #1 + 80064ca: 921b str r2, [sp, #108] ; 0x6c + 80064cc: 785b ldrb r3, [r3, #1] + 80064ce: 2b00 cmp r3, #0 + 80064d0: d1c2 bne.n 8006458 <_strtod_l+0x40> + 80064d2: 9b17 ldr r3, [sp, #92] ; 0x5c + 80064d4: 961b str r6, [sp, #108] ; 0x6c + 80064d6: 2b00 cmp r3, #0 + 80064d8: f040 8579 bne.w 8006fce <_strtod_l+0xbb6> + 80064dc: 4652 mov r2, sl + 80064de: 465b mov r3, fp + 80064e0: e7e2 b.n 80064a8 <_strtod_l+0x90> + 80064e2: 2200 movs r2, #0 + 80064e4: e7ef b.n 80064c6 <_strtod_l+0xae> + 80064e6: 9a1c ldr r2, [sp, #112] ; 0x70 + 80064e8: b13a cbz r2, 80064fa <_strtod_l+0xe2> + 80064ea: 2135 movs r1, #53 ; 0x35 + 80064ec: a81e add r0, sp, #120 ; 0x78 + 80064ee: f002 fe25 bl 800913c <__copybits> + 80064f2: 991c ldr r1, [sp, #112] ; 0x70 + 80064f4: 4648 mov r0, r9 + 80064f6: f002 fa92 bl 8008a1e <_Bfree> + 80064fa: 3c01 subs r4, #1 + 80064fc: 2c04 cmp r4, #4 + 80064fe: d806 bhi.n 800650e <_strtod_l+0xf6> + 8006500: e8df f004 tbb [pc, r4] + 8006504: 1714030a .word 0x1714030a + 8006508: 0a .byte 0x0a + 8006509: 00 .byte 0x00 + 800650a: e9dd ab1e ldrd sl, fp, [sp, #120] ; 0x78 + 800650e: 0730 lsls r0, r6, #28 + 8006510: d5c1 bpl.n 8006496 <_strtod_l+0x7e> + 8006512: f04b 4b00 orr.w fp, fp, #2147483648 ; 0x80000000 + 8006516: e7be b.n 8006496 <_strtod_l+0x7e> + 8006518: e9dd a31e ldrd sl, r3, [sp, #120] ; 0x78 + 800651c: 9a1d ldr r2, [sp, #116] ; 0x74 + 800651e: f423 1380 bic.w r3, r3, #1048576 ; 0x100000 + 8006522: f202 4233 addw r2, r2, #1075 ; 0x433 + 8006526: ea43 5b02 orr.w fp, r3, r2, lsl #20 + 800652a: e7f0 b.n 800650e <_strtod_l+0xf6> + 800652c: f8df b170 ldr.w fp, [pc, #368] ; 80066a0 <_strtod_l+0x288> + 8006530: e7ed b.n 800650e <_strtod_l+0xf6> + 8006532: f06f 4b00 mvn.w fp, #2147483648 ; 0x80000000 + 8006536: f04f 3aff mov.w sl, #4294967295 + 800653a: e7e8 b.n 800650e <_strtod_l+0xf6> + 800653c: 9b1b ldr r3, [sp, #108] ; 0x6c + 800653e: 1c5a adds r2, r3, #1 + 8006540: 921b str r2, [sp, #108] ; 0x6c + 8006542: 785b ldrb r3, [r3, #1] + 8006544: 2b30 cmp r3, #48 ; 0x30 + 8006546: d0f9 beq.n 800653c <_strtod_l+0x124> + 8006548: 2b00 cmp r3, #0 + 800654a: d0a4 beq.n 8006496 <_strtod_l+0x7e> + 800654c: 2301 movs r3, #1 + 800654e: 2500 movs r5, #0 + 8006550: 9306 str r3, [sp, #24] + 8006552: 9b1b ldr r3, [sp, #108] ; 0x6c + 8006554: 9308 str r3, [sp, #32] + 8006556: 9507 str r5, [sp, #28] + 8006558: 9505 str r5, [sp, #20] + 800655a: 220a movs r2, #10 + 800655c: 981b ldr r0, [sp, #108] ; 0x6c + 800655e: 7807 ldrb r7, [r0, #0] + 8006560: f1a7 0330 sub.w r3, r7, #48 ; 0x30 + 8006564: b2d9 uxtb r1, r3 + 8006566: 2909 cmp r1, #9 + 8006568: d929 bls.n 80065be <_strtod_l+0x1a6> + 800656a: 4622 mov r2, r4 + 800656c: f8d8 1000 ldr.w r1, [r8] + 8006570: f003 f903 bl 800977a + 8006574: 2800 cmp r0, #0 + 8006576: d031 beq.n 80065dc <_strtod_l+0x1c4> + 8006578: 2000 movs r0, #0 + 800657a: 9c05 ldr r4, [sp, #20] + 800657c: 9004 str r0, [sp, #16] + 800657e: 463b mov r3, r7 + 8006580: 4602 mov r2, r0 + 8006582: 2b65 cmp r3, #101 ; 0x65 + 8006584: d001 beq.n 800658a <_strtod_l+0x172> + 8006586: 2b45 cmp r3, #69 ; 0x45 + 8006588: d114 bne.n 80065b4 <_strtod_l+0x19c> + 800658a: b924 cbnz r4, 8006596 <_strtod_l+0x17e> + 800658c: b910 cbnz r0, 8006594 <_strtod_l+0x17c> + 800658e: 9b06 ldr r3, [sp, #24] + 8006590: 2b00 cmp r3, #0 + 8006592: d09e beq.n 80064d2 <_strtod_l+0xba> + 8006594: 2400 movs r4, #0 + 8006596: 9e1b ldr r6, [sp, #108] ; 0x6c + 8006598: 1c73 adds r3, r6, #1 + 800659a: 931b str r3, [sp, #108] ; 0x6c + 800659c: 7873 ldrb r3, [r6, #1] + 800659e: 2b2b cmp r3, #43 ; 0x2b + 80065a0: d078 beq.n 8006694 <_strtod_l+0x27c> + 80065a2: 2b2d cmp r3, #45 ; 0x2d + 80065a4: d070 beq.n 8006688 <_strtod_l+0x270> + 80065a6: f04f 0c00 mov.w ip, #0 + 80065aa: f1a3 0730 sub.w r7, r3, #48 ; 0x30 + 80065ae: 2f09 cmp r7, #9 + 80065b0: d97c bls.n 80066ac <_strtod_l+0x294> + 80065b2: 961b str r6, [sp, #108] ; 0x6c + 80065b4: f04f 0e00 mov.w lr, #0 + 80065b8: e09a b.n 80066f0 <_strtod_l+0x2d8> + 80065ba: 2300 movs r3, #0 + 80065bc: e7c7 b.n 800654e <_strtod_l+0x136> + 80065be: 9905 ldr r1, [sp, #20] + 80065c0: 2908 cmp r1, #8 + 80065c2: bfdd ittte le + 80065c4: 9907 ldrle r1, [sp, #28] + 80065c6: fb02 3301 mlale r3, r2, r1, r3 + 80065ca: 9307 strle r3, [sp, #28] + 80065cc: fb02 3505 mlagt r5, r2, r5, r3 + 80065d0: 9b05 ldr r3, [sp, #20] + 80065d2: 3001 adds r0, #1 + 80065d4: 3301 adds r3, #1 + 80065d6: 9305 str r3, [sp, #20] + 80065d8: 901b str r0, [sp, #108] ; 0x6c + 80065da: e7bf b.n 800655c <_strtod_l+0x144> + 80065dc: 9b1b ldr r3, [sp, #108] ; 0x6c + 80065de: 191a adds r2, r3, r4 + 80065e0: 921b str r2, [sp, #108] ; 0x6c + 80065e2: 9a05 ldr r2, [sp, #20] + 80065e4: 5d1b ldrb r3, [r3, r4] + 80065e6: 2a00 cmp r2, #0 + 80065e8: d037 beq.n 800665a <_strtod_l+0x242> + 80065ea: 9c05 ldr r4, [sp, #20] + 80065ec: 4602 mov r2, r0 + 80065ee: f1a3 0130 sub.w r1, r3, #48 ; 0x30 + 80065f2: 2909 cmp r1, #9 + 80065f4: d913 bls.n 800661e <_strtod_l+0x206> + 80065f6: 2101 movs r1, #1 + 80065f8: 9104 str r1, [sp, #16] + 80065fa: e7c2 b.n 8006582 <_strtod_l+0x16a> + 80065fc: 9b1b ldr r3, [sp, #108] ; 0x6c + 80065fe: 1c5a adds r2, r3, #1 + 8006600: 921b str r2, [sp, #108] ; 0x6c + 8006602: 785b ldrb r3, [r3, #1] + 8006604: 3001 adds r0, #1 + 8006606: 2b30 cmp r3, #48 ; 0x30 + 8006608: d0f8 beq.n 80065fc <_strtod_l+0x1e4> + 800660a: f1a3 0231 sub.w r2, r3, #49 ; 0x31 + 800660e: 2a08 cmp r2, #8 + 8006610: f200 84e4 bhi.w 8006fdc <_strtod_l+0xbc4> + 8006614: 9a1b ldr r2, [sp, #108] ; 0x6c + 8006616: 9208 str r2, [sp, #32] + 8006618: 4602 mov r2, r0 + 800661a: 2000 movs r0, #0 + 800661c: 4604 mov r4, r0 + 800661e: f1b3 0e30 subs.w lr, r3, #48 ; 0x30 + 8006622: f100 0101 add.w r1, r0, #1 + 8006626: d012 beq.n 800664e <_strtod_l+0x236> + 8006628: 440a add r2, r1 + 800662a: eb00 0c04 add.w ip, r0, r4 + 800662e: 4621 mov r1, r4 + 8006630: 270a movs r7, #10 + 8006632: 458c cmp ip, r1 + 8006634: d113 bne.n 800665e <_strtod_l+0x246> + 8006636: 1821 adds r1, r4, r0 + 8006638: 2908 cmp r1, #8 + 800663a: f104 0401 add.w r4, r4, #1 + 800663e: 4404 add r4, r0 + 8006640: dc19 bgt.n 8006676 <_strtod_l+0x25e> + 8006642: 9b07 ldr r3, [sp, #28] + 8006644: 210a movs r1, #10 + 8006646: fb01 e303 mla r3, r1, r3, lr + 800664a: 9307 str r3, [sp, #28] + 800664c: 2100 movs r1, #0 + 800664e: 9b1b ldr r3, [sp, #108] ; 0x6c + 8006650: 1c58 adds r0, r3, #1 + 8006652: 901b str r0, [sp, #108] ; 0x6c + 8006654: 785b ldrb r3, [r3, #1] + 8006656: 4608 mov r0, r1 + 8006658: e7c9 b.n 80065ee <_strtod_l+0x1d6> + 800665a: 9805 ldr r0, [sp, #20] + 800665c: e7d3 b.n 8006606 <_strtod_l+0x1ee> + 800665e: 2908 cmp r1, #8 + 8006660: f101 0101 add.w r1, r1, #1 + 8006664: dc03 bgt.n 800666e <_strtod_l+0x256> + 8006666: 9b07 ldr r3, [sp, #28] + 8006668: 437b muls r3, r7 + 800666a: 9307 str r3, [sp, #28] + 800666c: e7e1 b.n 8006632 <_strtod_l+0x21a> + 800666e: 2910 cmp r1, #16 + 8006670: bfd8 it le + 8006672: 437d mulle r5, r7 + 8006674: e7dd b.n 8006632 <_strtod_l+0x21a> + 8006676: 2c10 cmp r4, #16 + 8006678: bfdc itt le + 800667a: 210a movle r1, #10 + 800667c: fb01 e505 mlale r5, r1, r5, lr + 8006680: e7e4 b.n 800664c <_strtod_l+0x234> + 8006682: 2301 movs r3, #1 + 8006684: 9304 str r3, [sp, #16] + 8006686: e781 b.n 800658c <_strtod_l+0x174> + 8006688: f04f 0c01 mov.w ip, #1 + 800668c: 1cb3 adds r3, r6, #2 + 800668e: 931b str r3, [sp, #108] ; 0x6c + 8006690: 78b3 ldrb r3, [r6, #2] + 8006692: e78a b.n 80065aa <_strtod_l+0x192> + 8006694: f04f 0c00 mov.w ip, #0 + 8006698: e7f8 b.n 800668c <_strtod_l+0x274> + 800669a: bf00 nop + 800669c: 08009a78 .word 0x08009a78 + 80066a0: 7ff00000 .word 0x7ff00000 + 80066a4: 9b1b ldr r3, [sp, #108] ; 0x6c + 80066a6: 1c5f adds r7, r3, #1 + 80066a8: 971b str r7, [sp, #108] ; 0x6c + 80066aa: 785b ldrb r3, [r3, #1] + 80066ac: 2b30 cmp r3, #48 ; 0x30 + 80066ae: d0f9 beq.n 80066a4 <_strtod_l+0x28c> + 80066b0: f1a3 0731 sub.w r7, r3, #49 ; 0x31 + 80066b4: 2f08 cmp r7, #8 + 80066b6: f63f af7d bhi.w 80065b4 <_strtod_l+0x19c> + 80066ba: f1a3 0e30 sub.w lr, r3, #48 ; 0x30 + 80066be: 9b1b ldr r3, [sp, #108] ; 0x6c + 80066c0: 930a str r3, [sp, #40] ; 0x28 + 80066c2: 9b1b ldr r3, [sp, #108] ; 0x6c + 80066c4: 1c5f adds r7, r3, #1 + 80066c6: 971b str r7, [sp, #108] ; 0x6c + 80066c8: 785b ldrb r3, [r3, #1] + 80066ca: f1a3 0830 sub.w r8, r3, #48 ; 0x30 + 80066ce: f1b8 0f09 cmp.w r8, #9 + 80066d2: d937 bls.n 8006744 <_strtod_l+0x32c> + 80066d4: 990a ldr r1, [sp, #40] ; 0x28 + 80066d6: 1a7f subs r7, r7, r1 + 80066d8: 2f08 cmp r7, #8 + 80066da: f644 671f movw r7, #19999 ; 0x4e1f + 80066de: dc37 bgt.n 8006750 <_strtod_l+0x338> + 80066e0: 45be cmp lr, r7 + 80066e2: bfa8 it ge + 80066e4: 46be movge lr, r7 + 80066e6: f1bc 0f00 cmp.w ip, #0 + 80066ea: d001 beq.n 80066f0 <_strtod_l+0x2d8> + 80066ec: f1ce 0e00 rsb lr, lr, #0 + 80066f0: 2c00 cmp r4, #0 + 80066f2: d151 bne.n 8006798 <_strtod_l+0x380> + 80066f4: 2800 cmp r0, #0 + 80066f6: f47f aece bne.w 8006496 <_strtod_l+0x7e> + 80066fa: 9a06 ldr r2, [sp, #24] + 80066fc: 2a00 cmp r2, #0 + 80066fe: f47f aeca bne.w 8006496 <_strtod_l+0x7e> + 8006702: 9a04 ldr r2, [sp, #16] + 8006704: 2a00 cmp r2, #0 + 8006706: f47f aee4 bne.w 80064d2 <_strtod_l+0xba> + 800670a: 2b4e cmp r3, #78 ; 0x4e + 800670c: d027 beq.n 800675e <_strtod_l+0x346> + 800670e: dc21 bgt.n 8006754 <_strtod_l+0x33c> + 8006710: 2b49 cmp r3, #73 ; 0x49 + 8006712: f47f aede bne.w 80064d2 <_strtod_l+0xba> + 8006716: 49a0 ldr r1, [pc, #640] ; (8006998 <_strtod_l+0x580>) + 8006718: a81b add r0, sp, #108 ; 0x6c + 800671a: f002 f811 bl 8008740 <__match> + 800671e: 2800 cmp r0, #0 + 8006720: f43f aed7 beq.w 80064d2 <_strtod_l+0xba> + 8006724: 9b1b ldr r3, [sp, #108] ; 0x6c + 8006726: 499d ldr r1, [pc, #628] ; (800699c <_strtod_l+0x584>) + 8006728: 3b01 subs r3, #1 + 800672a: a81b add r0, sp, #108 ; 0x6c + 800672c: 931b str r3, [sp, #108] ; 0x6c + 800672e: f002 f807 bl 8008740 <__match> + 8006732: b910 cbnz r0, 800673a <_strtod_l+0x322> + 8006734: 9b1b ldr r3, [sp, #108] ; 0x6c + 8006736: 3301 adds r3, #1 + 8006738: 931b str r3, [sp, #108] ; 0x6c + 800673a: f8df b274 ldr.w fp, [pc, #628] ; 80069b0 <_strtod_l+0x598> + 800673e: f04f 0a00 mov.w sl, #0 + 8006742: e6a8 b.n 8006496 <_strtod_l+0x7e> + 8006744: 210a movs r1, #10 + 8006746: fb01 3e0e mla lr, r1, lr, r3 + 800674a: f1ae 0e30 sub.w lr, lr, #48 ; 0x30 + 800674e: e7b8 b.n 80066c2 <_strtod_l+0x2aa> + 8006750: 46be mov lr, r7 + 8006752: e7c8 b.n 80066e6 <_strtod_l+0x2ce> + 8006754: 2b69 cmp r3, #105 ; 0x69 + 8006756: d0de beq.n 8006716 <_strtod_l+0x2fe> + 8006758: 2b6e cmp r3, #110 ; 0x6e + 800675a: f47f aeba bne.w 80064d2 <_strtod_l+0xba> + 800675e: 4990 ldr r1, [pc, #576] ; (80069a0 <_strtod_l+0x588>) + 8006760: a81b add r0, sp, #108 ; 0x6c + 8006762: f001 ffed bl 8008740 <__match> + 8006766: 2800 cmp r0, #0 + 8006768: f43f aeb3 beq.w 80064d2 <_strtod_l+0xba> + 800676c: 9b1b ldr r3, [sp, #108] ; 0x6c + 800676e: 781b ldrb r3, [r3, #0] + 8006770: 2b28 cmp r3, #40 ; 0x28 + 8006772: d10e bne.n 8006792 <_strtod_l+0x37a> + 8006774: aa1e add r2, sp, #120 ; 0x78 + 8006776: 498b ldr r1, [pc, #556] ; (80069a4 <_strtod_l+0x58c>) + 8006778: a81b add r0, sp, #108 ; 0x6c + 800677a: f001 fff5 bl 8008768 <__hexnan> + 800677e: 2805 cmp r0, #5 + 8006780: d107 bne.n 8006792 <_strtod_l+0x37a> + 8006782: 9b1f ldr r3, [sp, #124] ; 0x7c + 8006784: f8dd a078 ldr.w sl, [sp, #120] ; 0x78 + 8006788: f043 4bff orr.w fp, r3, #2139095040 ; 0x7f800000 + 800678c: f44b 0be0 orr.w fp, fp, #7340032 ; 0x700000 + 8006790: e681 b.n 8006496 <_strtod_l+0x7e> + 8006792: f8df b224 ldr.w fp, [pc, #548] ; 80069b8 <_strtod_l+0x5a0> + 8006796: e7d2 b.n 800673e <_strtod_l+0x326> + 8006798: ebae 0302 sub.w r3, lr, r2 + 800679c: 9306 str r3, [sp, #24] + 800679e: 9b05 ldr r3, [sp, #20] + 80067a0: 9807 ldr r0, [sp, #28] + 80067a2: 2b00 cmp r3, #0 + 80067a4: bf08 it eq + 80067a6: 4623 moveq r3, r4 + 80067a8: 2c10 cmp r4, #16 + 80067aa: 9305 str r3, [sp, #20] + 80067ac: 46a0 mov r8, r4 + 80067ae: bfa8 it ge + 80067b0: f04f 0810 movge.w r8, #16 + 80067b4: f7f9 feae bl 8000514 <__aeabi_ui2d> + 80067b8: 2c09 cmp r4, #9 + 80067ba: 4682 mov sl, r0 + 80067bc: 468b mov fp, r1 + 80067be: dc13 bgt.n 80067e8 <_strtod_l+0x3d0> + 80067c0: 9b06 ldr r3, [sp, #24] + 80067c2: 2b00 cmp r3, #0 + 80067c4: f43f ae67 beq.w 8006496 <_strtod_l+0x7e> + 80067c8: 9b06 ldr r3, [sp, #24] + 80067ca: dd7a ble.n 80068c2 <_strtod_l+0x4aa> + 80067cc: 2b16 cmp r3, #22 + 80067ce: dc61 bgt.n 8006894 <_strtod_l+0x47c> + 80067d0: 4a75 ldr r2, [pc, #468] ; (80069a8 <_strtod_l+0x590>) + 80067d2: eb02 0ec3 add.w lr, r2, r3, lsl #3 + 80067d6: e9de 0100 ldrd r0, r1, [lr] + 80067da: 4652 mov r2, sl + 80067dc: 465b mov r3, fp + 80067de: f7f9 ff13 bl 8000608 <__aeabi_dmul> + 80067e2: 4682 mov sl, r0 + 80067e4: 468b mov fp, r1 + 80067e6: e656 b.n 8006496 <_strtod_l+0x7e> + 80067e8: 4b6f ldr r3, [pc, #444] ; (80069a8 <_strtod_l+0x590>) + 80067ea: eb03 03c8 add.w r3, r3, r8, lsl #3 + 80067ee: e953 2312 ldrd r2, r3, [r3, #-72] ; 0x48 + 80067f2: f7f9 ff09 bl 8000608 <__aeabi_dmul> + 80067f6: 4606 mov r6, r0 + 80067f8: 4628 mov r0, r5 + 80067fa: 460f mov r7, r1 + 80067fc: f7f9 fe8a bl 8000514 <__aeabi_ui2d> + 8006800: 4602 mov r2, r0 + 8006802: 460b mov r3, r1 + 8006804: 4630 mov r0, r6 + 8006806: 4639 mov r1, r7 + 8006808: f7f9 fd48 bl 800029c <__adddf3> + 800680c: 2c0f cmp r4, #15 + 800680e: 4682 mov sl, r0 + 8006810: 468b mov fp, r1 + 8006812: ddd5 ble.n 80067c0 <_strtod_l+0x3a8> + 8006814: 9b06 ldr r3, [sp, #24] + 8006816: eba4 0808 sub.w r8, r4, r8 + 800681a: 4498 add r8, r3 + 800681c: f1b8 0f00 cmp.w r8, #0 + 8006820: f340 8096 ble.w 8006950 <_strtod_l+0x538> + 8006824: f018 030f ands.w r3, r8, #15 + 8006828: d00a beq.n 8006840 <_strtod_l+0x428> + 800682a: 495f ldr r1, [pc, #380] ; (80069a8 <_strtod_l+0x590>) + 800682c: eb01 01c3 add.w r1, r1, r3, lsl #3 + 8006830: 4652 mov r2, sl + 8006832: 465b mov r3, fp + 8006834: e9d1 0100 ldrd r0, r1, [r1] + 8006838: f7f9 fee6 bl 8000608 <__aeabi_dmul> + 800683c: 4682 mov sl, r0 + 800683e: 468b mov fp, r1 + 8006840: f038 080f bics.w r8, r8, #15 + 8006844: d073 beq.n 800692e <_strtod_l+0x516> + 8006846: f5b8 7f9a cmp.w r8, #308 ; 0x134 + 800684a: dd47 ble.n 80068dc <_strtod_l+0x4c4> + 800684c: 2400 movs r4, #0 + 800684e: 46a0 mov r8, r4 + 8006850: 9407 str r4, [sp, #28] + 8006852: 9405 str r4, [sp, #20] + 8006854: 2322 movs r3, #34 ; 0x22 + 8006856: f8df b158 ldr.w fp, [pc, #344] ; 80069b0 <_strtod_l+0x598> + 800685a: f8c9 3000 str.w r3, [r9] + 800685e: f04f 0a00 mov.w sl, #0 + 8006862: 9b07 ldr r3, [sp, #28] + 8006864: 2b00 cmp r3, #0 + 8006866: f43f ae16 beq.w 8006496 <_strtod_l+0x7e> + 800686a: 991c ldr r1, [sp, #112] ; 0x70 + 800686c: 4648 mov r0, r9 + 800686e: f002 f8d6 bl 8008a1e <_Bfree> + 8006872: 9905 ldr r1, [sp, #20] + 8006874: 4648 mov r0, r9 + 8006876: f002 f8d2 bl 8008a1e <_Bfree> + 800687a: 4641 mov r1, r8 + 800687c: 4648 mov r0, r9 + 800687e: f002 f8ce bl 8008a1e <_Bfree> + 8006882: 9907 ldr r1, [sp, #28] + 8006884: 4648 mov r0, r9 + 8006886: f002 f8ca bl 8008a1e <_Bfree> + 800688a: 4621 mov r1, r4 + 800688c: 4648 mov r0, r9 + 800688e: f002 f8c6 bl 8008a1e <_Bfree> + 8006892: e600 b.n 8006496 <_strtod_l+0x7e> + 8006894: 9a06 ldr r2, [sp, #24] + 8006896: f1c4 0325 rsb r3, r4, #37 ; 0x25 + 800689a: 4293 cmp r3, r2 + 800689c: dbba blt.n 8006814 <_strtod_l+0x3fc> + 800689e: 4d42 ldr r5, [pc, #264] ; (80069a8 <_strtod_l+0x590>) + 80068a0: f1c4 040f rsb r4, r4, #15 + 80068a4: eb05 01c4 add.w r1, r5, r4, lsl #3 + 80068a8: 4652 mov r2, sl + 80068aa: 465b mov r3, fp + 80068ac: e9d1 0100 ldrd r0, r1, [r1] + 80068b0: f7f9 feaa bl 8000608 <__aeabi_dmul> + 80068b4: 9b06 ldr r3, [sp, #24] + 80068b6: 1b1c subs r4, r3, r4 + 80068b8: eb05 05c4 add.w r5, r5, r4, lsl #3 + 80068bc: e9d5 2300 ldrd r2, r3, [r5] + 80068c0: e78d b.n 80067de <_strtod_l+0x3c6> + 80068c2: f113 0f16 cmn.w r3, #22 + 80068c6: dba5 blt.n 8006814 <_strtod_l+0x3fc> + 80068c8: 4a37 ldr r2, [pc, #220] ; (80069a8 <_strtod_l+0x590>) + 80068ca: eba2 02c3 sub.w r2, r2, r3, lsl #3 + 80068ce: e9d2 2300 ldrd r2, r3, [r2] + 80068d2: 4650 mov r0, sl + 80068d4: 4659 mov r1, fp + 80068d6: f7f9 ffc1 bl 800085c <__aeabi_ddiv> + 80068da: e782 b.n 80067e2 <_strtod_l+0x3ca> + 80068dc: 2300 movs r3, #0 + 80068de: 4e33 ldr r6, [pc, #204] ; (80069ac <_strtod_l+0x594>) + 80068e0: ea4f 1828 mov.w r8, r8, asr #4 + 80068e4: 4650 mov r0, sl + 80068e6: 4659 mov r1, fp + 80068e8: 461d mov r5, r3 + 80068ea: f1b8 0f01 cmp.w r8, #1 + 80068ee: dc21 bgt.n 8006934 <_strtod_l+0x51c> + 80068f0: b10b cbz r3, 80068f6 <_strtod_l+0x4de> + 80068f2: 4682 mov sl, r0 + 80068f4: 468b mov fp, r1 + 80068f6: 4b2d ldr r3, [pc, #180] ; (80069ac <_strtod_l+0x594>) + 80068f8: f1ab 7b54 sub.w fp, fp, #55574528 ; 0x3500000 + 80068fc: eb03 05c5 add.w r5, r3, r5, lsl #3 + 8006900: 4652 mov r2, sl + 8006902: 465b mov r3, fp + 8006904: e9d5 0100 ldrd r0, r1, [r5] + 8006908: f7f9 fe7e bl 8000608 <__aeabi_dmul> + 800690c: 4b28 ldr r3, [pc, #160] ; (80069b0 <_strtod_l+0x598>) + 800690e: 460a mov r2, r1 + 8006910: 400b ands r3, r1 + 8006912: 4928 ldr r1, [pc, #160] ; (80069b4 <_strtod_l+0x59c>) + 8006914: 428b cmp r3, r1 + 8006916: 4682 mov sl, r0 + 8006918: d898 bhi.n 800684c <_strtod_l+0x434> + 800691a: f5a1 1180 sub.w r1, r1, #1048576 ; 0x100000 + 800691e: 428b cmp r3, r1 + 8006920: bf86 itte hi + 8006922: f8df b098 ldrhi.w fp, [pc, #152] ; 80069bc <_strtod_l+0x5a4> + 8006926: f04f 3aff movhi.w sl, #4294967295 + 800692a: f102 7b54 addls.w fp, r2, #55574528 ; 0x3500000 + 800692e: 2300 movs r3, #0 + 8006930: 9304 str r3, [sp, #16] + 8006932: e077 b.n 8006a24 <_strtod_l+0x60c> + 8006934: f018 0f01 tst.w r8, #1 + 8006938: d006 beq.n 8006948 <_strtod_l+0x530> + 800693a: eb06 03c5 add.w r3, r6, r5, lsl #3 + 800693e: e9d3 2300 ldrd r2, r3, [r3] + 8006942: f7f9 fe61 bl 8000608 <__aeabi_dmul> + 8006946: 2301 movs r3, #1 + 8006948: 3501 adds r5, #1 + 800694a: ea4f 0868 mov.w r8, r8, asr #1 + 800694e: e7cc b.n 80068ea <_strtod_l+0x4d2> + 8006950: d0ed beq.n 800692e <_strtod_l+0x516> + 8006952: f1c8 0800 rsb r8, r8, #0 + 8006956: f018 020f ands.w r2, r8, #15 + 800695a: d00a beq.n 8006972 <_strtod_l+0x55a> + 800695c: 4b12 ldr r3, [pc, #72] ; (80069a8 <_strtod_l+0x590>) + 800695e: eb03 03c2 add.w r3, r3, r2, lsl #3 + 8006962: 4650 mov r0, sl + 8006964: 4659 mov r1, fp + 8006966: e9d3 2300 ldrd r2, r3, [r3] + 800696a: f7f9 ff77 bl 800085c <__aeabi_ddiv> + 800696e: 4682 mov sl, r0 + 8006970: 468b mov fp, r1 + 8006972: ea5f 1828 movs.w r8, r8, asr #4 + 8006976: d0da beq.n 800692e <_strtod_l+0x516> + 8006978: f1b8 0f1f cmp.w r8, #31 + 800697c: dd20 ble.n 80069c0 <_strtod_l+0x5a8> + 800697e: 2400 movs r4, #0 + 8006980: 46a0 mov r8, r4 + 8006982: 9407 str r4, [sp, #28] + 8006984: 9405 str r4, [sp, #20] + 8006986: 2322 movs r3, #34 ; 0x22 + 8006988: f04f 0a00 mov.w sl, #0 + 800698c: f04f 0b00 mov.w fp, #0 + 8006990: f8c9 3000 str.w r3, [r9] + 8006994: e765 b.n 8006862 <_strtod_l+0x44a> + 8006996: bf00 nop + 8006998: 08009a41 .word 0x08009a41 + 800699c: 08009acb .word 0x08009acb + 80069a0: 08009a49 .word 0x08009a49 + 80069a4: 08009a8c .word 0x08009a8c + 80069a8: 08009b68 .word 0x08009b68 + 80069ac: 08009b40 .word 0x08009b40 + 80069b0: 7ff00000 .word 0x7ff00000 + 80069b4: 7ca00000 .word 0x7ca00000 + 80069b8: fff80000 .word 0xfff80000 + 80069bc: 7fefffff .word 0x7fefffff + 80069c0: f018 0310 ands.w r3, r8, #16 + 80069c4: bf18 it ne + 80069c6: 236a movne r3, #106 ; 0x6a + 80069c8: 4da0 ldr r5, [pc, #640] ; (8006c4c <_strtod_l+0x834>) + 80069ca: 9304 str r3, [sp, #16] + 80069cc: 4650 mov r0, sl + 80069ce: 4659 mov r1, fp + 80069d0: 2300 movs r3, #0 + 80069d2: f1b8 0f00 cmp.w r8, #0 + 80069d6: f300 810a bgt.w 8006bee <_strtod_l+0x7d6> + 80069da: b10b cbz r3, 80069e0 <_strtod_l+0x5c8> + 80069dc: 4682 mov sl, r0 + 80069de: 468b mov fp, r1 + 80069e0: 9b04 ldr r3, [sp, #16] + 80069e2: b1bb cbz r3, 8006a14 <_strtod_l+0x5fc> + 80069e4: f3cb 530a ubfx r3, fp, #20, #11 + 80069e8: f1c3 036b rsb r3, r3, #107 ; 0x6b + 80069ec: 2b00 cmp r3, #0 + 80069ee: 4659 mov r1, fp + 80069f0: dd10 ble.n 8006a14 <_strtod_l+0x5fc> + 80069f2: 2b1f cmp r3, #31 + 80069f4: f340 8107 ble.w 8006c06 <_strtod_l+0x7ee> + 80069f8: 2b34 cmp r3, #52 ; 0x34 + 80069fa: bfde ittt le + 80069fc: 3b20 suble r3, #32 + 80069fe: f04f 32ff movle.w r2, #4294967295 + 8006a02: fa02 f303 lslle.w r3, r2, r3 + 8006a06: f04f 0a00 mov.w sl, #0 + 8006a0a: bfcc ite gt + 8006a0c: f04f 7b5c movgt.w fp, #57671680 ; 0x3700000 + 8006a10: ea03 0b01 andle.w fp, r3, r1 + 8006a14: 2200 movs r2, #0 + 8006a16: 2300 movs r3, #0 + 8006a18: 4650 mov r0, sl + 8006a1a: 4659 mov r1, fp + 8006a1c: f7fa f85c bl 8000ad8 <__aeabi_dcmpeq> + 8006a20: 2800 cmp r0, #0 + 8006a22: d1ac bne.n 800697e <_strtod_l+0x566> + 8006a24: 9b07 ldr r3, [sp, #28] + 8006a26: 9300 str r3, [sp, #0] + 8006a28: 9a05 ldr r2, [sp, #20] + 8006a2a: 9908 ldr r1, [sp, #32] + 8006a2c: 4623 mov r3, r4 + 8006a2e: 4648 mov r0, r9 + 8006a30: f002 f847 bl 8008ac2 <__s2b> + 8006a34: 9007 str r0, [sp, #28] + 8006a36: 2800 cmp r0, #0 + 8006a38: f43f af08 beq.w 800684c <_strtod_l+0x434> + 8006a3c: 9a06 ldr r2, [sp, #24] + 8006a3e: 9b06 ldr r3, [sp, #24] + 8006a40: 2a00 cmp r2, #0 + 8006a42: f1c3 0300 rsb r3, r3, #0 + 8006a46: bfa8 it ge + 8006a48: 2300 movge r3, #0 + 8006a4a: 930e str r3, [sp, #56] ; 0x38 + 8006a4c: 2400 movs r4, #0 + 8006a4e: ea22 73e2 bic.w r3, r2, r2, asr #31 + 8006a52: 9316 str r3, [sp, #88] ; 0x58 + 8006a54: 46a0 mov r8, r4 + 8006a56: 9b07 ldr r3, [sp, #28] + 8006a58: 4648 mov r0, r9 + 8006a5a: 6859 ldr r1, [r3, #4] + 8006a5c: f001 ffab bl 80089b6 <_Balloc> + 8006a60: 9005 str r0, [sp, #20] + 8006a62: 2800 cmp r0, #0 + 8006a64: f43f aef6 beq.w 8006854 <_strtod_l+0x43c> + 8006a68: 9b07 ldr r3, [sp, #28] + 8006a6a: 691a ldr r2, [r3, #16] + 8006a6c: 3202 adds r2, #2 + 8006a6e: f103 010c add.w r1, r3, #12 + 8006a72: 0092 lsls r2, r2, #2 + 8006a74: 300c adds r0, #12 + 8006a76: f001 ff91 bl 800899c + 8006a7a: aa1e add r2, sp, #120 ; 0x78 + 8006a7c: a91d add r1, sp, #116 ; 0x74 + 8006a7e: ec4b ab10 vmov d0, sl, fp + 8006a82: 4648 mov r0, r9 + 8006a84: e9cd ab08 strd sl, fp, [sp, #32] + 8006a88: f002 fad6 bl 8009038 <__d2b> + 8006a8c: 901c str r0, [sp, #112] ; 0x70 + 8006a8e: 2800 cmp r0, #0 + 8006a90: f43f aee0 beq.w 8006854 <_strtod_l+0x43c> + 8006a94: 2101 movs r1, #1 + 8006a96: 4648 mov r0, r9 + 8006a98: f002 f89f bl 8008bda <__i2b> + 8006a9c: 4680 mov r8, r0 + 8006a9e: 2800 cmp r0, #0 + 8006aa0: f43f aed8 beq.w 8006854 <_strtod_l+0x43c> + 8006aa4: 9e1d ldr r6, [sp, #116] ; 0x74 + 8006aa6: 9a1e ldr r2, [sp, #120] ; 0x78 + 8006aa8: 2e00 cmp r6, #0 + 8006aaa: bfab itete ge + 8006aac: 9b0e ldrge r3, [sp, #56] ; 0x38 + 8006aae: 9b16 ldrlt r3, [sp, #88] ; 0x58 + 8006ab0: 9d16 ldrge r5, [sp, #88] ; 0x58 + 8006ab2: 9f0e ldrlt r7, [sp, #56] ; 0x38 + 8006ab4: bfac ite ge + 8006ab6: 18f7 addge r7, r6, r3 + 8006ab8: 1b9d sublt r5, r3, r6 + 8006aba: 9b04 ldr r3, [sp, #16] + 8006abc: 1af6 subs r6, r6, r3 + 8006abe: 4416 add r6, r2 + 8006ac0: 4b63 ldr r3, [pc, #396] ; (8006c50 <_strtod_l+0x838>) + 8006ac2: 3e01 subs r6, #1 + 8006ac4: 429e cmp r6, r3 + 8006ac6: f1c2 0236 rsb r2, r2, #54 ; 0x36 + 8006aca: f280 80af bge.w 8006c2c <_strtod_l+0x814> + 8006ace: 1b9b subs r3, r3, r6 + 8006ad0: 2b1f cmp r3, #31 + 8006ad2: eba2 0203 sub.w r2, r2, r3 + 8006ad6: f04f 0101 mov.w r1, #1 + 8006ada: f300 809b bgt.w 8006c14 <_strtod_l+0x7fc> + 8006ade: fa01 f303 lsl.w r3, r1, r3 + 8006ae2: 930f str r3, [sp, #60] ; 0x3c + 8006ae4: 2300 movs r3, #0 + 8006ae6: 930a str r3, [sp, #40] ; 0x28 + 8006ae8: 18be adds r6, r7, r2 + 8006aea: 9b04 ldr r3, [sp, #16] + 8006aec: 42b7 cmp r7, r6 + 8006aee: 4415 add r5, r2 + 8006af0: 441d add r5, r3 + 8006af2: 463b mov r3, r7 + 8006af4: bfa8 it ge + 8006af6: 4633 movge r3, r6 + 8006af8: 42ab cmp r3, r5 + 8006afa: bfa8 it ge + 8006afc: 462b movge r3, r5 + 8006afe: 2b00 cmp r3, #0 + 8006b00: bfc2 ittt gt + 8006b02: 1af6 subgt r6, r6, r3 + 8006b04: 1aed subgt r5, r5, r3 + 8006b06: 1aff subgt r7, r7, r3 + 8006b08: 9b0e ldr r3, [sp, #56] ; 0x38 + 8006b0a: b1bb cbz r3, 8006b3c <_strtod_l+0x724> + 8006b0c: 4641 mov r1, r8 + 8006b0e: 461a mov r2, r3 + 8006b10: 4648 mov r0, r9 + 8006b12: f002 f901 bl 8008d18 <__pow5mult> + 8006b16: 4680 mov r8, r0 + 8006b18: 2800 cmp r0, #0 + 8006b1a: f43f ae9b beq.w 8006854 <_strtod_l+0x43c> + 8006b1e: 4601 mov r1, r0 + 8006b20: 9a1c ldr r2, [sp, #112] ; 0x70 + 8006b22: 4648 mov r0, r9 + 8006b24: f002 f862 bl 8008bec <__multiply> + 8006b28: 900c str r0, [sp, #48] ; 0x30 + 8006b2a: 2800 cmp r0, #0 + 8006b2c: f43f ae92 beq.w 8006854 <_strtod_l+0x43c> + 8006b30: 991c ldr r1, [sp, #112] ; 0x70 + 8006b32: 4648 mov r0, r9 + 8006b34: f001 ff73 bl 8008a1e <_Bfree> + 8006b38: 9b0c ldr r3, [sp, #48] ; 0x30 + 8006b3a: 931c str r3, [sp, #112] ; 0x70 + 8006b3c: 2e00 cmp r6, #0 + 8006b3e: dc7a bgt.n 8006c36 <_strtod_l+0x81e> + 8006b40: 9b06 ldr r3, [sp, #24] + 8006b42: 2b00 cmp r3, #0 + 8006b44: dd08 ble.n 8006b58 <_strtod_l+0x740> + 8006b46: 9a16 ldr r2, [sp, #88] ; 0x58 + 8006b48: 9905 ldr r1, [sp, #20] + 8006b4a: 4648 mov r0, r9 + 8006b4c: f002 f8e4 bl 8008d18 <__pow5mult> + 8006b50: 9005 str r0, [sp, #20] + 8006b52: 2800 cmp r0, #0 + 8006b54: f43f ae7e beq.w 8006854 <_strtod_l+0x43c> + 8006b58: 2d00 cmp r5, #0 + 8006b5a: dd08 ble.n 8006b6e <_strtod_l+0x756> + 8006b5c: 462a mov r2, r5 + 8006b5e: 9905 ldr r1, [sp, #20] + 8006b60: 4648 mov r0, r9 + 8006b62: f002 f927 bl 8008db4 <__lshift> + 8006b66: 9005 str r0, [sp, #20] + 8006b68: 2800 cmp r0, #0 + 8006b6a: f43f ae73 beq.w 8006854 <_strtod_l+0x43c> + 8006b6e: 2f00 cmp r7, #0 + 8006b70: dd08 ble.n 8006b84 <_strtod_l+0x76c> + 8006b72: 4641 mov r1, r8 + 8006b74: 463a mov r2, r7 + 8006b76: 4648 mov r0, r9 + 8006b78: f002 f91c bl 8008db4 <__lshift> + 8006b7c: 4680 mov r8, r0 + 8006b7e: 2800 cmp r0, #0 + 8006b80: f43f ae68 beq.w 8006854 <_strtod_l+0x43c> + 8006b84: 9a05 ldr r2, [sp, #20] + 8006b86: 991c ldr r1, [sp, #112] ; 0x70 + 8006b88: 4648 mov r0, r9 + 8006b8a: f002 f981 bl 8008e90 <__mdiff> + 8006b8e: 4604 mov r4, r0 + 8006b90: 2800 cmp r0, #0 + 8006b92: f43f ae5f beq.w 8006854 <_strtod_l+0x43c> + 8006b96: 68c3 ldr r3, [r0, #12] + 8006b98: 930c str r3, [sp, #48] ; 0x30 + 8006b9a: 2300 movs r3, #0 + 8006b9c: 60c3 str r3, [r0, #12] + 8006b9e: 4641 mov r1, r8 + 8006ba0: f002 f95c bl 8008e5c <__mcmp> + 8006ba4: 2800 cmp r0, #0 + 8006ba6: da55 bge.n 8006c54 <_strtod_l+0x83c> + 8006ba8: 9b0c ldr r3, [sp, #48] ; 0x30 + 8006baa: b9e3 cbnz r3, 8006be6 <_strtod_l+0x7ce> + 8006bac: f1ba 0f00 cmp.w sl, #0 + 8006bb0: d119 bne.n 8006be6 <_strtod_l+0x7ce> + 8006bb2: f3cb 0313 ubfx r3, fp, #0, #20 + 8006bb6: b9b3 cbnz r3, 8006be6 <_strtod_l+0x7ce> + 8006bb8: f02b 4300 bic.w r3, fp, #2147483648 ; 0x80000000 + 8006bbc: 0d1b lsrs r3, r3, #20 + 8006bbe: 051b lsls r3, r3, #20 + 8006bc0: f1b3 6fd6 cmp.w r3, #112197632 ; 0x6b00000 + 8006bc4: d90f bls.n 8006be6 <_strtod_l+0x7ce> + 8006bc6: 6963 ldr r3, [r4, #20] + 8006bc8: b913 cbnz r3, 8006bd0 <_strtod_l+0x7b8> + 8006bca: 6923 ldr r3, [r4, #16] + 8006bcc: 2b01 cmp r3, #1 + 8006bce: dd0a ble.n 8006be6 <_strtod_l+0x7ce> + 8006bd0: 4621 mov r1, r4 + 8006bd2: 2201 movs r2, #1 + 8006bd4: 4648 mov r0, r9 + 8006bd6: f002 f8ed bl 8008db4 <__lshift> + 8006bda: 4641 mov r1, r8 + 8006bdc: 4604 mov r4, r0 + 8006bde: f002 f93d bl 8008e5c <__mcmp> + 8006be2: 2800 cmp r0, #0 + 8006be4: dc67 bgt.n 8006cb6 <_strtod_l+0x89e> + 8006be6: 9b04 ldr r3, [sp, #16] + 8006be8: 2b00 cmp r3, #0 + 8006bea: d171 bne.n 8006cd0 <_strtod_l+0x8b8> + 8006bec: e63d b.n 800686a <_strtod_l+0x452> + 8006bee: f018 0f01 tst.w r8, #1 + 8006bf2: d004 beq.n 8006bfe <_strtod_l+0x7e6> + 8006bf4: e9d5 2300 ldrd r2, r3, [r5] + 8006bf8: f7f9 fd06 bl 8000608 <__aeabi_dmul> + 8006bfc: 2301 movs r3, #1 + 8006bfe: ea4f 0868 mov.w r8, r8, asr #1 + 8006c02: 3508 adds r5, #8 + 8006c04: e6e5 b.n 80069d2 <_strtod_l+0x5ba> + 8006c06: f04f 32ff mov.w r2, #4294967295 + 8006c0a: fa02 f303 lsl.w r3, r2, r3 + 8006c0e: ea03 0a0a and.w sl, r3, sl + 8006c12: e6ff b.n 8006a14 <_strtod_l+0x5fc> + 8006c14: f1c6 467f rsb r6, r6, #4278190080 ; 0xff000000 + 8006c18: f506 067f add.w r6, r6, #16711680 ; 0xff0000 + 8006c1c: f506 467b add.w r6, r6, #64256 ; 0xfb00 + 8006c20: 36e2 adds r6, #226 ; 0xe2 + 8006c22: fa01 f306 lsl.w r3, r1, r6 + 8006c26: 930a str r3, [sp, #40] ; 0x28 + 8006c28: 910f str r1, [sp, #60] ; 0x3c + 8006c2a: e75d b.n 8006ae8 <_strtod_l+0x6d0> + 8006c2c: 2300 movs r3, #0 + 8006c2e: 930a str r3, [sp, #40] ; 0x28 + 8006c30: 2301 movs r3, #1 + 8006c32: 930f str r3, [sp, #60] ; 0x3c + 8006c34: e758 b.n 8006ae8 <_strtod_l+0x6d0> + 8006c36: 4632 mov r2, r6 + 8006c38: 991c ldr r1, [sp, #112] ; 0x70 + 8006c3a: 4648 mov r0, r9 + 8006c3c: f002 f8ba bl 8008db4 <__lshift> + 8006c40: 901c str r0, [sp, #112] ; 0x70 + 8006c42: 2800 cmp r0, #0 + 8006c44: f47f af7c bne.w 8006b40 <_strtod_l+0x728> + 8006c48: e604 b.n 8006854 <_strtod_l+0x43c> + 8006c4a: bf00 nop + 8006c4c: 08009aa0 .word 0x08009aa0 + 8006c50: fffffc02 .word 0xfffffc02 + 8006c54: 465d mov r5, fp + 8006c56: f040 8086 bne.w 8006d66 <_strtod_l+0x94e> + 8006c5a: 9a0c ldr r2, [sp, #48] ; 0x30 + 8006c5c: f3cb 0313 ubfx r3, fp, #0, #20 + 8006c60: b32a cbz r2, 8006cae <_strtod_l+0x896> + 8006c62: 4aaf ldr r2, [pc, #700] ; (8006f20 <_strtod_l+0xb08>) + 8006c64: 4293 cmp r3, r2 + 8006c66: d153 bne.n 8006d10 <_strtod_l+0x8f8> + 8006c68: 9b04 ldr r3, [sp, #16] + 8006c6a: 4650 mov r0, sl + 8006c6c: b1d3 cbz r3, 8006ca4 <_strtod_l+0x88c> + 8006c6e: 4aad ldr r2, [pc, #692] ; (8006f24 <_strtod_l+0xb0c>) + 8006c70: 402a ands r2, r5 + 8006c72: f1b2 6fd4 cmp.w r2, #111149056 ; 0x6a00000 + 8006c76: f04f 31ff mov.w r1, #4294967295 + 8006c7a: d816 bhi.n 8006caa <_strtod_l+0x892> + 8006c7c: 0d12 lsrs r2, r2, #20 + 8006c7e: f1c2 036b rsb r3, r2, #107 ; 0x6b + 8006c82: fa01 f303 lsl.w r3, r1, r3 + 8006c86: 4298 cmp r0, r3 + 8006c88: d142 bne.n 8006d10 <_strtod_l+0x8f8> + 8006c8a: 4ba7 ldr r3, [pc, #668] ; (8006f28 <_strtod_l+0xb10>) + 8006c8c: 429d cmp r5, r3 + 8006c8e: d102 bne.n 8006c96 <_strtod_l+0x87e> + 8006c90: 3001 adds r0, #1 + 8006c92: f43f addf beq.w 8006854 <_strtod_l+0x43c> + 8006c96: 4ba3 ldr r3, [pc, #652] ; (8006f24 <_strtod_l+0xb0c>) + 8006c98: 402b ands r3, r5 + 8006c9a: f503 1b80 add.w fp, r3, #1048576 ; 0x100000 + 8006c9e: f04f 0a00 mov.w sl, #0 + 8006ca2: e7a0 b.n 8006be6 <_strtod_l+0x7ce> + 8006ca4: f04f 33ff mov.w r3, #4294967295 + 8006ca8: e7ed b.n 8006c86 <_strtod_l+0x86e> + 8006caa: 460b mov r3, r1 + 8006cac: e7eb b.n 8006c86 <_strtod_l+0x86e> + 8006cae: bb7b cbnz r3, 8006d10 <_strtod_l+0x8f8> + 8006cb0: f1ba 0f00 cmp.w sl, #0 + 8006cb4: d12c bne.n 8006d10 <_strtod_l+0x8f8> + 8006cb6: 9904 ldr r1, [sp, #16] + 8006cb8: 4a9a ldr r2, [pc, #616] ; (8006f24 <_strtod_l+0xb0c>) + 8006cba: 465b mov r3, fp + 8006cbc: b1f1 cbz r1, 8006cfc <_strtod_l+0x8e4> + 8006cbe: ea02 010b and.w r1, r2, fp + 8006cc2: f1b1 6fd6 cmp.w r1, #112197632 ; 0x6b00000 + 8006cc6: dc19 bgt.n 8006cfc <_strtod_l+0x8e4> + 8006cc8: f1b1 7f5c cmp.w r1, #57671680 ; 0x3700000 + 8006ccc: f77f ae5b ble.w 8006986 <_strtod_l+0x56e> + 8006cd0: 4a96 ldr r2, [pc, #600] ; (8006f2c <_strtod_l+0xb14>) + 8006cd2: 2300 movs r3, #0 + 8006cd4: e9cd 3214 strd r3, r2, [sp, #80] ; 0x50 + 8006cd8: 4650 mov r0, sl + 8006cda: 4659 mov r1, fp + 8006cdc: e9dd 2314 ldrd r2, r3, [sp, #80] ; 0x50 + 8006ce0: f7f9 fc92 bl 8000608 <__aeabi_dmul> + 8006ce4: 4682 mov sl, r0 + 8006ce6: 468b mov fp, r1 + 8006ce8: 2900 cmp r1, #0 + 8006cea: f47f adbe bne.w 800686a <_strtod_l+0x452> + 8006cee: 2800 cmp r0, #0 + 8006cf0: f47f adbb bne.w 800686a <_strtod_l+0x452> + 8006cf4: 2322 movs r3, #34 ; 0x22 + 8006cf6: f8c9 3000 str.w r3, [r9] + 8006cfa: e5b6 b.n 800686a <_strtod_l+0x452> + 8006cfc: 4013 ands r3, r2 + 8006cfe: f5a3 1380 sub.w r3, r3, #1048576 ; 0x100000 + 8006d02: ea6f 5b13 mvn.w fp, r3, lsr #20 + 8006d06: ea6f 5b0b mvn.w fp, fp, lsl #20 + 8006d0a: f04f 3aff mov.w sl, #4294967295 + 8006d0e: e76a b.n 8006be6 <_strtod_l+0x7ce> + 8006d10: 9b0a ldr r3, [sp, #40] ; 0x28 + 8006d12: b193 cbz r3, 8006d3a <_strtod_l+0x922> + 8006d14: 422b tst r3, r5 + 8006d16: f43f af66 beq.w 8006be6 <_strtod_l+0x7ce> + 8006d1a: 9b0c ldr r3, [sp, #48] ; 0x30 + 8006d1c: 9a04 ldr r2, [sp, #16] + 8006d1e: 4650 mov r0, sl + 8006d20: 4659 mov r1, fp + 8006d22: b173 cbz r3, 8006d42 <_strtod_l+0x92a> + 8006d24: f7ff fb5a bl 80063dc + 8006d28: 4602 mov r2, r0 + 8006d2a: 460b mov r3, r1 + 8006d2c: e9dd 0108 ldrd r0, r1, [sp, #32] + 8006d30: f7f9 fab4 bl 800029c <__adddf3> + 8006d34: 4682 mov sl, r0 + 8006d36: 468b mov fp, r1 + 8006d38: e755 b.n 8006be6 <_strtod_l+0x7ce> + 8006d3a: 9b0f ldr r3, [sp, #60] ; 0x3c + 8006d3c: ea13 0f0a tst.w r3, sl + 8006d40: e7e9 b.n 8006d16 <_strtod_l+0x8fe> + 8006d42: f7ff fb4b bl 80063dc + 8006d46: 4602 mov r2, r0 + 8006d48: 460b mov r3, r1 + 8006d4a: e9dd 0108 ldrd r0, r1, [sp, #32] + 8006d4e: f7f9 faa3 bl 8000298 <__aeabi_dsub> + 8006d52: 2200 movs r2, #0 + 8006d54: 2300 movs r3, #0 + 8006d56: 4682 mov sl, r0 + 8006d58: 468b mov fp, r1 + 8006d5a: f7f9 febd bl 8000ad8 <__aeabi_dcmpeq> + 8006d5e: 2800 cmp r0, #0 + 8006d60: f47f ae11 bne.w 8006986 <_strtod_l+0x56e> + 8006d64: e73f b.n 8006be6 <_strtod_l+0x7ce> + 8006d66: 4641 mov r1, r8 + 8006d68: 4620 mov r0, r4 + 8006d6a: f002 f9b4 bl 80090d6 <__ratio> + 8006d6e: ec57 6b10 vmov r6, r7, d0 + 8006d72: 2200 movs r2, #0 + 8006d74: f04f 4380 mov.w r3, #1073741824 ; 0x40000000 + 8006d78: ee10 0a10 vmov r0, s0 + 8006d7c: 4639 mov r1, r7 + 8006d7e: f7f9 febf bl 8000b00 <__aeabi_dcmple> + 8006d82: 2800 cmp r0, #0 + 8006d84: d077 beq.n 8006e76 <_strtod_l+0xa5e> + 8006d86: 9b0c ldr r3, [sp, #48] ; 0x30 + 8006d88: 2b00 cmp r3, #0 + 8006d8a: d04a beq.n 8006e22 <_strtod_l+0xa0a> + 8006d8c: 4b68 ldr r3, [pc, #416] ; (8006f30 <_strtod_l+0xb18>) + 8006d8e: 2200 movs r2, #0 + 8006d90: e9cd 230a strd r2, r3, [sp, #40] ; 0x28 + 8006d94: 4f66 ldr r7, [pc, #408] ; (8006f30 <_strtod_l+0xb18>) + 8006d96: 2600 movs r6, #0 + 8006d98: 4b62 ldr r3, [pc, #392] ; (8006f24 <_strtod_l+0xb0c>) + 8006d9a: 402b ands r3, r5 + 8006d9c: 930f str r3, [sp, #60] ; 0x3c + 8006d9e: 9a0f ldr r2, [sp, #60] ; 0x3c + 8006da0: 4b64 ldr r3, [pc, #400] ; (8006f34 <_strtod_l+0xb1c>) + 8006da2: 429a cmp r2, r3 + 8006da4: f040 80ce bne.w 8006f44 <_strtod_l+0xb2c> + 8006da8: e9dd 2308 ldrd r2, r3, [sp, #32] + 8006dac: e9dd 010a ldrd r0, r1, [sp, #40] ; 0x28 + 8006db0: f1a5 7b54 sub.w fp, r5, #55574528 ; 0x3500000 + 8006db4: ec4b ab10 vmov d0, sl, fp + 8006db8: e9cd 2314 strd r2, r3, [sp, #80] ; 0x50 + 8006dbc: e9cd 010a strd r0, r1, [sp, #40] ; 0x28 + 8006dc0: f002 f8c4 bl 8008f4c <__ulp> + 8006dc4: e9dd 010a ldrd r0, r1, [sp, #40] ; 0x28 + 8006dc8: ec53 2b10 vmov r2, r3, d0 + 8006dcc: f7f9 fc1c bl 8000608 <__aeabi_dmul> + 8006dd0: 4652 mov r2, sl + 8006dd2: 465b mov r3, fp + 8006dd4: f7f9 fa62 bl 800029c <__adddf3> + 8006dd8: 460b mov r3, r1 + 8006dda: 4952 ldr r1, [pc, #328] ; (8006f24 <_strtod_l+0xb0c>) + 8006ddc: 4a56 ldr r2, [pc, #344] ; (8006f38 <_strtod_l+0xb20>) + 8006dde: 4019 ands r1, r3 + 8006de0: 4291 cmp r1, r2 + 8006de2: 4682 mov sl, r0 + 8006de4: d95b bls.n 8006e9e <_strtod_l+0xa86> + 8006de6: 9b09 ldr r3, [sp, #36] ; 0x24 + 8006de8: f102 7254 add.w r2, r2, #55574528 ; 0x3500000 + 8006dec: 4293 cmp r3, r2 + 8006dee: d103 bne.n 8006df8 <_strtod_l+0x9e0> + 8006df0: 9b08 ldr r3, [sp, #32] + 8006df2: 3301 adds r3, #1 + 8006df4: f43f ad2e beq.w 8006854 <_strtod_l+0x43c> + 8006df8: f8df b12c ldr.w fp, [pc, #300] ; 8006f28 <_strtod_l+0xb10> + 8006dfc: f04f 3aff mov.w sl, #4294967295 + 8006e00: 991c ldr r1, [sp, #112] ; 0x70 + 8006e02: 4648 mov r0, r9 + 8006e04: f001 fe0b bl 8008a1e <_Bfree> + 8006e08: 9905 ldr r1, [sp, #20] + 8006e0a: 4648 mov r0, r9 + 8006e0c: f001 fe07 bl 8008a1e <_Bfree> + 8006e10: 4641 mov r1, r8 + 8006e12: 4648 mov r0, r9 + 8006e14: f001 fe03 bl 8008a1e <_Bfree> + 8006e18: 4621 mov r1, r4 + 8006e1a: 4648 mov r0, r9 + 8006e1c: f001 fdff bl 8008a1e <_Bfree> + 8006e20: e619 b.n 8006a56 <_strtod_l+0x63e> + 8006e22: f1ba 0f00 cmp.w sl, #0 + 8006e26: d11a bne.n 8006e5e <_strtod_l+0xa46> + 8006e28: f3cb 0313 ubfx r3, fp, #0, #20 + 8006e2c: b9eb cbnz r3, 8006e6a <_strtod_l+0xa52> + 8006e2e: 2200 movs r2, #0 + 8006e30: 4b3f ldr r3, [pc, #252] ; (8006f30 <_strtod_l+0xb18>) + 8006e32: 4630 mov r0, r6 + 8006e34: 4639 mov r1, r7 + 8006e36: f7f9 fe59 bl 8000aec <__aeabi_dcmplt> + 8006e3a: b9c8 cbnz r0, 8006e70 <_strtod_l+0xa58> + 8006e3c: 4630 mov r0, r6 + 8006e3e: 4639 mov r1, r7 + 8006e40: 2200 movs r2, #0 + 8006e42: 4b3e ldr r3, [pc, #248] ; (8006f3c <_strtod_l+0xb24>) + 8006e44: f7f9 fbe0 bl 8000608 <__aeabi_dmul> + 8006e48: 4606 mov r6, r0 + 8006e4a: 460f mov r7, r1 + 8006e4c: f107 4300 add.w r3, r7, #2147483648 ; 0x80000000 + 8006e50: 9618 str r6, [sp, #96] ; 0x60 + 8006e52: 9319 str r3, [sp, #100] ; 0x64 + 8006e54: e9dd 2318 ldrd r2, r3, [sp, #96] ; 0x60 + 8006e58: e9cd 230a strd r2, r3, [sp, #40] ; 0x28 + 8006e5c: e79c b.n 8006d98 <_strtod_l+0x980> + 8006e5e: f1ba 0f01 cmp.w sl, #1 + 8006e62: d102 bne.n 8006e6a <_strtod_l+0xa52> + 8006e64: 2d00 cmp r5, #0 + 8006e66: f43f ad8e beq.w 8006986 <_strtod_l+0x56e> + 8006e6a: 2200 movs r2, #0 + 8006e6c: 4b34 ldr r3, [pc, #208] ; (8006f40 <_strtod_l+0xb28>) + 8006e6e: e78f b.n 8006d90 <_strtod_l+0x978> + 8006e70: 2600 movs r6, #0 + 8006e72: 4f32 ldr r7, [pc, #200] ; (8006f3c <_strtod_l+0xb24>) + 8006e74: e7ea b.n 8006e4c <_strtod_l+0xa34> + 8006e76: 4b31 ldr r3, [pc, #196] ; (8006f3c <_strtod_l+0xb24>) + 8006e78: 4630 mov r0, r6 + 8006e7a: 4639 mov r1, r7 + 8006e7c: 2200 movs r2, #0 + 8006e7e: f7f9 fbc3 bl 8000608 <__aeabi_dmul> + 8006e82: 9b0c ldr r3, [sp, #48] ; 0x30 + 8006e84: 4606 mov r6, r0 + 8006e86: 460f mov r7, r1 + 8006e88: b933 cbnz r3, 8006e98 <_strtod_l+0xa80> + 8006e8a: f101 4300 add.w r3, r1, #2147483648 ; 0x80000000 + 8006e8e: 9010 str r0, [sp, #64] ; 0x40 + 8006e90: 9311 str r3, [sp, #68] ; 0x44 + 8006e92: e9dd 2310 ldrd r2, r3, [sp, #64] ; 0x40 + 8006e96: e7df b.n 8006e58 <_strtod_l+0xa40> + 8006e98: e9cd 6710 strd r6, r7, [sp, #64] ; 0x40 + 8006e9c: e7f9 b.n 8006e92 <_strtod_l+0xa7a> + 8006e9e: f103 7b54 add.w fp, r3, #55574528 ; 0x3500000 + 8006ea2: 9b04 ldr r3, [sp, #16] + 8006ea4: 2b00 cmp r3, #0 + 8006ea6: d1ab bne.n 8006e00 <_strtod_l+0x9e8> + 8006ea8: f02b 4300 bic.w r3, fp, #2147483648 ; 0x80000000 + 8006eac: 0d1b lsrs r3, r3, #20 + 8006eae: 9a0f ldr r2, [sp, #60] ; 0x3c + 8006eb0: 051b lsls r3, r3, #20 + 8006eb2: 429a cmp r2, r3 + 8006eb4: 465d mov r5, fp + 8006eb6: d1a3 bne.n 8006e00 <_strtod_l+0x9e8> + 8006eb8: 4639 mov r1, r7 + 8006eba: 4630 mov r0, r6 + 8006ebc: f7f9 fe54 bl 8000b68 <__aeabi_d2iz> + 8006ec0: f7f9 fb38 bl 8000534 <__aeabi_i2d> + 8006ec4: 460b mov r3, r1 + 8006ec6: 4602 mov r2, r0 + 8006ec8: 4639 mov r1, r7 + 8006eca: 4630 mov r0, r6 + 8006ecc: f7f9 f9e4 bl 8000298 <__aeabi_dsub> + 8006ed0: 9b0c ldr r3, [sp, #48] ; 0x30 + 8006ed2: 4606 mov r6, r0 + 8006ed4: 460f mov r7, r1 + 8006ed6: b933 cbnz r3, 8006ee6 <_strtod_l+0xace> + 8006ed8: f1ba 0f00 cmp.w sl, #0 + 8006edc: d103 bne.n 8006ee6 <_strtod_l+0xace> + 8006ede: f3cb 0513 ubfx r5, fp, #0, #20 + 8006ee2: 2d00 cmp r5, #0 + 8006ee4: d06d beq.n 8006fc2 <_strtod_l+0xbaa> + 8006ee6: a30a add r3, pc, #40 ; (adr r3, 8006f10 <_strtod_l+0xaf8>) + 8006ee8: e9d3 2300 ldrd r2, r3, [r3] + 8006eec: 4630 mov r0, r6 + 8006eee: 4639 mov r1, r7 + 8006ef0: f7f9 fdfc bl 8000aec <__aeabi_dcmplt> + 8006ef4: 2800 cmp r0, #0 + 8006ef6: f47f acb8 bne.w 800686a <_strtod_l+0x452> + 8006efa: a307 add r3, pc, #28 ; (adr r3, 8006f18 <_strtod_l+0xb00>) + 8006efc: e9d3 2300 ldrd r2, r3, [r3] + 8006f00: 4630 mov r0, r6 + 8006f02: 4639 mov r1, r7 + 8006f04: f7f9 fe10 bl 8000b28 <__aeabi_dcmpgt> + 8006f08: 2800 cmp r0, #0 + 8006f0a: f43f af79 beq.w 8006e00 <_strtod_l+0x9e8> + 8006f0e: e4ac b.n 800686a <_strtod_l+0x452> + 8006f10: 94a03595 .word 0x94a03595 + 8006f14: 3fdfffff .word 0x3fdfffff + 8006f18: 35afe535 .word 0x35afe535 + 8006f1c: 3fe00000 .word 0x3fe00000 + 8006f20: 000fffff .word 0x000fffff + 8006f24: 7ff00000 .word 0x7ff00000 + 8006f28: 7fefffff .word 0x7fefffff + 8006f2c: 39500000 .word 0x39500000 + 8006f30: 3ff00000 .word 0x3ff00000 + 8006f34: 7fe00000 .word 0x7fe00000 + 8006f38: 7c9fffff .word 0x7c9fffff + 8006f3c: 3fe00000 .word 0x3fe00000 + 8006f40: bff00000 .word 0xbff00000 + 8006f44: 9b04 ldr r3, [sp, #16] + 8006f46: b333 cbz r3, 8006f96 <_strtod_l+0xb7e> + 8006f48: 9b0f ldr r3, [sp, #60] ; 0x3c + 8006f4a: f1b3 6fd4 cmp.w r3, #111149056 ; 0x6a00000 + 8006f4e: d822 bhi.n 8006f96 <_strtod_l+0xb7e> + 8006f50: a327 add r3, pc, #156 ; (adr r3, 8006ff0 <_strtod_l+0xbd8>) + 8006f52: e9d3 2300 ldrd r2, r3, [r3] + 8006f56: 4630 mov r0, r6 + 8006f58: 4639 mov r1, r7 + 8006f5a: f7f9 fdd1 bl 8000b00 <__aeabi_dcmple> + 8006f5e: b1a0 cbz r0, 8006f8a <_strtod_l+0xb72> + 8006f60: 4639 mov r1, r7 + 8006f62: 4630 mov r0, r6 + 8006f64: f7f9 fe28 bl 8000bb8 <__aeabi_d2uiz> + 8006f68: 2800 cmp r0, #0 + 8006f6a: bf08 it eq + 8006f6c: 2001 moveq r0, #1 + 8006f6e: f7f9 fad1 bl 8000514 <__aeabi_ui2d> + 8006f72: 9b0c ldr r3, [sp, #48] ; 0x30 + 8006f74: 4606 mov r6, r0 + 8006f76: 460f mov r7, r1 + 8006f78: bb03 cbnz r3, 8006fbc <_strtod_l+0xba4> + 8006f7a: f101 4300 add.w r3, r1, #2147483648 ; 0x80000000 + 8006f7e: 9012 str r0, [sp, #72] ; 0x48 + 8006f80: 9313 str r3, [sp, #76] ; 0x4c + 8006f82: e9dd 2312 ldrd r2, r3, [sp, #72] ; 0x48 + 8006f86: e9cd 230a strd r2, r3, [sp, #40] ; 0x28 + 8006f8a: 9b0b ldr r3, [sp, #44] ; 0x2c + 8006f8c: 9a0f ldr r2, [sp, #60] ; 0x3c + 8006f8e: f103 63d6 add.w r3, r3, #112197632 ; 0x6b00000 + 8006f92: 1a9b subs r3, r3, r2 + 8006f94: 930b str r3, [sp, #44] ; 0x2c + 8006f96: ed9d 0b08 vldr d0, [sp, #32] + 8006f9a: e9dd ab0a ldrd sl, fp, [sp, #40] ; 0x28 + 8006f9e: f001 ffd5 bl 8008f4c <__ulp> + 8006fa2: 4650 mov r0, sl + 8006fa4: ec53 2b10 vmov r2, r3, d0 + 8006fa8: 4659 mov r1, fp + 8006faa: f7f9 fb2d bl 8000608 <__aeabi_dmul> + 8006fae: e9dd 2308 ldrd r2, r3, [sp, #32] + 8006fb2: f7f9 f973 bl 800029c <__adddf3> + 8006fb6: 4682 mov sl, r0 + 8006fb8: 468b mov fp, r1 + 8006fba: e772 b.n 8006ea2 <_strtod_l+0xa8a> + 8006fbc: e9cd 6712 strd r6, r7, [sp, #72] ; 0x48 + 8006fc0: e7df b.n 8006f82 <_strtod_l+0xb6a> + 8006fc2: a30d add r3, pc, #52 ; (adr r3, 8006ff8 <_strtod_l+0xbe0>) + 8006fc4: e9d3 2300 ldrd r2, r3, [r3] + 8006fc8: f7f9 fd90 bl 8000aec <__aeabi_dcmplt> + 8006fcc: e79c b.n 8006f08 <_strtod_l+0xaf0> + 8006fce: 2300 movs r3, #0 + 8006fd0: 930d str r3, [sp, #52] ; 0x34 + 8006fd2: 9a17 ldr r2, [sp, #92] ; 0x5c + 8006fd4: 9b1b ldr r3, [sp, #108] ; 0x6c + 8006fd6: 6013 str r3, [r2, #0] + 8006fd8: f7ff ba61 b.w 800649e <_strtod_l+0x86> + 8006fdc: 2b65 cmp r3, #101 ; 0x65 + 8006fde: f04f 0200 mov.w r2, #0 + 8006fe2: f43f ab4e beq.w 8006682 <_strtod_l+0x26a> + 8006fe6: 2101 movs r1, #1 + 8006fe8: 4614 mov r4, r2 + 8006fea: 9104 str r1, [sp, #16] + 8006fec: f7ff bacb b.w 8006586 <_strtod_l+0x16e> + 8006ff0: ffc00000 .word 0xffc00000 + 8006ff4: 41dfffff .word 0x41dfffff + 8006ff8: 94a03595 .word 0x94a03595 + 8006ffc: 3fcfffff .word 0x3fcfffff + +08007000 <_strtod_r>: + 8007000: 4b05 ldr r3, [pc, #20] ; (8007018 <_strtod_r+0x18>) + 8007002: 681b ldr r3, [r3, #0] + 8007004: b410 push {r4} + 8007006: 6a1b ldr r3, [r3, #32] + 8007008: 4c04 ldr r4, [pc, #16] ; (800701c <_strtod_r+0x1c>) + 800700a: 2b00 cmp r3, #0 + 800700c: bf08 it eq + 800700e: 4623 moveq r3, r4 + 8007010: f85d 4b04 ldr.w r4, [sp], #4 + 8007014: f7ff ba00 b.w 8006418 <_strtod_l> + 8007018: 2000002c .word 0x2000002c + 800701c: 20000090 .word 0x20000090 + +08007020 <_strtol_l.isra.0>: + 8007020: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 8007024: 4680 mov r8, r0 + 8007026: 4689 mov r9, r1 + 8007028: 4692 mov sl, r2 + 800702a: 461e mov r6, r3 + 800702c: 460f mov r7, r1 + 800702e: 463d mov r5, r7 + 8007030: 9808 ldr r0, [sp, #32] + 8007032: f815 4b01 ldrb.w r4, [r5], #1 + 8007036: f001 fc27 bl 8008888 <__locale_ctype_ptr_l> + 800703a: 4420 add r0, r4 + 800703c: 7843 ldrb r3, [r0, #1] + 800703e: f013 0308 ands.w r3, r3, #8 + 8007042: d132 bne.n 80070aa <_strtol_l.isra.0+0x8a> + 8007044: 2c2d cmp r4, #45 ; 0x2d + 8007046: d132 bne.n 80070ae <_strtol_l.isra.0+0x8e> + 8007048: 787c ldrb r4, [r7, #1] + 800704a: 1cbd adds r5, r7, #2 + 800704c: 2201 movs r2, #1 + 800704e: 2e00 cmp r6, #0 + 8007050: d05d beq.n 800710e <_strtol_l.isra.0+0xee> + 8007052: 2e10 cmp r6, #16 + 8007054: d109 bne.n 800706a <_strtol_l.isra.0+0x4a> + 8007056: 2c30 cmp r4, #48 ; 0x30 + 8007058: d107 bne.n 800706a <_strtol_l.isra.0+0x4a> + 800705a: 782b ldrb r3, [r5, #0] + 800705c: f003 03df and.w r3, r3, #223 ; 0xdf + 8007060: 2b58 cmp r3, #88 ; 0x58 + 8007062: d14f bne.n 8007104 <_strtol_l.isra.0+0xe4> + 8007064: 786c ldrb r4, [r5, #1] + 8007066: 2610 movs r6, #16 + 8007068: 3502 adds r5, #2 + 800706a: 2a00 cmp r2, #0 + 800706c: bf14 ite ne + 800706e: f04f 4100 movne.w r1, #2147483648 ; 0x80000000 + 8007072: f06f 4100 mvneq.w r1, #2147483648 ; 0x80000000 + 8007076: 2700 movs r7, #0 + 8007078: fbb1 fcf6 udiv ip, r1, r6 + 800707c: 4638 mov r0, r7 + 800707e: fb06 1e1c mls lr, r6, ip, r1 + 8007082: f1a4 0330 sub.w r3, r4, #48 ; 0x30 + 8007086: 2b09 cmp r3, #9 + 8007088: d817 bhi.n 80070ba <_strtol_l.isra.0+0x9a> + 800708a: 461c mov r4, r3 + 800708c: 42a6 cmp r6, r4 + 800708e: dd23 ble.n 80070d8 <_strtol_l.isra.0+0xb8> + 8007090: 1c7b adds r3, r7, #1 + 8007092: d007 beq.n 80070a4 <_strtol_l.isra.0+0x84> + 8007094: 4584 cmp ip, r0 + 8007096: d31c bcc.n 80070d2 <_strtol_l.isra.0+0xb2> + 8007098: d101 bne.n 800709e <_strtol_l.isra.0+0x7e> + 800709a: 45a6 cmp lr, r4 + 800709c: db19 blt.n 80070d2 <_strtol_l.isra.0+0xb2> + 800709e: fb00 4006 mla r0, r0, r6, r4 + 80070a2: 2701 movs r7, #1 + 80070a4: f815 4b01 ldrb.w r4, [r5], #1 + 80070a8: e7eb b.n 8007082 <_strtol_l.isra.0+0x62> + 80070aa: 462f mov r7, r5 + 80070ac: e7bf b.n 800702e <_strtol_l.isra.0+0xe> + 80070ae: 2c2b cmp r4, #43 ; 0x2b + 80070b0: bf04 itt eq + 80070b2: 1cbd addeq r5, r7, #2 + 80070b4: 787c ldrbeq r4, [r7, #1] + 80070b6: 461a mov r2, r3 + 80070b8: e7c9 b.n 800704e <_strtol_l.isra.0+0x2e> + 80070ba: f1a4 0341 sub.w r3, r4, #65 ; 0x41 + 80070be: 2b19 cmp r3, #25 + 80070c0: d801 bhi.n 80070c6 <_strtol_l.isra.0+0xa6> + 80070c2: 3c37 subs r4, #55 ; 0x37 + 80070c4: e7e2 b.n 800708c <_strtol_l.isra.0+0x6c> + 80070c6: f1a4 0361 sub.w r3, r4, #97 ; 0x61 + 80070ca: 2b19 cmp r3, #25 + 80070cc: d804 bhi.n 80070d8 <_strtol_l.isra.0+0xb8> + 80070ce: 3c57 subs r4, #87 ; 0x57 + 80070d0: e7dc b.n 800708c <_strtol_l.isra.0+0x6c> + 80070d2: f04f 37ff mov.w r7, #4294967295 + 80070d6: e7e5 b.n 80070a4 <_strtol_l.isra.0+0x84> + 80070d8: 1c7b adds r3, r7, #1 + 80070da: d108 bne.n 80070ee <_strtol_l.isra.0+0xce> + 80070dc: 2322 movs r3, #34 ; 0x22 + 80070de: f8c8 3000 str.w r3, [r8] + 80070e2: 4608 mov r0, r1 + 80070e4: f1ba 0f00 cmp.w sl, #0 + 80070e8: d107 bne.n 80070fa <_strtol_l.isra.0+0xda> + 80070ea: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 80070ee: b102 cbz r2, 80070f2 <_strtol_l.isra.0+0xd2> + 80070f0: 4240 negs r0, r0 + 80070f2: f1ba 0f00 cmp.w sl, #0 + 80070f6: d0f8 beq.n 80070ea <_strtol_l.isra.0+0xca> + 80070f8: b10f cbz r7, 80070fe <_strtol_l.isra.0+0xde> + 80070fa: f105 39ff add.w r9, r5, #4294967295 + 80070fe: f8ca 9000 str.w r9, [sl] + 8007102: e7f2 b.n 80070ea <_strtol_l.isra.0+0xca> + 8007104: 2430 movs r4, #48 ; 0x30 + 8007106: 2e00 cmp r6, #0 + 8007108: d1af bne.n 800706a <_strtol_l.isra.0+0x4a> + 800710a: 2608 movs r6, #8 + 800710c: e7ad b.n 800706a <_strtol_l.isra.0+0x4a> + 800710e: 2c30 cmp r4, #48 ; 0x30 + 8007110: d0a3 beq.n 800705a <_strtol_l.isra.0+0x3a> + 8007112: 260a movs r6, #10 + 8007114: e7a9 b.n 800706a <_strtol_l.isra.0+0x4a> + ... + +08007118 <_strtol_r>: + 8007118: b537 push {r0, r1, r2, r4, r5, lr} + 800711a: 4c06 ldr r4, [pc, #24] ; (8007134 <_strtol_r+0x1c>) + 800711c: 4d06 ldr r5, [pc, #24] ; (8007138 <_strtol_r+0x20>) + 800711e: 6824 ldr r4, [r4, #0] + 8007120: 6a24 ldr r4, [r4, #32] + 8007122: 2c00 cmp r4, #0 + 8007124: bf08 it eq + 8007126: 462c moveq r4, r5 + 8007128: 9400 str r4, [sp, #0] + 800712a: f7ff ff79 bl 8007020 <_strtol_l.isra.0> + 800712e: b003 add sp, #12 + 8007130: bd30 pop {r4, r5, pc} + 8007132: bf00 nop + 8007134: 2000002c .word 0x2000002c + 8007138: 20000090 .word 0x20000090 + +0800713c <__swbuf_r>: + 800713c: b5f8 push {r3, r4, r5, r6, r7, lr} + 800713e: 460e mov r6, r1 + 8007140: 4614 mov r4, r2 + 8007142: 4605 mov r5, r0 + 8007144: b118 cbz r0, 800714e <__swbuf_r+0x12> + 8007146: 6983 ldr r3, [r0, #24] + 8007148: b90b cbnz r3, 800714e <__swbuf_r+0x12> + 800714a: f000 ffed bl 8008128 <__sinit> + 800714e: 4b21 ldr r3, [pc, #132] ; (80071d4 <__swbuf_r+0x98>) + 8007150: 429c cmp r4, r3 + 8007152: d12a bne.n 80071aa <__swbuf_r+0x6e> + 8007154: 686c ldr r4, [r5, #4] + 8007156: 69a3 ldr r3, [r4, #24] + 8007158: 60a3 str r3, [r4, #8] + 800715a: 89a3 ldrh r3, [r4, #12] + 800715c: 071a lsls r2, r3, #28 + 800715e: d52e bpl.n 80071be <__swbuf_r+0x82> + 8007160: 6923 ldr r3, [r4, #16] + 8007162: b363 cbz r3, 80071be <__swbuf_r+0x82> + 8007164: 6923 ldr r3, [r4, #16] + 8007166: 6820 ldr r0, [r4, #0] + 8007168: 1ac0 subs r0, r0, r3 + 800716a: 6963 ldr r3, [r4, #20] + 800716c: b2f6 uxtb r6, r6 + 800716e: 4283 cmp r3, r0 + 8007170: 4637 mov r7, r6 + 8007172: dc04 bgt.n 800717e <__swbuf_r+0x42> + 8007174: 4621 mov r1, r4 + 8007176: 4628 mov r0, r5 + 8007178: f000 ff6c bl 8008054 <_fflush_r> + 800717c: bb28 cbnz r0, 80071ca <__swbuf_r+0x8e> + 800717e: 68a3 ldr r3, [r4, #8] + 8007180: 3b01 subs r3, #1 + 8007182: 60a3 str r3, [r4, #8] + 8007184: 6823 ldr r3, [r4, #0] + 8007186: 1c5a adds r2, r3, #1 + 8007188: 6022 str r2, [r4, #0] + 800718a: 701e strb r6, [r3, #0] + 800718c: 6963 ldr r3, [r4, #20] + 800718e: 3001 adds r0, #1 + 8007190: 4283 cmp r3, r0 + 8007192: d004 beq.n 800719e <__swbuf_r+0x62> + 8007194: 89a3 ldrh r3, [r4, #12] + 8007196: 07db lsls r3, r3, #31 + 8007198: d519 bpl.n 80071ce <__swbuf_r+0x92> + 800719a: 2e0a cmp r6, #10 + 800719c: d117 bne.n 80071ce <__swbuf_r+0x92> + 800719e: 4621 mov r1, r4 + 80071a0: 4628 mov r0, r5 + 80071a2: f000 ff57 bl 8008054 <_fflush_r> + 80071a6: b190 cbz r0, 80071ce <__swbuf_r+0x92> + 80071a8: e00f b.n 80071ca <__swbuf_r+0x8e> + 80071aa: 4b0b ldr r3, [pc, #44] ; (80071d8 <__swbuf_r+0x9c>) + 80071ac: 429c cmp r4, r3 + 80071ae: d101 bne.n 80071b4 <__swbuf_r+0x78> + 80071b0: 68ac ldr r4, [r5, #8] + 80071b2: e7d0 b.n 8007156 <__swbuf_r+0x1a> + 80071b4: 4b09 ldr r3, [pc, #36] ; (80071dc <__swbuf_r+0xa0>) + 80071b6: 429c cmp r4, r3 + 80071b8: bf08 it eq + 80071ba: 68ec ldreq r4, [r5, #12] + 80071bc: e7cb b.n 8007156 <__swbuf_r+0x1a> + 80071be: 4621 mov r1, r4 + 80071c0: 4628 mov r0, r5 + 80071c2: f000 f80d bl 80071e0 <__swsetup_r> + 80071c6: 2800 cmp r0, #0 + 80071c8: d0cc beq.n 8007164 <__swbuf_r+0x28> + 80071ca: f04f 37ff mov.w r7, #4294967295 + 80071ce: 4638 mov r0, r7 + 80071d0: bdf8 pop {r3, r4, r5, r6, r7, pc} + 80071d2: bf00 nop + 80071d4: 08009af8 .word 0x08009af8 + 80071d8: 08009b18 .word 0x08009b18 + 80071dc: 08009ad8 .word 0x08009ad8 + +080071e0 <__swsetup_r>: + 80071e0: 4b32 ldr r3, [pc, #200] ; (80072ac <__swsetup_r+0xcc>) + 80071e2: b570 push {r4, r5, r6, lr} + 80071e4: 681d ldr r5, [r3, #0] + 80071e6: 4606 mov r6, r0 + 80071e8: 460c mov r4, r1 + 80071ea: b125 cbz r5, 80071f6 <__swsetup_r+0x16> + 80071ec: 69ab ldr r3, [r5, #24] + 80071ee: b913 cbnz r3, 80071f6 <__swsetup_r+0x16> + 80071f0: 4628 mov r0, r5 + 80071f2: f000 ff99 bl 8008128 <__sinit> + 80071f6: 4b2e ldr r3, [pc, #184] ; (80072b0 <__swsetup_r+0xd0>) + 80071f8: 429c cmp r4, r3 + 80071fa: d10f bne.n 800721c <__swsetup_r+0x3c> + 80071fc: 686c ldr r4, [r5, #4] + 80071fe: f9b4 300c ldrsh.w r3, [r4, #12] + 8007202: b29a uxth r2, r3 + 8007204: 0715 lsls r5, r2, #28 + 8007206: d42c bmi.n 8007262 <__swsetup_r+0x82> + 8007208: 06d0 lsls r0, r2, #27 + 800720a: d411 bmi.n 8007230 <__swsetup_r+0x50> + 800720c: 2209 movs r2, #9 + 800720e: 6032 str r2, [r6, #0] + 8007210: f043 0340 orr.w r3, r3, #64 ; 0x40 + 8007214: 81a3 strh r3, [r4, #12] + 8007216: f04f 30ff mov.w r0, #4294967295 + 800721a: e03e b.n 800729a <__swsetup_r+0xba> + 800721c: 4b25 ldr r3, [pc, #148] ; (80072b4 <__swsetup_r+0xd4>) + 800721e: 429c cmp r4, r3 + 8007220: d101 bne.n 8007226 <__swsetup_r+0x46> + 8007222: 68ac ldr r4, [r5, #8] + 8007224: e7eb b.n 80071fe <__swsetup_r+0x1e> + 8007226: 4b24 ldr r3, [pc, #144] ; (80072b8 <__swsetup_r+0xd8>) + 8007228: 429c cmp r4, r3 + 800722a: bf08 it eq + 800722c: 68ec ldreq r4, [r5, #12] + 800722e: e7e6 b.n 80071fe <__swsetup_r+0x1e> + 8007230: 0751 lsls r1, r2, #29 + 8007232: d512 bpl.n 800725a <__swsetup_r+0x7a> + 8007234: 6b61 ldr r1, [r4, #52] ; 0x34 + 8007236: b141 cbz r1, 800724a <__swsetup_r+0x6a> + 8007238: f104 0344 add.w r3, r4, #68 ; 0x44 + 800723c: 4299 cmp r1, r3 + 800723e: d002 beq.n 8007246 <__swsetup_r+0x66> + 8007240: 4630 mov r0, r6 + 8007242: f7fe f933 bl 80054ac <_free_r> + 8007246: 2300 movs r3, #0 + 8007248: 6363 str r3, [r4, #52] ; 0x34 + 800724a: 89a3 ldrh r3, [r4, #12] + 800724c: f023 0324 bic.w r3, r3, #36 ; 0x24 + 8007250: 81a3 strh r3, [r4, #12] + 8007252: 2300 movs r3, #0 + 8007254: 6063 str r3, [r4, #4] + 8007256: 6923 ldr r3, [r4, #16] + 8007258: 6023 str r3, [r4, #0] + 800725a: 89a3 ldrh r3, [r4, #12] + 800725c: f043 0308 orr.w r3, r3, #8 + 8007260: 81a3 strh r3, [r4, #12] + 8007262: 6923 ldr r3, [r4, #16] + 8007264: b94b cbnz r3, 800727a <__swsetup_r+0x9a> + 8007266: 89a3 ldrh r3, [r4, #12] + 8007268: f403 7320 and.w r3, r3, #640 ; 0x280 + 800726c: f5b3 7f00 cmp.w r3, #512 ; 0x200 + 8007270: d003 beq.n 800727a <__swsetup_r+0x9a> + 8007272: 4621 mov r1, r4 + 8007274: 4630 mov r0, r6 + 8007276: f001 fb3f bl 80088f8 <__smakebuf_r> + 800727a: 89a2 ldrh r2, [r4, #12] + 800727c: f012 0301 ands.w r3, r2, #1 + 8007280: d00c beq.n 800729c <__swsetup_r+0xbc> + 8007282: 2300 movs r3, #0 + 8007284: 60a3 str r3, [r4, #8] + 8007286: 6963 ldr r3, [r4, #20] + 8007288: 425b negs r3, r3 + 800728a: 61a3 str r3, [r4, #24] + 800728c: 6923 ldr r3, [r4, #16] + 800728e: b953 cbnz r3, 80072a6 <__swsetup_r+0xc6> + 8007290: f9b4 300c ldrsh.w r3, [r4, #12] + 8007294: f013 0080 ands.w r0, r3, #128 ; 0x80 + 8007298: d1ba bne.n 8007210 <__swsetup_r+0x30> + 800729a: bd70 pop {r4, r5, r6, pc} + 800729c: 0792 lsls r2, r2, #30 + 800729e: bf58 it pl + 80072a0: 6963 ldrpl r3, [r4, #20] + 80072a2: 60a3 str r3, [r4, #8] + 80072a4: e7f2 b.n 800728c <__swsetup_r+0xac> + 80072a6: 2000 movs r0, #0 + 80072a8: e7f7 b.n 800729a <__swsetup_r+0xba> + 80072aa: bf00 nop + 80072ac: 2000002c .word 0x2000002c + 80072b0: 08009af8 .word 0x08009af8 + 80072b4: 08009b18 .word 0x08009b18 + 80072b8: 08009ad8 .word 0x08009ad8 + +080072bc : + 80072bc: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} + 80072c0: 6903 ldr r3, [r0, #16] + 80072c2: 690c ldr r4, [r1, #16] + 80072c4: 42a3 cmp r3, r4 + 80072c6: 4680 mov r8, r0 + 80072c8: f2c0 8082 blt.w 80073d0 + 80072cc: 3c01 subs r4, #1 + 80072ce: f101 0714 add.w r7, r1, #20 + 80072d2: ea4f 0c84 mov.w ip, r4, lsl #2 + 80072d6: f100 0614 add.w r6, r0, #20 + 80072da: f857 5024 ldr.w r5, [r7, r4, lsl #2] + 80072de: f856 0024 ldr.w r0, [r6, r4, lsl #2] + 80072e2: eb06 030c add.w r3, r6, ip + 80072e6: 3501 adds r5, #1 + 80072e8: eb07 090c add.w r9, r7, ip + 80072ec: 9301 str r3, [sp, #4] + 80072ee: fbb0 f5f5 udiv r5, r0, r5 + 80072f2: b395 cbz r5, 800735a + 80072f4: f04f 0a00 mov.w sl, #0 + 80072f8: 4638 mov r0, r7 + 80072fa: 46b6 mov lr, r6 + 80072fc: 46d3 mov fp, sl + 80072fe: f850 2b04 ldr.w r2, [r0], #4 + 8007302: b293 uxth r3, r2 + 8007304: fb05 a303 mla r3, r5, r3, sl + 8007308: ea4f 4a13 mov.w sl, r3, lsr #16 + 800730c: b29b uxth r3, r3 + 800730e: ebab 0303 sub.w r3, fp, r3 + 8007312: 0c12 lsrs r2, r2, #16 + 8007314: f8de b000 ldr.w fp, [lr] + 8007318: fb05 a202 mla r2, r5, r2, sl + 800731c: fa13 f38b uxtah r3, r3, fp + 8007320: ea4f 4a12 mov.w sl, r2, lsr #16 + 8007324: fa1f fb82 uxth.w fp, r2 + 8007328: f8de 2000 ldr.w r2, [lr] + 800732c: ebcb 4212 rsb r2, fp, r2, lsr #16 + 8007330: eb02 4223 add.w r2, r2, r3, asr #16 + 8007334: b29b uxth r3, r3 + 8007336: ea43 4302 orr.w r3, r3, r2, lsl #16 + 800733a: 4581 cmp r9, r0 + 800733c: ea4f 4b22 mov.w fp, r2, asr #16 + 8007340: f84e 3b04 str.w r3, [lr], #4 + 8007344: d2db bcs.n 80072fe + 8007346: f856 300c ldr.w r3, [r6, ip] + 800734a: b933 cbnz r3, 800735a + 800734c: 9b01 ldr r3, [sp, #4] + 800734e: 3b04 subs r3, #4 + 8007350: 429e cmp r6, r3 + 8007352: 461a mov r2, r3 + 8007354: d330 bcc.n 80073b8 + 8007356: f8c8 4010 str.w r4, [r8, #16] + 800735a: 4640 mov r0, r8 + 800735c: f001 fd7e bl 8008e5c <__mcmp> + 8007360: 2800 cmp r0, #0 + 8007362: db25 blt.n 80073b0 + 8007364: 3501 adds r5, #1 + 8007366: 4630 mov r0, r6 + 8007368: f04f 0c00 mov.w ip, #0 + 800736c: f857 2b04 ldr.w r2, [r7], #4 + 8007370: f8d0 e000 ldr.w lr, [r0] + 8007374: b293 uxth r3, r2 + 8007376: ebac 0303 sub.w r3, ip, r3 + 800737a: 0c12 lsrs r2, r2, #16 + 800737c: fa13 f38e uxtah r3, r3, lr + 8007380: ebc2 421e rsb r2, r2, lr, lsr #16 + 8007384: eb02 4223 add.w r2, r2, r3, asr #16 + 8007388: b29b uxth r3, r3 + 800738a: ea43 4302 orr.w r3, r3, r2, lsl #16 + 800738e: 45b9 cmp r9, r7 + 8007390: ea4f 4c22 mov.w ip, r2, asr #16 + 8007394: f840 3b04 str.w r3, [r0], #4 + 8007398: d2e8 bcs.n 800736c + 800739a: f856 2024 ldr.w r2, [r6, r4, lsl #2] + 800739e: eb06 0384 add.w r3, r6, r4, lsl #2 + 80073a2: b92a cbnz r2, 80073b0 + 80073a4: 3b04 subs r3, #4 + 80073a6: 429e cmp r6, r3 + 80073a8: 461a mov r2, r3 + 80073aa: d30b bcc.n 80073c4 + 80073ac: f8c8 4010 str.w r4, [r8, #16] + 80073b0: 4628 mov r0, r5 + 80073b2: b003 add sp, #12 + 80073b4: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 80073b8: 6812 ldr r2, [r2, #0] + 80073ba: 3b04 subs r3, #4 + 80073bc: 2a00 cmp r2, #0 + 80073be: d1ca bne.n 8007356 + 80073c0: 3c01 subs r4, #1 + 80073c2: e7c5 b.n 8007350 + 80073c4: 6812 ldr r2, [r2, #0] + 80073c6: 3b04 subs r3, #4 + 80073c8: 2a00 cmp r2, #0 + 80073ca: d1ef bne.n 80073ac + 80073cc: 3c01 subs r4, #1 + 80073ce: e7ea b.n 80073a6 + 80073d0: 2000 movs r0, #0 + 80073d2: e7ee b.n 80073b2 + 80073d4: 0000 movs r0, r0 + ... + +080073d8 <_dtoa_r>: + 80073d8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 80073dc: ec57 6b10 vmov r6, r7, d0 + 80073e0: b097 sub sp, #92 ; 0x5c + 80073e2: 6a45 ldr r5, [r0, #36] ; 0x24 + 80073e4: 9106 str r1, [sp, #24] + 80073e6: 4604 mov r4, r0 + 80073e8: 920b str r2, [sp, #44] ; 0x2c + 80073ea: 9312 str r3, [sp, #72] ; 0x48 + 80073ec: f8dd 8080 ldr.w r8, [sp, #128] ; 0x80 + 80073f0: e9cd 6700 strd r6, r7, [sp] + 80073f4: b93d cbnz r5, 8007406 <_dtoa_r+0x2e> + 80073f6: 2010 movs r0, #16 + 80073f8: f7fe f840 bl 800547c + 80073fc: 6260 str r0, [r4, #36] ; 0x24 + 80073fe: e9c0 5501 strd r5, r5, [r0, #4] + 8007402: 6005 str r5, [r0, #0] + 8007404: 60c5 str r5, [r0, #12] + 8007406: 6a63 ldr r3, [r4, #36] ; 0x24 + 8007408: 6819 ldr r1, [r3, #0] + 800740a: b151 cbz r1, 8007422 <_dtoa_r+0x4a> + 800740c: 685a ldr r2, [r3, #4] + 800740e: 604a str r2, [r1, #4] + 8007410: 2301 movs r3, #1 + 8007412: 4093 lsls r3, r2 + 8007414: 608b str r3, [r1, #8] + 8007416: 4620 mov r0, r4 + 8007418: f001 fb01 bl 8008a1e <_Bfree> + 800741c: 6a63 ldr r3, [r4, #36] ; 0x24 + 800741e: 2200 movs r2, #0 + 8007420: 601a str r2, [r3, #0] + 8007422: 1e3b subs r3, r7, #0 + 8007424: bfbb ittet lt + 8007426: f023 4300 biclt.w r3, r3, #2147483648 ; 0x80000000 + 800742a: 9301 strlt r3, [sp, #4] + 800742c: 2300 movge r3, #0 + 800742e: 2201 movlt r2, #1 + 8007430: bfac ite ge + 8007432: f8c8 3000 strge.w r3, [r8] + 8007436: f8c8 2000 strlt.w r2, [r8] + 800743a: 4baf ldr r3, [pc, #700] ; (80076f8 <_dtoa_r+0x320>) + 800743c: f8dd 8004 ldr.w r8, [sp, #4] + 8007440: ea33 0308 bics.w r3, r3, r8 + 8007444: d114 bne.n 8007470 <_dtoa_r+0x98> + 8007446: 9a12 ldr r2, [sp, #72] ; 0x48 + 8007448: f242 730f movw r3, #9999 ; 0x270f + 800744c: 6013 str r3, [r2, #0] + 800744e: 9b00 ldr r3, [sp, #0] + 8007450: b923 cbnz r3, 800745c <_dtoa_r+0x84> + 8007452: f3c8 0013 ubfx r0, r8, #0, #20 + 8007456: 2800 cmp r0, #0 + 8007458: f000 8542 beq.w 8007ee0 <_dtoa_r+0xb08> + 800745c: 9b21 ldr r3, [sp, #132] ; 0x84 + 800745e: f8df b2ac ldr.w fp, [pc, #684] ; 800770c <_dtoa_r+0x334> + 8007462: 2b00 cmp r3, #0 + 8007464: f000 8544 beq.w 8007ef0 <_dtoa_r+0xb18> + 8007468: f10b 0303 add.w r3, fp, #3 + 800746c: f000 bd3e b.w 8007eec <_dtoa_r+0xb14> + 8007470: e9dd 6700 ldrd r6, r7, [sp] + 8007474: 2200 movs r2, #0 + 8007476: 2300 movs r3, #0 + 8007478: 4630 mov r0, r6 + 800747a: 4639 mov r1, r7 + 800747c: f7f9 fb2c bl 8000ad8 <__aeabi_dcmpeq> + 8007480: 4681 mov r9, r0 + 8007482: b168 cbz r0, 80074a0 <_dtoa_r+0xc8> + 8007484: 9a12 ldr r2, [sp, #72] ; 0x48 + 8007486: 2301 movs r3, #1 + 8007488: 6013 str r3, [r2, #0] + 800748a: 9b21 ldr r3, [sp, #132] ; 0x84 + 800748c: 2b00 cmp r3, #0 + 800748e: f000 8524 beq.w 8007eda <_dtoa_r+0xb02> + 8007492: 4b9a ldr r3, [pc, #616] ; (80076fc <_dtoa_r+0x324>) + 8007494: 9a21 ldr r2, [sp, #132] ; 0x84 + 8007496: f103 3bff add.w fp, r3, #4294967295 + 800749a: 6013 str r3, [r2, #0] + 800749c: f000 bd28 b.w 8007ef0 <_dtoa_r+0xb18> + 80074a0: aa14 add r2, sp, #80 ; 0x50 + 80074a2: a915 add r1, sp, #84 ; 0x54 + 80074a4: ec47 6b10 vmov d0, r6, r7 + 80074a8: 4620 mov r0, r4 + 80074aa: f001 fdc5 bl 8009038 <__d2b> + 80074ae: f3c8 550a ubfx r5, r8, #20, #11 + 80074b2: 9004 str r0, [sp, #16] + 80074b4: 2d00 cmp r5, #0 + 80074b6: d07c beq.n 80075b2 <_dtoa_r+0x1da> + 80074b8: f3c7 0313 ubfx r3, r7, #0, #20 + 80074bc: f043 5b7f orr.w fp, r3, #1069547520 ; 0x3fc00000 + 80074c0: 46b2 mov sl, r6 + 80074c2: f44b 1b40 orr.w fp, fp, #3145728 ; 0x300000 + 80074c6: f2a5 35ff subw r5, r5, #1023 ; 0x3ff + 80074ca: f8cd 904c str.w r9, [sp, #76] ; 0x4c + 80074ce: 2200 movs r2, #0 + 80074d0: 4b8b ldr r3, [pc, #556] ; (8007700 <_dtoa_r+0x328>) + 80074d2: 4650 mov r0, sl + 80074d4: 4659 mov r1, fp + 80074d6: f7f8 fedf bl 8000298 <__aeabi_dsub> + 80074da: a381 add r3, pc, #516 ; (adr r3, 80076e0 <_dtoa_r+0x308>) + 80074dc: e9d3 2300 ldrd r2, r3, [r3] + 80074e0: f7f9 f892 bl 8000608 <__aeabi_dmul> + 80074e4: a380 add r3, pc, #512 ; (adr r3, 80076e8 <_dtoa_r+0x310>) + 80074e6: e9d3 2300 ldrd r2, r3, [r3] + 80074ea: f7f8 fed7 bl 800029c <__adddf3> + 80074ee: 4606 mov r6, r0 + 80074f0: 4628 mov r0, r5 + 80074f2: 460f mov r7, r1 + 80074f4: f7f9 f81e bl 8000534 <__aeabi_i2d> + 80074f8: a37d add r3, pc, #500 ; (adr r3, 80076f0 <_dtoa_r+0x318>) + 80074fa: e9d3 2300 ldrd r2, r3, [r3] + 80074fe: f7f9 f883 bl 8000608 <__aeabi_dmul> + 8007502: 4602 mov r2, r0 + 8007504: 460b mov r3, r1 + 8007506: 4630 mov r0, r6 + 8007508: 4639 mov r1, r7 + 800750a: f7f8 fec7 bl 800029c <__adddf3> + 800750e: 4606 mov r6, r0 + 8007510: 460f mov r7, r1 + 8007512: f7f9 fb29 bl 8000b68 <__aeabi_d2iz> + 8007516: 2200 movs r2, #0 + 8007518: 4682 mov sl, r0 + 800751a: 2300 movs r3, #0 + 800751c: 4630 mov r0, r6 + 800751e: 4639 mov r1, r7 + 8007520: f7f9 fae4 bl 8000aec <__aeabi_dcmplt> + 8007524: b148 cbz r0, 800753a <_dtoa_r+0x162> + 8007526: 4650 mov r0, sl + 8007528: f7f9 f804 bl 8000534 <__aeabi_i2d> + 800752c: 4632 mov r2, r6 + 800752e: 463b mov r3, r7 + 8007530: f7f9 fad2 bl 8000ad8 <__aeabi_dcmpeq> + 8007534: b908 cbnz r0, 800753a <_dtoa_r+0x162> + 8007536: f10a 3aff add.w sl, sl, #4294967295 + 800753a: f1ba 0f16 cmp.w sl, #22 + 800753e: d859 bhi.n 80075f4 <_dtoa_r+0x21c> + 8007540: 4970 ldr r1, [pc, #448] ; (8007704 <_dtoa_r+0x32c>) + 8007542: eb01 01ca add.w r1, r1, sl, lsl #3 + 8007546: e9dd 2300 ldrd r2, r3, [sp] + 800754a: e9d1 0100 ldrd r0, r1, [r1] + 800754e: f7f9 faeb bl 8000b28 <__aeabi_dcmpgt> + 8007552: 2800 cmp r0, #0 + 8007554: d050 beq.n 80075f8 <_dtoa_r+0x220> + 8007556: f10a 3aff add.w sl, sl, #4294967295 + 800755a: 2300 movs r3, #0 + 800755c: 930f str r3, [sp, #60] ; 0x3c + 800755e: 9b14 ldr r3, [sp, #80] ; 0x50 + 8007560: 1b5d subs r5, r3, r5 + 8007562: f1b5 0801 subs.w r8, r5, #1 + 8007566: bf49 itett mi + 8007568: f1c5 0301 rsbmi r3, r5, #1 + 800756c: 2300 movpl r3, #0 + 800756e: 9305 strmi r3, [sp, #20] + 8007570: f04f 0800 movmi.w r8, #0 + 8007574: bf58 it pl + 8007576: 9305 strpl r3, [sp, #20] + 8007578: f1ba 0f00 cmp.w sl, #0 + 800757c: db3e blt.n 80075fc <_dtoa_r+0x224> + 800757e: 2300 movs r3, #0 + 8007580: 44d0 add r8, sl + 8007582: f8cd a038 str.w sl, [sp, #56] ; 0x38 + 8007586: 9307 str r3, [sp, #28] + 8007588: 9b06 ldr r3, [sp, #24] + 800758a: 2b09 cmp r3, #9 + 800758c: f200 8090 bhi.w 80076b0 <_dtoa_r+0x2d8> + 8007590: 2b05 cmp r3, #5 + 8007592: bfc4 itt gt + 8007594: 3b04 subgt r3, #4 + 8007596: 9306 strgt r3, [sp, #24] + 8007598: 9b06 ldr r3, [sp, #24] + 800759a: f1a3 0302 sub.w r3, r3, #2 + 800759e: bfcc ite gt + 80075a0: 2500 movgt r5, #0 + 80075a2: 2501 movle r5, #1 + 80075a4: 2b03 cmp r3, #3 + 80075a6: f200 808f bhi.w 80076c8 <_dtoa_r+0x2f0> + 80075aa: e8df f003 tbb [pc, r3] + 80075ae: 7f7d .short 0x7f7d + 80075b0: 7131 .short 0x7131 + 80075b2: e9dd 5314 ldrd r5, r3, [sp, #80] ; 0x50 + 80075b6: 441d add r5, r3 + 80075b8: f205 4032 addw r0, r5, #1074 ; 0x432 + 80075bc: 2820 cmp r0, #32 + 80075be: dd13 ble.n 80075e8 <_dtoa_r+0x210> + 80075c0: f1c0 0040 rsb r0, r0, #64 ; 0x40 + 80075c4: 9b00 ldr r3, [sp, #0] + 80075c6: fa08 f800 lsl.w r8, r8, r0 + 80075ca: f205 4012 addw r0, r5, #1042 ; 0x412 + 80075ce: fa23 f000 lsr.w r0, r3, r0 + 80075d2: ea48 0000 orr.w r0, r8, r0 + 80075d6: f7f8 ff9d bl 8000514 <__aeabi_ui2d> + 80075da: 2301 movs r3, #1 + 80075dc: 4682 mov sl, r0 + 80075de: f1a1 7bf8 sub.w fp, r1, #32505856 ; 0x1f00000 + 80075e2: 3d01 subs r5, #1 + 80075e4: 9313 str r3, [sp, #76] ; 0x4c + 80075e6: e772 b.n 80074ce <_dtoa_r+0xf6> + 80075e8: 9b00 ldr r3, [sp, #0] + 80075ea: f1c0 0020 rsb r0, r0, #32 + 80075ee: fa03 f000 lsl.w r0, r3, r0 + 80075f2: e7f0 b.n 80075d6 <_dtoa_r+0x1fe> + 80075f4: 2301 movs r3, #1 + 80075f6: e7b1 b.n 800755c <_dtoa_r+0x184> + 80075f8: 900f str r0, [sp, #60] ; 0x3c + 80075fa: e7b0 b.n 800755e <_dtoa_r+0x186> + 80075fc: 9b05 ldr r3, [sp, #20] + 80075fe: eba3 030a sub.w r3, r3, sl + 8007602: 9305 str r3, [sp, #20] + 8007604: f1ca 0300 rsb r3, sl, #0 + 8007608: 9307 str r3, [sp, #28] + 800760a: 2300 movs r3, #0 + 800760c: 930e str r3, [sp, #56] ; 0x38 + 800760e: e7bb b.n 8007588 <_dtoa_r+0x1b0> + 8007610: 2301 movs r3, #1 + 8007612: 930a str r3, [sp, #40] ; 0x28 + 8007614: 9b0b ldr r3, [sp, #44] ; 0x2c + 8007616: 2b00 cmp r3, #0 + 8007618: dd59 ble.n 80076ce <_dtoa_r+0x2f6> + 800761a: 9302 str r3, [sp, #8] + 800761c: 4699 mov r9, r3 + 800761e: 6a66 ldr r6, [r4, #36] ; 0x24 + 8007620: 2200 movs r2, #0 + 8007622: 6072 str r2, [r6, #4] + 8007624: 2204 movs r2, #4 + 8007626: f102 0014 add.w r0, r2, #20 + 800762a: 4298 cmp r0, r3 + 800762c: 6871 ldr r1, [r6, #4] + 800762e: d953 bls.n 80076d8 <_dtoa_r+0x300> + 8007630: 4620 mov r0, r4 + 8007632: f001 f9c0 bl 80089b6 <_Balloc> + 8007636: 6a63 ldr r3, [r4, #36] ; 0x24 + 8007638: 6030 str r0, [r6, #0] + 800763a: f1b9 0f0e cmp.w r9, #14 + 800763e: f8d3 b000 ldr.w fp, [r3] + 8007642: f200 80e6 bhi.w 8007812 <_dtoa_r+0x43a> + 8007646: 2d00 cmp r5, #0 + 8007648: f000 80e3 beq.w 8007812 <_dtoa_r+0x43a> + 800764c: ed9d 7b00 vldr d7, [sp] + 8007650: f1ba 0f00 cmp.w sl, #0 + 8007654: ed8d 7b10 vstr d7, [sp, #64] ; 0x40 + 8007658: dd74 ble.n 8007744 <_dtoa_r+0x36c> + 800765a: 4a2a ldr r2, [pc, #168] ; (8007704 <_dtoa_r+0x32c>) + 800765c: f00a 030f and.w r3, sl, #15 + 8007660: eb02 03c3 add.w r3, r2, r3, lsl #3 + 8007664: ed93 7b00 vldr d7, [r3] + 8007668: ea4f 162a mov.w r6, sl, asr #4 + 800766c: 06f0 lsls r0, r6, #27 + 800766e: ed8d 7b08 vstr d7, [sp, #32] + 8007672: d565 bpl.n 8007740 <_dtoa_r+0x368> + 8007674: 4b24 ldr r3, [pc, #144] ; (8007708 <_dtoa_r+0x330>) + 8007676: e9dd 0110 ldrd r0, r1, [sp, #64] ; 0x40 + 800767a: e9d3 2308 ldrd r2, r3, [r3, #32] + 800767e: f7f9 f8ed bl 800085c <__aeabi_ddiv> + 8007682: e9cd 0100 strd r0, r1, [sp] + 8007686: f006 060f and.w r6, r6, #15 + 800768a: 2503 movs r5, #3 + 800768c: 4f1e ldr r7, [pc, #120] ; (8007708 <_dtoa_r+0x330>) + 800768e: e04c b.n 800772a <_dtoa_r+0x352> + 8007690: 2301 movs r3, #1 + 8007692: 930a str r3, [sp, #40] ; 0x28 + 8007694: 9b0b ldr r3, [sp, #44] ; 0x2c + 8007696: 4453 add r3, sl + 8007698: f103 0901 add.w r9, r3, #1 + 800769c: 9302 str r3, [sp, #8] + 800769e: 464b mov r3, r9 + 80076a0: 2b01 cmp r3, #1 + 80076a2: bfb8 it lt + 80076a4: 2301 movlt r3, #1 + 80076a6: e7ba b.n 800761e <_dtoa_r+0x246> + 80076a8: 2300 movs r3, #0 + 80076aa: e7b2 b.n 8007612 <_dtoa_r+0x23a> + 80076ac: 2300 movs r3, #0 + 80076ae: e7f0 b.n 8007692 <_dtoa_r+0x2ba> + 80076b0: 2501 movs r5, #1 + 80076b2: 2300 movs r3, #0 + 80076b4: 9306 str r3, [sp, #24] + 80076b6: 950a str r5, [sp, #40] ; 0x28 + 80076b8: f04f 33ff mov.w r3, #4294967295 + 80076bc: 9302 str r3, [sp, #8] + 80076be: 4699 mov r9, r3 + 80076c0: 2200 movs r2, #0 + 80076c2: 2312 movs r3, #18 + 80076c4: 920b str r2, [sp, #44] ; 0x2c + 80076c6: e7aa b.n 800761e <_dtoa_r+0x246> + 80076c8: 2301 movs r3, #1 + 80076ca: 930a str r3, [sp, #40] ; 0x28 + 80076cc: e7f4 b.n 80076b8 <_dtoa_r+0x2e0> + 80076ce: 2301 movs r3, #1 + 80076d0: 9302 str r3, [sp, #8] + 80076d2: 4699 mov r9, r3 + 80076d4: 461a mov r2, r3 + 80076d6: e7f5 b.n 80076c4 <_dtoa_r+0x2ec> + 80076d8: 3101 adds r1, #1 + 80076da: 6071 str r1, [r6, #4] + 80076dc: 0052 lsls r2, r2, #1 + 80076de: e7a2 b.n 8007626 <_dtoa_r+0x24e> + 80076e0: 636f4361 .word 0x636f4361 + 80076e4: 3fd287a7 .word 0x3fd287a7 + 80076e8: 8b60c8b3 .word 0x8b60c8b3 + 80076ec: 3fc68a28 .word 0x3fc68a28 + 80076f0: 509f79fb .word 0x509f79fb + 80076f4: 3fd34413 .word 0x3fd34413 + 80076f8: 7ff00000 .word 0x7ff00000 + 80076fc: 08009a4d .word 0x08009a4d + 8007700: 3ff80000 .word 0x3ff80000 + 8007704: 08009b68 .word 0x08009b68 + 8007708: 08009b40 .word 0x08009b40 + 800770c: 08009ad1 .word 0x08009ad1 + 8007710: 07f1 lsls r1, r6, #31 + 8007712: d508 bpl.n 8007726 <_dtoa_r+0x34e> + 8007714: e9dd 0108 ldrd r0, r1, [sp, #32] + 8007718: e9d7 2300 ldrd r2, r3, [r7] + 800771c: f7f8 ff74 bl 8000608 <__aeabi_dmul> + 8007720: e9cd 0108 strd r0, r1, [sp, #32] + 8007724: 3501 adds r5, #1 + 8007726: 1076 asrs r6, r6, #1 + 8007728: 3708 adds r7, #8 + 800772a: 2e00 cmp r6, #0 + 800772c: d1f0 bne.n 8007710 <_dtoa_r+0x338> + 800772e: e9dd 2308 ldrd r2, r3, [sp, #32] + 8007732: e9dd 0100 ldrd r0, r1, [sp] + 8007736: f7f9 f891 bl 800085c <__aeabi_ddiv> + 800773a: e9cd 0100 strd r0, r1, [sp] + 800773e: e01a b.n 8007776 <_dtoa_r+0x39e> + 8007740: 2502 movs r5, #2 + 8007742: e7a3 b.n 800768c <_dtoa_r+0x2b4> + 8007744: f000 80a0 beq.w 8007888 <_dtoa_r+0x4b0> + 8007748: f1ca 0600 rsb r6, sl, #0 + 800774c: 4b9f ldr r3, [pc, #636] ; (80079cc <_dtoa_r+0x5f4>) + 800774e: 4fa0 ldr r7, [pc, #640] ; (80079d0 <_dtoa_r+0x5f8>) + 8007750: f006 020f and.w r2, r6, #15 + 8007754: eb03 03c2 add.w r3, r3, r2, lsl #3 + 8007758: e9d3 2300 ldrd r2, r3, [r3] + 800775c: e9dd 0110 ldrd r0, r1, [sp, #64] ; 0x40 + 8007760: f7f8 ff52 bl 8000608 <__aeabi_dmul> + 8007764: e9cd 0100 strd r0, r1, [sp] + 8007768: 1136 asrs r6, r6, #4 + 800776a: 2300 movs r3, #0 + 800776c: 2502 movs r5, #2 + 800776e: 2e00 cmp r6, #0 + 8007770: d17f bne.n 8007872 <_dtoa_r+0x49a> + 8007772: 2b00 cmp r3, #0 + 8007774: d1e1 bne.n 800773a <_dtoa_r+0x362> + 8007776: 9b0f ldr r3, [sp, #60] ; 0x3c + 8007778: 2b00 cmp r3, #0 + 800777a: f000 8087 beq.w 800788c <_dtoa_r+0x4b4> + 800777e: e9dd 6700 ldrd r6, r7, [sp] + 8007782: 2200 movs r2, #0 + 8007784: 4b93 ldr r3, [pc, #588] ; (80079d4 <_dtoa_r+0x5fc>) + 8007786: 4630 mov r0, r6 + 8007788: 4639 mov r1, r7 + 800778a: f7f9 f9af bl 8000aec <__aeabi_dcmplt> + 800778e: 2800 cmp r0, #0 + 8007790: d07c beq.n 800788c <_dtoa_r+0x4b4> + 8007792: f1b9 0f00 cmp.w r9, #0 + 8007796: d079 beq.n 800788c <_dtoa_r+0x4b4> + 8007798: 9b02 ldr r3, [sp, #8] + 800779a: 2b00 cmp r3, #0 + 800779c: dd35 ble.n 800780a <_dtoa_r+0x432> + 800779e: f10a 33ff add.w r3, sl, #4294967295 + 80077a2: 9308 str r3, [sp, #32] + 80077a4: 4639 mov r1, r7 + 80077a6: 2200 movs r2, #0 + 80077a8: 4b8b ldr r3, [pc, #556] ; (80079d8 <_dtoa_r+0x600>) + 80077aa: 4630 mov r0, r6 + 80077ac: f7f8 ff2c bl 8000608 <__aeabi_dmul> + 80077b0: e9cd 0100 strd r0, r1, [sp] + 80077b4: 9f02 ldr r7, [sp, #8] + 80077b6: 3501 adds r5, #1 + 80077b8: 4628 mov r0, r5 + 80077ba: f7f8 febb bl 8000534 <__aeabi_i2d> + 80077be: e9dd 2300 ldrd r2, r3, [sp] + 80077c2: f7f8 ff21 bl 8000608 <__aeabi_dmul> + 80077c6: 2200 movs r2, #0 + 80077c8: 4b84 ldr r3, [pc, #528] ; (80079dc <_dtoa_r+0x604>) + 80077ca: f7f8 fd67 bl 800029c <__adddf3> + 80077ce: 4605 mov r5, r0 + 80077d0: f1a1 7650 sub.w r6, r1, #54525952 ; 0x3400000 + 80077d4: 2f00 cmp r7, #0 + 80077d6: d15d bne.n 8007894 <_dtoa_r+0x4bc> + 80077d8: 2200 movs r2, #0 + 80077da: 4b81 ldr r3, [pc, #516] ; (80079e0 <_dtoa_r+0x608>) + 80077dc: e9dd 0100 ldrd r0, r1, [sp] + 80077e0: f7f8 fd5a bl 8000298 <__aeabi_dsub> + 80077e4: 462a mov r2, r5 + 80077e6: 4633 mov r3, r6 + 80077e8: e9cd 0100 strd r0, r1, [sp] + 80077ec: f7f9 f99c bl 8000b28 <__aeabi_dcmpgt> + 80077f0: 2800 cmp r0, #0 + 80077f2: f040 8288 bne.w 8007d06 <_dtoa_r+0x92e> + 80077f6: 462a mov r2, r5 + 80077f8: f106 4300 add.w r3, r6, #2147483648 ; 0x80000000 + 80077fc: e9dd 0100 ldrd r0, r1, [sp] + 8007800: f7f9 f974 bl 8000aec <__aeabi_dcmplt> + 8007804: 2800 cmp r0, #0 + 8007806: f040 827c bne.w 8007d02 <_dtoa_r+0x92a> + 800780a: e9dd 2310 ldrd r2, r3, [sp, #64] ; 0x40 + 800780e: e9cd 2300 strd r2, r3, [sp] + 8007812: 9b15 ldr r3, [sp, #84] ; 0x54 + 8007814: 2b00 cmp r3, #0 + 8007816: f2c0 8150 blt.w 8007aba <_dtoa_r+0x6e2> + 800781a: f1ba 0f0e cmp.w sl, #14 + 800781e: f300 814c bgt.w 8007aba <_dtoa_r+0x6e2> + 8007822: 4b6a ldr r3, [pc, #424] ; (80079cc <_dtoa_r+0x5f4>) + 8007824: eb03 03ca add.w r3, r3, sl, lsl #3 + 8007828: ed93 7b00 vldr d7, [r3] + 800782c: 9b0b ldr r3, [sp, #44] ; 0x2c + 800782e: 2b00 cmp r3, #0 + 8007830: ed8d 7b02 vstr d7, [sp, #8] + 8007834: f280 80d8 bge.w 80079e8 <_dtoa_r+0x610> + 8007838: f1b9 0f00 cmp.w r9, #0 + 800783c: f300 80d4 bgt.w 80079e8 <_dtoa_r+0x610> + 8007840: f040 825e bne.w 8007d00 <_dtoa_r+0x928> + 8007844: 2200 movs r2, #0 + 8007846: 4b66 ldr r3, [pc, #408] ; (80079e0 <_dtoa_r+0x608>) + 8007848: ec51 0b17 vmov r0, r1, d7 + 800784c: f7f8 fedc bl 8000608 <__aeabi_dmul> + 8007850: e9dd 2300 ldrd r2, r3, [sp] + 8007854: f7f9 f95e bl 8000b14 <__aeabi_dcmpge> + 8007858: 464f mov r7, r9 + 800785a: 464e mov r6, r9 + 800785c: 2800 cmp r0, #0 + 800785e: f040 8234 bne.w 8007cca <_dtoa_r+0x8f2> + 8007862: 2331 movs r3, #49 ; 0x31 + 8007864: f10b 0501 add.w r5, fp, #1 + 8007868: f88b 3000 strb.w r3, [fp] + 800786c: f10a 0a01 add.w sl, sl, #1 + 8007870: e22f b.n 8007cd2 <_dtoa_r+0x8fa> + 8007872: 07f2 lsls r2, r6, #31 + 8007874: d505 bpl.n 8007882 <_dtoa_r+0x4aa> + 8007876: e9d7 2300 ldrd r2, r3, [r7] + 800787a: f7f8 fec5 bl 8000608 <__aeabi_dmul> + 800787e: 3501 adds r5, #1 + 8007880: 2301 movs r3, #1 + 8007882: 1076 asrs r6, r6, #1 + 8007884: 3708 adds r7, #8 + 8007886: e772 b.n 800776e <_dtoa_r+0x396> + 8007888: 2502 movs r5, #2 + 800788a: e774 b.n 8007776 <_dtoa_r+0x39e> + 800788c: f8cd a020 str.w sl, [sp, #32] + 8007890: 464f mov r7, r9 + 8007892: e791 b.n 80077b8 <_dtoa_r+0x3e0> + 8007894: 4b4d ldr r3, [pc, #308] ; (80079cc <_dtoa_r+0x5f4>) + 8007896: eb03 03c7 add.w r3, r3, r7, lsl #3 + 800789a: e953 0102 ldrd r0, r1, [r3, #-8] + 800789e: 9b0a ldr r3, [sp, #40] ; 0x28 + 80078a0: 2b00 cmp r3, #0 + 80078a2: d047 beq.n 8007934 <_dtoa_r+0x55c> + 80078a4: 4602 mov r2, r0 + 80078a6: 460b mov r3, r1 + 80078a8: 2000 movs r0, #0 + 80078aa: 494e ldr r1, [pc, #312] ; (80079e4 <_dtoa_r+0x60c>) + 80078ac: f7f8 ffd6 bl 800085c <__aeabi_ddiv> + 80078b0: 462a mov r2, r5 + 80078b2: 4633 mov r3, r6 + 80078b4: f7f8 fcf0 bl 8000298 <__aeabi_dsub> + 80078b8: e9cd 010c strd r0, r1, [sp, #48] ; 0x30 + 80078bc: 465d mov r5, fp + 80078be: e9dd 0100 ldrd r0, r1, [sp] + 80078c2: f7f9 f951 bl 8000b68 <__aeabi_d2iz> + 80078c6: 4606 mov r6, r0 + 80078c8: f7f8 fe34 bl 8000534 <__aeabi_i2d> + 80078cc: 4602 mov r2, r0 + 80078ce: 460b mov r3, r1 + 80078d0: e9dd 0100 ldrd r0, r1, [sp] + 80078d4: f7f8 fce0 bl 8000298 <__aeabi_dsub> + 80078d8: 3630 adds r6, #48 ; 0x30 + 80078da: f805 6b01 strb.w r6, [r5], #1 + 80078de: e9dd 230c ldrd r2, r3, [sp, #48] ; 0x30 + 80078e2: e9cd 0100 strd r0, r1, [sp] + 80078e6: f7f9 f901 bl 8000aec <__aeabi_dcmplt> + 80078ea: 2800 cmp r0, #0 + 80078ec: d163 bne.n 80079b6 <_dtoa_r+0x5de> + 80078ee: e9dd 2300 ldrd r2, r3, [sp] + 80078f2: 2000 movs r0, #0 + 80078f4: 4937 ldr r1, [pc, #220] ; (80079d4 <_dtoa_r+0x5fc>) + 80078f6: f7f8 fccf bl 8000298 <__aeabi_dsub> + 80078fa: e9dd 230c ldrd r2, r3, [sp, #48] ; 0x30 + 80078fe: f7f9 f8f5 bl 8000aec <__aeabi_dcmplt> + 8007902: 2800 cmp r0, #0 + 8007904: f040 80b7 bne.w 8007a76 <_dtoa_r+0x69e> + 8007908: eba5 030b sub.w r3, r5, fp + 800790c: 429f cmp r7, r3 + 800790e: f77f af7c ble.w 800780a <_dtoa_r+0x432> + 8007912: 2200 movs r2, #0 + 8007914: 4b30 ldr r3, [pc, #192] ; (80079d8 <_dtoa_r+0x600>) + 8007916: e9dd 010c ldrd r0, r1, [sp, #48] ; 0x30 + 800791a: f7f8 fe75 bl 8000608 <__aeabi_dmul> + 800791e: 2200 movs r2, #0 + 8007920: e9cd 010c strd r0, r1, [sp, #48] ; 0x30 + 8007924: 4b2c ldr r3, [pc, #176] ; (80079d8 <_dtoa_r+0x600>) + 8007926: e9dd 0100 ldrd r0, r1, [sp] + 800792a: f7f8 fe6d bl 8000608 <__aeabi_dmul> + 800792e: e9cd 0100 strd r0, r1, [sp] + 8007932: e7c4 b.n 80078be <_dtoa_r+0x4e6> + 8007934: 462a mov r2, r5 + 8007936: 4633 mov r3, r6 + 8007938: f7f8 fe66 bl 8000608 <__aeabi_dmul> + 800793c: e9cd 010c strd r0, r1, [sp, #48] ; 0x30 + 8007940: eb0b 0507 add.w r5, fp, r7 + 8007944: 465e mov r6, fp + 8007946: e9dd 0100 ldrd r0, r1, [sp] + 800794a: f7f9 f90d bl 8000b68 <__aeabi_d2iz> + 800794e: 4607 mov r7, r0 + 8007950: f7f8 fdf0 bl 8000534 <__aeabi_i2d> + 8007954: 3730 adds r7, #48 ; 0x30 + 8007956: 4602 mov r2, r0 + 8007958: 460b mov r3, r1 + 800795a: e9dd 0100 ldrd r0, r1, [sp] + 800795e: f7f8 fc9b bl 8000298 <__aeabi_dsub> + 8007962: f806 7b01 strb.w r7, [r6], #1 + 8007966: 42ae cmp r6, r5 + 8007968: e9cd 0100 strd r0, r1, [sp] + 800796c: f04f 0200 mov.w r2, #0 + 8007970: d126 bne.n 80079c0 <_dtoa_r+0x5e8> + 8007972: 4b1c ldr r3, [pc, #112] ; (80079e4 <_dtoa_r+0x60c>) + 8007974: e9dd 010c ldrd r0, r1, [sp, #48] ; 0x30 + 8007978: f7f8 fc90 bl 800029c <__adddf3> + 800797c: 4602 mov r2, r0 + 800797e: 460b mov r3, r1 + 8007980: e9dd 0100 ldrd r0, r1, [sp] + 8007984: f7f9 f8d0 bl 8000b28 <__aeabi_dcmpgt> + 8007988: 2800 cmp r0, #0 + 800798a: d174 bne.n 8007a76 <_dtoa_r+0x69e> + 800798c: e9dd 230c ldrd r2, r3, [sp, #48] ; 0x30 + 8007990: 2000 movs r0, #0 + 8007992: 4914 ldr r1, [pc, #80] ; (80079e4 <_dtoa_r+0x60c>) + 8007994: f7f8 fc80 bl 8000298 <__aeabi_dsub> + 8007998: 4602 mov r2, r0 + 800799a: 460b mov r3, r1 + 800799c: e9dd 0100 ldrd r0, r1, [sp] + 80079a0: f7f9 f8a4 bl 8000aec <__aeabi_dcmplt> + 80079a4: 2800 cmp r0, #0 + 80079a6: f43f af30 beq.w 800780a <_dtoa_r+0x432> + 80079aa: f815 3c01 ldrb.w r3, [r5, #-1] + 80079ae: 2b30 cmp r3, #48 ; 0x30 + 80079b0: f105 32ff add.w r2, r5, #4294967295 + 80079b4: d002 beq.n 80079bc <_dtoa_r+0x5e4> + 80079b6: f8dd a020 ldr.w sl, [sp, #32] + 80079ba: e04a b.n 8007a52 <_dtoa_r+0x67a> + 80079bc: 4615 mov r5, r2 + 80079be: e7f4 b.n 80079aa <_dtoa_r+0x5d2> + 80079c0: 4b05 ldr r3, [pc, #20] ; (80079d8 <_dtoa_r+0x600>) + 80079c2: f7f8 fe21 bl 8000608 <__aeabi_dmul> + 80079c6: e9cd 0100 strd r0, r1, [sp] + 80079ca: e7bc b.n 8007946 <_dtoa_r+0x56e> + 80079cc: 08009b68 .word 0x08009b68 + 80079d0: 08009b40 .word 0x08009b40 + 80079d4: 3ff00000 .word 0x3ff00000 + 80079d8: 40240000 .word 0x40240000 + 80079dc: 401c0000 .word 0x401c0000 + 80079e0: 40140000 .word 0x40140000 + 80079e4: 3fe00000 .word 0x3fe00000 + 80079e8: e9dd 6700 ldrd r6, r7, [sp] + 80079ec: 465d mov r5, fp + 80079ee: e9dd 2302 ldrd r2, r3, [sp, #8] + 80079f2: 4630 mov r0, r6 + 80079f4: 4639 mov r1, r7 + 80079f6: f7f8 ff31 bl 800085c <__aeabi_ddiv> + 80079fa: f7f9 f8b5 bl 8000b68 <__aeabi_d2iz> + 80079fe: 4680 mov r8, r0 + 8007a00: f7f8 fd98 bl 8000534 <__aeabi_i2d> + 8007a04: e9dd 2302 ldrd r2, r3, [sp, #8] + 8007a08: f7f8 fdfe bl 8000608 <__aeabi_dmul> + 8007a0c: 4602 mov r2, r0 + 8007a0e: 460b mov r3, r1 + 8007a10: 4630 mov r0, r6 + 8007a12: 4639 mov r1, r7 + 8007a14: f108 0630 add.w r6, r8, #48 ; 0x30 + 8007a18: f7f8 fc3e bl 8000298 <__aeabi_dsub> + 8007a1c: f805 6b01 strb.w r6, [r5], #1 + 8007a20: eba5 060b sub.w r6, r5, fp + 8007a24: 45b1 cmp r9, r6 + 8007a26: 4602 mov r2, r0 + 8007a28: 460b mov r3, r1 + 8007a2a: d139 bne.n 8007aa0 <_dtoa_r+0x6c8> + 8007a2c: f7f8 fc36 bl 800029c <__adddf3> + 8007a30: e9dd 2302 ldrd r2, r3, [sp, #8] + 8007a34: 4606 mov r6, r0 + 8007a36: 460f mov r7, r1 + 8007a38: f7f9 f876 bl 8000b28 <__aeabi_dcmpgt> + 8007a3c: b9c8 cbnz r0, 8007a72 <_dtoa_r+0x69a> + 8007a3e: e9dd 2302 ldrd r2, r3, [sp, #8] + 8007a42: 4630 mov r0, r6 + 8007a44: 4639 mov r1, r7 + 8007a46: f7f9 f847 bl 8000ad8 <__aeabi_dcmpeq> + 8007a4a: b110 cbz r0, 8007a52 <_dtoa_r+0x67a> + 8007a4c: f018 0f01 tst.w r8, #1 + 8007a50: d10f bne.n 8007a72 <_dtoa_r+0x69a> + 8007a52: 9904 ldr r1, [sp, #16] + 8007a54: 4620 mov r0, r4 + 8007a56: f000 ffe2 bl 8008a1e <_Bfree> + 8007a5a: 2300 movs r3, #0 + 8007a5c: 9a12 ldr r2, [sp, #72] ; 0x48 + 8007a5e: 702b strb r3, [r5, #0] + 8007a60: f10a 0301 add.w r3, sl, #1 + 8007a64: 6013 str r3, [r2, #0] + 8007a66: 9b21 ldr r3, [sp, #132] ; 0x84 + 8007a68: 2b00 cmp r3, #0 + 8007a6a: f000 8241 beq.w 8007ef0 <_dtoa_r+0xb18> + 8007a6e: 601d str r5, [r3, #0] + 8007a70: e23e b.n 8007ef0 <_dtoa_r+0xb18> + 8007a72: f8cd a020 str.w sl, [sp, #32] + 8007a76: f815 2c01 ldrb.w r2, [r5, #-1] + 8007a7a: 2a39 cmp r2, #57 ; 0x39 + 8007a7c: f105 33ff add.w r3, r5, #4294967295 + 8007a80: d108 bne.n 8007a94 <_dtoa_r+0x6bc> + 8007a82: 459b cmp fp, r3 + 8007a84: d10a bne.n 8007a9c <_dtoa_r+0x6c4> + 8007a86: 9b08 ldr r3, [sp, #32] + 8007a88: 3301 adds r3, #1 + 8007a8a: 9308 str r3, [sp, #32] + 8007a8c: 2330 movs r3, #48 ; 0x30 + 8007a8e: f88b 3000 strb.w r3, [fp] + 8007a92: 465b mov r3, fp + 8007a94: 781a ldrb r2, [r3, #0] + 8007a96: 3201 adds r2, #1 + 8007a98: 701a strb r2, [r3, #0] + 8007a9a: e78c b.n 80079b6 <_dtoa_r+0x5de> + 8007a9c: 461d mov r5, r3 + 8007a9e: e7ea b.n 8007a76 <_dtoa_r+0x69e> + 8007aa0: 2200 movs r2, #0 + 8007aa2: 4b9b ldr r3, [pc, #620] ; (8007d10 <_dtoa_r+0x938>) + 8007aa4: f7f8 fdb0 bl 8000608 <__aeabi_dmul> + 8007aa8: 2200 movs r2, #0 + 8007aaa: 2300 movs r3, #0 + 8007aac: 4606 mov r6, r0 + 8007aae: 460f mov r7, r1 + 8007ab0: f7f9 f812 bl 8000ad8 <__aeabi_dcmpeq> + 8007ab4: 2800 cmp r0, #0 + 8007ab6: d09a beq.n 80079ee <_dtoa_r+0x616> + 8007ab8: e7cb b.n 8007a52 <_dtoa_r+0x67a> + 8007aba: 9a0a ldr r2, [sp, #40] ; 0x28 + 8007abc: 2a00 cmp r2, #0 + 8007abe: f000 808b beq.w 8007bd8 <_dtoa_r+0x800> + 8007ac2: 9a06 ldr r2, [sp, #24] + 8007ac4: 2a01 cmp r2, #1 + 8007ac6: dc6e bgt.n 8007ba6 <_dtoa_r+0x7ce> + 8007ac8: 9a13 ldr r2, [sp, #76] ; 0x4c + 8007aca: 2a00 cmp r2, #0 + 8007acc: d067 beq.n 8007b9e <_dtoa_r+0x7c6> + 8007ace: f203 4333 addw r3, r3, #1075 ; 0x433 + 8007ad2: 9f07 ldr r7, [sp, #28] + 8007ad4: 9d05 ldr r5, [sp, #20] + 8007ad6: 9a05 ldr r2, [sp, #20] + 8007ad8: 2101 movs r1, #1 + 8007ada: 441a add r2, r3 + 8007adc: 4620 mov r0, r4 + 8007ade: 9205 str r2, [sp, #20] + 8007ae0: 4498 add r8, r3 + 8007ae2: f001 f87a bl 8008bda <__i2b> + 8007ae6: 4606 mov r6, r0 + 8007ae8: 2d00 cmp r5, #0 + 8007aea: dd0c ble.n 8007b06 <_dtoa_r+0x72e> + 8007aec: f1b8 0f00 cmp.w r8, #0 + 8007af0: dd09 ble.n 8007b06 <_dtoa_r+0x72e> + 8007af2: 4545 cmp r5, r8 + 8007af4: 9a05 ldr r2, [sp, #20] + 8007af6: 462b mov r3, r5 + 8007af8: bfa8 it ge + 8007afa: 4643 movge r3, r8 + 8007afc: 1ad2 subs r2, r2, r3 + 8007afe: 9205 str r2, [sp, #20] + 8007b00: 1aed subs r5, r5, r3 + 8007b02: eba8 0803 sub.w r8, r8, r3 + 8007b06: 9b07 ldr r3, [sp, #28] + 8007b08: b1eb cbz r3, 8007b46 <_dtoa_r+0x76e> + 8007b0a: 9b0a ldr r3, [sp, #40] ; 0x28 + 8007b0c: 2b00 cmp r3, #0 + 8007b0e: d067 beq.n 8007be0 <_dtoa_r+0x808> + 8007b10: b18f cbz r7, 8007b36 <_dtoa_r+0x75e> + 8007b12: 4631 mov r1, r6 + 8007b14: 463a mov r2, r7 + 8007b16: 4620 mov r0, r4 + 8007b18: f001 f8fe bl 8008d18 <__pow5mult> + 8007b1c: 9a04 ldr r2, [sp, #16] + 8007b1e: 4601 mov r1, r0 + 8007b20: 4606 mov r6, r0 + 8007b22: 4620 mov r0, r4 + 8007b24: f001 f862 bl 8008bec <__multiply> + 8007b28: 9904 ldr r1, [sp, #16] + 8007b2a: 9008 str r0, [sp, #32] + 8007b2c: 4620 mov r0, r4 + 8007b2e: f000 ff76 bl 8008a1e <_Bfree> + 8007b32: 9b08 ldr r3, [sp, #32] + 8007b34: 9304 str r3, [sp, #16] + 8007b36: 9b07 ldr r3, [sp, #28] + 8007b38: 1bda subs r2, r3, r7 + 8007b3a: d004 beq.n 8007b46 <_dtoa_r+0x76e> + 8007b3c: 9904 ldr r1, [sp, #16] + 8007b3e: 4620 mov r0, r4 + 8007b40: f001 f8ea bl 8008d18 <__pow5mult> + 8007b44: 9004 str r0, [sp, #16] + 8007b46: 2101 movs r1, #1 + 8007b48: 4620 mov r0, r4 + 8007b4a: f001 f846 bl 8008bda <__i2b> + 8007b4e: 9b0e ldr r3, [sp, #56] ; 0x38 + 8007b50: 4607 mov r7, r0 + 8007b52: 2b00 cmp r3, #0 + 8007b54: f000 81d0 beq.w 8007ef8 <_dtoa_r+0xb20> + 8007b58: 461a mov r2, r3 + 8007b5a: 4601 mov r1, r0 + 8007b5c: 4620 mov r0, r4 + 8007b5e: f001 f8db bl 8008d18 <__pow5mult> + 8007b62: 9b06 ldr r3, [sp, #24] + 8007b64: 2b01 cmp r3, #1 + 8007b66: 4607 mov r7, r0 + 8007b68: dc40 bgt.n 8007bec <_dtoa_r+0x814> + 8007b6a: 9b00 ldr r3, [sp, #0] + 8007b6c: 2b00 cmp r3, #0 + 8007b6e: d139 bne.n 8007be4 <_dtoa_r+0x80c> + 8007b70: 9b01 ldr r3, [sp, #4] + 8007b72: f3c3 0313 ubfx r3, r3, #0, #20 + 8007b76: 2b00 cmp r3, #0 + 8007b78: d136 bne.n 8007be8 <_dtoa_r+0x810> + 8007b7a: 9b01 ldr r3, [sp, #4] + 8007b7c: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000 + 8007b80: 0d1b lsrs r3, r3, #20 + 8007b82: 051b lsls r3, r3, #20 + 8007b84: b12b cbz r3, 8007b92 <_dtoa_r+0x7ba> + 8007b86: 9b05 ldr r3, [sp, #20] + 8007b88: 3301 adds r3, #1 + 8007b8a: 9305 str r3, [sp, #20] + 8007b8c: f108 0801 add.w r8, r8, #1 + 8007b90: 2301 movs r3, #1 + 8007b92: 9307 str r3, [sp, #28] + 8007b94: 9b0e ldr r3, [sp, #56] ; 0x38 + 8007b96: 2b00 cmp r3, #0 + 8007b98: d12a bne.n 8007bf0 <_dtoa_r+0x818> + 8007b9a: 2001 movs r0, #1 + 8007b9c: e030 b.n 8007c00 <_dtoa_r+0x828> + 8007b9e: 9b14 ldr r3, [sp, #80] ; 0x50 + 8007ba0: f1c3 0336 rsb r3, r3, #54 ; 0x36 + 8007ba4: e795 b.n 8007ad2 <_dtoa_r+0x6fa> + 8007ba6: 9b07 ldr r3, [sp, #28] + 8007ba8: f109 37ff add.w r7, r9, #4294967295 + 8007bac: 42bb cmp r3, r7 + 8007bae: bfbf itttt lt + 8007bb0: 9b07 ldrlt r3, [sp, #28] + 8007bb2: 9707 strlt r7, [sp, #28] + 8007bb4: 1afa sublt r2, r7, r3 + 8007bb6: 9b0e ldrlt r3, [sp, #56] ; 0x38 + 8007bb8: bfbb ittet lt + 8007bba: 189b addlt r3, r3, r2 + 8007bbc: 930e strlt r3, [sp, #56] ; 0x38 + 8007bbe: 1bdf subge r7, r3, r7 + 8007bc0: 2700 movlt r7, #0 + 8007bc2: f1b9 0f00 cmp.w r9, #0 + 8007bc6: bfb5 itete lt + 8007bc8: 9b05 ldrlt r3, [sp, #20] + 8007bca: 9d05 ldrge r5, [sp, #20] + 8007bcc: eba3 0509 sublt.w r5, r3, r9 + 8007bd0: 464b movge r3, r9 + 8007bd2: bfb8 it lt + 8007bd4: 2300 movlt r3, #0 + 8007bd6: e77e b.n 8007ad6 <_dtoa_r+0x6fe> + 8007bd8: 9f07 ldr r7, [sp, #28] + 8007bda: 9d05 ldr r5, [sp, #20] + 8007bdc: 9e0a ldr r6, [sp, #40] ; 0x28 + 8007bde: e783 b.n 8007ae8 <_dtoa_r+0x710> + 8007be0: 9a07 ldr r2, [sp, #28] + 8007be2: e7ab b.n 8007b3c <_dtoa_r+0x764> + 8007be4: 2300 movs r3, #0 + 8007be6: e7d4 b.n 8007b92 <_dtoa_r+0x7ba> + 8007be8: 9b00 ldr r3, [sp, #0] + 8007bea: e7d2 b.n 8007b92 <_dtoa_r+0x7ba> + 8007bec: 2300 movs r3, #0 + 8007bee: 9307 str r3, [sp, #28] + 8007bf0: 693b ldr r3, [r7, #16] + 8007bf2: eb07 0383 add.w r3, r7, r3, lsl #2 + 8007bf6: 6918 ldr r0, [r3, #16] + 8007bf8: f000 ffa1 bl 8008b3e <__hi0bits> + 8007bfc: f1c0 0020 rsb r0, r0, #32 + 8007c00: 4440 add r0, r8 + 8007c02: f010 001f ands.w r0, r0, #31 + 8007c06: d047 beq.n 8007c98 <_dtoa_r+0x8c0> + 8007c08: f1c0 0320 rsb r3, r0, #32 + 8007c0c: 2b04 cmp r3, #4 + 8007c0e: dd3b ble.n 8007c88 <_dtoa_r+0x8b0> + 8007c10: 9b05 ldr r3, [sp, #20] + 8007c12: f1c0 001c rsb r0, r0, #28 + 8007c16: 4403 add r3, r0 + 8007c18: 9305 str r3, [sp, #20] + 8007c1a: 4405 add r5, r0 + 8007c1c: 4480 add r8, r0 + 8007c1e: 9b05 ldr r3, [sp, #20] + 8007c20: 2b00 cmp r3, #0 + 8007c22: dd05 ble.n 8007c30 <_dtoa_r+0x858> + 8007c24: 461a mov r2, r3 + 8007c26: 9904 ldr r1, [sp, #16] + 8007c28: 4620 mov r0, r4 + 8007c2a: f001 f8c3 bl 8008db4 <__lshift> + 8007c2e: 9004 str r0, [sp, #16] + 8007c30: f1b8 0f00 cmp.w r8, #0 + 8007c34: dd05 ble.n 8007c42 <_dtoa_r+0x86a> + 8007c36: 4639 mov r1, r7 + 8007c38: 4642 mov r2, r8 + 8007c3a: 4620 mov r0, r4 + 8007c3c: f001 f8ba bl 8008db4 <__lshift> + 8007c40: 4607 mov r7, r0 + 8007c42: 9b0f ldr r3, [sp, #60] ; 0x3c + 8007c44: b353 cbz r3, 8007c9c <_dtoa_r+0x8c4> + 8007c46: 4639 mov r1, r7 + 8007c48: 9804 ldr r0, [sp, #16] + 8007c4a: f001 f907 bl 8008e5c <__mcmp> + 8007c4e: 2800 cmp r0, #0 + 8007c50: da24 bge.n 8007c9c <_dtoa_r+0x8c4> + 8007c52: 2300 movs r3, #0 + 8007c54: 220a movs r2, #10 + 8007c56: 9904 ldr r1, [sp, #16] + 8007c58: 4620 mov r0, r4 + 8007c5a: f000 fef7 bl 8008a4c <__multadd> + 8007c5e: 9b0a ldr r3, [sp, #40] ; 0x28 + 8007c60: 9004 str r0, [sp, #16] + 8007c62: f10a 3aff add.w sl, sl, #4294967295 + 8007c66: 2b00 cmp r3, #0 + 8007c68: f000 814d beq.w 8007f06 <_dtoa_r+0xb2e> + 8007c6c: 2300 movs r3, #0 + 8007c6e: 4631 mov r1, r6 + 8007c70: 220a movs r2, #10 + 8007c72: 4620 mov r0, r4 + 8007c74: f000 feea bl 8008a4c <__multadd> + 8007c78: 9b02 ldr r3, [sp, #8] + 8007c7a: 2b00 cmp r3, #0 + 8007c7c: 4606 mov r6, r0 + 8007c7e: dc4f bgt.n 8007d20 <_dtoa_r+0x948> + 8007c80: 9b06 ldr r3, [sp, #24] + 8007c82: 2b02 cmp r3, #2 + 8007c84: dd4c ble.n 8007d20 <_dtoa_r+0x948> + 8007c86: e011 b.n 8007cac <_dtoa_r+0x8d4> + 8007c88: d0c9 beq.n 8007c1e <_dtoa_r+0x846> + 8007c8a: 9a05 ldr r2, [sp, #20] + 8007c8c: 331c adds r3, #28 + 8007c8e: 441a add r2, r3 + 8007c90: 9205 str r2, [sp, #20] + 8007c92: 441d add r5, r3 + 8007c94: 4498 add r8, r3 + 8007c96: e7c2 b.n 8007c1e <_dtoa_r+0x846> + 8007c98: 4603 mov r3, r0 + 8007c9a: e7f6 b.n 8007c8a <_dtoa_r+0x8b2> + 8007c9c: f1b9 0f00 cmp.w r9, #0 + 8007ca0: dc38 bgt.n 8007d14 <_dtoa_r+0x93c> + 8007ca2: 9b06 ldr r3, [sp, #24] + 8007ca4: 2b02 cmp r3, #2 + 8007ca6: dd35 ble.n 8007d14 <_dtoa_r+0x93c> + 8007ca8: f8cd 9008 str.w r9, [sp, #8] + 8007cac: 9b02 ldr r3, [sp, #8] + 8007cae: b963 cbnz r3, 8007cca <_dtoa_r+0x8f2> + 8007cb0: 4639 mov r1, r7 + 8007cb2: 2205 movs r2, #5 + 8007cb4: 4620 mov r0, r4 + 8007cb6: f000 fec9 bl 8008a4c <__multadd> + 8007cba: 4601 mov r1, r0 + 8007cbc: 4607 mov r7, r0 + 8007cbe: 9804 ldr r0, [sp, #16] + 8007cc0: f001 f8cc bl 8008e5c <__mcmp> + 8007cc4: 2800 cmp r0, #0 + 8007cc6: f73f adcc bgt.w 8007862 <_dtoa_r+0x48a> + 8007cca: 9b0b ldr r3, [sp, #44] ; 0x2c + 8007ccc: 465d mov r5, fp + 8007cce: ea6f 0a03 mvn.w sl, r3 + 8007cd2: f04f 0900 mov.w r9, #0 + 8007cd6: 4639 mov r1, r7 + 8007cd8: 4620 mov r0, r4 + 8007cda: f000 fea0 bl 8008a1e <_Bfree> + 8007cde: 2e00 cmp r6, #0 + 8007ce0: f43f aeb7 beq.w 8007a52 <_dtoa_r+0x67a> + 8007ce4: f1b9 0f00 cmp.w r9, #0 + 8007ce8: d005 beq.n 8007cf6 <_dtoa_r+0x91e> + 8007cea: 45b1 cmp r9, r6 + 8007cec: d003 beq.n 8007cf6 <_dtoa_r+0x91e> + 8007cee: 4649 mov r1, r9 + 8007cf0: 4620 mov r0, r4 + 8007cf2: f000 fe94 bl 8008a1e <_Bfree> + 8007cf6: 4631 mov r1, r6 + 8007cf8: 4620 mov r0, r4 + 8007cfa: f000 fe90 bl 8008a1e <_Bfree> + 8007cfe: e6a8 b.n 8007a52 <_dtoa_r+0x67a> + 8007d00: 2700 movs r7, #0 + 8007d02: 463e mov r6, r7 + 8007d04: e7e1 b.n 8007cca <_dtoa_r+0x8f2> + 8007d06: f8dd a020 ldr.w sl, [sp, #32] + 8007d0a: 463e mov r6, r7 + 8007d0c: e5a9 b.n 8007862 <_dtoa_r+0x48a> + 8007d0e: bf00 nop + 8007d10: 40240000 .word 0x40240000 + 8007d14: 9b0a ldr r3, [sp, #40] ; 0x28 + 8007d16: f8cd 9008 str.w r9, [sp, #8] + 8007d1a: 2b00 cmp r3, #0 + 8007d1c: f000 80fa beq.w 8007f14 <_dtoa_r+0xb3c> + 8007d20: 2d00 cmp r5, #0 + 8007d22: dd05 ble.n 8007d30 <_dtoa_r+0x958> + 8007d24: 4631 mov r1, r6 + 8007d26: 462a mov r2, r5 + 8007d28: 4620 mov r0, r4 + 8007d2a: f001 f843 bl 8008db4 <__lshift> + 8007d2e: 4606 mov r6, r0 + 8007d30: 9b07 ldr r3, [sp, #28] + 8007d32: 2b00 cmp r3, #0 + 8007d34: d04c beq.n 8007dd0 <_dtoa_r+0x9f8> + 8007d36: 6871 ldr r1, [r6, #4] + 8007d38: 4620 mov r0, r4 + 8007d3a: f000 fe3c bl 80089b6 <_Balloc> + 8007d3e: 6932 ldr r2, [r6, #16] + 8007d40: 3202 adds r2, #2 + 8007d42: 4605 mov r5, r0 + 8007d44: 0092 lsls r2, r2, #2 + 8007d46: f106 010c add.w r1, r6, #12 + 8007d4a: 300c adds r0, #12 + 8007d4c: f000 fe26 bl 800899c + 8007d50: 2201 movs r2, #1 + 8007d52: 4629 mov r1, r5 + 8007d54: 4620 mov r0, r4 + 8007d56: f001 f82d bl 8008db4 <__lshift> + 8007d5a: 9b00 ldr r3, [sp, #0] + 8007d5c: f8cd b014 str.w fp, [sp, #20] + 8007d60: f003 0301 and.w r3, r3, #1 + 8007d64: 46b1 mov r9, r6 + 8007d66: 9307 str r3, [sp, #28] + 8007d68: 4606 mov r6, r0 + 8007d6a: 4639 mov r1, r7 + 8007d6c: 9804 ldr r0, [sp, #16] + 8007d6e: f7ff faa5 bl 80072bc + 8007d72: 4649 mov r1, r9 + 8007d74: 4605 mov r5, r0 + 8007d76: f100 0830 add.w r8, r0, #48 ; 0x30 + 8007d7a: 9804 ldr r0, [sp, #16] + 8007d7c: f001 f86e bl 8008e5c <__mcmp> + 8007d80: 4632 mov r2, r6 + 8007d82: 9000 str r0, [sp, #0] + 8007d84: 4639 mov r1, r7 + 8007d86: 4620 mov r0, r4 + 8007d88: f001 f882 bl 8008e90 <__mdiff> + 8007d8c: 68c3 ldr r3, [r0, #12] + 8007d8e: 4602 mov r2, r0 + 8007d90: bb03 cbnz r3, 8007dd4 <_dtoa_r+0x9fc> + 8007d92: 4601 mov r1, r0 + 8007d94: 9008 str r0, [sp, #32] + 8007d96: 9804 ldr r0, [sp, #16] + 8007d98: f001 f860 bl 8008e5c <__mcmp> + 8007d9c: 9a08 ldr r2, [sp, #32] + 8007d9e: 4603 mov r3, r0 + 8007da0: 4611 mov r1, r2 + 8007da2: 4620 mov r0, r4 + 8007da4: 9308 str r3, [sp, #32] + 8007da6: f000 fe3a bl 8008a1e <_Bfree> + 8007daa: 9b08 ldr r3, [sp, #32] + 8007dac: b9a3 cbnz r3, 8007dd8 <_dtoa_r+0xa00> + 8007dae: 9a06 ldr r2, [sp, #24] + 8007db0: b992 cbnz r2, 8007dd8 <_dtoa_r+0xa00> + 8007db2: 9a07 ldr r2, [sp, #28] + 8007db4: b982 cbnz r2, 8007dd8 <_dtoa_r+0xa00> + 8007db6: f1b8 0f39 cmp.w r8, #57 ; 0x39 + 8007dba: d029 beq.n 8007e10 <_dtoa_r+0xa38> + 8007dbc: 9b00 ldr r3, [sp, #0] + 8007dbe: 2b00 cmp r3, #0 + 8007dc0: dd01 ble.n 8007dc6 <_dtoa_r+0x9ee> + 8007dc2: f105 0831 add.w r8, r5, #49 ; 0x31 + 8007dc6: 9b05 ldr r3, [sp, #20] + 8007dc8: 1c5d adds r5, r3, #1 + 8007dca: f883 8000 strb.w r8, [r3] + 8007dce: e782 b.n 8007cd6 <_dtoa_r+0x8fe> + 8007dd0: 4630 mov r0, r6 + 8007dd2: e7c2 b.n 8007d5a <_dtoa_r+0x982> + 8007dd4: 2301 movs r3, #1 + 8007dd6: e7e3 b.n 8007da0 <_dtoa_r+0x9c8> + 8007dd8: 9a00 ldr r2, [sp, #0] + 8007dda: 2a00 cmp r2, #0 + 8007ddc: db04 blt.n 8007de8 <_dtoa_r+0xa10> + 8007dde: d125 bne.n 8007e2c <_dtoa_r+0xa54> + 8007de0: 9a06 ldr r2, [sp, #24] + 8007de2: bb1a cbnz r2, 8007e2c <_dtoa_r+0xa54> + 8007de4: 9a07 ldr r2, [sp, #28] + 8007de6: bb0a cbnz r2, 8007e2c <_dtoa_r+0xa54> + 8007de8: 2b00 cmp r3, #0 + 8007dea: ddec ble.n 8007dc6 <_dtoa_r+0x9ee> + 8007dec: 2201 movs r2, #1 + 8007dee: 9904 ldr r1, [sp, #16] + 8007df0: 4620 mov r0, r4 + 8007df2: f000 ffdf bl 8008db4 <__lshift> + 8007df6: 4639 mov r1, r7 + 8007df8: 9004 str r0, [sp, #16] + 8007dfa: f001 f82f bl 8008e5c <__mcmp> + 8007dfe: 2800 cmp r0, #0 + 8007e00: dc03 bgt.n 8007e0a <_dtoa_r+0xa32> + 8007e02: d1e0 bne.n 8007dc6 <_dtoa_r+0x9ee> + 8007e04: f018 0f01 tst.w r8, #1 + 8007e08: d0dd beq.n 8007dc6 <_dtoa_r+0x9ee> + 8007e0a: f1b8 0f39 cmp.w r8, #57 ; 0x39 + 8007e0e: d1d8 bne.n 8007dc2 <_dtoa_r+0x9ea> + 8007e10: 9b05 ldr r3, [sp, #20] + 8007e12: 9a05 ldr r2, [sp, #20] + 8007e14: 1c5d adds r5, r3, #1 + 8007e16: 2339 movs r3, #57 ; 0x39 + 8007e18: 7013 strb r3, [r2, #0] + 8007e1a: f815 3c01 ldrb.w r3, [r5, #-1] + 8007e1e: 2b39 cmp r3, #57 ; 0x39 + 8007e20: f105 32ff add.w r2, r5, #4294967295 + 8007e24: d04f beq.n 8007ec6 <_dtoa_r+0xaee> + 8007e26: 3301 adds r3, #1 + 8007e28: 7013 strb r3, [r2, #0] + 8007e2a: e754 b.n 8007cd6 <_dtoa_r+0x8fe> + 8007e2c: 9a05 ldr r2, [sp, #20] + 8007e2e: 2b00 cmp r3, #0 + 8007e30: f102 0501 add.w r5, r2, #1 + 8007e34: dd06 ble.n 8007e44 <_dtoa_r+0xa6c> + 8007e36: f1b8 0f39 cmp.w r8, #57 ; 0x39 + 8007e3a: d0e9 beq.n 8007e10 <_dtoa_r+0xa38> + 8007e3c: f108 0801 add.w r8, r8, #1 + 8007e40: 9b05 ldr r3, [sp, #20] + 8007e42: e7c2 b.n 8007dca <_dtoa_r+0x9f2> + 8007e44: 9a02 ldr r2, [sp, #8] + 8007e46: f805 8c01 strb.w r8, [r5, #-1] + 8007e4a: eba5 030b sub.w r3, r5, fp + 8007e4e: 4293 cmp r3, r2 + 8007e50: d021 beq.n 8007e96 <_dtoa_r+0xabe> + 8007e52: 2300 movs r3, #0 + 8007e54: 220a movs r2, #10 + 8007e56: 9904 ldr r1, [sp, #16] + 8007e58: 4620 mov r0, r4 + 8007e5a: f000 fdf7 bl 8008a4c <__multadd> + 8007e5e: 45b1 cmp r9, r6 + 8007e60: 9004 str r0, [sp, #16] + 8007e62: f04f 0300 mov.w r3, #0 + 8007e66: f04f 020a mov.w r2, #10 + 8007e6a: 4649 mov r1, r9 + 8007e6c: 4620 mov r0, r4 + 8007e6e: d105 bne.n 8007e7c <_dtoa_r+0xaa4> + 8007e70: f000 fdec bl 8008a4c <__multadd> + 8007e74: 4681 mov r9, r0 + 8007e76: 4606 mov r6, r0 + 8007e78: 9505 str r5, [sp, #20] + 8007e7a: e776 b.n 8007d6a <_dtoa_r+0x992> + 8007e7c: f000 fde6 bl 8008a4c <__multadd> + 8007e80: 4631 mov r1, r6 + 8007e82: 4681 mov r9, r0 + 8007e84: 2300 movs r3, #0 + 8007e86: 220a movs r2, #10 + 8007e88: 4620 mov r0, r4 + 8007e8a: f000 fddf bl 8008a4c <__multadd> + 8007e8e: 4606 mov r6, r0 + 8007e90: e7f2 b.n 8007e78 <_dtoa_r+0xaa0> + 8007e92: f04f 0900 mov.w r9, #0 + 8007e96: 2201 movs r2, #1 + 8007e98: 9904 ldr r1, [sp, #16] + 8007e9a: 4620 mov r0, r4 + 8007e9c: f000 ff8a bl 8008db4 <__lshift> + 8007ea0: 4639 mov r1, r7 + 8007ea2: 9004 str r0, [sp, #16] + 8007ea4: f000 ffda bl 8008e5c <__mcmp> + 8007ea8: 2800 cmp r0, #0 + 8007eaa: dcb6 bgt.n 8007e1a <_dtoa_r+0xa42> + 8007eac: d102 bne.n 8007eb4 <_dtoa_r+0xadc> + 8007eae: f018 0f01 tst.w r8, #1 + 8007eb2: d1b2 bne.n 8007e1a <_dtoa_r+0xa42> + 8007eb4: f815 3c01 ldrb.w r3, [r5, #-1] + 8007eb8: 2b30 cmp r3, #48 ; 0x30 + 8007eba: f105 32ff add.w r2, r5, #4294967295 + 8007ebe: f47f af0a bne.w 8007cd6 <_dtoa_r+0x8fe> + 8007ec2: 4615 mov r5, r2 + 8007ec4: e7f6 b.n 8007eb4 <_dtoa_r+0xadc> + 8007ec6: 4593 cmp fp, r2 + 8007ec8: d105 bne.n 8007ed6 <_dtoa_r+0xafe> + 8007eca: 2331 movs r3, #49 ; 0x31 + 8007ecc: f10a 0a01 add.w sl, sl, #1 + 8007ed0: f88b 3000 strb.w r3, [fp] + 8007ed4: e6ff b.n 8007cd6 <_dtoa_r+0x8fe> + 8007ed6: 4615 mov r5, r2 + 8007ed8: e79f b.n 8007e1a <_dtoa_r+0xa42> + 8007eda: f8df b064 ldr.w fp, [pc, #100] ; 8007f40 <_dtoa_r+0xb68> + 8007ede: e007 b.n 8007ef0 <_dtoa_r+0xb18> + 8007ee0: 9b21 ldr r3, [sp, #132] ; 0x84 + 8007ee2: f8df b060 ldr.w fp, [pc, #96] ; 8007f44 <_dtoa_r+0xb6c> + 8007ee6: b11b cbz r3, 8007ef0 <_dtoa_r+0xb18> + 8007ee8: f10b 0308 add.w r3, fp, #8 + 8007eec: 9a21 ldr r2, [sp, #132] ; 0x84 + 8007eee: 6013 str r3, [r2, #0] + 8007ef0: 4658 mov r0, fp + 8007ef2: b017 add sp, #92 ; 0x5c + 8007ef4: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 8007ef8: 9b06 ldr r3, [sp, #24] + 8007efa: 2b01 cmp r3, #1 + 8007efc: f77f ae35 ble.w 8007b6a <_dtoa_r+0x792> + 8007f00: 9b0e ldr r3, [sp, #56] ; 0x38 + 8007f02: 9307 str r3, [sp, #28] + 8007f04: e649 b.n 8007b9a <_dtoa_r+0x7c2> + 8007f06: 9b02 ldr r3, [sp, #8] + 8007f08: 2b00 cmp r3, #0 + 8007f0a: dc03 bgt.n 8007f14 <_dtoa_r+0xb3c> + 8007f0c: 9b06 ldr r3, [sp, #24] + 8007f0e: 2b02 cmp r3, #2 + 8007f10: f73f aecc bgt.w 8007cac <_dtoa_r+0x8d4> + 8007f14: 465d mov r5, fp + 8007f16: 4639 mov r1, r7 + 8007f18: 9804 ldr r0, [sp, #16] + 8007f1a: f7ff f9cf bl 80072bc + 8007f1e: f100 0830 add.w r8, r0, #48 ; 0x30 + 8007f22: f805 8b01 strb.w r8, [r5], #1 + 8007f26: 9a02 ldr r2, [sp, #8] + 8007f28: eba5 030b sub.w r3, r5, fp + 8007f2c: 429a cmp r2, r3 + 8007f2e: ddb0 ble.n 8007e92 <_dtoa_r+0xaba> + 8007f30: 2300 movs r3, #0 + 8007f32: 220a movs r2, #10 + 8007f34: 9904 ldr r1, [sp, #16] + 8007f36: 4620 mov r0, r4 + 8007f38: f000 fd88 bl 8008a4c <__multadd> + 8007f3c: 9004 str r0, [sp, #16] + 8007f3e: e7ea b.n 8007f16 <_dtoa_r+0xb3e> + 8007f40: 08009a4c .word 0x08009a4c + 8007f44: 08009ac8 .word 0x08009ac8 + +08007f48 <__sflush_r>: + 8007f48: 898a ldrh r2, [r1, #12] + 8007f4a: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 8007f4e: 4605 mov r5, r0 + 8007f50: 0710 lsls r0, r2, #28 + 8007f52: 460c mov r4, r1 + 8007f54: d458 bmi.n 8008008 <__sflush_r+0xc0> + 8007f56: 684b ldr r3, [r1, #4] + 8007f58: 2b00 cmp r3, #0 + 8007f5a: dc05 bgt.n 8007f68 <__sflush_r+0x20> + 8007f5c: 6c0b ldr r3, [r1, #64] ; 0x40 + 8007f5e: 2b00 cmp r3, #0 + 8007f60: dc02 bgt.n 8007f68 <__sflush_r+0x20> + 8007f62: 2000 movs r0, #0 + 8007f64: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 8007f68: 6ae6 ldr r6, [r4, #44] ; 0x2c + 8007f6a: 2e00 cmp r6, #0 + 8007f6c: d0f9 beq.n 8007f62 <__sflush_r+0x1a> + 8007f6e: 2300 movs r3, #0 + 8007f70: f412 5280 ands.w r2, r2, #4096 ; 0x1000 + 8007f74: 682f ldr r7, [r5, #0] + 8007f76: 6a21 ldr r1, [r4, #32] + 8007f78: 602b str r3, [r5, #0] + 8007f7a: d032 beq.n 8007fe2 <__sflush_r+0x9a> + 8007f7c: 6d60 ldr r0, [r4, #84] ; 0x54 + 8007f7e: 89a3 ldrh r3, [r4, #12] + 8007f80: 075a lsls r2, r3, #29 + 8007f82: d505 bpl.n 8007f90 <__sflush_r+0x48> + 8007f84: 6863 ldr r3, [r4, #4] + 8007f86: 1ac0 subs r0, r0, r3 + 8007f88: 6b63 ldr r3, [r4, #52] ; 0x34 + 8007f8a: b10b cbz r3, 8007f90 <__sflush_r+0x48> + 8007f8c: 6c23 ldr r3, [r4, #64] ; 0x40 + 8007f8e: 1ac0 subs r0, r0, r3 + 8007f90: 2300 movs r3, #0 + 8007f92: 4602 mov r2, r0 + 8007f94: 6ae6 ldr r6, [r4, #44] ; 0x2c + 8007f96: 6a21 ldr r1, [r4, #32] + 8007f98: 4628 mov r0, r5 + 8007f9a: 47b0 blx r6 + 8007f9c: 1c43 adds r3, r0, #1 + 8007f9e: 89a3 ldrh r3, [r4, #12] + 8007fa0: d106 bne.n 8007fb0 <__sflush_r+0x68> + 8007fa2: 6829 ldr r1, [r5, #0] + 8007fa4: 291d cmp r1, #29 + 8007fa6: d848 bhi.n 800803a <__sflush_r+0xf2> + 8007fa8: 4a29 ldr r2, [pc, #164] ; (8008050 <__sflush_r+0x108>) + 8007faa: 40ca lsrs r2, r1 + 8007fac: 07d6 lsls r6, r2, #31 + 8007fae: d544 bpl.n 800803a <__sflush_r+0xf2> + 8007fb0: 2200 movs r2, #0 + 8007fb2: 6062 str r2, [r4, #4] + 8007fb4: 04d9 lsls r1, r3, #19 + 8007fb6: 6922 ldr r2, [r4, #16] + 8007fb8: 6022 str r2, [r4, #0] + 8007fba: d504 bpl.n 8007fc6 <__sflush_r+0x7e> + 8007fbc: 1c42 adds r2, r0, #1 + 8007fbe: d101 bne.n 8007fc4 <__sflush_r+0x7c> + 8007fc0: 682b ldr r3, [r5, #0] + 8007fc2: b903 cbnz r3, 8007fc6 <__sflush_r+0x7e> + 8007fc4: 6560 str r0, [r4, #84] ; 0x54 + 8007fc6: 6b61 ldr r1, [r4, #52] ; 0x34 + 8007fc8: 602f str r7, [r5, #0] + 8007fca: 2900 cmp r1, #0 + 8007fcc: d0c9 beq.n 8007f62 <__sflush_r+0x1a> + 8007fce: f104 0344 add.w r3, r4, #68 ; 0x44 + 8007fd2: 4299 cmp r1, r3 + 8007fd4: d002 beq.n 8007fdc <__sflush_r+0x94> + 8007fd6: 4628 mov r0, r5 + 8007fd8: f7fd fa68 bl 80054ac <_free_r> + 8007fdc: 2000 movs r0, #0 + 8007fde: 6360 str r0, [r4, #52] ; 0x34 + 8007fe0: e7c0 b.n 8007f64 <__sflush_r+0x1c> + 8007fe2: 2301 movs r3, #1 + 8007fe4: 4628 mov r0, r5 + 8007fe6: 47b0 blx r6 + 8007fe8: 1c41 adds r1, r0, #1 + 8007fea: d1c8 bne.n 8007f7e <__sflush_r+0x36> + 8007fec: 682b ldr r3, [r5, #0] + 8007fee: 2b00 cmp r3, #0 + 8007ff0: d0c5 beq.n 8007f7e <__sflush_r+0x36> + 8007ff2: 2b1d cmp r3, #29 + 8007ff4: d001 beq.n 8007ffa <__sflush_r+0xb2> + 8007ff6: 2b16 cmp r3, #22 + 8007ff8: d101 bne.n 8007ffe <__sflush_r+0xb6> + 8007ffa: 602f str r7, [r5, #0] + 8007ffc: e7b1 b.n 8007f62 <__sflush_r+0x1a> + 8007ffe: 89a3 ldrh r3, [r4, #12] + 8008000: f043 0340 orr.w r3, r3, #64 ; 0x40 + 8008004: 81a3 strh r3, [r4, #12] + 8008006: e7ad b.n 8007f64 <__sflush_r+0x1c> + 8008008: 690f ldr r7, [r1, #16] + 800800a: 2f00 cmp r7, #0 + 800800c: d0a9 beq.n 8007f62 <__sflush_r+0x1a> + 800800e: 0793 lsls r3, r2, #30 + 8008010: 680e ldr r6, [r1, #0] + 8008012: bf08 it eq + 8008014: 694b ldreq r3, [r1, #20] + 8008016: 600f str r7, [r1, #0] + 8008018: bf18 it ne + 800801a: 2300 movne r3, #0 + 800801c: eba6 0807 sub.w r8, r6, r7 + 8008020: 608b str r3, [r1, #8] + 8008022: f1b8 0f00 cmp.w r8, #0 + 8008026: dd9c ble.n 8007f62 <__sflush_r+0x1a> + 8008028: 4643 mov r3, r8 + 800802a: 463a mov r2, r7 + 800802c: 6a21 ldr r1, [r4, #32] + 800802e: 6aa6 ldr r6, [r4, #40] ; 0x28 + 8008030: 4628 mov r0, r5 + 8008032: 47b0 blx r6 + 8008034: 2800 cmp r0, #0 + 8008036: dc06 bgt.n 8008046 <__sflush_r+0xfe> + 8008038: 89a3 ldrh r3, [r4, #12] + 800803a: f043 0340 orr.w r3, r3, #64 ; 0x40 + 800803e: 81a3 strh r3, [r4, #12] + 8008040: f04f 30ff mov.w r0, #4294967295 + 8008044: e78e b.n 8007f64 <__sflush_r+0x1c> + 8008046: 4407 add r7, r0 + 8008048: eba8 0800 sub.w r8, r8, r0 + 800804c: e7e9 b.n 8008022 <__sflush_r+0xda> + 800804e: bf00 nop + 8008050: 20400001 .word 0x20400001 + +08008054 <_fflush_r>: + 8008054: b538 push {r3, r4, r5, lr} + 8008056: 690b ldr r3, [r1, #16] + 8008058: 4605 mov r5, r0 + 800805a: 460c mov r4, r1 + 800805c: b1db cbz r3, 8008096 <_fflush_r+0x42> + 800805e: b118 cbz r0, 8008068 <_fflush_r+0x14> + 8008060: 6983 ldr r3, [r0, #24] + 8008062: b90b cbnz r3, 8008068 <_fflush_r+0x14> + 8008064: f000 f860 bl 8008128 <__sinit> + 8008068: 4b0c ldr r3, [pc, #48] ; (800809c <_fflush_r+0x48>) + 800806a: 429c cmp r4, r3 + 800806c: d109 bne.n 8008082 <_fflush_r+0x2e> + 800806e: 686c ldr r4, [r5, #4] + 8008070: f9b4 300c ldrsh.w r3, [r4, #12] + 8008074: b17b cbz r3, 8008096 <_fflush_r+0x42> + 8008076: 4621 mov r1, r4 + 8008078: 4628 mov r0, r5 + 800807a: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} + 800807e: f7ff bf63 b.w 8007f48 <__sflush_r> + 8008082: 4b07 ldr r3, [pc, #28] ; (80080a0 <_fflush_r+0x4c>) + 8008084: 429c cmp r4, r3 + 8008086: d101 bne.n 800808c <_fflush_r+0x38> + 8008088: 68ac ldr r4, [r5, #8] + 800808a: e7f1 b.n 8008070 <_fflush_r+0x1c> + 800808c: 4b05 ldr r3, [pc, #20] ; (80080a4 <_fflush_r+0x50>) + 800808e: 429c cmp r4, r3 + 8008090: bf08 it eq + 8008092: 68ec ldreq r4, [r5, #12] + 8008094: e7ec b.n 8008070 <_fflush_r+0x1c> + 8008096: 2000 movs r0, #0 + 8008098: bd38 pop {r3, r4, r5, pc} + 800809a: bf00 nop + 800809c: 08009af8 .word 0x08009af8 + 80080a0: 08009b18 .word 0x08009b18 + 80080a4: 08009ad8 .word 0x08009ad8 + +080080a8 : + 80080a8: 2300 movs r3, #0 + 80080aa: b510 push {r4, lr} + 80080ac: 4604 mov r4, r0 + 80080ae: e9c0 3300 strd r3, r3, [r0] + 80080b2: 6083 str r3, [r0, #8] + 80080b4: 8181 strh r1, [r0, #12] + 80080b6: 6643 str r3, [r0, #100] ; 0x64 + 80080b8: 81c2 strh r2, [r0, #14] + 80080ba: e9c0 3304 strd r3, r3, [r0, #16] + 80080be: 6183 str r3, [r0, #24] + 80080c0: 4619 mov r1, r3 + 80080c2: 2208 movs r2, #8 + 80080c4: 305c adds r0, #92 ; 0x5c + 80080c6: f7fd f9e9 bl 800549c + 80080ca: 4b05 ldr r3, [pc, #20] ; (80080e0 ) + 80080cc: 6263 str r3, [r4, #36] ; 0x24 + 80080ce: 4b05 ldr r3, [pc, #20] ; (80080e4 ) + 80080d0: 62a3 str r3, [r4, #40] ; 0x28 + 80080d2: 4b05 ldr r3, [pc, #20] ; (80080e8 ) + 80080d4: 62e3 str r3, [r4, #44] ; 0x2c + 80080d6: 4b05 ldr r3, [pc, #20] ; (80080ec ) + 80080d8: 6224 str r4, [r4, #32] + 80080da: 6323 str r3, [r4, #48] ; 0x30 + 80080dc: bd10 pop {r4, pc} + 80080de: bf00 nop + 80080e0: 080096f5 .word 0x080096f5 + 80080e4: 08009717 .word 0x08009717 + 80080e8: 0800974f .word 0x0800974f + 80080ec: 08009773 .word 0x08009773 + +080080f0 <_cleanup_r>: + 80080f0: 4901 ldr r1, [pc, #4] ; (80080f8 <_cleanup_r+0x8>) + 80080f2: f000 b885 b.w 8008200 <_fwalk_reent> + 80080f6: bf00 nop + 80080f8: 08008055 .word 0x08008055 + +080080fc <__sfmoreglue>: + 80080fc: b570 push {r4, r5, r6, lr} + 80080fe: 1e4a subs r2, r1, #1 + 8008100: 2568 movs r5, #104 ; 0x68 + 8008102: 4355 muls r5, r2 + 8008104: 460e mov r6, r1 + 8008106: f105 0174 add.w r1, r5, #116 ; 0x74 + 800810a: f7fd fa1d bl 8005548 <_malloc_r> + 800810e: 4604 mov r4, r0 + 8008110: b140 cbz r0, 8008124 <__sfmoreglue+0x28> + 8008112: 2100 movs r1, #0 + 8008114: e9c0 1600 strd r1, r6, [r0] + 8008118: 300c adds r0, #12 + 800811a: 60a0 str r0, [r4, #8] + 800811c: f105 0268 add.w r2, r5, #104 ; 0x68 + 8008120: f7fd f9bc bl 800549c + 8008124: 4620 mov r0, r4 + 8008126: bd70 pop {r4, r5, r6, pc} + +08008128 <__sinit>: + 8008128: 6983 ldr r3, [r0, #24] + 800812a: b510 push {r4, lr} + 800812c: 4604 mov r4, r0 + 800812e: bb33 cbnz r3, 800817e <__sinit+0x56> + 8008130: e9c0 3312 strd r3, r3, [r0, #72] ; 0x48 + 8008134: 6503 str r3, [r0, #80] ; 0x50 + 8008136: 4b12 ldr r3, [pc, #72] ; (8008180 <__sinit+0x58>) + 8008138: 4a12 ldr r2, [pc, #72] ; (8008184 <__sinit+0x5c>) + 800813a: 681b ldr r3, [r3, #0] + 800813c: 6282 str r2, [r0, #40] ; 0x28 + 800813e: 4298 cmp r0, r3 + 8008140: bf04 itt eq + 8008142: 2301 moveq r3, #1 + 8008144: 6183 streq r3, [r0, #24] + 8008146: f000 f81f bl 8008188 <__sfp> + 800814a: 6060 str r0, [r4, #4] + 800814c: 4620 mov r0, r4 + 800814e: f000 f81b bl 8008188 <__sfp> + 8008152: 60a0 str r0, [r4, #8] + 8008154: 4620 mov r0, r4 + 8008156: f000 f817 bl 8008188 <__sfp> + 800815a: 2200 movs r2, #0 + 800815c: 60e0 str r0, [r4, #12] + 800815e: 2104 movs r1, #4 + 8008160: 6860 ldr r0, [r4, #4] + 8008162: f7ff ffa1 bl 80080a8 + 8008166: 2201 movs r2, #1 + 8008168: 2109 movs r1, #9 + 800816a: 68a0 ldr r0, [r4, #8] + 800816c: f7ff ff9c bl 80080a8 + 8008170: 2202 movs r2, #2 + 8008172: 2112 movs r1, #18 + 8008174: 68e0 ldr r0, [r4, #12] + 8008176: f7ff ff97 bl 80080a8 + 800817a: 2301 movs r3, #1 + 800817c: 61a3 str r3, [r4, #24] + 800817e: bd10 pop {r4, pc} + 8008180: 08009a38 .word 0x08009a38 + 8008184: 080080f1 .word 0x080080f1 + +08008188 <__sfp>: + 8008188: b5f8 push {r3, r4, r5, r6, r7, lr} + 800818a: 4b1b ldr r3, [pc, #108] ; (80081f8 <__sfp+0x70>) + 800818c: 681e ldr r6, [r3, #0] + 800818e: 69b3 ldr r3, [r6, #24] + 8008190: 4607 mov r7, r0 + 8008192: b913 cbnz r3, 800819a <__sfp+0x12> + 8008194: 4630 mov r0, r6 + 8008196: f7ff ffc7 bl 8008128 <__sinit> + 800819a: 3648 adds r6, #72 ; 0x48 + 800819c: e9d6 3401 ldrd r3, r4, [r6, #4] + 80081a0: 3b01 subs r3, #1 + 80081a2: d503 bpl.n 80081ac <__sfp+0x24> + 80081a4: 6833 ldr r3, [r6, #0] + 80081a6: b133 cbz r3, 80081b6 <__sfp+0x2e> + 80081a8: 6836 ldr r6, [r6, #0] + 80081aa: e7f7 b.n 800819c <__sfp+0x14> + 80081ac: f9b4 500c ldrsh.w r5, [r4, #12] + 80081b0: b16d cbz r5, 80081ce <__sfp+0x46> + 80081b2: 3468 adds r4, #104 ; 0x68 + 80081b4: e7f4 b.n 80081a0 <__sfp+0x18> + 80081b6: 2104 movs r1, #4 + 80081b8: 4638 mov r0, r7 + 80081ba: f7ff ff9f bl 80080fc <__sfmoreglue> + 80081be: 6030 str r0, [r6, #0] + 80081c0: 2800 cmp r0, #0 + 80081c2: d1f1 bne.n 80081a8 <__sfp+0x20> + 80081c4: 230c movs r3, #12 + 80081c6: 603b str r3, [r7, #0] + 80081c8: 4604 mov r4, r0 + 80081ca: 4620 mov r0, r4 + 80081cc: bdf8 pop {r3, r4, r5, r6, r7, pc} + 80081ce: 4b0b ldr r3, [pc, #44] ; (80081fc <__sfp+0x74>) + 80081d0: 6665 str r5, [r4, #100] ; 0x64 + 80081d2: e9c4 5500 strd r5, r5, [r4] + 80081d6: 60a5 str r5, [r4, #8] + 80081d8: e9c4 3503 strd r3, r5, [r4, #12] + 80081dc: e9c4 5505 strd r5, r5, [r4, #20] + 80081e0: 2208 movs r2, #8 + 80081e2: 4629 mov r1, r5 + 80081e4: f104 005c add.w r0, r4, #92 ; 0x5c + 80081e8: f7fd f958 bl 800549c + 80081ec: e9c4 550d strd r5, r5, [r4, #52] ; 0x34 + 80081f0: e9c4 5512 strd r5, r5, [r4, #72] ; 0x48 + 80081f4: e7e9 b.n 80081ca <__sfp+0x42> + 80081f6: bf00 nop + 80081f8: 08009a38 .word 0x08009a38 + 80081fc: ffff0001 .word 0xffff0001 + +08008200 <_fwalk_reent>: + 8008200: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} + 8008204: 4680 mov r8, r0 + 8008206: 4689 mov r9, r1 + 8008208: f100 0448 add.w r4, r0, #72 ; 0x48 + 800820c: 2600 movs r6, #0 + 800820e: b914 cbnz r4, 8008216 <_fwalk_reent+0x16> + 8008210: 4630 mov r0, r6 + 8008212: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} + 8008216: e9d4 7501 ldrd r7, r5, [r4, #4] + 800821a: 3f01 subs r7, #1 + 800821c: d501 bpl.n 8008222 <_fwalk_reent+0x22> + 800821e: 6824 ldr r4, [r4, #0] + 8008220: e7f5 b.n 800820e <_fwalk_reent+0xe> + 8008222: 89ab ldrh r3, [r5, #12] + 8008224: 2b01 cmp r3, #1 + 8008226: d907 bls.n 8008238 <_fwalk_reent+0x38> + 8008228: f9b5 300e ldrsh.w r3, [r5, #14] + 800822c: 3301 adds r3, #1 + 800822e: d003 beq.n 8008238 <_fwalk_reent+0x38> + 8008230: 4629 mov r1, r5 + 8008232: 4640 mov r0, r8 + 8008234: 47c8 blx r9 + 8008236: 4306 orrs r6, r0 + 8008238: 3568 adds r5, #104 ; 0x68 + 800823a: e7ee b.n 800821a <_fwalk_reent+0x1a> + +0800823c : + 800823c: b5f0 push {r4, r5, r6, r7, lr} + 800823e: 6906 ldr r6, [r0, #16] + 8008240: 114b asrs r3, r1, #5 + 8008242: 429e cmp r6, r3 + 8008244: f100 0414 add.w r4, r0, #20 + 8008248: dd30 ble.n 80082ac + 800824a: f011 011f ands.w r1, r1, #31 + 800824e: eb04 0686 add.w r6, r4, r6, lsl #2 + 8008252: eb04 0283 add.w r2, r4, r3, lsl #2 + 8008256: d108 bne.n 800826a + 8008258: 4621 mov r1, r4 + 800825a: 42b2 cmp r2, r6 + 800825c: 460b mov r3, r1 + 800825e: d211 bcs.n 8008284 + 8008260: f852 3b04 ldr.w r3, [r2], #4 + 8008264: f841 3b04 str.w r3, [r1], #4 + 8008268: e7f7 b.n 800825a + 800826a: f854 5023 ldr.w r5, [r4, r3, lsl #2] + 800826e: f1c1 0c20 rsb ip, r1, #32 + 8008272: 40cd lsrs r5, r1 + 8008274: 3204 adds r2, #4 + 8008276: 4623 mov r3, r4 + 8008278: 42b2 cmp r2, r6 + 800827a: 4617 mov r7, r2 + 800827c: d30c bcc.n 8008298 + 800827e: 601d str r5, [r3, #0] + 8008280: b105 cbz r5, 8008284 + 8008282: 3304 adds r3, #4 + 8008284: 1b1a subs r2, r3, r4 + 8008286: 42a3 cmp r3, r4 + 8008288: ea4f 02a2 mov.w r2, r2, asr #2 + 800828c: bf08 it eq + 800828e: 2300 moveq r3, #0 + 8008290: 6102 str r2, [r0, #16] + 8008292: bf08 it eq + 8008294: 6143 streq r3, [r0, #20] + 8008296: bdf0 pop {r4, r5, r6, r7, pc} + 8008298: 683f ldr r7, [r7, #0] + 800829a: fa07 f70c lsl.w r7, r7, ip + 800829e: 433d orrs r5, r7 + 80082a0: f843 5b04 str.w r5, [r3], #4 + 80082a4: f852 5b04 ldr.w r5, [r2], #4 + 80082a8: 40cd lsrs r5, r1 + 80082aa: e7e5 b.n 8008278 + 80082ac: 4623 mov r3, r4 + 80082ae: e7e9 b.n 8008284 + +080082b0 <__hexdig_fun>: + 80082b0: f1a0 0330 sub.w r3, r0, #48 ; 0x30 + 80082b4: 2b09 cmp r3, #9 + 80082b6: d802 bhi.n 80082be <__hexdig_fun+0xe> + 80082b8: 3820 subs r0, #32 + 80082ba: b2c0 uxtb r0, r0 + 80082bc: 4770 bx lr + 80082be: f1a0 0361 sub.w r3, r0, #97 ; 0x61 + 80082c2: 2b05 cmp r3, #5 + 80082c4: d801 bhi.n 80082ca <__hexdig_fun+0x1a> + 80082c6: 3847 subs r0, #71 ; 0x47 + 80082c8: e7f7 b.n 80082ba <__hexdig_fun+0xa> + 80082ca: f1a0 0341 sub.w r3, r0, #65 ; 0x41 + 80082ce: 2b05 cmp r3, #5 + 80082d0: d801 bhi.n 80082d6 <__hexdig_fun+0x26> + 80082d2: 3827 subs r0, #39 ; 0x27 + 80082d4: e7f1 b.n 80082ba <__hexdig_fun+0xa> + 80082d6: 2000 movs r0, #0 + 80082d8: 4770 bx lr + +080082da <__gethex>: + 80082da: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 80082de: b08b sub sp, #44 ; 0x2c + 80082e0: 468a mov sl, r1 + 80082e2: 9002 str r0, [sp, #8] + 80082e4: 9816 ldr r0, [sp, #88] ; 0x58 + 80082e6: 9306 str r3, [sp, #24] + 80082e8: 4690 mov r8, r2 + 80082ea: f000 fad0 bl 800888e <__localeconv_l> + 80082ee: 6803 ldr r3, [r0, #0] + 80082f0: 9303 str r3, [sp, #12] + 80082f2: 4618 mov r0, r3 + 80082f4: f7f7 ff74 bl 80001e0 + 80082f8: 9b03 ldr r3, [sp, #12] + 80082fa: 9001 str r0, [sp, #4] + 80082fc: 4403 add r3, r0 + 80082fe: f04f 0b00 mov.w fp, #0 + 8008302: f813 3c01 ldrb.w r3, [r3, #-1] + 8008306: 9307 str r3, [sp, #28] + 8008308: f8da 3000 ldr.w r3, [sl] + 800830c: 3302 adds r3, #2 + 800830e: 461f mov r7, r3 + 8008310: f813 0b01 ldrb.w r0, [r3], #1 + 8008314: 2830 cmp r0, #48 ; 0x30 + 8008316: d06c beq.n 80083f2 <__gethex+0x118> + 8008318: f7ff ffca bl 80082b0 <__hexdig_fun> + 800831c: 4604 mov r4, r0 + 800831e: 2800 cmp r0, #0 + 8008320: d16a bne.n 80083f8 <__gethex+0x11e> + 8008322: 9a01 ldr r2, [sp, #4] + 8008324: 9903 ldr r1, [sp, #12] + 8008326: 4638 mov r0, r7 + 8008328: f001 fa27 bl 800977a + 800832c: 2800 cmp r0, #0 + 800832e: d166 bne.n 80083fe <__gethex+0x124> + 8008330: 9b01 ldr r3, [sp, #4] + 8008332: 5cf8 ldrb r0, [r7, r3] + 8008334: 18fe adds r6, r7, r3 + 8008336: f7ff ffbb bl 80082b0 <__hexdig_fun> + 800833a: 2800 cmp r0, #0 + 800833c: d062 beq.n 8008404 <__gethex+0x12a> + 800833e: 4633 mov r3, r6 + 8008340: 7818 ldrb r0, [r3, #0] + 8008342: 2830 cmp r0, #48 ; 0x30 + 8008344: 461f mov r7, r3 + 8008346: f103 0301 add.w r3, r3, #1 + 800834a: d0f9 beq.n 8008340 <__gethex+0x66> + 800834c: f7ff ffb0 bl 80082b0 <__hexdig_fun> + 8008350: fab0 f580 clz r5, r0 + 8008354: 096d lsrs r5, r5, #5 + 8008356: 4634 mov r4, r6 + 8008358: f04f 0b01 mov.w fp, #1 + 800835c: 463a mov r2, r7 + 800835e: 4616 mov r6, r2 + 8008360: 3201 adds r2, #1 + 8008362: 7830 ldrb r0, [r6, #0] + 8008364: f7ff ffa4 bl 80082b0 <__hexdig_fun> + 8008368: 2800 cmp r0, #0 + 800836a: d1f8 bne.n 800835e <__gethex+0x84> + 800836c: 9a01 ldr r2, [sp, #4] + 800836e: 9903 ldr r1, [sp, #12] + 8008370: 4630 mov r0, r6 + 8008372: f001 fa02 bl 800977a + 8008376: b950 cbnz r0, 800838e <__gethex+0xb4> + 8008378: b954 cbnz r4, 8008390 <__gethex+0xb6> + 800837a: 9b01 ldr r3, [sp, #4] + 800837c: 18f4 adds r4, r6, r3 + 800837e: 4622 mov r2, r4 + 8008380: 4616 mov r6, r2 + 8008382: 3201 adds r2, #1 + 8008384: 7830 ldrb r0, [r6, #0] + 8008386: f7ff ff93 bl 80082b0 <__hexdig_fun> + 800838a: 2800 cmp r0, #0 + 800838c: d1f8 bne.n 8008380 <__gethex+0xa6> + 800838e: b10c cbz r4, 8008394 <__gethex+0xba> + 8008390: 1ba4 subs r4, r4, r6 + 8008392: 00a4 lsls r4, r4, #2 + 8008394: 7833 ldrb r3, [r6, #0] + 8008396: 2b50 cmp r3, #80 ; 0x50 + 8008398: d001 beq.n 800839e <__gethex+0xc4> + 800839a: 2b70 cmp r3, #112 ; 0x70 + 800839c: d140 bne.n 8008420 <__gethex+0x146> + 800839e: 7873 ldrb r3, [r6, #1] + 80083a0: 2b2b cmp r3, #43 ; 0x2b + 80083a2: d031 beq.n 8008408 <__gethex+0x12e> + 80083a4: 2b2d cmp r3, #45 ; 0x2d + 80083a6: d033 beq.n 8008410 <__gethex+0x136> + 80083a8: 1c71 adds r1, r6, #1 + 80083aa: f04f 0900 mov.w r9, #0 + 80083ae: 7808 ldrb r0, [r1, #0] + 80083b0: f7ff ff7e bl 80082b0 <__hexdig_fun> + 80083b4: 1e43 subs r3, r0, #1 + 80083b6: b2db uxtb r3, r3 + 80083b8: 2b18 cmp r3, #24 + 80083ba: d831 bhi.n 8008420 <__gethex+0x146> + 80083bc: f1a0 0210 sub.w r2, r0, #16 + 80083c0: f811 0f01 ldrb.w r0, [r1, #1]! + 80083c4: f7ff ff74 bl 80082b0 <__hexdig_fun> + 80083c8: 1e43 subs r3, r0, #1 + 80083ca: b2db uxtb r3, r3 + 80083cc: 2b18 cmp r3, #24 + 80083ce: d922 bls.n 8008416 <__gethex+0x13c> + 80083d0: f1b9 0f00 cmp.w r9, #0 + 80083d4: d000 beq.n 80083d8 <__gethex+0xfe> + 80083d6: 4252 negs r2, r2 + 80083d8: 4414 add r4, r2 + 80083da: f8ca 1000 str.w r1, [sl] + 80083de: b30d cbz r5, 8008424 <__gethex+0x14a> + 80083e0: f1bb 0f00 cmp.w fp, #0 + 80083e4: bf0c ite eq + 80083e6: 2706 moveq r7, #6 + 80083e8: 2700 movne r7, #0 + 80083ea: 4638 mov r0, r7 + 80083ec: b00b add sp, #44 ; 0x2c + 80083ee: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 80083f2: f10b 0b01 add.w fp, fp, #1 + 80083f6: e78a b.n 800830e <__gethex+0x34> + 80083f8: 2500 movs r5, #0 + 80083fa: 462c mov r4, r5 + 80083fc: e7ae b.n 800835c <__gethex+0x82> + 80083fe: 463e mov r6, r7 + 8008400: 2501 movs r5, #1 + 8008402: e7c7 b.n 8008394 <__gethex+0xba> + 8008404: 4604 mov r4, r0 + 8008406: e7fb b.n 8008400 <__gethex+0x126> + 8008408: f04f 0900 mov.w r9, #0 + 800840c: 1cb1 adds r1, r6, #2 + 800840e: e7ce b.n 80083ae <__gethex+0xd4> + 8008410: f04f 0901 mov.w r9, #1 + 8008414: e7fa b.n 800840c <__gethex+0x132> + 8008416: 230a movs r3, #10 + 8008418: fb03 0202 mla r2, r3, r2, r0 + 800841c: 3a10 subs r2, #16 + 800841e: e7cf b.n 80083c0 <__gethex+0xe6> + 8008420: 4631 mov r1, r6 + 8008422: e7da b.n 80083da <__gethex+0x100> + 8008424: 1bf3 subs r3, r6, r7 + 8008426: 3b01 subs r3, #1 + 8008428: 4629 mov r1, r5 + 800842a: 2b07 cmp r3, #7 + 800842c: dc49 bgt.n 80084c2 <__gethex+0x1e8> + 800842e: 9802 ldr r0, [sp, #8] + 8008430: f000 fac1 bl 80089b6 <_Balloc> + 8008434: 9b01 ldr r3, [sp, #4] + 8008436: f100 0914 add.w r9, r0, #20 + 800843a: f04f 0b00 mov.w fp, #0 + 800843e: f1c3 0301 rsb r3, r3, #1 + 8008442: 4605 mov r5, r0 + 8008444: f8cd 9010 str.w r9, [sp, #16] + 8008448: 46da mov sl, fp + 800844a: 9308 str r3, [sp, #32] + 800844c: 42b7 cmp r7, r6 + 800844e: d33b bcc.n 80084c8 <__gethex+0x1ee> + 8008450: 9804 ldr r0, [sp, #16] + 8008452: f840 ab04 str.w sl, [r0], #4 + 8008456: eba0 0009 sub.w r0, r0, r9 + 800845a: 1080 asrs r0, r0, #2 + 800845c: 6128 str r0, [r5, #16] + 800845e: 0147 lsls r7, r0, #5 + 8008460: 4650 mov r0, sl + 8008462: f000 fb6c bl 8008b3e <__hi0bits> + 8008466: f8d8 6000 ldr.w r6, [r8] + 800846a: 1a3f subs r7, r7, r0 + 800846c: 42b7 cmp r7, r6 + 800846e: dd64 ble.n 800853a <__gethex+0x260> + 8008470: 1bbf subs r7, r7, r6 + 8008472: 4639 mov r1, r7 + 8008474: 4628 mov r0, r5 + 8008476: f000 fe7b bl 8009170 <__any_on> + 800847a: 4682 mov sl, r0 + 800847c: b178 cbz r0, 800849e <__gethex+0x1c4> + 800847e: 1e7b subs r3, r7, #1 + 8008480: 1159 asrs r1, r3, #5 + 8008482: f003 021f and.w r2, r3, #31 + 8008486: f04f 0a01 mov.w sl, #1 + 800848a: f859 1021 ldr.w r1, [r9, r1, lsl #2] + 800848e: fa0a f202 lsl.w r2, sl, r2 + 8008492: 420a tst r2, r1 + 8008494: d003 beq.n 800849e <__gethex+0x1c4> + 8008496: 4553 cmp r3, sl + 8008498: dc46 bgt.n 8008528 <__gethex+0x24e> + 800849a: f04f 0a02 mov.w sl, #2 + 800849e: 4639 mov r1, r7 + 80084a0: 4628 mov r0, r5 + 80084a2: f7ff fecb bl 800823c + 80084a6: 443c add r4, r7 + 80084a8: f8d8 3008 ldr.w r3, [r8, #8] + 80084ac: 42a3 cmp r3, r4 + 80084ae: da52 bge.n 8008556 <__gethex+0x27c> + 80084b0: 4629 mov r1, r5 + 80084b2: 9802 ldr r0, [sp, #8] + 80084b4: f000 fab3 bl 8008a1e <_Bfree> + 80084b8: 9a14 ldr r2, [sp, #80] ; 0x50 + 80084ba: 2300 movs r3, #0 + 80084bc: 6013 str r3, [r2, #0] + 80084be: 27a3 movs r7, #163 ; 0xa3 + 80084c0: e793 b.n 80083ea <__gethex+0x110> + 80084c2: 3101 adds r1, #1 + 80084c4: 105b asrs r3, r3, #1 + 80084c6: e7b0 b.n 800842a <__gethex+0x150> + 80084c8: 1e73 subs r3, r6, #1 + 80084ca: 9305 str r3, [sp, #20] + 80084cc: 9a07 ldr r2, [sp, #28] + 80084ce: f816 3c01 ldrb.w r3, [r6, #-1] + 80084d2: 4293 cmp r3, r2 + 80084d4: d018 beq.n 8008508 <__gethex+0x22e> + 80084d6: f1bb 0f20 cmp.w fp, #32 + 80084da: d107 bne.n 80084ec <__gethex+0x212> + 80084dc: 9b04 ldr r3, [sp, #16] + 80084de: f8c3 a000 str.w sl, [r3] + 80084e2: 3304 adds r3, #4 + 80084e4: f04f 0a00 mov.w sl, #0 + 80084e8: 9304 str r3, [sp, #16] + 80084ea: 46d3 mov fp, sl + 80084ec: f816 0c01 ldrb.w r0, [r6, #-1] + 80084f0: f7ff fede bl 80082b0 <__hexdig_fun> + 80084f4: f000 000f and.w r0, r0, #15 + 80084f8: fa00 f00b lsl.w r0, r0, fp + 80084fc: ea4a 0a00 orr.w sl, sl, r0 + 8008500: f10b 0b04 add.w fp, fp, #4 + 8008504: 9b05 ldr r3, [sp, #20] + 8008506: e00d b.n 8008524 <__gethex+0x24a> + 8008508: 9b05 ldr r3, [sp, #20] + 800850a: 9a08 ldr r2, [sp, #32] + 800850c: 4413 add r3, r2 + 800850e: 42bb cmp r3, r7 + 8008510: d3e1 bcc.n 80084d6 <__gethex+0x1fc> + 8008512: 4618 mov r0, r3 + 8008514: 9a01 ldr r2, [sp, #4] + 8008516: 9903 ldr r1, [sp, #12] + 8008518: 9309 str r3, [sp, #36] ; 0x24 + 800851a: f001 f92e bl 800977a + 800851e: 9b09 ldr r3, [sp, #36] ; 0x24 + 8008520: 2800 cmp r0, #0 + 8008522: d1d8 bne.n 80084d6 <__gethex+0x1fc> + 8008524: 461e mov r6, r3 + 8008526: e791 b.n 800844c <__gethex+0x172> + 8008528: 1eb9 subs r1, r7, #2 + 800852a: 4628 mov r0, r5 + 800852c: f000 fe20 bl 8009170 <__any_on> + 8008530: 2800 cmp r0, #0 + 8008532: d0b2 beq.n 800849a <__gethex+0x1c0> + 8008534: f04f 0a03 mov.w sl, #3 + 8008538: e7b1 b.n 800849e <__gethex+0x1c4> + 800853a: da09 bge.n 8008550 <__gethex+0x276> + 800853c: 1bf7 subs r7, r6, r7 + 800853e: 4629 mov r1, r5 + 8008540: 463a mov r2, r7 + 8008542: 9802 ldr r0, [sp, #8] + 8008544: f000 fc36 bl 8008db4 <__lshift> + 8008548: 1be4 subs r4, r4, r7 + 800854a: 4605 mov r5, r0 + 800854c: f100 0914 add.w r9, r0, #20 + 8008550: f04f 0a00 mov.w sl, #0 + 8008554: e7a8 b.n 80084a8 <__gethex+0x1ce> + 8008556: f8d8 0004 ldr.w r0, [r8, #4] + 800855a: 42a0 cmp r0, r4 + 800855c: dd6a ble.n 8008634 <__gethex+0x35a> + 800855e: 1b04 subs r4, r0, r4 + 8008560: 42a6 cmp r6, r4 + 8008562: dc2e bgt.n 80085c2 <__gethex+0x2e8> + 8008564: f8d8 300c ldr.w r3, [r8, #12] + 8008568: 2b02 cmp r3, #2 + 800856a: d022 beq.n 80085b2 <__gethex+0x2d8> + 800856c: 2b03 cmp r3, #3 + 800856e: d024 beq.n 80085ba <__gethex+0x2e0> + 8008570: 2b01 cmp r3, #1 + 8008572: d115 bne.n 80085a0 <__gethex+0x2c6> + 8008574: 42a6 cmp r6, r4 + 8008576: d113 bne.n 80085a0 <__gethex+0x2c6> + 8008578: 2e01 cmp r6, #1 + 800857a: dc0b bgt.n 8008594 <__gethex+0x2ba> + 800857c: 9a06 ldr r2, [sp, #24] + 800857e: f8d8 3004 ldr.w r3, [r8, #4] + 8008582: 6013 str r3, [r2, #0] + 8008584: 2301 movs r3, #1 + 8008586: 612b str r3, [r5, #16] + 8008588: f8c9 3000 str.w r3, [r9] + 800858c: 9b14 ldr r3, [sp, #80] ; 0x50 + 800858e: 2762 movs r7, #98 ; 0x62 + 8008590: 601d str r5, [r3, #0] + 8008592: e72a b.n 80083ea <__gethex+0x110> + 8008594: 1e71 subs r1, r6, #1 + 8008596: 4628 mov r0, r5 + 8008598: f000 fdea bl 8009170 <__any_on> + 800859c: 2800 cmp r0, #0 + 800859e: d1ed bne.n 800857c <__gethex+0x2a2> + 80085a0: 4629 mov r1, r5 + 80085a2: 9802 ldr r0, [sp, #8] + 80085a4: f000 fa3b bl 8008a1e <_Bfree> + 80085a8: 9a14 ldr r2, [sp, #80] ; 0x50 + 80085aa: 2300 movs r3, #0 + 80085ac: 6013 str r3, [r2, #0] + 80085ae: 2750 movs r7, #80 ; 0x50 + 80085b0: e71b b.n 80083ea <__gethex+0x110> + 80085b2: 9b15 ldr r3, [sp, #84] ; 0x54 + 80085b4: 2b00 cmp r3, #0 + 80085b6: d0e1 beq.n 800857c <__gethex+0x2a2> + 80085b8: e7f2 b.n 80085a0 <__gethex+0x2c6> + 80085ba: 9b15 ldr r3, [sp, #84] ; 0x54 + 80085bc: 2b00 cmp r3, #0 + 80085be: d1dd bne.n 800857c <__gethex+0x2a2> + 80085c0: e7ee b.n 80085a0 <__gethex+0x2c6> + 80085c2: 1e67 subs r7, r4, #1 + 80085c4: f1ba 0f00 cmp.w sl, #0 + 80085c8: d131 bne.n 800862e <__gethex+0x354> + 80085ca: b127 cbz r7, 80085d6 <__gethex+0x2fc> + 80085cc: 4639 mov r1, r7 + 80085ce: 4628 mov r0, r5 + 80085d0: f000 fdce bl 8009170 <__any_on> + 80085d4: 4682 mov sl, r0 + 80085d6: 117a asrs r2, r7, #5 + 80085d8: 2301 movs r3, #1 + 80085da: f007 071f and.w r7, r7, #31 + 80085de: fa03 f707 lsl.w r7, r3, r7 + 80085e2: f859 3022 ldr.w r3, [r9, r2, lsl #2] + 80085e6: 4621 mov r1, r4 + 80085e8: 421f tst r7, r3 + 80085ea: 4628 mov r0, r5 + 80085ec: bf18 it ne + 80085ee: f04a 0a02 orrne.w sl, sl, #2 + 80085f2: 1b36 subs r6, r6, r4 + 80085f4: f7ff fe22 bl 800823c + 80085f8: f8d8 4004 ldr.w r4, [r8, #4] + 80085fc: 2702 movs r7, #2 + 80085fe: f1ba 0f00 cmp.w sl, #0 + 8008602: d048 beq.n 8008696 <__gethex+0x3bc> + 8008604: f8d8 300c ldr.w r3, [r8, #12] + 8008608: 2b02 cmp r3, #2 + 800860a: d015 beq.n 8008638 <__gethex+0x35e> + 800860c: 2b03 cmp r3, #3 + 800860e: d017 beq.n 8008640 <__gethex+0x366> + 8008610: 2b01 cmp r3, #1 + 8008612: d109 bne.n 8008628 <__gethex+0x34e> + 8008614: f01a 0f02 tst.w sl, #2 + 8008618: d006 beq.n 8008628 <__gethex+0x34e> + 800861a: f8d9 3000 ldr.w r3, [r9] + 800861e: ea4a 0a03 orr.w sl, sl, r3 + 8008622: f01a 0f01 tst.w sl, #1 + 8008626: d10e bne.n 8008646 <__gethex+0x36c> + 8008628: f047 0710 orr.w r7, r7, #16 + 800862c: e033 b.n 8008696 <__gethex+0x3bc> + 800862e: f04f 0a01 mov.w sl, #1 + 8008632: e7d0 b.n 80085d6 <__gethex+0x2fc> + 8008634: 2701 movs r7, #1 + 8008636: e7e2 b.n 80085fe <__gethex+0x324> + 8008638: 9b15 ldr r3, [sp, #84] ; 0x54 + 800863a: f1c3 0301 rsb r3, r3, #1 + 800863e: 9315 str r3, [sp, #84] ; 0x54 + 8008640: 9b15 ldr r3, [sp, #84] ; 0x54 + 8008642: 2b00 cmp r3, #0 + 8008644: d0f0 beq.n 8008628 <__gethex+0x34e> + 8008646: f8d5 9010 ldr.w r9, [r5, #16] + 800864a: f105 0314 add.w r3, r5, #20 + 800864e: ea4f 0a89 mov.w sl, r9, lsl #2 + 8008652: eb03 010a add.w r1, r3, sl + 8008656: f04f 0c00 mov.w ip, #0 + 800865a: 4618 mov r0, r3 + 800865c: f853 2b04 ldr.w r2, [r3], #4 + 8008660: f1b2 3fff cmp.w r2, #4294967295 + 8008664: d01c beq.n 80086a0 <__gethex+0x3c6> + 8008666: 3201 adds r2, #1 + 8008668: 6002 str r2, [r0, #0] + 800866a: 2f02 cmp r7, #2 + 800866c: f105 0314 add.w r3, r5, #20 + 8008670: d138 bne.n 80086e4 <__gethex+0x40a> + 8008672: f8d8 2000 ldr.w r2, [r8] + 8008676: 3a01 subs r2, #1 + 8008678: 42b2 cmp r2, r6 + 800867a: d10a bne.n 8008692 <__gethex+0x3b8> + 800867c: 1171 asrs r1, r6, #5 + 800867e: 2201 movs r2, #1 + 8008680: f006 061f and.w r6, r6, #31 + 8008684: f853 3021 ldr.w r3, [r3, r1, lsl #2] + 8008688: fa02 f606 lsl.w r6, r2, r6 + 800868c: 421e tst r6, r3 + 800868e: bf18 it ne + 8008690: 4617 movne r7, r2 + 8008692: f047 0720 orr.w r7, r7, #32 + 8008696: 9b14 ldr r3, [sp, #80] ; 0x50 + 8008698: 601d str r5, [r3, #0] + 800869a: 9b06 ldr r3, [sp, #24] + 800869c: 601c str r4, [r3, #0] + 800869e: e6a4 b.n 80083ea <__gethex+0x110> + 80086a0: 4299 cmp r1, r3 + 80086a2: f843 cc04 str.w ip, [r3, #-4] + 80086a6: d8d8 bhi.n 800865a <__gethex+0x380> + 80086a8: 68ab ldr r3, [r5, #8] + 80086aa: 4599 cmp r9, r3 + 80086ac: db12 blt.n 80086d4 <__gethex+0x3fa> + 80086ae: 6869 ldr r1, [r5, #4] + 80086b0: 9802 ldr r0, [sp, #8] + 80086b2: 3101 adds r1, #1 + 80086b4: f000 f97f bl 80089b6 <_Balloc> + 80086b8: 692a ldr r2, [r5, #16] + 80086ba: 3202 adds r2, #2 + 80086bc: f105 010c add.w r1, r5, #12 + 80086c0: 4683 mov fp, r0 + 80086c2: 0092 lsls r2, r2, #2 + 80086c4: 300c adds r0, #12 + 80086c6: f000 f969 bl 800899c + 80086ca: 4629 mov r1, r5 + 80086cc: 9802 ldr r0, [sp, #8] + 80086ce: f000 f9a6 bl 8008a1e <_Bfree> + 80086d2: 465d mov r5, fp + 80086d4: 692b ldr r3, [r5, #16] + 80086d6: 1c5a adds r2, r3, #1 + 80086d8: eb05 0383 add.w r3, r5, r3, lsl #2 + 80086dc: 612a str r2, [r5, #16] + 80086de: 2201 movs r2, #1 + 80086e0: 615a str r2, [r3, #20] + 80086e2: e7c2 b.n 800866a <__gethex+0x390> + 80086e4: 692a ldr r2, [r5, #16] + 80086e6: 454a cmp r2, r9 + 80086e8: dd0b ble.n 8008702 <__gethex+0x428> + 80086ea: 2101 movs r1, #1 + 80086ec: 4628 mov r0, r5 + 80086ee: f7ff fda5 bl 800823c + 80086f2: f8d8 3008 ldr.w r3, [r8, #8] + 80086f6: 3401 adds r4, #1 + 80086f8: 42a3 cmp r3, r4 + 80086fa: f6ff aed9 blt.w 80084b0 <__gethex+0x1d6> + 80086fe: 2701 movs r7, #1 + 8008700: e7c7 b.n 8008692 <__gethex+0x3b8> + 8008702: f016 061f ands.w r6, r6, #31 + 8008706: d0fa beq.n 80086fe <__gethex+0x424> + 8008708: 449a add sl, r3 + 800870a: f1c6 0620 rsb r6, r6, #32 + 800870e: f85a 0c04 ldr.w r0, [sl, #-4] + 8008712: f000 fa14 bl 8008b3e <__hi0bits> + 8008716: 42b0 cmp r0, r6 + 8008718: dbe7 blt.n 80086ea <__gethex+0x410> + 800871a: e7f0 b.n 80086fe <__gethex+0x424> + +0800871c : + 800871c: f1c2 0208 rsb r2, r2, #8 + 8008720: 0092 lsls r2, r2, #2 + 8008722: b570 push {r4, r5, r6, lr} + 8008724: f1c2 0620 rsb r6, r2, #32 + 8008728: 6843 ldr r3, [r0, #4] + 800872a: 6804 ldr r4, [r0, #0] + 800872c: fa03 f506 lsl.w r5, r3, r6 + 8008730: 432c orrs r4, r5 + 8008732: 40d3 lsrs r3, r2 + 8008734: 6004 str r4, [r0, #0] + 8008736: f840 3f04 str.w r3, [r0, #4]! + 800873a: 4288 cmp r0, r1 + 800873c: d3f4 bcc.n 8008728 + 800873e: bd70 pop {r4, r5, r6, pc} + +08008740 <__match>: + 8008740: b530 push {r4, r5, lr} + 8008742: 6803 ldr r3, [r0, #0] + 8008744: 3301 adds r3, #1 + 8008746: f811 4b01 ldrb.w r4, [r1], #1 + 800874a: b914 cbnz r4, 8008752 <__match+0x12> + 800874c: 6003 str r3, [r0, #0] + 800874e: 2001 movs r0, #1 + 8008750: bd30 pop {r4, r5, pc} + 8008752: f813 2b01 ldrb.w r2, [r3], #1 + 8008756: f1a2 0541 sub.w r5, r2, #65 ; 0x41 + 800875a: 2d19 cmp r5, #25 + 800875c: bf98 it ls + 800875e: 3220 addls r2, #32 + 8008760: 42a2 cmp r2, r4 + 8008762: d0f0 beq.n 8008746 <__match+0x6> + 8008764: 2000 movs r0, #0 + 8008766: e7f3 b.n 8008750 <__match+0x10> + +08008768 <__hexnan>: + 8008768: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 800876c: 680b ldr r3, [r1, #0] + 800876e: 6801 ldr r1, [r0, #0] + 8008770: 115f asrs r7, r3, #5 + 8008772: eb02 0787 add.w r7, r2, r7, lsl #2 + 8008776: f013 031f ands.w r3, r3, #31 + 800877a: b087 sub sp, #28 + 800877c: bf18 it ne + 800877e: 3704 addne r7, #4 + 8008780: 2500 movs r5, #0 + 8008782: 1f3e subs r6, r7, #4 + 8008784: 4682 mov sl, r0 + 8008786: 4690 mov r8, r2 + 8008788: 9301 str r3, [sp, #4] + 800878a: f847 5c04 str.w r5, [r7, #-4] + 800878e: 46b1 mov r9, r6 + 8008790: 4634 mov r4, r6 + 8008792: 9502 str r5, [sp, #8] + 8008794: 46ab mov fp, r5 + 8008796: 784a ldrb r2, [r1, #1] + 8008798: 1c4b adds r3, r1, #1 + 800879a: 9303 str r3, [sp, #12] + 800879c: b342 cbz r2, 80087f0 <__hexnan+0x88> + 800879e: 4610 mov r0, r2 + 80087a0: 9105 str r1, [sp, #20] + 80087a2: 9204 str r2, [sp, #16] + 80087a4: f7ff fd84 bl 80082b0 <__hexdig_fun> + 80087a8: 2800 cmp r0, #0 + 80087aa: d143 bne.n 8008834 <__hexnan+0xcc> + 80087ac: 9a04 ldr r2, [sp, #16] + 80087ae: 9905 ldr r1, [sp, #20] + 80087b0: 2a20 cmp r2, #32 + 80087b2: d818 bhi.n 80087e6 <__hexnan+0x7e> + 80087b4: 9b02 ldr r3, [sp, #8] + 80087b6: 459b cmp fp, r3 + 80087b8: dd13 ble.n 80087e2 <__hexnan+0x7a> + 80087ba: 454c cmp r4, r9 + 80087bc: d206 bcs.n 80087cc <__hexnan+0x64> + 80087be: 2d07 cmp r5, #7 + 80087c0: dc04 bgt.n 80087cc <__hexnan+0x64> + 80087c2: 462a mov r2, r5 + 80087c4: 4649 mov r1, r9 + 80087c6: 4620 mov r0, r4 + 80087c8: f7ff ffa8 bl 800871c + 80087cc: 4544 cmp r4, r8 + 80087ce: d944 bls.n 800885a <__hexnan+0xf2> + 80087d0: 2300 movs r3, #0 + 80087d2: f1a4 0904 sub.w r9, r4, #4 + 80087d6: f844 3c04 str.w r3, [r4, #-4] + 80087da: f8cd b008 str.w fp, [sp, #8] + 80087de: 464c mov r4, r9 + 80087e0: 461d mov r5, r3 + 80087e2: 9903 ldr r1, [sp, #12] + 80087e4: e7d7 b.n 8008796 <__hexnan+0x2e> + 80087e6: 2a29 cmp r2, #41 ; 0x29 + 80087e8: d14a bne.n 8008880 <__hexnan+0x118> + 80087ea: 3102 adds r1, #2 + 80087ec: f8ca 1000 str.w r1, [sl] + 80087f0: f1bb 0f00 cmp.w fp, #0 + 80087f4: d044 beq.n 8008880 <__hexnan+0x118> + 80087f6: 454c cmp r4, r9 + 80087f8: d206 bcs.n 8008808 <__hexnan+0xa0> + 80087fa: 2d07 cmp r5, #7 + 80087fc: dc04 bgt.n 8008808 <__hexnan+0xa0> + 80087fe: 462a mov r2, r5 + 8008800: 4649 mov r1, r9 + 8008802: 4620 mov r0, r4 + 8008804: f7ff ff8a bl 800871c + 8008808: 4544 cmp r4, r8 + 800880a: d928 bls.n 800885e <__hexnan+0xf6> + 800880c: 4643 mov r3, r8 + 800880e: f854 2b04 ldr.w r2, [r4], #4 + 8008812: f843 2b04 str.w r2, [r3], #4 + 8008816: 42a6 cmp r6, r4 + 8008818: d2f9 bcs.n 800880e <__hexnan+0xa6> + 800881a: 2200 movs r2, #0 + 800881c: f843 2b04 str.w r2, [r3], #4 + 8008820: 429e cmp r6, r3 + 8008822: d2fb bcs.n 800881c <__hexnan+0xb4> + 8008824: 6833 ldr r3, [r6, #0] + 8008826: b91b cbnz r3, 8008830 <__hexnan+0xc8> + 8008828: 4546 cmp r6, r8 + 800882a: d127 bne.n 800887c <__hexnan+0x114> + 800882c: 2301 movs r3, #1 + 800882e: 6033 str r3, [r6, #0] + 8008830: 2005 movs r0, #5 + 8008832: e026 b.n 8008882 <__hexnan+0x11a> + 8008834: 3501 adds r5, #1 + 8008836: 2d08 cmp r5, #8 + 8008838: f10b 0b01 add.w fp, fp, #1 + 800883c: dd06 ble.n 800884c <__hexnan+0xe4> + 800883e: 4544 cmp r4, r8 + 8008840: d9cf bls.n 80087e2 <__hexnan+0x7a> + 8008842: 2300 movs r3, #0 + 8008844: f844 3c04 str.w r3, [r4, #-4] + 8008848: 2501 movs r5, #1 + 800884a: 3c04 subs r4, #4 + 800884c: 6822 ldr r2, [r4, #0] + 800884e: f000 000f and.w r0, r0, #15 + 8008852: ea40 1002 orr.w r0, r0, r2, lsl #4 + 8008856: 6020 str r0, [r4, #0] + 8008858: e7c3 b.n 80087e2 <__hexnan+0x7a> + 800885a: 2508 movs r5, #8 + 800885c: e7c1 b.n 80087e2 <__hexnan+0x7a> + 800885e: 9b01 ldr r3, [sp, #4] + 8008860: 2b00 cmp r3, #0 + 8008862: d0df beq.n 8008824 <__hexnan+0xbc> + 8008864: f04f 32ff mov.w r2, #4294967295 + 8008868: f1c3 0320 rsb r3, r3, #32 + 800886c: fa22 f303 lsr.w r3, r2, r3 + 8008870: f857 2c04 ldr.w r2, [r7, #-4] + 8008874: 401a ands r2, r3 + 8008876: f847 2c04 str.w r2, [r7, #-4] + 800887a: e7d3 b.n 8008824 <__hexnan+0xbc> + 800887c: 3e04 subs r6, #4 + 800887e: e7d1 b.n 8008824 <__hexnan+0xbc> + 8008880: 2004 movs r0, #4 + 8008882: b007 add sp, #28 + 8008884: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + +08008888 <__locale_ctype_ptr_l>: + 8008888: f8d0 00ec ldr.w r0, [r0, #236] ; 0xec + 800888c: 4770 bx lr + +0800888e <__localeconv_l>: + 800888e: 30f0 adds r0, #240 ; 0xf0 + 8008890: 4770 bx lr + ... + +08008894 <_localeconv_r>: + 8008894: 4b04 ldr r3, [pc, #16] ; (80088a8 <_localeconv_r+0x14>) + 8008896: 681b ldr r3, [r3, #0] + 8008898: 6a18 ldr r0, [r3, #32] + 800889a: 4b04 ldr r3, [pc, #16] ; (80088ac <_localeconv_r+0x18>) + 800889c: 2800 cmp r0, #0 + 800889e: bf08 it eq + 80088a0: 4618 moveq r0, r3 + 80088a2: 30f0 adds r0, #240 ; 0xf0 + 80088a4: 4770 bx lr + 80088a6: bf00 nop + 80088a8: 2000002c .word 0x2000002c + 80088ac: 20000090 .word 0x20000090 + +080088b0 <__swhatbuf_r>: + 80088b0: b570 push {r4, r5, r6, lr} + 80088b2: 460e mov r6, r1 + 80088b4: f9b1 100e ldrsh.w r1, [r1, #14] + 80088b8: 2900 cmp r1, #0 + 80088ba: b096 sub sp, #88 ; 0x58 + 80088bc: 4614 mov r4, r2 + 80088be: 461d mov r5, r3 + 80088c0: da07 bge.n 80088d2 <__swhatbuf_r+0x22> + 80088c2: 2300 movs r3, #0 + 80088c4: 602b str r3, [r5, #0] + 80088c6: 89b3 ldrh r3, [r6, #12] + 80088c8: 061a lsls r2, r3, #24 + 80088ca: d410 bmi.n 80088ee <__swhatbuf_r+0x3e> + 80088cc: f44f 6380 mov.w r3, #1024 ; 0x400 + 80088d0: e00e b.n 80088f0 <__swhatbuf_r+0x40> + 80088d2: 466a mov r2, sp + 80088d4: f000 ff92 bl 80097fc <_fstat_r> + 80088d8: 2800 cmp r0, #0 + 80088da: dbf2 blt.n 80088c2 <__swhatbuf_r+0x12> + 80088dc: 9a01 ldr r2, [sp, #4] + 80088de: f402 4270 and.w r2, r2, #61440 ; 0xf000 + 80088e2: f5a2 5300 sub.w r3, r2, #8192 ; 0x2000 + 80088e6: 425a negs r2, r3 + 80088e8: 415a adcs r2, r3 + 80088ea: 602a str r2, [r5, #0] + 80088ec: e7ee b.n 80088cc <__swhatbuf_r+0x1c> + 80088ee: 2340 movs r3, #64 ; 0x40 + 80088f0: 2000 movs r0, #0 + 80088f2: 6023 str r3, [r4, #0] + 80088f4: b016 add sp, #88 ; 0x58 + 80088f6: bd70 pop {r4, r5, r6, pc} + +080088f8 <__smakebuf_r>: + 80088f8: 898b ldrh r3, [r1, #12] + 80088fa: b573 push {r0, r1, r4, r5, r6, lr} + 80088fc: 079d lsls r5, r3, #30 + 80088fe: 4606 mov r6, r0 + 8008900: 460c mov r4, r1 + 8008902: d507 bpl.n 8008914 <__smakebuf_r+0x1c> + 8008904: f104 0347 add.w r3, r4, #71 ; 0x47 + 8008908: 6023 str r3, [r4, #0] + 800890a: 6123 str r3, [r4, #16] + 800890c: 2301 movs r3, #1 + 800890e: 6163 str r3, [r4, #20] + 8008910: b002 add sp, #8 + 8008912: bd70 pop {r4, r5, r6, pc} + 8008914: ab01 add r3, sp, #4 + 8008916: 466a mov r2, sp + 8008918: f7ff ffca bl 80088b0 <__swhatbuf_r> + 800891c: 9900 ldr r1, [sp, #0] + 800891e: 4605 mov r5, r0 + 8008920: 4630 mov r0, r6 + 8008922: f7fc fe11 bl 8005548 <_malloc_r> + 8008926: b948 cbnz r0, 800893c <__smakebuf_r+0x44> + 8008928: f9b4 300c ldrsh.w r3, [r4, #12] + 800892c: 059a lsls r2, r3, #22 + 800892e: d4ef bmi.n 8008910 <__smakebuf_r+0x18> + 8008930: f023 0303 bic.w r3, r3, #3 + 8008934: f043 0302 orr.w r3, r3, #2 + 8008938: 81a3 strh r3, [r4, #12] + 800893a: e7e3 b.n 8008904 <__smakebuf_r+0xc> + 800893c: 4b0d ldr r3, [pc, #52] ; (8008974 <__smakebuf_r+0x7c>) + 800893e: 62b3 str r3, [r6, #40] ; 0x28 + 8008940: 89a3 ldrh r3, [r4, #12] + 8008942: 6020 str r0, [r4, #0] + 8008944: f043 0380 orr.w r3, r3, #128 ; 0x80 + 8008948: 81a3 strh r3, [r4, #12] + 800894a: 9b00 ldr r3, [sp, #0] + 800894c: 6163 str r3, [r4, #20] + 800894e: 9b01 ldr r3, [sp, #4] + 8008950: 6120 str r0, [r4, #16] + 8008952: b15b cbz r3, 800896c <__smakebuf_r+0x74> + 8008954: f9b4 100e ldrsh.w r1, [r4, #14] + 8008958: 4630 mov r0, r6 + 800895a: f000 ff61 bl 8009820 <_isatty_r> + 800895e: b128 cbz r0, 800896c <__smakebuf_r+0x74> + 8008960: 89a3 ldrh r3, [r4, #12] + 8008962: f023 0303 bic.w r3, r3, #3 + 8008966: f043 0301 orr.w r3, r3, #1 + 800896a: 81a3 strh r3, [r4, #12] + 800896c: 89a3 ldrh r3, [r4, #12] + 800896e: 431d orrs r5, r3 + 8008970: 81a5 strh r5, [r4, #12] + 8008972: e7cd b.n 8008910 <__smakebuf_r+0x18> + 8008974: 080080f1 .word 0x080080f1 + +08008978 <__ascii_mbtowc>: + 8008978: b082 sub sp, #8 + 800897a: b901 cbnz r1, 800897e <__ascii_mbtowc+0x6> + 800897c: a901 add r1, sp, #4 + 800897e: b142 cbz r2, 8008992 <__ascii_mbtowc+0x1a> + 8008980: b14b cbz r3, 8008996 <__ascii_mbtowc+0x1e> + 8008982: 7813 ldrb r3, [r2, #0] + 8008984: 600b str r3, [r1, #0] + 8008986: 7812 ldrb r2, [r2, #0] + 8008988: 1c10 adds r0, r2, #0 + 800898a: bf18 it ne + 800898c: 2001 movne r0, #1 + 800898e: b002 add sp, #8 + 8008990: 4770 bx lr + 8008992: 4610 mov r0, r2 + 8008994: e7fb b.n 800898e <__ascii_mbtowc+0x16> + 8008996: f06f 0001 mvn.w r0, #1 + 800899a: e7f8 b.n 800898e <__ascii_mbtowc+0x16> + +0800899c : + 800899c: b510 push {r4, lr} + 800899e: 1e43 subs r3, r0, #1 + 80089a0: 440a add r2, r1 + 80089a2: 4291 cmp r1, r2 + 80089a4: d100 bne.n 80089a8 + 80089a6: bd10 pop {r4, pc} + 80089a8: f811 4b01 ldrb.w r4, [r1], #1 + 80089ac: f803 4f01 strb.w r4, [r3, #1]! + 80089b0: e7f7 b.n 80089a2 + +080089b2 <__malloc_lock>: + 80089b2: 4770 bx lr + +080089b4 <__malloc_unlock>: + 80089b4: 4770 bx lr + +080089b6 <_Balloc>: + 80089b6: b570 push {r4, r5, r6, lr} + 80089b8: 6a45 ldr r5, [r0, #36] ; 0x24 + 80089ba: 4604 mov r4, r0 + 80089bc: 460e mov r6, r1 + 80089be: b93d cbnz r5, 80089d0 <_Balloc+0x1a> + 80089c0: 2010 movs r0, #16 + 80089c2: f7fc fd5b bl 800547c + 80089c6: 6260 str r0, [r4, #36] ; 0x24 + 80089c8: e9c0 5501 strd r5, r5, [r0, #4] + 80089cc: 6005 str r5, [r0, #0] + 80089ce: 60c5 str r5, [r0, #12] + 80089d0: 6a65 ldr r5, [r4, #36] ; 0x24 + 80089d2: 68eb ldr r3, [r5, #12] + 80089d4: b183 cbz r3, 80089f8 <_Balloc+0x42> + 80089d6: 6a63 ldr r3, [r4, #36] ; 0x24 + 80089d8: 68db ldr r3, [r3, #12] + 80089da: f853 0026 ldr.w r0, [r3, r6, lsl #2] + 80089de: b9b8 cbnz r0, 8008a10 <_Balloc+0x5a> + 80089e0: 2101 movs r1, #1 + 80089e2: fa01 f506 lsl.w r5, r1, r6 + 80089e6: 1d6a adds r2, r5, #5 + 80089e8: 0092 lsls r2, r2, #2 + 80089ea: 4620 mov r0, r4 + 80089ec: f000 fbe1 bl 80091b2 <_calloc_r> + 80089f0: b160 cbz r0, 8008a0c <_Balloc+0x56> + 80089f2: e9c0 6501 strd r6, r5, [r0, #4] + 80089f6: e00e b.n 8008a16 <_Balloc+0x60> + 80089f8: 2221 movs r2, #33 ; 0x21 + 80089fa: 2104 movs r1, #4 + 80089fc: 4620 mov r0, r4 + 80089fe: f000 fbd8 bl 80091b2 <_calloc_r> + 8008a02: 6a63 ldr r3, [r4, #36] ; 0x24 + 8008a04: 60e8 str r0, [r5, #12] + 8008a06: 68db ldr r3, [r3, #12] + 8008a08: 2b00 cmp r3, #0 + 8008a0a: d1e4 bne.n 80089d6 <_Balloc+0x20> + 8008a0c: 2000 movs r0, #0 + 8008a0e: bd70 pop {r4, r5, r6, pc} + 8008a10: 6802 ldr r2, [r0, #0] + 8008a12: f843 2026 str.w r2, [r3, r6, lsl #2] + 8008a16: 2300 movs r3, #0 + 8008a18: e9c0 3303 strd r3, r3, [r0, #12] + 8008a1c: e7f7 b.n 8008a0e <_Balloc+0x58> + +08008a1e <_Bfree>: + 8008a1e: b570 push {r4, r5, r6, lr} + 8008a20: 6a44 ldr r4, [r0, #36] ; 0x24 + 8008a22: 4606 mov r6, r0 + 8008a24: 460d mov r5, r1 + 8008a26: b93c cbnz r4, 8008a38 <_Bfree+0x1a> + 8008a28: 2010 movs r0, #16 + 8008a2a: f7fc fd27 bl 800547c + 8008a2e: 6270 str r0, [r6, #36] ; 0x24 + 8008a30: e9c0 4401 strd r4, r4, [r0, #4] + 8008a34: 6004 str r4, [r0, #0] + 8008a36: 60c4 str r4, [r0, #12] + 8008a38: b13d cbz r5, 8008a4a <_Bfree+0x2c> + 8008a3a: 6a73 ldr r3, [r6, #36] ; 0x24 + 8008a3c: 686a ldr r2, [r5, #4] + 8008a3e: 68db ldr r3, [r3, #12] + 8008a40: f853 1022 ldr.w r1, [r3, r2, lsl #2] + 8008a44: 6029 str r1, [r5, #0] + 8008a46: f843 5022 str.w r5, [r3, r2, lsl #2] + 8008a4a: bd70 pop {r4, r5, r6, pc} + +08008a4c <__multadd>: + 8008a4c: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 8008a50: 690d ldr r5, [r1, #16] + 8008a52: 461f mov r7, r3 + 8008a54: 4606 mov r6, r0 + 8008a56: 460c mov r4, r1 + 8008a58: f101 0c14 add.w ip, r1, #20 + 8008a5c: 2300 movs r3, #0 + 8008a5e: f8dc 0000 ldr.w r0, [ip] + 8008a62: b281 uxth r1, r0 + 8008a64: fb02 7101 mla r1, r2, r1, r7 + 8008a68: 0c0f lsrs r7, r1, #16 + 8008a6a: 0c00 lsrs r0, r0, #16 + 8008a6c: fb02 7000 mla r0, r2, r0, r7 + 8008a70: b289 uxth r1, r1 + 8008a72: 3301 adds r3, #1 + 8008a74: eb01 4100 add.w r1, r1, r0, lsl #16 + 8008a78: 429d cmp r5, r3 + 8008a7a: ea4f 4710 mov.w r7, r0, lsr #16 + 8008a7e: f84c 1b04 str.w r1, [ip], #4 + 8008a82: dcec bgt.n 8008a5e <__multadd+0x12> + 8008a84: b1d7 cbz r7, 8008abc <__multadd+0x70> + 8008a86: 68a3 ldr r3, [r4, #8] + 8008a88: 42ab cmp r3, r5 + 8008a8a: dc12 bgt.n 8008ab2 <__multadd+0x66> + 8008a8c: 6861 ldr r1, [r4, #4] + 8008a8e: 4630 mov r0, r6 + 8008a90: 3101 adds r1, #1 + 8008a92: f7ff ff90 bl 80089b6 <_Balloc> + 8008a96: 6922 ldr r2, [r4, #16] + 8008a98: 3202 adds r2, #2 + 8008a9a: f104 010c add.w r1, r4, #12 + 8008a9e: 4680 mov r8, r0 + 8008aa0: 0092 lsls r2, r2, #2 + 8008aa2: 300c adds r0, #12 + 8008aa4: f7ff ff7a bl 800899c + 8008aa8: 4621 mov r1, r4 + 8008aaa: 4630 mov r0, r6 + 8008aac: f7ff ffb7 bl 8008a1e <_Bfree> + 8008ab0: 4644 mov r4, r8 + 8008ab2: eb04 0385 add.w r3, r4, r5, lsl #2 + 8008ab6: 3501 adds r5, #1 + 8008ab8: 615f str r7, [r3, #20] + 8008aba: 6125 str r5, [r4, #16] + 8008abc: 4620 mov r0, r4 + 8008abe: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + +08008ac2 <__s2b>: + 8008ac2: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} + 8008ac6: 460c mov r4, r1 + 8008ac8: 4615 mov r5, r2 + 8008aca: 461f mov r7, r3 + 8008acc: 2209 movs r2, #9 + 8008ace: 3308 adds r3, #8 + 8008ad0: 4606 mov r6, r0 + 8008ad2: fb93 f3f2 sdiv r3, r3, r2 + 8008ad6: 2100 movs r1, #0 + 8008ad8: 2201 movs r2, #1 + 8008ada: 429a cmp r2, r3 + 8008adc: db20 blt.n 8008b20 <__s2b+0x5e> + 8008ade: 4630 mov r0, r6 + 8008ae0: f7ff ff69 bl 80089b6 <_Balloc> + 8008ae4: 9b08 ldr r3, [sp, #32] + 8008ae6: 6143 str r3, [r0, #20] + 8008ae8: 2d09 cmp r5, #9 + 8008aea: f04f 0301 mov.w r3, #1 + 8008aee: 6103 str r3, [r0, #16] + 8008af0: dd19 ble.n 8008b26 <__s2b+0x64> + 8008af2: f104 0809 add.w r8, r4, #9 + 8008af6: 46c1 mov r9, r8 + 8008af8: 442c add r4, r5 + 8008afa: f819 3b01 ldrb.w r3, [r9], #1 + 8008afe: 4601 mov r1, r0 + 8008b00: 3b30 subs r3, #48 ; 0x30 + 8008b02: 220a movs r2, #10 + 8008b04: 4630 mov r0, r6 + 8008b06: f7ff ffa1 bl 8008a4c <__multadd> + 8008b0a: 45a1 cmp r9, r4 + 8008b0c: d1f5 bne.n 8008afa <__s2b+0x38> + 8008b0e: eb08 0405 add.w r4, r8, r5 + 8008b12: 3c08 subs r4, #8 + 8008b14: 1b2d subs r5, r5, r4 + 8008b16: 1963 adds r3, r4, r5 + 8008b18: 42bb cmp r3, r7 + 8008b1a: db07 blt.n 8008b2c <__s2b+0x6a> + 8008b1c: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} + 8008b20: 0052 lsls r2, r2, #1 + 8008b22: 3101 adds r1, #1 + 8008b24: e7d9 b.n 8008ada <__s2b+0x18> + 8008b26: 340a adds r4, #10 + 8008b28: 2509 movs r5, #9 + 8008b2a: e7f3 b.n 8008b14 <__s2b+0x52> + 8008b2c: f814 3b01 ldrb.w r3, [r4], #1 + 8008b30: 4601 mov r1, r0 + 8008b32: 3b30 subs r3, #48 ; 0x30 + 8008b34: 220a movs r2, #10 + 8008b36: 4630 mov r0, r6 + 8008b38: f7ff ff88 bl 8008a4c <__multadd> + 8008b3c: e7eb b.n 8008b16 <__s2b+0x54> + +08008b3e <__hi0bits>: + 8008b3e: 0c02 lsrs r2, r0, #16 + 8008b40: 0412 lsls r2, r2, #16 + 8008b42: 4603 mov r3, r0 + 8008b44: b9b2 cbnz r2, 8008b74 <__hi0bits+0x36> + 8008b46: 0403 lsls r3, r0, #16 + 8008b48: 2010 movs r0, #16 + 8008b4a: f013 4f7f tst.w r3, #4278190080 ; 0xff000000 + 8008b4e: bf04 itt eq + 8008b50: 021b lsleq r3, r3, #8 + 8008b52: 3008 addeq r0, #8 + 8008b54: f013 4f70 tst.w r3, #4026531840 ; 0xf0000000 + 8008b58: bf04 itt eq + 8008b5a: 011b lsleq r3, r3, #4 + 8008b5c: 3004 addeq r0, #4 + 8008b5e: f013 4f40 tst.w r3, #3221225472 ; 0xc0000000 + 8008b62: bf04 itt eq + 8008b64: 009b lsleq r3, r3, #2 + 8008b66: 3002 addeq r0, #2 + 8008b68: 2b00 cmp r3, #0 + 8008b6a: db06 blt.n 8008b7a <__hi0bits+0x3c> + 8008b6c: 005b lsls r3, r3, #1 + 8008b6e: d503 bpl.n 8008b78 <__hi0bits+0x3a> + 8008b70: 3001 adds r0, #1 + 8008b72: 4770 bx lr + 8008b74: 2000 movs r0, #0 + 8008b76: e7e8 b.n 8008b4a <__hi0bits+0xc> + 8008b78: 2020 movs r0, #32 + 8008b7a: 4770 bx lr + +08008b7c <__lo0bits>: + 8008b7c: 6803 ldr r3, [r0, #0] + 8008b7e: f013 0207 ands.w r2, r3, #7 + 8008b82: 4601 mov r1, r0 + 8008b84: d00b beq.n 8008b9e <__lo0bits+0x22> + 8008b86: 07da lsls r2, r3, #31 + 8008b88: d423 bmi.n 8008bd2 <__lo0bits+0x56> + 8008b8a: 0798 lsls r0, r3, #30 + 8008b8c: bf49 itett mi + 8008b8e: 085b lsrmi r3, r3, #1 + 8008b90: 089b lsrpl r3, r3, #2 + 8008b92: 2001 movmi r0, #1 + 8008b94: 600b strmi r3, [r1, #0] + 8008b96: bf5c itt pl + 8008b98: 600b strpl r3, [r1, #0] + 8008b9a: 2002 movpl r0, #2 + 8008b9c: 4770 bx lr + 8008b9e: b298 uxth r0, r3 + 8008ba0: b9a8 cbnz r0, 8008bce <__lo0bits+0x52> + 8008ba2: 0c1b lsrs r3, r3, #16 + 8008ba4: 2010 movs r0, #16 + 8008ba6: f013 0fff tst.w r3, #255 ; 0xff + 8008baa: bf04 itt eq + 8008bac: 0a1b lsreq r3, r3, #8 + 8008bae: 3008 addeq r0, #8 + 8008bb0: 071a lsls r2, r3, #28 + 8008bb2: bf04 itt eq + 8008bb4: 091b lsreq r3, r3, #4 + 8008bb6: 3004 addeq r0, #4 + 8008bb8: 079a lsls r2, r3, #30 + 8008bba: bf04 itt eq + 8008bbc: 089b lsreq r3, r3, #2 + 8008bbe: 3002 addeq r0, #2 + 8008bc0: 07da lsls r2, r3, #31 + 8008bc2: d402 bmi.n 8008bca <__lo0bits+0x4e> + 8008bc4: 085b lsrs r3, r3, #1 + 8008bc6: d006 beq.n 8008bd6 <__lo0bits+0x5a> + 8008bc8: 3001 adds r0, #1 + 8008bca: 600b str r3, [r1, #0] + 8008bcc: 4770 bx lr + 8008bce: 4610 mov r0, r2 + 8008bd0: e7e9 b.n 8008ba6 <__lo0bits+0x2a> + 8008bd2: 2000 movs r0, #0 + 8008bd4: 4770 bx lr + 8008bd6: 2020 movs r0, #32 + 8008bd8: 4770 bx lr + +08008bda <__i2b>: + 8008bda: b510 push {r4, lr} + 8008bdc: 460c mov r4, r1 + 8008bde: 2101 movs r1, #1 + 8008be0: f7ff fee9 bl 80089b6 <_Balloc> + 8008be4: 2201 movs r2, #1 + 8008be6: 6144 str r4, [r0, #20] + 8008be8: 6102 str r2, [r0, #16] + 8008bea: bd10 pop {r4, pc} + +08008bec <__multiply>: + 8008bec: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} + 8008bf0: 4614 mov r4, r2 + 8008bf2: 690a ldr r2, [r1, #16] + 8008bf4: 6923 ldr r3, [r4, #16] + 8008bf6: 429a cmp r2, r3 + 8008bf8: bfb8 it lt + 8008bfa: 460b movlt r3, r1 + 8008bfc: 4688 mov r8, r1 + 8008bfe: bfbc itt lt + 8008c00: 46a0 movlt r8, r4 + 8008c02: 461c movlt r4, r3 + 8008c04: f8d8 7010 ldr.w r7, [r8, #16] + 8008c08: f8d4 9010 ldr.w r9, [r4, #16] + 8008c0c: f8d8 3008 ldr.w r3, [r8, #8] + 8008c10: f8d8 1004 ldr.w r1, [r8, #4] + 8008c14: eb07 0609 add.w r6, r7, r9 + 8008c18: 42b3 cmp r3, r6 + 8008c1a: bfb8 it lt + 8008c1c: 3101 addlt r1, #1 + 8008c1e: f7ff feca bl 80089b6 <_Balloc> + 8008c22: f100 0514 add.w r5, r0, #20 + 8008c26: eb05 0e86 add.w lr, r5, r6, lsl #2 + 8008c2a: 462b mov r3, r5 + 8008c2c: 2200 movs r2, #0 + 8008c2e: 4573 cmp r3, lr + 8008c30: d316 bcc.n 8008c60 <__multiply+0x74> + 8008c32: f104 0214 add.w r2, r4, #20 + 8008c36: f108 0114 add.w r1, r8, #20 + 8008c3a: eb02 0389 add.w r3, r2, r9, lsl #2 + 8008c3e: eb01 0787 add.w r7, r1, r7, lsl #2 + 8008c42: 9300 str r3, [sp, #0] + 8008c44: 9b00 ldr r3, [sp, #0] + 8008c46: 9201 str r2, [sp, #4] + 8008c48: 4293 cmp r3, r2 + 8008c4a: d80c bhi.n 8008c66 <__multiply+0x7a> + 8008c4c: 2e00 cmp r6, #0 + 8008c4e: dd03 ble.n 8008c58 <__multiply+0x6c> + 8008c50: f85e 3d04 ldr.w r3, [lr, #-4]! + 8008c54: 2b00 cmp r3, #0 + 8008c56: d05d beq.n 8008d14 <__multiply+0x128> + 8008c58: 6106 str r6, [r0, #16] + 8008c5a: b003 add sp, #12 + 8008c5c: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 8008c60: f843 2b04 str.w r2, [r3], #4 + 8008c64: e7e3 b.n 8008c2e <__multiply+0x42> + 8008c66: f8b2 b000 ldrh.w fp, [r2] + 8008c6a: f1bb 0f00 cmp.w fp, #0 + 8008c6e: d023 beq.n 8008cb8 <__multiply+0xcc> + 8008c70: 4689 mov r9, r1 + 8008c72: 46ac mov ip, r5 + 8008c74: f04f 0800 mov.w r8, #0 + 8008c78: f859 4b04 ldr.w r4, [r9], #4 + 8008c7c: f8dc a000 ldr.w sl, [ip] + 8008c80: b2a3 uxth r3, r4 + 8008c82: fa1f fa8a uxth.w sl, sl + 8008c86: fb0b a303 mla r3, fp, r3, sl + 8008c8a: ea4f 4a14 mov.w sl, r4, lsr #16 + 8008c8e: f8dc 4000 ldr.w r4, [ip] + 8008c92: 4443 add r3, r8 + 8008c94: ea4f 4814 mov.w r8, r4, lsr #16 + 8008c98: fb0b 840a mla r4, fp, sl, r8 + 8008c9c: eb04 4413 add.w r4, r4, r3, lsr #16 + 8008ca0: 46e2 mov sl, ip + 8008ca2: b29b uxth r3, r3 + 8008ca4: ea43 4304 orr.w r3, r3, r4, lsl #16 + 8008ca8: 454f cmp r7, r9 + 8008caa: ea4f 4814 mov.w r8, r4, lsr #16 + 8008cae: f84a 3b04 str.w r3, [sl], #4 + 8008cb2: d82b bhi.n 8008d0c <__multiply+0x120> + 8008cb4: f8cc 8004 str.w r8, [ip, #4] + 8008cb8: 9b01 ldr r3, [sp, #4] + 8008cba: f8b3 a002 ldrh.w sl, [r3, #2] + 8008cbe: 3204 adds r2, #4 + 8008cc0: f1ba 0f00 cmp.w sl, #0 + 8008cc4: d020 beq.n 8008d08 <__multiply+0x11c> + 8008cc6: 682b ldr r3, [r5, #0] + 8008cc8: 4689 mov r9, r1 + 8008cca: 46a8 mov r8, r5 + 8008ccc: f04f 0b00 mov.w fp, #0 + 8008cd0: f8b9 c000 ldrh.w ip, [r9] + 8008cd4: f8b8 4002 ldrh.w r4, [r8, #2] + 8008cd8: fb0a 440c mla r4, sl, ip, r4 + 8008cdc: 445c add r4, fp + 8008cde: 46c4 mov ip, r8 + 8008ce0: b29b uxth r3, r3 + 8008ce2: ea43 4304 orr.w r3, r3, r4, lsl #16 + 8008ce6: f84c 3b04 str.w r3, [ip], #4 + 8008cea: f859 3b04 ldr.w r3, [r9], #4 + 8008cee: f8b8 b004 ldrh.w fp, [r8, #4] + 8008cf2: 0c1b lsrs r3, r3, #16 + 8008cf4: fb0a b303 mla r3, sl, r3, fp + 8008cf8: eb03 4314 add.w r3, r3, r4, lsr #16 + 8008cfc: 454f cmp r7, r9 + 8008cfe: ea4f 4b13 mov.w fp, r3, lsr #16 + 8008d02: d805 bhi.n 8008d10 <__multiply+0x124> + 8008d04: f8c8 3004 str.w r3, [r8, #4] + 8008d08: 3504 adds r5, #4 + 8008d0a: e79b b.n 8008c44 <__multiply+0x58> + 8008d0c: 46d4 mov ip, sl + 8008d0e: e7b3 b.n 8008c78 <__multiply+0x8c> + 8008d10: 46e0 mov r8, ip + 8008d12: e7dd b.n 8008cd0 <__multiply+0xe4> + 8008d14: 3e01 subs r6, #1 + 8008d16: e799 b.n 8008c4c <__multiply+0x60> + +08008d18 <__pow5mult>: + 8008d18: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} + 8008d1c: 4615 mov r5, r2 + 8008d1e: f012 0203 ands.w r2, r2, #3 + 8008d22: 4606 mov r6, r0 + 8008d24: 460f mov r7, r1 + 8008d26: d007 beq.n 8008d38 <__pow5mult+0x20> + 8008d28: 3a01 subs r2, #1 + 8008d2a: 4c21 ldr r4, [pc, #132] ; (8008db0 <__pow5mult+0x98>) + 8008d2c: 2300 movs r3, #0 + 8008d2e: f854 2022 ldr.w r2, [r4, r2, lsl #2] + 8008d32: f7ff fe8b bl 8008a4c <__multadd> + 8008d36: 4607 mov r7, r0 + 8008d38: 10ad asrs r5, r5, #2 + 8008d3a: d035 beq.n 8008da8 <__pow5mult+0x90> + 8008d3c: 6a74 ldr r4, [r6, #36] ; 0x24 + 8008d3e: b93c cbnz r4, 8008d50 <__pow5mult+0x38> + 8008d40: 2010 movs r0, #16 + 8008d42: f7fc fb9b bl 800547c + 8008d46: 6270 str r0, [r6, #36] ; 0x24 + 8008d48: e9c0 4401 strd r4, r4, [r0, #4] + 8008d4c: 6004 str r4, [r0, #0] + 8008d4e: 60c4 str r4, [r0, #12] + 8008d50: f8d6 8024 ldr.w r8, [r6, #36] ; 0x24 + 8008d54: f8d8 4008 ldr.w r4, [r8, #8] + 8008d58: b94c cbnz r4, 8008d6e <__pow5mult+0x56> + 8008d5a: f240 2171 movw r1, #625 ; 0x271 + 8008d5e: 4630 mov r0, r6 + 8008d60: f7ff ff3b bl 8008bda <__i2b> + 8008d64: 2300 movs r3, #0 + 8008d66: f8c8 0008 str.w r0, [r8, #8] + 8008d6a: 4604 mov r4, r0 + 8008d6c: 6003 str r3, [r0, #0] + 8008d6e: f04f 0800 mov.w r8, #0 + 8008d72: 07eb lsls r3, r5, #31 + 8008d74: d50a bpl.n 8008d8c <__pow5mult+0x74> + 8008d76: 4639 mov r1, r7 + 8008d78: 4622 mov r2, r4 + 8008d7a: 4630 mov r0, r6 + 8008d7c: f7ff ff36 bl 8008bec <__multiply> + 8008d80: 4639 mov r1, r7 + 8008d82: 4681 mov r9, r0 + 8008d84: 4630 mov r0, r6 + 8008d86: f7ff fe4a bl 8008a1e <_Bfree> + 8008d8a: 464f mov r7, r9 + 8008d8c: 106d asrs r5, r5, #1 + 8008d8e: d00b beq.n 8008da8 <__pow5mult+0x90> + 8008d90: 6820 ldr r0, [r4, #0] + 8008d92: b938 cbnz r0, 8008da4 <__pow5mult+0x8c> + 8008d94: 4622 mov r2, r4 + 8008d96: 4621 mov r1, r4 + 8008d98: 4630 mov r0, r6 + 8008d9a: f7ff ff27 bl 8008bec <__multiply> + 8008d9e: 6020 str r0, [r4, #0] + 8008da0: f8c0 8000 str.w r8, [r0] + 8008da4: 4604 mov r4, r0 + 8008da6: e7e4 b.n 8008d72 <__pow5mult+0x5a> + 8008da8: 4638 mov r0, r7 + 8008daa: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} + 8008dae: bf00 nop + 8008db0: 08009c30 .word 0x08009c30 + +08008db4 <__lshift>: + 8008db4: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 8008db8: 460c mov r4, r1 + 8008dba: ea4f 1a62 mov.w sl, r2, asr #5 + 8008dbe: 6923 ldr r3, [r4, #16] + 8008dc0: 6849 ldr r1, [r1, #4] + 8008dc2: eb0a 0903 add.w r9, sl, r3 + 8008dc6: 68a3 ldr r3, [r4, #8] + 8008dc8: 4607 mov r7, r0 + 8008dca: 4616 mov r6, r2 + 8008dcc: f109 0501 add.w r5, r9, #1 + 8008dd0: 42ab cmp r3, r5 + 8008dd2: db32 blt.n 8008e3a <__lshift+0x86> + 8008dd4: 4638 mov r0, r7 + 8008dd6: f7ff fdee bl 80089b6 <_Balloc> + 8008dda: 2300 movs r3, #0 + 8008ddc: 4680 mov r8, r0 + 8008dde: f100 0114 add.w r1, r0, #20 + 8008de2: 461a mov r2, r3 + 8008de4: 4553 cmp r3, sl + 8008de6: db2b blt.n 8008e40 <__lshift+0x8c> + 8008de8: 6920 ldr r0, [r4, #16] + 8008dea: ea2a 7aea bic.w sl, sl, sl, asr #31 + 8008dee: f104 0314 add.w r3, r4, #20 + 8008df2: f016 021f ands.w r2, r6, #31 + 8008df6: eb01 018a add.w r1, r1, sl, lsl #2 + 8008dfa: eb03 0c80 add.w ip, r3, r0, lsl #2 + 8008dfe: d025 beq.n 8008e4c <__lshift+0x98> + 8008e00: f1c2 0e20 rsb lr, r2, #32 + 8008e04: 2000 movs r0, #0 + 8008e06: 681e ldr r6, [r3, #0] + 8008e08: 468a mov sl, r1 + 8008e0a: 4096 lsls r6, r2 + 8008e0c: 4330 orrs r0, r6 + 8008e0e: f84a 0b04 str.w r0, [sl], #4 + 8008e12: f853 0b04 ldr.w r0, [r3], #4 + 8008e16: 459c cmp ip, r3 + 8008e18: fa20 f00e lsr.w r0, r0, lr + 8008e1c: d814 bhi.n 8008e48 <__lshift+0x94> + 8008e1e: 6048 str r0, [r1, #4] + 8008e20: b108 cbz r0, 8008e26 <__lshift+0x72> + 8008e22: f109 0502 add.w r5, r9, #2 + 8008e26: 3d01 subs r5, #1 + 8008e28: 4638 mov r0, r7 + 8008e2a: f8c8 5010 str.w r5, [r8, #16] + 8008e2e: 4621 mov r1, r4 + 8008e30: f7ff fdf5 bl 8008a1e <_Bfree> + 8008e34: 4640 mov r0, r8 + 8008e36: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 8008e3a: 3101 adds r1, #1 + 8008e3c: 005b lsls r3, r3, #1 + 8008e3e: e7c7 b.n 8008dd0 <__lshift+0x1c> + 8008e40: f841 2023 str.w r2, [r1, r3, lsl #2] + 8008e44: 3301 adds r3, #1 + 8008e46: e7cd b.n 8008de4 <__lshift+0x30> + 8008e48: 4651 mov r1, sl + 8008e4a: e7dc b.n 8008e06 <__lshift+0x52> + 8008e4c: 3904 subs r1, #4 + 8008e4e: f853 2b04 ldr.w r2, [r3], #4 + 8008e52: f841 2f04 str.w r2, [r1, #4]! + 8008e56: 459c cmp ip, r3 + 8008e58: d8f9 bhi.n 8008e4e <__lshift+0x9a> + 8008e5a: e7e4 b.n 8008e26 <__lshift+0x72> + +08008e5c <__mcmp>: + 8008e5c: 6903 ldr r3, [r0, #16] + 8008e5e: 690a ldr r2, [r1, #16] + 8008e60: 1a9b subs r3, r3, r2 + 8008e62: b530 push {r4, r5, lr} + 8008e64: d10c bne.n 8008e80 <__mcmp+0x24> + 8008e66: 0092 lsls r2, r2, #2 + 8008e68: 3014 adds r0, #20 + 8008e6a: 3114 adds r1, #20 + 8008e6c: 1884 adds r4, r0, r2 + 8008e6e: 4411 add r1, r2 + 8008e70: f854 5d04 ldr.w r5, [r4, #-4]! + 8008e74: f851 2d04 ldr.w r2, [r1, #-4]! + 8008e78: 4295 cmp r5, r2 + 8008e7a: d003 beq.n 8008e84 <__mcmp+0x28> + 8008e7c: d305 bcc.n 8008e8a <__mcmp+0x2e> + 8008e7e: 2301 movs r3, #1 + 8008e80: 4618 mov r0, r3 + 8008e82: bd30 pop {r4, r5, pc} + 8008e84: 42a0 cmp r0, r4 + 8008e86: d3f3 bcc.n 8008e70 <__mcmp+0x14> + 8008e88: e7fa b.n 8008e80 <__mcmp+0x24> + 8008e8a: f04f 33ff mov.w r3, #4294967295 + 8008e8e: e7f7 b.n 8008e80 <__mcmp+0x24> + +08008e90 <__mdiff>: + 8008e90: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 8008e94: 460d mov r5, r1 + 8008e96: 4607 mov r7, r0 + 8008e98: 4611 mov r1, r2 + 8008e9a: 4628 mov r0, r5 + 8008e9c: 4614 mov r4, r2 + 8008e9e: f7ff ffdd bl 8008e5c <__mcmp> + 8008ea2: 1e06 subs r6, r0, #0 + 8008ea4: d108 bne.n 8008eb8 <__mdiff+0x28> + 8008ea6: 4631 mov r1, r6 + 8008ea8: 4638 mov r0, r7 + 8008eaa: f7ff fd84 bl 80089b6 <_Balloc> + 8008eae: 2301 movs r3, #1 + 8008eb0: e9c0 3604 strd r3, r6, [r0, #16] + 8008eb4: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 8008eb8: bfa4 itt ge + 8008eba: 4623 movge r3, r4 + 8008ebc: 462c movge r4, r5 + 8008ebe: 4638 mov r0, r7 + 8008ec0: 6861 ldr r1, [r4, #4] + 8008ec2: bfa6 itte ge + 8008ec4: 461d movge r5, r3 + 8008ec6: 2600 movge r6, #0 + 8008ec8: 2601 movlt r6, #1 + 8008eca: f7ff fd74 bl 80089b6 <_Balloc> + 8008ece: 692b ldr r3, [r5, #16] + 8008ed0: 60c6 str r6, [r0, #12] + 8008ed2: 6926 ldr r6, [r4, #16] + 8008ed4: f105 0914 add.w r9, r5, #20 + 8008ed8: f104 0214 add.w r2, r4, #20 + 8008edc: eb02 0786 add.w r7, r2, r6, lsl #2 + 8008ee0: eb09 0883 add.w r8, r9, r3, lsl #2 + 8008ee4: f100 0514 add.w r5, r0, #20 + 8008ee8: f04f 0e00 mov.w lr, #0 + 8008eec: f852 ab04 ldr.w sl, [r2], #4 + 8008ef0: f859 4b04 ldr.w r4, [r9], #4 + 8008ef4: fa1e f18a uxtah r1, lr, sl + 8008ef8: b2a3 uxth r3, r4 + 8008efa: 1ac9 subs r1, r1, r3 + 8008efc: 0c23 lsrs r3, r4, #16 + 8008efe: ebc3 431a rsb r3, r3, sl, lsr #16 + 8008f02: eb03 4321 add.w r3, r3, r1, asr #16 + 8008f06: b289 uxth r1, r1 + 8008f08: ea4f 4e23 mov.w lr, r3, asr #16 + 8008f0c: 45c8 cmp r8, r9 + 8008f0e: ea41 4303 orr.w r3, r1, r3, lsl #16 + 8008f12: 4694 mov ip, r2 + 8008f14: f845 3b04 str.w r3, [r5], #4 + 8008f18: d8e8 bhi.n 8008eec <__mdiff+0x5c> + 8008f1a: 45bc cmp ip, r7 + 8008f1c: d304 bcc.n 8008f28 <__mdiff+0x98> + 8008f1e: f855 3d04 ldr.w r3, [r5, #-4]! + 8008f22: b183 cbz r3, 8008f46 <__mdiff+0xb6> + 8008f24: 6106 str r6, [r0, #16] + 8008f26: e7c5 b.n 8008eb4 <__mdiff+0x24> + 8008f28: f85c 1b04 ldr.w r1, [ip], #4 + 8008f2c: fa1e f381 uxtah r3, lr, r1 + 8008f30: 141a asrs r2, r3, #16 + 8008f32: eb02 4211 add.w r2, r2, r1, lsr #16 + 8008f36: b29b uxth r3, r3 + 8008f38: ea43 4302 orr.w r3, r3, r2, lsl #16 + 8008f3c: ea4f 4e22 mov.w lr, r2, asr #16 + 8008f40: f845 3b04 str.w r3, [r5], #4 + 8008f44: e7e9 b.n 8008f1a <__mdiff+0x8a> + 8008f46: 3e01 subs r6, #1 + 8008f48: e7e9 b.n 8008f1e <__mdiff+0x8e> + ... + +08008f4c <__ulp>: + 8008f4c: 4b12 ldr r3, [pc, #72] ; (8008f98 <__ulp+0x4c>) + 8008f4e: ee10 2a90 vmov r2, s1 + 8008f52: 401a ands r2, r3 + 8008f54: f1a2 7350 sub.w r3, r2, #54525952 ; 0x3400000 + 8008f58: 2b00 cmp r3, #0 + 8008f5a: dd04 ble.n 8008f66 <__ulp+0x1a> + 8008f5c: 2000 movs r0, #0 + 8008f5e: 4619 mov r1, r3 + 8008f60: ec41 0b10 vmov d0, r0, r1 + 8008f64: 4770 bx lr + 8008f66: 425b negs r3, r3 + 8008f68: 151b asrs r3, r3, #20 + 8008f6a: 2b13 cmp r3, #19 + 8008f6c: f04f 0000 mov.w r0, #0 + 8008f70: f04f 0100 mov.w r1, #0 + 8008f74: dc04 bgt.n 8008f80 <__ulp+0x34> + 8008f76: f44f 2200 mov.w r2, #524288 ; 0x80000 + 8008f7a: fa42 f103 asr.w r1, r2, r3 + 8008f7e: e7ef b.n 8008f60 <__ulp+0x14> + 8008f80: 3b14 subs r3, #20 + 8008f82: 2b1e cmp r3, #30 + 8008f84: f04f 0201 mov.w r2, #1 + 8008f88: bfda itte le + 8008f8a: f1c3 031f rsble r3, r3, #31 + 8008f8e: fa02 f303 lslle.w r3, r2, r3 + 8008f92: 4613 movgt r3, r2 + 8008f94: 4618 mov r0, r3 + 8008f96: e7e3 b.n 8008f60 <__ulp+0x14> + 8008f98: 7ff00000 .word 0x7ff00000 + +08008f9c <__b2d>: + 8008f9c: b5f8 push {r3, r4, r5, r6, r7, lr} + 8008f9e: 6905 ldr r5, [r0, #16] + 8008fa0: f100 0714 add.w r7, r0, #20 + 8008fa4: eb07 0585 add.w r5, r7, r5, lsl #2 + 8008fa8: 1f2e subs r6, r5, #4 + 8008faa: f855 4c04 ldr.w r4, [r5, #-4] + 8008fae: 4620 mov r0, r4 + 8008fb0: f7ff fdc5 bl 8008b3e <__hi0bits> + 8008fb4: f1c0 0320 rsb r3, r0, #32 + 8008fb8: 280a cmp r0, #10 + 8008fba: 600b str r3, [r1, #0] + 8008fbc: f8df c074 ldr.w ip, [pc, #116] ; 8009034 <__b2d+0x98> + 8008fc0: dc14 bgt.n 8008fec <__b2d+0x50> + 8008fc2: f1c0 0e0b rsb lr, r0, #11 + 8008fc6: fa24 f10e lsr.w r1, r4, lr + 8008fca: 42b7 cmp r7, r6 + 8008fcc: ea41 030c orr.w r3, r1, ip + 8008fd0: bf34 ite cc + 8008fd2: f855 1c08 ldrcc.w r1, [r5, #-8] + 8008fd6: 2100 movcs r1, #0 + 8008fd8: 3015 adds r0, #21 + 8008fda: fa04 f000 lsl.w r0, r4, r0 + 8008fde: fa21 f10e lsr.w r1, r1, lr + 8008fe2: ea40 0201 orr.w r2, r0, r1 + 8008fe6: ec43 2b10 vmov d0, r2, r3 + 8008fea: bdf8 pop {r3, r4, r5, r6, r7, pc} + 8008fec: 42b7 cmp r7, r6 + 8008fee: bf3a itte cc + 8008ff0: f1a5 0608 subcc.w r6, r5, #8 + 8008ff4: f855 1c08 ldrcc.w r1, [r5, #-8] + 8008ff8: 2100 movcs r1, #0 + 8008ffa: 380b subs r0, #11 + 8008ffc: d015 beq.n 800902a <__b2d+0x8e> + 8008ffe: 4084 lsls r4, r0 + 8009000: f1c0 0520 rsb r5, r0, #32 + 8009004: f044 547f orr.w r4, r4, #1069547520 ; 0x3fc00000 + 8009008: f444 1440 orr.w r4, r4, #3145728 ; 0x300000 + 800900c: 42be cmp r6, r7 + 800900e: fa21 fc05 lsr.w ip, r1, r5 + 8009012: ea44 030c orr.w r3, r4, ip + 8009016: bf8c ite hi + 8009018: f856 4c04 ldrhi.w r4, [r6, #-4] + 800901c: 2400 movls r4, #0 + 800901e: fa01 f000 lsl.w r0, r1, r0 + 8009022: 40ec lsrs r4, r5 + 8009024: ea40 0204 orr.w r2, r0, r4 + 8009028: e7dd b.n 8008fe6 <__b2d+0x4a> + 800902a: ea44 030c orr.w r3, r4, ip + 800902e: 460a mov r2, r1 + 8009030: e7d9 b.n 8008fe6 <__b2d+0x4a> + 8009032: bf00 nop + 8009034: 3ff00000 .word 0x3ff00000 + +08009038 <__d2b>: + 8009038: e92d 43f7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr} + 800903c: 460e mov r6, r1 + 800903e: 2101 movs r1, #1 + 8009040: ec59 8b10 vmov r8, r9, d0 + 8009044: 4615 mov r5, r2 + 8009046: f7ff fcb6 bl 80089b6 <_Balloc> + 800904a: f3c9 540a ubfx r4, r9, #20, #11 + 800904e: 4607 mov r7, r0 + 8009050: f3c9 0313 ubfx r3, r9, #0, #20 + 8009054: bb34 cbnz r4, 80090a4 <__d2b+0x6c> + 8009056: 9301 str r3, [sp, #4] + 8009058: f1b8 0300 subs.w r3, r8, #0 + 800905c: d027 beq.n 80090ae <__d2b+0x76> + 800905e: a802 add r0, sp, #8 + 8009060: f840 3d08 str.w r3, [r0, #-8]! + 8009064: f7ff fd8a bl 8008b7c <__lo0bits> + 8009068: 9900 ldr r1, [sp, #0] + 800906a: b1f0 cbz r0, 80090aa <__d2b+0x72> + 800906c: 9a01 ldr r2, [sp, #4] + 800906e: f1c0 0320 rsb r3, r0, #32 + 8009072: fa02 f303 lsl.w r3, r2, r3 + 8009076: 430b orrs r3, r1 + 8009078: 40c2 lsrs r2, r0 + 800907a: 617b str r3, [r7, #20] + 800907c: 9201 str r2, [sp, #4] + 800907e: 9b01 ldr r3, [sp, #4] + 8009080: 61bb str r3, [r7, #24] + 8009082: 2b00 cmp r3, #0 + 8009084: bf14 ite ne + 8009086: 2102 movne r1, #2 + 8009088: 2101 moveq r1, #1 + 800908a: 6139 str r1, [r7, #16] + 800908c: b1c4 cbz r4, 80090c0 <__d2b+0x88> + 800908e: f2a4 4433 subw r4, r4, #1075 ; 0x433 + 8009092: 4404 add r4, r0 + 8009094: 6034 str r4, [r6, #0] + 8009096: f1c0 0035 rsb r0, r0, #53 ; 0x35 + 800909a: 6028 str r0, [r5, #0] + 800909c: 4638 mov r0, r7 + 800909e: b003 add sp, #12 + 80090a0: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} + 80090a4: f443 1380 orr.w r3, r3, #1048576 ; 0x100000 + 80090a8: e7d5 b.n 8009056 <__d2b+0x1e> + 80090aa: 6179 str r1, [r7, #20] + 80090ac: e7e7 b.n 800907e <__d2b+0x46> + 80090ae: a801 add r0, sp, #4 + 80090b0: f7ff fd64 bl 8008b7c <__lo0bits> + 80090b4: 9b01 ldr r3, [sp, #4] + 80090b6: 617b str r3, [r7, #20] + 80090b8: 2101 movs r1, #1 + 80090ba: 6139 str r1, [r7, #16] + 80090bc: 3020 adds r0, #32 + 80090be: e7e5 b.n 800908c <__d2b+0x54> + 80090c0: eb07 0381 add.w r3, r7, r1, lsl #2 + 80090c4: f2a0 4032 subw r0, r0, #1074 ; 0x432 + 80090c8: 6030 str r0, [r6, #0] + 80090ca: 6918 ldr r0, [r3, #16] + 80090cc: f7ff fd37 bl 8008b3e <__hi0bits> + 80090d0: ebc0 1041 rsb r0, r0, r1, lsl #5 + 80090d4: e7e1 b.n 800909a <__d2b+0x62> + +080090d6 <__ratio>: + 80090d6: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} + 80090da: 4688 mov r8, r1 + 80090dc: 4669 mov r1, sp + 80090de: 4681 mov r9, r0 + 80090e0: f7ff ff5c bl 8008f9c <__b2d> + 80090e4: a901 add r1, sp, #4 + 80090e6: 4640 mov r0, r8 + 80090e8: ec57 6b10 vmov r6, r7, d0 + 80090ec: f7ff ff56 bl 8008f9c <__b2d> + 80090f0: f8d9 3010 ldr.w r3, [r9, #16] + 80090f4: f8d8 2010 ldr.w r2, [r8, #16] + 80090f8: eba3 0c02 sub.w ip, r3, r2 + 80090fc: e9dd 3200 ldrd r3, r2, [sp] + 8009100: 1a9b subs r3, r3, r2 + 8009102: eb03 134c add.w r3, r3, ip, lsl #5 + 8009106: ec5b ab10 vmov sl, fp, d0 + 800910a: 2b00 cmp r3, #0 + 800910c: bfce itee gt + 800910e: 463a movgt r2, r7 + 8009110: ebc3 3303 rsble r3, r3, r3, lsl #12 + 8009114: 465a movle r2, fp + 8009116: 4659 mov r1, fp + 8009118: 463d mov r5, r7 + 800911a: bfd4 ite le + 800911c: eb02 5103 addle.w r1, r2, r3, lsl #20 + 8009120: eb02 5503 addgt.w r5, r2, r3, lsl #20 + 8009124: 4630 mov r0, r6 + 8009126: ee10 2a10 vmov r2, s0 + 800912a: 460b mov r3, r1 + 800912c: 4629 mov r1, r5 + 800912e: f7f7 fb95 bl 800085c <__aeabi_ddiv> + 8009132: ec41 0b10 vmov d0, r0, r1 + 8009136: b003 add sp, #12 + 8009138: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + +0800913c <__copybits>: + 800913c: 3901 subs r1, #1 + 800913e: b510 push {r4, lr} + 8009140: 1149 asrs r1, r1, #5 + 8009142: 6914 ldr r4, [r2, #16] + 8009144: 3101 adds r1, #1 + 8009146: f102 0314 add.w r3, r2, #20 + 800914a: eb00 0181 add.w r1, r0, r1, lsl #2 + 800914e: eb03 0484 add.w r4, r3, r4, lsl #2 + 8009152: 42a3 cmp r3, r4 + 8009154: 4602 mov r2, r0 + 8009156: d303 bcc.n 8009160 <__copybits+0x24> + 8009158: 2300 movs r3, #0 + 800915a: 428a cmp r2, r1 + 800915c: d305 bcc.n 800916a <__copybits+0x2e> + 800915e: bd10 pop {r4, pc} + 8009160: f853 2b04 ldr.w r2, [r3], #4 + 8009164: f840 2b04 str.w r2, [r0], #4 + 8009168: e7f3 b.n 8009152 <__copybits+0x16> + 800916a: f842 3b04 str.w r3, [r2], #4 + 800916e: e7f4 b.n 800915a <__copybits+0x1e> + +08009170 <__any_on>: + 8009170: f100 0214 add.w r2, r0, #20 + 8009174: 6900 ldr r0, [r0, #16] + 8009176: 114b asrs r3, r1, #5 + 8009178: 4298 cmp r0, r3 + 800917a: b510 push {r4, lr} + 800917c: db11 blt.n 80091a2 <__any_on+0x32> + 800917e: dd0a ble.n 8009196 <__any_on+0x26> + 8009180: f011 011f ands.w r1, r1, #31 + 8009184: d007 beq.n 8009196 <__any_on+0x26> + 8009186: f852 4023 ldr.w r4, [r2, r3, lsl #2] + 800918a: fa24 f001 lsr.w r0, r4, r1 + 800918e: fa00 f101 lsl.w r1, r0, r1 + 8009192: 428c cmp r4, r1 + 8009194: d10b bne.n 80091ae <__any_on+0x3e> + 8009196: eb02 0383 add.w r3, r2, r3, lsl #2 + 800919a: 4293 cmp r3, r2 + 800919c: d803 bhi.n 80091a6 <__any_on+0x36> + 800919e: 2000 movs r0, #0 + 80091a0: bd10 pop {r4, pc} + 80091a2: 4603 mov r3, r0 + 80091a4: e7f7 b.n 8009196 <__any_on+0x26> + 80091a6: f853 1d04 ldr.w r1, [r3, #-4]! + 80091aa: 2900 cmp r1, #0 + 80091ac: d0f5 beq.n 800919a <__any_on+0x2a> + 80091ae: 2001 movs r0, #1 + 80091b0: e7f6 b.n 80091a0 <__any_on+0x30> + +080091b2 <_calloc_r>: + 80091b2: b538 push {r3, r4, r5, lr} + 80091b4: fb02 f401 mul.w r4, r2, r1 + 80091b8: 4621 mov r1, r4 + 80091ba: f7fc f9c5 bl 8005548 <_malloc_r> + 80091be: 4605 mov r5, r0 + 80091c0: b118 cbz r0, 80091ca <_calloc_r+0x18> + 80091c2: 4622 mov r2, r4 + 80091c4: 2100 movs r1, #0 + 80091c6: f7fc f969 bl 800549c + 80091ca: 4628 mov r0, r5 + 80091cc: bd38 pop {r3, r4, r5, pc} + +080091ce <__ssputs_r>: + 80091ce: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 80091d2: 688e ldr r6, [r1, #8] + 80091d4: 429e cmp r6, r3 + 80091d6: 4682 mov sl, r0 + 80091d8: 460c mov r4, r1 + 80091da: 4690 mov r8, r2 + 80091dc: 4699 mov r9, r3 + 80091de: d837 bhi.n 8009250 <__ssputs_r+0x82> + 80091e0: 898a ldrh r2, [r1, #12] + 80091e2: f412 6f90 tst.w r2, #1152 ; 0x480 + 80091e6: d031 beq.n 800924c <__ssputs_r+0x7e> + 80091e8: 6825 ldr r5, [r4, #0] + 80091ea: 6909 ldr r1, [r1, #16] + 80091ec: 1a6f subs r7, r5, r1 + 80091ee: 6965 ldr r5, [r4, #20] + 80091f0: 2302 movs r3, #2 + 80091f2: eb05 0545 add.w r5, r5, r5, lsl #1 + 80091f6: fb95 f5f3 sdiv r5, r5, r3 + 80091fa: f109 0301 add.w r3, r9, #1 + 80091fe: 443b add r3, r7 + 8009200: 429d cmp r5, r3 + 8009202: bf38 it cc + 8009204: 461d movcc r5, r3 + 8009206: 0553 lsls r3, r2, #21 + 8009208: d530 bpl.n 800926c <__ssputs_r+0x9e> + 800920a: 4629 mov r1, r5 + 800920c: f7fc f99c bl 8005548 <_malloc_r> + 8009210: 4606 mov r6, r0 + 8009212: b950 cbnz r0, 800922a <__ssputs_r+0x5c> + 8009214: 230c movs r3, #12 + 8009216: f8ca 3000 str.w r3, [sl] + 800921a: 89a3 ldrh r3, [r4, #12] + 800921c: f043 0340 orr.w r3, r3, #64 ; 0x40 + 8009220: 81a3 strh r3, [r4, #12] + 8009222: f04f 30ff mov.w r0, #4294967295 + 8009226: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 800922a: 463a mov r2, r7 + 800922c: 6921 ldr r1, [r4, #16] + 800922e: f7ff fbb5 bl 800899c + 8009232: 89a3 ldrh r3, [r4, #12] + 8009234: f423 6390 bic.w r3, r3, #1152 ; 0x480 + 8009238: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800923c: 81a3 strh r3, [r4, #12] + 800923e: 6126 str r6, [r4, #16] + 8009240: 6165 str r5, [r4, #20] + 8009242: 443e add r6, r7 + 8009244: 1bed subs r5, r5, r7 + 8009246: 6026 str r6, [r4, #0] + 8009248: 60a5 str r5, [r4, #8] + 800924a: 464e mov r6, r9 + 800924c: 454e cmp r6, r9 + 800924e: d900 bls.n 8009252 <__ssputs_r+0x84> + 8009250: 464e mov r6, r9 + 8009252: 4632 mov r2, r6 + 8009254: 4641 mov r1, r8 + 8009256: 6820 ldr r0, [r4, #0] + 8009258: f000 fb04 bl 8009864 + 800925c: 68a3 ldr r3, [r4, #8] + 800925e: 1b9b subs r3, r3, r6 + 8009260: 60a3 str r3, [r4, #8] + 8009262: 6823 ldr r3, [r4, #0] + 8009264: 441e add r6, r3 + 8009266: 6026 str r6, [r4, #0] + 8009268: 2000 movs r0, #0 + 800926a: e7dc b.n 8009226 <__ssputs_r+0x58> + 800926c: 462a mov r2, r5 + 800926e: f000 fb12 bl 8009896 <_realloc_r> + 8009272: 4606 mov r6, r0 + 8009274: 2800 cmp r0, #0 + 8009276: d1e2 bne.n 800923e <__ssputs_r+0x70> + 8009278: 6921 ldr r1, [r4, #16] + 800927a: 4650 mov r0, sl + 800927c: f7fc f916 bl 80054ac <_free_r> + 8009280: e7c8 b.n 8009214 <__ssputs_r+0x46> + ... + +08009284 <_svfiprintf_r>: + 8009284: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 8009288: 461d mov r5, r3 + 800928a: 898b ldrh r3, [r1, #12] + 800928c: 061f lsls r7, r3, #24 + 800928e: b09d sub sp, #116 ; 0x74 + 8009290: 4680 mov r8, r0 + 8009292: 460c mov r4, r1 + 8009294: 4616 mov r6, r2 + 8009296: d50f bpl.n 80092b8 <_svfiprintf_r+0x34> + 8009298: 690b ldr r3, [r1, #16] + 800929a: b96b cbnz r3, 80092b8 <_svfiprintf_r+0x34> + 800929c: 2140 movs r1, #64 ; 0x40 + 800929e: f7fc f953 bl 8005548 <_malloc_r> + 80092a2: 6020 str r0, [r4, #0] + 80092a4: 6120 str r0, [r4, #16] + 80092a6: b928 cbnz r0, 80092b4 <_svfiprintf_r+0x30> + 80092a8: 230c movs r3, #12 + 80092aa: f8c8 3000 str.w r3, [r8] + 80092ae: f04f 30ff mov.w r0, #4294967295 + 80092b2: e0c8 b.n 8009446 <_svfiprintf_r+0x1c2> + 80092b4: 2340 movs r3, #64 ; 0x40 + 80092b6: 6163 str r3, [r4, #20] + 80092b8: 2300 movs r3, #0 + 80092ba: 9309 str r3, [sp, #36] ; 0x24 + 80092bc: 2320 movs r3, #32 + 80092be: f88d 3029 strb.w r3, [sp, #41] ; 0x29 + 80092c2: 2330 movs r3, #48 ; 0x30 + 80092c4: f88d 302a strb.w r3, [sp, #42] ; 0x2a + 80092c8: 9503 str r5, [sp, #12] + 80092ca: f04f 0b01 mov.w fp, #1 + 80092ce: 4637 mov r7, r6 + 80092d0: 463d mov r5, r7 + 80092d2: f815 3b01 ldrb.w r3, [r5], #1 + 80092d6: b10b cbz r3, 80092dc <_svfiprintf_r+0x58> + 80092d8: 2b25 cmp r3, #37 ; 0x25 + 80092da: d13e bne.n 800935a <_svfiprintf_r+0xd6> + 80092dc: ebb7 0a06 subs.w sl, r7, r6 + 80092e0: d00b beq.n 80092fa <_svfiprintf_r+0x76> + 80092e2: 4653 mov r3, sl + 80092e4: 4632 mov r2, r6 + 80092e6: 4621 mov r1, r4 + 80092e8: 4640 mov r0, r8 + 80092ea: f7ff ff70 bl 80091ce <__ssputs_r> + 80092ee: 3001 adds r0, #1 + 80092f0: f000 80a4 beq.w 800943c <_svfiprintf_r+0x1b8> + 80092f4: 9b09 ldr r3, [sp, #36] ; 0x24 + 80092f6: 4453 add r3, sl + 80092f8: 9309 str r3, [sp, #36] ; 0x24 + 80092fa: 783b ldrb r3, [r7, #0] + 80092fc: 2b00 cmp r3, #0 + 80092fe: f000 809d beq.w 800943c <_svfiprintf_r+0x1b8> + 8009302: 2300 movs r3, #0 + 8009304: f04f 32ff mov.w r2, #4294967295 + 8009308: e9cd 2305 strd r2, r3, [sp, #20] + 800930c: 9304 str r3, [sp, #16] + 800930e: 9307 str r3, [sp, #28] + 8009310: f88d 3053 strb.w r3, [sp, #83] ; 0x53 + 8009314: 931a str r3, [sp, #104] ; 0x68 + 8009316: 462f mov r7, r5 + 8009318: 2205 movs r2, #5 + 800931a: f817 1b01 ldrb.w r1, [r7], #1 + 800931e: 4850 ldr r0, [pc, #320] ; (8009460 <_svfiprintf_r+0x1dc>) + 8009320: f7f6 ff66 bl 80001f0 + 8009324: 9b04 ldr r3, [sp, #16] + 8009326: b9d0 cbnz r0, 800935e <_svfiprintf_r+0xda> + 8009328: 06d9 lsls r1, r3, #27 + 800932a: bf44 itt mi + 800932c: 2220 movmi r2, #32 + 800932e: f88d 2053 strbmi.w r2, [sp, #83] ; 0x53 + 8009332: 071a lsls r2, r3, #28 + 8009334: bf44 itt mi + 8009336: 222b movmi r2, #43 ; 0x2b + 8009338: f88d 2053 strbmi.w r2, [sp, #83] ; 0x53 + 800933c: 782a ldrb r2, [r5, #0] + 800933e: 2a2a cmp r2, #42 ; 0x2a + 8009340: d015 beq.n 800936e <_svfiprintf_r+0xea> + 8009342: 9a07 ldr r2, [sp, #28] + 8009344: 462f mov r7, r5 + 8009346: 2000 movs r0, #0 + 8009348: 250a movs r5, #10 + 800934a: 4639 mov r1, r7 + 800934c: f811 3b01 ldrb.w r3, [r1], #1 + 8009350: 3b30 subs r3, #48 ; 0x30 + 8009352: 2b09 cmp r3, #9 + 8009354: d94d bls.n 80093f2 <_svfiprintf_r+0x16e> + 8009356: b1b8 cbz r0, 8009388 <_svfiprintf_r+0x104> + 8009358: e00f b.n 800937a <_svfiprintf_r+0xf6> + 800935a: 462f mov r7, r5 + 800935c: e7b8 b.n 80092d0 <_svfiprintf_r+0x4c> + 800935e: 4a40 ldr r2, [pc, #256] ; (8009460 <_svfiprintf_r+0x1dc>) + 8009360: 1a80 subs r0, r0, r2 + 8009362: fa0b f000 lsl.w r0, fp, r0 + 8009366: 4318 orrs r0, r3 + 8009368: 9004 str r0, [sp, #16] + 800936a: 463d mov r5, r7 + 800936c: e7d3 b.n 8009316 <_svfiprintf_r+0x92> + 800936e: 9a03 ldr r2, [sp, #12] + 8009370: 1d11 adds r1, r2, #4 + 8009372: 6812 ldr r2, [r2, #0] + 8009374: 9103 str r1, [sp, #12] + 8009376: 2a00 cmp r2, #0 + 8009378: db01 blt.n 800937e <_svfiprintf_r+0xfa> + 800937a: 9207 str r2, [sp, #28] + 800937c: e004 b.n 8009388 <_svfiprintf_r+0x104> + 800937e: 4252 negs r2, r2 + 8009380: f043 0302 orr.w r3, r3, #2 + 8009384: 9207 str r2, [sp, #28] + 8009386: 9304 str r3, [sp, #16] + 8009388: 783b ldrb r3, [r7, #0] + 800938a: 2b2e cmp r3, #46 ; 0x2e + 800938c: d10c bne.n 80093a8 <_svfiprintf_r+0x124> + 800938e: 787b ldrb r3, [r7, #1] + 8009390: 2b2a cmp r3, #42 ; 0x2a + 8009392: d133 bne.n 80093fc <_svfiprintf_r+0x178> + 8009394: 9b03 ldr r3, [sp, #12] + 8009396: 1d1a adds r2, r3, #4 + 8009398: 681b ldr r3, [r3, #0] + 800939a: 9203 str r2, [sp, #12] + 800939c: 2b00 cmp r3, #0 + 800939e: bfb8 it lt + 80093a0: f04f 33ff movlt.w r3, #4294967295 + 80093a4: 3702 adds r7, #2 + 80093a6: 9305 str r3, [sp, #20] + 80093a8: 4d2e ldr r5, [pc, #184] ; (8009464 <_svfiprintf_r+0x1e0>) + 80093aa: 7839 ldrb r1, [r7, #0] + 80093ac: 2203 movs r2, #3 + 80093ae: 4628 mov r0, r5 + 80093b0: f7f6 ff1e bl 80001f0 + 80093b4: b138 cbz r0, 80093c6 <_svfiprintf_r+0x142> + 80093b6: 2340 movs r3, #64 ; 0x40 + 80093b8: 1b40 subs r0, r0, r5 + 80093ba: fa03 f000 lsl.w r0, r3, r0 + 80093be: 9b04 ldr r3, [sp, #16] + 80093c0: 4303 orrs r3, r0 + 80093c2: 3701 adds r7, #1 + 80093c4: 9304 str r3, [sp, #16] + 80093c6: 7839 ldrb r1, [r7, #0] + 80093c8: 4827 ldr r0, [pc, #156] ; (8009468 <_svfiprintf_r+0x1e4>) + 80093ca: f88d 1028 strb.w r1, [sp, #40] ; 0x28 + 80093ce: 2206 movs r2, #6 + 80093d0: 1c7e adds r6, r7, #1 + 80093d2: f7f6 ff0d bl 80001f0 + 80093d6: 2800 cmp r0, #0 + 80093d8: d038 beq.n 800944c <_svfiprintf_r+0x1c8> + 80093da: 4b24 ldr r3, [pc, #144] ; (800946c <_svfiprintf_r+0x1e8>) + 80093dc: bb13 cbnz r3, 8009424 <_svfiprintf_r+0x1a0> + 80093de: 9b03 ldr r3, [sp, #12] + 80093e0: 3307 adds r3, #7 + 80093e2: f023 0307 bic.w r3, r3, #7 + 80093e6: 3308 adds r3, #8 + 80093e8: 9303 str r3, [sp, #12] + 80093ea: 9b09 ldr r3, [sp, #36] ; 0x24 + 80093ec: 444b add r3, r9 + 80093ee: 9309 str r3, [sp, #36] ; 0x24 + 80093f0: e76d b.n 80092ce <_svfiprintf_r+0x4a> + 80093f2: fb05 3202 mla r2, r5, r2, r3 + 80093f6: 2001 movs r0, #1 + 80093f8: 460f mov r7, r1 + 80093fa: e7a6 b.n 800934a <_svfiprintf_r+0xc6> + 80093fc: 2300 movs r3, #0 + 80093fe: 3701 adds r7, #1 + 8009400: 9305 str r3, [sp, #20] + 8009402: 4619 mov r1, r3 + 8009404: 250a movs r5, #10 + 8009406: 4638 mov r0, r7 + 8009408: f810 2b01 ldrb.w r2, [r0], #1 + 800940c: 3a30 subs r2, #48 ; 0x30 + 800940e: 2a09 cmp r2, #9 + 8009410: d903 bls.n 800941a <_svfiprintf_r+0x196> + 8009412: 2b00 cmp r3, #0 + 8009414: d0c8 beq.n 80093a8 <_svfiprintf_r+0x124> + 8009416: 9105 str r1, [sp, #20] + 8009418: e7c6 b.n 80093a8 <_svfiprintf_r+0x124> + 800941a: fb05 2101 mla r1, r5, r1, r2 + 800941e: 2301 movs r3, #1 + 8009420: 4607 mov r7, r0 + 8009422: e7f0 b.n 8009406 <_svfiprintf_r+0x182> + 8009424: ab03 add r3, sp, #12 + 8009426: 9300 str r3, [sp, #0] + 8009428: 4622 mov r2, r4 + 800942a: 4b11 ldr r3, [pc, #68] ; (8009470 <_svfiprintf_r+0x1ec>) + 800942c: a904 add r1, sp, #16 + 800942e: 4640 mov r0, r8 + 8009430: f7fc f978 bl 8005724 <_printf_float> + 8009434: f1b0 3fff cmp.w r0, #4294967295 + 8009438: 4681 mov r9, r0 + 800943a: d1d6 bne.n 80093ea <_svfiprintf_r+0x166> + 800943c: 89a3 ldrh r3, [r4, #12] + 800943e: 065b lsls r3, r3, #25 + 8009440: f53f af35 bmi.w 80092ae <_svfiprintf_r+0x2a> + 8009444: 9809 ldr r0, [sp, #36] ; 0x24 + 8009446: b01d add sp, #116 ; 0x74 + 8009448: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 800944c: ab03 add r3, sp, #12 + 800944e: 9300 str r3, [sp, #0] + 8009450: 4622 mov r2, r4 + 8009452: 4b07 ldr r3, [pc, #28] ; (8009470 <_svfiprintf_r+0x1ec>) + 8009454: a904 add r1, sp, #16 + 8009456: 4640 mov r0, r8 + 8009458: f7fc fc1a bl 8005c90 <_printf_i> + 800945c: e7ea b.n 8009434 <_svfiprintf_r+0x1b0> + 800945e: bf00 nop + 8009460: 08009c3c .word 0x08009c3c + 8009464: 08009c42 .word 0x08009c42 + 8009468: 08009c46 .word 0x08009c46 + 800946c: 08005725 .word 0x08005725 + 8009470: 080091cf .word 0x080091cf + +08009474 <__sfputc_r>: + 8009474: 6893 ldr r3, [r2, #8] + 8009476: 3b01 subs r3, #1 + 8009478: 2b00 cmp r3, #0 + 800947a: b410 push {r4} + 800947c: 6093 str r3, [r2, #8] + 800947e: da08 bge.n 8009492 <__sfputc_r+0x1e> + 8009480: 6994 ldr r4, [r2, #24] + 8009482: 42a3 cmp r3, r4 + 8009484: db01 blt.n 800948a <__sfputc_r+0x16> + 8009486: 290a cmp r1, #10 + 8009488: d103 bne.n 8009492 <__sfputc_r+0x1e> + 800948a: f85d 4b04 ldr.w r4, [sp], #4 + 800948e: f7fd be55 b.w 800713c <__swbuf_r> + 8009492: 6813 ldr r3, [r2, #0] + 8009494: 1c58 adds r0, r3, #1 + 8009496: 6010 str r0, [r2, #0] + 8009498: 7019 strb r1, [r3, #0] + 800949a: 4608 mov r0, r1 + 800949c: f85d 4b04 ldr.w r4, [sp], #4 + 80094a0: 4770 bx lr + +080094a2 <__sfputs_r>: + 80094a2: b5f8 push {r3, r4, r5, r6, r7, lr} + 80094a4: 4606 mov r6, r0 + 80094a6: 460f mov r7, r1 + 80094a8: 4614 mov r4, r2 + 80094aa: 18d5 adds r5, r2, r3 + 80094ac: 42ac cmp r4, r5 + 80094ae: d101 bne.n 80094b4 <__sfputs_r+0x12> + 80094b0: 2000 movs r0, #0 + 80094b2: e007 b.n 80094c4 <__sfputs_r+0x22> + 80094b4: 463a mov r2, r7 + 80094b6: f814 1b01 ldrb.w r1, [r4], #1 + 80094ba: 4630 mov r0, r6 + 80094bc: f7ff ffda bl 8009474 <__sfputc_r> + 80094c0: 1c43 adds r3, r0, #1 + 80094c2: d1f3 bne.n 80094ac <__sfputs_r+0xa> + 80094c4: bdf8 pop {r3, r4, r5, r6, r7, pc} + ... + +080094c8 <_vfiprintf_r>: + 80094c8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 80094cc: 460c mov r4, r1 + 80094ce: b09d sub sp, #116 ; 0x74 + 80094d0: 4617 mov r7, r2 + 80094d2: 461d mov r5, r3 + 80094d4: 4606 mov r6, r0 + 80094d6: b118 cbz r0, 80094e0 <_vfiprintf_r+0x18> + 80094d8: 6983 ldr r3, [r0, #24] + 80094da: b90b cbnz r3, 80094e0 <_vfiprintf_r+0x18> + 80094dc: f7fe fe24 bl 8008128 <__sinit> + 80094e0: 4b7c ldr r3, [pc, #496] ; (80096d4 <_vfiprintf_r+0x20c>) + 80094e2: 429c cmp r4, r3 + 80094e4: d158 bne.n 8009598 <_vfiprintf_r+0xd0> + 80094e6: 6874 ldr r4, [r6, #4] + 80094e8: 89a3 ldrh r3, [r4, #12] + 80094ea: 0718 lsls r0, r3, #28 + 80094ec: d55e bpl.n 80095ac <_vfiprintf_r+0xe4> + 80094ee: 6923 ldr r3, [r4, #16] + 80094f0: 2b00 cmp r3, #0 + 80094f2: d05b beq.n 80095ac <_vfiprintf_r+0xe4> + 80094f4: 2300 movs r3, #0 + 80094f6: 9309 str r3, [sp, #36] ; 0x24 + 80094f8: 2320 movs r3, #32 + 80094fa: f88d 3029 strb.w r3, [sp, #41] ; 0x29 + 80094fe: 2330 movs r3, #48 ; 0x30 + 8009500: f88d 302a strb.w r3, [sp, #42] ; 0x2a + 8009504: 9503 str r5, [sp, #12] + 8009506: f04f 0b01 mov.w fp, #1 + 800950a: 46b8 mov r8, r7 + 800950c: 4645 mov r5, r8 + 800950e: f815 3b01 ldrb.w r3, [r5], #1 + 8009512: b10b cbz r3, 8009518 <_vfiprintf_r+0x50> + 8009514: 2b25 cmp r3, #37 ; 0x25 + 8009516: d154 bne.n 80095c2 <_vfiprintf_r+0xfa> + 8009518: ebb8 0a07 subs.w sl, r8, r7 + 800951c: d00b beq.n 8009536 <_vfiprintf_r+0x6e> + 800951e: 4653 mov r3, sl + 8009520: 463a mov r2, r7 + 8009522: 4621 mov r1, r4 + 8009524: 4630 mov r0, r6 + 8009526: f7ff ffbc bl 80094a2 <__sfputs_r> + 800952a: 3001 adds r0, #1 + 800952c: f000 80c2 beq.w 80096b4 <_vfiprintf_r+0x1ec> + 8009530: 9b09 ldr r3, [sp, #36] ; 0x24 + 8009532: 4453 add r3, sl + 8009534: 9309 str r3, [sp, #36] ; 0x24 + 8009536: f898 3000 ldrb.w r3, [r8] + 800953a: 2b00 cmp r3, #0 + 800953c: f000 80ba beq.w 80096b4 <_vfiprintf_r+0x1ec> + 8009540: 2300 movs r3, #0 + 8009542: f04f 32ff mov.w r2, #4294967295 + 8009546: e9cd 2305 strd r2, r3, [sp, #20] + 800954a: 9304 str r3, [sp, #16] + 800954c: 9307 str r3, [sp, #28] + 800954e: f88d 3053 strb.w r3, [sp, #83] ; 0x53 + 8009552: 931a str r3, [sp, #104] ; 0x68 + 8009554: 46a8 mov r8, r5 + 8009556: 2205 movs r2, #5 + 8009558: f818 1b01 ldrb.w r1, [r8], #1 + 800955c: 485e ldr r0, [pc, #376] ; (80096d8 <_vfiprintf_r+0x210>) + 800955e: f7f6 fe47 bl 80001f0 + 8009562: 9b04 ldr r3, [sp, #16] + 8009564: bb78 cbnz r0, 80095c6 <_vfiprintf_r+0xfe> + 8009566: 06d9 lsls r1, r3, #27 + 8009568: bf44 itt mi + 800956a: 2220 movmi r2, #32 + 800956c: f88d 2053 strbmi.w r2, [sp, #83] ; 0x53 + 8009570: 071a lsls r2, r3, #28 + 8009572: bf44 itt mi + 8009574: 222b movmi r2, #43 ; 0x2b + 8009576: f88d 2053 strbmi.w r2, [sp, #83] ; 0x53 + 800957a: 782a ldrb r2, [r5, #0] + 800957c: 2a2a cmp r2, #42 ; 0x2a + 800957e: d02a beq.n 80095d6 <_vfiprintf_r+0x10e> + 8009580: 9a07 ldr r2, [sp, #28] + 8009582: 46a8 mov r8, r5 + 8009584: 2000 movs r0, #0 + 8009586: 250a movs r5, #10 + 8009588: 4641 mov r1, r8 + 800958a: f811 3b01 ldrb.w r3, [r1], #1 + 800958e: 3b30 subs r3, #48 ; 0x30 + 8009590: 2b09 cmp r3, #9 + 8009592: d969 bls.n 8009668 <_vfiprintf_r+0x1a0> + 8009594: b360 cbz r0, 80095f0 <_vfiprintf_r+0x128> + 8009596: e024 b.n 80095e2 <_vfiprintf_r+0x11a> + 8009598: 4b50 ldr r3, [pc, #320] ; (80096dc <_vfiprintf_r+0x214>) + 800959a: 429c cmp r4, r3 + 800959c: d101 bne.n 80095a2 <_vfiprintf_r+0xda> + 800959e: 68b4 ldr r4, [r6, #8] + 80095a0: e7a2 b.n 80094e8 <_vfiprintf_r+0x20> + 80095a2: 4b4f ldr r3, [pc, #316] ; (80096e0 <_vfiprintf_r+0x218>) + 80095a4: 429c cmp r4, r3 + 80095a6: bf08 it eq + 80095a8: 68f4 ldreq r4, [r6, #12] + 80095aa: e79d b.n 80094e8 <_vfiprintf_r+0x20> + 80095ac: 4621 mov r1, r4 + 80095ae: 4630 mov r0, r6 + 80095b0: f7fd fe16 bl 80071e0 <__swsetup_r> + 80095b4: 2800 cmp r0, #0 + 80095b6: d09d beq.n 80094f4 <_vfiprintf_r+0x2c> + 80095b8: f04f 30ff mov.w r0, #4294967295 + 80095bc: b01d add sp, #116 ; 0x74 + 80095be: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 80095c2: 46a8 mov r8, r5 + 80095c4: e7a2 b.n 800950c <_vfiprintf_r+0x44> + 80095c6: 4a44 ldr r2, [pc, #272] ; (80096d8 <_vfiprintf_r+0x210>) + 80095c8: 1a80 subs r0, r0, r2 + 80095ca: fa0b f000 lsl.w r0, fp, r0 + 80095ce: 4318 orrs r0, r3 + 80095d0: 9004 str r0, [sp, #16] + 80095d2: 4645 mov r5, r8 + 80095d4: e7be b.n 8009554 <_vfiprintf_r+0x8c> + 80095d6: 9a03 ldr r2, [sp, #12] + 80095d8: 1d11 adds r1, r2, #4 + 80095da: 6812 ldr r2, [r2, #0] + 80095dc: 9103 str r1, [sp, #12] + 80095de: 2a00 cmp r2, #0 + 80095e0: db01 blt.n 80095e6 <_vfiprintf_r+0x11e> + 80095e2: 9207 str r2, [sp, #28] + 80095e4: e004 b.n 80095f0 <_vfiprintf_r+0x128> + 80095e6: 4252 negs r2, r2 + 80095e8: f043 0302 orr.w r3, r3, #2 + 80095ec: 9207 str r2, [sp, #28] + 80095ee: 9304 str r3, [sp, #16] + 80095f0: f898 3000 ldrb.w r3, [r8] + 80095f4: 2b2e cmp r3, #46 ; 0x2e + 80095f6: d10e bne.n 8009616 <_vfiprintf_r+0x14e> + 80095f8: f898 3001 ldrb.w r3, [r8, #1] + 80095fc: 2b2a cmp r3, #42 ; 0x2a + 80095fe: d138 bne.n 8009672 <_vfiprintf_r+0x1aa> + 8009600: 9b03 ldr r3, [sp, #12] + 8009602: 1d1a adds r2, r3, #4 + 8009604: 681b ldr r3, [r3, #0] + 8009606: 9203 str r2, [sp, #12] + 8009608: 2b00 cmp r3, #0 + 800960a: bfb8 it lt + 800960c: f04f 33ff movlt.w r3, #4294967295 + 8009610: f108 0802 add.w r8, r8, #2 + 8009614: 9305 str r3, [sp, #20] + 8009616: 4d33 ldr r5, [pc, #204] ; (80096e4 <_vfiprintf_r+0x21c>) + 8009618: f898 1000 ldrb.w r1, [r8] + 800961c: 2203 movs r2, #3 + 800961e: 4628 mov r0, r5 + 8009620: f7f6 fde6 bl 80001f0 + 8009624: b140 cbz r0, 8009638 <_vfiprintf_r+0x170> + 8009626: 2340 movs r3, #64 ; 0x40 + 8009628: 1b40 subs r0, r0, r5 + 800962a: fa03 f000 lsl.w r0, r3, r0 + 800962e: 9b04 ldr r3, [sp, #16] + 8009630: 4303 orrs r3, r0 + 8009632: f108 0801 add.w r8, r8, #1 + 8009636: 9304 str r3, [sp, #16] + 8009638: f898 1000 ldrb.w r1, [r8] + 800963c: 482a ldr r0, [pc, #168] ; (80096e8 <_vfiprintf_r+0x220>) + 800963e: f88d 1028 strb.w r1, [sp, #40] ; 0x28 + 8009642: 2206 movs r2, #6 + 8009644: f108 0701 add.w r7, r8, #1 + 8009648: f7f6 fdd2 bl 80001f0 + 800964c: 2800 cmp r0, #0 + 800964e: d037 beq.n 80096c0 <_vfiprintf_r+0x1f8> + 8009650: 4b26 ldr r3, [pc, #152] ; (80096ec <_vfiprintf_r+0x224>) + 8009652: bb1b cbnz r3, 800969c <_vfiprintf_r+0x1d4> + 8009654: 9b03 ldr r3, [sp, #12] + 8009656: 3307 adds r3, #7 + 8009658: f023 0307 bic.w r3, r3, #7 + 800965c: 3308 adds r3, #8 + 800965e: 9303 str r3, [sp, #12] + 8009660: 9b09 ldr r3, [sp, #36] ; 0x24 + 8009662: 444b add r3, r9 + 8009664: 9309 str r3, [sp, #36] ; 0x24 + 8009666: e750 b.n 800950a <_vfiprintf_r+0x42> + 8009668: fb05 3202 mla r2, r5, r2, r3 + 800966c: 2001 movs r0, #1 + 800966e: 4688 mov r8, r1 + 8009670: e78a b.n 8009588 <_vfiprintf_r+0xc0> + 8009672: 2300 movs r3, #0 + 8009674: f108 0801 add.w r8, r8, #1 + 8009678: 9305 str r3, [sp, #20] + 800967a: 4619 mov r1, r3 + 800967c: 250a movs r5, #10 + 800967e: 4640 mov r0, r8 + 8009680: f810 2b01 ldrb.w r2, [r0], #1 + 8009684: 3a30 subs r2, #48 ; 0x30 + 8009686: 2a09 cmp r2, #9 + 8009688: d903 bls.n 8009692 <_vfiprintf_r+0x1ca> + 800968a: 2b00 cmp r3, #0 + 800968c: d0c3 beq.n 8009616 <_vfiprintf_r+0x14e> + 800968e: 9105 str r1, [sp, #20] + 8009690: e7c1 b.n 8009616 <_vfiprintf_r+0x14e> + 8009692: fb05 2101 mla r1, r5, r1, r2 + 8009696: 2301 movs r3, #1 + 8009698: 4680 mov r8, r0 + 800969a: e7f0 b.n 800967e <_vfiprintf_r+0x1b6> + 800969c: ab03 add r3, sp, #12 + 800969e: 9300 str r3, [sp, #0] + 80096a0: 4622 mov r2, r4 + 80096a2: 4b13 ldr r3, [pc, #76] ; (80096f0 <_vfiprintf_r+0x228>) + 80096a4: a904 add r1, sp, #16 + 80096a6: 4630 mov r0, r6 + 80096a8: f7fc f83c bl 8005724 <_printf_float> + 80096ac: f1b0 3fff cmp.w r0, #4294967295 + 80096b0: 4681 mov r9, r0 + 80096b2: d1d5 bne.n 8009660 <_vfiprintf_r+0x198> + 80096b4: 89a3 ldrh r3, [r4, #12] + 80096b6: 065b lsls r3, r3, #25 + 80096b8: f53f af7e bmi.w 80095b8 <_vfiprintf_r+0xf0> + 80096bc: 9809 ldr r0, [sp, #36] ; 0x24 + 80096be: e77d b.n 80095bc <_vfiprintf_r+0xf4> + 80096c0: ab03 add r3, sp, #12 + 80096c2: 9300 str r3, [sp, #0] + 80096c4: 4622 mov r2, r4 + 80096c6: 4b0a ldr r3, [pc, #40] ; (80096f0 <_vfiprintf_r+0x228>) + 80096c8: a904 add r1, sp, #16 + 80096ca: 4630 mov r0, r6 + 80096cc: f7fc fae0 bl 8005c90 <_printf_i> + 80096d0: e7ec b.n 80096ac <_vfiprintf_r+0x1e4> + 80096d2: bf00 nop + 80096d4: 08009af8 .word 0x08009af8 + 80096d8: 08009c3c .word 0x08009c3c + 80096dc: 08009b18 .word 0x08009b18 + 80096e0: 08009ad8 .word 0x08009ad8 + 80096e4: 08009c42 .word 0x08009c42 + 80096e8: 08009c46 .word 0x08009c46 + 80096ec: 08005725 .word 0x08005725 + 80096f0: 080094a3 .word 0x080094a3 + +080096f4 <__sread>: + 80096f4: b510 push {r4, lr} + 80096f6: 460c mov r4, r1 + 80096f8: f9b1 100e ldrsh.w r1, [r1, #14] + 80096fc: f000 f8f2 bl 80098e4 <_read_r> + 8009700: 2800 cmp r0, #0 + 8009702: bfab itete ge + 8009704: 6d63 ldrge r3, [r4, #84] ; 0x54 + 8009706: 89a3 ldrhlt r3, [r4, #12] + 8009708: 181b addge r3, r3, r0 + 800970a: f423 5380 biclt.w r3, r3, #4096 ; 0x1000 + 800970e: bfac ite ge + 8009710: 6563 strge r3, [r4, #84] ; 0x54 + 8009712: 81a3 strhlt r3, [r4, #12] + 8009714: bd10 pop {r4, pc} + +08009716 <__swrite>: + 8009716: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 800971a: 461f mov r7, r3 + 800971c: 898b ldrh r3, [r1, #12] + 800971e: 05db lsls r3, r3, #23 + 8009720: 4605 mov r5, r0 + 8009722: 460c mov r4, r1 + 8009724: 4616 mov r6, r2 + 8009726: d505 bpl.n 8009734 <__swrite+0x1e> + 8009728: 2302 movs r3, #2 + 800972a: 2200 movs r2, #0 + 800972c: f9b1 100e ldrsh.w r1, [r1, #14] + 8009730: f000 f886 bl 8009840 <_lseek_r> + 8009734: 89a3 ldrh r3, [r4, #12] + 8009736: f9b4 100e ldrsh.w r1, [r4, #14] + 800973a: f423 5380 bic.w r3, r3, #4096 ; 0x1000 + 800973e: 81a3 strh r3, [r4, #12] + 8009740: 4632 mov r2, r6 + 8009742: 463b mov r3, r7 + 8009744: 4628 mov r0, r5 + 8009746: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} + 800974a: f000 b835 b.w 80097b8 <_write_r> + +0800974e <__sseek>: + 800974e: b510 push {r4, lr} + 8009750: 460c mov r4, r1 + 8009752: f9b1 100e ldrsh.w r1, [r1, #14] + 8009756: f000 f873 bl 8009840 <_lseek_r> + 800975a: 1c43 adds r3, r0, #1 + 800975c: 89a3 ldrh r3, [r4, #12] + 800975e: bf15 itete ne + 8009760: 6560 strne r0, [r4, #84] ; 0x54 + 8009762: f423 5380 biceq.w r3, r3, #4096 ; 0x1000 + 8009766: f443 5380 orrne.w r3, r3, #4096 ; 0x1000 + 800976a: 81a3 strheq r3, [r4, #12] + 800976c: bf18 it ne + 800976e: 81a3 strhne r3, [r4, #12] + 8009770: bd10 pop {r4, pc} + +08009772 <__sclose>: + 8009772: f9b1 100e ldrsh.w r1, [r1, #14] + 8009776: f000 b831 b.w 80097dc <_close_r> + +0800977a : + 800977a: b510 push {r4, lr} + 800977c: b16a cbz r2, 800979a + 800977e: 3901 subs r1, #1 + 8009780: 1884 adds r4, r0, r2 + 8009782: f810 3b01 ldrb.w r3, [r0], #1 + 8009786: f811 2f01 ldrb.w r2, [r1, #1]! + 800978a: 4293 cmp r3, r2 + 800978c: d103 bne.n 8009796 + 800978e: 42a0 cmp r0, r4 + 8009790: d001 beq.n 8009796 + 8009792: 2b00 cmp r3, #0 + 8009794: d1f5 bne.n 8009782 + 8009796: 1a98 subs r0, r3, r2 + 8009798: bd10 pop {r4, pc} + 800979a: 4610 mov r0, r2 + 800979c: e7fc b.n 8009798 + +0800979e <__ascii_wctomb>: + 800979e: b149 cbz r1, 80097b4 <__ascii_wctomb+0x16> + 80097a0: 2aff cmp r2, #255 ; 0xff + 80097a2: bf85 ittet hi + 80097a4: 238a movhi r3, #138 ; 0x8a + 80097a6: 6003 strhi r3, [r0, #0] + 80097a8: 700a strbls r2, [r1, #0] + 80097aa: f04f 30ff movhi.w r0, #4294967295 + 80097ae: bf98 it ls + 80097b0: 2001 movls r0, #1 + 80097b2: 4770 bx lr + 80097b4: 4608 mov r0, r1 + 80097b6: 4770 bx lr + +080097b8 <_write_r>: + 80097b8: b538 push {r3, r4, r5, lr} + 80097ba: 4c07 ldr r4, [pc, #28] ; (80097d8 <_write_r+0x20>) + 80097bc: 4605 mov r5, r0 + 80097be: 4608 mov r0, r1 + 80097c0: 4611 mov r1, r2 + 80097c2: 2200 movs r2, #0 + 80097c4: 6022 str r2, [r4, #0] + 80097c6: 461a mov r2, r3 + 80097c8: f7f7 ffb8 bl 800173c <_write> + 80097cc: 1c43 adds r3, r0, #1 + 80097ce: d102 bne.n 80097d6 <_write_r+0x1e> + 80097d0: 6823 ldr r3, [r4, #0] + 80097d2: b103 cbz r3, 80097d6 <_write_r+0x1e> + 80097d4: 602b str r3, [r5, #0] + 80097d6: bd38 pop {r3, r4, r5, pc} + 80097d8: 20000ab0 .word 0x20000ab0 + +080097dc <_close_r>: + 80097dc: b538 push {r3, r4, r5, lr} + 80097de: 4c06 ldr r4, [pc, #24] ; (80097f8 <_close_r+0x1c>) + 80097e0: 2300 movs r3, #0 + 80097e2: 4605 mov r5, r0 + 80097e4: 4608 mov r0, r1 + 80097e6: 6023 str r3, [r4, #0] + 80097e8: f7f7 ffb6 bl 8001758 <_close> + 80097ec: 1c43 adds r3, r0, #1 + 80097ee: d102 bne.n 80097f6 <_close_r+0x1a> + 80097f0: 6823 ldr r3, [r4, #0] + 80097f2: b103 cbz r3, 80097f6 <_close_r+0x1a> + 80097f4: 602b str r3, [r5, #0] + 80097f6: bd38 pop {r3, r4, r5, pc} + 80097f8: 20000ab0 .word 0x20000ab0 + +080097fc <_fstat_r>: + 80097fc: b538 push {r3, r4, r5, lr} + 80097fe: 4c07 ldr r4, [pc, #28] ; (800981c <_fstat_r+0x20>) + 8009800: 2300 movs r3, #0 + 8009802: 4605 mov r5, r0 + 8009804: 4608 mov r0, r1 + 8009806: 4611 mov r1, r2 + 8009808: 6023 str r3, [r4, #0] + 800980a: f7f7 ffa8 bl 800175e <_fstat> + 800980e: 1c43 adds r3, r0, #1 + 8009810: d102 bne.n 8009818 <_fstat_r+0x1c> + 8009812: 6823 ldr r3, [r4, #0] + 8009814: b103 cbz r3, 8009818 <_fstat_r+0x1c> + 8009816: 602b str r3, [r5, #0] + 8009818: bd38 pop {r3, r4, r5, pc} + 800981a: bf00 nop + 800981c: 20000ab0 .word 0x20000ab0 + +08009820 <_isatty_r>: + 8009820: b538 push {r3, r4, r5, lr} + 8009822: 4c06 ldr r4, [pc, #24] ; (800983c <_isatty_r+0x1c>) + 8009824: 2300 movs r3, #0 + 8009826: 4605 mov r5, r0 + 8009828: 4608 mov r0, r1 + 800982a: 6023 str r3, [r4, #0] + 800982c: f7f7 ff9c bl 8001768 <_isatty> + 8009830: 1c43 adds r3, r0, #1 + 8009832: d102 bne.n 800983a <_isatty_r+0x1a> + 8009834: 6823 ldr r3, [r4, #0] + 8009836: b103 cbz r3, 800983a <_isatty_r+0x1a> + 8009838: 602b str r3, [r5, #0] + 800983a: bd38 pop {r3, r4, r5, pc} + 800983c: 20000ab0 .word 0x20000ab0 + +08009840 <_lseek_r>: + 8009840: b538 push {r3, r4, r5, lr} + 8009842: 4c07 ldr r4, [pc, #28] ; (8009860 <_lseek_r+0x20>) + 8009844: 4605 mov r5, r0 + 8009846: 4608 mov r0, r1 + 8009848: 4611 mov r1, r2 + 800984a: 2200 movs r2, #0 + 800984c: 6022 str r2, [r4, #0] + 800984e: 461a mov r2, r3 + 8009850: f7f7 ff8c bl 800176c <_lseek> + 8009854: 1c43 adds r3, r0, #1 + 8009856: d102 bne.n 800985e <_lseek_r+0x1e> + 8009858: 6823 ldr r3, [r4, #0] + 800985a: b103 cbz r3, 800985e <_lseek_r+0x1e> + 800985c: 602b str r3, [r5, #0] + 800985e: bd38 pop {r3, r4, r5, pc} + 8009860: 20000ab0 .word 0x20000ab0 + +08009864 : + 8009864: 4288 cmp r0, r1 + 8009866: b510 push {r4, lr} + 8009868: eb01 0302 add.w r3, r1, r2 + 800986c: d807 bhi.n 800987e + 800986e: 1e42 subs r2, r0, #1 + 8009870: 4299 cmp r1, r3 + 8009872: d00a beq.n 800988a + 8009874: f811 4b01 ldrb.w r4, [r1], #1 + 8009878: f802 4f01 strb.w r4, [r2, #1]! + 800987c: e7f8 b.n 8009870 + 800987e: 4283 cmp r3, r0 + 8009880: d9f5 bls.n 800986e + 8009882: 1881 adds r1, r0, r2 + 8009884: 1ad2 subs r2, r2, r3 + 8009886: 42d3 cmn r3, r2 + 8009888: d100 bne.n 800988c + 800988a: bd10 pop {r4, pc} + 800988c: f813 4d01 ldrb.w r4, [r3, #-1]! + 8009890: f801 4d01 strb.w r4, [r1, #-1]! + 8009894: e7f7 b.n 8009886 + +08009896 <_realloc_r>: + 8009896: b5f8 push {r3, r4, r5, r6, r7, lr} + 8009898: 4607 mov r7, r0 + 800989a: 4614 mov r4, r2 + 800989c: 460e mov r6, r1 + 800989e: b921 cbnz r1, 80098aa <_realloc_r+0x14> + 80098a0: 4611 mov r1, r2 + 80098a2: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr} + 80098a6: f7fb be4f b.w 8005548 <_malloc_r> + 80098aa: b922 cbnz r2, 80098b6 <_realloc_r+0x20> + 80098ac: f7fb fdfe bl 80054ac <_free_r> + 80098b0: 4625 mov r5, r4 + 80098b2: 4628 mov r0, r5 + 80098b4: bdf8 pop {r3, r4, r5, r6, r7, pc} + 80098b6: f000 f827 bl 8009908 <_malloc_usable_size_r> + 80098ba: 42a0 cmp r0, r4 + 80098bc: d20f bcs.n 80098de <_realloc_r+0x48> + 80098be: 4621 mov r1, r4 + 80098c0: 4638 mov r0, r7 + 80098c2: f7fb fe41 bl 8005548 <_malloc_r> + 80098c6: 4605 mov r5, r0 + 80098c8: 2800 cmp r0, #0 + 80098ca: d0f2 beq.n 80098b2 <_realloc_r+0x1c> + 80098cc: 4631 mov r1, r6 + 80098ce: 4622 mov r2, r4 + 80098d0: f7ff f864 bl 800899c + 80098d4: 4631 mov r1, r6 + 80098d6: 4638 mov r0, r7 + 80098d8: f7fb fde8 bl 80054ac <_free_r> + 80098dc: e7e9 b.n 80098b2 <_realloc_r+0x1c> + 80098de: 4635 mov r5, r6 + 80098e0: e7e7 b.n 80098b2 <_realloc_r+0x1c> + ... + +080098e4 <_read_r>: + 80098e4: b538 push {r3, r4, r5, lr} + 80098e6: 4c07 ldr r4, [pc, #28] ; (8009904 <_read_r+0x20>) + 80098e8: 4605 mov r5, r0 + 80098ea: 4608 mov r0, r1 + 80098ec: 4611 mov r1, r2 + 80098ee: 2200 movs r2, #0 + 80098f0: 6022 str r2, [r4, #0] + 80098f2: 461a mov r2, r3 + 80098f4: f7f7 ff14 bl 8001720 <_read> + 80098f8: 1c43 adds r3, r0, #1 + 80098fa: d102 bne.n 8009902 <_read_r+0x1e> + 80098fc: 6823 ldr r3, [r4, #0] + 80098fe: b103 cbz r3, 8009902 <_read_r+0x1e> + 8009900: 602b str r3, [r5, #0] + 8009902: bd38 pop {r3, r4, r5, pc} + 8009904: 20000ab0 .word 0x20000ab0 + +08009908 <_malloc_usable_size_r>: + 8009908: f851 3c04 ldr.w r3, [r1, #-4] + 800990c: 1f18 subs r0, r3, #4 + 800990e: 2b00 cmp r3, #0 + 8009910: bfbc itt lt + 8009912: 580b ldrlt r3, [r1, r0] + 8009914: 18c0 addlt r0, r0, r3 + 8009916: 4770 bx lr + +08009918 <_init>: + 8009918: b5f8 push {r3, r4, r5, r6, r7, lr} + 800991a: bf00 nop + 800991c: bcf8 pop {r3, r4, r5, r6, r7} + 800991e: bc08 pop {r3} + 8009920: 469e mov lr, r3 + 8009922: 4770 bx lr + +08009924 <_fini>: + 8009924: b5f8 push {r3, r4, r5, r6, r7, lr} + 8009926: bf00 nop + 8009928: bcf8 pop {r3, r4, r5, r6, r7} + 800992a: bc08 pop {r3} + 800992c: 469e mov lr, r3 + 800992e: 4770 bx lr diff --git a/Release/makefile b/Release/makefile new file mode 100644 index 0000000..4c2252b --- /dev/null +++ b/Release/makefile @@ -0,0 +1,115 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +-include ../makefile.init + +RM := rm -rf + +# All of the sources participating in the build are defined here +-include sources.mk +-include USB_HOST/Target/subdir.mk +-include USB_HOST/App/subdir.mk +-include Middlewares/ST/STM32_USB_Host_Library/Core/Src/subdir.mk +-include Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Src/subdir.mk +-include Drivers/STM32F4xx_HAL_Driver/Src/subdir.mk +-include Drivers/LSM303DLHC/subdir.mk +-include Drivers/COMPASS_LEDS/subdir.mk +-include Core/Startup/subdir.mk +-include Core/Src/subdir.mk +-include subdir.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(CC_DEPS)),) +-include $(CC_DEPS) +endif +ifneq ($(strip $(C++_DEPS)),) +-include $(C++_DEPS) +endif +ifneq ($(strip $(C_UPPER_DEPS)),) +-include $(C_UPPER_DEPS) +endif +ifneq ($(strip $(CXX_DEPS)),) +-include $(CXX_DEPS) +endif +ifneq ($(strip $(S_DEPS)),) +-include $(S_DEPS) +endif +ifneq ($(strip $(S_UPPER_DEPS)),) +-include $(S_UPPER_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +ifneq ($(strip $(CPP_DEPS)),) +-include $(CPP_DEPS) +endif +endif + +-include ../makefile.defs + +BUILD_ARTIFACT_NAME := eCompass +BUILD_ARTIFACT_EXTENSION := elf +BUILD_ARTIFACT_PREFIX := +BUILD_ARTIFACT := $(BUILD_ARTIFACT_PREFIX)$(BUILD_ARTIFACT_NAME).$(BUILD_ARTIFACT_EXTENSION) + +# Add inputs and outputs from these tool invocations to the build variables +EXECUTABLES += \ +eCompass.elf \ + +SIZE_OUTPUT += \ +default.size.stdout \ + +OBJDUMP_LIST += \ +eCompass.list \ + +OBJCOPY_BIN += \ +eCompass.bin \ + + +# All Target +all: main-build + +# Main-build Target +main-build: eCompass.elf secondary-outputs + +# Tool invocations +eCompass.elf: $(OBJS) $(USER_OBJS) D:\Users\Think\Programmation\STM32CUBEIDE\eCompass\STM32F401VCTX_FLASH.ld + arm-none-eabi-g++ -o "eCompass.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m4 -T"D:\Users\Think\Programmation\STM32CUBEIDE\eCompass\STM32F401VCTX_FLASH.ld" --specs=nosys.specs -Wl,-Map="eCompass.map" -Wl,--gc-sections -static --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -u _printf_float -u _scanf_float -Wl,--start-group -lc -lm -lstdc++ -lsupc++ -Wl,--end-group + @echo 'Finished building target: $@' + @echo ' ' + +default.size.stdout: $(EXECUTABLES) + arm-none-eabi-size $(EXECUTABLES) + @echo 'Finished building: $@' + @echo ' ' + +eCompass.list: $(EXECUTABLES) + arm-none-eabi-objdump -h -S $(EXECUTABLES) > "eCompass.list" + @echo 'Finished building: $@' + @echo ' ' + +eCompass.bin: $(EXECUTABLES) + arm-none-eabi-objcopy -O binary $(EXECUTABLES) "eCompass.bin" + @echo 'Finished building: $@' + @echo ' ' + +# Other Targets +clean: + -$(RM) * + -@echo ' ' + +secondary-outputs: $(SIZE_OUTPUT) $(OBJDUMP_LIST) $(OBJCOPY_BIN) + +fail-specified-linker-script-missing: + @echo 'Error: Cannot find the specified linker script. Check the linker settings in the build configuration.' + @exit 2 + +warn-no-linker-script-specified: + @echo 'Warning: No linker script specified. Check the linker settings in the build configuration.' + +.PHONY: all clean dependents fail-specified-linker-script-missing warn-no-linker-script-specified +.SECONDARY: + +-include ../makefile.targets diff --git a/Release/objects.list b/Release/objects.list new file mode 100644 index 0000000..14bd046 --- /dev/null +++ b/Release/objects.list @@ -0,0 +1,41 @@ +"Core/Src/app.o" +"Core/Src/main.o" +"Core/Src/stm32f4xx_hal_msp.o" +"Core/Src/stm32f4xx_it.o" +"Core/Src/syscalls.o" +"Core/Src/sysmem.o" +"Core/Src/system_stm32f4xx.o" +"Core/Startup/startup_stm32f401vctx.o" +"Drivers/COMPASS_LEDS/COMPASS_LEDS.o" +"Drivers/LSM303DLHC/LSM303DLHC.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.o" +"Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Src/usbh_cdc.o" +"Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_core.o" +"Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ctlreq.o" +"Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ioreq.o" +"Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_pipes.o" +"USB_HOST/App/usb_host.o" +"USB_HOST/Target/usbh_conf.o" +"USB_HOST/Target/usbh_platform.o" diff --git a/Release/objects.mk b/Release/objects.mk new file mode 100644 index 0000000..742c2da --- /dev/null +++ b/Release/objects.mk @@ -0,0 +1,8 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +USER_OBJS := + +LIBS := + diff --git a/Release/sources.mk b/Release/sources.mk new file mode 100644 index 0000000..66f231b --- /dev/null +++ b/Release/sources.mk @@ -0,0 +1,41 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +ELF_SRCS := +C_UPPER_SRCS := +CXX_SRCS := +C++_SRCS := +OBJ_SRCS := +S_SRCS := +CC_SRCS := +C_SRCS := +CPP_SRCS := +S_UPPER_SRCS := +O_SRCS := +OBJDUMP_LIST := +C_UPPER_DEPS := +S_DEPS := +C_DEPS := +OBJCOPY_BIN := +CC_DEPS := +SIZE_OUTPUT := +C++_DEPS := +EXECUTABLES := +OBJS := +CXX_DEPS := +S_UPPER_DEPS := +CPP_DEPS := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +Core/Src \ +Core/Startup \ +Drivers/COMPASS_LEDS \ +Drivers/LSM303DLHC \ +Drivers/STM32F4xx_HAL_Driver/Src \ +Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Src \ +Middlewares/ST/STM32_USB_Host_Library/Core/Src \ +USB_HOST/App \ +USB_HOST/Target \ + diff --git a/STM32F401VCTX_FLASH.ld b/STM32F401VCTX_FLASH.ld new file mode 100644 index 0000000..324d260 --- /dev/null +++ b/STM32F401VCTX_FLASH.ld @@ -0,0 +1,177 @@ +/** + ****************************************************************************** + * @file LinkerScript.ld + * @author Auto-generated by STM32CubeIDE + * Abstract : Linker script for STM32F401C-DISCO Board embedding STM32F401VCTx Device from stm32f4 series + * 256Kbytes FLASH + * 64Kbytes RAM + * + * Set heap size, stack size and stack location according + * to application requirements. + * + * Set memory bank area and size if external memory is used + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200 ; /* required amount of heap */ +_Min_Stack_Size = 0x400 ; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K + FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 256K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM : { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/Test Debug.launch b/Test Debug.launch new file mode 100644 index 0000000..3977792 --- /dev/null +++ b/Test Debug.launch @@ -0,0 +1,73 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/USB_HOST/App/usb_host.c b/USB_HOST/App/usb_host.c new file mode 100644 index 0000000..6982f08 --- /dev/null +++ b/USB_HOST/App/usb_host.c @@ -0,0 +1,138 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : usb_host.c + * @version : v1.0_Cube + * @brief : This file implements the USB Host + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ + +#include "usb_host.h" +#include "usbh_core.h" +#include "usbh_cdc.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* USER CODE BEGIN PV */ +/* Private variables ---------------------------------------------------------*/ + +/* USER CODE END PV */ + +/* USER CODE BEGIN PFP */ +/* Private function prototypes -----------------------------------------------*/ + +/* USER CODE END PFP */ + +/* USB Host core handle declaration */ +USBH_HandleTypeDef hUsbHostFS; +ApplicationTypeDef Appli_state = APPLICATION_IDLE; + +/* + * -- Insert your variables declaration here -- + */ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* + * user callback declaration + */ +static void USBH_UserProcess(USBH_HandleTypeDef *phost, uint8_t id); + +/* + * -- Insert your external function declaration here -- + */ +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/** + * Init USB host library, add supported class and start the library + * @retval None + */ +void MX_USB_HOST_Init(void) +{ + /* USER CODE BEGIN USB_HOST_Init_PreTreatment */ + + /* USER CODE END USB_HOST_Init_PreTreatment */ + + /* Init host Library, add supported class and start the library. */ + if (USBH_Init(&hUsbHostFS, USBH_UserProcess, HOST_FS) != USBH_OK) + { + Error_Handler(); + } + if (USBH_RegisterClass(&hUsbHostFS, USBH_CDC_CLASS) != USBH_OK) + { + Error_Handler(); + } + if (USBH_Start(&hUsbHostFS) != USBH_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USB_HOST_Init_PostTreatment */ + + /* USER CODE END USB_HOST_Init_PostTreatment */ +} + +/* + * Background task + */ +void MX_USB_HOST_Process(void) +{ + /* USB Host Background task */ + USBH_Process(&hUsbHostFS); +} +/* + * user callback definition + */ +static void USBH_UserProcess (USBH_HandleTypeDef *phost, uint8_t id) +{ + /* USER CODE BEGIN CALL_BACK_1 */ + switch(id) + { + case HOST_USER_SELECT_CONFIGURATION: + break; + + case HOST_USER_DISCONNECTION: + Appli_state = APPLICATION_DISCONNECT; + break; + + case HOST_USER_CLASS_ACTIVE: + Appli_state = APPLICATION_READY; + break; + + case HOST_USER_CONNECTION: + Appli_state = APPLICATION_START; + break; + + default: + break; + } + /* USER CODE END CALL_BACK_1 */ +} + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/USB_HOST/App/usb_host.h b/USB_HOST/App/usb_host.h new file mode 100644 index 0000000..bbb2da1 --- /dev/null +++ b/USB_HOST/App/usb_host.h @@ -0,0 +1,94 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : usb_host.h + * @version : v1.0_Cube + * @brief : Header for usb_host.c file. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USB_HOST__H__ +#define __USB_HOST__H__ + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" +#include "stm32f4xx_hal.h" + +/* USER CODE BEGIN INCLUDE */ + +/* USER CODE END INCLUDE */ + +/** @addtogroup USBH_OTG_DRIVER + * @{ + */ + +/** @defgroup USBH_HOST USBH_HOST + * @brief Host file for Usb otg low level driver. + * @{ + */ + +/** @defgroup USBH_HOST_Exported_Variables USBH_HOST_Exported_Variables + * @brief Public variables. + * @{ + */ + +/** + * @} + */ + +/** Status of the application. */ +typedef enum { + APPLICATION_IDLE = 0, + APPLICATION_START, + APPLICATION_READY, + APPLICATION_DISCONNECT +}ApplicationTypeDef; + +/** @defgroup USBH_HOST_Exported_FunctionsPrototype USBH_HOST_Exported_FunctionsPrototype + * @brief Declaration of public functions for Usb host. + * @{ + */ + +/* Exported functions -------------------------------------------------------*/ + +/** @brief USB Host initialization function. */ +void MX_USB_HOST_Init(void); + +void MX_USB_HOST_Process(void); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_HOST__H__ */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/USB_HOST/Target/usbh_conf.c b/USB_HOST/Target/usbh_conf.c new file mode 100644 index 0000000..f69c230 --- /dev/null +++ b/USB_HOST/Target/usbh_conf.c @@ -0,0 +1,550 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : Target/usbh_conf.c + * @version : v1.0_Cube + * @brief : This file implements the board support package for the USB host library + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbh_core.h" +#include "usbh_platform.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ + +/* USER CODE BEGIN PV */ +/* Private variables ---------------------------------------------------------*/ + +/* USER CODE END PV */ + +HCD_HandleTypeDef hhcd_USB_OTG_FS; +void Error_Handler(void); + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* USER CODE BEGIN PFP */ +/* Private function prototypes -----------------------------------------------*/ +USBH_StatusTypeDef USBH_Get_USB_Status(HAL_StatusTypeDef hal_status); + +/* USER CODE END PFP */ + +/* Private functions ---------------------------------------------------------*/ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/******************************************************************************* + LL Driver Callbacks (HCD -> USB Host Library) +*******************************************************************************/ +/* MSP Init */ + +void HAL_HCD_MspInit(HCD_HandleTypeDef* hcdHandle) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hcdHandle->Instance==USB_OTG_FS) + { + /* USER CODE BEGIN USB_OTG_FS_MspInit 0 */ + + /* USER CODE END USB_OTG_FS_MspInit 0 */ + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**USB_OTG_FS GPIO Configuration + PA9 ------> USB_OTG_FS_VBUS + PA10 ------> USB_OTG_FS_ID + PA11 ------> USB_OTG_FS_DM + PA12 ------> USB_OTG_FS_DP + */ + GPIO_InitStruct.Pin = VBUS_FS_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(VBUS_FS_GPIO_Port, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = OTG_FS_ID_Pin|OTG_FS_DM_Pin|OTG_FS_DP_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* Peripheral clock enable */ + __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); + + /* Peripheral interrupt init */ + HAL_NVIC_SetPriority(OTG_FS_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(OTG_FS_IRQn); + /* USER CODE BEGIN USB_OTG_FS_MspInit 1 */ + + /* USER CODE END USB_OTG_FS_MspInit 1 */ + } +} + +void HAL_HCD_MspDeInit(HCD_HandleTypeDef* hcdHandle) +{ + if(hcdHandle->Instance==USB_OTG_FS) + { + /* USER CODE BEGIN USB_OTG_FS_MspDeInit 0 */ + + /* USER CODE END USB_OTG_FS_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USB_OTG_FS_CLK_DISABLE(); + + /**USB_OTG_FS GPIO Configuration + PA9 ------> USB_OTG_FS_VBUS + PA10 ------> USB_OTG_FS_ID + PA11 ------> USB_OTG_FS_DM + PA12 ------> USB_OTG_FS_DP + */ + HAL_GPIO_DeInit(GPIOA, VBUS_FS_Pin|OTG_FS_ID_Pin|OTG_FS_DM_Pin|OTG_FS_DP_Pin); + + /* Peripheral interrupt Deinit*/ + HAL_NVIC_DisableIRQ(OTG_FS_IRQn); + + /* USER CODE BEGIN USB_OTG_FS_MspDeInit 1 */ + + /* USER CODE END USB_OTG_FS_MspDeInit 1 */ + } +} + +/** + * @brief SOF callback. + * @param hhcd: HCD handle + * @retval None + */ +void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd) +{ + USBH_LL_IncTimer(hhcd->pData); +} + +/** + * @brief SOF callback. + * @param hhcd: HCD handle + * @retval None + */ +void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd) +{ + USBH_LL_Connect(hhcd->pData); +} + +/** + * @brief SOF callback. + * @param hhcd: HCD handle + * @retval None + */ +void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd) +{ + USBH_LL_Disconnect(hhcd->pData); +} + +/** + * @brief Notify URB state change callback. + * @param hhcd: HCD handle + * @param chnum: channel number + * @param urb_state: state + * @retval None + */ +void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state) +{ + /* To be used with OS to sync URB state with the global state machine */ +#if (USBH_USE_OS == 1) + USBH_LL_NotifyURBChange(hhcd->pData); +#endif +} +/** +* @brief Port Port Enabled callback. + * @param hhcd: HCD handle + * @retval None + */ +void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd) +{ + USBH_LL_PortEnabled(hhcd->pData); +} + +/** + * @brief Port Port Disabled callback. + * @param hhcd: HCD handle + * @retval None + */ +void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd) +{ + USBH_LL_PortDisabled(hhcd->pData); +} + +/******************************************************************************* + LL Driver Interface (USB Host Library --> HCD) +*******************************************************************************/ + +/** + * @brief Initialize the low level portion of the host driver. + * @param phost: Host handle + * @retval USBH status + */ +USBH_StatusTypeDef USBH_LL_Init(USBH_HandleTypeDef *phost) +{ + /* Init USB_IP */ + if (phost->id == HOST_FS) { + /* Link the driver to the stack. */ + hhcd_USB_OTG_FS.pData = phost; + phost->pData = &hhcd_USB_OTG_FS; + + hhcd_USB_OTG_FS.Instance = USB_OTG_FS; + hhcd_USB_OTG_FS.Init.Host_channels = 8; + hhcd_USB_OTG_FS.Init.speed = HCD_SPEED_FULL; + hhcd_USB_OTG_FS.Init.dma_enable = DISABLE; + hhcd_USB_OTG_FS.Init.phy_itface = HCD_PHY_EMBEDDED; + hhcd_USB_OTG_FS.Init.Sof_enable = DISABLE; + if (HAL_HCD_Init(&hhcd_USB_OTG_FS) != HAL_OK) + { + Error_Handler( ); + } + + USBH_LL_SetTimer(phost, HAL_HCD_GetCurrentFrame(&hhcd_USB_OTG_FS)); + } + return USBH_OK; +} + +/** + * @brief De-Initialize the low level portion of the host driver. + * @param phost: Host handle + * @retval USBH status + */ +USBH_StatusTypeDef USBH_LL_DeInit(USBH_HandleTypeDef *phost) +{ + HAL_StatusTypeDef hal_status = HAL_OK; + USBH_StatusTypeDef usb_status = USBH_OK; + + hal_status = HAL_HCD_DeInit(phost->pData); + + usb_status = USBH_Get_USB_Status(hal_status); + + return usb_status; +} + +/** + * @brief Start the low level portion of the host driver. + * @param phost: Host handle + * @retval USBH status + */ +USBH_StatusTypeDef USBH_LL_Start(USBH_HandleTypeDef *phost) +{ + HAL_StatusTypeDef hal_status = HAL_OK; + USBH_StatusTypeDef usb_status = USBH_OK; + + hal_status = HAL_HCD_Start(phost->pData); + + usb_status = USBH_Get_USB_Status(hal_status); + + return usb_status; +} + +/** + * @brief Stop the low level portion of the host driver. + * @param phost: Host handle + * @retval USBH status + */ +USBH_StatusTypeDef USBH_LL_Stop(USBH_HandleTypeDef *phost) +{ + HAL_StatusTypeDef hal_status = HAL_OK; + USBH_StatusTypeDef usb_status = USBH_OK; + + hal_status = HAL_HCD_Stop(phost->pData); + + usb_status = USBH_Get_USB_Status(hal_status); + + return usb_status; +} + +/** + * @brief Return the USB host speed from the low level driver. + * @param phost: Host handle + * @retval USBH speeds + */ +USBH_SpeedTypeDef USBH_LL_GetSpeed(USBH_HandleTypeDef *phost) +{ + USBH_SpeedTypeDef speed = USBH_SPEED_FULL; + + switch (HAL_HCD_GetCurrentSpeed(phost->pData)) + { + case 0 : + speed = USBH_SPEED_HIGH; + break; + + case 1 : + speed = USBH_SPEED_FULL; + break; + + case 2 : + speed = USBH_SPEED_LOW; + break; + + default: + speed = USBH_SPEED_FULL; + break; + } + return speed; +} + +/** + * @brief Reset the Host port of the low level driver. + * @param phost: Host handle + * @retval USBH status + */ +USBH_StatusTypeDef USBH_LL_ResetPort(USBH_HandleTypeDef *phost) +{ + HAL_StatusTypeDef hal_status = HAL_OK; + USBH_StatusTypeDef usb_status = USBH_OK; + + hal_status = HAL_HCD_ResetPort(phost->pData); + + usb_status = USBH_Get_USB_Status(hal_status); + + return usb_status; +} + +/** + * @brief Return the last transfered packet size. + * @param phost: Host handle + * @param pipe: Pipe index + * @retval Packet size + */ +uint32_t USBH_LL_GetLastXferSize(USBH_HandleTypeDef *phost, uint8_t pipe) +{ + return HAL_HCD_HC_GetXferCount(phost->pData, pipe); +} + +/** + * @brief Open a pipe of the low level driver. + * @param phost: Host handle + * @param pipe_num: Pipe index + * @param epnum: Endpoint number + * @param dev_address: Device USB address + * @param speed: Device Speed + * @param ep_type: Endpoint type + * @param mps: Endpoint max packet size + * @retval USBH status + */ +USBH_StatusTypeDef USBH_LL_OpenPipe(USBH_HandleTypeDef *phost, uint8_t pipe_num, uint8_t epnum, + uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps) +{ + HAL_StatusTypeDef hal_status = HAL_OK; + USBH_StatusTypeDef usb_status = USBH_OK; + + hal_status = HAL_HCD_HC_Init(phost->pData, pipe_num, epnum, + dev_address, speed, ep_type, mps); + + usb_status = USBH_Get_USB_Status(hal_status); + + return usb_status; +} + +/** + * @brief Close a pipe of the low level driver. + * @param phost: Host handle + * @param pipe: Pipe index + * @retval USBH status + */ +USBH_StatusTypeDef USBH_LL_ClosePipe(USBH_HandleTypeDef *phost, uint8_t pipe) +{ + HAL_StatusTypeDef hal_status = HAL_OK; + USBH_StatusTypeDef usb_status = USBH_OK; + + hal_status = HAL_HCD_HC_Halt(phost->pData, pipe); + + usb_status = USBH_Get_USB_Status(hal_status); + + return usb_status; +} + +/** + * @brief Submit a new URB to the low level driver. + * @param phost: Host handle + * @param pipe: Pipe index + * This parameter can be a value from 1 to 15 + * @param direction : Channel number + * This parameter can be one of the these values: + * 0 : Output + * 1 : Input + * @param ep_type : Endpoint Type + * This parameter can be one of the these values: + * @arg EP_TYPE_CTRL: Control type + * @arg EP_TYPE_ISOC: Isochrounous type + * @arg EP_TYPE_BULK: Bulk type + * @arg EP_TYPE_INTR: Interrupt type + * @param token : Endpoint Type + * This parameter can be one of the these values: + * @arg 0: PID_SETUP + * @arg 1: PID_DATA + * @param pbuff : pointer to URB data + * @param length : Length of URB data + * @param do_ping : activate do ping protocol (for high speed only) + * This parameter can be one of the these values: + * 0 : do ping inactive + * 1 : do ping active + * @retval Status + */ +USBH_StatusTypeDef USBH_LL_SubmitURB(USBH_HandleTypeDef *phost, uint8_t pipe, uint8_t direction, + uint8_t ep_type, uint8_t token, uint8_t *pbuff, uint16_t length, + uint8_t do_ping) +{ + HAL_StatusTypeDef hal_status = HAL_OK; + USBH_StatusTypeDef usb_status = USBH_OK; + + hal_status = HAL_HCD_HC_SubmitRequest(phost->pData, pipe, direction , + ep_type, token, pbuff, length, + do_ping); + usb_status = USBH_Get_USB_Status(hal_status); + + return usb_status; +} + +/** + * @brief Get a URB state from the low level driver. + * @param phost: Host handle + * @param pipe: Pipe index + * This parameter can be a value from 1 to 15 + * @retval URB state + * This parameter can be one of the these values: + * @arg URB_IDLE + * @arg URB_DONE + * @arg URB_NOTREADY + * @arg URB_NYET + * @arg URB_ERROR + * @arg URB_STALL + */ +USBH_URBStateTypeDef USBH_LL_GetURBState(USBH_HandleTypeDef *phost, uint8_t pipe) +{ + return (USBH_URBStateTypeDef)HAL_HCD_HC_GetURBState (phost->pData, pipe); +} + +/** + * @brief Drive VBUS. + * @param phost: Host handle + * @param state : VBUS state + * This parameter can be one of the these values: + * 0 : VBUS Inactive + * 1 : VBUS Active + * @retval Status + */ +USBH_StatusTypeDef USBH_LL_DriverVBUS(USBH_HandleTypeDef *phost, uint8_t state) +{ + if (phost->id == HOST_FS) { + MX_DriverVbusFS(state); + } + + /* USER CODE BEGIN 0 */ + + /* USER CODE END 0*/ + + HAL_Delay(200); + return USBH_OK; +} + +/** + * @brief Set toggle for a pipe. + * @param phost: Host handle + * @param pipe: Pipe index + * @param toggle: toggle (0/1) + * @retval Status + */ +USBH_StatusTypeDef USBH_LL_SetToggle(USBH_HandleTypeDef *phost, uint8_t pipe, uint8_t toggle) +{ + HCD_HandleTypeDef *pHandle; + pHandle = phost->pData; + + if(pHandle->hc[pipe].ep_is_in) + { + pHandle->hc[pipe].toggle_in = toggle; + } + else + { + pHandle->hc[pipe].toggle_out = toggle; + } + + return USBH_OK; +} + +/** + * @brief Return the current toggle of a pipe. + * @param phost: Host handle + * @param pipe: Pipe index + * @retval toggle (0/1) + */ +uint8_t USBH_LL_GetToggle(USBH_HandleTypeDef *phost, uint8_t pipe) +{ + uint8_t toggle = 0; + HCD_HandleTypeDef *pHandle; + pHandle = phost->pData; + + if(pHandle->hc[pipe].ep_is_in) + { + toggle = pHandle->hc[pipe].toggle_in; + } + else + { + toggle = pHandle->hc[pipe].toggle_out; + } + return toggle; +} + +/** + * @brief Delay routine for the USB Host Library + * @param Delay: Delay in ms + * @retval None + */ +void USBH_Delay(uint32_t Delay) +{ + HAL_Delay(Delay); +} + +/** + * @brief Retuns the USB status depending on the HAL status: + * @param hal_status: HAL status + * @retval USB status + */ +USBH_StatusTypeDef USBH_Get_USB_Status(HAL_StatusTypeDef hal_status) +{ + USBH_StatusTypeDef usb_status = USBH_OK; + + switch (hal_status) + { + case HAL_OK : + usb_status = USBH_OK; + break; + case HAL_ERROR : + usb_status = USBH_FAIL; + break; + case HAL_BUSY : + usb_status = USBH_BUSY; + break; + case HAL_TIMEOUT : + usb_status = USBH_FAIL; + break; + default : + usb_status = USBH_FAIL; + break; + } + return usb_status; +} + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/USB_HOST/Target/usbh_conf.h b/USB_HOST/Target/usbh_conf.h new file mode 100644 index 0000000..67b4de4 --- /dev/null +++ b/USB_HOST/Target/usbh_conf.h @@ -0,0 +1,196 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : Target/usbh_conf.h + * @version : v1.0_Cube + * @brief : Header for usbh_conf.c file. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USBH_CONF__H__ +#define __USBH_CONF__H__ +#ifdef __cplusplus + extern "C" { +#endif +/* Includes ------------------------------------------------------------------*/ + +#include +#include +#include +#include "main.h" + +#include "stm32f4xx.h" +#include "stm32f4xx_hal.h" + +/* USER CODE BEGIN INCLUDE */ + +/* USER CODE END INCLUDE */ + +/** @addtogroup STM32_USB_HOST_LIBRARY + * @{ + */ + +/** @defgroup USBH_CONF + * @brief usb host low level driver configuration file + * @{ + */ + +/** @defgroup USBH_CONF_Exported_Variables USBH_CONF_Exported_Variables + * @brief Public variables. + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBH_CONF_Exported_Defines USBH_CONF_Exported_Defines + * @brief Defines for configuration of the Usb host. + * @{ + */ + +/*---------- -----------*/ +#define USBH_MAX_NUM_ENDPOINTS 2U + +/*---------- -----------*/ +#define USBH_MAX_NUM_INTERFACES 2U + +/*---------- -----------*/ +#define USBH_MAX_NUM_CONFIGURATION 1U + +/*---------- -----------*/ +#define USBH_KEEP_CFG_DESCRIPTOR 1U + +/*---------- -----------*/ +#define USBH_MAX_NUM_SUPPORTED_CLASS 1U + +/*---------- -----------*/ +#define USBH_MAX_SIZE_CONFIGURATION 256U + +/*---------- -----------*/ +#define USBH_MAX_DATA_BUFFER 512U + +/*---------- -----------*/ +#define USBH_DEBUG_LEVEL 0U + +/*---------- -----------*/ +#define USBH_USE_OS 0U + +/****************************************/ +/* #define for FS and HS identification */ +#define HOST_HS 0 +#define HOST_FS 1 + +#if (USBH_USE_OS == 1) + #include "cmsis_os.h" + #define USBH_PROCESS_PRIO osPriorityNormal + #define USBH_PROCESS_STACK_SIZE ((uint16_t)0) +#endif /* (USBH_USE_OS == 1) */ + +/** + * @} + */ + +/** @defgroup USBH_CONF_Exported_Macros USBH_CONF_Exported_Macros + * @brief Aliases. + * @{ + */ + +/* Memory management macros */ + +/** Alias for memory allocation. */ +#define USBH_malloc malloc + +/** Alias for memory release. */ +#define USBH_free free + +/** Alias for memory set. */ +#define USBH_memset memset + +/** Alias for memory copy. */ +#define USBH_memcpy memcpy + +/* DEBUG macros */ + +#if (USBH_DEBUG_LEVEL > 0U) +#define USBH_UsrLog(...) do { \ + printf(__VA_ARGS__); \ + printf("\n"); \ +} while (0) +#else +#define USBH_UsrLog(...) do {} while (0) +#endif + +#if (USBH_DEBUG_LEVEL > 1U) + +#define USBH_ErrLog(...) do { \ + printf("ERROR: ") ; \ + printf(__VA_ARGS__); \ + printf("\n"); \ +} while (0) +#else +#define USBH_ErrLog(...) do {} while (0) +#endif + +#if (USBH_DEBUG_LEVEL > 2U) +#define USBH_DbgLog(...) do { \ + printf("DEBUG : ") ; \ + printf(__VA_ARGS__); \ + printf("\n"); \ +} while (0) +#else +#define USBH_DbgLog(...) do {} while (0) +#endif + +/** + * @} + */ + +/** @defgroup USBH_CONF_Exported_Types USBH_CONF_Exported_Types + * @brief Types. + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBH_CONF_Exported_FunctionsPrototype USBH_CONF_Exported_FunctionsPrototype + * @brief Declaration of public functions for Usb host. + * @{ + */ + +/* Exported functions -------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USBH_CONF__H__ */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/USB_HOST/Target/usbh_platform.c b/USB_HOST/Target/usbh_platform.c new file mode 100644 index 0000000..9b8f8c7 --- /dev/null +++ b/USB_HOST/Target/usbh_platform.c @@ -0,0 +1,54 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : usbh_platform.c + + * @brief : This file implements the USB platform + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbh_platform.h" + +/* USER CODE BEGIN INCLUDE */ + +/* USER CODE END INCLUDE */ + +/** + * @brief Drive VBUS. + * @param state : VBUS state + * This parameter can be one of the these values: + * - 1 : VBUS Active + * - 0 : VBUS Inactive + */ +void MX_DriverVbusFS(uint8_t state) +{ + uint8_t data = state; + /* USER CODE BEGIN PREPARE_GPIO_DATA_VBUS_FS */ + if(state == 0) + { + /* Drive high Charge pump */ + data = GPIO_PIN_SET; + } + else + { + /* Drive low Charge pump */ + data = GPIO_PIN_RESET; + } + /* USER CODE END PREPARE_GPIO_DATA_VBUS_FS */ + HAL_GPIO_WritePin(GPIOC,GPIO_PIN_0,(GPIO_PinState)data); +} + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/USB_HOST/Target/usbh_platform.h b/USB_HOST/Target/usbh_platform.h new file mode 100644 index 0000000..e082140 --- /dev/null +++ b/USB_HOST/Target/usbh_platform.h @@ -0,0 +1,44 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : usbh_platform.h + * @brief : Header for usbh_platform.c file. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USBH_PLATFORM_H__ +#define __USBH_PLATFORM_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "usb_host.h" + +/* USER CODE BEGIN INCLUDE */ + +/* USER CODE END INCLUDE */ + +void MX_DriverVbusFS(uint8_t state); + +#ifdef __cplusplus +} +#endif + +#endif /* __USBH_PLATFORM_H__ */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/eCompass.ioc b/eCompass.ioc new file mode 100644 index 0000000..3400cd3 --- /dev/null +++ b/eCompass.ioc @@ -0,0 +1,381 @@ +#MicroXplorer Configuration settings - do not modify +File.Version=6 +I2S2.ErrorAudioFreq=0.0 % +I2S2.FullDuplexMode=I2S_FULLDUPLEXMODE_DISABLE +I2S2.IPParameters=RealAudioFreq,ErrorAudioFreq,Instance,VirtualMode,FullDuplexMode +I2S2.Instance=SPI$Index +I2S2.RealAudioFreq=8.0 KHz +I2S2.VirtualMode=I2S_MODE_MASTER +I2S3.AudioFreq=I2S_AUDIOFREQ_96K +I2S3.ErrorAudioFreq=-2.34 % +I2S3.FullDuplexMode=I2S_FULLDUPLEXMODE_DISABLE +I2S3.IPParameters=AudioFreq,RealAudioFreq,ErrorAudioFreq,Instance,VirtualMode,FullDuplexMode +I2S3.Instance=SPI$Index +I2S3.RealAudioFreq=93.75 KHz +I2S3.VirtualMode=I2S_MODE_MASTER +KeepUserPlacement=false +Mcu.Family=STM32F4 +Mcu.IP0=I2C1 +Mcu.IP1=I2S2 +Mcu.IP2=I2S3 +Mcu.IP3=NVIC +Mcu.IP4=RCC +Mcu.IP5=SPI1 +Mcu.IP6=SYS +Mcu.IP7=USART2 +Mcu.IP8=USB_HOST +Mcu.IP9=USB_OTG_FS +Mcu.IPNb=10 +Mcu.Name=STM32F401V(B-C)Tx +Mcu.Package=LQFP100 +Mcu.Pin0=PE2 +Mcu.Pin1=PE3 +Mcu.Pin10=PA0-WKUP +Mcu.Pin11=PA2 +Mcu.Pin12=PA3 +Mcu.Pin13=PA4 +Mcu.Pin14=PA5 +Mcu.Pin15=PA6 +Mcu.Pin16=PA7 +Mcu.Pin17=PB10 +Mcu.Pin18=PB12 +Mcu.Pin19=PD12 +Mcu.Pin2=PE4 +Mcu.Pin20=PD13 +Mcu.Pin21=PD14 +Mcu.Pin22=PD15 +Mcu.Pin23=PC7 +Mcu.Pin24=PA9 +Mcu.Pin25=PA10 +Mcu.Pin26=PA11 +Mcu.Pin27=PA12 +Mcu.Pin28=PA13 +Mcu.Pin29=PA14 +Mcu.Pin3=PE5 +Mcu.Pin30=PC10 +Mcu.Pin31=PC12 +Mcu.Pin32=PD4 +Mcu.Pin33=PD5 +Mcu.Pin34=PB3 +Mcu.Pin35=PB6 +Mcu.Pin36=PB9 +Mcu.Pin37=PE1 +Mcu.Pin38=VP_SYS_VS_Systick +Mcu.Pin39=VP_USB_HOST_VS_USB_HOST_CDC_FS +Mcu.Pin4=PC14-OSC32_IN +Mcu.Pin5=PC15-OSC32_OUT +Mcu.Pin6=PH0 - OSC_IN +Mcu.Pin7=PH1 - OSC_OUT +Mcu.Pin8=PC0 +Mcu.Pin9=PC3 +Mcu.PinsNb=40 +Mcu.ThirdPartyNb=0 +Mcu.UserConstants= +Mcu.UserName=STM32F401VCTx +MxCube.Version=6.1.1 +MxDb.Version=DB.6.0.10 +NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false +NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:true\:false +NVIC.ForceEnableDMAVector=true +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false +NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:true\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:true\:false +NVIC.OTG_FS_IRQn=true\:0\:0\:false\:false\:true\:true\:true +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false +NVIC.PriorityGroup=NVIC_PRIORITYGROUP_0 +NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false +NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true +NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false +PA0-WKUP.GPIOParameters=GPIO_Label,GPIO_ModeDefaultEXTI +PA0-WKUP.GPIO_Label=B1 [Blue PushButton] +PA0-WKUP.GPIO_ModeDefaultEXTI=GPIO_MODE_EVT_RISING +PA0-WKUP.Locked=true +PA0-WKUP.Signal=GPXTI0 +PA10.GPIOParameters=GPIO_Label +PA10.GPIO_Label=OTG_FS_ID +PA10.Locked=true +PA10.Signal=USB_OTG_FS_ID +PA11.GPIOParameters=GPIO_Label +PA11.GPIO_Label=OTG_FS_DM +PA11.Locked=true +PA11.Mode=Host_Only +PA11.Signal=USB_OTG_FS_DM +PA12.GPIOParameters=GPIO_Label +PA12.GPIO_Label=OTG_FS_DP +PA12.Locked=true +PA12.Mode=Host_Only +PA12.Signal=USB_OTG_FS_DP +PA13.GPIOParameters=GPIO_Label +PA13.GPIO_Label=SWDIO +PA13.Locked=true +PA13.Mode=Serial_Wire +PA13.Signal=SYS_JTMS-SWDIO +PA14.GPIOParameters=GPIO_Label +PA14.GPIO_Label=SWCLK +PA14.Locked=true +PA14.Mode=Serial_Wire +PA14.Signal=SYS_JTCK-SWCLK +PA2.Mode=Asynchronous +PA2.Signal=USART2_TX +PA3.Mode=Asynchronous +PA3.Signal=USART2_RX +PA4.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode +PA4.GPIO_Label=I2S3_WS [CS43L22_LRCK] +PA4.GPIO_Mode=GPIO_MODE_AF_PP +PA4.GPIO_PuPd=GPIO_NOPULL +PA4.GPIO_Speed=GPIO_SPEED_FREQ_LOW +PA4.Locked=true +PA4.Mode=Half_Duplex_Master +PA4.Signal=I2S3_WS +PA5.GPIOParameters=GPIO_Label +PA5.GPIO_Label=SPI1_SCK [L3GD20_SC/SPC] +PA5.Locked=true +PA5.Mode=Full_Duplex_Master +PA5.Signal=SPI1_SCK +PA6.GPIOParameters=GPIO_Label +PA6.GPIO_Label=SPI1_MISO [L3GD20_AS0/SDO] +PA6.Locked=true +PA6.Mode=Full_Duplex_Master +PA6.Signal=SPI1_MISO +PA7.GPIOParameters=GPIO_Label +PA7.GPIO_Label=SPI1_MISO [L3GD20_SDA/SDI/SDO] +PA7.Locked=true +PA7.Mode=Full_Duplex_Master +PA7.Signal=SPI1_MOSI +PA9.GPIOParameters=GPIO_Label +PA9.GPIO_Label=VBUS_FS +PA9.Locked=true +PA9.Mode=Activate_VBUS +PA9.Signal=USB_OTG_FS_VBUS +PB10.GPIOParameters=GPIO_Label +PB10.GPIO_Label=CLK_IN [MP45DT02_CLK] +PB10.Locked=true +PB10.Mode=Half_Duplex_Master +PB10.Signal=I2S2_CK +PB12.Locked=true +PB12.Mode=Half_Duplex_Master +PB12.Signal=I2S2_WS +PB3.GPIOParameters=GPIO_Label +PB3.GPIO_Label=SWO +PB3.Locked=true +PB3.Signal=SYS_JTDO-SWO +PB6.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode +PB6.GPIO_Label=Audio_SCL [CS43L22_SCL] +PB6.GPIO_Mode=GPIO_MODE_AF_OD +PB6.GPIO_PuPd=GPIO_NOPULL +PB6.GPIO_Speed=GPIO_SPEED_FREQ_LOW +PB6.Locked=true +PB6.Mode=I2C +PB6.Signal=I2C1_SCL +PB9.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode +PB9.GPIO_Label=Audio_SDA [CS43L22_SDA] +PB9.GPIO_Mode=GPIO_MODE_AF_OD +PB9.GPIO_PuPd=GPIO_NOPULL +PB9.GPIO_Speed=GPIO_SPEED_FREQ_LOW +PB9.Locked=true +PB9.Mode=I2C +PB9.Signal=I2C1_SDA +PC0.GPIOParameters=PinState,GPIO_Label +PC0.GPIO_Label=OTG_FS_PowerSwitchOn +PC0.Locked=true +PC0.PinState=GPIO_PIN_SET +PC0.Signal=GPIO_Output +PC10.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode +PC10.GPIO_Label=I2S3_SCK [CS43L22_SCLK] +PC10.GPIO_Mode=GPIO_MODE_AF_PP +PC10.GPIO_PuPd=GPIO_NOPULL +PC10.GPIO_Speed=GPIO_SPEED_FREQ_LOW +PC10.Locked=true +PC10.Mode=Half_Duplex_Master +PC10.Signal=I2S3_CK +PC12.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode +PC12.GPIO_Label=I2S3_SD [CS43L22_SDIN] +PC12.GPIO_Mode=GPIO_MODE_AF_PP +PC12.GPIO_PuPd=GPIO_NOPULL +PC12.GPIO_Speed=GPIO_SPEED_FREQ_LOW +PC12.Locked=true +PC12.Mode=Half_Duplex_Master +PC12.Signal=I2S3_SD +PC14-OSC32_IN.GPIOParameters=GPIO_Label +PC14-OSC32_IN.GPIO_Label=PC14-OSC32_IN +PC14-OSC32_IN.Locked=true +PC14-OSC32_IN.Mode=LSE-External-Oscillator +PC14-OSC32_IN.Signal=RCC_OSC32_IN +PC15-OSC32_OUT.GPIOParameters=GPIO_Label +PC15-OSC32_OUT.GPIO_Label=PC15-OSC32_OUT +PC15-OSC32_OUT.Locked=true +PC15-OSC32_OUT.Mode=LSE-External-Oscillator +PC15-OSC32_OUT.Signal=RCC_OSC32_OUT +PC3.GPIOParameters=GPIO_Label +PC3.GPIO_Label=PDM_OUT [MP45DT02_DOUT] +PC3.Locked=true +PC3.Mode=Half_Duplex_Master +PC3.Signal=I2S2_SD +PC7.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode +PC7.GPIO_Label=I2S3_MCK [CS43L22_MCLK] +PC7.GPIO_Mode=GPIO_MODE_AF_PP +PC7.GPIO_PuPd=GPIO_NOPULL +PC7.GPIO_Speed=GPIO_SPEED_FREQ_LOW +PC7.Locked=true +PC7.Mode=Master_Clock_Activated +PC7.Signal=I2S3_MCK +PD12.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label +PD12.GPIO_Label=LD4 [Green Led] +PD12.GPIO_PuPd=GPIO_NOPULL +PD12.GPIO_Speed=GPIO_SPEED_FREQ_LOW +PD12.Locked=true +PD12.Signal=GPIO_Output +PD13.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label +PD13.GPIO_Label=LD3 [Orange Led] +PD13.GPIO_PuPd=GPIO_NOPULL +PD13.GPIO_Speed=GPIO_SPEED_FREQ_LOW +PD13.Locked=true +PD13.Signal=GPIO_Output +PD14.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label +PD14.GPIO_Label=LD5 [Red Led] +PD14.GPIO_PuPd=GPIO_NOPULL +PD14.GPIO_Speed=GPIO_SPEED_FREQ_LOW +PD14.Locked=true +PD14.Signal=GPIO_Output +PD15.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label +PD15.GPIO_Label=LD6 [Blue Led] +PD15.GPIO_PuPd=GPIO_NOPULL +PD15.GPIO_Speed=GPIO_SPEED_FREQ_LOW +PD15.Locked=true +PD15.Signal=GPIO_Output +PD4.GPIOParameters=GPIO_Label +PD4.GPIO_Label=Audio_RST [CS43L22_RESET] +PD4.Locked=true +PD4.Signal=GPIO_Output +PD5.GPIOParameters=GPIO_Label +PD5.GPIO_Label=OTG_FS_OverCurrent +PD5.Locked=true +PD5.Signal=GPIO_Input +PE1.GPIOParameters=GPIO_Label,GPIO_ModeDefaultEXTI +PE1.GPIO_Label=MEMS_INT2 [L3GD20_INT2] +PE1.GPIO_ModeDefaultEXTI=GPIO_MODE_EVT_RISING +PE1.Locked=true +PE1.Signal=GPXTI1 +PE2.Locked=true +PE2.Signal=GPIO_Input +PE3.GPIOParameters=GPIO_Label +PE3.GPIO_Label=CS_I2C/SPI [L3GD20_CS_I2C/SPI] +PE3.Locked=true +PE3.Signal=GPIO_Output +PE4.GPIOParameters=GPIO_ModeDefaultEXTI +PE4.GPIO_ModeDefaultEXTI=GPIO_MODE_EVT_RISING +PE4.Locked=true +PE4.Signal=GPXTI4 +PE5.GPIOParameters=GPIO_ModeDefaultEXTI +PE5.GPIO_ModeDefaultEXTI=GPIO_MODE_EVT_RISING +PE5.Locked=true +PE5.Signal=GPXTI5 +PH0\ -\ OSC_IN.GPIOParameters=GPIO_Label +PH0\ -\ OSC_IN.GPIO_Label=PH0-OSC_IN +PH0\ -\ OSC_IN.Locked=true +PH0\ -\ OSC_IN.Mode=HSE-External-Oscillator +PH0\ -\ OSC_IN.Signal=RCC_OSC_IN +PH1\ -\ OSC_OUT.GPIOParameters=GPIO_Label +PH1\ -\ OSC_OUT.GPIO_Label=PH1-OSC_OUT +PH1\ -\ OSC_OUT.Locked=true +PH1\ -\ OSC_OUT.Mode=HSE-External-Oscillator +PH1\ -\ OSC_OUT.Signal=RCC_OSC_OUT +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=false +ProjectManager.CompilerOptimize=6 +ProjectManager.ComputerToolchain=false +ProjectManager.CoupleFile=false +ProjectManager.CustomerFirmwarePackage= +ProjectManager.DefaultFWLocation=true +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32F401VCTx +ProjectManager.FirmwarePackage=STM32Cube FW_F4 V1.25.2 +ProjectManager.FreePins=false +ProjectManager.HalAssertFull=false +ProjectManager.HeapSize=0x200 +ProjectManager.KeepUserCode=true +ProjectManager.LastFirmware=true +ProjectManager.LibraryCopy=1 +ProjectManager.MainLocation=Core/Src +ProjectManager.NoMain=false +ProjectManager.PreviousToolchain= +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=Test.ioc +ProjectManager.ProjectName=Test +ProjectManager.RegisterCallBack= +ProjectManager.StackSize=0x400 +ProjectManager.TargetToolchain=STM32CubeIDE +ProjectManager.ToolChainLocation= +ProjectManager.UnderRoot=true +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_I2C1_Init-I2C1-false-HAL-true,4-MX_I2S2_Init-I2S2-false-HAL-true,5-MX_I2S3_Init-I2S3-false-HAL-true,6-MX_SPI1_Init-SPI1-false-HAL-true,7-MX_USB_HOST_Init-USB_HOST-false-HAL-false +RCC.AHBFreq_Value=84000000 +RCC.APB1CLKDivider=RCC_HCLK_DIV2 +RCC.APB1Freq_Value=42000000 +RCC.APB1TimFreq_Value=84000000 +RCC.APB2Freq_Value=84000000 +RCC.APB2TimFreq_Value=84000000 +RCC.CortexFreq_Value=84000000 +RCC.FCLKCortexFreq_Value=84000000 +RCC.HCLKFreq_Value=84000000 +RCC.HSE_VALUE=8000000 +RCC.HSI_VALUE=16000000 +RCC.I2SClocksFreq_Value=96000000 +RCC.IPParameters=AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,FCLKCortexFreq_Value,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLM,PLLN,PLLP,PLLQ,PLLQCLKFreq_Value,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VcooutputI2S +RCC.LSI_VALUE=32000 +RCC.MCO2PinFreq_Value=84000000 +RCC.PLLCLKFreq_Value=84000000 +RCC.PLLM=8 +RCC.PLLN=336 +RCC.PLLP=RCC_PLLP_DIV4 +RCC.PLLQ=7 +RCC.PLLQCLKFreq_Value=48000000 +RCC.RTCFreq_Value=32000 +RCC.RTCHSEDivFreq_Value=4000000 +RCC.SYSCLKFreq_VALUE=84000000 +RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK +RCC.VCOI2SOutputFreq_Value=192000000 +RCC.VCOInputFreq_Value=1000000 +RCC.VCOOutputFreq_Value=336000000 +RCC.VcooutputI2S=96000000 +SH.GPXTI0.0=GPIO_EXTI0 +SH.GPXTI0.ConfNb=1 +SH.GPXTI1.0=GPIO_EXTI1 +SH.GPXTI1.ConfNb=1 +SH.GPXTI4.0=GPIO_EXTI4 +SH.GPXTI4.ConfNb=1 +SH.GPXTI5.0=GPIO_EXTI5 +SH.GPXTI5.ConfNb=1 +SPI1.CalculateBaudRate=42.0 MBits/s +SPI1.Direction=SPI_DIRECTION_2LINES +SPI1.IPParameters=Mode,CalculateBaudRate,VirtualType,Direction +SPI1.Mode=SPI_MODE_MASTER +SPI1.VirtualType=VM_MASTER +USART2.IPParameters=VirtualMode +USART2.VirtualMode=VM_ASYNC +USB_HOST.BSP.number=1 +USB_HOST.IPParameters=VirtualModeFS,USBH_HandleTypeDef +USB_HOST.USBH_HandleTypeDef=hUsbHostFS +USB_HOST.VirtualModeFS=Cdc +USB_HOST0.BSP.STBoard=false +USB_HOST0.BSP.api=Unknown +USB_HOST0.BSP.component= +USB_HOST0.BSP.condition= +USB_HOST0.BSP.i2caddr=0 +USB_HOST0.BSP.i2creg=0 +USB_HOST0.BSP.instance=PC0 +USB_HOST0.BSP.ip=GPIO +USB_HOST0.BSP.mode=Output +USB_HOST0.BSP.name=Drive_VBUS_FS +USB_HOST0.BSP.semaphore= +USB_HOST0.BSP.solution=PC0 +USB_OTG_FS.IPParameters=phy_itface,VirtualMode +USB_OTG_FS.VirtualMode=Host_Only +USB_OTG_FS.phy_itface=HCD_PHY_EMBEDDED +VP_SYS_VS_Systick.Mode=SysTick +VP_SYS_VS_Systick.Signal=SYS_VS_Systick +VP_USB_HOST_VS_USB_HOST_CDC_FS.Mode=CDC_FS +VP_USB_HOST_VS_USB_HOST_CDC_FS.Signal=USB_HOST_VS_USB_HOST_CDC_FS +board=STM32F401C-DISCO +boardIOC=true +isbadioc=false diff --git a/eCompass.launch b/eCompass.launch new file mode 100644 index 0000000..58ac99e --- /dev/null +++ b/eCompass.launch @@ -0,0 +1,72 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +