Th3maz1ng/W800_Smart_Watch
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Added RTC osc calibration function : tls_pmu_32k_calibrate to try help mitigate internal RTC time drift when using the 32K OSC (while MCU sleeps)

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This commit is contained in:
anschrammh 2024-08-01 01:36:24 +02:00
parent b4c8c8c05a
commit 4919b17c3c
3 changed files with 34 additions and 4 deletions
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8
src/W800_SDK_v1.00.10/include/driver/wm_pmu.h
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@ -148,14 +148,14 @@ void tls_pmu_clk_select(u8 bypass);
/** NOT PART OF THE OFFICIAL SDK **/
/**
* @brief Starts the internal 32K oscillator calibration cycle.
* @brief Starts the internal 32K oscillator calibration cycle using the PMU's calibration circuit.
*
* @param None
* @param None
*
* @return None
* @return true if successful, false otherwise
*
*/
void tls_pmu_clk_calibrate(void);
bool tls_pmu_32k_calibrate(void);
/**********************************/

28
src/W800_SDK_v1.00.10/platform/drivers/pmu/wm_pmu.c
View File

@ -188,6 +188,34 @@ void tls_pmu_clk_select(u8 bypass)
tls_reg_write32(HR_PMU_PS_CR, val);
}
/** NOT PART OF THE OFFICIAL SDK **/
bool tls_pmu_32k_calibrate(void)
{
/* To start the calibration procedure, the bit 3 needs to be set to 0 and then to 1 */
unsigned int pmu_ps_cr = tls_reg_read32(HR_PMU_PS_CR);
/* First make sure the bit 3 is 0 */
if((pmu_ps_cr & BIT(3)) != 0)
{
pmu_ps_cr &= ~(BIT(3));
tls_reg_write32(HR_PMU_PS_CR, pmu_ps_cr);
}
pmu_ps_cr = tls_reg_read32(HR_PMU_PS_CR);
if((pmu_ps_cr & BIT(3)) == 0)
{
/* Then flip it to one */
pmu_ps_cr |= BIT(3);
tls_reg_write32(HR_PMU_PS_CR, pmu_ps_cr);
}
else
{
return false;
}
return true;
}
/**********************************/
/**
* @brief This function is used to start pmu timer0

2
src/W800_SDK_v1.00.10/platform/drivers/rtc/wm_rtc.c
View File

@ -84,12 +84,14 @@ void tls_get_rtc(struct tm *tblock)
tblock->tm_sec = ctrl1 & 0x0000003f;
}
/** NOT PART OF THE OFFICIAL SDK **/
bool tls_is_rtc_running(void)
{
int ctrl2 = tls_reg_read32(HR_PMU_RTC_CTRL2);
return ctrl2 & (1 << 16) ? true : false;
}
/**********************************/
void PMU_RTC_IRQHandler(void)
{